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TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/comp_dmac.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for DMAC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_DMAC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_DMAC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR DMAC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_DMAC Direct Memory Access Controller */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define DMAC_U2223
AnnaBridge 171:3a7713b1edbc 54 #define REV_DMAC 0x100
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
AnnaBridge 171:3a7713b1edbc 62 uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
AnnaBridge 171:3a7713b1edbc 63 uint16_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 64 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
AnnaBridge 171:3a7713b1edbc 65 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
AnnaBridge 171:3a7713b1edbc 66 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
AnnaBridge 171:3a7713b1edbc 67 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
AnnaBridge 171:3a7713b1edbc 68 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 69 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 70 struct {
AnnaBridge 171:3a7713b1edbc 71 uint16_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 72 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
AnnaBridge 171:3a7713b1edbc 73 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 74 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 75 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 76 } DMAC_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 80 #define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 83 #define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 84 #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
AnnaBridge 171:3a7713b1edbc 85 #define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 86 #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
AnnaBridge 171:3a7713b1edbc 87 #define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 88 #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
AnnaBridge 171:3a7713b1edbc 89 #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
AnnaBridge 171:3a7713b1edbc 91 #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
AnnaBridge 171:3a7713b1edbc 92 #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
AnnaBridge 171:3a7713b1edbc 93 #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
AnnaBridge 171:3a7713b1edbc 94 #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
AnnaBridge 171:3a7713b1edbc 95 #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
AnnaBridge 171:3a7713b1edbc 96 #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
AnnaBridge 171:3a7713b1edbc 97 #define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
AnnaBridge 171:3a7713b1edbc 98 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
AnnaBridge 171:3a7713b1edbc 99 #define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
AnnaBridge 171:3a7713b1edbc 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 103 typedef union {
AnnaBridge 171:3a7713b1edbc 104 struct {
AnnaBridge 171:3a7713b1edbc 105 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
AnnaBridge 171:3a7713b1edbc 106 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
AnnaBridge 171:3a7713b1edbc 107 uint16_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 108 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
AnnaBridge 171:3a7713b1edbc 109 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 110 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 111 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 112 } DMAC_CRCCTRL_Type;
AnnaBridge 171:3a7713b1edbc 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
AnnaBridge 171:3a7713b1edbc 116 #define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
AnnaBridge 171:3a7713b1edbc 119 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
AnnaBridge 171:3a7713b1edbc 121 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 122 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 123 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 124 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 126 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 127 #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
AnnaBridge 171:3a7713b1edbc 128 #define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
AnnaBridge 171:3a7713b1edbc 129 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
AnnaBridge 171:3a7713b1edbc 130 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
AnnaBridge 171:3a7713b1edbc 131 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
AnnaBridge 171:3a7713b1edbc 132 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
AnnaBridge 171:3a7713b1edbc 133 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
AnnaBridge 171:3a7713b1edbc 134 #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
AnnaBridge 171:3a7713b1edbc 135 #define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
AnnaBridge 171:3a7713b1edbc 136 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
AnnaBridge 171:3a7713b1edbc 137 #define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
AnnaBridge 171:3a7713b1edbc 138 #define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
AnnaBridge 171:3a7713b1edbc 139 #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
AnnaBridge 171:3a7713b1edbc 140 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
AnnaBridge 171:3a7713b1edbc 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 145 typedef union {
AnnaBridge 171:3a7713b1edbc 146 struct {
AnnaBridge 171:3a7713b1edbc 147 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
AnnaBridge 171:3a7713b1edbc 148 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 149 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 150 } DMAC_CRCDATAIN_Type;
AnnaBridge 171:3a7713b1edbc 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
AnnaBridge 171:3a7713b1edbc 154 #define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
AnnaBridge 171:3a7713b1edbc 157 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
AnnaBridge 171:3a7713b1edbc 158 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
AnnaBridge 171:3a7713b1edbc 159 #define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
AnnaBridge 171:3a7713b1edbc 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 163 typedef union {
AnnaBridge 171:3a7713b1edbc 164 struct {
AnnaBridge 171:3a7713b1edbc 165 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
AnnaBridge 171:3a7713b1edbc 166 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 167 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 168 } DMAC_CRCCHKSUM_Type;
AnnaBridge 171:3a7713b1edbc 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
AnnaBridge 171:3a7713b1edbc 172 #define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
AnnaBridge 171:3a7713b1edbc 175 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
AnnaBridge 171:3a7713b1edbc 176 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
AnnaBridge 171:3a7713b1edbc 177 #define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
AnnaBridge 171:3a7713b1edbc 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 181 typedef union {
AnnaBridge 171:3a7713b1edbc 182 struct {
AnnaBridge 171:3a7713b1edbc 183 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
AnnaBridge 171:3a7713b1edbc 184 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
AnnaBridge 171:3a7713b1edbc 185 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 186 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 187 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 188 } DMAC_CRCSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
AnnaBridge 171:3a7713b1edbc 192 #define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
AnnaBridge 171:3a7713b1edbc 195 #define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 196 #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
AnnaBridge 171:3a7713b1edbc 197 #define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
AnnaBridge 171:3a7713b1edbc 198 #define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 202 typedef union {
AnnaBridge 171:3a7713b1edbc 203 struct {
AnnaBridge 171:3a7713b1edbc 204 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
AnnaBridge 171:3a7713b1edbc 205 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 206 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 207 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 208 } DMAC_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
AnnaBridge 171:3a7713b1edbc 212 #define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
AnnaBridge 171:3a7713b1edbc 215 #define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
AnnaBridge 171:3a7713b1edbc 216 #define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
AnnaBridge 171:3a7713b1edbc 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 220 typedef union {
AnnaBridge 171:3a7713b1edbc 221 struct {
AnnaBridge 171:3a7713b1edbc 222 uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
AnnaBridge 171:3a7713b1edbc 223 uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
AnnaBridge 171:3a7713b1edbc 224 uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
AnnaBridge 171:3a7713b1edbc 225 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 226 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 227 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 228 } DMAC_QOSCTRL_Type;
AnnaBridge 171:3a7713b1edbc 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 #define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
AnnaBridge 171:3a7713b1edbc 232 #define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 #define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
AnnaBridge 171:3a7713b1edbc 235 #define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
AnnaBridge 171:3a7713b1edbc 236 #define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
AnnaBridge 171:3a7713b1edbc 237 #define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
AnnaBridge 171:3a7713b1edbc 238 #define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
AnnaBridge 171:3a7713b1edbc 239 #define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
AnnaBridge 171:3a7713b1edbc 240 #define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
AnnaBridge 171:3a7713b1edbc 241 #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
AnnaBridge 171:3a7713b1edbc 242 #define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
AnnaBridge 171:3a7713b1edbc 243 #define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
AnnaBridge 171:3a7713b1edbc 244 #define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
AnnaBridge 171:3a7713b1edbc 245 #define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
AnnaBridge 171:3a7713b1edbc 246 #define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
AnnaBridge 171:3a7713b1edbc 247 #define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
AnnaBridge 171:3a7713b1edbc 248 #define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
AnnaBridge 171:3a7713b1edbc 249 #define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
AnnaBridge 171:3a7713b1edbc 250 #define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
AnnaBridge 171:3a7713b1edbc 251 #define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
AnnaBridge 171:3a7713b1edbc 252 #define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
AnnaBridge 171:3a7713b1edbc 253 #define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
AnnaBridge 171:3a7713b1edbc 254 #define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
AnnaBridge 171:3a7713b1edbc 255 #define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
AnnaBridge 171:3a7713b1edbc 256 #define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
AnnaBridge 171:3a7713b1edbc 257 #define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
AnnaBridge 171:3a7713b1edbc 258 #define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
AnnaBridge 171:3a7713b1edbc 259 #define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
AnnaBridge 171:3a7713b1edbc 260 #define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
AnnaBridge 171:3a7713b1edbc 261 #define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
AnnaBridge 171:3a7713b1edbc 262 #define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
AnnaBridge 171:3a7713b1edbc 263 #define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
AnnaBridge 171:3a7713b1edbc 264 #define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
AnnaBridge 171:3a7713b1edbc 265 #define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
AnnaBridge 171:3a7713b1edbc 266 #define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
AnnaBridge 171:3a7713b1edbc 267 #define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
AnnaBridge 171:3a7713b1edbc 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 271 typedef union {
AnnaBridge 171:3a7713b1edbc 272 struct {
AnnaBridge 171:3a7713b1edbc 273 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
AnnaBridge 171:3a7713b1edbc 274 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
AnnaBridge 171:3a7713b1edbc 275 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
AnnaBridge 171:3a7713b1edbc 276 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
AnnaBridge 171:3a7713b1edbc 277 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
AnnaBridge 171:3a7713b1edbc 278 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
AnnaBridge 171:3a7713b1edbc 279 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
AnnaBridge 171:3a7713b1edbc 280 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
AnnaBridge 171:3a7713b1edbc 281 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
AnnaBridge 171:3a7713b1edbc 282 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
AnnaBridge 171:3a7713b1edbc 283 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
AnnaBridge 171:3a7713b1edbc 284 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
AnnaBridge 171:3a7713b1edbc 285 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 286 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 287 struct {
AnnaBridge 171:3a7713b1edbc 288 uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
AnnaBridge 171:3a7713b1edbc 289 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 290 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 291 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 292 } DMAC_SWTRIGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
AnnaBridge 171:3a7713b1edbc 296 #define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
AnnaBridge 171:3a7713b1edbc 299 #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
AnnaBridge 171:3a7713b1edbc 300 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
AnnaBridge 171:3a7713b1edbc 301 #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
AnnaBridge 171:3a7713b1edbc 302 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
AnnaBridge 171:3a7713b1edbc 303 #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
AnnaBridge 171:3a7713b1edbc 305 #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
AnnaBridge 171:3a7713b1edbc 306 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
AnnaBridge 171:3a7713b1edbc 307 #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
AnnaBridge 171:3a7713b1edbc 309 #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
AnnaBridge 171:3a7713b1edbc 310 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
AnnaBridge 171:3a7713b1edbc 311 #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
AnnaBridge 171:3a7713b1edbc 312 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
AnnaBridge 171:3a7713b1edbc 313 #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
AnnaBridge 171:3a7713b1edbc 314 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
AnnaBridge 171:3a7713b1edbc 315 #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
AnnaBridge 171:3a7713b1edbc 316 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
AnnaBridge 171:3a7713b1edbc 317 #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
AnnaBridge 171:3a7713b1edbc 318 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
AnnaBridge 171:3a7713b1edbc 319 #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
AnnaBridge 171:3a7713b1edbc 320 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
AnnaBridge 171:3a7713b1edbc 321 #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
AnnaBridge 171:3a7713b1edbc 322 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
AnnaBridge 171:3a7713b1edbc 323 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
AnnaBridge 171:3a7713b1edbc 324 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
AnnaBridge 171:3a7713b1edbc 325 #define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
AnnaBridge 171:3a7713b1edbc 328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 329 typedef union {
AnnaBridge 171:3a7713b1edbc 330 struct {
AnnaBridge 171:3a7713b1edbc 331 uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 332 uint32_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 333 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 334 uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 335 uint32_t :3; /*!< bit: 12..14 Reserved */
AnnaBridge 171:3a7713b1edbc 336 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 337 uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 338 uint32_t :3; /*!< bit: 20..22 Reserved */
AnnaBridge 171:3a7713b1edbc 339 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 340 uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 341 uint32_t :3; /*!< bit: 28..30 Reserved */
AnnaBridge 171:3a7713b1edbc 342 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 343 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 344 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 345 } DMAC_PRICTRL0_Type;
AnnaBridge 171:3a7713b1edbc 346 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
AnnaBridge 171:3a7713b1edbc 349 #define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 352 #define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
AnnaBridge 171:3a7713b1edbc 353 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
AnnaBridge 171:3a7713b1edbc 354 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 355 #define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
AnnaBridge 171:3a7713b1edbc 356 #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 357 #define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
AnnaBridge 171:3a7713b1edbc 358 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
AnnaBridge 171:3a7713b1edbc 359 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 360 #define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
AnnaBridge 171:3a7713b1edbc 361 #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 362 #define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
AnnaBridge 171:3a7713b1edbc 363 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
AnnaBridge 171:3a7713b1edbc 364 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 365 #define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
AnnaBridge 171:3a7713b1edbc 366 #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
AnnaBridge 171:3a7713b1edbc 367 #define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
AnnaBridge 171:3a7713b1edbc 368 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
AnnaBridge 171:3a7713b1edbc 369 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
AnnaBridge 171:3a7713b1edbc 370 #define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
AnnaBridge 171:3a7713b1edbc 371 #define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
AnnaBridge 171:3a7713b1edbc 372
AnnaBridge 171:3a7713b1edbc 373 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
AnnaBridge 171:3a7713b1edbc 374 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 375 typedef union {
AnnaBridge 171:3a7713b1edbc 376 struct {
AnnaBridge 171:3a7713b1edbc 377 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
AnnaBridge 171:3a7713b1edbc 378 uint16_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 379 uint16_t TERR:1; /*!< bit: 8 Transfer Error */
AnnaBridge 171:3a7713b1edbc 380 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 381 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
AnnaBridge 171:3a7713b1edbc 382 uint16_t :2; /*!< bit: 11..12 Reserved */
AnnaBridge 171:3a7713b1edbc 383 uint16_t FERR:1; /*!< bit: 13 Fetch Error */
AnnaBridge 171:3a7713b1edbc 384 uint16_t BUSY:1; /*!< bit: 14 Busy */
AnnaBridge 171:3a7713b1edbc 385 uint16_t PEND:1; /*!< bit: 15 Pending */
AnnaBridge 171:3a7713b1edbc 386 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 387 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 388 } DMAC_INTPEND_Type;
AnnaBridge 171:3a7713b1edbc 389 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
AnnaBridge 171:3a7713b1edbc 392 #define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
AnnaBridge 171:3a7713b1edbc 395 #define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
AnnaBridge 171:3a7713b1edbc 396 #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
AnnaBridge 171:3a7713b1edbc 397 #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
AnnaBridge 171:3a7713b1edbc 398 #define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
AnnaBridge 171:3a7713b1edbc 399 #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
AnnaBridge 171:3a7713b1edbc 400 #define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos)
AnnaBridge 171:3a7713b1edbc 401 #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
AnnaBridge 171:3a7713b1edbc 402 #define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos)
AnnaBridge 171:3a7713b1edbc 403 #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
AnnaBridge 171:3a7713b1edbc 404 #define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos)
AnnaBridge 171:3a7713b1edbc 405 #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
AnnaBridge 171:3a7713b1edbc 406 #define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
AnnaBridge 171:3a7713b1edbc 407 #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
AnnaBridge 171:3a7713b1edbc 408 #define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
AnnaBridge 171:3a7713b1edbc 409 #define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
AnnaBridge 171:3a7713b1edbc 412 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 413 typedef union {
AnnaBridge 171:3a7713b1edbc 414 struct {
AnnaBridge 171:3a7713b1edbc 415 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 416 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 417 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 418 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 419 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 420 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 421 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 422 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 423 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 424 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 425 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 426 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 427 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 428 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 429 struct {
AnnaBridge 171:3a7713b1edbc 430 uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 431 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 432 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 433 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 434 } DMAC_INTSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
AnnaBridge 171:3a7713b1edbc 438 #define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 441 #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
AnnaBridge 171:3a7713b1edbc 442 #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 443 #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
AnnaBridge 171:3a7713b1edbc 444 #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 445 #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
AnnaBridge 171:3a7713b1edbc 446 #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 447 #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
AnnaBridge 171:3a7713b1edbc 448 #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 449 #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
AnnaBridge 171:3a7713b1edbc 450 #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 451 #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
AnnaBridge 171:3a7713b1edbc 452 #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 453 #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
AnnaBridge 171:3a7713b1edbc 454 #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 455 #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
AnnaBridge 171:3a7713b1edbc 456 #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 457 #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
AnnaBridge 171:3a7713b1edbc 458 #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 459 #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
AnnaBridge 171:3a7713b1edbc 460 #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 461 #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
AnnaBridge 171:3a7713b1edbc 462 #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 463 #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
AnnaBridge 171:3a7713b1edbc 464 #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
AnnaBridge 171:3a7713b1edbc 465 #define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
AnnaBridge 171:3a7713b1edbc 466 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
AnnaBridge 171:3a7713b1edbc 467 #define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
AnnaBridge 171:3a7713b1edbc 470 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 471 typedef union {
AnnaBridge 171:3a7713b1edbc 472 struct {
AnnaBridge 171:3a7713b1edbc 473 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
AnnaBridge 171:3a7713b1edbc 474 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
AnnaBridge 171:3a7713b1edbc 475 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
AnnaBridge 171:3a7713b1edbc 476 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
AnnaBridge 171:3a7713b1edbc 477 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
AnnaBridge 171:3a7713b1edbc 478 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
AnnaBridge 171:3a7713b1edbc 479 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
AnnaBridge 171:3a7713b1edbc 480 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
AnnaBridge 171:3a7713b1edbc 481 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
AnnaBridge 171:3a7713b1edbc 482 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
AnnaBridge 171:3a7713b1edbc 483 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
AnnaBridge 171:3a7713b1edbc 484 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
AnnaBridge 171:3a7713b1edbc 485 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 486 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 487 struct {
AnnaBridge 171:3a7713b1edbc 488 uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
AnnaBridge 171:3a7713b1edbc 489 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 490 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 491 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 492 } DMAC_BUSYCH_Type;
AnnaBridge 171:3a7713b1edbc 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
AnnaBridge 171:3a7713b1edbc 496 #define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
AnnaBridge 171:3a7713b1edbc 499 #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
AnnaBridge 171:3a7713b1edbc 500 #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
AnnaBridge 171:3a7713b1edbc 501 #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
AnnaBridge 171:3a7713b1edbc 502 #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
AnnaBridge 171:3a7713b1edbc 503 #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
AnnaBridge 171:3a7713b1edbc 504 #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
AnnaBridge 171:3a7713b1edbc 505 #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
AnnaBridge 171:3a7713b1edbc 506 #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
AnnaBridge 171:3a7713b1edbc 507 #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
AnnaBridge 171:3a7713b1edbc 508 #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
AnnaBridge 171:3a7713b1edbc 509 #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
AnnaBridge 171:3a7713b1edbc 510 #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
AnnaBridge 171:3a7713b1edbc 511 #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
AnnaBridge 171:3a7713b1edbc 512 #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
AnnaBridge 171:3a7713b1edbc 513 #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
AnnaBridge 171:3a7713b1edbc 514 #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
AnnaBridge 171:3a7713b1edbc 515 #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
AnnaBridge 171:3a7713b1edbc 516 #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
AnnaBridge 171:3a7713b1edbc 517 #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
AnnaBridge 171:3a7713b1edbc 518 #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
AnnaBridge 171:3a7713b1edbc 519 #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
AnnaBridge 171:3a7713b1edbc 520 #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
AnnaBridge 171:3a7713b1edbc 521 #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
AnnaBridge 171:3a7713b1edbc 522 #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
AnnaBridge 171:3a7713b1edbc 523 #define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
AnnaBridge 171:3a7713b1edbc 524 #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
AnnaBridge 171:3a7713b1edbc 525 #define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
AnnaBridge 171:3a7713b1edbc 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 529 typedef union {
AnnaBridge 171:3a7713b1edbc 530 struct {
AnnaBridge 171:3a7713b1edbc 531 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
AnnaBridge 171:3a7713b1edbc 532 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
AnnaBridge 171:3a7713b1edbc 533 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
AnnaBridge 171:3a7713b1edbc 534 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
AnnaBridge 171:3a7713b1edbc 535 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
AnnaBridge 171:3a7713b1edbc 536 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
AnnaBridge 171:3a7713b1edbc 537 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
AnnaBridge 171:3a7713b1edbc 538 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
AnnaBridge 171:3a7713b1edbc 539 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
AnnaBridge 171:3a7713b1edbc 540 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
AnnaBridge 171:3a7713b1edbc 541 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
AnnaBridge 171:3a7713b1edbc 542 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
AnnaBridge 171:3a7713b1edbc 543 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 544 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 545 struct {
AnnaBridge 171:3a7713b1edbc 546 uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
AnnaBridge 171:3a7713b1edbc 547 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 548 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 549 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 550 } DMAC_PENDCH_Type;
AnnaBridge 171:3a7713b1edbc 551 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
AnnaBridge 171:3a7713b1edbc 554 #define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556 #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
AnnaBridge 171:3a7713b1edbc 557 #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
AnnaBridge 171:3a7713b1edbc 558 #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
AnnaBridge 171:3a7713b1edbc 559 #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
AnnaBridge 171:3a7713b1edbc 561 #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
AnnaBridge 171:3a7713b1edbc 562 #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
AnnaBridge 171:3a7713b1edbc 563 #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
AnnaBridge 171:3a7713b1edbc 564 #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
AnnaBridge 171:3a7713b1edbc 565 #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
AnnaBridge 171:3a7713b1edbc 566 #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
AnnaBridge 171:3a7713b1edbc 567 #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
AnnaBridge 171:3a7713b1edbc 568 #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
AnnaBridge 171:3a7713b1edbc 569 #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
AnnaBridge 171:3a7713b1edbc 570 #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
AnnaBridge 171:3a7713b1edbc 571 #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
AnnaBridge 171:3a7713b1edbc 572 #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
AnnaBridge 171:3a7713b1edbc 573 #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
AnnaBridge 171:3a7713b1edbc 574 #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
AnnaBridge 171:3a7713b1edbc 575 #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
AnnaBridge 171:3a7713b1edbc 576 #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
AnnaBridge 171:3a7713b1edbc 577 #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
AnnaBridge 171:3a7713b1edbc 578 #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
AnnaBridge 171:3a7713b1edbc 579 #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
AnnaBridge 171:3a7713b1edbc 580 #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
AnnaBridge 171:3a7713b1edbc 581 #define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
AnnaBridge 171:3a7713b1edbc 582 #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
AnnaBridge 171:3a7713b1edbc 583 #define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
AnnaBridge 171:3a7713b1edbc 586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 587 typedef union {
AnnaBridge 171:3a7713b1edbc 588 struct {
AnnaBridge 171:3a7713b1edbc 589 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 590 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 591 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 592 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 593 uint32_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 594 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
AnnaBridge 171:3a7713b1edbc 595 uint32_t :2; /*!< bit: 13..14 Reserved */
AnnaBridge 171:3a7713b1edbc 596 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
AnnaBridge 171:3a7713b1edbc 597 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 598 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 599 struct {
AnnaBridge 171:3a7713b1edbc 600 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 601 uint32_t :28; /*!< bit: 4..31 Reserved */
AnnaBridge 171:3a7713b1edbc 602 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 603 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 604 } DMAC_ACTIVE_Type;
AnnaBridge 171:3a7713b1edbc 605 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
AnnaBridge 171:3a7713b1edbc 608 #define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 611 #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
AnnaBridge 171:3a7713b1edbc 612 #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 613 #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
AnnaBridge 171:3a7713b1edbc 614 #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 615 #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
AnnaBridge 171:3a7713b1edbc 616 #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 617 #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
AnnaBridge 171:3a7713b1edbc 618 #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
AnnaBridge 171:3a7713b1edbc 619 #define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
AnnaBridge 171:3a7713b1edbc 620 #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
AnnaBridge 171:3a7713b1edbc 621 #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
AnnaBridge 171:3a7713b1edbc 622 #define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
AnnaBridge 171:3a7713b1edbc 623 #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
AnnaBridge 171:3a7713b1edbc 624 #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
AnnaBridge 171:3a7713b1edbc 625 #define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
AnnaBridge 171:3a7713b1edbc 626 #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 627 #define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
AnnaBridge 171:3a7713b1edbc 628 #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
AnnaBridge 171:3a7713b1edbc 629 #define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
AnnaBridge 171:3a7713b1edbc 630
AnnaBridge 171:3a7713b1edbc 631 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
AnnaBridge 171:3a7713b1edbc 632 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 633 typedef union {
AnnaBridge 171:3a7713b1edbc 634 struct {
AnnaBridge 171:3a7713b1edbc 635 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
AnnaBridge 171:3a7713b1edbc 636 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 637 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 638 } DMAC_BASEADDR_Type;
AnnaBridge 171:3a7713b1edbc 639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 642 #define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 643
AnnaBridge 171:3a7713b1edbc 644 #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
AnnaBridge 171:3a7713b1edbc 645 #define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
AnnaBridge 171:3a7713b1edbc 646 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
AnnaBridge 171:3a7713b1edbc 647 #define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
AnnaBridge 171:3a7713b1edbc 650 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 651 typedef union {
AnnaBridge 171:3a7713b1edbc 652 struct {
AnnaBridge 171:3a7713b1edbc 653 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
AnnaBridge 171:3a7713b1edbc 654 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 655 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 656 } DMAC_WRBADDR_Type;
AnnaBridge 171:3a7713b1edbc 657 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 660 #define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
AnnaBridge 171:3a7713b1edbc 663 #define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
AnnaBridge 171:3a7713b1edbc 664 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
AnnaBridge 171:3a7713b1edbc 665 #define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
AnnaBridge 171:3a7713b1edbc 668 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 669 typedef union {
AnnaBridge 171:3a7713b1edbc 670 struct {
AnnaBridge 171:3a7713b1edbc 671 uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
AnnaBridge 171:3a7713b1edbc 672 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 673 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 674 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 675 } DMAC_CHID_Type;
AnnaBridge 171:3a7713b1edbc 676 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 677
AnnaBridge 171:3a7713b1edbc 678 #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
AnnaBridge 171:3a7713b1edbc 679 #define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
AnnaBridge 171:3a7713b1edbc 682 #define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
AnnaBridge 171:3a7713b1edbc 683 #define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
AnnaBridge 171:3a7713b1edbc 684 #define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
AnnaBridge 171:3a7713b1edbc 685
AnnaBridge 171:3a7713b1edbc 686 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
AnnaBridge 171:3a7713b1edbc 687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 688 typedef union {
AnnaBridge 171:3a7713b1edbc 689 struct {
AnnaBridge 171:3a7713b1edbc 690 uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
AnnaBridge 171:3a7713b1edbc 691 uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
AnnaBridge 171:3a7713b1edbc 692 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 693 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 694 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 695 } DMAC_CHCTRLA_Type;
AnnaBridge 171:3a7713b1edbc 696 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 697
AnnaBridge 171:3a7713b1edbc 698 #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
AnnaBridge 171:3a7713b1edbc 699 #define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
AnnaBridge 171:3a7713b1edbc 702 #define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 703 #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
AnnaBridge 171:3a7713b1edbc 704 #define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 705 #define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
AnnaBridge 171:3a7713b1edbc 708 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 709 typedef union {
AnnaBridge 171:3a7713b1edbc 710 struct {
AnnaBridge 171:3a7713b1edbc 711 uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
AnnaBridge 171:3a7713b1edbc 712 uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
AnnaBridge 171:3a7713b1edbc 713 uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
AnnaBridge 171:3a7713b1edbc 714 uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
AnnaBridge 171:3a7713b1edbc 715 uint32_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 716 uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
AnnaBridge 171:3a7713b1edbc 717 uint32_t :8; /*!< bit: 14..21 Reserved */
AnnaBridge 171:3a7713b1edbc 718 uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
AnnaBridge 171:3a7713b1edbc 719 uint32_t CMD:2; /*!< bit: 24..25 Software Command */
AnnaBridge 171:3a7713b1edbc 720 uint32_t :6; /*!< bit: 26..31 Reserved */
AnnaBridge 171:3a7713b1edbc 721 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 722 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 723 } DMAC_CHCTRLB_Type;
AnnaBridge 171:3a7713b1edbc 724 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
AnnaBridge 171:3a7713b1edbc 727 #define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
AnnaBridge 171:3a7713b1edbc 730 #define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 731 #define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
AnnaBridge 171:3a7713b1edbc 732 #define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
AnnaBridge 171:3a7713b1edbc 733 #define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
AnnaBridge 171:3a7713b1edbc 734 #define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
AnnaBridge 171:3a7713b1edbc 735 #define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
AnnaBridge 171:3a7713b1edbc 736 #define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
AnnaBridge 171:3a7713b1edbc 737 #define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
AnnaBridge 171:3a7713b1edbc 738 #define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
AnnaBridge 171:3a7713b1edbc 739 #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 740 #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 741 #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 742 #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 743 #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 744 #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 745 #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 746 #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
AnnaBridge 171:3a7713b1edbc 747 #define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
AnnaBridge 171:3a7713b1edbc 748 #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
AnnaBridge 171:3a7713b1edbc 749 #define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
AnnaBridge 171:3a7713b1edbc 750 #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
AnnaBridge 171:3a7713b1edbc 751 #define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
AnnaBridge 171:3a7713b1edbc 752 #define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
AnnaBridge 171:3a7713b1edbc 753 #define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
AnnaBridge 171:3a7713b1edbc 754 #define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
AnnaBridge 171:3a7713b1edbc 755 #define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
AnnaBridge 171:3a7713b1edbc 756 #define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
AnnaBridge 171:3a7713b1edbc 757 #define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
AnnaBridge 171:3a7713b1edbc 758 #define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
AnnaBridge 171:3a7713b1edbc 759 #define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
AnnaBridge 171:3a7713b1edbc 760 #define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
AnnaBridge 171:3a7713b1edbc 761 #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */
AnnaBridge 171:3a7713b1edbc 762 #define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
AnnaBridge 171:3a7713b1edbc 763 #define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
AnnaBridge 171:3a7713b1edbc 764 #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
AnnaBridge 171:3a7713b1edbc 765 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
AnnaBridge 171:3a7713b1edbc 766 #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
AnnaBridge 171:3a7713b1edbc 767 #define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
AnnaBridge 171:3a7713b1edbc 768 #define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
AnnaBridge 171:3a7713b1edbc 769 #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
AnnaBridge 171:3a7713b1edbc 770 #define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
AnnaBridge 171:3a7713b1edbc 771 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
AnnaBridge 171:3a7713b1edbc 772 #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
AnnaBridge 171:3a7713b1edbc 773 #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
AnnaBridge 171:3a7713b1edbc 774 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
AnnaBridge 171:3a7713b1edbc 775 #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
AnnaBridge 171:3a7713b1edbc 776 #define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 777 #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 778 #define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
AnnaBridge 171:3a7713b1edbc 779 #define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
AnnaBridge 171:3a7713b1edbc 780 #define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
AnnaBridge 171:3a7713b1edbc 781 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 782 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 783 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 784 #define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 785
AnnaBridge 171:3a7713b1edbc 786 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 787 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 788 typedef union {
AnnaBridge 171:3a7713b1edbc 789 struct {
AnnaBridge 171:3a7713b1edbc 790 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 791 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 792 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 793 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 794 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 795 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 796 } DMAC_CHINTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 797 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 800 #define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 803 #define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
AnnaBridge 171:3a7713b1edbc 804 #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 805 #define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
AnnaBridge 171:3a7713b1edbc 806 #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 807 #define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
AnnaBridge 171:3a7713b1edbc 808 #define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 811 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 812 typedef union {
AnnaBridge 171:3a7713b1edbc 813 struct {
AnnaBridge 171:3a7713b1edbc 814 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 815 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 816 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 817 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 818 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 819 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 820 } DMAC_CHINTENSET_Type;
AnnaBridge 171:3a7713b1edbc 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 822
AnnaBridge 171:3a7713b1edbc 823 #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 824 #define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826 #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 827 #define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos)
AnnaBridge 171:3a7713b1edbc 828 #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 829 #define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
AnnaBridge 171:3a7713b1edbc 830 #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 831 #define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
AnnaBridge 171:3a7713b1edbc 832 #define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 835 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 836 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 837 struct {
AnnaBridge 171:3a7713b1edbc 838 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
AnnaBridge 171:3a7713b1edbc 839 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
AnnaBridge 171:3a7713b1edbc 840 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
AnnaBridge 171:3a7713b1edbc 841 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 842 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 843 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 844 } DMAC_CHINTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 845 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 848 #define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 849
AnnaBridge 171:3a7713b1edbc 850 #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
AnnaBridge 171:3a7713b1edbc 851 #define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
AnnaBridge 171:3a7713b1edbc 852 #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
AnnaBridge 171:3a7713b1edbc 853 #define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
AnnaBridge 171:3a7713b1edbc 854 #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
AnnaBridge 171:3a7713b1edbc 855 #define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
AnnaBridge 171:3a7713b1edbc 856 #define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
AnnaBridge 171:3a7713b1edbc 859 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 860 typedef union {
AnnaBridge 171:3a7713b1edbc 861 struct {
AnnaBridge 171:3a7713b1edbc 862 uint8_t PEND:1; /*!< bit: 0 Channel Pending */
AnnaBridge 171:3a7713b1edbc 863 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
AnnaBridge 171:3a7713b1edbc 864 uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
AnnaBridge 171:3a7713b1edbc 865 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 866 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 867 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 868 } DMAC_CHSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 869 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
AnnaBridge 171:3a7713b1edbc 872 #define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
AnnaBridge 171:3a7713b1edbc 875 #define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos)
AnnaBridge 171:3a7713b1edbc 876 #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
AnnaBridge 171:3a7713b1edbc 877 #define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
AnnaBridge 171:3a7713b1edbc 878 #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
AnnaBridge 171:3a7713b1edbc 879 #define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos)
AnnaBridge 171:3a7713b1edbc 880 #define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 881
AnnaBridge 171:3a7713b1edbc 882 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
AnnaBridge 171:3a7713b1edbc 883 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 884 typedef union {
AnnaBridge 171:3a7713b1edbc 885 struct {
AnnaBridge 171:3a7713b1edbc 886 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
AnnaBridge 171:3a7713b1edbc 887 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
AnnaBridge 171:3a7713b1edbc 888 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
AnnaBridge 171:3a7713b1edbc 889 uint16_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 890 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
AnnaBridge 171:3a7713b1edbc 891 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
AnnaBridge 171:3a7713b1edbc 892 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
AnnaBridge 171:3a7713b1edbc 893 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
AnnaBridge 171:3a7713b1edbc 894 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
AnnaBridge 171:3a7713b1edbc 895 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 896 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 897 } DMAC_BTCTRL_Type;
AnnaBridge 171:3a7713b1edbc 898 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 899
AnnaBridge 171:3a7713b1edbc 900 #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
AnnaBridge 171:3a7713b1edbc 901 #define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
AnnaBridge 171:3a7713b1edbc 902
AnnaBridge 171:3a7713b1edbc 903 #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
AnnaBridge 171:3a7713b1edbc 904 #define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
AnnaBridge 171:3a7713b1edbc 905 #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
AnnaBridge 171:3a7713b1edbc 906 #define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
AnnaBridge 171:3a7713b1edbc 907 #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
AnnaBridge 171:3a7713b1edbc 908 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
AnnaBridge 171:3a7713b1edbc 909 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
AnnaBridge 171:3a7713b1edbc 910 #define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
AnnaBridge 171:3a7713b1edbc 911 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
AnnaBridge 171:3a7713b1edbc 912 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
AnnaBridge 171:3a7713b1edbc 913 #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
AnnaBridge 171:3a7713b1edbc 914 #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
AnnaBridge 171:3a7713b1edbc 915 #define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
AnnaBridge 171:3a7713b1edbc 916 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
AnnaBridge 171:3a7713b1edbc 917 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
AnnaBridge 171:3a7713b1edbc 918 #define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
AnnaBridge 171:3a7713b1edbc 919 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
AnnaBridge 171:3a7713b1edbc 920 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
AnnaBridge 171:3a7713b1edbc 921 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
AnnaBridge 171:3a7713b1edbc 922 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
AnnaBridge 171:3a7713b1edbc 923 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
AnnaBridge 171:3a7713b1edbc 924 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
AnnaBridge 171:3a7713b1edbc 925 #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
AnnaBridge 171:3a7713b1edbc 926 #define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 927 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
AnnaBridge 171:3a7713b1edbc 928 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 929 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 930 #define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
AnnaBridge 171:3a7713b1edbc 931 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 932 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 933 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 934 #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
AnnaBridge 171:3a7713b1edbc 935 #define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
AnnaBridge 171:3a7713b1edbc 936 #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
AnnaBridge 171:3a7713b1edbc 937 #define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
AnnaBridge 171:3a7713b1edbc 938 #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
AnnaBridge 171:3a7713b1edbc 939 #define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
AnnaBridge 171:3a7713b1edbc 940 #define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
AnnaBridge 171:3a7713b1edbc 941 #define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
AnnaBridge 171:3a7713b1edbc 942 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
AnnaBridge 171:3a7713b1edbc 943 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
AnnaBridge 171:3a7713b1edbc 944 #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
AnnaBridge 171:3a7713b1edbc 945 #define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 946 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
AnnaBridge 171:3a7713b1edbc 947 #define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */
AnnaBridge 171:3a7713b1edbc 948 #define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */
AnnaBridge 171:3a7713b1edbc 949 #define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */
AnnaBridge 171:3a7713b1edbc 950 #define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */
AnnaBridge 171:3a7713b1edbc 951 #define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */
AnnaBridge 171:3a7713b1edbc 952 #define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */
AnnaBridge 171:3a7713b1edbc 953 #define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */
AnnaBridge 171:3a7713b1edbc 954 #define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */
AnnaBridge 171:3a7713b1edbc 955 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 956 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 957 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 958 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 959 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 960 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 961 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 962 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 963 #define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 964
AnnaBridge 171:3a7713b1edbc 965 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
AnnaBridge 171:3a7713b1edbc 966 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 967 typedef union {
AnnaBridge 171:3a7713b1edbc 968 struct {
AnnaBridge 171:3a7713b1edbc 969 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 970 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 971 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 972 } DMAC_BTCNT_Type;
AnnaBridge 171:3a7713b1edbc 973 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975 #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 976
AnnaBridge 171:3a7713b1edbc 977 #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 978 #define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
AnnaBridge 171:3a7713b1edbc 979 #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
AnnaBridge 171:3a7713b1edbc 980 #define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
AnnaBridge 171:3a7713b1edbc 983 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 984 typedef union {
AnnaBridge 171:3a7713b1edbc 985 struct {
AnnaBridge 171:3a7713b1edbc 986 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
AnnaBridge 171:3a7713b1edbc 987 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 988 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 989 } DMAC_SRCADDR_Type;
AnnaBridge 171:3a7713b1edbc 990 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 991
AnnaBridge 171:3a7713b1edbc 992 #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
AnnaBridge 171:3a7713b1edbc 995 #define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
AnnaBridge 171:3a7713b1edbc 996 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
AnnaBridge 171:3a7713b1edbc 997 #define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 998
AnnaBridge 171:3a7713b1edbc 999 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
AnnaBridge 171:3a7713b1edbc 1000 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1001 typedef union {
AnnaBridge 171:3a7713b1edbc 1002 struct {
AnnaBridge 171:3a7713b1edbc 1003 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
AnnaBridge 171:3a7713b1edbc 1004 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1005 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1006 } DMAC_DSTADDR_Type;
AnnaBridge 171:3a7713b1edbc 1007 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1008
AnnaBridge 171:3a7713b1edbc 1009 #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
AnnaBridge 171:3a7713b1edbc 1010
AnnaBridge 171:3a7713b1edbc 1011 #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
AnnaBridge 171:3a7713b1edbc 1012 #define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
AnnaBridge 171:3a7713b1edbc 1013 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
AnnaBridge 171:3a7713b1edbc 1014 #define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
AnnaBridge 171:3a7713b1edbc 1017 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1018 typedef union {
AnnaBridge 171:3a7713b1edbc 1019 struct {
AnnaBridge 171:3a7713b1edbc 1020 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
AnnaBridge 171:3a7713b1edbc 1021 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1022 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1023 } DMAC_DESCADDR_Type;
AnnaBridge 171:3a7713b1edbc 1024 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1025
AnnaBridge 171:3a7713b1edbc 1026 #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
AnnaBridge 171:3a7713b1edbc 1027
AnnaBridge 171:3a7713b1edbc 1028 #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
AnnaBridge 171:3a7713b1edbc 1029 #define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
AnnaBridge 171:3a7713b1edbc 1030 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
AnnaBridge 171:3a7713b1edbc 1031 #define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 1032
AnnaBridge 171:3a7713b1edbc 1033 /** \brief DMAC APB hardware registers */
AnnaBridge 171:3a7713b1edbc 1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1035 typedef struct {
AnnaBridge 171:3a7713b1edbc 1036 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
AnnaBridge 171:3a7713b1edbc 1037 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
AnnaBridge 171:3a7713b1edbc 1038 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
AnnaBridge 171:3a7713b1edbc 1039 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
AnnaBridge 171:3a7713b1edbc 1040 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
AnnaBridge 171:3a7713b1edbc 1041 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 1042 __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
AnnaBridge 171:3a7713b1edbc 1043 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 1044 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
AnnaBridge 171:3a7713b1edbc 1045 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
AnnaBridge 171:3a7713b1edbc 1046 RoReg8 Reserved2[0x8];
AnnaBridge 171:3a7713b1edbc 1047 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
AnnaBridge 171:3a7713b1edbc 1048 RoReg8 Reserved3[0x2];
AnnaBridge 171:3a7713b1edbc 1049 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
AnnaBridge 171:3a7713b1edbc 1050 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
AnnaBridge 171:3a7713b1edbc 1051 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
AnnaBridge 171:3a7713b1edbc 1052 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
AnnaBridge 171:3a7713b1edbc 1053 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 1054 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
AnnaBridge 171:3a7713b1edbc 1055 RoReg8 Reserved4[0x3];
AnnaBridge 171:3a7713b1edbc 1056 __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
AnnaBridge 171:3a7713b1edbc 1057 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
AnnaBridge 171:3a7713b1edbc 1058 RoReg8 Reserved5[0x3];
AnnaBridge 171:3a7713b1edbc 1059 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
AnnaBridge 171:3a7713b1edbc 1060 RoReg8 Reserved6[0x4];
AnnaBridge 171:3a7713b1edbc 1061 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1062 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1063 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1064 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
AnnaBridge 171:3a7713b1edbc 1065 } Dmac;
AnnaBridge 171:3a7713b1edbc 1066 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1067
AnnaBridge 171:3a7713b1edbc 1068 /** \brief DMAC Descriptor SRAM registers */
AnnaBridge 171:3a7713b1edbc 1069 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1070 typedef struct {
AnnaBridge 171:3a7713b1edbc 1071 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
AnnaBridge 171:3a7713b1edbc 1072 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
AnnaBridge 171:3a7713b1edbc 1073 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
AnnaBridge 171:3a7713b1edbc 1074 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
AnnaBridge 171:3a7713b1edbc 1075 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
AnnaBridge 171:3a7713b1edbc 1076 } DmacDescriptor
AnnaBridge 171:3a7713b1edbc 1077 #ifdef __GNUC__
AnnaBridge 171:3a7713b1edbc 1078 __attribute__ ((aligned (8)))
AnnaBridge 171:3a7713b1edbc 1079 #endif
AnnaBridge 171:3a7713b1edbc 1080 ;
AnnaBridge 171:3a7713b1edbc 1081 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1082 #define SECTION_DMAC_DESCRIPTOR
AnnaBridge 171:3a7713b1edbc 1083
AnnaBridge 171:3a7713b1edbc 1084 /*@}*/
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 #endif /* _SAMR21_DMAC_COMPONENT_ */