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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/pio_samr21e16a.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
| AnnaBridge | 171:3a7713b1edbc | 3 | * |
| AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Peripheral I/O description for SAMR21E16A |
| AnnaBridge | 171:3a7713b1edbc | 5 | * |
| AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2015 Atmel Corporation. All rights reserved. |
| AnnaBridge | 171:3a7713b1edbc | 7 | * |
| AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
| AnnaBridge | 171:3a7713b1edbc | 11 | * |
| AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
| AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 14 | * |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 24 | * |
| AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
| AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 39 | * |
| AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
| AnnaBridge | 171:3a7713b1edbc | 41 | * |
| AnnaBridge | 171:3a7713b1edbc | 42 | */ |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | #ifndef _SAMR21E16A_PIO_ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #define _SAMR21E16A_PIO_ |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | #define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | #define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | #define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | #define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | #define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | #define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | #define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | #define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | #define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | #define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define PIN_PC16 80 /**< \brief Pin Number for PC16 */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | /* ========== PORT definition for GCLK peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define MUX_PB14H_GCLK_IO0 7L |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define PORT_PB14H_GCLK_IO0 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define MUX_PA14H_GCLK_IO0 7L |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define PORT_PA14H_GCLK_IO0 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define MUX_PA27H_GCLK_IO0 7L |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define PORT_PA27H_GCLK_IO0 (1ul << 27) |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define MUX_PA28H_GCLK_IO0 7L |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define PORT_PA28H_GCLK_IO0 (1ul << 28) |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define MUX_PA30H_GCLK_IO0 7L |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define PORT_PA30H_GCLK_IO0 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define MUX_PB15H_GCLK_IO1 7L |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define PORT_PB15H_GCLK_IO1 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define MUX_PA15H_GCLK_IO1 7L |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define PORT_PA15H_GCLK_IO1 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define MUX_PC16F_GCLK_IO1 5L |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define PORT_PC16F_GCLK_IO1 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define MUX_PB16H_GCLK_IO2 7L |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define PORT_PB16H_GCLK_IO2 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define MUX_PA16H_GCLK_IO2 7L |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define PORT_PA16H_GCLK_IO2 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define MUX_PA17H_GCLK_IO3 7L |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define PORT_PA17H_GCLK_IO3 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define MUX_PB17H_GCLK_IO3 7L |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define PORT_PB17H_GCLK_IO3 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define MUX_PA10H_GCLK_IO4 7L |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define PORT_PA10H_GCLK_IO4 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define MUX_PA20H_GCLK_IO4 7L |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define PORT_PA20H_GCLK_IO4 (1ul << 20) |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define MUX_PA11H_GCLK_IO5 7L |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define PORT_PA11H_GCLK_IO5 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 170 | /* ========== PORT definition for EIC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define MUX_PA16A_EIC_EXTINT0 0L |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define PORT_PA16A_EIC_EXTINT0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define MUX_PB00A_EIC_EXTINT0 0L |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define PORT_PB00A_EIC_EXTINT0 (1ul << 0) |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define MUX_PB16A_EIC_EXTINT0 0L |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define PORT_PB16A_EIC_EXTINT0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define MUX_PA17A_EIC_EXTINT1 0L |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define PORT_PA17A_EIC_EXTINT1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define MUX_PB17A_EIC_EXTINT1 0L |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define PORT_PB17A_EIC_EXTINT1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define MUX_PA18A_EIC_EXTINT2 0L |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define PORT_PA18A_EIC_EXTINT2 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define MUX_PA19A_EIC_EXTINT3 0L |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define PORT_PA19A_EIC_EXTINT3 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define MUX_PA20A_EIC_EXTINT4 0L |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define PORT_PA20A_EIC_EXTINT4 (1ul << 20) |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define MUX_PA06A_EIC_EXTINT6 0L |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define PORT_PA06A_EIC_EXTINT6 (1ul << 6) |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define MUX_PA07A_EIC_EXTINT7 0L |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define PORT_PA07A_EIC_EXTINT7 (1ul << 7) |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define MUX_PA28A_EIC_EXTINT8 0L |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define PORT_PA28A_EIC_EXTINT8 (1ul << 28) |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define MUX_PB08A_EIC_EXTINT8 0L |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define PORT_PB08A_EIC_EXTINT8 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define MUX_PA09A_EIC_EXTINT9 0L |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define PORT_PA09A_EIC_EXTINT9 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define MUX_PB09A_EIC_EXTINT9 0L |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define PORT_PB09A_EIC_EXTINT9 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define MUX_PA10A_EIC_EXTINT10 0L |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define PORT_PA10A_EIC_EXTINT10 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define MUX_PA30A_EIC_EXTINT10 0L |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define PORT_PA30A_EIC_EXTINT10 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define MUX_PA11A_EIC_EXTINT11 0L |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define PORT_PA11A_EIC_EXTINT11 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define MUX_PA31A_EIC_EXTINT11 0L |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define PORT_PA31A_EIC_EXTINT11 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define MUX_PA24A_EIC_EXTINT12 0L |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define PORT_PA24A_EIC_EXTINT12 (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define MUX_PA25A_EIC_EXTINT13 0L |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define PORT_PA25A_EIC_EXTINT13 (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define MUX_PB14A_EIC_EXTINT14 0L |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define PORT_PB14A_EIC_EXTINT14 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define MUX_PB30A_EIC_EXTINT14 0L |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define PORT_PB30A_EIC_EXTINT14 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define MUX_PA14A_EIC_EXTINT14 0L |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define PORT_PA14A_EIC_EXTINT14 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define MUX_PA15A_EIC_EXTINT15 0L |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define PORT_PA15A_EIC_EXTINT15 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define MUX_PA27A_EIC_EXTINT15 0L |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define PORT_PA27A_EIC_EXTINT15 (1ul << 27) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define MUX_PB15A_EIC_EXTINT15 0L |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define PORT_PB15A_EIC_EXTINT15 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define MUX_PB31A_EIC_EXTINT15 0L |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define PORT_PB31A_EIC_EXTINT15 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define MUX_PA08A_EIC_NMI 0L |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define PORT_PA08A_EIC_NMI (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 283 | /* ========== PORT definition for USB peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define MUX_PA24G_USB_DM 6L |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define PORT_PA24G_USB_DM (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define MUX_PA25G_USB_DP 6L |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define PORT_PA25G_USB_DP (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 292 | /* ========== PORT definition for SERCOM0 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define MUX_PA08C_SERCOM0_PAD0 2L |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define MUX_PA09C_SERCOM0_PAD1 2L |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define MUX_PA06D_SERCOM0_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define MUX_PA10C_SERCOM0_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define MUX_PA07D_SERCOM0_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define MUX_PA11C_SERCOM0_PAD3 2L |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 317 | /* ========== PORT definition for SERCOM1 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define MUX_PA16C_SERCOM1_PAD0 2L |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define MUX_PA17C_SERCOM1_PAD1 2L |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define MUX_PA30D_SERCOM1_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define MUX_PA18C_SERCOM1_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define MUX_PA31D_SERCOM1_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define MUX_PA19C_SERCOM1_PAD3 2L |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 342 | /* ========== PORT definition for SERCOM2 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define MUX_PA08D_SERCOM2_PAD0 3L |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define MUX_PA09D_SERCOM2_PAD1 3L |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define MUX_PA10D_SERCOM2_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define MUX_PA14C_SERCOM2_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define MUX_PA11D_SERCOM2_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define MUX_PA15C_SERCOM2_PAD3 2L |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 367 | /* ========== PORT definition for SERCOM3 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define MUX_PA16D_SERCOM3_PAD0 3L |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define MUX_PA27F_SERCOM3_PAD0 5L |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define MUX_PA17D_SERCOM3_PAD1 3L |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define MUX_PA28F_SERCOM3_PAD1 5L |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define MUX_PA18D_SERCOM3_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define MUX_PA20D_SERCOM3_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define MUX_PA24C_SERCOM3_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define MUX_PA19D_SERCOM3_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define MUX_PA25C_SERCOM3_PAD3 2L |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 404 | /* ========== PORT definition for SERCOM4 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define MUX_PB08D_SERCOM4_PAD0 3L |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define MUX_PC19F_SERCOM4_PAD0 5L |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define MUX_PB09D_SERCOM4_PAD1 3L |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define MUX_PB31F_SERCOM4_PAD1 5L |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define MUX_PA14D_SERCOM4_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define MUX_PB14C_SERCOM4_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define MUX_PB30F_SERCOM4_PAD2 5L |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define MUX_PA15D_SERCOM4_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define MUX_PB15C_SERCOM4_PAD3 2L |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define MUX_PC18F_SERCOM4_PAD3 5L |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 445 | /* ========== PORT definition for SERCOM5 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define MUX_PB16C_SERCOM5_PAD0 2L |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define MUX_PB30D_SERCOM5_PAD0 3L |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define MUX_PB17C_SERCOM5_PAD1 2L |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define MUX_PB31D_SERCOM5_PAD1 3L |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define MUX_PA24D_SERCOM5_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define MUX_PB00D_SERCOM5_PAD2 3L |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define MUX_PA20C_SERCOM5_PAD2 2L |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define MUX_PA25D_SERCOM5_PAD3 3L |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 478 | /* ========== PORT definition for TCC0 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define MUX_PA08E_TCC0_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define PORT_PA08E_TCC0_WO0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define MUX_PB30E_TCC0_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define PORT_PB30E_TCC0_WO0 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define MUX_PA16F_TCC0_WO0 5L |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define PORT_PA16F_TCC0_WO0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define MUX_PA09E_TCC0_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define PORT_PA09E_TCC0_WO1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define MUX_PB31E_TCC0_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define PORT_PB31E_TCC0_WO1 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define MUX_PA17F_TCC0_WO1 5L |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define PORT_PA17F_TCC0_WO1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define MUX_PA10F_TCC0_WO2 5L |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define PORT_PA10F_TCC0_WO2 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 507 | #define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define MUX_PA18F_TCC0_WO2 5L |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define PORT_PA18F_TCC0_WO2 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define MUX_PA11F_TCC0_WO3 5L |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define PORT_PA11F_TCC0_WO3 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define MUX_PA19F_TCC0_WO3 5L |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define PORT_PA19F_TCC0_WO3 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define MUX_PB16F_TCC0_WO4 5L |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define PORT_PB16F_TCC0_WO4 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define MUX_PB17F_TCC0_WO5 5L |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define PORT_PB17F_TCC0_WO5 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define MUX_PA20F_TCC0_WO6 5L |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define PORT_PA20F_TCC0_WO6 (1ul << 20) |
| AnnaBridge | 171:3a7713b1edbc | 531 | /* ========== PORT definition for TCC1 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define MUX_PA06E_TCC1_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define PORT_PA06E_TCC1_WO0 (1ul << 6) |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define MUX_PA10E_TCC1_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define PORT_PA10E_TCC1_WO0 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define MUX_PA30E_TCC1_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define PORT_PA30E_TCC1_WO0 (1ul << 30) |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define MUX_PA07E_TCC1_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define PORT_PA07E_TCC1_WO1 (1ul << 7) |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define MUX_PA11E_TCC1_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define PORT_PA11E_TCC1_WO1 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define MUX_PA31E_TCC1_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define PORT_PA31E_TCC1_WO1 (1ul << 31) |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define MUX_PA24F_TCC1_WO2 5L |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define PORT_PA24F_TCC1_WO2 (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define MUX_PA25F_TCC1_WO3 5L |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define PORT_PA25F_TCC1_WO3 (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 564 | /* ========== PORT definition for TCC2 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define MUX_PA16E_TCC2_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define PORT_PA16E_TCC2_WO0 (1ul << 16) |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define MUX_PA17E_TCC2_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define PORT_PA17E_TCC2_WO1 (1ul << 17) |
| AnnaBridge | 171:3a7713b1edbc | 573 | /* ========== PORT definition for TC3 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define MUX_PA18E_TC3_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define PORT_PA18E_TC3_WO0 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define MUX_PA14E_TC3_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define PORT_PA14E_TC3_WO0 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define MUX_PA19E_TC3_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define PORT_PA19E_TC3_WO1 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define MUX_PA15E_TC3_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define PORT_PA15E_TC3_WO1 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 590 | /* ========== PORT definition for TC4 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define MUX_PB08E_TC4_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define PORT_PB08E_TC4_WO0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define MUX_PB09E_TC4_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define PORT_PB09E_TC4_WO1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 599 | /* ========== PORT definition for TC5 peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define MUX_PA24E_TC5_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define PORT_PA24E_TC5_WO0 (1ul << 24) |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define MUX_PB14E_TC5_WO0 4L |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define PORT_PB14E_TC5_WO0 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define MUX_PA25E_TC5_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define PORT_PA25E_TC5_WO1 (1ul << 25) |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define MUX_PB15E_TC5_WO1 4L |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define PORT_PB15E_TC5_WO1 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 616 | /* ========== PORT definition for ADC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define MUX_PB08B_ADC_AIN2 1L |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define PORT_PB08B_ADC_AIN2 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define MUX_PB09B_ADC_AIN3 1L |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define PORT_PB09B_ADC_AIN3 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define MUX_PA06B_ADC_AIN6 1L |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define PORT_PA06B_ADC_AIN6 (1ul << 6) |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define MUX_PA07B_ADC_AIN7 1L |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define PORT_PA07B_ADC_AIN7 (1ul << 7) |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define MUX_PB00B_ADC_AIN8 1L |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define PORT_PB00B_ADC_AIN8 (1ul << 0) |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define MUX_PA08B_ADC_AIN16 1L |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define PORT_PA08B_ADC_AIN16 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | #define MUX_PA09B_ADC_AIN17 1L |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define PORT_PA09B_ADC_AIN17 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define MUX_PA10B_ADC_AIN18 1L |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define PORT_PA10B_ADC_AIN18 (1ul << 10) |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define MUX_PA11B_ADC_AIN19 1L |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define PORT_PA11B_ADC_AIN19 (1ul << 11) |
| AnnaBridge | 171:3a7713b1edbc | 653 | /* ========== PORT definition for AC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define MUX_PA06B_AC_AIN2 1L |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) |
| AnnaBridge | 171:3a7713b1edbc | 657 | #define PORT_PA06B_AC_AIN2 (1ul << 6) |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define MUX_PA07B_AC_AIN3 1L |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define PORT_PA07B_AC_AIN3 (1ul << 7) |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define MUX_PA18H_AC_CMP0 7L |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define PORT_PA18H_AC_CMP0 (1ul << 18) |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define MUX_PA19H_AC_CMP1 7L |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define PORT_PA19H_AC_CMP1 (1ul << 19) |
| AnnaBridge | 171:3a7713b1edbc | 670 | /* ========== PORT definition for RFCTRL peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define MUX_PA08F_RFCTRL_FECTRL0 5L |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define MUX_PA09F_RFCTRL_FECTRL1 5L |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define MUX_PA14F_RFCTRL_FECTRL4 5L |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define MUX_PA15F_RFCTRL_FECTRL5 5L |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) |
| AnnaBridge | 171:3a7713b1edbc | 687 | |
| AnnaBridge | 171:3a7713b1edbc | 688 | #endif /* _SAMR21E16A_PIO_ */ |
