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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/ins_sercom3.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Instance description for SERCOM3
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_SERCOM3_INSTANCE_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_SERCOM3_INSTANCE_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========== Register definition for SERCOM3 peripheral ========== */
AnnaBridge 171:3a7713b1edbc 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 49 #define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
AnnaBridge 171:3a7713b1edbc 50 #define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
AnnaBridge 171:3a7713b1edbc 51 #define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
AnnaBridge 171:3a7713b1edbc 52 #define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 53 #define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 54 #define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 55 #define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
AnnaBridge 171:3a7713b1edbc 56 #define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
AnnaBridge 171:3a7713b1edbc 57 #define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
AnnaBridge 171:3a7713b1edbc 58 #define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
AnnaBridge 171:3a7713b1edbc 59 #define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
AnnaBridge 171:3a7713b1edbc 60 #define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
AnnaBridge 171:3a7713b1edbc 61 #define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
AnnaBridge 171:3a7713b1edbc 62 #define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 63 #define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 64 #define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 65 #define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
AnnaBridge 171:3a7713b1edbc 66 #define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
AnnaBridge 171:3a7713b1edbc 67 #define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
AnnaBridge 171:3a7713b1edbc 68 #define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
AnnaBridge 171:3a7713b1edbc 69 #define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
AnnaBridge 171:3a7713b1edbc 70 #define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
AnnaBridge 171:3a7713b1edbc 71 #define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
AnnaBridge 171:3a7713b1edbc 72 #define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 73 #define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 74 #define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 75 #define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
AnnaBridge 171:3a7713b1edbc 76 #define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
AnnaBridge 171:3a7713b1edbc 77 #define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
AnnaBridge 171:3a7713b1edbc 78 #define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
AnnaBridge 171:3a7713b1edbc 79 #define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
AnnaBridge 171:3a7713b1edbc 80 #define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
AnnaBridge 171:3a7713b1edbc 81 #define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
AnnaBridge 171:3a7713b1edbc 82 #define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
AnnaBridge 171:3a7713b1edbc 83 #define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 84 #define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 85 #define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 86 #define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 87 #define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
AnnaBridge 171:3a7713b1edbc 88 #define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
AnnaBridge 171:3a7713b1edbc 89 #define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
AnnaBridge 171:3a7713b1edbc 90 #define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
AnnaBridge 171:3a7713b1edbc 91 #else
AnnaBridge 171:3a7713b1edbc 92 #define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
AnnaBridge 171:3a7713b1edbc 93 #define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
AnnaBridge 171:3a7713b1edbc 94 #define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
AnnaBridge 171:3a7713b1edbc 95 #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 96 #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 97 #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 98 #define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
AnnaBridge 171:3a7713b1edbc 99 #define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
AnnaBridge 171:3a7713b1edbc 100 #define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
AnnaBridge 171:3a7713b1edbc 101 #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
AnnaBridge 171:3a7713b1edbc 102 #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
AnnaBridge 171:3a7713b1edbc 103 #define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
AnnaBridge 171:3a7713b1edbc 104 #define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
AnnaBridge 171:3a7713b1edbc 105 #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 106 #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 107 #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 108 #define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
AnnaBridge 171:3a7713b1edbc 109 #define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
AnnaBridge 171:3a7713b1edbc 110 #define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
AnnaBridge 171:3a7713b1edbc 111 #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
AnnaBridge 171:3a7713b1edbc 112 #define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
AnnaBridge 171:3a7713b1edbc 113 #define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
AnnaBridge 171:3a7713b1edbc 114 #define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
AnnaBridge 171:3a7713b1edbc 115 #define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 116 #define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 117 #define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 118 #define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
AnnaBridge 171:3a7713b1edbc 119 #define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
AnnaBridge 171:3a7713b1edbc 120 #define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
AnnaBridge 171:3a7713b1edbc 121 #define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
AnnaBridge 171:3a7713b1edbc 122 #define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
AnnaBridge 171:3a7713b1edbc 123 #define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
AnnaBridge 171:3a7713b1edbc 124 #define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
AnnaBridge 171:3a7713b1edbc 125 #define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
AnnaBridge 171:3a7713b1edbc 126 #define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 127 #define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 128 #define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 129 #define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 130 #define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
AnnaBridge 171:3a7713b1edbc 131 #define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
AnnaBridge 171:3a7713b1edbc 132 #define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
AnnaBridge 171:3a7713b1edbc 133 #define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
AnnaBridge 171:3a7713b1edbc 134 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /* ========== Instance parameters for SERCOM3 peripheral ========== */
AnnaBridge 171:3a7713b1edbc 137 #define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
AnnaBridge 171:3a7713b1edbc 138 #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
AnnaBridge 171:3a7713b1edbc 139 #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
AnnaBridge 171:3a7713b1edbc 140 #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
AnnaBridge 171:3a7713b1edbc 141 #define SERCOM3_INT_MSB 6
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #endif /* _SAMR21_SERCOM3_INSTANCE_ */