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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/ins_port.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Instance description for PORT
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_PORT_INSTANCE_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_PORT_INSTANCE_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========== Register definition for PORT peripheral ========== */
AnnaBridge 171:3a7713b1edbc 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 49 #define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
AnnaBridge 171:3a7713b1edbc 50 #define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
AnnaBridge 171:3a7713b1edbc 51 #define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
AnnaBridge 171:3a7713b1edbc 52 #define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
AnnaBridge 171:3a7713b1edbc 53 #define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
AnnaBridge 171:3a7713b1edbc 54 #define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
AnnaBridge 171:3a7713b1edbc 55 #define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
AnnaBridge 171:3a7713b1edbc 56 #define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
AnnaBridge 171:3a7713b1edbc 57 #define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
AnnaBridge 171:3a7713b1edbc 58 #define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
AnnaBridge 171:3a7713b1edbc 59 #define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
AnnaBridge 171:3a7713b1edbc 60 #define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
AnnaBridge 171:3a7713b1edbc 61 #define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
AnnaBridge 171:3a7713b1edbc 62 #define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
AnnaBridge 171:3a7713b1edbc 63 #define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
AnnaBridge 171:3a7713b1edbc 64 #define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
AnnaBridge 171:3a7713b1edbc 65 #define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
AnnaBridge 171:3a7713b1edbc 66 #define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
AnnaBridge 171:3a7713b1edbc 67 #define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
AnnaBridge 171:3a7713b1edbc 68 #define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
AnnaBridge 171:3a7713b1edbc 69 #define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
AnnaBridge 171:3a7713b1edbc 70 #define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
AnnaBridge 171:3a7713b1edbc 71 #define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
AnnaBridge 171:3a7713b1edbc 72 #define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
AnnaBridge 171:3a7713b1edbc 73 #define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
AnnaBridge 171:3a7713b1edbc 74 #define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
AnnaBridge 171:3a7713b1edbc 75 #define REG_PORT_DIR2 (0x41004500U) /**< \brief (PORT) Data Direction 2 */
AnnaBridge 171:3a7713b1edbc 76 #define REG_PORT_DIRCLR2 (0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */
AnnaBridge 171:3a7713b1edbc 77 #define REG_PORT_DIRSET2 (0x41004508U) /**< \brief (PORT) Data Direction Set 2 */
AnnaBridge 171:3a7713b1edbc 78 #define REG_PORT_DIRTGL2 (0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */
AnnaBridge 171:3a7713b1edbc 79 #define REG_PORT_OUT2 (0x41004510U) /**< \brief (PORT) Data Output Value 2 */
AnnaBridge 171:3a7713b1edbc 80 #define REG_PORT_OUTCLR2 (0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */
AnnaBridge 171:3a7713b1edbc 81 #define REG_PORT_OUTSET2 (0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */
AnnaBridge 171:3a7713b1edbc 82 #define REG_PORT_OUTTGL2 (0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */
AnnaBridge 171:3a7713b1edbc 83 #define REG_PORT_IN2 (0x41004520U) /**< \brief (PORT) Data Input Value 2 */
AnnaBridge 171:3a7713b1edbc 84 #define REG_PORT_CTRL2 (0x41004524U) /**< \brief (PORT) Control 2 */
AnnaBridge 171:3a7713b1edbc 85 #define REG_PORT_WRCONFIG2 (0x41004528U) /**< \brief (PORT) Write Configuration 2 */
AnnaBridge 171:3a7713b1edbc 86 #define REG_PORT_PMUX2 (0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */
AnnaBridge 171:3a7713b1edbc 87 #define REG_PORT_PINCFG2 (0x41004540U) /**< \brief (PORT) Pin Configuration 2 */
AnnaBridge 171:3a7713b1edbc 88 #else
AnnaBridge 171:3a7713b1edbc 89 #define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
AnnaBridge 171:3a7713b1edbc 90 #define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
AnnaBridge 171:3a7713b1edbc 91 #define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
AnnaBridge 171:3a7713b1edbc 92 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
AnnaBridge 171:3a7713b1edbc 93 #define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
AnnaBridge 171:3a7713b1edbc 94 #define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
AnnaBridge 171:3a7713b1edbc 95 #define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
AnnaBridge 171:3a7713b1edbc 96 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
AnnaBridge 171:3a7713b1edbc 97 #define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
AnnaBridge 171:3a7713b1edbc 98 #define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
AnnaBridge 171:3a7713b1edbc 99 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
AnnaBridge 171:3a7713b1edbc 100 #define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
AnnaBridge 171:3a7713b1edbc 101 #define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
AnnaBridge 171:3a7713b1edbc 102 #define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
AnnaBridge 171:3a7713b1edbc 103 #define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
AnnaBridge 171:3a7713b1edbc 104 #define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
AnnaBridge 171:3a7713b1edbc 105 #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
AnnaBridge 171:3a7713b1edbc 106 #define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
AnnaBridge 171:3a7713b1edbc 107 #define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
AnnaBridge 171:3a7713b1edbc 108 #define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
AnnaBridge 171:3a7713b1edbc 109 #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
AnnaBridge 171:3a7713b1edbc 110 #define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
AnnaBridge 171:3a7713b1edbc 111 #define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
AnnaBridge 171:3a7713b1edbc 112 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
AnnaBridge 171:3a7713b1edbc 113 #define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
AnnaBridge 171:3a7713b1edbc 114 #define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
AnnaBridge 171:3a7713b1edbc 115 #define REG_PORT_DIR2 (*(RwReg *)0x41004500U) /**< \brief (PORT) Data Direction 2 */
AnnaBridge 171:3a7713b1edbc 116 #define REG_PORT_DIRCLR2 (*(RwReg *)0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */
AnnaBridge 171:3a7713b1edbc 117 #define REG_PORT_DIRSET2 (*(RwReg *)0x41004508U) /**< \brief (PORT) Data Direction Set 2 */
AnnaBridge 171:3a7713b1edbc 118 #define REG_PORT_DIRTGL2 (*(RwReg *)0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */
AnnaBridge 171:3a7713b1edbc 119 #define REG_PORT_OUT2 (*(RwReg *)0x41004510U) /**< \brief (PORT) Data Output Value 2 */
AnnaBridge 171:3a7713b1edbc 120 #define REG_PORT_OUTCLR2 (*(RwReg *)0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */
AnnaBridge 171:3a7713b1edbc 121 #define REG_PORT_OUTSET2 (*(RwReg *)0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */
AnnaBridge 171:3a7713b1edbc 122 #define REG_PORT_OUTTGL2 (*(RwReg *)0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */
AnnaBridge 171:3a7713b1edbc 123 #define REG_PORT_IN2 (*(RoReg *)0x41004520U) /**< \brief (PORT) Data Input Value 2 */
AnnaBridge 171:3a7713b1edbc 124 #define REG_PORT_CTRL2 (*(RwReg *)0x41004524U) /**< \brief (PORT) Control 2 */
AnnaBridge 171:3a7713b1edbc 125 #define REG_PORT_WRCONFIG2 (*(WoReg *)0x41004528U) /**< \brief (PORT) Write Configuration 2 */
AnnaBridge 171:3a7713b1edbc 126 #define REG_PORT_PMUX2 (*(RwReg *)0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */
AnnaBridge 171:3a7713b1edbc 127 #define REG_PORT_PINCFG2 (*(RwReg *)0x41004540U) /**< \brief (PORT) Pin Configuration 2 */
AnnaBridge 171:3a7713b1edbc 128 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /* ========== Instance parameters for PORT peripheral ========== */
AnnaBridge 171:3a7713b1edbc 131 #define PORT_BITS 84 // Number of PORT pins
AnnaBridge 171:3a7713b1edbc 132 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
AnnaBridge 171:3a7713b1edbc 133 #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
AnnaBridge 171:3a7713b1edbc 134 #define PORT_DRVSTR 1 // DRVSTR supported
AnnaBridge 171:3a7713b1edbc 135 #define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
AnnaBridge 171:3a7713b1edbc 136 #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
AnnaBridge 171:3a7713b1edbc 137 #define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
AnnaBridge 171:3a7713b1edbc 138 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
AnnaBridge 171:3a7713b1edbc 139 #define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
AnnaBridge 171:3a7713b1edbc 140 #define PORT_ODRAIN 0 // ODRAIN supported
AnnaBridge 171:3a7713b1edbc 141 #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
AnnaBridge 171:3a7713b1edbc 142 #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
AnnaBridge 171:3a7713b1edbc 143 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
AnnaBridge 171:3a7713b1edbc 144 #define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
AnnaBridge 171:3a7713b1edbc 145 #define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
AnnaBridge 171:3a7713b1edbc 146 #define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
AnnaBridge 171:3a7713b1edbc 147 #define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
AnnaBridge 171:3a7713b1edbc 148 #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
AnnaBridge 171:3a7713b1edbc 149 #define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
AnnaBridge 171:3a7713b1edbc 150 #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
AnnaBridge 171:3a7713b1edbc 151 #define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
AnnaBridge 171:3a7713b1edbc 152 #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
AnnaBridge 171:3a7713b1edbc 153 #define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
AnnaBridge 171:3a7713b1edbc 154 #define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
AnnaBridge 171:3a7713b1edbc 155 #define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
AnnaBridge 171:3a7713b1edbc 156 #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
AnnaBridge 171:3a7713b1edbc 157 #define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
AnnaBridge 171:3a7713b1edbc 158 #define PORT_SLEWLIM 0 // SLEWLIM supported
AnnaBridge 171:3a7713b1edbc 159 #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
AnnaBridge 171:3a7713b1edbc 160 #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 #endif /* _SAMR21_PORT_INSTANCE_ */