mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/ins_dmac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
| AnnaBridge | 171:3a7713b1edbc | 3 | * |
| AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for DMAC |
| AnnaBridge | 171:3a7713b1edbc | 5 | * |
| AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2015 Atmel Corporation. All rights reserved. |
| AnnaBridge | 171:3a7713b1edbc | 7 | * |
| AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
| AnnaBridge | 171:3a7713b1edbc | 11 | * |
| AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
| AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 14 | * |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 24 | * |
| AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
| AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 39 | * |
| AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
| AnnaBridge | 171:3a7713b1edbc | 41 | * |
| AnnaBridge | 171:3a7713b1edbc | 42 | */ |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | #ifndef _SAMR21_DMAC_INSTANCE_ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #define _SAMR21_DMAC_INSTANCE_ |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /* ========== Register definition for DMAC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| AnnaBridge | 171:3a7713b1edbc | 49 | #define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | #define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | #define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #else |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | /* ========== Instance parameters for DMAC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define DMAC_CH_BITS 4 // Number of bits to select channel |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define DMAC_CH_NUM 12 // Number of channels |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define DMAC_CLK_AHB_ID 5 // AHB clock index |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define DMAC_EVIN_NUM 4 // Number of input events |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define DMAC_EVOUT_NUM 4 // Number of output events |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define DMAC_LVL_BITS 2 // Number of bit to select level priority |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define DMAC_LVL_NUM 4 // Enable priority level number |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define DMAC_TRIG_BITS 6 // Number of bits to select trigger source |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define DMAC_TRIG_NUM 45 // Number of peripheral triggers |
| AnnaBridge | 171:3a7713b1edbc | 108 | |
| AnnaBridge | 171:3a7713b1edbc | 109 | #endif /* _SAMR21_DMAC_INSTANCE_ */ |
