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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/ins_adc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
| AnnaBridge | 171:3a7713b1edbc | 3 | * |
| AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for ADC |
| AnnaBridge | 171:3a7713b1edbc | 5 | * |
| AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2015 Atmel Corporation. All rights reserved. |
| AnnaBridge | 171:3a7713b1edbc | 7 | * |
| AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
| AnnaBridge | 171:3a7713b1edbc | 11 | * |
| AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
| AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 14 | * |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 24 | * |
| AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
| AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 39 | * |
| AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
| AnnaBridge | 171:3a7713b1edbc | 41 | * |
| AnnaBridge | 171:3a7713b1edbc | 42 | */ |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | #ifndef _SAMR21_ADC_INSTANCE_ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #define _SAMR21_ADC_INSTANCE_ |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /* ========== Register definition for ADC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| AnnaBridge | 171:3a7713b1edbc | 49 | #define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | #define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | #define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | #else |
| AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | /* ========== Instance parameters for ADC peripheral ========== */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define ADC_EXTCHANNEL_MSB 19 // Number of external channels |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define ADC_GCLK_ID 30 // Index of Generic Clock |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define ADC_RESULT_MSB 15 // Size of Result |
| AnnaBridge | 171:3a7713b1edbc | 98 | |
| AnnaBridge | 171:3a7713b1edbc | 99 | #endif /* _SAMR21_ADC_INSTANCE_ */ |
