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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_tcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for TCC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_TCC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_TCC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR TCC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_TCC Timer Counter Control */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define TCC_U2213
AnnaBridge 171:3a7713b1edbc 54 #define REV_TCC 0x101
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint32_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint32_t :3; /*!< bit: 2.. 4 Reserved */
AnnaBridge 171:3a7713b1edbc 63 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
AnnaBridge 171:3a7713b1edbc 64 uint32_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 65 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
AnnaBridge 171:3a7713b1edbc 66 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
AnnaBridge 171:3a7713b1edbc 67 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
AnnaBridge 171:3a7713b1edbc 68 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
AnnaBridge 171:3a7713b1edbc 69 uint32_t :9; /*!< bit: 15..23 Reserved */
AnnaBridge 171:3a7713b1edbc 70 uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 71 uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 72 uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
AnnaBridge 171:3a7713b1edbc 73 uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
AnnaBridge 171:3a7713b1edbc 74 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 75 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 76 struct {
AnnaBridge 171:3a7713b1edbc 77 uint32_t :24; /*!< bit: 0..23 Reserved */
AnnaBridge 171:3a7713b1edbc 78 uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
AnnaBridge 171:3a7713b1edbc 79 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 80 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 81 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 82 } TCC_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 #define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
AnnaBridge 171:3a7713b1edbc 86 #define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 #define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 89 #define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 91 #define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 92 #define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
AnnaBridge 171:3a7713b1edbc 93 #define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
AnnaBridge 171:3a7713b1edbc 94 #define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
AnnaBridge 171:3a7713b1edbc 95 #define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
AnnaBridge 171:3a7713b1edbc 96 #define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
AnnaBridge 171:3a7713b1edbc 97 #define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
AnnaBridge 171:3a7713b1edbc 98 #define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
AnnaBridge 171:3a7713b1edbc 99 #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
AnnaBridge 171:3a7713b1edbc 100 #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
AnnaBridge 171:3a7713b1edbc 101 #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
AnnaBridge 171:3a7713b1edbc 102 #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
AnnaBridge 171:3a7713b1edbc 103 #define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
AnnaBridge 171:3a7713b1edbc 104 #define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 105 #define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 106 #define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
AnnaBridge 171:3a7713b1edbc 107 #define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
AnnaBridge 171:3a7713b1edbc 108 #define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
AnnaBridge 171:3a7713b1edbc 109 #define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */
AnnaBridge 171:3a7713b1edbc 110 #define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */
AnnaBridge 171:3a7713b1edbc 111 #define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */
AnnaBridge 171:3a7713b1edbc 112 #define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */
AnnaBridge 171:3a7713b1edbc 113 #define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */
AnnaBridge 171:3a7713b1edbc 114 #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 116 #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 117 #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 118 #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 119 #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 121 #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 122 #define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
AnnaBridge 171:3a7713b1edbc 123 #define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 124 #define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
AnnaBridge 171:3a7713b1edbc 125 #define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 126 #define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
AnnaBridge 171:3a7713b1edbc 127 #define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
AnnaBridge 171:3a7713b1edbc 128 #define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
AnnaBridge 171:3a7713b1edbc 129 #define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
AnnaBridge 171:3a7713b1edbc 130 #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 131 #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 132 #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 133 #define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
AnnaBridge 171:3a7713b1edbc 134 #define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos)
AnnaBridge 171:3a7713b1edbc 135 #define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 136 #define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
AnnaBridge 171:3a7713b1edbc 137 #define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 138 #define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
AnnaBridge 171:3a7713b1edbc 139 #define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
AnnaBridge 171:3a7713b1edbc 140 #define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
AnnaBridge 171:3a7713b1edbc 142 #define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
AnnaBridge 171:3a7713b1edbc 144 #define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
AnnaBridge 171:3a7713b1edbc 145 #define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
AnnaBridge 171:3a7713b1edbc 146 #define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
AnnaBridge 171:3a7713b1edbc 149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 150 typedef union {
AnnaBridge 171:3a7713b1edbc 151 struct {
AnnaBridge 171:3a7713b1edbc 152 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
AnnaBridge 171:3a7713b1edbc 153 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
AnnaBridge 171:3a7713b1edbc 154 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
AnnaBridge 171:3a7713b1edbc 155 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
AnnaBridge 171:3a7713b1edbc 156 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
AnnaBridge 171:3a7713b1edbc 157 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 158 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 159 } TCC_CTRLBCLR_Type;
AnnaBridge 171:3a7713b1edbc 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 #define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
AnnaBridge 171:3a7713b1edbc 163 #define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 #define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
AnnaBridge 171:3a7713b1edbc 166 #define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 167 #define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
AnnaBridge 171:3a7713b1edbc 168 #define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
AnnaBridge 171:3a7713b1edbc 169 #define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
AnnaBridge 171:3a7713b1edbc 170 #define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
AnnaBridge 171:3a7713b1edbc 171 #define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
AnnaBridge 171:3a7713b1edbc 172 #define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 173 #define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
AnnaBridge 171:3a7713b1edbc 174 #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
AnnaBridge 171:3a7713b1edbc 175 #define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
AnnaBridge 171:3a7713b1edbc 176 #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
AnnaBridge 171:3a7713b1edbc 177 #define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
AnnaBridge 171:3a7713b1edbc 178 #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 179 #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 180 #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 181 #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 182 #define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
AnnaBridge 171:3a7713b1edbc 183 #define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 184 #define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 185 #define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
AnnaBridge 171:3a7713b1edbc 186 #define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
AnnaBridge 171:3a7713b1edbc 187 #define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
AnnaBridge 171:3a7713b1edbc 188 #define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
AnnaBridge 171:3a7713b1edbc 189 #define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
AnnaBridge 171:3a7713b1edbc 190 #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 192 #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 193 #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 194 #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 195 #define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
AnnaBridge 171:3a7713b1edbc 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 199 typedef union {
AnnaBridge 171:3a7713b1edbc 200 struct {
AnnaBridge 171:3a7713b1edbc 201 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
AnnaBridge 171:3a7713b1edbc 202 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
AnnaBridge 171:3a7713b1edbc 203 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
AnnaBridge 171:3a7713b1edbc 204 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
AnnaBridge 171:3a7713b1edbc 205 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
AnnaBridge 171:3a7713b1edbc 206 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 207 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 208 } TCC_CTRLBSET_Type;
AnnaBridge 171:3a7713b1edbc 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 #define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
AnnaBridge 171:3a7713b1edbc 212 #define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 #define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
AnnaBridge 171:3a7713b1edbc 215 #define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 216 #define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
AnnaBridge 171:3a7713b1edbc 217 #define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos)
AnnaBridge 171:3a7713b1edbc 218 #define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
AnnaBridge 171:3a7713b1edbc 219 #define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
AnnaBridge 171:3a7713b1edbc 220 #define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
AnnaBridge 171:3a7713b1edbc 221 #define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 222 #define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
AnnaBridge 171:3a7713b1edbc 223 #define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
AnnaBridge 171:3a7713b1edbc 224 #define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
AnnaBridge 171:3a7713b1edbc 225 #define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
AnnaBridge 171:3a7713b1edbc 226 #define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
AnnaBridge 171:3a7713b1edbc 227 #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 229 #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 230 #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
AnnaBridge 171:3a7713b1edbc 231 #define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
AnnaBridge 171:3a7713b1edbc 232 #define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 233 #define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 234 #define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
AnnaBridge 171:3a7713b1edbc 235 #define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
AnnaBridge 171:3a7713b1edbc 236 #define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
AnnaBridge 171:3a7713b1edbc 237 #define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
AnnaBridge 171:3a7713b1edbc 238 #define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
AnnaBridge 171:3a7713b1edbc 239 #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 240 #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 241 #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 242 #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 243 #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 244 #define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
AnnaBridge 171:3a7713b1edbc 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 248 typedef union {
AnnaBridge 171:3a7713b1edbc 249 struct {
AnnaBridge 171:3a7713b1edbc 250 uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
AnnaBridge 171:3a7713b1edbc 251 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
AnnaBridge 171:3a7713b1edbc 252 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
AnnaBridge 171:3a7713b1edbc 253 uint32_t STATUS:1; /*!< bit: 3 Status Busy */
AnnaBridge 171:3a7713b1edbc 254 uint32_t COUNT:1; /*!< bit: 4 Count Busy */
AnnaBridge 171:3a7713b1edbc 255 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
AnnaBridge 171:3a7713b1edbc 256 uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
AnnaBridge 171:3a7713b1edbc 257 uint32_t PER:1; /*!< bit: 7 Period busy */
AnnaBridge 171:3a7713b1edbc 258 uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
AnnaBridge 171:3a7713b1edbc 259 uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
AnnaBridge 171:3a7713b1edbc 260 uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
AnnaBridge 171:3a7713b1edbc 261 uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
AnnaBridge 171:3a7713b1edbc 262 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 263 uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
AnnaBridge 171:3a7713b1edbc 264 uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
AnnaBridge 171:3a7713b1edbc 265 uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
AnnaBridge 171:3a7713b1edbc 266 uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
AnnaBridge 171:3a7713b1edbc 267 uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
AnnaBridge 171:3a7713b1edbc 268 uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
AnnaBridge 171:3a7713b1edbc 269 uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
AnnaBridge 171:3a7713b1edbc 270 uint32_t :9; /*!< bit: 23..31 Reserved */
AnnaBridge 171:3a7713b1edbc 271 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 272 struct {
AnnaBridge 171:3a7713b1edbc 273 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 274 uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
AnnaBridge 171:3a7713b1edbc 275 uint32_t :7; /*!< bit: 12..18 Reserved */
AnnaBridge 171:3a7713b1edbc 276 uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
AnnaBridge 171:3a7713b1edbc 277 uint32_t :9; /*!< bit: 23..31 Reserved */
AnnaBridge 171:3a7713b1edbc 278 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 279 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 280 } TCC_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 284 #define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 #define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
AnnaBridge 171:3a7713b1edbc 287 #define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 288 #define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
AnnaBridge 171:3a7713b1edbc 289 #define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 290 #define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
AnnaBridge 171:3a7713b1edbc 291 #define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
AnnaBridge 171:3a7713b1edbc 292 #define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
AnnaBridge 171:3a7713b1edbc 293 #define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
AnnaBridge 171:3a7713b1edbc 294 #define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
AnnaBridge 171:3a7713b1edbc 295 #define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 296 #define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
AnnaBridge 171:3a7713b1edbc 297 #define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos)
AnnaBridge 171:3a7713b1edbc 298 #define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
AnnaBridge 171:3a7713b1edbc 299 #define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
AnnaBridge 171:3a7713b1edbc 300 #define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
AnnaBridge 171:3a7713b1edbc 301 #define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos)
AnnaBridge 171:3a7713b1edbc 302 #define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
AnnaBridge 171:3a7713b1edbc 303 #define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
AnnaBridge 171:3a7713b1edbc 305 #define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
AnnaBridge 171:3a7713b1edbc 306 #define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
AnnaBridge 171:3a7713b1edbc 307 #define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
AnnaBridge 171:3a7713b1edbc 309 #define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
AnnaBridge 171:3a7713b1edbc 310 #define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
AnnaBridge 171:3a7713b1edbc 311 #define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
AnnaBridge 171:3a7713b1edbc 312 #define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
AnnaBridge 171:3a7713b1edbc 313 #define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
AnnaBridge 171:3a7713b1edbc 314 #define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
AnnaBridge 171:3a7713b1edbc 315 #define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
AnnaBridge 171:3a7713b1edbc 316 #define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
AnnaBridge 171:3a7713b1edbc 317 #define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
AnnaBridge 171:3a7713b1edbc 318 #define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos)
AnnaBridge 171:3a7713b1edbc 319 #define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
AnnaBridge 171:3a7713b1edbc 320 #define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
AnnaBridge 171:3a7713b1edbc 321 #define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
AnnaBridge 171:3a7713b1edbc 322 #define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
AnnaBridge 171:3a7713b1edbc 323 #define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
AnnaBridge 171:3a7713b1edbc 324 #define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
AnnaBridge 171:3a7713b1edbc 325 #define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
AnnaBridge 171:3a7713b1edbc 326 #define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
AnnaBridge 171:3a7713b1edbc 328 #define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
AnnaBridge 171:3a7713b1edbc 329 #define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
AnnaBridge 171:3a7713b1edbc 330 #define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
AnnaBridge 171:3a7713b1edbc 333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 334 typedef union {
AnnaBridge 171:3a7713b1edbc 335 struct {
AnnaBridge 171:3a7713b1edbc 336 uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
AnnaBridge 171:3a7713b1edbc 337 uint32_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 338 uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
AnnaBridge 171:3a7713b1edbc 339 uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
AnnaBridge 171:3a7713b1edbc 340 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
AnnaBridge 171:3a7713b1edbc 341 uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
AnnaBridge 171:3a7713b1edbc 342 uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
AnnaBridge 171:3a7713b1edbc 343 uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
AnnaBridge 171:3a7713b1edbc 344 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
AnnaBridge 171:3a7713b1edbc 345 uint32_t :1; /*!< bit: 15 Reserved */
AnnaBridge 171:3a7713b1edbc 346 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
AnnaBridge 171:3a7713b1edbc 347 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
AnnaBridge 171:3a7713b1edbc 348 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 349 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 350 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 351 } TCC_FCTRLA_Type;
AnnaBridge 171:3a7713b1edbc 352 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
AnnaBridge 171:3a7713b1edbc 355 #define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 #define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
AnnaBridge 171:3a7713b1edbc 358 #define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 359 #define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
AnnaBridge 171:3a7713b1edbc 360 #define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
AnnaBridge 171:3a7713b1edbc 361 #define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
AnnaBridge 171:3a7713b1edbc 362 #define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
AnnaBridge 171:3a7713b1edbc 363 #define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
AnnaBridge 171:3a7713b1edbc 364 #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 365 #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 366 #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 367 #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 368 #define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
AnnaBridge 171:3a7713b1edbc 369 #define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos)
AnnaBridge 171:3a7713b1edbc 370 #define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
AnnaBridge 171:3a7713b1edbc 371 #define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
AnnaBridge 171:3a7713b1edbc 372 #define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
AnnaBridge 171:3a7713b1edbc 373 #define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 374 #define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
AnnaBridge 171:3a7713b1edbc 375 #define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
AnnaBridge 171:3a7713b1edbc 376 #define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
AnnaBridge 171:3a7713b1edbc 377 #define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
AnnaBridge 171:3a7713b1edbc 378 #define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
AnnaBridge 171:3a7713b1edbc 379 #define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 380 #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 381 #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 382 #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 383 #define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
AnnaBridge 171:3a7713b1edbc 384 #define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
AnnaBridge 171:3a7713b1edbc 385 #define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
AnnaBridge 171:3a7713b1edbc 386 #define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
AnnaBridge 171:3a7713b1edbc 388 #define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
AnnaBridge 171:3a7713b1edbc 389 #define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
AnnaBridge 171:3a7713b1edbc 390 #define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
AnnaBridge 171:3a7713b1edbc 391 #define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */
AnnaBridge 171:3a7713b1edbc 392 #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 393 #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 394 #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 395 #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 396 #define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
AnnaBridge 171:3a7713b1edbc 397 #define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 398 #define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
AnnaBridge 171:3a7713b1edbc 399 #define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
AnnaBridge 171:3a7713b1edbc 400 #define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
AnnaBridge 171:3a7713b1edbc 401 #define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
AnnaBridge 171:3a7713b1edbc 402 #define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
AnnaBridge 171:3a7713b1edbc 403 #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 404 #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 405 #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 406 #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 407 #define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
AnnaBridge 171:3a7713b1edbc 408 #define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 409 #define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
AnnaBridge 171:3a7713b1edbc 410 #define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
AnnaBridge 171:3a7713b1edbc 411 #define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
AnnaBridge 171:3a7713b1edbc 412 #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
AnnaBridge 171:3a7713b1edbc 413 #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */
AnnaBridge 171:3a7713b1edbc 414 #define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
AnnaBridge 171:3a7713b1edbc 415 #define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
AnnaBridge 171:3a7713b1edbc 416 #define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
AnnaBridge 171:3a7713b1edbc 417 #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 418 #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 419 #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 420 #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 421 #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 422 #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 423 #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 424 #define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
AnnaBridge 171:3a7713b1edbc 425 #define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
AnnaBridge 171:3a7713b1edbc 426 #define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
AnnaBridge 171:3a7713b1edbc 427 #define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
AnnaBridge 171:3a7713b1edbc 428 #define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
AnnaBridge 171:3a7713b1edbc 429 #define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
AnnaBridge 171:3a7713b1edbc 430 #define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
AnnaBridge 171:3a7713b1edbc 433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 434 typedef union {
AnnaBridge 171:3a7713b1edbc 435 struct {
AnnaBridge 171:3a7713b1edbc 436 uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
AnnaBridge 171:3a7713b1edbc 437 uint32_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 438 uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
AnnaBridge 171:3a7713b1edbc 439 uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
AnnaBridge 171:3a7713b1edbc 440 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
AnnaBridge 171:3a7713b1edbc 441 uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
AnnaBridge 171:3a7713b1edbc 442 uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
AnnaBridge 171:3a7713b1edbc 443 uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
AnnaBridge 171:3a7713b1edbc 444 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
AnnaBridge 171:3a7713b1edbc 445 uint32_t :1; /*!< bit: 15 Reserved */
AnnaBridge 171:3a7713b1edbc 446 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
AnnaBridge 171:3a7713b1edbc 447 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
AnnaBridge 171:3a7713b1edbc 448 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 449 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 450 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 451 } TCC_FCTRLB_Type;
AnnaBridge 171:3a7713b1edbc 452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 #define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
AnnaBridge 171:3a7713b1edbc 455 #define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
AnnaBridge 171:3a7713b1edbc 458 #define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 459 #define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
AnnaBridge 171:3a7713b1edbc 460 #define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
AnnaBridge 171:3a7713b1edbc 461 #define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
AnnaBridge 171:3a7713b1edbc 462 #define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
AnnaBridge 171:3a7713b1edbc 463 #define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
AnnaBridge 171:3a7713b1edbc 464 #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 465 #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 466 #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 467 #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
AnnaBridge 171:3a7713b1edbc 468 #define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
AnnaBridge 171:3a7713b1edbc 469 #define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos)
AnnaBridge 171:3a7713b1edbc 470 #define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
AnnaBridge 171:3a7713b1edbc 471 #define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
AnnaBridge 171:3a7713b1edbc 472 #define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
AnnaBridge 171:3a7713b1edbc 473 #define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 474 #define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
AnnaBridge 171:3a7713b1edbc 475 #define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
AnnaBridge 171:3a7713b1edbc 476 #define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
AnnaBridge 171:3a7713b1edbc 477 #define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
AnnaBridge 171:3a7713b1edbc 478 #define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
AnnaBridge 171:3a7713b1edbc 479 #define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 480 #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 481 #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 482 #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
AnnaBridge 171:3a7713b1edbc 483 #define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
AnnaBridge 171:3a7713b1edbc 484 #define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
AnnaBridge 171:3a7713b1edbc 485 #define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
AnnaBridge 171:3a7713b1edbc 486 #define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 487 #define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
AnnaBridge 171:3a7713b1edbc 488 #define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
AnnaBridge 171:3a7713b1edbc 489 #define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
AnnaBridge 171:3a7713b1edbc 490 #define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
AnnaBridge 171:3a7713b1edbc 491 #define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */
AnnaBridge 171:3a7713b1edbc 492 #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 493 #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 494 #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 495 #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
AnnaBridge 171:3a7713b1edbc 496 #define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
AnnaBridge 171:3a7713b1edbc 497 #define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 498 #define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
AnnaBridge 171:3a7713b1edbc 499 #define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
AnnaBridge 171:3a7713b1edbc 500 #define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
AnnaBridge 171:3a7713b1edbc 501 #define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
AnnaBridge 171:3a7713b1edbc 502 #define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
AnnaBridge 171:3a7713b1edbc 503 #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 504 #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 505 #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 506 #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
AnnaBridge 171:3a7713b1edbc 507 #define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
AnnaBridge 171:3a7713b1edbc 508 #define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 509 #define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
AnnaBridge 171:3a7713b1edbc 510 #define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
AnnaBridge 171:3a7713b1edbc 511 #define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
AnnaBridge 171:3a7713b1edbc 512 #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
AnnaBridge 171:3a7713b1edbc 513 #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */
AnnaBridge 171:3a7713b1edbc 514 #define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
AnnaBridge 171:3a7713b1edbc 515 #define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
AnnaBridge 171:3a7713b1edbc 516 #define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
AnnaBridge 171:3a7713b1edbc 517 #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 518 #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 519 #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 520 #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 521 #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 522 #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 523 #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
AnnaBridge 171:3a7713b1edbc 524 #define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
AnnaBridge 171:3a7713b1edbc 525 #define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
AnnaBridge 171:3a7713b1edbc 526 #define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
AnnaBridge 171:3a7713b1edbc 527 #define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
AnnaBridge 171:3a7713b1edbc 528 #define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
AnnaBridge 171:3a7713b1edbc 529 #define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
AnnaBridge 171:3a7713b1edbc 530 #define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
AnnaBridge 171:3a7713b1edbc 533 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 534 typedef union {
AnnaBridge 171:3a7713b1edbc 535 struct {
AnnaBridge 171:3a7713b1edbc 536 uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
AnnaBridge 171:3a7713b1edbc 537 uint32_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 538 uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
AnnaBridge 171:3a7713b1edbc 539 uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
AnnaBridge 171:3a7713b1edbc 540 uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
AnnaBridge 171:3a7713b1edbc 541 uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
AnnaBridge 171:3a7713b1edbc 542 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 543 uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
AnnaBridge 171:3a7713b1edbc 544 uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
AnnaBridge 171:3a7713b1edbc 545 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 546 struct {
AnnaBridge 171:3a7713b1edbc 547 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 548 uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
AnnaBridge 171:3a7713b1edbc 549 uint32_t :20; /*!< bit: 12..31 Reserved */
AnnaBridge 171:3a7713b1edbc 550 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 551 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 552 } TCC_WEXCTRL_Type;
AnnaBridge 171:3a7713b1edbc 553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 #define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
AnnaBridge 171:3a7713b1edbc 556 #define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
AnnaBridge 171:3a7713b1edbc 559 #define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
AnnaBridge 171:3a7713b1edbc 561 #define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
AnnaBridge 171:3a7713b1edbc 562 #define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
AnnaBridge 171:3a7713b1edbc 563 #define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
AnnaBridge 171:3a7713b1edbc 564 #define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
AnnaBridge 171:3a7713b1edbc 565 #define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
AnnaBridge 171:3a7713b1edbc 566 #define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
AnnaBridge 171:3a7713b1edbc 567 #define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
AnnaBridge 171:3a7713b1edbc 568 #define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
AnnaBridge 171:3a7713b1edbc 569 #define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
AnnaBridge 171:3a7713b1edbc 570 #define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
AnnaBridge 171:3a7713b1edbc 571 #define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
AnnaBridge 171:3a7713b1edbc 572 #define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
AnnaBridge 171:3a7713b1edbc 573 #define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
AnnaBridge 171:3a7713b1edbc 574 #define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
AnnaBridge 171:3a7713b1edbc 575 #define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
AnnaBridge 171:3a7713b1edbc 576 #define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
AnnaBridge 171:3a7713b1edbc 577 #define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
AnnaBridge 171:3a7713b1edbc 578 #define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
AnnaBridge 171:3a7713b1edbc 581 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 582 typedef union {
AnnaBridge 171:3a7713b1edbc 583 struct {
AnnaBridge 171:3a7713b1edbc 584 uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 585 uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 586 uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 587 uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 588 uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 589 uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 590 uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 591 uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 592 uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
AnnaBridge 171:3a7713b1edbc 593 uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
AnnaBridge 171:3a7713b1edbc 594 uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
AnnaBridge 171:3a7713b1edbc 595 uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
AnnaBridge 171:3a7713b1edbc 596 uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
AnnaBridge 171:3a7713b1edbc 597 uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
AnnaBridge 171:3a7713b1edbc 598 uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
AnnaBridge 171:3a7713b1edbc 599 uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
AnnaBridge 171:3a7713b1edbc 600 uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
AnnaBridge 171:3a7713b1edbc 601 uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
AnnaBridge 171:3a7713b1edbc 602 uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
AnnaBridge 171:3a7713b1edbc 603 uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
AnnaBridge 171:3a7713b1edbc 604 uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
AnnaBridge 171:3a7713b1edbc 605 uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
AnnaBridge 171:3a7713b1edbc 606 uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
AnnaBridge 171:3a7713b1edbc 607 uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
AnnaBridge 171:3a7713b1edbc 608 uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
AnnaBridge 171:3a7713b1edbc 609 uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
AnnaBridge 171:3a7713b1edbc 610 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 611 struct {
AnnaBridge 171:3a7713b1edbc 612 uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
AnnaBridge 171:3a7713b1edbc 613 uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
AnnaBridge 171:3a7713b1edbc 614 uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
AnnaBridge 171:3a7713b1edbc 615 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 616 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 617 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 618 } TCC_DRVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 619 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
AnnaBridge 171:3a7713b1edbc 622 #define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 #define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 625 #define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
AnnaBridge 171:3a7713b1edbc 626 #define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 627 #define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
AnnaBridge 171:3a7713b1edbc 628 #define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 629 #define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
AnnaBridge 171:3a7713b1edbc 630 #define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 631 #define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
AnnaBridge 171:3a7713b1edbc 632 #define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 633 #define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
AnnaBridge 171:3a7713b1edbc 634 #define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 635 #define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
AnnaBridge 171:3a7713b1edbc 636 #define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 637 #define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
AnnaBridge 171:3a7713b1edbc 638 #define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 639 #define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
AnnaBridge 171:3a7713b1edbc 640 #define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
AnnaBridge 171:3a7713b1edbc 641 #define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
AnnaBridge 171:3a7713b1edbc 642 #define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
AnnaBridge 171:3a7713b1edbc 643 #define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
AnnaBridge 171:3a7713b1edbc 644 #define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
AnnaBridge 171:3a7713b1edbc 645 #define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
AnnaBridge 171:3a7713b1edbc 646 #define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
AnnaBridge 171:3a7713b1edbc 647 #define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
AnnaBridge 171:3a7713b1edbc 648 #define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
AnnaBridge 171:3a7713b1edbc 649 #define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
AnnaBridge 171:3a7713b1edbc 650 #define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
AnnaBridge 171:3a7713b1edbc 651 #define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
AnnaBridge 171:3a7713b1edbc 652 #define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
AnnaBridge 171:3a7713b1edbc 653 #define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
AnnaBridge 171:3a7713b1edbc 654 #define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
AnnaBridge 171:3a7713b1edbc 655 #define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
AnnaBridge 171:3a7713b1edbc 656 #define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
AnnaBridge 171:3a7713b1edbc 657 #define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
AnnaBridge 171:3a7713b1edbc 658 #define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
AnnaBridge 171:3a7713b1edbc 659 #define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
AnnaBridge 171:3a7713b1edbc 660 #define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
AnnaBridge 171:3a7713b1edbc 661 #define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
AnnaBridge 171:3a7713b1edbc 662 #define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
AnnaBridge 171:3a7713b1edbc 663 #define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
AnnaBridge 171:3a7713b1edbc 664 #define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
AnnaBridge 171:3a7713b1edbc 665 #define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
AnnaBridge 171:3a7713b1edbc 666 #define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
AnnaBridge 171:3a7713b1edbc 667 #define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
AnnaBridge 171:3a7713b1edbc 668 #define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
AnnaBridge 171:3a7713b1edbc 669 #define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
AnnaBridge 171:3a7713b1edbc 670 #define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
AnnaBridge 171:3a7713b1edbc 671 #define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
AnnaBridge 171:3a7713b1edbc 672 #define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
AnnaBridge 171:3a7713b1edbc 673 #define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
AnnaBridge 171:3a7713b1edbc 674 #define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
AnnaBridge 171:3a7713b1edbc 675 #define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
AnnaBridge 171:3a7713b1edbc 676 #define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
AnnaBridge 171:3a7713b1edbc 677 #define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
AnnaBridge 171:3a7713b1edbc 678 #define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
AnnaBridge 171:3a7713b1edbc 679 #define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
AnnaBridge 171:3a7713b1edbc 680 #define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
AnnaBridge 171:3a7713b1edbc 681 #define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
AnnaBridge 171:3a7713b1edbc 682 #define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
AnnaBridge 171:3a7713b1edbc 683 #define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
AnnaBridge 171:3a7713b1edbc 684 #define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
AnnaBridge 171:3a7713b1edbc 685 #define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
AnnaBridge 171:3a7713b1edbc 686 #define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
AnnaBridge 171:3a7713b1edbc 687 #define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 691 typedef union {
AnnaBridge 171:3a7713b1edbc 692 struct {
AnnaBridge 171:3a7713b1edbc 693 uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
AnnaBridge 171:3a7713b1edbc 694 uint8_t :1; /*!< bit: 1 Reserved */
AnnaBridge 171:3a7713b1edbc 695 uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
AnnaBridge 171:3a7713b1edbc 696 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 697 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 698 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 699 } TCC_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 700 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 #define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
AnnaBridge 171:3a7713b1edbc 703 #define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 #define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
AnnaBridge 171:3a7713b1edbc 706 #define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
AnnaBridge 171:3a7713b1edbc 707 #define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
AnnaBridge 171:3a7713b1edbc 708 #define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
AnnaBridge 171:3a7713b1edbc 709 #define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
AnnaBridge 171:3a7713b1edbc 712 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 713 typedef union {
AnnaBridge 171:3a7713b1edbc 714 struct {
AnnaBridge 171:3a7713b1edbc 715 uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
AnnaBridge 171:3a7713b1edbc 716 uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
AnnaBridge 171:3a7713b1edbc 717 uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
AnnaBridge 171:3a7713b1edbc 718 uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
AnnaBridge 171:3a7713b1edbc 719 uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
AnnaBridge 171:3a7713b1edbc 720 uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
AnnaBridge 171:3a7713b1edbc 721 uint32_t :1; /*!< bit: 11 Reserved */
AnnaBridge 171:3a7713b1edbc 722 uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
AnnaBridge 171:3a7713b1edbc 723 uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
AnnaBridge 171:3a7713b1edbc 724 uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
AnnaBridge 171:3a7713b1edbc 725 uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
AnnaBridge 171:3a7713b1edbc 726 uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 727 uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 728 uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 729 uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 730 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 731 uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 732 uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 733 uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 734 uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 735 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 736 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 737 struct {
AnnaBridge 171:3a7713b1edbc 738 uint32_t :12; /*!< bit: 0..11 Reserved */
AnnaBridge 171:3a7713b1edbc 739 uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
AnnaBridge 171:3a7713b1edbc 740 uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
AnnaBridge 171:3a7713b1edbc 741 uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
AnnaBridge 171:3a7713b1edbc 742 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 743 uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 744 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 745 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 746 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 747 } TCC_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 748 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 749
AnnaBridge 171:3a7713b1edbc 750 #define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
AnnaBridge 171:3a7713b1edbc 751 #define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
AnnaBridge 171:3a7713b1edbc 752
AnnaBridge 171:3a7713b1edbc 753 #define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
AnnaBridge 171:3a7713b1edbc 754 #define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 755 #define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
AnnaBridge 171:3a7713b1edbc 756 #define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
AnnaBridge 171:3a7713b1edbc 757 #define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
AnnaBridge 171:3a7713b1edbc 758 #define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
AnnaBridge 171:3a7713b1edbc 759 #define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */
AnnaBridge 171:3a7713b1edbc 760 #define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */
AnnaBridge 171:3a7713b1edbc 761 #define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
AnnaBridge 171:3a7713b1edbc 762 #define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
AnnaBridge 171:3a7713b1edbc 763 #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 764 #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 765 #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 766 #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 767 #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 768 #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 769 #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
AnnaBridge 171:3a7713b1edbc 770 #define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
AnnaBridge 171:3a7713b1edbc 771 #define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 772 #define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
AnnaBridge 171:3a7713b1edbc 773 #define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
AnnaBridge 171:3a7713b1edbc 774 #define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
AnnaBridge 171:3a7713b1edbc 775 #define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
AnnaBridge 171:3a7713b1edbc 776 #define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */
AnnaBridge 171:3a7713b1edbc 777 #define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */
AnnaBridge 171:3a7713b1edbc 778 #define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
AnnaBridge 171:3a7713b1edbc 779 #define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
AnnaBridge 171:3a7713b1edbc 780 #define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
AnnaBridge 171:3a7713b1edbc 781 #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 782 #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 783 #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 784 #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 785 #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 786 #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 787 #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 788 #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
AnnaBridge 171:3a7713b1edbc 789 #define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
AnnaBridge 171:3a7713b1edbc 790 #define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
AnnaBridge 171:3a7713b1edbc 791 #define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
AnnaBridge 171:3a7713b1edbc 792 #define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
AnnaBridge 171:3a7713b1edbc 793 #define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
AnnaBridge 171:3a7713b1edbc 794 #define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
AnnaBridge 171:3a7713b1edbc 795 #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
AnnaBridge 171:3a7713b1edbc 796 #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
AnnaBridge 171:3a7713b1edbc 797 #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
AnnaBridge 171:3a7713b1edbc 798 #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
AnnaBridge 171:3a7713b1edbc 799 #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
AnnaBridge 171:3a7713b1edbc 800 #define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
AnnaBridge 171:3a7713b1edbc 801 #define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos)
AnnaBridge 171:3a7713b1edbc 802 #define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
AnnaBridge 171:3a7713b1edbc 803 #define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos)
AnnaBridge 171:3a7713b1edbc 804 #define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
AnnaBridge 171:3a7713b1edbc 805 #define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos)
AnnaBridge 171:3a7713b1edbc 806 #define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
AnnaBridge 171:3a7713b1edbc 807 #define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
AnnaBridge 171:3a7713b1edbc 808 #define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
AnnaBridge 171:3a7713b1edbc 809 #define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
AnnaBridge 171:3a7713b1edbc 810 #define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
AnnaBridge 171:3a7713b1edbc 811 #define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
AnnaBridge 171:3a7713b1edbc 812 #define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
AnnaBridge 171:3a7713b1edbc 813 #define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
AnnaBridge 171:3a7713b1edbc 814 #define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
AnnaBridge 171:3a7713b1edbc 815 #define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
AnnaBridge 171:3a7713b1edbc 816 #define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
AnnaBridge 171:3a7713b1edbc 817 #define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
AnnaBridge 171:3a7713b1edbc 818 #define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
AnnaBridge 171:3a7713b1edbc 819 #define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
AnnaBridge 171:3a7713b1edbc 820 #define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 821 #define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
AnnaBridge 171:3a7713b1edbc 822 #define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 823 #define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
AnnaBridge 171:3a7713b1edbc 824 #define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 825 #define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
AnnaBridge 171:3a7713b1edbc 826 #define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
AnnaBridge 171:3a7713b1edbc 827 #define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
AnnaBridge 171:3a7713b1edbc 828 #define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
AnnaBridge 171:3a7713b1edbc 829 #define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
AnnaBridge 171:3a7713b1edbc 830 #define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
AnnaBridge 171:3a7713b1edbc 831 #define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 832 #define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
AnnaBridge 171:3a7713b1edbc 833 #define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 834 #define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
AnnaBridge 171:3a7713b1edbc 835 #define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 836 #define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
AnnaBridge 171:3a7713b1edbc 837 #define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 838 #define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
AnnaBridge 171:3a7713b1edbc 839 #define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 840 #define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
AnnaBridge 171:3a7713b1edbc 841 #define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
AnnaBridge 171:3a7713b1edbc 842 #define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 843
AnnaBridge 171:3a7713b1edbc 844 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 845 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 846 typedef union {
AnnaBridge 171:3a7713b1edbc 847 struct {
AnnaBridge 171:3a7713b1edbc 848 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 849 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 850 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 851 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 852 uint32_t :7; /*!< bit: 4..10 Reserved */
AnnaBridge 171:3a7713b1edbc 853 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 854 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 855 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 856 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 857 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 858 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 859 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 860 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 861 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 862 uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 863 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 864 struct {
AnnaBridge 171:3a7713b1edbc 865 uint32_t :16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 866 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 867 uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 868 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 869 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 870 } TCC_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 871 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 872
AnnaBridge 171:3a7713b1edbc 873 #define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 874 #define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 875
AnnaBridge 171:3a7713b1edbc 876 #define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 877 #define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 878 #define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 879 #define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos)
AnnaBridge 171:3a7713b1edbc 880 #define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 881 #define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos)
AnnaBridge 171:3a7713b1edbc 882 #define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 883 #define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 884 #define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 885 #define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos)
AnnaBridge 171:3a7713b1edbc 886 #define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 887 #define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos)
AnnaBridge 171:3a7713b1edbc 888 #define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 889 #define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos)
AnnaBridge 171:3a7713b1edbc 890 #define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 891 #define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos)
AnnaBridge 171:3a7713b1edbc 892 #define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 893 #define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos)
AnnaBridge 171:3a7713b1edbc 894 #define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 895 #define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 896 #define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 897 #define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 898 #define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 899 #define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
AnnaBridge 171:3a7713b1edbc 900 #define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 901 #define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
AnnaBridge 171:3a7713b1edbc 902 #define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 903 #define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
AnnaBridge 171:3a7713b1edbc 904 #define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
AnnaBridge 171:3a7713b1edbc 905 #define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 906
AnnaBridge 171:3a7713b1edbc 907 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 908 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 909 typedef union {
AnnaBridge 171:3a7713b1edbc 910 struct {
AnnaBridge 171:3a7713b1edbc 911 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 912 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 913 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 914 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 915 uint32_t :7; /*!< bit: 4..10 Reserved */
AnnaBridge 171:3a7713b1edbc 916 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 917 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 918 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 919 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 920 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 921 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 922 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 923 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 924 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 925 uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 926 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 927 struct {
AnnaBridge 171:3a7713b1edbc 928 uint32_t :16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 929 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 930 uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 931 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 932 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 933 } TCC_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 934 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936 #define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 937 #define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 938
AnnaBridge 171:3a7713b1edbc 939 #define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 940 #define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 941 #define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 942 #define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos)
AnnaBridge 171:3a7713b1edbc 943 #define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 944 #define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos)
AnnaBridge 171:3a7713b1edbc 945 #define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 946 #define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 947 #define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 948 #define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos)
AnnaBridge 171:3a7713b1edbc 949 #define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 950 #define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos)
AnnaBridge 171:3a7713b1edbc 951 #define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 952 #define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos)
AnnaBridge 171:3a7713b1edbc 953 #define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 954 #define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos)
AnnaBridge 171:3a7713b1edbc 955 #define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 956 #define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos)
AnnaBridge 171:3a7713b1edbc 957 #define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 958 #define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 959 #define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 960 #define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 961 #define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 962 #define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
AnnaBridge 171:3a7713b1edbc 963 #define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 964 #define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
AnnaBridge 171:3a7713b1edbc 965 #define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 966 #define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
AnnaBridge 171:3a7713b1edbc 967 #define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
AnnaBridge 171:3a7713b1edbc 968 #define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 969
AnnaBridge 171:3a7713b1edbc 970 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 971 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 972 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 973 struct {
AnnaBridge 171:3a7713b1edbc 974 __I uint32_t OVF:1; /*!< bit: 0 Overflow */
AnnaBridge 171:3a7713b1edbc 975 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
AnnaBridge 171:3a7713b1edbc 976 __I uint32_t CNT:1; /*!< bit: 2 Counter */
AnnaBridge 171:3a7713b1edbc 977 __I uint32_t ERR:1; /*!< bit: 3 Error */
AnnaBridge 171:3a7713b1edbc 978 __I uint32_t :7; /*!< bit: 4..10 Reserved */
AnnaBridge 171:3a7713b1edbc 979 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
AnnaBridge 171:3a7713b1edbc 980 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
AnnaBridge 171:3a7713b1edbc 981 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
AnnaBridge 171:3a7713b1edbc 982 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
AnnaBridge 171:3a7713b1edbc 983 __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
AnnaBridge 171:3a7713b1edbc 984 __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
AnnaBridge 171:3a7713b1edbc 985 __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
AnnaBridge 171:3a7713b1edbc 986 __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
AnnaBridge 171:3a7713b1edbc 987 __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
AnnaBridge 171:3a7713b1edbc 988 __I uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 989 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 990 struct {
AnnaBridge 171:3a7713b1edbc 991 __I uint32_t :16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 992 __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
AnnaBridge 171:3a7713b1edbc 993 __I uint32_t :12; /*!< bit: 20..31 Reserved */
AnnaBridge 171:3a7713b1edbc 994 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 995 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 996 } TCC_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 997 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 998
AnnaBridge 171:3a7713b1edbc 999 #define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1000 #define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1001
AnnaBridge 171:3a7713b1edbc 1002 #define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
AnnaBridge 171:3a7713b1edbc 1003 #define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 1004 #define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
AnnaBridge 171:3a7713b1edbc 1005 #define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos)
AnnaBridge 171:3a7713b1edbc 1006 #define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
AnnaBridge 171:3a7713b1edbc 1007 #define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos)
AnnaBridge 171:3a7713b1edbc 1008 #define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
AnnaBridge 171:3a7713b1edbc 1009 #define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 1010 #define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
AnnaBridge 171:3a7713b1edbc 1011 #define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos)
AnnaBridge 171:3a7713b1edbc 1012 #define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
AnnaBridge 171:3a7713b1edbc 1013 #define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos)
AnnaBridge 171:3a7713b1edbc 1014 #define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
AnnaBridge 171:3a7713b1edbc 1015 #define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos)
AnnaBridge 171:3a7713b1edbc 1016 #define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
AnnaBridge 171:3a7713b1edbc 1017 #define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos)
AnnaBridge 171:3a7713b1edbc 1018 #define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
AnnaBridge 171:3a7713b1edbc 1019 #define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos)
AnnaBridge 171:3a7713b1edbc 1020 #define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
AnnaBridge 171:3a7713b1edbc 1021 #define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 1022 #define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
AnnaBridge 171:3a7713b1edbc 1023 #define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 1024 #define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
AnnaBridge 171:3a7713b1edbc 1025 #define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
AnnaBridge 171:3a7713b1edbc 1026 #define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
AnnaBridge 171:3a7713b1edbc 1027 #define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
AnnaBridge 171:3a7713b1edbc 1028 #define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
AnnaBridge 171:3a7713b1edbc 1029 #define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
AnnaBridge 171:3a7713b1edbc 1030 #define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
AnnaBridge 171:3a7713b1edbc 1031 #define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 1032
AnnaBridge 171:3a7713b1edbc 1033 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
AnnaBridge 171:3a7713b1edbc 1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1035 typedef union {
AnnaBridge 171:3a7713b1edbc 1036 struct {
AnnaBridge 171:3a7713b1edbc 1037 uint32_t STOP:1; /*!< bit: 0 Stop */
AnnaBridge 171:3a7713b1edbc 1038 uint32_t IDX:1; /*!< bit: 1 Ramp */
AnnaBridge 171:3a7713b1edbc 1039 uint32_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 1040 uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
AnnaBridge 171:3a7713b1edbc 1041 uint32_t SLAVE:1; /*!< bit: 4 Slave */
AnnaBridge 171:3a7713b1edbc 1042 uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1043 uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1044 uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1045 uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
AnnaBridge 171:3a7713b1edbc 1046 uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
AnnaBridge 171:3a7713b1edbc 1047 uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
AnnaBridge 171:3a7713b1edbc 1048 uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
AnnaBridge 171:3a7713b1edbc 1049 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
AnnaBridge 171:3a7713b1edbc 1050 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
AnnaBridge 171:3a7713b1edbc 1051 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
AnnaBridge 171:3a7713b1edbc 1052 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
AnnaBridge 171:3a7713b1edbc 1053 uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1054 uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1055 uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1056 uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1057 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1058 uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
AnnaBridge 171:3a7713b1edbc 1059 uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
AnnaBridge 171:3a7713b1edbc 1060 uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
AnnaBridge 171:3a7713b1edbc 1061 uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
AnnaBridge 171:3a7713b1edbc 1062 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1063 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1064 struct {
AnnaBridge 171:3a7713b1edbc 1065 uint32_t :16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1066 uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1067 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1068 uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
AnnaBridge 171:3a7713b1edbc 1069 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1070 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 1071 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1072 } TCC_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 1073 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1074
AnnaBridge 171:3a7713b1edbc 1075 #define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 1076 #define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 1077
AnnaBridge 171:3a7713b1edbc 1078 #define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
AnnaBridge 171:3a7713b1edbc 1079 #define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos)
AnnaBridge 171:3a7713b1edbc 1080 #define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
AnnaBridge 171:3a7713b1edbc 1081 #define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos)
AnnaBridge 171:3a7713b1edbc 1082 #define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
AnnaBridge 171:3a7713b1edbc 1083 #define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos)
AnnaBridge 171:3a7713b1edbc 1084 #define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
AnnaBridge 171:3a7713b1edbc 1085 #define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos)
AnnaBridge 171:3a7713b1edbc 1086 #define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1087 #define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos)
AnnaBridge 171:3a7713b1edbc 1088 #define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1089 #define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos)
AnnaBridge 171:3a7713b1edbc 1090 #define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1091 #define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos)
AnnaBridge 171:3a7713b1edbc 1092 #define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
AnnaBridge 171:3a7713b1edbc 1093 #define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos)
AnnaBridge 171:3a7713b1edbc 1094 #define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
AnnaBridge 171:3a7713b1edbc 1095 #define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos)
AnnaBridge 171:3a7713b1edbc 1096 #define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
AnnaBridge 171:3a7713b1edbc 1097 #define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos)
AnnaBridge 171:3a7713b1edbc 1098 #define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
AnnaBridge 171:3a7713b1edbc 1099 #define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos)
AnnaBridge 171:3a7713b1edbc 1100 #define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
AnnaBridge 171:3a7713b1edbc 1101 #define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos)
AnnaBridge 171:3a7713b1edbc 1102 #define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
AnnaBridge 171:3a7713b1edbc 1103 #define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos)
AnnaBridge 171:3a7713b1edbc 1104 #define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
AnnaBridge 171:3a7713b1edbc 1105 #define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos)
AnnaBridge 171:3a7713b1edbc 1106 #define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
AnnaBridge 171:3a7713b1edbc 1107 #define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos)
AnnaBridge 171:3a7713b1edbc 1108 #define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1109 #define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
AnnaBridge 171:3a7713b1edbc 1110 #define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1111 #define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
AnnaBridge 171:3a7713b1edbc 1112 #define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1113 #define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
AnnaBridge 171:3a7713b1edbc 1114 #define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1115 #define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
AnnaBridge 171:3a7713b1edbc 1116 #define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
AnnaBridge 171:3a7713b1edbc 1117 #define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
AnnaBridge 171:3a7713b1edbc 1118 #define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
AnnaBridge 171:3a7713b1edbc 1119 #define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
AnnaBridge 171:3a7713b1edbc 1120 #define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 1121 #define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
AnnaBridge 171:3a7713b1edbc 1122 #define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
AnnaBridge 171:3a7713b1edbc 1123 #define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
AnnaBridge 171:3a7713b1edbc 1124 #define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
AnnaBridge 171:3a7713b1edbc 1125 #define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
AnnaBridge 171:3a7713b1edbc 1126 #define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
AnnaBridge 171:3a7713b1edbc 1127 #define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
AnnaBridge 171:3a7713b1edbc 1128 #define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 1129 #define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 1130 #define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 1131
AnnaBridge 171:3a7713b1edbc 1132 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
AnnaBridge 171:3a7713b1edbc 1133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1134 typedef union {
AnnaBridge 171:3a7713b1edbc 1135 struct { // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1136 uint32_t :4; /*!< bit: 0.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 1137 uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
AnnaBridge 171:3a7713b1edbc 1138 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1139 } DITH4; /*!< Structure used for DITH4 */
AnnaBridge 171:3a7713b1edbc 1140 struct { // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1141 uint32_t :5; /*!< bit: 0.. 4 Reserved */
AnnaBridge 171:3a7713b1edbc 1142 uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
AnnaBridge 171:3a7713b1edbc 1143 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1144 } DITH5; /*!< Structure used for DITH5 */
AnnaBridge 171:3a7713b1edbc 1145 struct { // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1146 uint32_t :6; /*!< bit: 0.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 1147 uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
AnnaBridge 171:3a7713b1edbc 1148 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1149 } DITH6; /*!< Structure used for DITH6 */
AnnaBridge 171:3a7713b1edbc 1150 struct {
AnnaBridge 171:3a7713b1edbc 1151 uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
AnnaBridge 171:3a7713b1edbc 1152 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1153 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1154 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1155 } TCC_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 1156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1157
AnnaBridge 171:3a7713b1edbc 1158 #define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
AnnaBridge 171:3a7713b1edbc 1159 #define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1162 #define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
AnnaBridge 171:3a7713b1edbc 1163 #define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 1164 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 1165 #define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
AnnaBridge 171:3a7713b1edbc 1166
AnnaBridge 171:3a7713b1edbc 1167 // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1168 #define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
AnnaBridge 171:3a7713b1edbc 1169 #define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 1170 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 1171 #define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
AnnaBridge 171:3a7713b1edbc 1172
AnnaBridge 171:3a7713b1edbc 1173 // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1174 #define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
AnnaBridge 171:3a7713b1edbc 1175 #define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 1176 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 1177 #define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 #define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
AnnaBridge 171:3a7713b1edbc 1180 #define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 1181 #define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 1182 #define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 1183
AnnaBridge 171:3a7713b1edbc 1184 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
AnnaBridge 171:3a7713b1edbc 1185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1186 typedef union {
AnnaBridge 171:3a7713b1edbc 1187 struct {
AnnaBridge 171:3a7713b1edbc 1188 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 1189 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 1190 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 1191 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 1192 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 1193 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 1194 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 1195 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 1196 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
AnnaBridge 171:3a7713b1edbc 1197 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
AnnaBridge 171:3a7713b1edbc 1198 uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
AnnaBridge 171:3a7713b1edbc 1199 uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
AnnaBridge 171:3a7713b1edbc 1200 uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
AnnaBridge 171:3a7713b1edbc 1201 uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
AnnaBridge 171:3a7713b1edbc 1202 uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
AnnaBridge 171:3a7713b1edbc 1203 uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
AnnaBridge 171:3a7713b1edbc 1204 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1205 struct {
AnnaBridge 171:3a7713b1edbc 1206 uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
AnnaBridge 171:3a7713b1edbc 1207 uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
AnnaBridge 171:3a7713b1edbc 1208 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 1209 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1210 } TCC_PATT_Type;
AnnaBridge 171:3a7713b1edbc 1211 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213 #define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
AnnaBridge 171:3a7713b1edbc 1214 #define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */
AnnaBridge 171:3a7713b1edbc 1215
AnnaBridge 171:3a7713b1edbc 1216 #define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 1217 #define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
AnnaBridge 171:3a7713b1edbc 1218 #define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 1219 #define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
AnnaBridge 171:3a7713b1edbc 1220 #define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 1221 #define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
AnnaBridge 171:3a7713b1edbc 1222 #define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 1223 #define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
AnnaBridge 171:3a7713b1edbc 1224 #define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 1225 #define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
AnnaBridge 171:3a7713b1edbc 1226 #define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 1227 #define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
AnnaBridge 171:3a7713b1edbc 1228 #define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 1229 #define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
AnnaBridge 171:3a7713b1edbc 1230 #define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 1231 #define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
AnnaBridge 171:3a7713b1edbc 1232 #define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
AnnaBridge 171:3a7713b1edbc 1233 #define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
AnnaBridge 171:3a7713b1edbc 1234 #define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
AnnaBridge 171:3a7713b1edbc 1235 #define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
AnnaBridge 171:3a7713b1edbc 1236 #define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
AnnaBridge 171:3a7713b1edbc 1237 #define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
AnnaBridge 171:3a7713b1edbc 1238 #define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
AnnaBridge 171:3a7713b1edbc 1239 #define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
AnnaBridge 171:3a7713b1edbc 1240 #define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
AnnaBridge 171:3a7713b1edbc 1241 #define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
AnnaBridge 171:3a7713b1edbc 1242 #define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
AnnaBridge 171:3a7713b1edbc 1243 #define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
AnnaBridge 171:3a7713b1edbc 1244 #define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
AnnaBridge 171:3a7713b1edbc 1245 #define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
AnnaBridge 171:3a7713b1edbc 1246 #define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
AnnaBridge 171:3a7713b1edbc 1247 #define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
AnnaBridge 171:3a7713b1edbc 1248 #define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
AnnaBridge 171:3a7713b1edbc 1249 #define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
AnnaBridge 171:3a7713b1edbc 1250 #define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
AnnaBridge 171:3a7713b1edbc 1251 #define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
AnnaBridge 171:3a7713b1edbc 1252 #define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
AnnaBridge 171:3a7713b1edbc 1253 #define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
AnnaBridge 171:3a7713b1edbc 1254 #define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
AnnaBridge 171:3a7713b1edbc 1255
AnnaBridge 171:3a7713b1edbc 1256 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
AnnaBridge 171:3a7713b1edbc 1257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1258 typedef union {
AnnaBridge 171:3a7713b1edbc 1259 struct {
AnnaBridge 171:3a7713b1edbc 1260 uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
AnnaBridge 171:3a7713b1edbc 1261 uint32_t :1; /*!< bit: 3 Reserved */
AnnaBridge 171:3a7713b1edbc 1262 uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
AnnaBridge 171:3a7713b1edbc 1263 uint32_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 1264 uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
AnnaBridge 171:3a7713b1edbc 1265 uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 1266 uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 1267 uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
AnnaBridge 171:3a7713b1edbc 1268 uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
AnnaBridge 171:3a7713b1edbc 1269 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1270 uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
AnnaBridge 171:3a7713b1edbc 1271 uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
AnnaBridge 171:3a7713b1edbc 1272 uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
AnnaBridge 171:3a7713b1edbc 1273 uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
AnnaBridge 171:3a7713b1edbc 1274 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1275 uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
AnnaBridge 171:3a7713b1edbc 1276 uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
AnnaBridge 171:3a7713b1edbc 1277 uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
AnnaBridge 171:3a7713b1edbc 1278 uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
AnnaBridge 171:3a7713b1edbc 1279 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1280 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1281 struct {
AnnaBridge 171:3a7713b1edbc 1282 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 1283 uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
AnnaBridge 171:3a7713b1edbc 1284 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1285 uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
AnnaBridge 171:3a7713b1edbc 1286 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1287 uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
AnnaBridge 171:3a7713b1edbc 1288 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1289 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 1290 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1291 } TCC_WAVE_Type;
AnnaBridge 171:3a7713b1edbc 1292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1293
AnnaBridge 171:3a7713b1edbc 1294 #define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
AnnaBridge 171:3a7713b1edbc 1295 #define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
AnnaBridge 171:3a7713b1edbc 1296
AnnaBridge 171:3a7713b1edbc 1297 #define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
AnnaBridge 171:3a7713b1edbc 1298 #define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1299 #define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
AnnaBridge 171:3a7713b1edbc 1300 #define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
AnnaBridge 171:3a7713b1edbc 1301 #define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
AnnaBridge 171:3a7713b1edbc 1302 #define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
AnnaBridge 171:3a7713b1edbc 1303 #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */
AnnaBridge 171:3a7713b1edbc 1304 #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
AnnaBridge 171:3a7713b1edbc 1305 #define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
AnnaBridge 171:3a7713b1edbc 1306 #define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
AnnaBridge 171:3a7713b1edbc 1307 #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1308 #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1309 #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1310 #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1311 #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1312 #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1313 #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 1314 #define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
AnnaBridge 171:3a7713b1edbc 1315 #define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
AnnaBridge 171:3a7713b1edbc 1316 #define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
AnnaBridge 171:3a7713b1edbc 1317 #define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
AnnaBridge 171:3a7713b1edbc 1318 #define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
AnnaBridge 171:3a7713b1edbc 1319 #define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
AnnaBridge 171:3a7713b1edbc 1320 #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
AnnaBridge 171:3a7713b1edbc 1321 #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
AnnaBridge 171:3a7713b1edbc 1322 #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
AnnaBridge 171:3a7713b1edbc 1323 #define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
AnnaBridge 171:3a7713b1edbc 1324 #define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
AnnaBridge 171:3a7713b1edbc 1325 #define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 1326 #define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
AnnaBridge 171:3a7713b1edbc 1327 #define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 1328 #define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
AnnaBridge 171:3a7713b1edbc 1329 #define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
AnnaBridge 171:3a7713b1edbc 1330 #define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
AnnaBridge 171:3a7713b1edbc 1331 #define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
AnnaBridge 171:3a7713b1edbc 1332 #define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
AnnaBridge 171:3a7713b1edbc 1333 #define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
AnnaBridge 171:3a7713b1edbc 1334 #define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
AnnaBridge 171:3a7713b1edbc 1335 #define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
AnnaBridge 171:3a7713b1edbc 1336 #define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
AnnaBridge 171:3a7713b1edbc 1337 #define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
AnnaBridge 171:3a7713b1edbc 1338 #define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
AnnaBridge 171:3a7713b1edbc 1339 #define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
AnnaBridge 171:3a7713b1edbc 1340 #define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
AnnaBridge 171:3a7713b1edbc 1341 #define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
AnnaBridge 171:3a7713b1edbc 1342 #define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
AnnaBridge 171:3a7713b1edbc 1343 #define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
AnnaBridge 171:3a7713b1edbc 1344 #define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
AnnaBridge 171:3a7713b1edbc 1345 #define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
AnnaBridge 171:3a7713b1edbc 1346 #define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
AnnaBridge 171:3a7713b1edbc 1347 #define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
AnnaBridge 171:3a7713b1edbc 1348 #define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
AnnaBridge 171:3a7713b1edbc 1349 #define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
AnnaBridge 171:3a7713b1edbc 1350 #define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
AnnaBridge 171:3a7713b1edbc 1351 #define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
AnnaBridge 171:3a7713b1edbc 1352 #define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
AnnaBridge 171:3a7713b1edbc 1353 #define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
AnnaBridge 171:3a7713b1edbc 1354 #define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
AnnaBridge 171:3a7713b1edbc 1355 #define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
AnnaBridge 171:3a7713b1edbc 1356 #define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
AnnaBridge 171:3a7713b1edbc 1357 #define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
AnnaBridge 171:3a7713b1edbc 1358 #define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
AnnaBridge 171:3a7713b1edbc 1359
AnnaBridge 171:3a7713b1edbc 1360 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
AnnaBridge 171:3a7713b1edbc 1361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1362 typedef union {
AnnaBridge 171:3a7713b1edbc 1363 struct { // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1364 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1365 uint32_t PER:20; /*!< bit: 4..23 Period Value */
AnnaBridge 171:3a7713b1edbc 1366 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1367 } DITH4; /*!< Structure used for DITH4 */
AnnaBridge 171:3a7713b1edbc 1368 struct { // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1369 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1370 uint32_t PER:19; /*!< bit: 5..23 Period Value */
AnnaBridge 171:3a7713b1edbc 1371 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1372 } DITH5; /*!< Structure used for DITH5 */
AnnaBridge 171:3a7713b1edbc 1373 struct { // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1374 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1375 uint32_t PER:18; /*!< bit: 6..23 Period Value */
AnnaBridge 171:3a7713b1edbc 1376 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1377 } DITH6; /*!< Structure used for DITH6 */
AnnaBridge 171:3a7713b1edbc 1378 struct {
AnnaBridge 171:3a7713b1edbc 1379 uint32_t PER:24; /*!< bit: 0..23 Period Value */
AnnaBridge 171:3a7713b1edbc 1380 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1381 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1382 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1383 } TCC_PER_Type;
AnnaBridge 171:3a7713b1edbc 1384 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1385
AnnaBridge 171:3a7713b1edbc 1386 #define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
AnnaBridge 171:3a7713b1edbc 1387 #define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1390 #define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1391 #define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1392 #define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1393 #define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
AnnaBridge 171:3a7713b1edbc 1394 #define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
AnnaBridge 171:3a7713b1edbc 1395 #define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
AnnaBridge 171:3a7713b1edbc 1396 #define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
AnnaBridge 171:3a7713b1edbc 1397
AnnaBridge 171:3a7713b1edbc 1398 // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1399 #define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1400 #define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1401 #define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1402 #define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
AnnaBridge 171:3a7713b1edbc 1403 #define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
AnnaBridge 171:3a7713b1edbc 1404 #define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
AnnaBridge 171:3a7713b1edbc 1405 #define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
AnnaBridge 171:3a7713b1edbc 1406
AnnaBridge 171:3a7713b1edbc 1407 // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1408 #define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1409 #define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1410 #define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1411 #define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
AnnaBridge 171:3a7713b1edbc 1412 #define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
AnnaBridge 171:3a7713b1edbc 1413 #define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
AnnaBridge 171:3a7713b1edbc 1414 #define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
AnnaBridge 171:3a7713b1edbc 1415
AnnaBridge 171:3a7713b1edbc 1416 #define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
AnnaBridge 171:3a7713b1edbc 1417 #define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
AnnaBridge 171:3a7713b1edbc 1418 #define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
AnnaBridge 171:3a7713b1edbc 1419 #define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
AnnaBridge 171:3a7713b1edbc 1422 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1423 typedef union {
AnnaBridge 171:3a7713b1edbc 1424 struct { // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1425 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1426 uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1427 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1428 } DITH4; /*!< Structure used for DITH4 */
AnnaBridge 171:3a7713b1edbc 1429 struct { // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1430 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1431 uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1432 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1433 } DITH5; /*!< Structure used for DITH5 */
AnnaBridge 171:3a7713b1edbc 1434 struct { // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1435 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1436 uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1437 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1438 } DITH6; /*!< Structure used for DITH6 */
AnnaBridge 171:3a7713b1edbc 1439 struct {
AnnaBridge 171:3a7713b1edbc 1440 uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1441 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1442 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1443 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1444 } TCC_CC_Type;
AnnaBridge 171:3a7713b1edbc 1445 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1446
AnnaBridge 171:3a7713b1edbc 1447 #define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
AnnaBridge 171:3a7713b1edbc 1448 #define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
AnnaBridge 171:3a7713b1edbc 1449
AnnaBridge 171:3a7713b1edbc 1450 // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1451 #define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1452 #define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1453 #define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1454 #define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1455 #define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
AnnaBridge 171:3a7713b1edbc 1456 #define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
AnnaBridge 171:3a7713b1edbc 1457 #define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
AnnaBridge 171:3a7713b1edbc 1458
AnnaBridge 171:3a7713b1edbc 1459 // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1460 #define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1461 #define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1462 #define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1463 #define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1464 #define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
AnnaBridge 171:3a7713b1edbc 1465 #define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
AnnaBridge 171:3a7713b1edbc 1466 #define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
AnnaBridge 171:3a7713b1edbc 1467
AnnaBridge 171:3a7713b1edbc 1468 // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1469 #define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
AnnaBridge 171:3a7713b1edbc 1470 #define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
AnnaBridge 171:3a7713b1edbc 1471 #define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
AnnaBridge 171:3a7713b1edbc 1472 #define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1473 #define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
AnnaBridge 171:3a7713b1edbc 1474 #define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
AnnaBridge 171:3a7713b1edbc 1475 #define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
AnnaBridge 171:3a7713b1edbc 1476
AnnaBridge 171:3a7713b1edbc 1477 #define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 1478 #define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
AnnaBridge 171:3a7713b1edbc 1479 #define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
AnnaBridge 171:3a7713b1edbc 1480 #define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
AnnaBridge 171:3a7713b1edbc 1481
AnnaBridge 171:3a7713b1edbc 1482 /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
AnnaBridge 171:3a7713b1edbc 1483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1484 typedef union {
AnnaBridge 171:3a7713b1edbc 1485 struct {
AnnaBridge 171:3a7713b1edbc 1486 uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1487 uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1488 uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1489 uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1490 uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1491 uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1492 uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1493 uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1494 uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 1495 uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 1496 uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 1497 uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 1498 uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 1499 uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 1500 uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 1501 uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 1502 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1503 struct {
AnnaBridge 171:3a7713b1edbc 1504 uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1505 uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
AnnaBridge 171:3a7713b1edbc 1506 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 1507 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1508 } TCC_PATTB_Type;
AnnaBridge 171:3a7713b1edbc 1509 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511 #define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
AnnaBridge 171:3a7713b1edbc 1512 #define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
AnnaBridge 171:3a7713b1edbc 1513
AnnaBridge 171:3a7713b1edbc 1514 #define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1515 #define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
AnnaBridge 171:3a7713b1edbc 1516 #define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1517 #define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
AnnaBridge 171:3a7713b1edbc 1518 #define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1519 #define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
AnnaBridge 171:3a7713b1edbc 1520 #define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1521 #define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
AnnaBridge 171:3a7713b1edbc 1522 #define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1523 #define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
AnnaBridge 171:3a7713b1edbc 1524 #define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1525 #define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
AnnaBridge 171:3a7713b1edbc 1526 #define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1527 #define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
AnnaBridge 171:3a7713b1edbc 1528 #define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1529 #define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
AnnaBridge 171:3a7713b1edbc 1530 #define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1531 #define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
AnnaBridge 171:3a7713b1edbc 1532 #define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
AnnaBridge 171:3a7713b1edbc 1533 #define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
AnnaBridge 171:3a7713b1edbc 1534 #define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
AnnaBridge 171:3a7713b1edbc 1535 #define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
AnnaBridge 171:3a7713b1edbc 1536 #define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
AnnaBridge 171:3a7713b1edbc 1537 #define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
AnnaBridge 171:3a7713b1edbc 1538 #define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
AnnaBridge 171:3a7713b1edbc 1539 #define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
AnnaBridge 171:3a7713b1edbc 1540 #define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
AnnaBridge 171:3a7713b1edbc 1541 #define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
AnnaBridge 171:3a7713b1edbc 1542 #define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
AnnaBridge 171:3a7713b1edbc 1543 #define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
AnnaBridge 171:3a7713b1edbc 1544 #define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
AnnaBridge 171:3a7713b1edbc 1545 #define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
AnnaBridge 171:3a7713b1edbc 1546 #define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
AnnaBridge 171:3a7713b1edbc 1547 #define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
AnnaBridge 171:3a7713b1edbc 1548 #define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
AnnaBridge 171:3a7713b1edbc 1549 #define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
AnnaBridge 171:3a7713b1edbc 1550 #define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
AnnaBridge 171:3a7713b1edbc 1551 #define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
AnnaBridge 171:3a7713b1edbc 1552 #define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
AnnaBridge 171:3a7713b1edbc 1553
AnnaBridge 171:3a7713b1edbc 1554 /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
AnnaBridge 171:3a7713b1edbc 1555 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1556 typedef union {
AnnaBridge 171:3a7713b1edbc 1557 struct {
AnnaBridge 171:3a7713b1edbc 1558 uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
AnnaBridge 171:3a7713b1edbc 1559 uint32_t :1; /*!< bit: 3 Reserved */
AnnaBridge 171:3a7713b1edbc 1560 uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
AnnaBridge 171:3a7713b1edbc 1561 uint32_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 1562 uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1563 uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1564 uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1565 uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1566 uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1567 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1568 uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1569 uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1570 uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1571 uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1572 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1573 uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
AnnaBridge 171:3a7713b1edbc 1574 uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
AnnaBridge 171:3a7713b1edbc 1575 uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
AnnaBridge 171:3a7713b1edbc 1576 uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
AnnaBridge 171:3a7713b1edbc 1577 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1578 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1579 struct {
AnnaBridge 171:3a7713b1edbc 1580 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 1581 uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1582 uint32_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1583 uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1584 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 1585 uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
AnnaBridge 171:3a7713b1edbc 1586 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1587 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 1588 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1589 } TCC_WAVEB_Type;
AnnaBridge 171:3a7713b1edbc 1590 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1591
AnnaBridge 171:3a7713b1edbc 1592 #define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
AnnaBridge 171:3a7713b1edbc 1593 #define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
AnnaBridge 171:3a7713b1edbc 1594
AnnaBridge 171:3a7713b1edbc 1595 #define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
AnnaBridge 171:3a7713b1edbc 1596 #define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1597 #define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
AnnaBridge 171:3a7713b1edbc 1598 #define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
AnnaBridge 171:3a7713b1edbc 1599 #define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
AnnaBridge 171:3a7713b1edbc 1600 #define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
AnnaBridge 171:3a7713b1edbc 1601 #define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */
AnnaBridge 171:3a7713b1edbc 1602 #define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
AnnaBridge 171:3a7713b1edbc 1603 #define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
AnnaBridge 171:3a7713b1edbc 1604 #define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
AnnaBridge 171:3a7713b1edbc 1605 #define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1606 #define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1607 #define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1608 #define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1609 #define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1610 #define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1611 #define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
AnnaBridge 171:3a7713b1edbc 1612 #define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
AnnaBridge 171:3a7713b1edbc 1613 #define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
AnnaBridge 171:3a7713b1edbc 1614 #define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
AnnaBridge 171:3a7713b1edbc 1615 #define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
AnnaBridge 171:3a7713b1edbc 1616 #define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
AnnaBridge 171:3a7713b1edbc 1617 #define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
AnnaBridge 171:3a7713b1edbc 1618 #define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos)
AnnaBridge 171:3a7713b1edbc 1619 #define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos)
AnnaBridge 171:3a7713b1edbc 1620 #define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos)
AnnaBridge 171:3a7713b1edbc 1621 #define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1622 #define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos)
AnnaBridge 171:3a7713b1edbc 1623 #define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1624 #define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
AnnaBridge 171:3a7713b1edbc 1625 #define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1626 #define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
AnnaBridge 171:3a7713b1edbc 1627 #define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1628 #define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
AnnaBridge 171:3a7713b1edbc 1629 #define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1630 #define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
AnnaBridge 171:3a7713b1edbc 1631 #define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
AnnaBridge 171:3a7713b1edbc 1632 #define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
AnnaBridge 171:3a7713b1edbc 1633 #define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
AnnaBridge 171:3a7713b1edbc 1634 #define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1635 #define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
AnnaBridge 171:3a7713b1edbc 1636 #define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1637 #define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
AnnaBridge 171:3a7713b1edbc 1638 #define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1639 #define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
AnnaBridge 171:3a7713b1edbc 1640 #define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1641 #define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
AnnaBridge 171:3a7713b1edbc 1642 #define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
AnnaBridge 171:3a7713b1edbc 1643 #define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
AnnaBridge 171:3a7713b1edbc 1644 #define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
AnnaBridge 171:3a7713b1edbc 1645 #define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
AnnaBridge 171:3a7713b1edbc 1646 #define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
AnnaBridge 171:3a7713b1edbc 1647 #define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
AnnaBridge 171:3a7713b1edbc 1648 #define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
AnnaBridge 171:3a7713b1edbc 1649 #define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
AnnaBridge 171:3a7713b1edbc 1650 #define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
AnnaBridge 171:3a7713b1edbc 1651 #define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
AnnaBridge 171:3a7713b1edbc 1652 #define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
AnnaBridge 171:3a7713b1edbc 1653 #define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
AnnaBridge 171:3a7713b1edbc 1654 #define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
AnnaBridge 171:3a7713b1edbc 1655 #define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
AnnaBridge 171:3a7713b1edbc 1656 #define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
AnnaBridge 171:3a7713b1edbc 1657
AnnaBridge 171:3a7713b1edbc 1658 /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
AnnaBridge 171:3a7713b1edbc 1659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1660 typedef union {
AnnaBridge 171:3a7713b1edbc 1661 struct { // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1662 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1663 uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1664 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1665 } DITH4; /*!< Structure used for DITH4 */
AnnaBridge 171:3a7713b1edbc 1666 struct { // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1667 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1668 uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1669 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1670 } DITH5; /*!< Structure used for DITH5 */
AnnaBridge 171:3a7713b1edbc 1671 struct { // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1672 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1673 uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1674 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1675 } DITH6; /*!< Structure used for DITH6 */
AnnaBridge 171:3a7713b1edbc 1676 struct {
AnnaBridge 171:3a7713b1edbc 1677 uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1678 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1679 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1680 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1681 } TCC_PERB_Type;
AnnaBridge 171:3a7713b1edbc 1682 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1683
AnnaBridge 171:3a7713b1edbc 1684 #define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
AnnaBridge 171:3a7713b1edbc 1685 #define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
AnnaBridge 171:3a7713b1edbc 1686
AnnaBridge 171:3a7713b1edbc 1687 // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1688 #define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1689 #define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1690 #define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1691 #define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1692 #define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
AnnaBridge 171:3a7713b1edbc 1693 #define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
AnnaBridge 171:3a7713b1edbc 1694 #define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
AnnaBridge 171:3a7713b1edbc 1695
AnnaBridge 171:3a7713b1edbc 1696 // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1697 #define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1698 #define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1699 #define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1700 #define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1701 #define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
AnnaBridge 171:3a7713b1edbc 1702 #define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
AnnaBridge 171:3a7713b1edbc 1703 #define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
AnnaBridge 171:3a7713b1edbc 1704
AnnaBridge 171:3a7713b1edbc 1705 // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1706 #define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1707 #define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1708 #define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1709 #define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1710 #define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
AnnaBridge 171:3a7713b1edbc 1711 #define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
AnnaBridge 171:3a7713b1edbc 1712 #define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
AnnaBridge 171:3a7713b1edbc 1713
AnnaBridge 171:3a7713b1edbc 1714 #define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
AnnaBridge 171:3a7713b1edbc 1715 #define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
AnnaBridge 171:3a7713b1edbc 1716 #define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
AnnaBridge 171:3a7713b1edbc 1717 #define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
AnnaBridge 171:3a7713b1edbc 1718
AnnaBridge 171:3a7713b1edbc 1719 /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
AnnaBridge 171:3a7713b1edbc 1720 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1721 typedef union {
AnnaBridge 171:3a7713b1edbc 1722 struct { // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1723 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1724 uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1725 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1726 } DITH4; /*!< Structure used for DITH4 */
AnnaBridge 171:3a7713b1edbc 1727 struct { // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1728 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1729 uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1730 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1731 } DITH5; /*!< Structure used for DITH5 */
AnnaBridge 171:3a7713b1edbc 1732 struct { // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1733 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1734 uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1735 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1736 } DITH6; /*!< Structure used for DITH6 */
AnnaBridge 171:3a7713b1edbc 1737 struct {
AnnaBridge 171:3a7713b1edbc 1738 uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1739 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1740 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1741 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1742 } TCC_CCB_Type;
AnnaBridge 171:3a7713b1edbc 1743 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1744
AnnaBridge 171:3a7713b1edbc 1745 #define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
AnnaBridge 171:3a7713b1edbc 1746 #define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
AnnaBridge 171:3a7713b1edbc 1747
AnnaBridge 171:3a7713b1edbc 1748 // DITH4 mode
AnnaBridge 171:3a7713b1edbc 1749 #define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1750 #define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1751 #define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1752 #define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1753 #define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
AnnaBridge 171:3a7713b1edbc 1754 #define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
AnnaBridge 171:3a7713b1edbc 1755 #define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
AnnaBridge 171:3a7713b1edbc 1756
AnnaBridge 171:3a7713b1edbc 1757 // DITH5 mode
AnnaBridge 171:3a7713b1edbc 1758 #define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1759 #define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1760 #define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1761 #define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1762 #define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
AnnaBridge 171:3a7713b1edbc 1763 #define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
AnnaBridge 171:3a7713b1edbc 1764 #define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
AnnaBridge 171:3a7713b1edbc 1765
AnnaBridge 171:3a7713b1edbc 1766 // DITH6 mode
AnnaBridge 171:3a7713b1edbc 1767 #define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
AnnaBridge 171:3a7713b1edbc 1768 #define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
AnnaBridge 171:3a7713b1edbc 1769 #define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
AnnaBridge 171:3a7713b1edbc 1770 #define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1771 #define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
AnnaBridge 171:3a7713b1edbc 1772 #define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
AnnaBridge 171:3a7713b1edbc 1773 #define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
AnnaBridge 171:3a7713b1edbc 1774
AnnaBridge 171:3a7713b1edbc 1775 #define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
AnnaBridge 171:3a7713b1edbc 1776 #define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
AnnaBridge 171:3a7713b1edbc 1777 #define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
AnnaBridge 171:3a7713b1edbc 1778 #define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
AnnaBridge 171:3a7713b1edbc 1779
AnnaBridge 171:3a7713b1edbc 1780 /** \brief TCC hardware registers */
AnnaBridge 171:3a7713b1edbc 1781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1782 typedef struct {
AnnaBridge 171:3a7713b1edbc 1783 __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
AnnaBridge 171:3a7713b1edbc 1784 __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
AnnaBridge 171:3a7713b1edbc 1785 __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
AnnaBridge 171:3a7713b1edbc 1786 RoReg8 Reserved1[0x2];
AnnaBridge 171:3a7713b1edbc 1787 __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1788 __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
AnnaBridge 171:3a7713b1edbc 1789 __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
AnnaBridge 171:3a7713b1edbc 1790 __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
AnnaBridge 171:3a7713b1edbc 1791 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
AnnaBridge 171:3a7713b1edbc 1792 RoReg8 Reserved2[0x2];
AnnaBridge 171:3a7713b1edbc 1793 __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 1794 RoReg8 Reserved3[0x1];
AnnaBridge 171:3a7713b1edbc 1795 __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
AnnaBridge 171:3a7713b1edbc 1796 __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1797 __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1798 __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1799 __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
AnnaBridge 171:3a7713b1edbc 1800 __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
AnnaBridge 171:3a7713b1edbc 1801 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
AnnaBridge 171:3a7713b1edbc 1802 RoReg8 Reserved4[0x2];
AnnaBridge 171:3a7713b1edbc 1803 __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
AnnaBridge 171:3a7713b1edbc 1804 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
AnnaBridge 171:3a7713b1edbc 1805 __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
AnnaBridge 171:3a7713b1edbc 1806 RoReg8 Reserved5[0x10];
AnnaBridge 171:3a7713b1edbc 1807 __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
AnnaBridge 171:3a7713b1edbc 1808 RoReg8 Reserved6[0x2];
AnnaBridge 171:3a7713b1edbc 1809 __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
AnnaBridge 171:3a7713b1edbc 1810 __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
AnnaBridge 171:3a7713b1edbc 1811 __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
AnnaBridge 171:3a7713b1edbc 1812 } Tcc;
AnnaBridge 171:3a7713b1edbc 1813 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1814
AnnaBridge 171:3a7713b1edbc 1815 /*@}*/
AnnaBridge 171:3a7713b1edbc 1816
AnnaBridge 171:3a7713b1edbc 1817 #endif /* _SAMR21_TCC_COMPONENT_ */