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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_tc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for TC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_TC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_TC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR TC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_TC Basic Timer Counter */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define TC_U2212
AnnaBridge 171:3a7713b1edbc 54 #define REV_TC 0x121
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint16_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
AnnaBridge 171:3a7713b1edbc 63 uint16_t :1; /*!< bit: 4 Reserved */
AnnaBridge 171:3a7713b1edbc 64 uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
AnnaBridge 171:3a7713b1edbc 65 uint16_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 66 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
AnnaBridge 171:3a7713b1edbc 67 uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
AnnaBridge 171:3a7713b1edbc 68 uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
AnnaBridge 171:3a7713b1edbc 69 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 70 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 71 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 72 } TC_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
AnnaBridge 171:3a7713b1edbc 76 #define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 79 #define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 80 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 81 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 82 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
AnnaBridge 171:3a7713b1edbc 83 #define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 84 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 85 #define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
AnnaBridge 171:3a7713b1edbc 86 #define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
AnnaBridge 171:3a7713b1edbc 87 #define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
AnnaBridge 171:3a7713b1edbc 88 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 89 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 91 #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
AnnaBridge 171:3a7713b1edbc 92 #define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 93 #define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
AnnaBridge 171:3a7713b1edbc 94 #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
AnnaBridge 171:3a7713b1edbc 95 #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
AnnaBridge 171:3a7713b1edbc 96 #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
AnnaBridge 171:3a7713b1edbc 97 #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */
AnnaBridge 171:3a7713b1edbc 98 #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 99 #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 100 #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 101 #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
AnnaBridge 171:3a7713b1edbc 102 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
AnnaBridge 171:3a7713b1edbc 103 #define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 105 #define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
AnnaBridge 171:3a7713b1edbc 106 #define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
AnnaBridge 171:3a7713b1edbc 107 #define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
AnnaBridge 171:3a7713b1edbc 108 #define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
AnnaBridge 171:3a7713b1edbc 109 #define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
AnnaBridge 171:3a7713b1edbc 110 #define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
AnnaBridge 171:3a7713b1edbc 111 #define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
AnnaBridge 171:3a7713b1edbc 112 #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
AnnaBridge 171:3a7713b1edbc 113 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 114 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 116 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 117 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 118 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 119 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 121 #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
AnnaBridge 171:3a7713b1edbc 122 #define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 123 #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
AnnaBridge 171:3a7713b1edbc 124 #define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
AnnaBridge 171:3a7713b1edbc 126 #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
AnnaBridge 171:3a7713b1edbc 127 #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
AnnaBridge 171:3a7713b1edbc 128 #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
AnnaBridge 171:3a7713b1edbc 129 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 130 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 131 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
AnnaBridge 171:3a7713b1edbc 132 #define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
AnnaBridge 171:3a7713b1edbc 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 136 typedef union {
AnnaBridge 171:3a7713b1edbc 137 struct {
AnnaBridge 171:3a7713b1edbc 138 uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
AnnaBridge 171:3a7713b1edbc 139 uint16_t :9; /*!< bit: 5..13 Reserved */
AnnaBridge 171:3a7713b1edbc 140 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
AnnaBridge 171:3a7713b1edbc 141 uint16_t RREQ:1; /*!< bit: 15 Read Request */
AnnaBridge 171:3a7713b1edbc 142 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 143 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 144 } TC_READREQ_Type;
AnnaBridge 171:3a7713b1edbc 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
AnnaBridge 171:3a7713b1edbc 148 #define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
AnnaBridge 171:3a7713b1edbc 151 #define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 152 #define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 153 #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
AnnaBridge 171:3a7713b1edbc 154 #define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
AnnaBridge 171:3a7713b1edbc 155 #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
AnnaBridge 171:3a7713b1edbc 156 #define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos)
AnnaBridge 171:3a7713b1edbc 157 #define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
AnnaBridge 171:3a7713b1edbc 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 161 typedef union {
AnnaBridge 171:3a7713b1edbc 162 struct {
AnnaBridge 171:3a7713b1edbc 163 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
AnnaBridge 171:3a7713b1edbc 164 uint8_t :1; /*!< bit: 1 Reserved */
AnnaBridge 171:3a7713b1edbc 165 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
AnnaBridge 171:3a7713b1edbc 166 uint8_t :3; /*!< bit: 3.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 167 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
AnnaBridge 171:3a7713b1edbc 168 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 169 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 170 } TC_CTRLBCLR_Type;
AnnaBridge 171:3a7713b1edbc 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
AnnaBridge 171:3a7713b1edbc 174 #define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
AnnaBridge 171:3a7713b1edbc 177 #define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 178 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
AnnaBridge 171:3a7713b1edbc 179 #define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
AnnaBridge 171:3a7713b1edbc 180 #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
AnnaBridge 171:3a7713b1edbc 181 #define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 182 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 183 #define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
AnnaBridge 171:3a7713b1edbc 184 #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
AnnaBridge 171:3a7713b1edbc 185 #define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
AnnaBridge 171:3a7713b1edbc 186 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 187 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 188 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 189 #define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
AnnaBridge 171:3a7713b1edbc 192 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 193 typedef union {
AnnaBridge 171:3a7713b1edbc 194 struct {
AnnaBridge 171:3a7713b1edbc 195 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
AnnaBridge 171:3a7713b1edbc 196 uint8_t :1; /*!< bit: 1 Reserved */
AnnaBridge 171:3a7713b1edbc 197 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
AnnaBridge 171:3a7713b1edbc 198 uint8_t :3; /*!< bit: 3.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 199 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
AnnaBridge 171:3a7713b1edbc 200 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 201 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 202 } TC_CTRLBSET_Type;
AnnaBridge 171:3a7713b1edbc 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
AnnaBridge 171:3a7713b1edbc 206 #define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
AnnaBridge 171:3a7713b1edbc 209 #define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 210 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
AnnaBridge 171:3a7713b1edbc 211 #define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
AnnaBridge 171:3a7713b1edbc 212 #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
AnnaBridge 171:3a7713b1edbc 213 #define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 214 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 215 #define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
AnnaBridge 171:3a7713b1edbc 216 #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
AnnaBridge 171:3a7713b1edbc 217 #define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
AnnaBridge 171:3a7713b1edbc 218 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 219 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 220 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 221 #define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
AnnaBridge 171:3a7713b1edbc 224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 225 typedef union {
AnnaBridge 171:3a7713b1edbc 226 struct {
AnnaBridge 171:3a7713b1edbc 227 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
AnnaBridge 171:3a7713b1edbc 228 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
AnnaBridge 171:3a7713b1edbc 229 uint8_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 230 uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 231 uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 232 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 233 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 234 struct {
AnnaBridge 171:3a7713b1edbc 235 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
AnnaBridge 171:3a7713b1edbc 236 uint8_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 237 uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
AnnaBridge 171:3a7713b1edbc 238 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 239 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 240 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 241 } TC_CTRLC_Type;
AnnaBridge 171:3a7713b1edbc 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
AnnaBridge 171:3a7713b1edbc 245 #define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
AnnaBridge 171:3a7713b1edbc 248 #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
AnnaBridge 171:3a7713b1edbc 249 #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
AnnaBridge 171:3a7713b1edbc 250 #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
AnnaBridge 171:3a7713b1edbc 251 #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
AnnaBridge 171:3a7713b1edbc 252 #define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
AnnaBridge 171:3a7713b1edbc 253 #define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
AnnaBridge 171:3a7713b1edbc 254 #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 255 #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
AnnaBridge 171:3a7713b1edbc 256 #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 257 #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
AnnaBridge 171:3a7713b1edbc 258 #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
AnnaBridge 171:3a7713b1edbc 259 #define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
AnnaBridge 171:3a7713b1edbc 260 #define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
AnnaBridge 171:3a7713b1edbc 261 #define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 265 typedef union {
AnnaBridge 171:3a7713b1edbc 266 struct {
AnnaBridge 171:3a7713b1edbc 267 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
AnnaBridge 171:3a7713b1edbc 268 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 269 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 270 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 271 } TC_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 272 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
AnnaBridge 171:3a7713b1edbc 275 #define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
AnnaBridge 171:3a7713b1edbc 278 #define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
AnnaBridge 171:3a7713b1edbc 279 #define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
AnnaBridge 171:3a7713b1edbc 282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 283 typedef union {
AnnaBridge 171:3a7713b1edbc 284 struct {
AnnaBridge 171:3a7713b1edbc 285 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
AnnaBridge 171:3a7713b1edbc 286 uint16_t :1; /*!< bit: 3 Reserved */
AnnaBridge 171:3a7713b1edbc 287 uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
AnnaBridge 171:3a7713b1edbc 288 uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
AnnaBridge 171:3a7713b1edbc 289 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 290 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 291 uint16_t :3; /*!< bit: 9..11 Reserved */
AnnaBridge 171:3a7713b1edbc 292 uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 293 uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 294 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 295 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 296 struct {
AnnaBridge 171:3a7713b1edbc 297 uint16_t :12; /*!< bit: 0..11 Reserved */
AnnaBridge 171:3a7713b1edbc 298 uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 299 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 300 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 301 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 302 } TC_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
AnnaBridge 171:3a7713b1edbc 306 #define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
AnnaBridge 171:3a7713b1edbc 309 #define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 310 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
AnnaBridge 171:3a7713b1edbc 311 #define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
AnnaBridge 171:3a7713b1edbc 312 #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
AnnaBridge 171:3a7713b1edbc 313 #define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
AnnaBridge 171:3a7713b1edbc 314 #define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */
AnnaBridge 171:3a7713b1edbc 315 #define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
AnnaBridge 171:3a7713b1edbc 316 #define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
AnnaBridge 171:3a7713b1edbc 317 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 318 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 319 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 320 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 321 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 322 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
AnnaBridge 171:3a7713b1edbc 323 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
AnnaBridge 171:3a7713b1edbc 324 #define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos)
AnnaBridge 171:3a7713b1edbc 325 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
AnnaBridge 171:3a7713b1edbc 326 #define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 328 #define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos)
AnnaBridge 171:3a7713b1edbc 329 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 330 #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
AnnaBridge 171:3a7713b1edbc 331 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 332 #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
AnnaBridge 171:3a7713b1edbc 333 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 334 #define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
AnnaBridge 171:3a7713b1edbc 335 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
AnnaBridge 171:3a7713b1edbc 336 #define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 340 typedef union {
AnnaBridge 171:3a7713b1edbc 341 struct {
AnnaBridge 171:3a7713b1edbc 342 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 343 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 344 uint8_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 345 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 346 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 347 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 348 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 349 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 350 struct {
AnnaBridge 171:3a7713b1edbc 351 uint8_t :4; /*!< bit: 0.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 352 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 353 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 354 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 355 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 356 } TC_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 360 #define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 363 #define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 364 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 365 #define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 366 #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 367 #define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 368 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 369 #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 370 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 371 #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 372 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 373 #define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
AnnaBridge 171:3a7713b1edbc 374 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
AnnaBridge 171:3a7713b1edbc 375 #define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 379 typedef union {
AnnaBridge 171:3a7713b1edbc 380 struct {
AnnaBridge 171:3a7713b1edbc 381 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 382 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 383 uint8_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 384 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 385 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 386 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 387 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 388 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 389 struct {
AnnaBridge 171:3a7713b1edbc 390 uint8_t :4; /*!< bit: 0.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 391 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 392 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 393 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 394 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 395 } TC_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 396 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 399 #define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 402 #define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 403 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 404 #define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 405 #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 406 #define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 407 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 408 #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 409 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 410 #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 411 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 412 #define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
AnnaBridge 171:3a7713b1edbc 413 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
AnnaBridge 171:3a7713b1edbc 414 #define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 418 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 419 struct {
AnnaBridge 171:3a7713b1edbc 420 __I uint8_t OVF:1; /*!< bit: 0 Overflow */
AnnaBridge 171:3a7713b1edbc 421 __I uint8_t ERR:1; /*!< bit: 1 Error */
AnnaBridge 171:3a7713b1edbc 422 __I uint8_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 423 __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 424 __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
AnnaBridge 171:3a7713b1edbc 425 __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
AnnaBridge 171:3a7713b1edbc 426 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 427 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 428 struct {
AnnaBridge 171:3a7713b1edbc 429 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 430 __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
AnnaBridge 171:3a7713b1edbc 431 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 432 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 433 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 434 } TC_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 438 #define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
AnnaBridge 171:3a7713b1edbc 441 #define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 442 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
AnnaBridge 171:3a7713b1edbc 443 #define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos)
AnnaBridge 171:3a7713b1edbc 444 #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 445 #define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 446 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
AnnaBridge 171:3a7713b1edbc 447 #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
AnnaBridge 171:3a7713b1edbc 448 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
AnnaBridge 171:3a7713b1edbc 449 #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
AnnaBridge 171:3a7713b1edbc 450 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
AnnaBridge 171:3a7713b1edbc 451 #define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
AnnaBridge 171:3a7713b1edbc 452 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
AnnaBridge 171:3a7713b1edbc 453 #define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
AnnaBridge 171:3a7713b1edbc 456 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 457 typedef union {
AnnaBridge 171:3a7713b1edbc 458 struct {
AnnaBridge 171:3a7713b1edbc 459 uint8_t :3; /*!< bit: 0.. 2 Reserved */
AnnaBridge 171:3a7713b1edbc 460 uint8_t STOP:1; /*!< bit: 3 Stop */
AnnaBridge 171:3a7713b1edbc 461 uint8_t SLAVE:1; /*!< bit: 4 Slave */
AnnaBridge 171:3a7713b1edbc 462 uint8_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 463 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 464 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 465 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 466 } TC_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 467 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 470 #define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
AnnaBridge 171:3a7713b1edbc 473 #define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos)
AnnaBridge 171:3a7713b1edbc 474 #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
AnnaBridge 171:3a7713b1edbc 475 #define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos)
AnnaBridge 171:3a7713b1edbc 476 #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 477 #define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 478 #define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
AnnaBridge 171:3a7713b1edbc 481 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 482 typedef union {
AnnaBridge 171:3a7713b1edbc 483 struct {
AnnaBridge 171:3a7713b1edbc 484 uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
AnnaBridge 171:3a7713b1edbc 485 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 486 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 487 } TC_COUNT16_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 488 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 489
AnnaBridge 171:3a7713b1edbc 490 #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
AnnaBridge 171:3a7713b1edbc 491 #define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
AnnaBridge 171:3a7713b1edbc 494 #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 495 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 496 #define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
AnnaBridge 171:3a7713b1edbc 499 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 500 typedef union {
AnnaBridge 171:3a7713b1edbc 501 struct {
AnnaBridge 171:3a7713b1edbc 502 uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
AnnaBridge 171:3a7713b1edbc 503 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 504 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 505 } TC_COUNT32_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 506 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
AnnaBridge 171:3a7713b1edbc 509 #define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
AnnaBridge 171:3a7713b1edbc 510
AnnaBridge 171:3a7713b1edbc 511 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
AnnaBridge 171:3a7713b1edbc 512 #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 513 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 514 #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
AnnaBridge 171:3a7713b1edbc 517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 518 typedef union {
AnnaBridge 171:3a7713b1edbc 519 struct {
AnnaBridge 171:3a7713b1edbc 520 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
AnnaBridge 171:3a7713b1edbc 521 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 522 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 523 } TC_COUNT8_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 524 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526 #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
AnnaBridge 171:3a7713b1edbc 527 #define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
AnnaBridge 171:3a7713b1edbc 530 #define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 531 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 532 #define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
AnnaBridge 171:3a7713b1edbc 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 536 typedef union {
AnnaBridge 171:3a7713b1edbc 537 struct {
AnnaBridge 171:3a7713b1edbc 538 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
AnnaBridge 171:3a7713b1edbc 539 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 540 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 541 } TC_COUNT8_PER_Type;
AnnaBridge 171:3a7713b1edbc 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
AnnaBridge 171:3a7713b1edbc 545 #define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
AnnaBridge 171:3a7713b1edbc 548 #define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
AnnaBridge 171:3a7713b1edbc 549 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
AnnaBridge 171:3a7713b1edbc 550 #define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
AnnaBridge 171:3a7713b1edbc 553 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 554 typedef union {
AnnaBridge 171:3a7713b1edbc 555 struct {
AnnaBridge 171:3a7713b1edbc 556 uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 557 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 558 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 559 } TC_COUNT16_CC_Type;
AnnaBridge 171:3a7713b1edbc 560 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 563 #define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 566 #define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
AnnaBridge 171:3a7713b1edbc 567 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
AnnaBridge 171:3a7713b1edbc 568 #define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
AnnaBridge 171:3a7713b1edbc 569
AnnaBridge 171:3a7713b1edbc 570 /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
AnnaBridge 171:3a7713b1edbc 571 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 572 typedef union {
AnnaBridge 171:3a7713b1edbc 573 struct {
AnnaBridge 171:3a7713b1edbc 574 uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 575 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 576 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 577 } TC_COUNT32_CC_Type;
AnnaBridge 171:3a7713b1edbc 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 581 #define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 584 #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
AnnaBridge 171:3a7713b1edbc 585 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
AnnaBridge 171:3a7713b1edbc 586 #define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
AnnaBridge 171:3a7713b1edbc 589 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 590 typedef union {
AnnaBridge 171:3a7713b1edbc 591 struct {
AnnaBridge 171:3a7713b1edbc 592 uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 593 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 594 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 595 } TC_COUNT8_CC_Type;
AnnaBridge 171:3a7713b1edbc 596 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 599 #define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
AnnaBridge 171:3a7713b1edbc 602 #define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
AnnaBridge 171:3a7713b1edbc 603 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
AnnaBridge 171:3a7713b1edbc 604 #define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 /** \brief TC_COUNT8 hardware registers */
AnnaBridge 171:3a7713b1edbc 607 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 608 typedef struct { /* 8-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 609 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
AnnaBridge 171:3a7713b1edbc 610 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 611 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
AnnaBridge 171:3a7713b1edbc 612 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
AnnaBridge 171:3a7713b1edbc 613 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
AnnaBridge 171:3a7713b1edbc 614 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 615 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 616 RoReg8 Reserved2[0x1];
AnnaBridge 171:3a7713b1edbc 617 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
AnnaBridge 171:3a7713b1edbc 618 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 619 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 620 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 621 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 622 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
AnnaBridge 171:3a7713b1edbc 623 RoReg8 Reserved3[0x3];
AnnaBridge 171:3a7713b1edbc 624 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
AnnaBridge 171:3a7713b1edbc 625 RoReg8 Reserved4[0x3];
AnnaBridge 171:3a7713b1edbc 626 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 627 } TcCount8;
AnnaBridge 171:3a7713b1edbc 628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /** \brief TC_COUNT16 hardware registers */
AnnaBridge 171:3a7713b1edbc 631 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 632 typedef struct { /* 16-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 633 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
AnnaBridge 171:3a7713b1edbc 634 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 635 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
AnnaBridge 171:3a7713b1edbc 636 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
AnnaBridge 171:3a7713b1edbc 637 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
AnnaBridge 171:3a7713b1edbc 638 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 639 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 640 RoReg8 Reserved2[0x1];
AnnaBridge 171:3a7713b1edbc 641 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
AnnaBridge 171:3a7713b1edbc 642 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 643 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 644 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 645 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 646 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
AnnaBridge 171:3a7713b1edbc 647 RoReg8 Reserved3[0x6];
AnnaBridge 171:3a7713b1edbc 648 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 649 } TcCount16;
AnnaBridge 171:3a7713b1edbc 650 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /** \brief TC_COUNT32 hardware registers */
AnnaBridge 171:3a7713b1edbc 653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 654 typedef struct { /* 32-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 655 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
AnnaBridge 171:3a7713b1edbc 656 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 657 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
AnnaBridge 171:3a7713b1edbc 658 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
AnnaBridge 171:3a7713b1edbc 659 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
AnnaBridge 171:3a7713b1edbc 660 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 661 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 662 RoReg8 Reserved2[0x1];
AnnaBridge 171:3a7713b1edbc 663 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
AnnaBridge 171:3a7713b1edbc 664 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 665 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 666 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 667 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 668 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
AnnaBridge 171:3a7713b1edbc 669 RoReg8 Reserved3[0x4];
AnnaBridge 171:3a7713b1edbc 670 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
AnnaBridge 171:3a7713b1edbc 671 } TcCount32;
AnnaBridge 171:3a7713b1edbc 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 675 typedef union {
AnnaBridge 171:3a7713b1edbc 676 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 677 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 678 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
AnnaBridge 171:3a7713b1edbc 679 } Tc;
AnnaBridge 171:3a7713b1edbc 680 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 681
AnnaBridge 171:3a7713b1edbc 682 /*@}*/
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 #endif /* _SAMR21_TC_COMPONENT_ */