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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_rtc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for RTC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_RTC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_RTC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR RTC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_RTC Real-Time Counter */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define RTC_U2202
AnnaBridge 171:3a7713b1edbc 54 #define REV_RTC 0x101
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint16_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
AnnaBridge 171:3a7713b1edbc 63 uint16_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 64 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
AnnaBridge 171:3a7713b1edbc 65 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
AnnaBridge 171:3a7713b1edbc 66 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 67 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 68 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 69 } RTC_MODE0_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
AnnaBridge 171:3a7713b1edbc 73 #define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 76 #define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 77 #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
AnnaBridge 171:3a7713b1edbc 78 #define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 79 #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
AnnaBridge 171:3a7713b1edbc 80 #define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 81 #define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 82 #define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
AnnaBridge 171:3a7713b1edbc 83 #define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
AnnaBridge 171:3a7713b1edbc 84 #define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
AnnaBridge 171:3a7713b1edbc 85 #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 86 #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 87 #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 88 #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
AnnaBridge 171:3a7713b1edbc 89 #define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
AnnaBridge 171:3a7713b1edbc 91 #define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 92 #define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 93 #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
AnnaBridge 171:3a7713b1edbc 94 #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
AnnaBridge 171:3a7713b1edbc 95 #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
AnnaBridge 171:3a7713b1edbc 96 #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
AnnaBridge 171:3a7713b1edbc 97 #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
AnnaBridge 171:3a7713b1edbc 98 #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
AnnaBridge 171:3a7713b1edbc 99 #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
AnnaBridge 171:3a7713b1edbc 100 #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
AnnaBridge 171:3a7713b1edbc 101 #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
AnnaBridge 171:3a7713b1edbc 102 #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
AnnaBridge 171:3a7713b1edbc 103 #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
AnnaBridge 171:3a7713b1edbc 104 #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 105 #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 107 #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 108 #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 109 #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 110 #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 111 #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 112 #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 113 #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 114 #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
AnnaBridge 171:3a7713b1edbc 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 119 typedef union {
AnnaBridge 171:3a7713b1edbc 120 struct {
AnnaBridge 171:3a7713b1edbc 121 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 122 uint16_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 123 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
AnnaBridge 171:3a7713b1edbc 124 uint16_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 125 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
AnnaBridge 171:3a7713b1edbc 126 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 127 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 128 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 129 } RTC_MODE1_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 130 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
AnnaBridge 171:3a7713b1edbc 133 #define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 136 #define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 137 #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
AnnaBridge 171:3a7713b1edbc 138 #define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 139 #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
AnnaBridge 171:3a7713b1edbc 140 #define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 142 #define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
AnnaBridge 171:3a7713b1edbc 143 #define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
AnnaBridge 171:3a7713b1edbc 144 #define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
AnnaBridge 171:3a7713b1edbc 145 #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 146 #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 148 #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
AnnaBridge 171:3a7713b1edbc 149 #define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 150 #define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 151 #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
AnnaBridge 171:3a7713b1edbc 152 #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
AnnaBridge 171:3a7713b1edbc 153 #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
AnnaBridge 171:3a7713b1edbc 154 #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
AnnaBridge 171:3a7713b1edbc 155 #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
AnnaBridge 171:3a7713b1edbc 156 #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
AnnaBridge 171:3a7713b1edbc 157 #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
AnnaBridge 171:3a7713b1edbc 158 #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
AnnaBridge 171:3a7713b1edbc 159 #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
AnnaBridge 171:3a7713b1edbc 160 #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
AnnaBridge 171:3a7713b1edbc 161 #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
AnnaBridge 171:3a7713b1edbc 162 #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 163 #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 164 #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 165 #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 166 #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 167 #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 168 #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 169 #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 170 #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 171 #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 172 #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 173 #define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
AnnaBridge 171:3a7713b1edbc 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 177 typedef union {
AnnaBridge 171:3a7713b1edbc 178 struct {
AnnaBridge 171:3a7713b1edbc 179 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 180 uint16_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 181 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
AnnaBridge 171:3a7713b1edbc 182 uint16_t :2; /*!< bit: 4.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 183 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
AnnaBridge 171:3a7713b1edbc 184 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
AnnaBridge 171:3a7713b1edbc 185 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
AnnaBridge 171:3a7713b1edbc 186 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 187 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 188 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 189 } RTC_MODE2_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
AnnaBridge 171:3a7713b1edbc 193 #define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 196 #define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 197 #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
AnnaBridge 171:3a7713b1edbc 198 #define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 199 #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
AnnaBridge 171:3a7713b1edbc 200 #define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 201 #define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 202 #define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
AnnaBridge 171:3a7713b1edbc 203 #define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
AnnaBridge 171:3a7713b1edbc 204 #define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
AnnaBridge 171:3a7713b1edbc 205 #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 206 #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 207 #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 208 #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
AnnaBridge 171:3a7713b1edbc 209 #define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
AnnaBridge 171:3a7713b1edbc 210 #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
AnnaBridge 171:3a7713b1edbc 211 #define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
AnnaBridge 171:3a7713b1edbc 212 #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
AnnaBridge 171:3a7713b1edbc 213 #define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 214 #define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 215 #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
AnnaBridge 171:3a7713b1edbc 216 #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
AnnaBridge 171:3a7713b1edbc 217 #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
AnnaBridge 171:3a7713b1edbc 218 #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
AnnaBridge 171:3a7713b1edbc 219 #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
AnnaBridge 171:3a7713b1edbc 220 #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
AnnaBridge 171:3a7713b1edbc 221 #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
AnnaBridge 171:3a7713b1edbc 222 #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
AnnaBridge 171:3a7713b1edbc 223 #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
AnnaBridge 171:3a7713b1edbc 224 #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
AnnaBridge 171:3a7713b1edbc 225 #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
AnnaBridge 171:3a7713b1edbc 226 #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 227 #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 229 #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 230 #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 231 #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 232 #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 233 #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 234 #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 235 #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 236 #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 237 #define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
AnnaBridge 171:3a7713b1edbc 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 241 typedef union {
AnnaBridge 171:3a7713b1edbc 242 struct {
AnnaBridge 171:3a7713b1edbc 243 uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
AnnaBridge 171:3a7713b1edbc 244 uint16_t :8; /*!< bit: 6..13 Reserved */
AnnaBridge 171:3a7713b1edbc 245 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
AnnaBridge 171:3a7713b1edbc 246 uint16_t RREQ:1; /*!< bit: 15 Read Request */
AnnaBridge 171:3a7713b1edbc 247 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 248 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 249 } RTC_READREQ_Type;
AnnaBridge 171:3a7713b1edbc 250 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
AnnaBridge 171:3a7713b1edbc 253 #define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
AnnaBridge 171:3a7713b1edbc 256 #define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 257 #define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 258 #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
AnnaBridge 171:3a7713b1edbc 259 #define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
AnnaBridge 171:3a7713b1edbc 260 #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
AnnaBridge 171:3a7713b1edbc 261 #define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos)
AnnaBridge 171:3a7713b1edbc 262 #define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
AnnaBridge 171:3a7713b1edbc 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 266 typedef union {
AnnaBridge 171:3a7713b1edbc 267 struct {
AnnaBridge 171:3a7713b1edbc 268 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 269 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 270 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 271 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 272 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 273 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 274 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 275 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 276 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 277 uint16_t :6; /*!< bit: 9..14 Reserved */
AnnaBridge 171:3a7713b1edbc 278 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 279 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 280 struct {
AnnaBridge 171:3a7713b1edbc 281 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 282 uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 283 uint16_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 284 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 285 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 286 } RTC_MODE0_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
AnnaBridge 171:3a7713b1edbc 290 #define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 293 #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
AnnaBridge 171:3a7713b1edbc 294 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 295 #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
AnnaBridge 171:3a7713b1edbc 296 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 297 #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
AnnaBridge 171:3a7713b1edbc 298 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 299 #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
AnnaBridge 171:3a7713b1edbc 300 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 301 #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
AnnaBridge 171:3a7713b1edbc 302 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 303 #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 305 #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
AnnaBridge 171:3a7713b1edbc 306 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 307 #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 309 #define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
AnnaBridge 171:3a7713b1edbc 310 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
AnnaBridge 171:3a7713b1edbc 311 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 312 #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
AnnaBridge 171:3a7713b1edbc 313 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 314 #define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
AnnaBridge 171:3a7713b1edbc 315 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
AnnaBridge 171:3a7713b1edbc 316 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 317 #define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
AnnaBridge 171:3a7713b1edbc 318 #define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
AnnaBridge 171:3a7713b1edbc 321 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 322 typedef union {
AnnaBridge 171:3a7713b1edbc 323 struct {
AnnaBridge 171:3a7713b1edbc 324 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 325 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 326 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 327 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 328 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 329 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 330 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 331 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 332 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 333 uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 334 uint16_t :5; /*!< bit: 10..14 Reserved */
AnnaBridge 171:3a7713b1edbc 335 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 336 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 337 struct {
AnnaBridge 171:3a7713b1edbc 338 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 339 uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 340 uint16_t :6; /*!< bit: 10..15 Reserved */
AnnaBridge 171:3a7713b1edbc 341 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 342 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 343 } RTC_MODE1_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
AnnaBridge 171:3a7713b1edbc 347 #define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 350 #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
AnnaBridge 171:3a7713b1edbc 351 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 352 #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
AnnaBridge 171:3a7713b1edbc 353 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 354 #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
AnnaBridge 171:3a7713b1edbc 355 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 356 #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
AnnaBridge 171:3a7713b1edbc 357 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 358 #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
AnnaBridge 171:3a7713b1edbc 359 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 360 #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
AnnaBridge 171:3a7713b1edbc 361 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 362 #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
AnnaBridge 171:3a7713b1edbc 363 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 364 #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
AnnaBridge 171:3a7713b1edbc 365 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 366 #define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
AnnaBridge 171:3a7713b1edbc 367 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
AnnaBridge 171:3a7713b1edbc 368 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 369 #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
AnnaBridge 171:3a7713b1edbc 370 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 371 #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
AnnaBridge 171:3a7713b1edbc 372 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 373 #define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
AnnaBridge 171:3a7713b1edbc 374 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
AnnaBridge 171:3a7713b1edbc 375 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 376 #define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
AnnaBridge 171:3a7713b1edbc 377 #define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
AnnaBridge 171:3a7713b1edbc 380 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 381 typedef union {
AnnaBridge 171:3a7713b1edbc 382 struct {
AnnaBridge 171:3a7713b1edbc 383 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 384 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 385 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 386 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 387 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 388 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 389 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 390 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 391 uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 392 uint16_t :6; /*!< bit: 9..14 Reserved */
AnnaBridge 171:3a7713b1edbc 393 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 394 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 395 struct {
AnnaBridge 171:3a7713b1edbc 396 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 397 uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 398 uint16_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 399 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 400 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 401 } RTC_MODE2_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
AnnaBridge 171:3a7713b1edbc 405 #define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 408 #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
AnnaBridge 171:3a7713b1edbc 409 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 410 #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
AnnaBridge 171:3a7713b1edbc 411 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 412 #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
AnnaBridge 171:3a7713b1edbc 413 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 414 #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
AnnaBridge 171:3a7713b1edbc 415 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 416 #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
AnnaBridge 171:3a7713b1edbc 417 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 418 #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
AnnaBridge 171:3a7713b1edbc 419 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 420 #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
AnnaBridge 171:3a7713b1edbc 421 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 422 #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
AnnaBridge 171:3a7713b1edbc 423 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 424 #define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
AnnaBridge 171:3a7713b1edbc 425 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
AnnaBridge 171:3a7713b1edbc 426 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 427 #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
AnnaBridge 171:3a7713b1edbc 428 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 429 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
AnnaBridge 171:3a7713b1edbc 430 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
AnnaBridge 171:3a7713b1edbc 431 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
AnnaBridge 171:3a7713b1edbc 432 #define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
AnnaBridge 171:3a7713b1edbc 433 #define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 437 typedef union {
AnnaBridge 171:3a7713b1edbc 438 struct {
AnnaBridge 171:3a7713b1edbc 439 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 440 uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 441 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 442 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 443 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 444 struct {
AnnaBridge 171:3a7713b1edbc 445 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 446 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 447 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 448 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 449 } RTC_MODE0_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 453 #define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 456 #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 457 #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 458 #define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 459 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 460 #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 461 #define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 462 #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 463 #define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 464 #define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 467 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 468 typedef union {
AnnaBridge 171:3a7713b1edbc 469 struct {
AnnaBridge 171:3a7713b1edbc 470 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 471 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 472 uint8_t :4; /*!< bit: 2.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 473 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 474 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 475 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 476 struct {
AnnaBridge 171:3a7713b1edbc 477 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 478 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 479 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 480 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 481 } RTC_MODE1_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 485 #define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 488 #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 489 #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 490 #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
AnnaBridge 171:3a7713b1edbc 491 #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 492 #define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 493 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 494 #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 495 #define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 496 #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 497 #define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 498 #define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 502 typedef union {
AnnaBridge 171:3a7713b1edbc 503 struct {
AnnaBridge 171:3a7713b1edbc 504 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 505 uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 506 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 507 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 508 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 509 struct {
AnnaBridge 171:3a7713b1edbc 510 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 511 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 512 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 513 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 514 } RTC_MODE2_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 515 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 518 #define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 521 #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
AnnaBridge 171:3a7713b1edbc 522 #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 523 #define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
AnnaBridge 171:3a7713b1edbc 524 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
AnnaBridge 171:3a7713b1edbc 525 #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 526 #define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 527 #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 528 #define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 529 #define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 533 typedef union {
AnnaBridge 171:3a7713b1edbc 534 struct {
AnnaBridge 171:3a7713b1edbc 535 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 536 uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 537 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 538 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 539 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 540 struct {
AnnaBridge 171:3a7713b1edbc 541 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 542 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 543 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 544 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 545 } RTC_MODE0_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 546 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 549 #define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 552 #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 553 #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 554 #define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 555 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 556 #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 557 #define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 558 #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 559 #define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 564 typedef union {
AnnaBridge 171:3a7713b1edbc 565 struct {
AnnaBridge 171:3a7713b1edbc 566 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 567 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 568 uint8_t :4; /*!< bit: 2.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 569 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 570 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 571 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 572 struct {
AnnaBridge 171:3a7713b1edbc 573 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 574 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 575 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 576 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 577 } RTC_MODE1_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 581 #define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 584 #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 585 #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 586 #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
AnnaBridge 171:3a7713b1edbc 587 #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 588 #define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 589 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 590 #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 591 #define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 592 #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 593 #define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 594 #define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 597 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 598 typedef union {
AnnaBridge 171:3a7713b1edbc 599 struct {
AnnaBridge 171:3a7713b1edbc 600 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 601 uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 602 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 603 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 604 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 605 struct {
AnnaBridge 171:3a7713b1edbc 606 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 607 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 608 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 609 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 610 } RTC_MODE2_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 611 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 614 #define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 617 #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
AnnaBridge 171:3a7713b1edbc 618 #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 619 #define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
AnnaBridge 171:3a7713b1edbc 620 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
AnnaBridge 171:3a7713b1edbc 621 #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 622 #define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 623 #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 624 #define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 625 #define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 628 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 629 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 630 struct {
AnnaBridge 171:3a7713b1edbc 631 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
AnnaBridge 171:3a7713b1edbc 632 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 633 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 634 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
AnnaBridge 171:3a7713b1edbc 635 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 636 struct {
AnnaBridge 171:3a7713b1edbc 637 __I uint8_t CMP:1; /*!< bit: 0 Compare x */
AnnaBridge 171:3a7713b1edbc 638 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 639 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 640 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 641 } RTC_MODE0_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 643
AnnaBridge 171:3a7713b1edbc 644 #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 645 #define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
AnnaBridge 171:3a7713b1edbc 648 #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 649 #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
AnnaBridge 171:3a7713b1edbc 650 #define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 651 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 652 #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 653 #define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 654 #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
AnnaBridge 171:3a7713b1edbc 655 #define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 656 #define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 657
AnnaBridge 171:3a7713b1edbc 658 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 660 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 661 struct {
AnnaBridge 171:3a7713b1edbc 662 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
AnnaBridge 171:3a7713b1edbc 663 __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
AnnaBridge 171:3a7713b1edbc 664 __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 665 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 666 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
AnnaBridge 171:3a7713b1edbc 667 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 668 struct {
AnnaBridge 171:3a7713b1edbc 669 __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
AnnaBridge 171:3a7713b1edbc 670 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 671 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 672 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 673 } RTC_MODE1_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 674 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 677 #define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
AnnaBridge 171:3a7713b1edbc 680 #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
AnnaBridge 171:3a7713b1edbc 681 #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
AnnaBridge 171:3a7713b1edbc 682 #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
AnnaBridge 171:3a7713b1edbc 683 #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
AnnaBridge 171:3a7713b1edbc 684 #define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
AnnaBridge 171:3a7713b1edbc 685 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
AnnaBridge 171:3a7713b1edbc 686 #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 687 #define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 688 #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
AnnaBridge 171:3a7713b1edbc 689 #define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 690 #define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 691
AnnaBridge 171:3a7713b1edbc 692 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 693 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 694 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 695 struct {
AnnaBridge 171:3a7713b1edbc 696 __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
AnnaBridge 171:3a7713b1edbc 697 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 698 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 699 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
AnnaBridge 171:3a7713b1edbc 700 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 701 struct {
AnnaBridge 171:3a7713b1edbc 702 __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
AnnaBridge 171:3a7713b1edbc 703 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 704 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 705 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 706 } RTC_MODE2_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 707 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709 #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 710 #define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
AnnaBridge 171:3a7713b1edbc 713 #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
AnnaBridge 171:3a7713b1edbc 714 #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
AnnaBridge 171:3a7713b1edbc 715 #define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
AnnaBridge 171:3a7713b1edbc 716 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
AnnaBridge 171:3a7713b1edbc 717 #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 718 #define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 719 #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
AnnaBridge 171:3a7713b1edbc 720 #define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
AnnaBridge 171:3a7713b1edbc 721 #define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 722
AnnaBridge 171:3a7713b1edbc 723 /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
AnnaBridge 171:3a7713b1edbc 724 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 725 typedef union {
AnnaBridge 171:3a7713b1edbc 726 struct {
AnnaBridge 171:3a7713b1edbc 727 uint8_t :7; /*!< bit: 0.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 728 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 729 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 730 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 731 } RTC_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 732 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 735 #define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 738 #define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 739 #define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 740
AnnaBridge 171:3a7713b1edbc 741 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 742 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 743 typedef union {
AnnaBridge 171:3a7713b1edbc 744 struct {
AnnaBridge 171:3a7713b1edbc 745 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
AnnaBridge 171:3a7713b1edbc 746 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 747 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 748 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 749 } RTC_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 750 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
AnnaBridge 171:3a7713b1edbc 753 #define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
AnnaBridge 171:3a7713b1edbc 754
AnnaBridge 171:3a7713b1edbc 755 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
AnnaBridge 171:3a7713b1edbc 756 #define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
AnnaBridge 171:3a7713b1edbc 757 #define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 758
AnnaBridge 171:3a7713b1edbc 759 /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
AnnaBridge 171:3a7713b1edbc 760 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 761 typedef union {
AnnaBridge 171:3a7713b1edbc 762 struct {
AnnaBridge 171:3a7713b1edbc 763 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
AnnaBridge 171:3a7713b1edbc 764 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
AnnaBridge 171:3a7713b1edbc 765 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 766 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 767 } RTC_FREQCORR_Type;
AnnaBridge 171:3a7713b1edbc 768 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
AnnaBridge 171:3a7713b1edbc 771 #define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
AnnaBridge 171:3a7713b1edbc 774 #define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
AnnaBridge 171:3a7713b1edbc 775 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
AnnaBridge 171:3a7713b1edbc 776 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
AnnaBridge 171:3a7713b1edbc 777 #define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
AnnaBridge 171:3a7713b1edbc 778 #define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
AnnaBridge 171:3a7713b1edbc 779
AnnaBridge 171:3a7713b1edbc 780 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
AnnaBridge 171:3a7713b1edbc 781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 782 typedef union {
AnnaBridge 171:3a7713b1edbc 783 struct {
AnnaBridge 171:3a7713b1edbc 784 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
AnnaBridge 171:3a7713b1edbc 785 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 786 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 787 } RTC_MODE0_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 788 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
AnnaBridge 171:3a7713b1edbc 791 #define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
AnnaBridge 171:3a7713b1edbc 794 #define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 795 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 796 #define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
AnnaBridge 171:3a7713b1edbc 799 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 800 typedef union {
AnnaBridge 171:3a7713b1edbc 801 struct {
AnnaBridge 171:3a7713b1edbc 802 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
AnnaBridge 171:3a7713b1edbc 803 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 804 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 805 } RTC_MODE1_COUNT_Type;
AnnaBridge 171:3a7713b1edbc 806 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 807
AnnaBridge 171:3a7713b1edbc 808 #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
AnnaBridge 171:3a7713b1edbc 809 #define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
AnnaBridge 171:3a7713b1edbc 810
AnnaBridge 171:3a7713b1edbc 811 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
AnnaBridge 171:3a7713b1edbc 812 #define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
AnnaBridge 171:3a7713b1edbc 813 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
AnnaBridge 171:3a7713b1edbc 814 #define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
AnnaBridge 171:3a7713b1edbc 815
AnnaBridge 171:3a7713b1edbc 816 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
AnnaBridge 171:3a7713b1edbc 817 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 818 typedef union {
AnnaBridge 171:3a7713b1edbc 819 struct {
AnnaBridge 171:3a7713b1edbc 820 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
AnnaBridge 171:3a7713b1edbc 821 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
AnnaBridge 171:3a7713b1edbc 822 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
AnnaBridge 171:3a7713b1edbc 823 uint32_t DAY:5; /*!< bit: 17..21 Day */
AnnaBridge 171:3a7713b1edbc 824 uint32_t MONTH:4; /*!< bit: 22..25 Month */
AnnaBridge 171:3a7713b1edbc 825 uint32_t YEAR:6; /*!< bit: 26..31 Year */
AnnaBridge 171:3a7713b1edbc 826 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 827 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 828 } RTC_MODE2_CLOCK_Type;
AnnaBridge 171:3a7713b1edbc 829 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831 #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
AnnaBridge 171:3a7713b1edbc 832 #define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
AnnaBridge 171:3a7713b1edbc 835 #define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
AnnaBridge 171:3a7713b1edbc 836 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
AnnaBridge 171:3a7713b1edbc 837 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
AnnaBridge 171:3a7713b1edbc 838 #define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
AnnaBridge 171:3a7713b1edbc 839 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
AnnaBridge 171:3a7713b1edbc 840 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
AnnaBridge 171:3a7713b1edbc 841 #define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
AnnaBridge 171:3a7713b1edbc 842 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
AnnaBridge 171:3a7713b1edbc 843 #define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
AnnaBridge 171:3a7713b1edbc 844 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
AnnaBridge 171:3a7713b1edbc 845 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
AnnaBridge 171:3a7713b1edbc 846 #define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
AnnaBridge 171:3a7713b1edbc 847 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
AnnaBridge 171:3a7713b1edbc 848 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
AnnaBridge 171:3a7713b1edbc 849 #define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
AnnaBridge 171:3a7713b1edbc 850 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
AnnaBridge 171:3a7713b1edbc 851 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
AnnaBridge 171:3a7713b1edbc 852 #define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
AnnaBridge 171:3a7713b1edbc 853 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
AnnaBridge 171:3a7713b1edbc 854 #define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
AnnaBridge 171:3a7713b1edbc 855
AnnaBridge 171:3a7713b1edbc 856 /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
AnnaBridge 171:3a7713b1edbc 857 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 858 typedef union {
AnnaBridge 171:3a7713b1edbc 859 struct {
AnnaBridge 171:3a7713b1edbc 860 uint16_t PER:16; /*!< bit: 0..15 Counter Period */
AnnaBridge 171:3a7713b1edbc 861 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 862 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 863 } RTC_MODE1_PER_Type;
AnnaBridge 171:3a7713b1edbc 864 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 865
AnnaBridge 171:3a7713b1edbc 866 #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
AnnaBridge 171:3a7713b1edbc 867 #define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
AnnaBridge 171:3a7713b1edbc 868
AnnaBridge 171:3a7713b1edbc 869 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
AnnaBridge 171:3a7713b1edbc 870 #define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
AnnaBridge 171:3a7713b1edbc 871 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
AnnaBridge 171:3a7713b1edbc 872 #define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
AnnaBridge 171:3a7713b1edbc 875 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 876 typedef union {
AnnaBridge 171:3a7713b1edbc 877 struct {
AnnaBridge 171:3a7713b1edbc 878 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
AnnaBridge 171:3a7713b1edbc 879 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 880 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 881 } RTC_MODE0_COMP_Type;
AnnaBridge 171:3a7713b1edbc 882 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 883
AnnaBridge 171:3a7713b1edbc 884 #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
AnnaBridge 171:3a7713b1edbc 885 #define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
AnnaBridge 171:3a7713b1edbc 886
AnnaBridge 171:3a7713b1edbc 887 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
AnnaBridge 171:3a7713b1edbc 888 #define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
AnnaBridge 171:3a7713b1edbc 889 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
AnnaBridge 171:3a7713b1edbc 890 #define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
AnnaBridge 171:3a7713b1edbc 893 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 894 typedef union {
AnnaBridge 171:3a7713b1edbc 895 struct {
AnnaBridge 171:3a7713b1edbc 896 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
AnnaBridge 171:3a7713b1edbc 897 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 898 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 899 } RTC_MODE1_COMP_Type;
AnnaBridge 171:3a7713b1edbc 900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 901
AnnaBridge 171:3a7713b1edbc 902 #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
AnnaBridge 171:3a7713b1edbc 903 #define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
AnnaBridge 171:3a7713b1edbc 906 #define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
AnnaBridge 171:3a7713b1edbc 907 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
AnnaBridge 171:3a7713b1edbc 908 #define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
AnnaBridge 171:3a7713b1edbc 911 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 912 typedef union {
AnnaBridge 171:3a7713b1edbc 913 struct {
AnnaBridge 171:3a7713b1edbc 914 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
AnnaBridge 171:3a7713b1edbc 915 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
AnnaBridge 171:3a7713b1edbc 916 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
AnnaBridge 171:3a7713b1edbc 917 uint32_t DAY:5; /*!< bit: 17..21 Day */
AnnaBridge 171:3a7713b1edbc 918 uint32_t MONTH:4; /*!< bit: 22..25 Month */
AnnaBridge 171:3a7713b1edbc 919 uint32_t YEAR:6; /*!< bit: 26..31 Year */
AnnaBridge 171:3a7713b1edbc 920 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 921 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 922 } RTC_MODE2_ALARM_Type;
AnnaBridge 171:3a7713b1edbc 923 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
AnnaBridge 171:3a7713b1edbc 926 #define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
AnnaBridge 171:3a7713b1edbc 929 #define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
AnnaBridge 171:3a7713b1edbc 930 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
AnnaBridge 171:3a7713b1edbc 931 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
AnnaBridge 171:3a7713b1edbc 932 #define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
AnnaBridge 171:3a7713b1edbc 933 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
AnnaBridge 171:3a7713b1edbc 934 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
AnnaBridge 171:3a7713b1edbc 935 #define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
AnnaBridge 171:3a7713b1edbc 936 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
AnnaBridge 171:3a7713b1edbc 937 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
AnnaBridge 171:3a7713b1edbc 938 #define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
AnnaBridge 171:3a7713b1edbc 939 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
AnnaBridge 171:3a7713b1edbc 940 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
AnnaBridge 171:3a7713b1edbc 941 #define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
AnnaBridge 171:3a7713b1edbc 942 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
AnnaBridge 171:3a7713b1edbc 943 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
AnnaBridge 171:3a7713b1edbc 944 #define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
AnnaBridge 171:3a7713b1edbc 945 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
AnnaBridge 171:3a7713b1edbc 946 #define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
AnnaBridge 171:3a7713b1edbc 947
AnnaBridge 171:3a7713b1edbc 948 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
AnnaBridge 171:3a7713b1edbc 949 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 950 typedef union {
AnnaBridge 171:3a7713b1edbc 951 struct {
AnnaBridge 171:3a7713b1edbc 952 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
AnnaBridge 171:3a7713b1edbc 953 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 954 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 955 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 956 } RTC_MODE2_MASK_Type;
AnnaBridge 171:3a7713b1edbc 957 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 958
AnnaBridge 171:3a7713b1edbc 959 #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
AnnaBridge 171:3a7713b1edbc 960 #define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
AnnaBridge 171:3a7713b1edbc 961
AnnaBridge 171:3a7713b1edbc 962 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
AnnaBridge 171:3a7713b1edbc 963 #define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 964 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
AnnaBridge 171:3a7713b1edbc 965 #define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
AnnaBridge 171:3a7713b1edbc 966 #define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
AnnaBridge 171:3a7713b1edbc 967 #define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
AnnaBridge 171:3a7713b1edbc 968 #define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
AnnaBridge 171:3a7713b1edbc 969 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
AnnaBridge 171:3a7713b1edbc 970 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
AnnaBridge 171:3a7713b1edbc 971 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
AnnaBridge 171:3a7713b1edbc 972 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 973 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 974 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 975 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 976 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 977 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 978 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
AnnaBridge 171:3a7713b1edbc 979 #define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */
AnnaBridge 171:3a7713b1edbc 980
AnnaBridge 171:3a7713b1edbc 981 /** \brief RtcMode2Alarm hardware registers */
AnnaBridge 171:3a7713b1edbc 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 983 typedef struct {
AnnaBridge 171:3a7713b1edbc 984 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
AnnaBridge 171:3a7713b1edbc 985 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
AnnaBridge 171:3a7713b1edbc 986 RoReg8 Reserved1[0x3];
AnnaBridge 171:3a7713b1edbc 987 } RtcMode2Alarm;
AnnaBridge 171:3a7713b1edbc 988 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 989
AnnaBridge 171:3a7713b1edbc 990 /** \brief RTC_MODE0 hardware registers */
AnnaBridge 171:3a7713b1edbc 991 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 992 typedef struct { /* 32-bit Counter with Single 32-bit Compare */
AnnaBridge 171:3a7713b1edbc 993 __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
AnnaBridge 171:3a7713b1edbc 994 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 995 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
AnnaBridge 171:3a7713b1edbc 996 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 997 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 998 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 999 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 1000 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
AnnaBridge 171:3a7713b1edbc 1001 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 1002 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
AnnaBridge 171:3a7713b1edbc 1003 RoReg8 Reserved2[0x3];
AnnaBridge 171:3a7713b1edbc 1004 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
AnnaBridge 171:3a7713b1edbc 1005 RoReg8 Reserved3[0x4];
AnnaBridge 171:3a7713b1edbc 1006 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
AnnaBridge 171:3a7713b1edbc 1007 } RtcMode0;
AnnaBridge 171:3a7713b1edbc 1008 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010 /** \brief RTC_MODE1 hardware registers */
AnnaBridge 171:3a7713b1edbc 1011 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1012 typedef struct { /* 16-bit Counter with Two 16-bit Compares */
AnnaBridge 171:3a7713b1edbc 1013 __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
AnnaBridge 171:3a7713b1edbc 1014 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 1015 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
AnnaBridge 171:3a7713b1edbc 1016 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1017 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1018 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1019 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 1020 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
AnnaBridge 171:3a7713b1edbc 1021 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 1022 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
AnnaBridge 171:3a7713b1edbc 1023 RoReg8 Reserved2[0x3];
AnnaBridge 171:3a7713b1edbc 1024 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
AnnaBridge 171:3a7713b1edbc 1025 RoReg8 Reserved3[0x2];
AnnaBridge 171:3a7713b1edbc 1026 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
AnnaBridge 171:3a7713b1edbc 1027 RoReg8 Reserved4[0x2];
AnnaBridge 171:3a7713b1edbc 1028 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
AnnaBridge 171:3a7713b1edbc 1029 } RtcMode1;
AnnaBridge 171:3a7713b1edbc 1030 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1031
AnnaBridge 171:3a7713b1edbc 1032 /** \brief RTC_MODE2 hardware registers */
AnnaBridge 171:3a7713b1edbc 1033 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1034 typedef struct { /* Clock/Calendar with Alarm */
AnnaBridge 171:3a7713b1edbc 1035 __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
AnnaBridge 171:3a7713b1edbc 1036 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
AnnaBridge 171:3a7713b1edbc 1037 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
AnnaBridge 171:3a7713b1edbc 1038 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1039 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1040 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1041 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 1042 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
AnnaBridge 171:3a7713b1edbc 1043 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 1044 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
AnnaBridge 171:3a7713b1edbc 1045 RoReg8 Reserved2[0x3];
AnnaBridge 171:3a7713b1edbc 1046 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
AnnaBridge 171:3a7713b1edbc 1047 RoReg8 Reserved3[0x4];
AnnaBridge 171:3a7713b1edbc 1048 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
AnnaBridge 171:3a7713b1edbc 1049 } RtcMode2;
AnnaBridge 171:3a7713b1edbc 1050 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1051
AnnaBridge 171:3a7713b1edbc 1052 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1053 typedef union {
AnnaBridge 171:3a7713b1edbc 1054 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
AnnaBridge 171:3a7713b1edbc 1055 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
AnnaBridge 171:3a7713b1edbc 1056 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
AnnaBridge 171:3a7713b1edbc 1057 } Rtc;
AnnaBridge 171:3a7713b1edbc 1058 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /*@}*/
AnnaBridge 171:3a7713b1edbc 1061
AnnaBridge 171:3a7713b1edbc 1062 #endif /* _SAMR21_RTC_COMPONENT_ */