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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_port.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for PORT
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_PORT_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_PORT_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR PORT */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_PORT Port Module */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define PORT_U2210
AnnaBridge 171:3a7713b1edbc 54 #define REV_PORT 0x100
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
AnnaBridge 171:3a7713b1edbc 61 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 62 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 63 } PORT_DIR_Type;
AnnaBridge 171:3a7713b1edbc 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
AnnaBridge 171:3a7713b1edbc 67 #define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 #define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
AnnaBridge 171:3a7713b1edbc 70 #define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 71 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
AnnaBridge 171:3a7713b1edbc 72 #define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
AnnaBridge 171:3a7713b1edbc 75 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 76 typedef union {
AnnaBridge 171:3a7713b1edbc 77 struct {
AnnaBridge 171:3a7713b1edbc 78 uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
AnnaBridge 171:3a7713b1edbc 79 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 80 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 81 } PORT_DIRCLR_Type;
AnnaBridge 171:3a7713b1edbc 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
AnnaBridge 171:3a7713b1edbc 85 #define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 #define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
AnnaBridge 171:3a7713b1edbc 88 #define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
AnnaBridge 171:3a7713b1edbc 89 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
AnnaBridge 171:3a7713b1edbc 90 #define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
AnnaBridge 171:3a7713b1edbc 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 94 typedef union {
AnnaBridge 171:3a7713b1edbc 95 struct {
AnnaBridge 171:3a7713b1edbc 96 uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
AnnaBridge 171:3a7713b1edbc 97 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 98 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 99 } PORT_DIRSET_Type;
AnnaBridge 171:3a7713b1edbc 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
AnnaBridge 171:3a7713b1edbc 103 #define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 #define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
AnnaBridge 171:3a7713b1edbc 106 #define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
AnnaBridge 171:3a7713b1edbc 107 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
AnnaBridge 171:3a7713b1edbc 108 #define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
AnnaBridge 171:3a7713b1edbc 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 112 typedef union {
AnnaBridge 171:3a7713b1edbc 113 struct {
AnnaBridge 171:3a7713b1edbc 114 uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
AnnaBridge 171:3a7713b1edbc 115 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 116 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 117 } PORT_DIRTGL_Type;
AnnaBridge 171:3a7713b1edbc 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
AnnaBridge 171:3a7713b1edbc 121 #define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 #define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
AnnaBridge 171:3a7713b1edbc 124 #define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
AnnaBridge 171:3a7713b1edbc 126 #define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
AnnaBridge 171:3a7713b1edbc 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 130 typedef union {
AnnaBridge 171:3a7713b1edbc 131 struct {
AnnaBridge 171:3a7713b1edbc 132 uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
AnnaBridge 171:3a7713b1edbc 133 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 134 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 135 } PORT_OUT_Type;
AnnaBridge 171:3a7713b1edbc 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
AnnaBridge 171:3a7713b1edbc 139 #define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 #define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
AnnaBridge 171:3a7713b1edbc 142 #define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
AnnaBridge 171:3a7713b1edbc 144 #define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
AnnaBridge 171:3a7713b1edbc 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 148 typedef union {
AnnaBridge 171:3a7713b1edbc 149 struct {
AnnaBridge 171:3a7713b1edbc 150 uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
AnnaBridge 171:3a7713b1edbc 151 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 152 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 153 } PORT_OUTCLR_Type;
AnnaBridge 171:3a7713b1edbc 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
AnnaBridge 171:3a7713b1edbc 157 #define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 #define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
AnnaBridge 171:3a7713b1edbc 160 #define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
AnnaBridge 171:3a7713b1edbc 161 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
AnnaBridge 171:3a7713b1edbc 162 #define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
AnnaBridge 171:3a7713b1edbc 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 166 typedef union {
AnnaBridge 171:3a7713b1edbc 167 struct {
AnnaBridge 171:3a7713b1edbc 168 uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
AnnaBridge 171:3a7713b1edbc 169 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 170 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 171 } PORT_OUTSET_Type;
AnnaBridge 171:3a7713b1edbc 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
AnnaBridge 171:3a7713b1edbc 175 #define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 #define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
AnnaBridge 171:3a7713b1edbc 178 #define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
AnnaBridge 171:3a7713b1edbc 179 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
AnnaBridge 171:3a7713b1edbc 180 #define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
AnnaBridge 171:3a7713b1edbc 183 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 184 typedef union {
AnnaBridge 171:3a7713b1edbc 185 struct {
AnnaBridge 171:3a7713b1edbc 186 uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
AnnaBridge 171:3a7713b1edbc 187 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 188 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 189 } PORT_OUTTGL_Type;
AnnaBridge 171:3a7713b1edbc 190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
AnnaBridge 171:3a7713b1edbc 193 #define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 #define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
AnnaBridge 171:3a7713b1edbc 196 #define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
AnnaBridge 171:3a7713b1edbc 197 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
AnnaBridge 171:3a7713b1edbc 198 #define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
AnnaBridge 171:3a7713b1edbc 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 202 typedef union {
AnnaBridge 171:3a7713b1edbc 203 struct {
AnnaBridge 171:3a7713b1edbc 204 uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
AnnaBridge 171:3a7713b1edbc 205 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 206 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 207 } PORT_IN_Type;
AnnaBridge 171:3a7713b1edbc 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
AnnaBridge 171:3a7713b1edbc 211 #define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 #define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
AnnaBridge 171:3a7713b1edbc 214 #define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
AnnaBridge 171:3a7713b1edbc 215 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
AnnaBridge 171:3a7713b1edbc 216 #define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
AnnaBridge 171:3a7713b1edbc 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 220 typedef union {
AnnaBridge 171:3a7713b1edbc 221 struct {
AnnaBridge 171:3a7713b1edbc 222 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
AnnaBridge 171:3a7713b1edbc 223 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 224 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 225 } PORT_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 229 #define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
AnnaBridge 171:3a7713b1edbc 232 #define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
AnnaBridge 171:3a7713b1edbc 233 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
AnnaBridge 171:3a7713b1edbc 234 #define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
AnnaBridge 171:3a7713b1edbc 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 238 typedef union {
AnnaBridge 171:3a7713b1edbc 239 struct {
AnnaBridge 171:3a7713b1edbc 240 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
AnnaBridge 171:3a7713b1edbc 241 uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
AnnaBridge 171:3a7713b1edbc 242 uint32_t INEN:1; /*!< bit: 17 Input Enable */
AnnaBridge 171:3a7713b1edbc 243 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
AnnaBridge 171:3a7713b1edbc 244 uint32_t :3; /*!< bit: 19..21 Reserved */
AnnaBridge 171:3a7713b1edbc 245 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
AnnaBridge 171:3a7713b1edbc 246 uint32_t :1; /*!< bit: 23 Reserved */
AnnaBridge 171:3a7713b1edbc 247 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
AnnaBridge 171:3a7713b1edbc 248 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
AnnaBridge 171:3a7713b1edbc 249 uint32_t :1; /*!< bit: 29 Reserved */
AnnaBridge 171:3a7713b1edbc 250 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
AnnaBridge 171:3a7713b1edbc 251 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
AnnaBridge 171:3a7713b1edbc 252 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 253 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 254 } PORT_WRCONFIG_Type;
AnnaBridge 171:3a7713b1edbc 255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
AnnaBridge 171:3a7713b1edbc 258 #define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
AnnaBridge 171:3a7713b1edbc 261 #define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
AnnaBridge 171:3a7713b1edbc 262 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
AnnaBridge 171:3a7713b1edbc 263 #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
AnnaBridge 171:3a7713b1edbc 264 #define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
AnnaBridge 171:3a7713b1edbc 265 #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
AnnaBridge 171:3a7713b1edbc 266 #define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos)
AnnaBridge 171:3a7713b1edbc 267 #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
AnnaBridge 171:3a7713b1edbc 268 #define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
AnnaBridge 171:3a7713b1edbc 269 #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
AnnaBridge 171:3a7713b1edbc 270 #define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
AnnaBridge 171:3a7713b1edbc 271 #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
AnnaBridge 171:3a7713b1edbc 272 #define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
AnnaBridge 171:3a7713b1edbc 273 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
AnnaBridge 171:3a7713b1edbc 274 #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
AnnaBridge 171:3a7713b1edbc 275 #define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
AnnaBridge 171:3a7713b1edbc 276 #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
AnnaBridge 171:3a7713b1edbc 277 #define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
AnnaBridge 171:3a7713b1edbc 278 #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
AnnaBridge 171:3a7713b1edbc 279 #define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
AnnaBridge 171:3a7713b1edbc 280 #define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
AnnaBridge 171:3a7713b1edbc 283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 284 typedef union {
AnnaBridge 171:3a7713b1edbc 285 struct {
AnnaBridge 171:3a7713b1edbc 286 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
AnnaBridge 171:3a7713b1edbc 287 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
AnnaBridge 171:3a7713b1edbc 288 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 289 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 290 } PORT_PMUX_Type;
AnnaBridge 171:3a7713b1edbc 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
AnnaBridge 171:3a7713b1edbc 294 #define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
AnnaBridge 171:3a7713b1edbc 297 #define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 298 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
AnnaBridge 171:3a7713b1edbc 299 #define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
AnnaBridge 171:3a7713b1edbc 300 #define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
AnnaBridge 171:3a7713b1edbc 301 #define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
AnnaBridge 171:3a7713b1edbc 302 #define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
AnnaBridge 171:3a7713b1edbc 303 #define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
AnnaBridge 171:3a7713b1edbc 304 #define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
AnnaBridge 171:3a7713b1edbc 305 #define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
AnnaBridge 171:3a7713b1edbc 306 #define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
AnnaBridge 171:3a7713b1edbc 307 #define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 309 #define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 310 #define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 311 #define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 312 #define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 313 #define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 314 #define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
AnnaBridge 171:3a7713b1edbc 315 #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
AnnaBridge 171:3a7713b1edbc 316 #define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 317 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
AnnaBridge 171:3a7713b1edbc 318 #define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
AnnaBridge 171:3a7713b1edbc 319 #define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
AnnaBridge 171:3a7713b1edbc 320 #define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
AnnaBridge 171:3a7713b1edbc 321 #define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
AnnaBridge 171:3a7713b1edbc 322 #define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
AnnaBridge 171:3a7713b1edbc 323 #define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
AnnaBridge 171:3a7713b1edbc 324 #define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
AnnaBridge 171:3a7713b1edbc 325 #define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
AnnaBridge 171:3a7713b1edbc 326 #define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 328 #define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 329 #define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 330 #define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 331 #define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 332 #define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 333 #define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
AnnaBridge 171:3a7713b1edbc 334 #define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
AnnaBridge 171:3a7713b1edbc 337 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 338 typedef union {
AnnaBridge 171:3a7713b1edbc 339 struct {
AnnaBridge 171:3a7713b1edbc 340 uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
AnnaBridge 171:3a7713b1edbc 341 uint8_t INEN:1; /*!< bit: 1 Input Enable */
AnnaBridge 171:3a7713b1edbc 342 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
AnnaBridge 171:3a7713b1edbc 343 uint8_t :3; /*!< bit: 3.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 344 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
AnnaBridge 171:3a7713b1edbc 345 uint8_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 346 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 347 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 348 } PORT_PINCFG_Type;
AnnaBridge 171:3a7713b1edbc 349 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
AnnaBridge 171:3a7713b1edbc 352 #define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
AnnaBridge 171:3a7713b1edbc 355 #define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos)
AnnaBridge 171:3a7713b1edbc 356 #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
AnnaBridge 171:3a7713b1edbc 357 #define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos)
AnnaBridge 171:3a7713b1edbc 358 #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
AnnaBridge 171:3a7713b1edbc 359 #define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos)
AnnaBridge 171:3a7713b1edbc 360 #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
AnnaBridge 171:3a7713b1edbc 361 #define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos)
AnnaBridge 171:3a7713b1edbc 362 #define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 /** \brief PortGroup hardware registers */
AnnaBridge 171:3a7713b1edbc 365 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 366 typedef struct {
AnnaBridge 171:3a7713b1edbc 367 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
AnnaBridge 171:3a7713b1edbc 368 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
AnnaBridge 171:3a7713b1edbc 369 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
AnnaBridge 171:3a7713b1edbc 370 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
AnnaBridge 171:3a7713b1edbc 371 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
AnnaBridge 171:3a7713b1edbc 372 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
AnnaBridge 171:3a7713b1edbc 373 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
AnnaBridge 171:3a7713b1edbc 374 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
AnnaBridge 171:3a7713b1edbc 375 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
AnnaBridge 171:3a7713b1edbc 376 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
AnnaBridge 171:3a7713b1edbc 377 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
AnnaBridge 171:3a7713b1edbc 378 RoReg8 Reserved1[0x4];
AnnaBridge 171:3a7713b1edbc 379 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
AnnaBridge 171:3a7713b1edbc 380 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
AnnaBridge 171:3a7713b1edbc 381 RoReg8 Reserved2[0x20];
AnnaBridge 171:3a7713b1edbc 382 } PortGroup;
AnnaBridge 171:3a7713b1edbc 383 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /** \brief PORT hardware registers */
AnnaBridge 171:3a7713b1edbc 386 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 387 typedef struct {
AnnaBridge 171:3a7713b1edbc 388 PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
AnnaBridge 171:3a7713b1edbc 389 } Port;
AnnaBridge 171:3a7713b1edbc 390 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 391 #define SECTION_PORT_IOBUS
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /*@}*/
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 #endif /* _SAMR21_PORT_COMPONENT_ */