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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_pm.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for PM
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_PM_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_PM_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR PM */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_PM Power Manager */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define PM_U2206
AnnaBridge 171:3a7713b1edbc 54 #define REV_PM 0x201
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 60 } PM_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 64 #define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 #define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
AnnaBridge 171:3a7713b1edbc 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 70 typedef union {
AnnaBridge 171:3a7713b1edbc 71 struct {
AnnaBridge 171:3a7713b1edbc 72 uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
AnnaBridge 171:3a7713b1edbc 73 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 74 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 75 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 76 } PM_SLEEP_Type;
AnnaBridge 171:3a7713b1edbc 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
AnnaBridge 171:3a7713b1edbc 80 #define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
AnnaBridge 171:3a7713b1edbc 83 #define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
AnnaBridge 171:3a7713b1edbc 84 #define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
AnnaBridge 171:3a7713b1edbc 85 #define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
AnnaBridge 171:3a7713b1edbc 86 #define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
AnnaBridge 171:3a7713b1edbc 87 #define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
AnnaBridge 171:3a7713b1edbc 88 #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
AnnaBridge 171:3a7713b1edbc 89 #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
AnnaBridge 171:3a7713b1edbc 91 #define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
AnnaBridge 171:3a7713b1edbc 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 95 typedef union {
AnnaBridge 171:3a7713b1edbc 96 struct {
AnnaBridge 171:3a7713b1edbc 97 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 98 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 99 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 100 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 101 } PM_CPUSEL_Type;
AnnaBridge 171:3a7713b1edbc 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
AnnaBridge 171:3a7713b1edbc 105 #define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 108 #define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 109 #define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
AnnaBridge 171:3a7713b1edbc 110 #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
AnnaBridge 171:3a7713b1edbc 111 #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
AnnaBridge 171:3a7713b1edbc 112 #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
AnnaBridge 171:3a7713b1edbc 113 #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */
AnnaBridge 171:3a7713b1edbc 114 #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */
AnnaBridge 171:3a7713b1edbc 115 #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */
AnnaBridge 171:3a7713b1edbc 116 #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */
AnnaBridge 171:3a7713b1edbc 117 #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */
AnnaBridge 171:3a7713b1edbc 118 #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 119 #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 121 #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 122 #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 123 #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 124 #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
AnnaBridge 171:3a7713b1edbc 126 #define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
AnnaBridge 171:3a7713b1edbc 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 130 typedef union {
AnnaBridge 171:3a7713b1edbc 131 struct {
AnnaBridge 171:3a7713b1edbc 132 uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 133 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 134 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 135 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 136 } PM_APBASEL_Type;
AnnaBridge 171:3a7713b1edbc 137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
AnnaBridge 171:3a7713b1edbc 140 #define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 143 #define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 144 #define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
AnnaBridge 171:3a7713b1edbc 145 #define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
AnnaBridge 171:3a7713b1edbc 146 #define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
AnnaBridge 171:3a7713b1edbc 147 #define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
AnnaBridge 171:3a7713b1edbc 148 #define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */
AnnaBridge 171:3a7713b1edbc 149 #define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */
AnnaBridge 171:3a7713b1edbc 150 #define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */
AnnaBridge 171:3a7713b1edbc 151 #define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */
AnnaBridge 171:3a7713b1edbc 152 #define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */
AnnaBridge 171:3a7713b1edbc 153 #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 154 #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 155 #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 156 #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 157 #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 158 #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 159 #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 160 #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
AnnaBridge 171:3a7713b1edbc 161 #define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
AnnaBridge 171:3a7713b1edbc 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 165 typedef union {
AnnaBridge 171:3a7713b1edbc 166 struct {
AnnaBridge 171:3a7713b1edbc 167 uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 168 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 169 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 170 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 171 } PM_APBBSEL_Type;
AnnaBridge 171:3a7713b1edbc 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
AnnaBridge 171:3a7713b1edbc 175 #define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 178 #define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 179 #define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
AnnaBridge 171:3a7713b1edbc 180 #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
AnnaBridge 171:3a7713b1edbc 181 #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
AnnaBridge 171:3a7713b1edbc 182 #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
AnnaBridge 171:3a7713b1edbc 183 #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */
AnnaBridge 171:3a7713b1edbc 184 #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */
AnnaBridge 171:3a7713b1edbc 185 #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */
AnnaBridge 171:3a7713b1edbc 186 #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */
AnnaBridge 171:3a7713b1edbc 187 #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */
AnnaBridge 171:3a7713b1edbc 188 #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 189 #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 190 #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 192 #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 193 #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 194 #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 195 #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
AnnaBridge 171:3a7713b1edbc 196 #define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
AnnaBridge 171:3a7713b1edbc 199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 200 typedef union {
AnnaBridge 171:3a7713b1edbc 201 struct {
AnnaBridge 171:3a7713b1edbc 202 uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 203 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 204 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 205 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 206 } PM_APBCSEL_Type;
AnnaBridge 171:3a7713b1edbc 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
AnnaBridge 171:3a7713b1edbc 210 #define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
AnnaBridge 171:3a7713b1edbc 213 #define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 214 #define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
AnnaBridge 171:3a7713b1edbc 215 #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
AnnaBridge 171:3a7713b1edbc 216 #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
AnnaBridge 171:3a7713b1edbc 217 #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
AnnaBridge 171:3a7713b1edbc 218 #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */
AnnaBridge 171:3a7713b1edbc 219 #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */
AnnaBridge 171:3a7713b1edbc 220 #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */
AnnaBridge 171:3a7713b1edbc 221 #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */
AnnaBridge 171:3a7713b1edbc 222 #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */
AnnaBridge 171:3a7713b1edbc 223 #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 224 #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 225 #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 226 #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 227 #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 229 #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 230 #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
AnnaBridge 171:3a7713b1edbc 231 #define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
AnnaBridge 171:3a7713b1edbc 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 235 typedef union {
AnnaBridge 171:3a7713b1edbc 236 struct {
AnnaBridge 171:3a7713b1edbc 237 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 238 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 239 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 240 uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 241 uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 242 uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 243 uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 244 uint32_t :25; /*!< bit: 7..31 Reserved */
AnnaBridge 171:3a7713b1edbc 245 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 246 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 247 } PM_AHBMASK_Type;
AnnaBridge 171:3a7713b1edbc 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
AnnaBridge 171:3a7713b1edbc 251 #define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 254 #define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos)
AnnaBridge 171:3a7713b1edbc 255 #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 256 #define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos)
AnnaBridge 171:3a7713b1edbc 257 #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 258 #define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos)
AnnaBridge 171:3a7713b1edbc 259 #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 260 #define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos)
AnnaBridge 171:3a7713b1edbc 261 #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 262 #define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
AnnaBridge 171:3a7713b1edbc 263 #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 264 #define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos)
AnnaBridge 171:3a7713b1edbc 265 #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
AnnaBridge 171:3a7713b1edbc 266 #define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos)
AnnaBridge 171:3a7713b1edbc 267 #define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
AnnaBridge 171:3a7713b1edbc 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 271 typedef union {
AnnaBridge 171:3a7713b1edbc 272 struct {
AnnaBridge 171:3a7713b1edbc 273 uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 274 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 275 uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 276 uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 277 uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 278 uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 279 uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 280 uint32_t :25; /*!< bit: 7..31 Reserved */
AnnaBridge 171:3a7713b1edbc 281 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 282 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 283 } PM_APBAMASK_Type;
AnnaBridge 171:3a7713b1edbc 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
AnnaBridge 171:3a7713b1edbc 287 #define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 290 #define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos)
AnnaBridge 171:3a7713b1edbc 291 #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 292 #define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos)
AnnaBridge 171:3a7713b1edbc 293 #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 294 #define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
AnnaBridge 171:3a7713b1edbc 295 #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 296 #define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos)
AnnaBridge 171:3a7713b1edbc 297 #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 298 #define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos)
AnnaBridge 171:3a7713b1edbc 299 #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 300 #define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos)
AnnaBridge 171:3a7713b1edbc 301 #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 302 #define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos)
AnnaBridge 171:3a7713b1edbc 303 #define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
AnnaBridge 171:3a7713b1edbc 306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 307 typedef union {
AnnaBridge 171:3a7713b1edbc 308 struct {
AnnaBridge 171:3a7713b1edbc 309 uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 310 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 311 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 312 uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 313 uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 314 uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 315 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 316 uint32_t :25; /*!< bit: 7..31 Reserved */
AnnaBridge 171:3a7713b1edbc 317 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 318 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 319 } PM_APBBMASK_Type;
AnnaBridge 171:3a7713b1edbc 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
AnnaBridge 171:3a7713b1edbc 323 #define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 326 #define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 328 #define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos)
AnnaBridge 171:3a7713b1edbc 329 #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 330 #define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
AnnaBridge 171:3a7713b1edbc 331 #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 332 #define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos)
AnnaBridge 171:3a7713b1edbc 333 #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 334 #define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos)
AnnaBridge 171:3a7713b1edbc 335 #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 336 #define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos)
AnnaBridge 171:3a7713b1edbc 337 #define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 338 #define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos)
AnnaBridge 171:3a7713b1edbc 339 #define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
AnnaBridge 171:3a7713b1edbc 342 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 343 typedef union {
AnnaBridge 171:3a7713b1edbc 344 struct {
AnnaBridge 171:3a7713b1edbc 345 uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 346 uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 347 uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 348 uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 349 uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 350 uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 351 uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 352 uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 353 uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 354 uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 355 uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 356 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 357 uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 358 uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 359 uint32_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 360 uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 361 uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 362 uint32_t :1; /*!< bit: 18 Reserved */
AnnaBridge 171:3a7713b1edbc 363 uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 364 uint32_t :1; /*!< bit: 20 Reserved */
AnnaBridge 171:3a7713b1edbc 365 uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 366 uint32_t :10; /*!< bit: 22..31 Reserved */
AnnaBridge 171:3a7713b1edbc 367 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 368 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 369 } PM_APBCMASK_Type;
AnnaBridge 171:3a7713b1edbc 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
AnnaBridge 171:3a7713b1edbc 373 #define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 376 #define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
AnnaBridge 171:3a7713b1edbc 377 #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 378 #define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos)
AnnaBridge 171:3a7713b1edbc 379 #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 380 #define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos)
AnnaBridge 171:3a7713b1edbc 381 #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 382 #define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
AnnaBridge 171:3a7713b1edbc 383 #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 384 #define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
AnnaBridge 171:3a7713b1edbc 385 #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 386 #define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 388 #define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
AnnaBridge 171:3a7713b1edbc 389 #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 390 #define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
AnnaBridge 171:3a7713b1edbc 391 #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 392 #define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
AnnaBridge 171:3a7713b1edbc 393 #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 394 #define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
AnnaBridge 171:3a7713b1edbc 395 #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 396 #define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
AnnaBridge 171:3a7713b1edbc 397 #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 398 #define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
AnnaBridge 171:3a7713b1edbc 399 #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 400 #define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
AnnaBridge 171:3a7713b1edbc 401 #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 402 #define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
AnnaBridge 171:3a7713b1edbc 403 #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 404 #define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
AnnaBridge 171:3a7713b1edbc 405 #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 406 #define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
AnnaBridge 171:3a7713b1edbc 407 #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 408 #define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
AnnaBridge 171:3a7713b1edbc 409 #define PM_APBCMASK_RFCTRL_Pos 21 /**< \brief (PM_APBCMASK) RFCTRL APB Clock Enable */
AnnaBridge 171:3a7713b1edbc 410 #define PM_APBCMASK_RFCTRL (0x1ul << PM_APBCMASK_RFCTRL_Pos)
AnnaBridge 171:3a7713b1edbc 411 #define PM_APBCMASK_MASK 0x002B3FFFul /**< \brief (PM_APBCMASK) MASK Register */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 414 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 415 typedef union {
AnnaBridge 171:3a7713b1edbc 416 struct {
AnnaBridge 171:3a7713b1edbc 417 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 418 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 419 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 420 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 421 } PM_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 422 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 425 #define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 428 #define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
AnnaBridge 171:3a7713b1edbc 429 #define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 433 typedef union {
AnnaBridge 171:3a7713b1edbc 434 struct {
AnnaBridge 171:3a7713b1edbc 435 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 436 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 437 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 438 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 439 } PM_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 440 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 443 #define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 444
AnnaBridge 171:3a7713b1edbc 445 #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 446 #define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
AnnaBridge 171:3a7713b1edbc 447 #define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 451 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 452 struct {
AnnaBridge 171:3a7713b1edbc 453 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
AnnaBridge 171:3a7713b1edbc 454 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 455 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 456 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 457 } PM_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 458 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 461 #define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463 #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
AnnaBridge 171:3a7713b1edbc 464 #define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
AnnaBridge 171:3a7713b1edbc 465 #define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
AnnaBridge 171:3a7713b1edbc 468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 469 typedef union {
AnnaBridge 171:3a7713b1edbc 470 struct {
AnnaBridge 171:3a7713b1edbc 471 uint8_t POR:1; /*!< bit: 0 Power On Reset */
AnnaBridge 171:3a7713b1edbc 472 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
AnnaBridge 171:3a7713b1edbc 473 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
AnnaBridge 171:3a7713b1edbc 474 uint8_t :1; /*!< bit: 3 Reserved */
AnnaBridge 171:3a7713b1edbc 475 uint8_t EXT:1; /*!< bit: 4 External Reset */
AnnaBridge 171:3a7713b1edbc 476 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
AnnaBridge 171:3a7713b1edbc 477 uint8_t SYST:1; /*!< bit: 6 System Reset Request */
AnnaBridge 171:3a7713b1edbc 478 uint8_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 479 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 480 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 481 } PM_RCAUSE_Type;
AnnaBridge 171:3a7713b1edbc 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
AnnaBridge 171:3a7713b1edbc 485 #define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
AnnaBridge 171:3a7713b1edbc 488 #define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos)
AnnaBridge 171:3a7713b1edbc 489 #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
AnnaBridge 171:3a7713b1edbc 490 #define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos)
AnnaBridge 171:3a7713b1edbc 491 #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
AnnaBridge 171:3a7713b1edbc 492 #define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos)
AnnaBridge 171:3a7713b1edbc 493 #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
AnnaBridge 171:3a7713b1edbc 494 #define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos)
AnnaBridge 171:3a7713b1edbc 495 #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
AnnaBridge 171:3a7713b1edbc 496 #define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos)
AnnaBridge 171:3a7713b1edbc 497 #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
AnnaBridge 171:3a7713b1edbc 498 #define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos)
AnnaBridge 171:3a7713b1edbc 499 #define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /** \brief PM hardware registers */
AnnaBridge 171:3a7713b1edbc 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 503 typedef struct {
AnnaBridge 171:3a7713b1edbc 504 __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
AnnaBridge 171:3a7713b1edbc 505 __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
AnnaBridge 171:3a7713b1edbc 506 RoReg8 Reserved1[0x6];
AnnaBridge 171:3a7713b1edbc 507 __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
AnnaBridge 171:3a7713b1edbc 508 __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
AnnaBridge 171:3a7713b1edbc 509 __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
AnnaBridge 171:3a7713b1edbc 510 __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
AnnaBridge 171:3a7713b1edbc 511 RoReg8 Reserved2[0x8];
AnnaBridge 171:3a7713b1edbc 512 __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
AnnaBridge 171:3a7713b1edbc 513 __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
AnnaBridge 171:3a7713b1edbc 514 __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
AnnaBridge 171:3a7713b1edbc 515 __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
AnnaBridge 171:3a7713b1edbc 516 RoReg8 Reserved3[0x10];
AnnaBridge 171:3a7713b1edbc 517 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 518 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 519 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 520 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 521 __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
AnnaBridge 171:3a7713b1edbc 522 } Pm;
AnnaBridge 171:3a7713b1edbc 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 /*@}*/
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 #endif /* _SAMR21_PM_COMPONENT_ */