mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_nvmctrl.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for NVMCTRL
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_NVMCTRL_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_NVMCTRL_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR NVMCTRL */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_NVMCTRL Non-Volatile Memory Controller */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define NVMCTRL_U2207
AnnaBridge 171:3a7713b1edbc 54 #define REV_NVMCTRL 0x106
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint16_t CMD:7; /*!< bit: 0.. 6 Command */
AnnaBridge 171:3a7713b1edbc 61 uint16_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 62 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
AnnaBridge 171:3a7713b1edbc 63 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 64 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 65 } NVMCTRL_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
AnnaBridge 171:3a7713b1edbc 69 #define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
AnnaBridge 171:3a7713b1edbc 72 #define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 73 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 74 #define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
AnnaBridge 171:3a7713b1edbc 75 #define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
AnnaBridge 171:3a7713b1edbc 76 #define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
AnnaBridge 171:3a7713b1edbc 77 #define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
AnnaBridge 171:3a7713b1edbc 78 #define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
AnnaBridge 171:3a7713b1edbc 79 #define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
AnnaBridge 171:3a7713b1edbc 80 #define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
AnnaBridge 171:3a7713b1edbc 81 #define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
AnnaBridge 171:3a7713b1edbc 82 #define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
AnnaBridge 171:3a7713b1edbc 83 #define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
AnnaBridge 171:3a7713b1edbc 84 #define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
AnnaBridge 171:3a7713b1edbc 85 #define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
AnnaBridge 171:3a7713b1edbc 86 #define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
AnnaBridge 171:3a7713b1edbc 87 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 88 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 89 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 91 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 92 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 93 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 94 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 95 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 96 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 97 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 98 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 99 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 100 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
AnnaBridge 171:3a7713b1edbc 101 #define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
AnnaBridge 171:3a7713b1edbc 102 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
AnnaBridge 171:3a7713b1edbc 103 #define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
AnnaBridge 171:3a7713b1edbc 104 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
AnnaBridge 171:3a7713b1edbc 105 #define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
AnnaBridge 171:3a7713b1edbc 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 109 typedef union {
AnnaBridge 171:3a7713b1edbc 110 struct {
AnnaBridge 171:3a7713b1edbc 111 uint32_t :1; /*!< bit: 0 Reserved */
AnnaBridge 171:3a7713b1edbc 112 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
AnnaBridge 171:3a7713b1edbc 113 uint32_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 114 uint32_t MANW:1; /*!< bit: 7 Manual Write */
AnnaBridge 171:3a7713b1edbc 115 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
AnnaBridge 171:3a7713b1edbc 116 uint32_t :6; /*!< bit: 10..15 Reserved */
AnnaBridge 171:3a7713b1edbc 117 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
AnnaBridge 171:3a7713b1edbc 118 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
AnnaBridge 171:3a7713b1edbc 119 uint32_t :13; /*!< bit: 19..31 Reserved */
AnnaBridge 171:3a7713b1edbc 120 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 121 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 122 } NVMCTRL_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
AnnaBridge 171:3a7713b1edbc 126 #define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
AnnaBridge 171:3a7713b1edbc 129 #define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
AnnaBridge 171:3a7713b1edbc 130 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
AnnaBridge 171:3a7713b1edbc 131 #define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
AnnaBridge 171:3a7713b1edbc 132 #define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
AnnaBridge 171:3a7713b1edbc 133 #define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
AnnaBridge 171:3a7713b1edbc 134 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
AnnaBridge 171:3a7713b1edbc 135 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
AnnaBridge 171:3a7713b1edbc 136 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
AnnaBridge 171:3a7713b1edbc 137 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
AnnaBridge 171:3a7713b1edbc 138 #define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
AnnaBridge 171:3a7713b1edbc 139 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
AnnaBridge 171:3a7713b1edbc 140 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
AnnaBridge 171:3a7713b1edbc 142 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
AnnaBridge 171:3a7713b1edbc 143 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
AnnaBridge 171:3a7713b1edbc 144 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
AnnaBridge 171:3a7713b1edbc 145 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
AnnaBridge 171:3a7713b1edbc 146 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
AnnaBridge 171:3a7713b1edbc 148 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
AnnaBridge 171:3a7713b1edbc 149 #define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
AnnaBridge 171:3a7713b1edbc 150 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
AnnaBridge 171:3a7713b1edbc 151 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
AnnaBridge 171:3a7713b1edbc 152 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
AnnaBridge 171:3a7713b1edbc 153 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
AnnaBridge 171:3a7713b1edbc 154 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
AnnaBridge 171:3a7713b1edbc 155 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
AnnaBridge 171:3a7713b1edbc 156 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
AnnaBridge 171:3a7713b1edbc 157 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
AnnaBridge 171:3a7713b1edbc 158 #define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
AnnaBridge 171:3a7713b1edbc 159 #define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
AnnaBridge 171:3a7713b1edbc 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 163 typedef union {
AnnaBridge 171:3a7713b1edbc 164 struct {
AnnaBridge 171:3a7713b1edbc 165 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
AnnaBridge 171:3a7713b1edbc 166 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
AnnaBridge 171:3a7713b1edbc 167 uint32_t :13; /*!< bit: 19..31 Reserved */
AnnaBridge 171:3a7713b1edbc 168 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 169 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 170 } NVMCTRL_PARAM_Type;
AnnaBridge 171:3a7713b1edbc 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
AnnaBridge 171:3a7713b1edbc 174 #define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
AnnaBridge 171:3a7713b1edbc 177 #define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
AnnaBridge 171:3a7713b1edbc 178 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
AnnaBridge 171:3a7713b1edbc 179 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
AnnaBridge 171:3a7713b1edbc 180 #define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 181 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
AnnaBridge 171:3a7713b1edbc 182 #define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
AnnaBridge 171:3a7713b1edbc 183 #define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
AnnaBridge 171:3a7713b1edbc 184 #define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
AnnaBridge 171:3a7713b1edbc 185 #define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */
AnnaBridge 171:3a7713b1edbc 186 #define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */
AnnaBridge 171:3a7713b1edbc 187 #define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */
AnnaBridge 171:3a7713b1edbc 188 #define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */
AnnaBridge 171:3a7713b1edbc 189 #define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */
AnnaBridge 171:3a7713b1edbc 190 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 192 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 193 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 194 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 195 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 196 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 197 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 198 #define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 202 typedef union {
AnnaBridge 171:3a7713b1edbc 203 struct {
AnnaBridge 171:3a7713b1edbc 204 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 205 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 206 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 207 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 208 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 209 } NVMCTRL_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 213 #define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 216 #define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
AnnaBridge 171:3a7713b1edbc 217 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 218 #define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 219 #define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 223 typedef union {
AnnaBridge 171:3a7713b1edbc 224 struct {
AnnaBridge 171:3a7713b1edbc 225 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 226 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 227 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 228 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 229 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 230 } NVMCTRL_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 234 #define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 237 #define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos)
AnnaBridge 171:3a7713b1edbc 238 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 239 #define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 240 #define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 244 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 245 struct {
AnnaBridge 171:3a7713b1edbc 246 __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
AnnaBridge 171:3a7713b1edbc 247 __I uint8_t ERROR:1; /*!< bit: 1 Error */
AnnaBridge 171:3a7713b1edbc 248 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 249 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 250 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 251 } NVMCTRL_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 252 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 255 #define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
AnnaBridge 171:3a7713b1edbc 258 #define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
AnnaBridge 171:3a7713b1edbc 259 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
AnnaBridge 171:3a7713b1edbc 260 #define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 261 #define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
AnnaBridge 171:3a7713b1edbc 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 265 typedef union {
AnnaBridge 171:3a7713b1edbc 266 struct {
AnnaBridge 171:3a7713b1edbc 267 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
AnnaBridge 171:3a7713b1edbc 268 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
AnnaBridge 171:3a7713b1edbc 269 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
AnnaBridge 171:3a7713b1edbc 270 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
AnnaBridge 171:3a7713b1edbc 271 uint16_t NVME:1; /*!< bit: 4 NVM Error */
AnnaBridge 171:3a7713b1edbc 272 uint16_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 273 uint16_t SB:1; /*!< bit: 8 Security Bit Status */
AnnaBridge 171:3a7713b1edbc 274 uint16_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 275 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 276 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 277 } NVMCTRL_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 281 #define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
AnnaBridge 171:3a7713b1edbc 284 #define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos)
AnnaBridge 171:3a7713b1edbc 285 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
AnnaBridge 171:3a7713b1edbc 286 #define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
AnnaBridge 171:3a7713b1edbc 287 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
AnnaBridge 171:3a7713b1edbc 288 #define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
AnnaBridge 171:3a7713b1edbc 289 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
AnnaBridge 171:3a7713b1edbc 290 #define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
AnnaBridge 171:3a7713b1edbc 291 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
AnnaBridge 171:3a7713b1edbc 292 #define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos)
AnnaBridge 171:3a7713b1edbc 293 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
AnnaBridge 171:3a7713b1edbc 294 #define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos)
AnnaBridge 171:3a7713b1edbc 295 #define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
AnnaBridge 171:3a7713b1edbc 298 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 299 typedef union {
AnnaBridge 171:3a7713b1edbc 300 struct {
AnnaBridge 171:3a7713b1edbc 301 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
AnnaBridge 171:3a7713b1edbc 302 uint32_t :10; /*!< bit: 22..31 Reserved */
AnnaBridge 171:3a7713b1edbc 303 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 304 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 305 } NVMCTRL_ADDR_Type;
AnnaBridge 171:3a7713b1edbc 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
AnnaBridge 171:3a7713b1edbc 309 #define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
AnnaBridge 171:3a7713b1edbc 312 #define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 313 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 314 #define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
AnnaBridge 171:3a7713b1edbc 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 318 typedef union {
AnnaBridge 171:3a7713b1edbc 319 struct {
AnnaBridge 171:3a7713b1edbc 320 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
AnnaBridge 171:3a7713b1edbc 321 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 322 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 323 } NVMCTRL_LOCK_Type;
AnnaBridge 171:3a7713b1edbc 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
AnnaBridge 171:3a7713b1edbc 329 #define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
AnnaBridge 171:3a7713b1edbc 330 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
AnnaBridge 171:3a7713b1edbc 331 #define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 /** \brief NVMCTRL APB hardware registers */
AnnaBridge 171:3a7713b1edbc 334 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 335 typedef struct {
AnnaBridge 171:3a7713b1edbc 336 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
AnnaBridge 171:3a7713b1edbc 337 RoReg8 Reserved1[0x2];
AnnaBridge 171:3a7713b1edbc 338 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
AnnaBridge 171:3a7713b1edbc 339 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
AnnaBridge 171:3a7713b1edbc 340 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 341 RoReg8 Reserved2[0x3];
AnnaBridge 171:3a7713b1edbc 342 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 343 RoReg8 Reserved3[0x3];
AnnaBridge 171:3a7713b1edbc 344 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 345 RoReg8 Reserved4[0x3];
AnnaBridge 171:3a7713b1edbc 346 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
AnnaBridge 171:3a7713b1edbc 347 RoReg8 Reserved5[0x2];
AnnaBridge 171:3a7713b1edbc 348 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
AnnaBridge 171:3a7713b1edbc 349 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
AnnaBridge 171:3a7713b1edbc 350 } Nvmctrl;
AnnaBridge 171:3a7713b1edbc 351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 352 #define SECTION_NVMCTRL_CAL
AnnaBridge 171:3a7713b1edbc 353 #define SECTION_NVMCTRL_LOCKBIT
AnnaBridge 171:3a7713b1edbc 354 #define SECTION_NVMCTRL_OTP1
AnnaBridge 171:3a7713b1edbc 355 #define SECTION_NVMCTRL_OTP2
AnnaBridge 171:3a7713b1edbc 356 #define SECTION_NVMCTRL_OTP4
AnnaBridge 171:3a7713b1edbc 357 #define SECTION_NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 358 #define SECTION_NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /*@}*/
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /* ************************************************************************** */
AnnaBridge 171:3a7713b1edbc 363 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
AnnaBridge 171:3a7713b1edbc 364 /* ************************************************************************** */
AnnaBridge 171:3a7713b1edbc 365 /** \addtogroup fuses_api Peripheral Software API */
AnnaBridge 171:3a7713b1edbc 366 /*@{*/
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 #define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 370 #define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
AnnaBridge 171:3a7713b1edbc 371 #define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
AnnaBridge 171:3a7713b1edbc 372 #define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 #define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
AnnaBridge 171:3a7713b1edbc 375 #define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
AnnaBridge 171:3a7713b1edbc 376 #define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
AnnaBridge 171:3a7713b1edbc 377 #define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 #define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 380 #define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
AnnaBridge 171:3a7713b1edbc 381 #define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
AnnaBridge 171:3a7713b1edbc 382 #define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
AnnaBridge 171:3a7713b1edbc 383
AnnaBridge 171:3a7713b1edbc 384 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 385 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
AnnaBridge 171:3a7713b1edbc 386 #define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 390 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
AnnaBridge 171:3a7713b1edbc 391 #define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
AnnaBridge 171:3a7713b1edbc 392 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 #define FUSES_BOD33_EN_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 395 #define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
AnnaBridge 171:3a7713b1edbc 396 #define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos)
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
AnnaBridge 171:3a7713b1edbc 399 #define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
AnnaBridge 171:3a7713b1edbc 400 #define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos)
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 403 #define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
AnnaBridge 171:3a7713b1edbc 404 #define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
AnnaBridge 171:3a7713b1edbc 405 #define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
AnnaBridge 171:3a7713b1edbc 408 #define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
AnnaBridge 171:3a7713b1edbc 409 #define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
AnnaBridge 171:3a7713b1edbc 410 #define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 #define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
AnnaBridge 171:3a7713b1edbc 413 #define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
AnnaBridge 171:3a7713b1edbc 414 #define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
AnnaBridge 171:3a7713b1edbc 415 #define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
AnnaBridge 171:3a7713b1edbc 416
AnnaBridge 171:3a7713b1edbc 417 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
AnnaBridge 171:3a7713b1edbc 418 #define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
AnnaBridge 171:3a7713b1edbc 419 #define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
AnnaBridge 171:3a7713b1edbc 420 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 423 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
AnnaBridge 171:3a7713b1edbc 424 #define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
AnnaBridge 171:3a7713b1edbc 425 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 428 #define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
AnnaBridge 171:3a7713b1edbc 429 #define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
AnnaBridge 171:3a7713b1edbc 430 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 #define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 433 #define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
AnnaBridge 171:3a7713b1edbc 434 #define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
AnnaBridge 171:3a7713b1edbc 435 #define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 #define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
AnnaBridge 171:3a7713b1edbc 438 #define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
AnnaBridge 171:3a7713b1edbc 439 #define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
AnnaBridge 171:3a7713b1edbc 440 #define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 443 #define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
AnnaBridge 171:3a7713b1edbc 444 #define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
AnnaBridge 171:3a7713b1edbc 445 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 448 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
AnnaBridge 171:3a7713b1edbc 449 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
AnnaBridge 171:3a7713b1edbc 450 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
AnnaBridge 171:3a7713b1edbc 453 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
AnnaBridge 171:3a7713b1edbc 454 #define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
AnnaBridge 171:3a7713b1edbc 455 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 458 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
AnnaBridge 171:3a7713b1edbc 459 #define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
AnnaBridge 171:3a7713b1edbc 460 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 463 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
AnnaBridge 171:3a7713b1edbc 464 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
AnnaBridge 171:3a7713b1edbc 465 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 #define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
AnnaBridge 171:3a7713b1edbc 468 #define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
AnnaBridge 171:3a7713b1edbc 469 #define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
AnnaBridge 171:3a7713b1edbc 470 #define NVMCTRL_FUSES_NVMP(value) (NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 #define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
AnnaBridge 171:3a7713b1edbc 473 #define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
AnnaBridge 171:3a7713b1edbc 474 #define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
AnnaBridge 171:3a7713b1edbc 475 #define NVMCTRL_FUSES_NVM_LOCK(value) (NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 #define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
AnnaBridge 171:3a7713b1edbc 478 #define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
AnnaBridge 171:3a7713b1edbc 479 #define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
AnnaBridge 171:3a7713b1edbc 480 #define NVMCTRL_FUSES_PSZ(value) (NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
AnnaBridge 171:3a7713b1edbc 483 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
AnnaBridge 171:3a7713b1edbc 484 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
AnnaBridge 171:3a7713b1edbc 485 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 488 #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
AnnaBridge 171:3a7713b1edbc 489 #define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
AnnaBridge 171:3a7713b1edbc 490 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 493 #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
AnnaBridge 171:3a7713b1edbc 494 #define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
AnnaBridge 171:3a7713b1edbc 495 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 #define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
AnnaBridge 171:3a7713b1edbc 498 #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
AnnaBridge 171:3a7713b1edbc 499 #define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
AnnaBridge 171:3a7713b1edbc 500 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 503 #define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
AnnaBridge 171:3a7713b1edbc 504 #define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos)
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 507 #define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
AnnaBridge 171:3a7713b1edbc 508 #define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 509
AnnaBridge 171:3a7713b1edbc 510 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
AnnaBridge 171:3a7713b1edbc 511 #define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
AnnaBridge 171:3a7713b1edbc 512 #define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 513 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 #define WDT_FUSES_PER_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 516 #define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
AnnaBridge 171:3a7713b1edbc 517 #define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
AnnaBridge 171:3a7713b1edbc 518 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
AnnaBridge 171:3a7713b1edbc 521 #define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
AnnaBridge 171:3a7713b1edbc 522 #define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos)
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 #define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
AnnaBridge 171:3a7713b1edbc 525 #define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
AnnaBridge 171:3a7713b1edbc 526 #define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos)
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 #define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
AnnaBridge 171:3a7713b1edbc 529 #define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
AnnaBridge 171:3a7713b1edbc 530 #define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
AnnaBridge 171:3a7713b1edbc 531 #define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
AnnaBridge 171:3a7713b1edbc 532
AnnaBridge 171:3a7713b1edbc 533 /*@}*/
AnnaBridge 171:3a7713b1edbc 534
AnnaBridge 171:3a7713b1edbc 535 #endif /* _SAMR21_NVMCTRL_COMPONENT_ */