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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_evsys.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for EVSYS
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_EVSYS_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_EVSYS_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR EVSYS */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_EVSYS Event System Interface */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define EVSYS_U2208
AnnaBridge 171:3a7713b1edbc 54 #define REV_EVSYS 0x101
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint8_t :3; /*!< bit: 1.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 62 uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
AnnaBridge 171:3a7713b1edbc 63 uint8_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 64 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 65 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 66 } EVSYS_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 #define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 70 #define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 #define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 73 #define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 74 #define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
AnnaBridge 171:3a7713b1edbc 75 #define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
AnnaBridge 171:3a7713b1edbc 76 #define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
AnnaBridge 171:3a7713b1edbc 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 80 typedef union {
AnnaBridge 171:3a7713b1edbc 81 struct {
AnnaBridge 171:3a7713b1edbc 82 uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
AnnaBridge 171:3a7713b1edbc 83 uint32_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 84 uint32_t SWEVT:1; /*!< bit: 8 Software Event */
AnnaBridge 171:3a7713b1edbc 85 uint32_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 86 uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
AnnaBridge 171:3a7713b1edbc 87 uint32_t :1; /*!< bit: 23 Reserved */
AnnaBridge 171:3a7713b1edbc 88 uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
AnnaBridge 171:3a7713b1edbc 89 uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
AnnaBridge 171:3a7713b1edbc 90 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 91 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 92 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 93 } EVSYS_CHANNEL_Type;
AnnaBridge 171:3a7713b1edbc 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 #define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
AnnaBridge 171:3a7713b1edbc 97 #define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 #define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
AnnaBridge 171:3a7713b1edbc 100 #define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
AnnaBridge 171:3a7713b1edbc 101 #define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
AnnaBridge 171:3a7713b1edbc 102 #define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
AnnaBridge 171:3a7713b1edbc 103 #define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
AnnaBridge 171:3a7713b1edbc 105 #define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
AnnaBridge 171:3a7713b1edbc 107 #define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
AnnaBridge 171:3a7713b1edbc 108 #define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
AnnaBridge 171:3a7713b1edbc 109 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
AnnaBridge 171:3a7713b1edbc 110 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
AnnaBridge 171:3a7713b1edbc 111 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
AnnaBridge 171:3a7713b1edbc 112 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
AnnaBridge 171:3a7713b1edbc 113 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
AnnaBridge 171:3a7713b1edbc 114 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
AnnaBridge 171:3a7713b1edbc 116 #define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
AnnaBridge 171:3a7713b1edbc 117 #define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
AnnaBridge 171:3a7713b1edbc 118 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
AnnaBridge 171:3a7713b1edbc 119 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
AnnaBridge 171:3a7713b1edbc 120 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
AnnaBridge 171:3a7713b1edbc 121 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
AnnaBridge 171:3a7713b1edbc 122 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
AnnaBridge 171:3a7713b1edbc 123 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
AnnaBridge 171:3a7713b1edbc 124 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
AnnaBridge 171:3a7713b1edbc 126 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
AnnaBridge 171:3a7713b1edbc 127 #define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
AnnaBridge 171:3a7713b1edbc 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 131 typedef union {
AnnaBridge 171:3a7713b1edbc 132 struct {
AnnaBridge 171:3a7713b1edbc 133 uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
AnnaBridge 171:3a7713b1edbc 134 uint16_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 135 uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
AnnaBridge 171:3a7713b1edbc 136 uint16_t :3; /*!< bit: 13..15 Reserved */
AnnaBridge 171:3a7713b1edbc 137 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 138 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 139 } EVSYS_USER_Type;
AnnaBridge 171:3a7713b1edbc 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 #define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
AnnaBridge 171:3a7713b1edbc 143 #define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 #define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
AnnaBridge 171:3a7713b1edbc 146 #define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
AnnaBridge 171:3a7713b1edbc 148 #define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
AnnaBridge 171:3a7713b1edbc 149 #define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
AnnaBridge 171:3a7713b1edbc 150 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
AnnaBridge 171:3a7713b1edbc 151 #define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
AnnaBridge 171:3a7713b1edbc 152 #define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
AnnaBridge 171:3a7713b1edbc 153 #define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
AnnaBridge 171:3a7713b1edbc 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 157 typedef union {
AnnaBridge 171:3a7713b1edbc 158 struct {
AnnaBridge 171:3a7713b1edbc 159 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
AnnaBridge 171:3a7713b1edbc 160 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
AnnaBridge 171:3a7713b1edbc 161 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
AnnaBridge 171:3a7713b1edbc 162 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
AnnaBridge 171:3a7713b1edbc 163 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
AnnaBridge 171:3a7713b1edbc 164 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
AnnaBridge 171:3a7713b1edbc 165 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
AnnaBridge 171:3a7713b1edbc 166 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
AnnaBridge 171:3a7713b1edbc 167 uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
AnnaBridge 171:3a7713b1edbc 168 uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
AnnaBridge 171:3a7713b1edbc 169 uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
AnnaBridge 171:3a7713b1edbc 170 uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
AnnaBridge 171:3a7713b1edbc 171 uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
AnnaBridge 171:3a7713b1edbc 172 uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
AnnaBridge 171:3a7713b1edbc 173 uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
AnnaBridge 171:3a7713b1edbc 174 uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
AnnaBridge 171:3a7713b1edbc 175 uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
AnnaBridge 171:3a7713b1edbc 176 uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
AnnaBridge 171:3a7713b1edbc 177 uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
AnnaBridge 171:3a7713b1edbc 178 uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
AnnaBridge 171:3a7713b1edbc 179 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 180 uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
AnnaBridge 171:3a7713b1edbc 181 uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
AnnaBridge 171:3a7713b1edbc 182 uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
AnnaBridge 171:3a7713b1edbc 183 uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
AnnaBridge 171:3a7713b1edbc 184 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 185 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 186 struct {
AnnaBridge 171:3a7713b1edbc 187 uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
AnnaBridge 171:3a7713b1edbc 188 uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
AnnaBridge 171:3a7713b1edbc 189 uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
AnnaBridge 171:3a7713b1edbc 190 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 191 uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
AnnaBridge 171:3a7713b1edbc 192 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 193 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 194 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 195 } EVSYS_CHSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
AnnaBridge 171:3a7713b1edbc 199 #define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
AnnaBridge 171:3a7713b1edbc 202 #define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 203 #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
AnnaBridge 171:3a7713b1edbc 204 #define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 205 #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
AnnaBridge 171:3a7713b1edbc 206 #define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
AnnaBridge 171:3a7713b1edbc 207 #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
AnnaBridge 171:3a7713b1edbc 208 #define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
AnnaBridge 171:3a7713b1edbc 209 #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
AnnaBridge 171:3a7713b1edbc 210 #define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
AnnaBridge 171:3a7713b1edbc 211 #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
AnnaBridge 171:3a7713b1edbc 212 #define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
AnnaBridge 171:3a7713b1edbc 213 #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
AnnaBridge 171:3a7713b1edbc 214 #define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
AnnaBridge 171:3a7713b1edbc 215 #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
AnnaBridge 171:3a7713b1edbc 216 #define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
AnnaBridge 171:3a7713b1edbc 217 #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
AnnaBridge 171:3a7713b1edbc 218 #define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
AnnaBridge 171:3a7713b1edbc 219 #define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
AnnaBridge 171:3a7713b1edbc 220 #define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
AnnaBridge 171:3a7713b1edbc 221 #define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
AnnaBridge 171:3a7713b1edbc 222 #define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
AnnaBridge 171:3a7713b1edbc 223 #define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
AnnaBridge 171:3a7713b1edbc 224 #define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
AnnaBridge 171:3a7713b1edbc 225 #define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
AnnaBridge 171:3a7713b1edbc 226 #define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
AnnaBridge 171:3a7713b1edbc 227 #define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
AnnaBridge 171:3a7713b1edbc 229 #define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
AnnaBridge 171:3a7713b1edbc 230 #define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
AnnaBridge 171:3a7713b1edbc 231 #define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
AnnaBridge 171:3a7713b1edbc 232 #define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
AnnaBridge 171:3a7713b1edbc 233 #define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
AnnaBridge 171:3a7713b1edbc 234 #define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
AnnaBridge 171:3a7713b1edbc 235 #define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
AnnaBridge 171:3a7713b1edbc 236 #define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
AnnaBridge 171:3a7713b1edbc 237 #define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 238 #define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
AnnaBridge 171:3a7713b1edbc 239 #define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
AnnaBridge 171:3a7713b1edbc 240 #define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
AnnaBridge 171:3a7713b1edbc 241 #define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
AnnaBridge 171:3a7713b1edbc 242 #define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
AnnaBridge 171:3a7713b1edbc 243 #define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
AnnaBridge 171:3a7713b1edbc 244 #define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
AnnaBridge 171:3a7713b1edbc 245 #define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
AnnaBridge 171:3a7713b1edbc 246 #define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
AnnaBridge 171:3a7713b1edbc 247 #define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
AnnaBridge 171:3a7713b1edbc 248 #define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
AnnaBridge 171:3a7713b1edbc 249 #define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
AnnaBridge 171:3a7713b1edbc 250 #define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
AnnaBridge 171:3a7713b1edbc 251 #define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
AnnaBridge 171:3a7713b1edbc 253 #define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
AnnaBridge 171:3a7713b1edbc 254 #define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
AnnaBridge 171:3a7713b1edbc 255 #define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
AnnaBridge 171:3a7713b1edbc 256 #define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
AnnaBridge 171:3a7713b1edbc 257 #define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
AnnaBridge 171:3a7713b1edbc 258 #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
AnnaBridge 171:3a7713b1edbc 259 #define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
AnnaBridge 171:3a7713b1edbc 260 #define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
AnnaBridge 171:3a7713b1edbc 261 #define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 265 typedef union {
AnnaBridge 171:3a7713b1edbc 266 struct {
AnnaBridge 171:3a7713b1edbc 267 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 268 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 269 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 270 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 271 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 272 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 273 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 274 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 275 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 276 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 277 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 278 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 279 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 280 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 281 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 282 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 283 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 284 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 285 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 286 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 287 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 288 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 289 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 290 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 291 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 292 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 293 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 294 struct {
AnnaBridge 171:3a7713b1edbc 295 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 296 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 297 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 298 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 299 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 300 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 301 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 302 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 303 } EVSYS_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 307 #define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 310 #define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
AnnaBridge 171:3a7713b1edbc 311 #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 312 #define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
AnnaBridge 171:3a7713b1edbc 313 #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 314 #define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
AnnaBridge 171:3a7713b1edbc 315 #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 316 #define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
AnnaBridge 171:3a7713b1edbc 317 #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 318 #define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
AnnaBridge 171:3a7713b1edbc 319 #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 320 #define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
AnnaBridge 171:3a7713b1edbc 321 #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 322 #define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
AnnaBridge 171:3a7713b1edbc 323 #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 324 #define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
AnnaBridge 171:3a7713b1edbc 325 #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 326 #define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
AnnaBridge 171:3a7713b1edbc 328 #define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 329 #define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
AnnaBridge 171:3a7713b1edbc 330 #define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 331 #define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
AnnaBridge 171:3a7713b1edbc 332 #define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 333 #define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
AnnaBridge 171:3a7713b1edbc 334 #define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 335 #define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
AnnaBridge 171:3a7713b1edbc 336 #define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 337 #define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
AnnaBridge 171:3a7713b1edbc 338 #define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 339 #define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
AnnaBridge 171:3a7713b1edbc 340 #define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 341 #define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
AnnaBridge 171:3a7713b1edbc 342 #define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 343 #define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
AnnaBridge 171:3a7713b1edbc 344 #define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 345 #define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
AnnaBridge 171:3a7713b1edbc 346 #define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
AnnaBridge 171:3a7713b1edbc 347 #define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 348 #define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
AnnaBridge 171:3a7713b1edbc 349 #define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 350 #define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
AnnaBridge 171:3a7713b1edbc 351 #define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 352 #define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
AnnaBridge 171:3a7713b1edbc 353 #define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 354 #define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
AnnaBridge 171:3a7713b1edbc 355 #define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 356 #define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
AnnaBridge 171:3a7713b1edbc 357 #define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
AnnaBridge 171:3a7713b1edbc 358 #define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 359 #define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
AnnaBridge 171:3a7713b1edbc 360 #define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 361 #define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
AnnaBridge 171:3a7713b1edbc 362 #define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 363 #define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
AnnaBridge 171:3a7713b1edbc 364 #define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 365 #define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
AnnaBridge 171:3a7713b1edbc 366 #define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 367 #define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
AnnaBridge 171:3a7713b1edbc 368 #define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
AnnaBridge 171:3a7713b1edbc 369 #define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 372 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 373 typedef union {
AnnaBridge 171:3a7713b1edbc 374 struct {
AnnaBridge 171:3a7713b1edbc 375 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 376 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 377 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 378 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 379 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 380 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 381 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 382 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 383 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 384 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 385 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 386 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 387 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 388 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 389 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 390 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 391 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 392 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 393 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 394 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 395 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 396 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 397 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 398 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 399 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 400 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 401 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 402 struct {
AnnaBridge 171:3a7713b1edbc 403 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 404 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 405 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 406 uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 407 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 408 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 409 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 410 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 411 } EVSYS_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 412 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 415 #define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 416
AnnaBridge 171:3a7713b1edbc 417 #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 418 #define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
AnnaBridge 171:3a7713b1edbc 419 #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 420 #define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
AnnaBridge 171:3a7713b1edbc 421 #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 422 #define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
AnnaBridge 171:3a7713b1edbc 423 #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 424 #define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
AnnaBridge 171:3a7713b1edbc 425 #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 426 #define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
AnnaBridge 171:3a7713b1edbc 427 #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 428 #define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
AnnaBridge 171:3a7713b1edbc 429 #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 430 #define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
AnnaBridge 171:3a7713b1edbc 431 #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 432 #define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
AnnaBridge 171:3a7713b1edbc 433 #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 434 #define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
AnnaBridge 171:3a7713b1edbc 435 #define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
AnnaBridge 171:3a7713b1edbc 436 #define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 437 #define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
AnnaBridge 171:3a7713b1edbc 438 #define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 439 #define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
AnnaBridge 171:3a7713b1edbc 440 #define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 441 #define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
AnnaBridge 171:3a7713b1edbc 442 #define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 443 #define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
AnnaBridge 171:3a7713b1edbc 444 #define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 445 #define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
AnnaBridge 171:3a7713b1edbc 446 #define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 447 #define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
AnnaBridge 171:3a7713b1edbc 448 #define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 449 #define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
AnnaBridge 171:3a7713b1edbc 450 #define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 451 #define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
AnnaBridge 171:3a7713b1edbc 452 #define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 453 #define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
AnnaBridge 171:3a7713b1edbc 454 #define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
AnnaBridge 171:3a7713b1edbc 455 #define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 456 #define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
AnnaBridge 171:3a7713b1edbc 457 #define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 458 #define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
AnnaBridge 171:3a7713b1edbc 459 #define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 460 #define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
AnnaBridge 171:3a7713b1edbc 461 #define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 462 #define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
AnnaBridge 171:3a7713b1edbc 463 #define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 464 #define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
AnnaBridge 171:3a7713b1edbc 465 #define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
AnnaBridge 171:3a7713b1edbc 466 #define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 467 #define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
AnnaBridge 171:3a7713b1edbc 468 #define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 469 #define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
AnnaBridge 171:3a7713b1edbc 470 #define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 471 #define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
AnnaBridge 171:3a7713b1edbc 472 #define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 473 #define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
AnnaBridge 171:3a7713b1edbc 474 #define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 475 #define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
AnnaBridge 171:3a7713b1edbc 476 #define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
AnnaBridge 171:3a7713b1edbc 477 #define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 480 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 481 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 482 struct {
AnnaBridge 171:3a7713b1edbc 483 __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
AnnaBridge 171:3a7713b1edbc 484 __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
AnnaBridge 171:3a7713b1edbc 485 __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
AnnaBridge 171:3a7713b1edbc 486 __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
AnnaBridge 171:3a7713b1edbc 487 __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
AnnaBridge 171:3a7713b1edbc 488 __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
AnnaBridge 171:3a7713b1edbc 489 __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
AnnaBridge 171:3a7713b1edbc 490 __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
AnnaBridge 171:3a7713b1edbc 491 __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
AnnaBridge 171:3a7713b1edbc 492 __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
AnnaBridge 171:3a7713b1edbc 493 __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
AnnaBridge 171:3a7713b1edbc 494 __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
AnnaBridge 171:3a7713b1edbc 495 __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
AnnaBridge 171:3a7713b1edbc 496 __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
AnnaBridge 171:3a7713b1edbc 497 __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
AnnaBridge 171:3a7713b1edbc 498 __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
AnnaBridge 171:3a7713b1edbc 499 __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
AnnaBridge 171:3a7713b1edbc 500 __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
AnnaBridge 171:3a7713b1edbc 501 __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
AnnaBridge 171:3a7713b1edbc 502 __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
AnnaBridge 171:3a7713b1edbc 503 __I uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 504 __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
AnnaBridge 171:3a7713b1edbc 505 __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
AnnaBridge 171:3a7713b1edbc 506 __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
AnnaBridge 171:3a7713b1edbc 507 __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
AnnaBridge 171:3a7713b1edbc 508 __I uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 509 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 510 struct {
AnnaBridge 171:3a7713b1edbc 511 __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
AnnaBridge 171:3a7713b1edbc 512 __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
AnnaBridge 171:3a7713b1edbc 513 __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
AnnaBridge 171:3a7713b1edbc 514 __I uint32_t :4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 515 __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
AnnaBridge 171:3a7713b1edbc 516 __I uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 517 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 518 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 519 } EVSYS_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 523 #define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
AnnaBridge 171:3a7713b1edbc 526 #define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
AnnaBridge 171:3a7713b1edbc 527 #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
AnnaBridge 171:3a7713b1edbc 528 #define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
AnnaBridge 171:3a7713b1edbc 529 #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
AnnaBridge 171:3a7713b1edbc 530 #define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
AnnaBridge 171:3a7713b1edbc 531 #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
AnnaBridge 171:3a7713b1edbc 532 #define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
AnnaBridge 171:3a7713b1edbc 533 #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
AnnaBridge 171:3a7713b1edbc 534 #define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
AnnaBridge 171:3a7713b1edbc 535 #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
AnnaBridge 171:3a7713b1edbc 536 #define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
AnnaBridge 171:3a7713b1edbc 537 #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
AnnaBridge 171:3a7713b1edbc 538 #define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
AnnaBridge 171:3a7713b1edbc 539 #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
AnnaBridge 171:3a7713b1edbc 540 #define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
AnnaBridge 171:3a7713b1edbc 541 #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
AnnaBridge 171:3a7713b1edbc 542 #define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
AnnaBridge 171:3a7713b1edbc 543 #define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
AnnaBridge 171:3a7713b1edbc 544 #define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
AnnaBridge 171:3a7713b1edbc 545 #define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
AnnaBridge 171:3a7713b1edbc 546 #define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
AnnaBridge 171:3a7713b1edbc 547 #define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
AnnaBridge 171:3a7713b1edbc 548 #define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
AnnaBridge 171:3a7713b1edbc 549 #define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
AnnaBridge 171:3a7713b1edbc 550 #define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
AnnaBridge 171:3a7713b1edbc 551 #define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
AnnaBridge 171:3a7713b1edbc 552 #define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
AnnaBridge 171:3a7713b1edbc 553 #define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
AnnaBridge 171:3a7713b1edbc 554 #define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
AnnaBridge 171:3a7713b1edbc 555 #define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
AnnaBridge 171:3a7713b1edbc 556 #define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
AnnaBridge 171:3a7713b1edbc 557 #define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
AnnaBridge 171:3a7713b1edbc 558 #define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
AnnaBridge 171:3a7713b1edbc 559 #define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
AnnaBridge 171:3a7713b1edbc 561 #define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
AnnaBridge 171:3a7713b1edbc 562 #define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
AnnaBridge 171:3a7713b1edbc 563 #define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
AnnaBridge 171:3a7713b1edbc 564 #define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
AnnaBridge 171:3a7713b1edbc 565 #define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
AnnaBridge 171:3a7713b1edbc 566 #define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
AnnaBridge 171:3a7713b1edbc 567 #define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
AnnaBridge 171:3a7713b1edbc 568 #define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
AnnaBridge 171:3a7713b1edbc 569 #define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
AnnaBridge 171:3a7713b1edbc 570 #define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
AnnaBridge 171:3a7713b1edbc 571 #define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
AnnaBridge 171:3a7713b1edbc 572 #define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
AnnaBridge 171:3a7713b1edbc 573 #define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
AnnaBridge 171:3a7713b1edbc 574 #define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
AnnaBridge 171:3a7713b1edbc 575 #define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
AnnaBridge 171:3a7713b1edbc 576 #define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
AnnaBridge 171:3a7713b1edbc 577 #define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
AnnaBridge 171:3a7713b1edbc 578 #define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
AnnaBridge 171:3a7713b1edbc 579 #define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
AnnaBridge 171:3a7713b1edbc 580 #define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
AnnaBridge 171:3a7713b1edbc 581 #define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
AnnaBridge 171:3a7713b1edbc 582 #define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
AnnaBridge 171:3a7713b1edbc 583 #define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
AnnaBridge 171:3a7713b1edbc 584 #define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
AnnaBridge 171:3a7713b1edbc 585 #define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /** \brief EVSYS hardware registers */
AnnaBridge 171:3a7713b1edbc 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 589 typedef struct {
AnnaBridge 171:3a7713b1edbc 590 __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
AnnaBridge 171:3a7713b1edbc 591 RoReg8 Reserved1[0x3];
AnnaBridge 171:3a7713b1edbc 592 __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
AnnaBridge 171:3a7713b1edbc 593 __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
AnnaBridge 171:3a7713b1edbc 594 RoReg8 Reserved2[0x2];
AnnaBridge 171:3a7713b1edbc 595 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
AnnaBridge 171:3a7713b1edbc 596 __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 597 __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 598 __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 599 } Evsys;
AnnaBridge 171:3a7713b1edbc 600 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /*@}*/
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 #endif /* _SAMR21_EVSYS_COMPONENT_ */