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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_eic.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for EIC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_EIC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_EIC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR EIC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_EIC External Interrupt Controller */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define EIC_U2217
AnnaBridge 171:3a7713b1edbc 54 #define REV_EIC 0x101
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 63 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 64 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 65 } EIC_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 #define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 69 #define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 72 #define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 73 #define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
AnnaBridge 171:3a7713b1edbc 74 #define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 75 #define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
AnnaBridge 171:3a7713b1edbc 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 79 typedef union {
AnnaBridge 171:3a7713b1edbc 80 struct {
AnnaBridge 171:3a7713b1edbc 81 uint8_t :7; /*!< bit: 0.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 82 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 83 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 84 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 85 } EIC_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 #define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 89 #define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 #define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 92 #define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 93 #define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
AnnaBridge 171:3a7713b1edbc 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 97 typedef union {
AnnaBridge 171:3a7713b1edbc 98 struct {
AnnaBridge 171:3a7713b1edbc 99 uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
AnnaBridge 171:3a7713b1edbc 100 uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
AnnaBridge 171:3a7713b1edbc 101 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 102 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 103 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 104 } EIC_NMICTRL_Type;
AnnaBridge 171:3a7713b1edbc 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 #define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
AnnaBridge 171:3a7713b1edbc 108 #define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
AnnaBridge 171:3a7713b1edbc 111 #define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 112 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
AnnaBridge 171:3a7713b1edbc 113 #define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
AnnaBridge 171:3a7713b1edbc 114 #define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
AnnaBridge 171:3a7713b1edbc 115 #define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
AnnaBridge 171:3a7713b1edbc 116 #define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */
AnnaBridge 171:3a7713b1edbc 117 #define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */
AnnaBridge 171:3a7713b1edbc 118 #define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */
AnnaBridge 171:3a7713b1edbc 119 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 121 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 122 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 123 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 124 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
AnnaBridge 171:3a7713b1edbc 126 #define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
AnnaBridge 171:3a7713b1edbc 127 #define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 131 typedef union {
AnnaBridge 171:3a7713b1edbc 132 struct {
AnnaBridge 171:3a7713b1edbc 133 uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 134 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 135 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 136 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 137 } EIC_NMIFLAG_Type;
AnnaBridge 171:3a7713b1edbc 138 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 141 #define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 144 #define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos)
AnnaBridge 171:3a7713b1edbc 145 #define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
AnnaBridge 171:3a7713b1edbc 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 149 typedef union {
AnnaBridge 171:3a7713b1edbc 150 struct {
AnnaBridge 171:3a7713b1edbc 151 uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 152 uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 153 uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 154 uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 155 uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 156 uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 157 uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 158 uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 159 uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 160 uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 161 uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 162 uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 163 uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 164 uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 165 uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 166 uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 167 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 168 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 169 struct {
AnnaBridge 171:3a7713b1edbc 170 uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 171 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 172 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 173 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 174 } EIC_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 #define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
AnnaBridge 171:3a7713b1edbc 178 #define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 #define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 181 #define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
AnnaBridge 171:3a7713b1edbc 182 #define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 183 #define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
AnnaBridge 171:3a7713b1edbc 184 #define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 185 #define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
AnnaBridge 171:3a7713b1edbc 186 #define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 187 #define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
AnnaBridge 171:3a7713b1edbc 188 #define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 189 #define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
AnnaBridge 171:3a7713b1edbc 190 #define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 191 #define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
AnnaBridge 171:3a7713b1edbc 192 #define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 193 #define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
AnnaBridge 171:3a7713b1edbc 194 #define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 195 #define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
AnnaBridge 171:3a7713b1edbc 196 #define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 197 #define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
AnnaBridge 171:3a7713b1edbc 198 #define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 199 #define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
AnnaBridge 171:3a7713b1edbc 200 #define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 201 #define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
AnnaBridge 171:3a7713b1edbc 202 #define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 203 #define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
AnnaBridge 171:3a7713b1edbc 204 #define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 205 #define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
AnnaBridge 171:3a7713b1edbc 206 #define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 207 #define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
AnnaBridge 171:3a7713b1edbc 208 #define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 209 #define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
AnnaBridge 171:3a7713b1edbc 210 #define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
AnnaBridge 171:3a7713b1edbc 211 #define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
AnnaBridge 171:3a7713b1edbc 212 #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
AnnaBridge 171:3a7713b1edbc 213 #define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
AnnaBridge 171:3a7713b1edbc 214 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
AnnaBridge 171:3a7713b1edbc 215 #define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 219 typedef union {
AnnaBridge 171:3a7713b1edbc 220 struct {
AnnaBridge 171:3a7713b1edbc 221 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
AnnaBridge 171:3a7713b1edbc 222 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
AnnaBridge 171:3a7713b1edbc 223 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
AnnaBridge 171:3a7713b1edbc 224 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
AnnaBridge 171:3a7713b1edbc 225 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
AnnaBridge 171:3a7713b1edbc 226 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
AnnaBridge 171:3a7713b1edbc 227 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
AnnaBridge 171:3a7713b1edbc 228 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
AnnaBridge 171:3a7713b1edbc 229 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
AnnaBridge 171:3a7713b1edbc 230 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
AnnaBridge 171:3a7713b1edbc 231 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
AnnaBridge 171:3a7713b1edbc 232 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
AnnaBridge 171:3a7713b1edbc 233 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
AnnaBridge 171:3a7713b1edbc 234 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
AnnaBridge 171:3a7713b1edbc 235 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
AnnaBridge 171:3a7713b1edbc 236 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
AnnaBridge 171:3a7713b1edbc 237 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 238 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 239 struct {
AnnaBridge 171:3a7713b1edbc 240 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
AnnaBridge 171:3a7713b1edbc 241 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 242 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 243 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 244 } EIC_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 #define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 248 #define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
AnnaBridge 171:3a7713b1edbc 251 #define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
AnnaBridge 171:3a7713b1edbc 253 #define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
AnnaBridge 171:3a7713b1edbc 254 #define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
AnnaBridge 171:3a7713b1edbc 255 #define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
AnnaBridge 171:3a7713b1edbc 256 #define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
AnnaBridge 171:3a7713b1edbc 257 #define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
AnnaBridge 171:3a7713b1edbc 258 #define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
AnnaBridge 171:3a7713b1edbc 259 #define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
AnnaBridge 171:3a7713b1edbc 260 #define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
AnnaBridge 171:3a7713b1edbc 261 #define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
AnnaBridge 171:3a7713b1edbc 262 #define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
AnnaBridge 171:3a7713b1edbc 263 #define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
AnnaBridge 171:3a7713b1edbc 264 #define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
AnnaBridge 171:3a7713b1edbc 265 #define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
AnnaBridge 171:3a7713b1edbc 266 #define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
AnnaBridge 171:3a7713b1edbc 267 #define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
AnnaBridge 171:3a7713b1edbc 268 #define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
AnnaBridge 171:3a7713b1edbc 269 #define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
AnnaBridge 171:3a7713b1edbc 270 #define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
AnnaBridge 171:3a7713b1edbc 271 #define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
AnnaBridge 171:3a7713b1edbc 272 #define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
AnnaBridge 171:3a7713b1edbc 273 #define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
AnnaBridge 171:3a7713b1edbc 274 #define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
AnnaBridge 171:3a7713b1edbc 275 #define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
AnnaBridge 171:3a7713b1edbc 276 #define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
AnnaBridge 171:3a7713b1edbc 277 #define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
AnnaBridge 171:3a7713b1edbc 278 #define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
AnnaBridge 171:3a7713b1edbc 279 #define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
AnnaBridge 171:3a7713b1edbc 280 #define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
AnnaBridge 171:3a7713b1edbc 281 #define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
AnnaBridge 171:3a7713b1edbc 282 #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
AnnaBridge 171:3a7713b1edbc 283 #define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
AnnaBridge 171:3a7713b1edbc 284 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
AnnaBridge 171:3a7713b1edbc 285 #define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 289 typedef union {
AnnaBridge 171:3a7713b1edbc 290 struct {
AnnaBridge 171:3a7713b1edbc 291 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
AnnaBridge 171:3a7713b1edbc 292 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
AnnaBridge 171:3a7713b1edbc 293 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
AnnaBridge 171:3a7713b1edbc 294 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
AnnaBridge 171:3a7713b1edbc 295 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
AnnaBridge 171:3a7713b1edbc 296 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
AnnaBridge 171:3a7713b1edbc 297 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
AnnaBridge 171:3a7713b1edbc 298 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
AnnaBridge 171:3a7713b1edbc 299 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
AnnaBridge 171:3a7713b1edbc 300 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
AnnaBridge 171:3a7713b1edbc 301 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
AnnaBridge 171:3a7713b1edbc 302 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
AnnaBridge 171:3a7713b1edbc 303 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
AnnaBridge 171:3a7713b1edbc 304 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
AnnaBridge 171:3a7713b1edbc 305 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
AnnaBridge 171:3a7713b1edbc 306 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
AnnaBridge 171:3a7713b1edbc 307 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 308 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 309 struct {
AnnaBridge 171:3a7713b1edbc 310 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
AnnaBridge 171:3a7713b1edbc 311 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 312 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 313 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 314 } EIC_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 #define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 318 #define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
AnnaBridge 171:3a7713b1edbc 321 #define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
AnnaBridge 171:3a7713b1edbc 322 #define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
AnnaBridge 171:3a7713b1edbc 323 #define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
AnnaBridge 171:3a7713b1edbc 324 #define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
AnnaBridge 171:3a7713b1edbc 325 #define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
AnnaBridge 171:3a7713b1edbc 326 #define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
AnnaBridge 171:3a7713b1edbc 327 #define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
AnnaBridge 171:3a7713b1edbc 328 #define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
AnnaBridge 171:3a7713b1edbc 329 #define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
AnnaBridge 171:3a7713b1edbc 330 #define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
AnnaBridge 171:3a7713b1edbc 331 #define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
AnnaBridge 171:3a7713b1edbc 332 #define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
AnnaBridge 171:3a7713b1edbc 333 #define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
AnnaBridge 171:3a7713b1edbc 334 #define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
AnnaBridge 171:3a7713b1edbc 335 #define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
AnnaBridge 171:3a7713b1edbc 336 #define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
AnnaBridge 171:3a7713b1edbc 337 #define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
AnnaBridge 171:3a7713b1edbc 338 #define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
AnnaBridge 171:3a7713b1edbc 339 #define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
AnnaBridge 171:3a7713b1edbc 340 #define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
AnnaBridge 171:3a7713b1edbc 341 #define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
AnnaBridge 171:3a7713b1edbc 342 #define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
AnnaBridge 171:3a7713b1edbc 343 #define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
AnnaBridge 171:3a7713b1edbc 344 #define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
AnnaBridge 171:3a7713b1edbc 345 #define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
AnnaBridge 171:3a7713b1edbc 346 #define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
AnnaBridge 171:3a7713b1edbc 347 #define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
AnnaBridge 171:3a7713b1edbc 348 #define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
AnnaBridge 171:3a7713b1edbc 349 #define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
AnnaBridge 171:3a7713b1edbc 350 #define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
AnnaBridge 171:3a7713b1edbc 351 #define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
AnnaBridge 171:3a7713b1edbc 352 #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
AnnaBridge 171:3a7713b1edbc 353 #define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
AnnaBridge 171:3a7713b1edbc 354 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
AnnaBridge 171:3a7713b1edbc 355 #define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 359 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 360 struct {
AnnaBridge 171:3a7713b1edbc 361 __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
AnnaBridge 171:3a7713b1edbc 362 __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
AnnaBridge 171:3a7713b1edbc 363 __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
AnnaBridge 171:3a7713b1edbc 364 __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
AnnaBridge 171:3a7713b1edbc 365 __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
AnnaBridge 171:3a7713b1edbc 366 __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
AnnaBridge 171:3a7713b1edbc 367 __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
AnnaBridge 171:3a7713b1edbc 368 __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
AnnaBridge 171:3a7713b1edbc 369 __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
AnnaBridge 171:3a7713b1edbc 370 __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
AnnaBridge 171:3a7713b1edbc 371 __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
AnnaBridge 171:3a7713b1edbc 372 __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
AnnaBridge 171:3a7713b1edbc 373 __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
AnnaBridge 171:3a7713b1edbc 374 __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
AnnaBridge 171:3a7713b1edbc 375 __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
AnnaBridge 171:3a7713b1edbc 376 __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
AnnaBridge 171:3a7713b1edbc 377 __I uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 378 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 379 struct {
AnnaBridge 171:3a7713b1edbc 380 __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
AnnaBridge 171:3a7713b1edbc 381 __I uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 382 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 383 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 384 } EIC_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 385 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 #define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 388 #define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 #define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
AnnaBridge 171:3a7713b1edbc 391 #define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
AnnaBridge 171:3a7713b1edbc 392 #define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
AnnaBridge 171:3a7713b1edbc 393 #define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
AnnaBridge 171:3a7713b1edbc 394 #define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
AnnaBridge 171:3a7713b1edbc 395 #define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
AnnaBridge 171:3a7713b1edbc 396 #define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
AnnaBridge 171:3a7713b1edbc 397 #define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
AnnaBridge 171:3a7713b1edbc 398 #define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
AnnaBridge 171:3a7713b1edbc 399 #define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
AnnaBridge 171:3a7713b1edbc 400 #define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
AnnaBridge 171:3a7713b1edbc 401 #define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
AnnaBridge 171:3a7713b1edbc 402 #define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
AnnaBridge 171:3a7713b1edbc 403 #define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
AnnaBridge 171:3a7713b1edbc 404 #define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
AnnaBridge 171:3a7713b1edbc 405 #define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
AnnaBridge 171:3a7713b1edbc 406 #define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
AnnaBridge 171:3a7713b1edbc 407 #define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
AnnaBridge 171:3a7713b1edbc 408 #define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
AnnaBridge 171:3a7713b1edbc 409 #define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
AnnaBridge 171:3a7713b1edbc 410 #define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
AnnaBridge 171:3a7713b1edbc 411 #define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
AnnaBridge 171:3a7713b1edbc 412 #define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
AnnaBridge 171:3a7713b1edbc 413 #define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
AnnaBridge 171:3a7713b1edbc 414 #define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
AnnaBridge 171:3a7713b1edbc 415 #define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
AnnaBridge 171:3a7713b1edbc 416 #define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
AnnaBridge 171:3a7713b1edbc 417 #define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
AnnaBridge 171:3a7713b1edbc 418 #define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
AnnaBridge 171:3a7713b1edbc 419 #define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
AnnaBridge 171:3a7713b1edbc 420 #define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
AnnaBridge 171:3a7713b1edbc 421 #define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
AnnaBridge 171:3a7713b1edbc 422 #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
AnnaBridge 171:3a7713b1edbc 423 #define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
AnnaBridge 171:3a7713b1edbc 424 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
AnnaBridge 171:3a7713b1edbc 425 #define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
AnnaBridge 171:3a7713b1edbc 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 429 typedef union {
AnnaBridge 171:3a7713b1edbc 430 struct {
AnnaBridge 171:3a7713b1edbc 431 uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 432 uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 433 uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 434 uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 435 uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 436 uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 437 uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 438 uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 439 uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 440 uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 441 uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 442 uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 443 uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 444 uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 445 uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 446 uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 447 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 448 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 449 struct {
AnnaBridge 171:3a7713b1edbc 450 uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 451 uint32_t :16; /*!< bit: 16..31 Reserved */
AnnaBridge 171:3a7713b1edbc 452 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 453 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 454 } EIC_WAKEUP_Type;
AnnaBridge 171:3a7713b1edbc 455 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
AnnaBridge 171:3a7713b1edbc 458 #define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 #define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 461 #define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
AnnaBridge 171:3a7713b1edbc 462 #define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 463 #define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
AnnaBridge 171:3a7713b1edbc 464 #define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 465 #define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
AnnaBridge 171:3a7713b1edbc 466 #define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 467 #define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
AnnaBridge 171:3a7713b1edbc 468 #define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 469 #define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
AnnaBridge 171:3a7713b1edbc 470 #define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 471 #define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
AnnaBridge 171:3a7713b1edbc 472 #define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 473 #define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
AnnaBridge 171:3a7713b1edbc 474 #define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 475 #define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
AnnaBridge 171:3a7713b1edbc 476 #define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 477 #define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
AnnaBridge 171:3a7713b1edbc 478 #define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 479 #define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
AnnaBridge 171:3a7713b1edbc 480 #define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 481 #define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
AnnaBridge 171:3a7713b1edbc 482 #define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 483 #define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
AnnaBridge 171:3a7713b1edbc 484 #define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 485 #define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
AnnaBridge 171:3a7713b1edbc 486 #define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 487 #define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
AnnaBridge 171:3a7713b1edbc 488 #define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 489 #define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
AnnaBridge 171:3a7713b1edbc 490 #define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 491 #define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
AnnaBridge 171:3a7713b1edbc 492 #define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
AnnaBridge 171:3a7713b1edbc 493 #define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
AnnaBridge 171:3a7713b1edbc 494 #define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
AnnaBridge 171:3a7713b1edbc 495 #define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
AnnaBridge 171:3a7713b1edbc 498 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 499 typedef union {
AnnaBridge 171:3a7713b1edbc 500 struct {
AnnaBridge 171:3a7713b1edbc 501 uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
AnnaBridge 171:3a7713b1edbc 502 uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
AnnaBridge 171:3a7713b1edbc 503 uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
AnnaBridge 171:3a7713b1edbc 504 uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
AnnaBridge 171:3a7713b1edbc 505 uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
AnnaBridge 171:3a7713b1edbc 506 uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
AnnaBridge 171:3a7713b1edbc 507 uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
AnnaBridge 171:3a7713b1edbc 508 uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
AnnaBridge 171:3a7713b1edbc 509 uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
AnnaBridge 171:3a7713b1edbc 510 uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
AnnaBridge 171:3a7713b1edbc 511 uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
AnnaBridge 171:3a7713b1edbc 512 uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
AnnaBridge 171:3a7713b1edbc 513 uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
AnnaBridge 171:3a7713b1edbc 514 uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
AnnaBridge 171:3a7713b1edbc 515 uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
AnnaBridge 171:3a7713b1edbc 516 uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
AnnaBridge 171:3a7713b1edbc 517 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 518 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 519 } EIC_CONFIG_Type;
AnnaBridge 171:3a7713b1edbc 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 #define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
AnnaBridge 171:3a7713b1edbc 523 #define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
AnnaBridge 171:3a7713b1edbc 526 #define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 527 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
AnnaBridge 171:3a7713b1edbc 528 #define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 529 #define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
AnnaBridge 171:3a7713b1edbc 530 #define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
AnnaBridge 171:3a7713b1edbc 531 #define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */
AnnaBridge 171:3a7713b1edbc 532 #define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */
AnnaBridge 171:3a7713b1edbc 533 #define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */
AnnaBridge 171:3a7713b1edbc 534 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 535 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 536 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 537 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 538 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 539 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
AnnaBridge 171:3a7713b1edbc 540 #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
AnnaBridge 171:3a7713b1edbc 541 #define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
AnnaBridge 171:3a7713b1edbc 542 #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
AnnaBridge 171:3a7713b1edbc 543 #define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 544 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
AnnaBridge 171:3a7713b1edbc 545 #define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 546 #define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 547 #define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 548 #define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 549 #define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 550 #define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 551 #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 552 #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 553 #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 554 #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 555 #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 556 #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
AnnaBridge 171:3a7713b1edbc 557 #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
AnnaBridge 171:3a7713b1edbc 558 #define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
AnnaBridge 171:3a7713b1edbc 559 #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
AnnaBridge 171:3a7713b1edbc 560 #define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 561 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
AnnaBridge 171:3a7713b1edbc 562 #define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 563 #define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 564 #define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 565 #define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 566 #define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 567 #define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 568 #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 569 #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 570 #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 571 #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 572 #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 573 #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
AnnaBridge 171:3a7713b1edbc 574 #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
AnnaBridge 171:3a7713b1edbc 575 #define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
AnnaBridge 171:3a7713b1edbc 576 #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
AnnaBridge 171:3a7713b1edbc 577 #define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 578 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
AnnaBridge 171:3a7713b1edbc 579 #define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 580 #define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 581 #define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 582 #define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 583 #define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 584 #define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 585 #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 586 #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 587 #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 588 #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 589 #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 590 #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
AnnaBridge 171:3a7713b1edbc 591 #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
AnnaBridge 171:3a7713b1edbc 592 #define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
AnnaBridge 171:3a7713b1edbc 593 #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
AnnaBridge 171:3a7713b1edbc 594 #define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 595 #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
AnnaBridge 171:3a7713b1edbc 596 #define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 597 #define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 598 #define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 599 #define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 600 #define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 601 #define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 602 #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 603 #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 604 #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 605 #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 606 #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 607 #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
AnnaBridge 171:3a7713b1edbc 608 #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
AnnaBridge 171:3a7713b1edbc 609 #define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
AnnaBridge 171:3a7713b1edbc 610 #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
AnnaBridge 171:3a7713b1edbc 611 #define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 612 #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
AnnaBridge 171:3a7713b1edbc 613 #define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 614 #define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 615 #define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 616 #define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 617 #define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 618 #define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 619 #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 620 #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 621 #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 622 #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 623 #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 624 #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
AnnaBridge 171:3a7713b1edbc 625 #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
AnnaBridge 171:3a7713b1edbc 626 #define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
AnnaBridge 171:3a7713b1edbc 627 #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
AnnaBridge 171:3a7713b1edbc 628 #define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 629 #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
AnnaBridge 171:3a7713b1edbc 630 #define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 631 #define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 632 #define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 633 #define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 634 #define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 635 #define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 636 #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 637 #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 638 #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 639 #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 640 #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 641 #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
AnnaBridge 171:3a7713b1edbc 642 #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
AnnaBridge 171:3a7713b1edbc 643 #define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
AnnaBridge 171:3a7713b1edbc 644 #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
AnnaBridge 171:3a7713b1edbc 645 #define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 646 #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
AnnaBridge 171:3a7713b1edbc 647 #define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
AnnaBridge 171:3a7713b1edbc 648 #define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
AnnaBridge 171:3a7713b1edbc 649 #define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
AnnaBridge 171:3a7713b1edbc 650 #define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
AnnaBridge 171:3a7713b1edbc 651 #define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
AnnaBridge 171:3a7713b1edbc 652 #define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
AnnaBridge 171:3a7713b1edbc 653 #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 654 #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 655 #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 656 #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 657 #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 658 #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
AnnaBridge 171:3a7713b1edbc 659 #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
AnnaBridge 171:3a7713b1edbc 660 #define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos)
AnnaBridge 171:3a7713b1edbc 661 #define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /** \brief EIC hardware registers */
AnnaBridge 171:3a7713b1edbc 664 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 665 typedef struct {
AnnaBridge 171:3a7713b1edbc 666 __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
AnnaBridge 171:3a7713b1edbc 667 __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 668 __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
AnnaBridge 171:3a7713b1edbc 669 __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 670 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
AnnaBridge 171:3a7713b1edbc 671 __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 672 __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 673 __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 674 __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
AnnaBridge 171:3a7713b1edbc 675 __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
AnnaBridge 171:3a7713b1edbc 676 } Eic;
AnnaBridge 171:3a7713b1edbc 677 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /*@}*/
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 #endif /* _SAMR21_EIC_COMPONENT_ */