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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_dsu.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for DSU
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_DSU_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_DSU_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR DSU */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_DSU Device Service Unit */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define DSU_U2209
AnnaBridge 171:3a7713b1edbc 54 #define REV_DSU 0x200
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint8_t :1; /*!< bit: 1 Reserved */
AnnaBridge 171:3a7713b1edbc 62 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
AnnaBridge 171:3a7713b1edbc 63 uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
AnnaBridge 171:3a7713b1edbc 64 uint8_t CE:1; /*!< bit: 4 Chip Erase */
AnnaBridge 171:3a7713b1edbc 65 uint8_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 66 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 67 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 68 } DSU_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 72 #define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
AnnaBridge 171:3a7713b1edbc 75 #define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 76 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
AnnaBridge 171:3a7713b1edbc 77 #define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
AnnaBridge 171:3a7713b1edbc 78 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
AnnaBridge 171:3a7713b1edbc 79 #define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
AnnaBridge 171:3a7713b1edbc 80 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
AnnaBridge 171:3a7713b1edbc 81 #define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
AnnaBridge 171:3a7713b1edbc 82 #define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
AnnaBridge 171:3a7713b1edbc 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 86 typedef union {
AnnaBridge 171:3a7713b1edbc 87 struct {
AnnaBridge 171:3a7713b1edbc 88 uint8_t DONE:1; /*!< bit: 0 Done */
AnnaBridge 171:3a7713b1edbc 89 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
AnnaBridge 171:3a7713b1edbc 90 uint8_t BERR:1; /*!< bit: 2 Bus Error */
AnnaBridge 171:3a7713b1edbc 91 uint8_t FAIL:1; /*!< bit: 3 Failure */
AnnaBridge 171:3a7713b1edbc 92 uint8_t PERR:1; /*!< bit: 4 Protection Error */
AnnaBridge 171:3a7713b1edbc 93 uint8_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 94 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 95 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 96 } DSU_STATUSA_Type;
AnnaBridge 171:3a7713b1edbc 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
AnnaBridge 171:3a7713b1edbc 100 #define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
AnnaBridge 171:3a7713b1edbc 103 #define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
AnnaBridge 171:3a7713b1edbc 105 #define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
AnnaBridge 171:3a7713b1edbc 107 #define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
AnnaBridge 171:3a7713b1edbc 108 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
AnnaBridge 171:3a7713b1edbc 109 #define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
AnnaBridge 171:3a7713b1edbc 110 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
AnnaBridge 171:3a7713b1edbc 111 #define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
AnnaBridge 171:3a7713b1edbc 112 #define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
AnnaBridge 171:3a7713b1edbc 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 116 typedef union {
AnnaBridge 171:3a7713b1edbc 117 struct {
AnnaBridge 171:3a7713b1edbc 118 uint8_t PROT:1; /*!< bit: 0 Protected */
AnnaBridge 171:3a7713b1edbc 119 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
AnnaBridge 171:3a7713b1edbc 120 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
AnnaBridge 171:3a7713b1edbc 121 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
AnnaBridge 171:3a7713b1edbc 122 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
AnnaBridge 171:3a7713b1edbc 123 uint8_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 124 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 125 struct {
AnnaBridge 171:3a7713b1edbc 126 uint8_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 127 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
AnnaBridge 171:3a7713b1edbc 128 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 129 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 130 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 131 } DSU_STATUSB_Type;
AnnaBridge 171:3a7713b1edbc 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
AnnaBridge 171:3a7713b1edbc 135 #define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
AnnaBridge 171:3a7713b1edbc 138 #define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
AnnaBridge 171:3a7713b1edbc 139 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
AnnaBridge 171:3a7713b1edbc 140 #define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
AnnaBridge 171:3a7713b1edbc 142 #define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
AnnaBridge 171:3a7713b1edbc 144 #define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
AnnaBridge 171:3a7713b1edbc 145 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
AnnaBridge 171:3a7713b1edbc 146 #define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
AnnaBridge 171:3a7713b1edbc 148 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
AnnaBridge 171:3a7713b1edbc 149 #define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
AnnaBridge 171:3a7713b1edbc 150 #define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
AnnaBridge 171:3a7713b1edbc 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 154 typedef union {
AnnaBridge 171:3a7713b1edbc 155 struct {
AnnaBridge 171:3a7713b1edbc 156 uint32_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 157 uint32_t ADDR:30; /*!< bit: 2..31 Address */
AnnaBridge 171:3a7713b1edbc 158 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 159 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 160 } DSU_ADDR_Type;
AnnaBridge 171:3a7713b1edbc 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
AnnaBridge 171:3a7713b1edbc 164 #define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
AnnaBridge 171:3a7713b1edbc 167 #define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 168 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 169 #define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
AnnaBridge 171:3a7713b1edbc 172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 173 typedef union {
AnnaBridge 171:3a7713b1edbc 174 struct {
AnnaBridge 171:3a7713b1edbc 175 uint32_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 176 uint32_t LENGTH:30; /*!< bit: 2..31 Length */
AnnaBridge 171:3a7713b1edbc 177 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 178 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 179 } DSU_LENGTH_Type;
AnnaBridge 171:3a7713b1edbc 180 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
AnnaBridge 171:3a7713b1edbc 183 #define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
AnnaBridge 171:3a7713b1edbc 186 #define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
AnnaBridge 171:3a7713b1edbc 187 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
AnnaBridge 171:3a7713b1edbc 188 #define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
AnnaBridge 171:3a7713b1edbc 191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 192 typedef union {
AnnaBridge 171:3a7713b1edbc 193 struct {
AnnaBridge 171:3a7713b1edbc 194 uint32_t DATA:32; /*!< bit: 0..31 Data */
AnnaBridge 171:3a7713b1edbc 195 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 196 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 197 } DSU_DATA_Type;
AnnaBridge 171:3a7713b1edbc 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
AnnaBridge 171:3a7713b1edbc 201 #define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
AnnaBridge 171:3a7713b1edbc 204 #define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 205 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 206 #define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
AnnaBridge 171:3a7713b1edbc 209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 210 typedef union {
AnnaBridge 171:3a7713b1edbc 211 struct {
AnnaBridge 171:3a7713b1edbc 212 uint32_t DATA:32; /*!< bit: 0..31 Data */
AnnaBridge 171:3a7713b1edbc 213 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 214 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 215 } DSU_DCC_Type;
AnnaBridge 171:3a7713b1edbc 216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
AnnaBridge 171:3a7713b1edbc 219 #define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
AnnaBridge 171:3a7713b1edbc 222 #define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 223 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 224 #define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
AnnaBridge 171:3a7713b1edbc 227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 228 typedef union {
AnnaBridge 171:3a7713b1edbc 229 struct {
AnnaBridge 171:3a7713b1edbc 230 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
AnnaBridge 171:3a7713b1edbc 231 uint32_t REVISION:4; /*!< bit: 8..11 Revision */
AnnaBridge 171:3a7713b1edbc 232 uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
AnnaBridge 171:3a7713b1edbc 233 uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
AnnaBridge 171:3a7713b1edbc 234 uint32_t :1; /*!< bit: 22 Reserved */
AnnaBridge 171:3a7713b1edbc 235 uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
AnnaBridge 171:3a7713b1edbc 236 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
AnnaBridge 171:3a7713b1edbc 237 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 238 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 239 } DSU_DID_Type;
AnnaBridge 171:3a7713b1edbc 240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
AnnaBridge 171:3a7713b1edbc 245 #define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
AnnaBridge 171:3a7713b1edbc 246 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
AnnaBridge 171:3a7713b1edbc 247 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
AnnaBridge 171:3a7713b1edbc 248 #define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
AnnaBridge 171:3a7713b1edbc 249 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
AnnaBridge 171:3a7713b1edbc 250 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
AnnaBridge 171:3a7713b1edbc 251 #define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
AnnaBridge 171:3a7713b1edbc 253 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
AnnaBridge 171:3a7713b1edbc 254 #define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
AnnaBridge 171:3a7713b1edbc 255 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
AnnaBridge 171:3a7713b1edbc 256 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
AnnaBridge 171:3a7713b1edbc 257 #define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
AnnaBridge 171:3a7713b1edbc 258 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
AnnaBridge 171:3a7713b1edbc 259 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
AnnaBridge 171:3a7713b1edbc 260 #define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
AnnaBridge 171:3a7713b1edbc 261 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
AnnaBridge 171:3a7713b1edbc 262 #define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
AnnaBridge 171:3a7713b1edbc 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 266 typedef union {
AnnaBridge 171:3a7713b1edbc 267 struct {
AnnaBridge 171:3a7713b1edbc 268 uint32_t EPRES:1; /*!< bit: 0 Entry Present */
AnnaBridge 171:3a7713b1edbc 269 uint32_t FMT:1; /*!< bit: 1 Format */
AnnaBridge 171:3a7713b1edbc 270 uint32_t :10; /*!< bit: 2..11 Reserved */
AnnaBridge 171:3a7713b1edbc 271 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
AnnaBridge 171:3a7713b1edbc 272 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 273 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 274 } DSU_ENTRY_Type;
AnnaBridge 171:3a7713b1edbc 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 #define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
AnnaBridge 171:3a7713b1edbc 278 #define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 #define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
AnnaBridge 171:3a7713b1edbc 281 #define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
AnnaBridge 171:3a7713b1edbc 282 #define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
AnnaBridge 171:3a7713b1edbc 283 #define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
AnnaBridge 171:3a7713b1edbc 284 #define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
AnnaBridge 171:3a7713b1edbc 285 #define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
AnnaBridge 171:3a7713b1edbc 286 #define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
AnnaBridge 171:3a7713b1edbc 287 #define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
AnnaBridge 171:3a7713b1edbc 290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 291 typedef union {
AnnaBridge 171:3a7713b1edbc 292 struct {
AnnaBridge 171:3a7713b1edbc 293 uint32_t END:32; /*!< bit: 0..31 End Marker */
AnnaBridge 171:3a7713b1edbc 294 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 295 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 296 } DSU_END_Type;
AnnaBridge 171:3a7713b1edbc 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
AnnaBridge 171:3a7713b1edbc 300 #define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
AnnaBridge 171:3a7713b1edbc 303 #define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
AnnaBridge 171:3a7713b1edbc 305 #define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
AnnaBridge 171:3a7713b1edbc 308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 309 typedef union {
AnnaBridge 171:3a7713b1edbc 310 struct {
AnnaBridge 171:3a7713b1edbc 311 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
AnnaBridge 171:3a7713b1edbc 312 uint32_t :31; /*!< bit: 1..31 Reserved */
AnnaBridge 171:3a7713b1edbc 313 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 314 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 315 } DSU_MEMTYPE_Type;
AnnaBridge 171:3a7713b1edbc 316 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
AnnaBridge 171:3a7713b1edbc 319 #define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
AnnaBridge 171:3a7713b1edbc 322 #define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
AnnaBridge 171:3a7713b1edbc 323 #define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
AnnaBridge 171:3a7713b1edbc 326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 327 typedef union {
AnnaBridge 171:3a7713b1edbc 328 struct {
AnnaBridge 171:3a7713b1edbc 329 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
AnnaBridge 171:3a7713b1edbc 330 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
AnnaBridge 171:3a7713b1edbc 331 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 332 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 333 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 334 } DSU_PID4_Type;
AnnaBridge 171:3a7713b1edbc 335 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
AnnaBridge 171:3a7713b1edbc 338 #define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
AnnaBridge 171:3a7713b1edbc 341 #define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
AnnaBridge 171:3a7713b1edbc 342 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
AnnaBridge 171:3a7713b1edbc 343 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
AnnaBridge 171:3a7713b1edbc 344 #define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
AnnaBridge 171:3a7713b1edbc 345 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
AnnaBridge 171:3a7713b1edbc 346 #define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
AnnaBridge 171:3a7713b1edbc 349 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 350 typedef union {
AnnaBridge 171:3a7713b1edbc 351 struct {
AnnaBridge 171:3a7713b1edbc 352 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
AnnaBridge 171:3a7713b1edbc 353 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 354 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 355 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 356 } DSU_PID0_Type;
AnnaBridge 171:3a7713b1edbc 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
AnnaBridge 171:3a7713b1edbc 360 #define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
AnnaBridge 171:3a7713b1edbc 363 #define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
AnnaBridge 171:3a7713b1edbc 364 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
AnnaBridge 171:3a7713b1edbc 365 #define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
AnnaBridge 171:3a7713b1edbc 368 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 369 typedef union {
AnnaBridge 171:3a7713b1edbc 370 struct {
AnnaBridge 171:3a7713b1edbc 371 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
AnnaBridge 171:3a7713b1edbc 372 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
AnnaBridge 171:3a7713b1edbc 373 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 374 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 375 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 376 } DSU_PID1_Type;
AnnaBridge 171:3a7713b1edbc 377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
AnnaBridge 171:3a7713b1edbc 380 #define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
AnnaBridge 171:3a7713b1edbc 383 #define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
AnnaBridge 171:3a7713b1edbc 384 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
AnnaBridge 171:3a7713b1edbc 385 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
AnnaBridge 171:3a7713b1edbc 386 #define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
AnnaBridge 171:3a7713b1edbc 388 #define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
AnnaBridge 171:3a7713b1edbc 391 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 392 typedef union {
AnnaBridge 171:3a7713b1edbc 393 struct {
AnnaBridge 171:3a7713b1edbc 394 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
AnnaBridge 171:3a7713b1edbc 395 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
AnnaBridge 171:3a7713b1edbc 396 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
AnnaBridge 171:3a7713b1edbc 397 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 398 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 399 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 400 } DSU_PID2_Type;
AnnaBridge 171:3a7713b1edbc 401 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
AnnaBridge 171:3a7713b1edbc 404 #define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
AnnaBridge 171:3a7713b1edbc 407 #define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
AnnaBridge 171:3a7713b1edbc 408 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
AnnaBridge 171:3a7713b1edbc 409 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
AnnaBridge 171:3a7713b1edbc 410 #define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
AnnaBridge 171:3a7713b1edbc 411 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
AnnaBridge 171:3a7713b1edbc 412 #define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
AnnaBridge 171:3a7713b1edbc 413 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
AnnaBridge 171:3a7713b1edbc 414 #define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
AnnaBridge 171:3a7713b1edbc 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 418 typedef union {
AnnaBridge 171:3a7713b1edbc 419 struct {
AnnaBridge 171:3a7713b1edbc 420 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
AnnaBridge 171:3a7713b1edbc 421 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
AnnaBridge 171:3a7713b1edbc 422 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 423 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 424 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 425 } DSU_PID3_Type;
AnnaBridge 171:3a7713b1edbc 426 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
AnnaBridge 171:3a7713b1edbc 429 #define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
AnnaBridge 171:3a7713b1edbc 432 #define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
AnnaBridge 171:3a7713b1edbc 433 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
AnnaBridge 171:3a7713b1edbc 434 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
AnnaBridge 171:3a7713b1edbc 435 #define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
AnnaBridge 171:3a7713b1edbc 436 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
AnnaBridge 171:3a7713b1edbc 437 #define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
AnnaBridge 171:3a7713b1edbc 440 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 441 typedef union {
AnnaBridge 171:3a7713b1edbc 442 struct {
AnnaBridge 171:3a7713b1edbc 443 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
AnnaBridge 171:3a7713b1edbc 444 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 445 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 446 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 447 } DSU_CID0_Type;
AnnaBridge 171:3a7713b1edbc 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
AnnaBridge 171:3a7713b1edbc 451 #define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
AnnaBridge 171:3a7713b1edbc 454 #define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
AnnaBridge 171:3a7713b1edbc 455 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
AnnaBridge 171:3a7713b1edbc 456 #define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
AnnaBridge 171:3a7713b1edbc 459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 460 typedef union {
AnnaBridge 171:3a7713b1edbc 461 struct {
AnnaBridge 171:3a7713b1edbc 462 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
AnnaBridge 171:3a7713b1edbc 463 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
AnnaBridge 171:3a7713b1edbc 464 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 465 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 466 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 467 } DSU_CID1_Type;
AnnaBridge 171:3a7713b1edbc 468 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
AnnaBridge 171:3a7713b1edbc 471 #define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
AnnaBridge 171:3a7713b1edbc 472
AnnaBridge 171:3a7713b1edbc 473 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
AnnaBridge 171:3a7713b1edbc 474 #define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
AnnaBridge 171:3a7713b1edbc 475 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
AnnaBridge 171:3a7713b1edbc 476 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
AnnaBridge 171:3a7713b1edbc 477 #define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
AnnaBridge 171:3a7713b1edbc 478 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
AnnaBridge 171:3a7713b1edbc 479 #define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
AnnaBridge 171:3a7713b1edbc 482 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 483 typedef union {
AnnaBridge 171:3a7713b1edbc 484 struct {
AnnaBridge 171:3a7713b1edbc 485 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
AnnaBridge 171:3a7713b1edbc 486 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 487 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 488 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 489 } DSU_CID2_Type;
AnnaBridge 171:3a7713b1edbc 490 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
AnnaBridge 171:3a7713b1edbc 493 #define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
AnnaBridge 171:3a7713b1edbc 496 #define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
AnnaBridge 171:3a7713b1edbc 497 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
AnnaBridge 171:3a7713b1edbc 498 #define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
AnnaBridge 171:3a7713b1edbc 501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 502 typedef union {
AnnaBridge 171:3a7713b1edbc 503 struct {
AnnaBridge 171:3a7713b1edbc 504 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
AnnaBridge 171:3a7713b1edbc 505 uint32_t :24; /*!< bit: 8..31 Reserved */
AnnaBridge 171:3a7713b1edbc 506 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 507 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 508 } DSU_CID3_Type;
AnnaBridge 171:3a7713b1edbc 509 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 510
AnnaBridge 171:3a7713b1edbc 511 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
AnnaBridge 171:3a7713b1edbc 512 #define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
AnnaBridge 171:3a7713b1edbc 515 #define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
AnnaBridge 171:3a7713b1edbc 516 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
AnnaBridge 171:3a7713b1edbc 517 #define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
AnnaBridge 171:3a7713b1edbc 518
AnnaBridge 171:3a7713b1edbc 519 /** \brief DSU hardware registers */
AnnaBridge 171:3a7713b1edbc 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 521 typedef struct {
AnnaBridge 171:3a7713b1edbc 522 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
AnnaBridge 171:3a7713b1edbc 523 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
AnnaBridge 171:3a7713b1edbc 524 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
AnnaBridge 171:3a7713b1edbc 525 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 526 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
AnnaBridge 171:3a7713b1edbc 527 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
AnnaBridge 171:3a7713b1edbc 528 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
AnnaBridge 171:3a7713b1edbc 529 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
AnnaBridge 171:3a7713b1edbc 530 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
AnnaBridge 171:3a7713b1edbc 531 RoReg8 Reserved2[0xFE4];
AnnaBridge 171:3a7713b1edbc 532 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
AnnaBridge 171:3a7713b1edbc 533 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
AnnaBridge 171:3a7713b1edbc 534 RoReg8 Reserved3[0xFC0];
AnnaBridge 171:3a7713b1edbc 535 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
AnnaBridge 171:3a7713b1edbc 536 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
AnnaBridge 171:3a7713b1edbc 537 RoReg8 Reserved4[0xC];
AnnaBridge 171:3a7713b1edbc 538 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
AnnaBridge 171:3a7713b1edbc 539 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
AnnaBridge 171:3a7713b1edbc 540 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
AnnaBridge 171:3a7713b1edbc 541 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
AnnaBridge 171:3a7713b1edbc 542 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
AnnaBridge 171:3a7713b1edbc 543 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
AnnaBridge 171:3a7713b1edbc 544 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
AnnaBridge 171:3a7713b1edbc 545 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
AnnaBridge 171:3a7713b1edbc 546 } Dsu;
AnnaBridge 171:3a7713b1edbc 547 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /*@}*/
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 #endif /* _SAMR21_DSU_COMPONENT_ */