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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_adc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for ADC
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_ADC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_ADC_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR ADC */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_ADC Analog Digital Converter */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define ADC_U2204
AnnaBridge 171:3a7713b1edbc 54 #define REV_ADC 0x120
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
AnnaBridge 171:3a7713b1edbc 63 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 64 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 65 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 66 } ADC_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
AnnaBridge 171:3a7713b1edbc 70 #define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 73 #define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 74 #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 75 #define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 76 #define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
AnnaBridge 171:3a7713b1edbc 77 #define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 78 #define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
AnnaBridge 171:3a7713b1edbc 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 82 typedef union {
AnnaBridge 171:3a7713b1edbc 83 struct {
AnnaBridge 171:3a7713b1edbc 84 uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
AnnaBridge 171:3a7713b1edbc 85 uint8_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 86 uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
AnnaBridge 171:3a7713b1edbc 87 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 88 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 89 } ADC_REFCTRL_Type;
AnnaBridge 171:3a7713b1edbc 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 #define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
AnnaBridge 171:3a7713b1edbc 93 #define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
AnnaBridge 171:3a7713b1edbc 96 #define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 97 #define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
AnnaBridge 171:3a7713b1edbc 98 #define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
AnnaBridge 171:3a7713b1edbc 99 #define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
AnnaBridge 171:3a7713b1edbc 100 #define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
AnnaBridge 171:3a7713b1edbc 101 #define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */
AnnaBridge 171:3a7713b1edbc 102 #define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */
AnnaBridge 171:3a7713b1edbc 103 #define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 105 #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 107 #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
AnnaBridge 171:3a7713b1edbc 108 #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
AnnaBridge 171:3a7713b1edbc 109 #define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
AnnaBridge 171:3a7713b1edbc 110 #define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
AnnaBridge 171:3a7713b1edbc 113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 114 typedef union {
AnnaBridge 171:3a7713b1edbc 115 struct {
AnnaBridge 171:3a7713b1edbc 116 uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
AnnaBridge 171:3a7713b1edbc 117 uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
AnnaBridge 171:3a7713b1edbc 118 uint8_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 119 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 120 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 121 } ADC_AVGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 #define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
AnnaBridge 171:3a7713b1edbc 125 #define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
AnnaBridge 171:3a7713b1edbc 128 #define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 129 #define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
AnnaBridge 171:3a7713b1edbc 130 #define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
AnnaBridge 171:3a7713b1edbc 131 #define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
AnnaBridge 171:3a7713b1edbc 132 #define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
AnnaBridge 171:3a7713b1edbc 133 #define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */
AnnaBridge 171:3a7713b1edbc 134 #define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */
AnnaBridge 171:3a7713b1edbc 135 #define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */
AnnaBridge 171:3a7713b1edbc 136 #define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */
AnnaBridge 171:3a7713b1edbc 137 #define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */
AnnaBridge 171:3a7713b1edbc 138 #define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */
AnnaBridge 171:3a7713b1edbc 139 #define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */
AnnaBridge 171:3a7713b1edbc 140 #define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */
AnnaBridge 171:3a7713b1edbc 141 #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 142 #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 144 #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 145 #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 146 #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 148 #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 149 #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 150 #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 151 #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
AnnaBridge 171:3a7713b1edbc 152 #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
AnnaBridge 171:3a7713b1edbc 153 #define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
AnnaBridge 171:3a7713b1edbc 154 #define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
AnnaBridge 171:3a7713b1edbc 155 #define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
AnnaBridge 171:3a7713b1edbc 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 159 typedef union {
AnnaBridge 171:3a7713b1edbc 160 struct {
AnnaBridge 171:3a7713b1edbc 161 uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
AnnaBridge 171:3a7713b1edbc 162 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 163 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 164 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 165 } ADC_SAMPCTRL_Type;
AnnaBridge 171:3a7713b1edbc 166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 #define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
AnnaBridge 171:3a7713b1edbc 169 #define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
AnnaBridge 171:3a7713b1edbc 172 #define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
AnnaBridge 171:3a7713b1edbc 173 #define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
AnnaBridge 171:3a7713b1edbc 174 #define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
AnnaBridge 171:3a7713b1edbc 177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 178 typedef union {
AnnaBridge 171:3a7713b1edbc 179 struct {
AnnaBridge 171:3a7713b1edbc 180 uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
AnnaBridge 171:3a7713b1edbc 181 uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
AnnaBridge 171:3a7713b1edbc 182 uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
AnnaBridge 171:3a7713b1edbc 183 uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
AnnaBridge 171:3a7713b1edbc 184 uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
AnnaBridge 171:3a7713b1edbc 185 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 186 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
AnnaBridge 171:3a7713b1edbc 187 uint16_t :5; /*!< bit: 11..15 Reserved */
AnnaBridge 171:3a7713b1edbc 188 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 189 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 190 } ADC_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 #define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
AnnaBridge 171:3a7713b1edbc 194 #define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 #define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
AnnaBridge 171:3a7713b1edbc 197 #define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
AnnaBridge 171:3a7713b1edbc 198 #define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
AnnaBridge 171:3a7713b1edbc 199 #define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
AnnaBridge 171:3a7713b1edbc 200 #define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
AnnaBridge 171:3a7713b1edbc 201 #define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos)
AnnaBridge 171:3a7713b1edbc 202 #define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
AnnaBridge 171:3a7713b1edbc 203 #define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
AnnaBridge 171:3a7713b1edbc 204 #define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
AnnaBridge 171:3a7713b1edbc 205 #define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
AnnaBridge 171:3a7713b1edbc 206 #define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
AnnaBridge 171:3a7713b1edbc 207 #define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
AnnaBridge 171:3a7713b1edbc 208 #define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
AnnaBridge 171:3a7713b1edbc 209 #define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
AnnaBridge 171:3a7713b1edbc 210 #define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */
AnnaBridge 171:3a7713b1edbc 211 #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
AnnaBridge 171:3a7713b1edbc 212 #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
AnnaBridge 171:3a7713b1edbc 213 #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
AnnaBridge 171:3a7713b1edbc 214 #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
AnnaBridge 171:3a7713b1edbc 215 #define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
AnnaBridge 171:3a7713b1edbc 216 #define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 217 #define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
AnnaBridge 171:3a7713b1edbc 218 #define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
AnnaBridge 171:3a7713b1edbc 219 #define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
AnnaBridge 171:3a7713b1edbc 220 #define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
AnnaBridge 171:3a7713b1edbc 221 #define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
AnnaBridge 171:3a7713b1edbc 222 #define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
AnnaBridge 171:3a7713b1edbc 223 #define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
AnnaBridge 171:3a7713b1edbc 224 #define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
AnnaBridge 171:3a7713b1edbc 225 #define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
AnnaBridge 171:3a7713b1edbc 226 #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 227 #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 229 #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 230 #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 231 #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 232 #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 233 #define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
AnnaBridge 171:3a7713b1edbc 234 #define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
AnnaBridge 171:3a7713b1edbc 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 238 typedef union {
AnnaBridge 171:3a7713b1edbc 239 struct {
AnnaBridge 171:3a7713b1edbc 240 uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
AnnaBridge 171:3a7713b1edbc 241 uint8_t :5; /*!< bit: 3.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 242 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 243 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 244 } ADC_WINCTRL_Type;
AnnaBridge 171:3a7713b1edbc 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 #define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
AnnaBridge 171:3a7713b1edbc 248 #define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
AnnaBridge 171:3a7713b1edbc 251 #define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
AnnaBridge 171:3a7713b1edbc 253 #define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
AnnaBridge 171:3a7713b1edbc 254 #define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
AnnaBridge 171:3a7713b1edbc 255 #define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
AnnaBridge 171:3a7713b1edbc 256 #define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
AnnaBridge 171:3a7713b1edbc 257 #define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
AnnaBridge 171:3a7713b1edbc 258 #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 259 #define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 260 #define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 261 #define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 262 #define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
AnnaBridge 171:3a7713b1edbc 263 #define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
AnnaBridge 171:3a7713b1edbc 266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 267 typedef union {
AnnaBridge 171:3a7713b1edbc 268 struct {
AnnaBridge 171:3a7713b1edbc 269 uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
AnnaBridge 171:3a7713b1edbc 270 uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
AnnaBridge 171:3a7713b1edbc 271 uint8_t :6; /*!< bit: 2.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 272 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 273 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 274 } ADC_SWTRIG_Type;
AnnaBridge 171:3a7713b1edbc 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 #define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
AnnaBridge 171:3a7713b1edbc 278 #define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
AnnaBridge 171:3a7713b1edbc 281 #define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos)
AnnaBridge 171:3a7713b1edbc 282 #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
AnnaBridge 171:3a7713b1edbc 283 #define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos)
AnnaBridge 171:3a7713b1edbc 284 #define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
AnnaBridge 171:3a7713b1edbc 287 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 288 typedef union {
AnnaBridge 171:3a7713b1edbc 289 struct {
AnnaBridge 171:3a7713b1edbc 290 uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
AnnaBridge 171:3a7713b1edbc 291 uint32_t :3; /*!< bit: 5.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 292 uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
AnnaBridge 171:3a7713b1edbc 293 uint32_t :3; /*!< bit: 13..15 Reserved */
AnnaBridge 171:3a7713b1edbc 294 uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
AnnaBridge 171:3a7713b1edbc 295 uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
AnnaBridge 171:3a7713b1edbc 296 uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
AnnaBridge 171:3a7713b1edbc 297 uint32_t :4; /*!< bit: 28..31 Reserved */
AnnaBridge 171:3a7713b1edbc 298 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 299 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 300 } ADC_INPUTCTRL_Type;
AnnaBridge 171:3a7713b1edbc 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 #define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
AnnaBridge 171:3a7713b1edbc 304 #define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
AnnaBridge 171:3a7713b1edbc 307 #define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
AnnaBridge 171:3a7713b1edbc 309 #define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
AnnaBridge 171:3a7713b1edbc 310 #define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
AnnaBridge 171:3a7713b1edbc 311 #define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
AnnaBridge 171:3a7713b1edbc 312 #define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
AnnaBridge 171:3a7713b1edbc 313 #define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
AnnaBridge 171:3a7713b1edbc 314 #define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
AnnaBridge 171:3a7713b1edbc 315 #define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
AnnaBridge 171:3a7713b1edbc 316 #define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
AnnaBridge 171:3a7713b1edbc 317 #define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
AnnaBridge 171:3a7713b1edbc 318 #define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
AnnaBridge 171:3a7713b1edbc 319 #define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
AnnaBridge 171:3a7713b1edbc 320 #define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
AnnaBridge 171:3a7713b1edbc 321 #define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
AnnaBridge 171:3a7713b1edbc 322 #define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
AnnaBridge 171:3a7713b1edbc 323 #define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
AnnaBridge 171:3a7713b1edbc 324 #define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
AnnaBridge 171:3a7713b1edbc 325 #define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
AnnaBridge 171:3a7713b1edbc 326 #define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
AnnaBridge 171:3a7713b1edbc 327 #define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
AnnaBridge 171:3a7713b1edbc 328 #define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
AnnaBridge 171:3a7713b1edbc 329 #define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */
AnnaBridge 171:3a7713b1edbc 330 #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
AnnaBridge 171:3a7713b1edbc 331 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
AnnaBridge 171:3a7713b1edbc 332 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
AnnaBridge 171:3a7713b1edbc 333 #define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */
AnnaBridge 171:3a7713b1edbc 334 #define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 335 #define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 336 #define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 337 #define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 338 #define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 339 #define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 340 #define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 341 #define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 342 #define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 343 #define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 344 #define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 345 #define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 346 #define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 347 #define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 348 #define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 349 #define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 350 #define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 351 #define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 352 #define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 353 #define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 354 #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 355 #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 356 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 357 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 358 #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
AnnaBridge 171:3a7713b1edbc 359 #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
AnnaBridge 171:3a7713b1edbc 360 #define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 361 #define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
AnnaBridge 171:3a7713b1edbc 362 #define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
AnnaBridge 171:3a7713b1edbc 363 #define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
AnnaBridge 171:3a7713b1edbc 364 #define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
AnnaBridge 171:3a7713b1edbc 365 #define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
AnnaBridge 171:3a7713b1edbc 366 #define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
AnnaBridge 171:3a7713b1edbc 367 #define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
AnnaBridge 171:3a7713b1edbc 368 #define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
AnnaBridge 171:3a7713b1edbc 369 #define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
AnnaBridge 171:3a7713b1edbc 370 #define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */
AnnaBridge 171:3a7713b1edbc 371 #define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */
AnnaBridge 171:3a7713b1edbc 372 #define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 373 #define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 374 #define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 375 #define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 376 #define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 377 #define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 378 #define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 379 #define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 380 #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 381 #define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
AnnaBridge 171:3a7713b1edbc 382 #define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
AnnaBridge 171:3a7713b1edbc 383 #define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
AnnaBridge 171:3a7713b1edbc 384 #define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
AnnaBridge 171:3a7713b1edbc 385 #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
AnnaBridge 171:3a7713b1edbc 386 #define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
AnnaBridge 171:3a7713b1edbc 388 #define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
AnnaBridge 171:3a7713b1edbc 389 #define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 390 #define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
AnnaBridge 171:3a7713b1edbc 391 #define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
AnnaBridge 171:3a7713b1edbc 392 #define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
AnnaBridge 171:3a7713b1edbc 393 #define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
AnnaBridge 171:3a7713b1edbc 394 #define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */
AnnaBridge 171:3a7713b1edbc 395 #define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */
AnnaBridge 171:3a7713b1edbc 396 #define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */
AnnaBridge 171:3a7713b1edbc 397 #define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 398 #define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 399 #define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 400 #define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 401 #define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 402 #define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
AnnaBridge 171:3a7713b1edbc 403 #define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
AnnaBridge 171:3a7713b1edbc 406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 407 typedef union {
AnnaBridge 171:3a7713b1edbc 408 struct {
AnnaBridge 171:3a7713b1edbc 409 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
AnnaBridge 171:3a7713b1edbc 410 uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
AnnaBridge 171:3a7713b1edbc 411 uint8_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 412 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
AnnaBridge 171:3a7713b1edbc 413 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
AnnaBridge 171:3a7713b1edbc 414 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 415 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 416 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 417 } ADC_EVCTRL_Type;
AnnaBridge 171:3a7713b1edbc 418 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 #define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
AnnaBridge 171:3a7713b1edbc 421 #define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 #define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
AnnaBridge 171:3a7713b1edbc 424 #define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos)
AnnaBridge 171:3a7713b1edbc 425 #define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
AnnaBridge 171:3a7713b1edbc 426 #define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
AnnaBridge 171:3a7713b1edbc 427 #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
AnnaBridge 171:3a7713b1edbc 428 #define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
AnnaBridge 171:3a7713b1edbc 429 #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
AnnaBridge 171:3a7713b1edbc 430 #define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
AnnaBridge 171:3a7713b1edbc 431 #define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 435 typedef union {
AnnaBridge 171:3a7713b1edbc 436 struct {
AnnaBridge 171:3a7713b1edbc 437 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 438 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 439 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 440 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 441 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 442 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 443 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 444 } ADC_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 445 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 448 #define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 451 #define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos)
AnnaBridge 171:3a7713b1edbc 452 #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 453 #define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
AnnaBridge 171:3a7713b1edbc 454 #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 455 #define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos)
AnnaBridge 171:3a7713b1edbc 456 #define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 457 #define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 461 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 462 typedef union {
AnnaBridge 171:3a7713b1edbc 463 struct {
AnnaBridge 171:3a7713b1edbc 464 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 465 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 466 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 467 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 468 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 469 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 470 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 471 } ADC_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 472 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 #define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 475 #define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 478 #define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos)
AnnaBridge 171:3a7713b1edbc 479 #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 480 #define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos)
AnnaBridge 171:3a7713b1edbc 481 #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 482 #define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos)
AnnaBridge 171:3a7713b1edbc 483 #define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 484 #define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 485 #define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 488 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 489 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 490 struct {
AnnaBridge 171:3a7713b1edbc 491 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
AnnaBridge 171:3a7713b1edbc 492 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
AnnaBridge 171:3a7713b1edbc 493 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
AnnaBridge 171:3a7713b1edbc 494 __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 495 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 496 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 497 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 498 } ADC_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 #define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 502 #define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 503
AnnaBridge 171:3a7713b1edbc 504 #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
AnnaBridge 171:3a7713b1edbc 505 #define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos)
AnnaBridge 171:3a7713b1edbc 506 #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
AnnaBridge 171:3a7713b1edbc 507 #define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
AnnaBridge 171:3a7713b1edbc 508 #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
AnnaBridge 171:3a7713b1edbc 509 #define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos)
AnnaBridge 171:3a7713b1edbc 510 #define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
AnnaBridge 171:3a7713b1edbc 511 #define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
AnnaBridge 171:3a7713b1edbc 512 #define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
AnnaBridge 171:3a7713b1edbc 515 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 516 typedef union {
AnnaBridge 171:3a7713b1edbc 517 struct {
AnnaBridge 171:3a7713b1edbc 518 uint8_t :7; /*!< bit: 0.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 519 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 520 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 521 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 522 } ADC_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 #define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 526 #define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 #define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 529 #define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 530 #define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
AnnaBridge 171:3a7713b1edbc 533 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 534 typedef union {
AnnaBridge 171:3a7713b1edbc 535 struct {
AnnaBridge 171:3a7713b1edbc 536 uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
AnnaBridge 171:3a7713b1edbc 537 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 538 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 539 } ADC_RESULT_Type;
AnnaBridge 171:3a7713b1edbc 540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 541
AnnaBridge 171:3a7713b1edbc 542 #define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
AnnaBridge 171:3a7713b1edbc 543 #define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */
AnnaBridge 171:3a7713b1edbc 544
AnnaBridge 171:3a7713b1edbc 545 #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
AnnaBridge 171:3a7713b1edbc 546 #define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
AnnaBridge 171:3a7713b1edbc 547 #define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
AnnaBridge 171:3a7713b1edbc 548 #define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
AnnaBridge 171:3a7713b1edbc 551 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 552 typedef union {
AnnaBridge 171:3a7713b1edbc 553 struct {
AnnaBridge 171:3a7713b1edbc 554 uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
AnnaBridge 171:3a7713b1edbc 555 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 556 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 557 } ADC_WINLT_Type;
AnnaBridge 171:3a7713b1edbc 558 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 #define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
AnnaBridge 171:3a7713b1edbc 561 #define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
AnnaBridge 171:3a7713b1edbc 564 #define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
AnnaBridge 171:3a7713b1edbc 565 #define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
AnnaBridge 171:3a7713b1edbc 566 #define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
AnnaBridge 171:3a7713b1edbc 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 570 typedef union {
AnnaBridge 171:3a7713b1edbc 571 struct {
AnnaBridge 171:3a7713b1edbc 572 uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
AnnaBridge 171:3a7713b1edbc 573 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 574 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 575 } ADC_WINUT_Type;
AnnaBridge 171:3a7713b1edbc 576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 #define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
AnnaBridge 171:3a7713b1edbc 579 #define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
AnnaBridge 171:3a7713b1edbc 582 #define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
AnnaBridge 171:3a7713b1edbc 583 #define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
AnnaBridge 171:3a7713b1edbc 584 #define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
AnnaBridge 171:3a7713b1edbc 587 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 588 typedef union {
AnnaBridge 171:3a7713b1edbc 589 struct {
AnnaBridge 171:3a7713b1edbc 590 uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
AnnaBridge 171:3a7713b1edbc 591 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 592 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 593 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 594 } ADC_GAINCORR_Type;
AnnaBridge 171:3a7713b1edbc 595 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 #define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
AnnaBridge 171:3a7713b1edbc 598 #define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
AnnaBridge 171:3a7713b1edbc 601 #define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
AnnaBridge 171:3a7713b1edbc 602 #define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
AnnaBridge 171:3a7713b1edbc 603 #define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
AnnaBridge 171:3a7713b1edbc 606 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 607 typedef union {
AnnaBridge 171:3a7713b1edbc 608 struct {
AnnaBridge 171:3a7713b1edbc 609 uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
AnnaBridge 171:3a7713b1edbc 610 uint16_t :4; /*!< bit: 12..15 Reserved */
AnnaBridge 171:3a7713b1edbc 611 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 612 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 613 } ADC_OFFSETCORR_Type;
AnnaBridge 171:3a7713b1edbc 614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 #define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
AnnaBridge 171:3a7713b1edbc 617 #define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
AnnaBridge 171:3a7713b1edbc 620 #define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
AnnaBridge 171:3a7713b1edbc 621 #define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
AnnaBridge 171:3a7713b1edbc 622 #define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
AnnaBridge 171:3a7713b1edbc 625 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 626 typedef union {
AnnaBridge 171:3a7713b1edbc 627 struct {
AnnaBridge 171:3a7713b1edbc 628 uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
AnnaBridge 171:3a7713b1edbc 629 uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
AnnaBridge 171:3a7713b1edbc 630 uint16_t :5; /*!< bit: 11..15 Reserved */
AnnaBridge 171:3a7713b1edbc 631 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 632 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 633 } ADC_CALIB_Type;
AnnaBridge 171:3a7713b1edbc 634 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
AnnaBridge 171:3a7713b1edbc 637 #define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 #define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
AnnaBridge 171:3a7713b1edbc 640 #define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
AnnaBridge 171:3a7713b1edbc 641 #define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
AnnaBridge 171:3a7713b1edbc 642 #define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
AnnaBridge 171:3a7713b1edbc 643 #define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
AnnaBridge 171:3a7713b1edbc 644 #define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
AnnaBridge 171:3a7713b1edbc 645 #define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 649 typedef union {
AnnaBridge 171:3a7713b1edbc 650 struct {
AnnaBridge 171:3a7713b1edbc 651 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
AnnaBridge 171:3a7713b1edbc 652 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 653 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 654 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 655 } ADC_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 656 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 657
AnnaBridge 171:3a7713b1edbc 658 #define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
AnnaBridge 171:3a7713b1edbc 659 #define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
AnnaBridge 171:3a7713b1edbc 662 #define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
AnnaBridge 171:3a7713b1edbc 663 #define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 /** \brief ADC hardware registers */
AnnaBridge 171:3a7713b1edbc 666 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 667 typedef struct {
AnnaBridge 171:3a7713b1edbc 668 __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
AnnaBridge 171:3a7713b1edbc 669 __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
AnnaBridge 171:3a7713b1edbc 670 __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
AnnaBridge 171:3a7713b1edbc 671 __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
AnnaBridge 171:3a7713b1edbc 672 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
AnnaBridge 171:3a7713b1edbc 673 RoReg8 Reserved1[0x2];
AnnaBridge 171:3a7713b1edbc 674 __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
AnnaBridge 171:3a7713b1edbc 675 RoReg8 Reserved2[0x3];
AnnaBridge 171:3a7713b1edbc 676 __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
AnnaBridge 171:3a7713b1edbc 677 RoReg8 Reserved3[0x3];
AnnaBridge 171:3a7713b1edbc 678 __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
AnnaBridge 171:3a7713b1edbc 679 __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
AnnaBridge 171:3a7713b1edbc 680 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 681 __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 682 __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 683 __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 684 __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 685 __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
AnnaBridge 171:3a7713b1edbc 686 __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
AnnaBridge 171:3a7713b1edbc 687 RoReg8 Reserved5[0x2];
AnnaBridge 171:3a7713b1edbc 688 __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
AnnaBridge 171:3a7713b1edbc 689 RoReg8 Reserved6[0x2];
AnnaBridge 171:3a7713b1edbc 690 __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
AnnaBridge 171:3a7713b1edbc 691 __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
AnnaBridge 171:3a7713b1edbc 692 __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
AnnaBridge 171:3a7713b1edbc 693 __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
AnnaBridge 171:3a7713b1edbc 694 } Adc;
AnnaBridge 171:3a7713b1edbc 695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /*@}*/
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699 #endif /* _SAMR21_ADC_COMPONENT_ */