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TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/comp_i2s.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for I2S
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43 /*
AnnaBridge 171:3a7713b1edbc 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
AnnaBridge 171:3a7713b1edbc 45 */
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 #ifndef _SAMD21_I2S_COMPONENT_
AnnaBridge 171:3a7713b1edbc 48 #define _SAMD21_I2S_COMPONENT_
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 51 /** SOFTWARE API DEFINITION FOR I2S */
AnnaBridge 171:3a7713b1edbc 52 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 53 /** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
AnnaBridge 171:3a7713b1edbc 54 /*@{*/
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 #define I2S_U2224
AnnaBridge 171:3a7713b1edbc 57 #define REV_I2S 0x110
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
AnnaBridge 171:3a7713b1edbc 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 61 typedef union {
AnnaBridge 171:3a7713b1edbc 62 struct {
AnnaBridge 171:3a7713b1edbc 63 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 64 uint8_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 65 uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
AnnaBridge 171:3a7713b1edbc 66 uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
AnnaBridge 171:3a7713b1edbc 67 uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
AnnaBridge 171:3a7713b1edbc 68 uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
AnnaBridge 171:3a7713b1edbc 69 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 70 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 71 struct {
AnnaBridge 171:3a7713b1edbc 72 uint8_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 73 uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
AnnaBridge 171:3a7713b1edbc 74 uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
AnnaBridge 171:3a7713b1edbc 75 uint8_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 76 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 77 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 78 } I2S_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 #define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
AnnaBridge 171:3a7713b1edbc 82 #define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 #define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 85 #define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 86 #define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 87 #define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 88 #define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
AnnaBridge 171:3a7713b1edbc 89 #define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
AnnaBridge 171:3a7713b1edbc 90 #define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
AnnaBridge 171:3a7713b1edbc 91 #define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
AnnaBridge 171:3a7713b1edbc 92 #define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
AnnaBridge 171:3a7713b1edbc 93 #define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos)
AnnaBridge 171:3a7713b1edbc 94 #define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
AnnaBridge 171:3a7713b1edbc 95 #define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
AnnaBridge 171:3a7713b1edbc 96 #define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
AnnaBridge 171:3a7713b1edbc 97 #define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
AnnaBridge 171:3a7713b1edbc 98 #define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
AnnaBridge 171:3a7713b1edbc 99 #define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
AnnaBridge 171:3a7713b1edbc 100 #define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos)
AnnaBridge 171:3a7713b1edbc 101 #define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
AnnaBridge 171:3a7713b1edbc 102 #define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
AnnaBridge 171:3a7713b1edbc 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 106 typedef union {
AnnaBridge 171:3a7713b1edbc 107 struct {
AnnaBridge 171:3a7713b1edbc 108 uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
AnnaBridge 171:3a7713b1edbc 109 uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
AnnaBridge 171:3a7713b1edbc 110 uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
AnnaBridge 171:3a7713b1edbc 111 uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
AnnaBridge 171:3a7713b1edbc 112 uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
AnnaBridge 171:3a7713b1edbc 113 uint32_t :2; /*!< bit: 9..10 Reserved */
AnnaBridge 171:3a7713b1edbc 114 uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
AnnaBridge 171:3a7713b1edbc 115 uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
AnnaBridge 171:3a7713b1edbc 116 uint32_t :3; /*!< bit: 13..15 Reserved */
AnnaBridge 171:3a7713b1edbc 117 uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
AnnaBridge 171:3a7713b1edbc 118 uint32_t :1; /*!< bit: 17 Reserved */
AnnaBridge 171:3a7713b1edbc 119 uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
AnnaBridge 171:3a7713b1edbc 120 uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
AnnaBridge 171:3a7713b1edbc 121 uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
AnnaBridge 171:3a7713b1edbc 122 uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
AnnaBridge 171:3a7713b1edbc 123 uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
AnnaBridge 171:3a7713b1edbc 124 uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
AnnaBridge 171:3a7713b1edbc 125 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 126 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 127 } I2S_CLKCTRL_Type;
AnnaBridge 171:3a7713b1edbc 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 #define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
AnnaBridge 171:3a7713b1edbc 131 #define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 #define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
AnnaBridge 171:3a7713b1edbc 134 #define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 135 #define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
AnnaBridge 171:3a7713b1edbc 136 #define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
AnnaBridge 171:3a7713b1edbc 137 #define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
AnnaBridge 171:3a7713b1edbc 138 #define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
AnnaBridge 171:3a7713b1edbc 139 #define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
AnnaBridge 171:3a7713b1edbc 140 #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 142 #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 144 #define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
AnnaBridge 171:3a7713b1edbc 145 #define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
AnnaBridge 171:3a7713b1edbc 146 #define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
AnnaBridge 171:3a7713b1edbc 147 #define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
AnnaBridge 171:3a7713b1edbc 148 #define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
AnnaBridge 171:3a7713b1edbc 149 #define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
AnnaBridge 171:3a7713b1edbc 150 #define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
AnnaBridge 171:3a7713b1edbc 151 #define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
AnnaBridge 171:3a7713b1edbc 152 #define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
AnnaBridge 171:3a7713b1edbc 153 #define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
AnnaBridge 171:3a7713b1edbc 154 #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
AnnaBridge 171:3a7713b1edbc 155 #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
AnnaBridge 171:3a7713b1edbc 156 #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
AnnaBridge 171:3a7713b1edbc 157 #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
AnnaBridge 171:3a7713b1edbc 158 #define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
AnnaBridge 171:3a7713b1edbc 159 #define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
AnnaBridge 171:3a7713b1edbc 160 #define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
AnnaBridge 171:3a7713b1edbc 161 #define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
AnnaBridge 171:3a7713b1edbc 162 #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
AnnaBridge 171:3a7713b1edbc 163 #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
AnnaBridge 171:3a7713b1edbc 164 #define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
AnnaBridge 171:3a7713b1edbc 165 #define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
AnnaBridge 171:3a7713b1edbc 166 #define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
AnnaBridge 171:3a7713b1edbc 167 #define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
AnnaBridge 171:3a7713b1edbc 168 #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
AnnaBridge 171:3a7713b1edbc 169 #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
AnnaBridge 171:3a7713b1edbc 170 #define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
AnnaBridge 171:3a7713b1edbc 171 #define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos)
AnnaBridge 171:3a7713b1edbc 172 #define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
AnnaBridge 171:3a7713b1edbc 173 #define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 174 #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
AnnaBridge 171:3a7713b1edbc 175 #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
AnnaBridge 171:3a7713b1edbc 176 #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 177 #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 178 #define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
AnnaBridge 171:3a7713b1edbc 179 #define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 180 #define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
AnnaBridge 171:3a7713b1edbc 181 #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
AnnaBridge 171:3a7713b1edbc 182 #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 183 #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 184 #define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
AnnaBridge 171:3a7713b1edbc 185 #define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
AnnaBridge 171:3a7713b1edbc 186 #define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
AnnaBridge 171:3a7713b1edbc 187 #define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
AnnaBridge 171:3a7713b1edbc 188 #define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
AnnaBridge 171:3a7713b1edbc 189 #define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
AnnaBridge 171:3a7713b1edbc 190 #define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
AnnaBridge 171:3a7713b1edbc 192 #define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
AnnaBridge 171:3a7713b1edbc 193 #define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
AnnaBridge 171:3a7713b1edbc 194 #define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
AnnaBridge 171:3a7713b1edbc 195 #define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
AnnaBridge 171:3a7713b1edbc 196 #define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
AnnaBridge 171:3a7713b1edbc 197 #define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
AnnaBridge 171:3a7713b1edbc 198 #define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 202 typedef union {
AnnaBridge 171:3a7713b1edbc 203 struct {
AnnaBridge 171:3a7713b1edbc 204 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 205 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 206 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 207 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 208 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 209 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 210 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 211 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 212 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 213 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 214 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 215 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 216 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 217 struct {
AnnaBridge 171:3a7713b1edbc 218 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 219 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 220 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 221 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 222 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 223 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 224 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 225 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 226 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 227 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 228 } I2S_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 #define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 232 #define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 #define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 235 #define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 236 #define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 237 #define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 238 #define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 239 #define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 240 #define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 241 #define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 242 #define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
AnnaBridge 171:3a7713b1edbc 243 #define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 244 #define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
AnnaBridge 171:3a7713b1edbc 245 #define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 246 #define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos)
AnnaBridge 171:3a7713b1edbc 247 #define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
AnnaBridge 171:3a7713b1edbc 248 #define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 249 #define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 250 #define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 251 #define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 253 #define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 254 #define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 255 #define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 256 #define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
AnnaBridge 171:3a7713b1edbc 257 #define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 258 #define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
AnnaBridge 171:3a7713b1edbc 259 #define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 260 #define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos)
AnnaBridge 171:3a7713b1edbc 261 #define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
AnnaBridge 171:3a7713b1edbc 262 #define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 266 typedef union {
AnnaBridge 171:3a7713b1edbc 267 struct {
AnnaBridge 171:3a7713b1edbc 268 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 269 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 270 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 271 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 272 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 273 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 274 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 275 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 276 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 277 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 278 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 279 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 280 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 281 struct {
AnnaBridge 171:3a7713b1edbc 282 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 283 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 284 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 285 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 286 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 287 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 288 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 289 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 290 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 291 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 292 } I2S_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 #define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 296 #define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 #define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 299 #define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 300 #define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 301 #define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 302 #define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 303 #define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 305 #define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 306 #define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
AnnaBridge 171:3a7713b1edbc 307 #define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 308 #define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
AnnaBridge 171:3a7713b1edbc 309 #define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 310 #define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos)
AnnaBridge 171:3a7713b1edbc 311 #define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
AnnaBridge 171:3a7713b1edbc 312 #define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 313 #define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 314 #define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 315 #define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 316 #define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 317 #define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 318 #define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 319 #define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 320 #define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
AnnaBridge 171:3a7713b1edbc 321 #define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 322 #define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
AnnaBridge 171:3a7713b1edbc 323 #define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 324 #define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos)
AnnaBridge 171:3a7713b1edbc 325 #define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
AnnaBridge 171:3a7713b1edbc 326 #define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 330 typedef union {
AnnaBridge 171:3a7713b1edbc 331 struct {
AnnaBridge 171:3a7713b1edbc 332 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
AnnaBridge 171:3a7713b1edbc 333 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
AnnaBridge 171:3a7713b1edbc 334 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 335 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
AnnaBridge 171:3a7713b1edbc 336 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
AnnaBridge 171:3a7713b1edbc 337 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 338 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
AnnaBridge 171:3a7713b1edbc 339 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
AnnaBridge 171:3a7713b1edbc 340 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 341 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
AnnaBridge 171:3a7713b1edbc 342 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
AnnaBridge 171:3a7713b1edbc 343 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 344 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 345 struct {
AnnaBridge 171:3a7713b1edbc 346 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
AnnaBridge 171:3a7713b1edbc 347 uint16_t :2; /*!< bit: 2.. 3 Reserved */
AnnaBridge 171:3a7713b1edbc 348 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
AnnaBridge 171:3a7713b1edbc 349 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 350 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
AnnaBridge 171:3a7713b1edbc 351 uint16_t :2; /*!< bit: 10..11 Reserved */
AnnaBridge 171:3a7713b1edbc 352 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
AnnaBridge 171:3a7713b1edbc 353 uint16_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 354 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 355 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 356 } I2S_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 360 #define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
AnnaBridge 171:3a7713b1edbc 363 #define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 364 #define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
AnnaBridge 171:3a7713b1edbc 365 #define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 366 #define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
AnnaBridge 171:3a7713b1edbc 367 #define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 368 #define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 369 #define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
AnnaBridge 171:3a7713b1edbc 370 #define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
AnnaBridge 171:3a7713b1edbc 371 #define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
AnnaBridge 171:3a7713b1edbc 372 #define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
AnnaBridge 171:3a7713b1edbc 373 #define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
AnnaBridge 171:3a7713b1edbc 374 #define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos)
AnnaBridge 171:3a7713b1edbc 375 #define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
AnnaBridge 171:3a7713b1edbc 376 #define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
AnnaBridge 171:3a7713b1edbc 377 #define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
AnnaBridge 171:3a7713b1edbc 378 #define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
AnnaBridge 171:3a7713b1edbc 379 #define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
AnnaBridge 171:3a7713b1edbc 380 #define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
AnnaBridge 171:3a7713b1edbc 381 #define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos)
AnnaBridge 171:3a7713b1edbc 382 #define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
AnnaBridge 171:3a7713b1edbc 383 #define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
AnnaBridge 171:3a7713b1edbc 384 #define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
AnnaBridge 171:3a7713b1edbc 385 #define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
AnnaBridge 171:3a7713b1edbc 386 #define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
AnnaBridge 171:3a7713b1edbc 387 #define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
AnnaBridge 171:3a7713b1edbc 388 #define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos)
AnnaBridge 171:3a7713b1edbc 389 #define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
AnnaBridge 171:3a7713b1edbc 390 #define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
AnnaBridge 171:3a7713b1edbc 393 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 394 typedef union {
AnnaBridge 171:3a7713b1edbc 395 struct {
AnnaBridge 171:3a7713b1edbc 396 uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
AnnaBridge 171:3a7713b1edbc 397 uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 398 uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 399 uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 400 uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 401 uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 402 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 403 uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
AnnaBridge 171:3a7713b1edbc 404 uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
AnnaBridge 171:3a7713b1edbc 405 uint16_t :6; /*!< bit: 10..15 Reserved */
AnnaBridge 171:3a7713b1edbc 406 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 407 struct {
AnnaBridge 171:3a7713b1edbc 408 uint16_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 409 uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 410 uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 411 uint16_t :2; /*!< bit: 6.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 412 uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
AnnaBridge 171:3a7713b1edbc 413 uint16_t :6; /*!< bit: 10..15 Reserved */
AnnaBridge 171:3a7713b1edbc 414 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 415 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 416 } I2S_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 #define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
AnnaBridge 171:3a7713b1edbc 420 #define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
AnnaBridge 171:3a7713b1edbc 423 #define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 424 #define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 425 #define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 426 #define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 427 #define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
AnnaBridge 171:3a7713b1edbc 428 #define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 429 #define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
AnnaBridge 171:3a7713b1edbc 430 #define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 431 #define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
AnnaBridge 171:3a7713b1edbc 432 #define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
AnnaBridge 171:3a7713b1edbc 433 #define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 434 #define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
AnnaBridge 171:3a7713b1edbc 435 #define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 436 #define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
AnnaBridge 171:3a7713b1edbc 437 #define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
AnnaBridge 171:3a7713b1edbc 438 #define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
AnnaBridge 171:3a7713b1edbc 439 #define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
AnnaBridge 171:3a7713b1edbc 440 #define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
AnnaBridge 171:3a7713b1edbc 441 #define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
AnnaBridge 171:3a7713b1edbc 442 #define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
AnnaBridge 171:3a7713b1edbc 443 #define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
AnnaBridge 171:3a7713b1edbc 444 #define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
AnnaBridge 171:3a7713b1edbc 445 #define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 446 #define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
AnnaBridge 171:3a7713b1edbc 447 #define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
AnnaBridge 171:3a7713b1edbc 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 451 typedef union {
AnnaBridge 171:3a7713b1edbc 452 struct {
AnnaBridge 171:3a7713b1edbc 453 uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
AnnaBridge 171:3a7713b1edbc 454 uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
AnnaBridge 171:3a7713b1edbc 455 uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
AnnaBridge 171:3a7713b1edbc 456 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
AnnaBridge 171:3a7713b1edbc 457 uint32_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 458 uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
AnnaBridge 171:3a7713b1edbc 459 uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
AnnaBridge 171:3a7713b1edbc 460 uint32_t :1; /*!< bit: 11 Reserved */
AnnaBridge 171:3a7713b1edbc 461 uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
AnnaBridge 171:3a7713b1edbc 462 uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
AnnaBridge 171:3a7713b1edbc 463 uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
AnnaBridge 171:3a7713b1edbc 464 uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 465 uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 466 uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 467 uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 468 uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 469 uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 470 uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 471 uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 472 uint32_t MONO:1; /*!< bit: 24 Mono Mode */
AnnaBridge 171:3a7713b1edbc 473 uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
AnnaBridge 171:3a7713b1edbc 474 uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
AnnaBridge 171:3a7713b1edbc 475 uint32_t :5; /*!< bit: 27..31 Reserved */
AnnaBridge 171:3a7713b1edbc 476 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 477 struct {
AnnaBridge 171:3a7713b1edbc 478 uint32_t :16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 479 uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 480 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 481 } vec; /*!< Structure used for vec access */
AnnaBridge 171:3a7713b1edbc 482 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 483 } I2S_SERCTRL_Type;
AnnaBridge 171:3a7713b1edbc 484 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 #define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
AnnaBridge 171:3a7713b1edbc 487 #define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 #define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
AnnaBridge 171:3a7713b1edbc 490 #define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos)
AnnaBridge 171:3a7713b1edbc 491 #define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
AnnaBridge 171:3a7713b1edbc 492 #define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */
AnnaBridge 171:3a7713b1edbc 493 #define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */
AnnaBridge 171:3a7713b1edbc 494 #define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
AnnaBridge 171:3a7713b1edbc 495 #define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
AnnaBridge 171:3a7713b1edbc 496 #define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
AnnaBridge 171:3a7713b1edbc 497 #define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
AnnaBridge 171:3a7713b1edbc 498 #define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
AnnaBridge 171:3a7713b1edbc 499 #define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
AnnaBridge 171:3a7713b1edbc 500 #define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
AnnaBridge 171:3a7713b1edbc 501 #define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
AnnaBridge 171:3a7713b1edbc 502 #define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
AnnaBridge 171:3a7713b1edbc 503 #define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
AnnaBridge 171:3a7713b1edbc 504 #define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
AnnaBridge 171:3a7713b1edbc 505 #define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
AnnaBridge 171:3a7713b1edbc 506 #define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
AnnaBridge 171:3a7713b1edbc 507 #define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
AnnaBridge 171:3a7713b1edbc 508 #define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos)
AnnaBridge 171:3a7713b1edbc 509 #define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
AnnaBridge 171:3a7713b1edbc 510 #define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
AnnaBridge 171:3a7713b1edbc 511 #define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
AnnaBridge 171:3a7713b1edbc 512 #define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
AnnaBridge 171:3a7713b1edbc 513 #define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
AnnaBridge 171:3a7713b1edbc 514 #define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 515 #define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
AnnaBridge 171:3a7713b1edbc 516 #define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
AnnaBridge 171:3a7713b1edbc 517 #define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 518 #define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
AnnaBridge 171:3a7713b1edbc 519 #define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
AnnaBridge 171:3a7713b1edbc 520 #define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
AnnaBridge 171:3a7713b1edbc 521 #define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
AnnaBridge 171:3a7713b1edbc 522 #define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
AnnaBridge 171:3a7713b1edbc 523 #define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
AnnaBridge 171:3a7713b1edbc 524 #define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
AnnaBridge 171:3a7713b1edbc 525 #define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
AnnaBridge 171:3a7713b1edbc 526 #define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 527 #define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
AnnaBridge 171:3a7713b1edbc 528 #define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */
AnnaBridge 171:3a7713b1edbc 529 #define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */
AnnaBridge 171:3a7713b1edbc 530 #define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */
AnnaBridge 171:3a7713b1edbc 531 #define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */
AnnaBridge 171:3a7713b1edbc 532 #define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */
AnnaBridge 171:3a7713b1edbc 533 #define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
AnnaBridge 171:3a7713b1edbc 534 #define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */
AnnaBridge 171:3a7713b1edbc 535 #define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
AnnaBridge 171:3a7713b1edbc 536 #define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 537 #define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 538 #define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 539 #define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 540 #define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 541 #define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 542 #define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 543 #define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
AnnaBridge 171:3a7713b1edbc 544 #define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
AnnaBridge 171:3a7713b1edbc 545 #define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
AnnaBridge 171:3a7713b1edbc 546 #define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
AnnaBridge 171:3a7713b1edbc 547 #define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
AnnaBridge 171:3a7713b1edbc 548 #define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
AnnaBridge 171:3a7713b1edbc 549 #define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
AnnaBridge 171:3a7713b1edbc 550 #define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
AnnaBridge 171:3a7713b1edbc 551 #define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos)
AnnaBridge 171:3a7713b1edbc 552 #define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
AnnaBridge 171:3a7713b1edbc 553 #define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */
AnnaBridge 171:3a7713b1edbc 554 #define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */
AnnaBridge 171:3a7713b1edbc 555 #define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
AnnaBridge 171:3a7713b1edbc 556 #define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
AnnaBridge 171:3a7713b1edbc 557 #define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
AnnaBridge 171:3a7713b1edbc 558 #define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
AnnaBridge 171:3a7713b1edbc 559 #define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
AnnaBridge 171:3a7713b1edbc 561 #define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
AnnaBridge 171:3a7713b1edbc 562 #define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos)
AnnaBridge 171:3a7713b1edbc 563 #define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
AnnaBridge 171:3a7713b1edbc 564 #define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
AnnaBridge 171:3a7713b1edbc 565 #define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
AnnaBridge 171:3a7713b1edbc 566 #define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
AnnaBridge 171:3a7713b1edbc 567 #define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 568 #define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
AnnaBridge 171:3a7713b1edbc 569 #define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 570 #define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
AnnaBridge 171:3a7713b1edbc 571 #define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 572 #define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
AnnaBridge 171:3a7713b1edbc 573 #define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 574 #define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
AnnaBridge 171:3a7713b1edbc 575 #define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 576 #define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
AnnaBridge 171:3a7713b1edbc 577 #define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 578 #define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
AnnaBridge 171:3a7713b1edbc 579 #define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 580 #define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
AnnaBridge 171:3a7713b1edbc 581 #define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 582 #define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
AnnaBridge 171:3a7713b1edbc 583 #define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
AnnaBridge 171:3a7713b1edbc 584 #define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
AnnaBridge 171:3a7713b1edbc 585 #define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
AnnaBridge 171:3a7713b1edbc 586 #define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
AnnaBridge 171:3a7713b1edbc 587 #define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos)
AnnaBridge 171:3a7713b1edbc 588 #define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */
AnnaBridge 171:3a7713b1edbc 589 #define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
AnnaBridge 171:3a7713b1edbc 590 #define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
AnnaBridge 171:3a7713b1edbc 591 #define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
AnnaBridge 171:3a7713b1edbc 592 #define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
AnnaBridge 171:3a7713b1edbc 593 #define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos)
AnnaBridge 171:3a7713b1edbc 594 #define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */
AnnaBridge 171:3a7713b1edbc 595 #define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
AnnaBridge 171:3a7713b1edbc 596 #define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
AnnaBridge 171:3a7713b1edbc 597 #define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
AnnaBridge 171:3a7713b1edbc 598 #define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
AnnaBridge 171:3a7713b1edbc 599 #define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
AnnaBridge 171:3a7713b1edbc 600 #define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
AnnaBridge 171:3a7713b1edbc 603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 604 typedef union {
AnnaBridge 171:3a7713b1edbc 605 struct {
AnnaBridge 171:3a7713b1edbc 606 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
AnnaBridge 171:3a7713b1edbc 607 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 608 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 609 } I2S_DATA_Type;
AnnaBridge 171:3a7713b1edbc 610 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612 #define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
AnnaBridge 171:3a7713b1edbc 613 #define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
AnnaBridge 171:3a7713b1edbc 614
AnnaBridge 171:3a7713b1edbc 615 #define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
AnnaBridge 171:3a7713b1edbc 616 #define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 617 #define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
AnnaBridge 171:3a7713b1edbc 618 #define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 /** \brief I2S hardware registers */
AnnaBridge 171:3a7713b1edbc 621 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 622 typedef struct {
AnnaBridge 171:3a7713b1edbc 623 __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
AnnaBridge 171:3a7713b1edbc 624 RoReg8 Reserved1[0x3];
AnnaBridge 171:3a7713b1edbc 625 __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
AnnaBridge 171:3a7713b1edbc 626 __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 627 RoReg8 Reserved2[0x2];
AnnaBridge 171:3a7713b1edbc 628 __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 629 RoReg8 Reserved3[0x2];
AnnaBridge 171:3a7713b1edbc 630 __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 631 RoReg8 Reserved4[0x2];
AnnaBridge 171:3a7713b1edbc 632 __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
AnnaBridge 171:3a7713b1edbc 633 RoReg8 Reserved5[0x6];
AnnaBridge 171:3a7713b1edbc 634 __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
AnnaBridge 171:3a7713b1edbc 635 RoReg8 Reserved6[0x8];
AnnaBridge 171:3a7713b1edbc 636 __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
AnnaBridge 171:3a7713b1edbc 637 } I2s;
AnnaBridge 171:3a7713b1edbc 638 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /*@}*/
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 #endif /* _SAMD21_I2S_COMPONENT_ */