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TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/spibsc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_VK_RZ_A1H/TARGET_RENESAS/TARGET_RZ_A1XX/spibsc.h@170:e95d10626187
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 170:e95d10626187 | 1 | /******************************************************************************* |
| AnnaBridge | 170:e95d10626187 | 2 | * DISCLAIMER |
| AnnaBridge | 170:e95d10626187 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| AnnaBridge | 170:e95d10626187 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| AnnaBridge | 170:e95d10626187 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| AnnaBridge | 170:e95d10626187 | 6 | * all applicable laws, including copyright laws. |
| AnnaBridge | 170:e95d10626187 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| AnnaBridge | 170:e95d10626187 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| AnnaBridge | 170:e95d10626187 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| AnnaBridge | 170:e95d10626187 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| AnnaBridge | 170:e95d10626187 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| AnnaBridge | 170:e95d10626187 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| AnnaBridge | 170:e95d10626187 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| AnnaBridge | 170:e95d10626187 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| AnnaBridge | 170:e95d10626187 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| AnnaBridge | 170:e95d10626187 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| AnnaBridge | 170:e95d10626187 | 17 | * and to discontinue the availability of this software. By using this software, |
| AnnaBridge | 170:e95d10626187 | 18 | * you agree to the additional terms and conditions found by accessing the |
| AnnaBridge | 170:e95d10626187 | 19 | * following link: |
| AnnaBridge | 170:e95d10626187 | 20 | * http://www.renesas.com/disclaimer |
| AnnaBridge | 170:e95d10626187 | 21 | * |
| AnnaBridge | 170:e95d10626187 | 22 | * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. |
| AnnaBridge | 170:e95d10626187 | 23 | *******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 24 | /****************************************************************************** |
| AnnaBridge | 170:e95d10626187 | 25 | * File Name : spibsc.h |
| AnnaBridge | 170:e95d10626187 | 26 | * $Rev: 12 $ |
| AnnaBridge | 170:e95d10626187 | 27 | * $Date:: 2016-05-19 17:26:37 +0900#$ |
| AnnaBridge | 170:e95d10626187 | 28 | * Description : |
| AnnaBridge | 170:e95d10626187 | 29 | ******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 30 | #ifndef _SPIBSC_H_ |
| AnnaBridge | 170:e95d10626187 | 31 | #define _SPIBSC_H_ |
| AnnaBridge | 170:e95d10626187 | 32 | |
| AnnaBridge | 170:e95d10626187 | 33 | /****************************************************************************** |
| AnnaBridge | 170:e95d10626187 | 34 | Includes <System Includes> , "Project Includes" |
| AnnaBridge | 170:e95d10626187 | 35 | ******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 36 | #include "iodefine.h" |
| AnnaBridge | 170:e95d10626187 | 37 | |
| AnnaBridge | 170:e95d10626187 | 38 | /****************************************************************************** |
| AnnaBridge | 170:e95d10626187 | 39 | Macro definitions |
| AnnaBridge | 170:e95d10626187 | 40 | ******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 41 | #define SPIBSC_CMNCR_MD_EXTRD (0u) |
| AnnaBridge | 170:e95d10626187 | 42 | #define SPIBSC_CMNCR_MD_SPI (1u) |
| AnnaBridge | 170:e95d10626187 | 43 | |
| AnnaBridge | 170:e95d10626187 | 44 | #define SPIBSC_OUTPUT_LOW (0u) |
| AnnaBridge | 170:e95d10626187 | 45 | #define SPIBSC_OUTPUT_HIGH (1u) |
| AnnaBridge | 170:e95d10626187 | 46 | #define SPIBSC_OUTPUT_LAST (2u) |
| AnnaBridge | 170:e95d10626187 | 47 | #define SPIBSC_OUTPUT_HiZ (3u) |
| AnnaBridge | 170:e95d10626187 | 48 | |
| AnnaBridge | 170:e95d10626187 | 49 | #define SPIBSC_CMNCR_CPHAT_EVEN (0u) |
| AnnaBridge | 170:e95d10626187 | 50 | #define SPIBSC_CMNCR_CPHAT_ODD (1u) |
| AnnaBridge | 170:e95d10626187 | 51 | |
| AnnaBridge | 170:e95d10626187 | 52 | #define SPIBSC_CMNCR_CPHAR_ODD (0u) |
| AnnaBridge | 170:e95d10626187 | 53 | #define SPIBSC_CMNCR_CPHAR_EVEN (1u) |
| AnnaBridge | 170:e95d10626187 | 54 | |
| AnnaBridge | 170:e95d10626187 | 55 | #define SPIBSC_CMNCR_SSLP_LOW (0u) |
| AnnaBridge | 170:e95d10626187 | 56 | #define SPIBSC_CMNCR_SSLP_HIGH (1u) |
| AnnaBridge | 170:e95d10626187 | 57 | |
| AnnaBridge | 170:e95d10626187 | 58 | #define SPIBSC_CMNCR_CPOL_LOW (0u) |
| AnnaBridge | 170:e95d10626187 | 59 | #define SPIBSC_CMNCR_CPOL_HIGH (1u) |
| AnnaBridge | 170:e95d10626187 | 60 | |
| AnnaBridge | 170:e95d10626187 | 61 | #define SPIBSC_CMNCR_BSZ_SINGLE (0u) |
| AnnaBridge | 170:e95d10626187 | 62 | #define SPIBSC_CMNCR_BSZ_DUAL (1u) |
| AnnaBridge | 170:e95d10626187 | 63 | |
| AnnaBridge | 170:e95d10626187 | 64 | #define SPIBSC_DELAY_1SPBCLK (0u) |
| AnnaBridge | 170:e95d10626187 | 65 | #define SPIBSC_DELAY_2SPBCLK (1u) |
| AnnaBridge | 170:e95d10626187 | 66 | #define SPIBSC_DELAY_3SPBCLK (2u) |
| AnnaBridge | 170:e95d10626187 | 67 | #define SPIBSC_DELAY_4SPBCLK (3u) |
| AnnaBridge | 170:e95d10626187 | 68 | #define SPIBSC_DELAY_5SPBCLK (4u) |
| AnnaBridge | 170:e95d10626187 | 69 | #define SPIBSC_DELAY_6SPBCLK (5u) |
| AnnaBridge | 170:e95d10626187 | 70 | #define SPIBSC_DELAY_7SPBCLK (6u) |
| AnnaBridge | 170:e95d10626187 | 71 | #define SPIBSC_DELAY_8SPBCLK (7u) |
| AnnaBridge | 170:e95d10626187 | 72 | |
| AnnaBridge | 170:e95d10626187 | 73 | |
| AnnaBridge | 170:e95d10626187 | 74 | #define SPIBSC_BURST_1 (0x00u) |
| AnnaBridge | 170:e95d10626187 | 75 | #define SPIBSC_BURST_2 (0x01u) |
| AnnaBridge | 170:e95d10626187 | 76 | #define SPIBSC_BURST_3 (0x02u) |
| AnnaBridge | 170:e95d10626187 | 77 | #define SPIBSC_BURST_4 (0x03u) |
| AnnaBridge | 170:e95d10626187 | 78 | #define SPIBSC_BURST_5 (0x04u) |
| AnnaBridge | 170:e95d10626187 | 79 | #define SPIBSC_BURST_6 (0x05u) |
| AnnaBridge | 170:e95d10626187 | 80 | #define SPIBSC_BURST_7 (0x06u) |
| AnnaBridge | 170:e95d10626187 | 81 | #define SPIBSC_BURST_8 (0x07u) |
| AnnaBridge | 170:e95d10626187 | 82 | #define SPIBSC_BURST_9 (0x08u) |
| AnnaBridge | 170:e95d10626187 | 83 | #define SPIBSC_BURST_10 (0x09u) |
| AnnaBridge | 170:e95d10626187 | 84 | #define SPIBSC_BURST_11 (0x0au) |
| AnnaBridge | 170:e95d10626187 | 85 | #define SPIBSC_BURST_12 (0x0bu) |
| AnnaBridge | 170:e95d10626187 | 86 | #define SPIBSC_BURST_13 (0x0cu) |
| AnnaBridge | 170:e95d10626187 | 87 | #define SPIBSC_BURST_14 (0x0du) |
| AnnaBridge | 170:e95d10626187 | 88 | #define SPIBSC_BURST_15 (0x0eu) |
| AnnaBridge | 170:e95d10626187 | 89 | #define SPIBSC_BURST_16 (0x0fu) |
| AnnaBridge | 170:e95d10626187 | 90 | |
| AnnaBridge | 170:e95d10626187 | 91 | #define SPIBSC_BURST_DISABLE (0u) |
| AnnaBridge | 170:e95d10626187 | 92 | #define SPIBSC_BURST_ENABLE (1u) |
| AnnaBridge | 170:e95d10626187 | 93 | |
| AnnaBridge | 170:e95d10626187 | 94 | #define SPIBSC_DRCR_RCF_EXE (1u) |
| AnnaBridge | 170:e95d10626187 | 95 | |
| AnnaBridge | 170:e95d10626187 | 96 | #define SPIBSC_SSL_NEGATE (0u) |
| AnnaBridge | 170:e95d10626187 | 97 | #define SPIBSC_TRANS_END (1u) |
| AnnaBridge | 170:e95d10626187 | 98 | |
| AnnaBridge | 170:e95d10626187 | 99 | #define SPIBSC_1BIT (0u) |
| AnnaBridge | 170:e95d10626187 | 100 | #define SPIBSC_2BIT (1u) |
| AnnaBridge | 170:e95d10626187 | 101 | #define SPIBSC_4BIT (2u) |
| AnnaBridge | 170:e95d10626187 | 102 | |
| AnnaBridge | 170:e95d10626187 | 103 | #define SPIBSC_OUTPUT_DISABLE (0u) |
| AnnaBridge | 170:e95d10626187 | 104 | #define SPIBSC_OUTPUT_ENABLE (1u) |
| AnnaBridge | 170:e95d10626187 | 105 | #define SPIBSC_OUTPUT_ADDR_24 (0x07u) |
| AnnaBridge | 170:e95d10626187 | 106 | #define SPIBSC_OUTPUT_ADDR_32 (0x0fu) |
| AnnaBridge | 170:e95d10626187 | 107 | #define SPIBSC_OUTPUT_OPD_3 (0x08u) |
| AnnaBridge | 170:e95d10626187 | 108 | #define SPIBSC_OUTPUT_OPD_32 (0x0cu) |
| AnnaBridge | 170:e95d10626187 | 109 | #define SPIBSC_OUTPUT_OPD_321 (0x0eu) |
| AnnaBridge | 170:e95d10626187 | 110 | #define SPIBSC_OUTPUT_OPD_3210 (0x0fu) |
| AnnaBridge | 170:e95d10626187 | 111 | |
| AnnaBridge | 170:e95d10626187 | 112 | #define SPIBSC_OUTPUT_SPID_8 (0x08u) |
| AnnaBridge | 170:e95d10626187 | 113 | #define SPIBSC_OUTPUT_SPID_16 (0x0cu) |
| AnnaBridge | 170:e95d10626187 | 114 | #define SPIBSC_OUTPUT_SPID_32 (0x0fu) |
| AnnaBridge | 170:e95d10626187 | 115 | |
| AnnaBridge | 170:e95d10626187 | 116 | #define SPIBSC_SPISSL_NEGATE (0u) |
| AnnaBridge | 170:e95d10626187 | 117 | #define SPIBSC_SPISSL_KEEP (1u) |
| AnnaBridge | 170:e95d10626187 | 118 | |
| AnnaBridge | 170:e95d10626187 | 119 | #define SPIBSC_SPIDATA_DISABLE (0u) |
| AnnaBridge | 170:e95d10626187 | 120 | #define SPIBSC_SPIDATA_ENABLE (1u) |
| AnnaBridge | 170:e95d10626187 | 121 | |
| AnnaBridge | 170:e95d10626187 | 122 | #define SPIBSC_SPI_DISABLE (0u) |
| AnnaBridge | 170:e95d10626187 | 123 | #define SPIBSC_SPI_ENABLE (1u) |
| AnnaBridge | 170:e95d10626187 | 124 | |
| AnnaBridge | 170:e95d10626187 | 125 | |
| AnnaBridge | 170:e95d10626187 | 126 | /* Use for setting of the DME bit of "data read enable register"(DRENR) */ |
| AnnaBridge | 170:e95d10626187 | 127 | #define SPIBSC_DUMMY_CYC_DISABLE (0u) |
| AnnaBridge | 170:e95d10626187 | 128 | #define SPIBSC_DUMMY_CYC_ENABLE (1u) |
| AnnaBridge | 170:e95d10626187 | 129 | |
| AnnaBridge | 170:e95d10626187 | 130 | /* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */ |
| AnnaBridge | 170:e95d10626187 | 131 | #define SPIBSC_DUMMY_1CYC (0u) |
| AnnaBridge | 170:e95d10626187 | 132 | #define SPIBSC_DUMMY_2CYC (1u) |
| AnnaBridge | 170:e95d10626187 | 133 | #define SPIBSC_DUMMY_3CYC (2u) |
| AnnaBridge | 170:e95d10626187 | 134 | #define SPIBSC_DUMMY_4CYC (3u) |
| AnnaBridge | 170:e95d10626187 | 135 | #define SPIBSC_DUMMY_5CYC (4u) |
| AnnaBridge | 170:e95d10626187 | 136 | #define SPIBSC_DUMMY_6CYC (5u) |
| AnnaBridge | 170:e95d10626187 | 137 | #define SPIBSC_DUMMY_7CYC (6u) |
| AnnaBridge | 170:e95d10626187 | 138 | #define SPIBSC_DUMMY_8CYC (7u) |
| AnnaBridge | 170:e95d10626187 | 139 | |
| AnnaBridge | 170:e95d10626187 | 140 | /* Use for setting of "data read DDR enable register"(DRDRENR) */ |
| AnnaBridge | 170:e95d10626187 | 141 | #define SPIBSC_SDR_TRANS (0u) |
| AnnaBridge | 170:e95d10626187 | 142 | #define SPIBSC_DDR_TRANS (1u) |
| AnnaBridge | 170:e95d10626187 | 143 | |
| AnnaBridge | 170:e95d10626187 | 144 | /* Use for setting the CKDLY regsiter */ |
| AnnaBridge | 170:e95d10626187 | 145 | #define SPIBSC_CKDLY_DEFAULT (0x0000A504uL) /* Initial value */ |
| AnnaBridge | 170:e95d10626187 | 146 | #define SPIBSC_CKDLY_TUNING (0x0000A50AuL) /* Shorten the data input setup time and extend the data hold time */ |
| AnnaBridge | 170:e95d10626187 | 147 | |
| AnnaBridge | 170:e95d10626187 | 148 | /* Use for setting the SPODLY regsiter */ |
| AnnaBridge | 170:e95d10626187 | 149 | #define SPIBSC_SPODLY_DEFAULT (0xA5000000uL) /* Initial value */ |
| AnnaBridge | 170:e95d10626187 | 150 | #define SPIBSC_SPODLY_TUNING (0xA5001111uL) /* Delay the data output delay/hold/buffer-on/buffer-off time */ |
| AnnaBridge | 170:e95d10626187 | 151 | |
| AnnaBridge | 170:e95d10626187 | 152 | #endif /* _SPIBSC_H_ */ |
| AnnaBridge | 170:e95d10626187 | 153 | |
| AnnaBridge | 170:e95d10626187 | 154 | /* End of File */ |
