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mbed 2

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TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M451Series.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * @file M451Series.h
AnnaBridge 171:3a7713b1edbc 3 * @version V3.10
AnnaBridge 171:3a7713b1edbc 4 * $Revision: 179 $
AnnaBridge 171:3a7713b1edbc 5 * $Date: 15/09/04 3:45p $
AnnaBridge 171:3a7713b1edbc 6 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * @note
AnnaBridge 171:3a7713b1edbc 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 171:3a7713b1edbc 10 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 11
AnnaBridge 171:3a7713b1edbc 12
AnnaBridge 171:3a7713b1edbc 13 /**
AnnaBridge 171:3a7713b1edbc 14 \mainpage Introduction
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * This user manual describes the usage of M451 Series MCU device driver
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * <b>Disclaimer</b>
AnnaBridge 171:3a7713b1edbc 20 *
AnnaBridge 171:3a7713b1edbc 21 * The Software is furnished "AS IS", without warranty as to performance or results, and
AnnaBridge 171:3a7713b1edbc 22 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
AnnaBridge 171:3a7713b1edbc 23 * warranties, express, implied or otherwise, with regard to the Software, its use, or
AnnaBridge 171:3a7713b1edbc 24 * operation, including without limitation any and all warranties of merchantability, fitness
AnnaBridge 171:3a7713b1edbc 25 * for a particular purpose, and non-infringement of intellectual property rights.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * <b>Copyright Notice</b>
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 /**
AnnaBridge 171:3a7713b1edbc 33 * \page PG_REV Revision History
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 * <b>Revision 3.01.001</b>
AnnaBridge 171:3a7713b1edbc 36 * \li Added Nu-LB-M451, NuEdu and USB device sample code.
AnnaBridge 171:3a7713b1edbc 37 * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
AnnaBridge 171:3a7713b1edbc 38 * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
AnnaBridge 171:3a7713b1edbc 39 * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
AnnaBridge 171:3a7713b1edbc 40 * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
AnnaBridge 171:3a7713b1edbc 41 * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
AnnaBridge 171:3a7713b1edbc 42 * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
AnnaBridge 171:3a7713b1edbc 43 * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
AnnaBridge 171:3a7713b1edbc 44 * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
AnnaBridge 171:3a7713b1edbc 45 * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
AnnaBridge 171:3a7713b1edbc 46 * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
AnnaBridge 171:3a7713b1edbc 47 * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
AnnaBridge 171:3a7713b1edbc 48 * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
AnnaBridge 171:3a7713b1edbc 49 * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register.
AnnaBridge 171:3a7713b1edbc 50 * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
AnnaBridge 171:3a7713b1edbc 51 * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
AnnaBridge 171:3a7713b1edbc 52 * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
AnnaBridge 171:3a7713b1edbc 53 * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
AnnaBridge 171:3a7713b1edbc 54 * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
AnnaBridge 171:3a7713b1edbc 55 * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
AnnaBridge 171:3a7713b1edbc 56 * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
AnnaBridge 171:3a7713b1edbc 57 * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
AnnaBridge 171:3a7713b1edbc 58 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
AnnaBridge 171:3a7713b1edbc 59 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
AnnaBridge 171:3a7713b1edbc 60 * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
AnnaBridge 171:3a7713b1edbc 61 * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
AnnaBridge 171:3a7713b1edbc 62 * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
AnnaBridge 171:3a7713b1edbc 63 * \li Fixed SC_SET_STOP_BIT_LEN definition error.
AnnaBridge 171:3a7713b1edbc 64 * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
AnnaBridge 171:3a7713b1edbc 65 * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
AnnaBridge 171:3a7713b1edbc 66 * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
AnnaBridge 171:3a7713b1edbc 67 * \li Fixed SMBD_Enable constant value definition error in I2C driver.
AnnaBridge 171:3a7713b1edbc 68 * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
AnnaBridge 171:3a7713b1edbc 69 * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
AnnaBridge 171:3a7713b1edbc 70 * \li Improved compatibility of USBH driver for pen driver.
AnnaBridge 171:3a7713b1edbc 71 * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
AnnaBridge 171:3a7713b1edbc 72 * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
AnnaBridge 171:3a7713b1edbc 73 * \li Improved SC driver to support more than one SC port.
AnnaBridge 171:3a7713b1edbc 74 * \li Improved USBH driver to support composite HID devices
AnnaBridge 171:3a7713b1edbc 75 * \li Improved USBD driver to support more USB device sample code.
AnnaBridge 171:3a7713b1edbc 76 * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
AnnaBridge 171:3a7713b1edbc 77 * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
AnnaBridge 171:3a7713b1edbc 78 * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
AnnaBridge 171:3a7713b1edbc 79 * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
AnnaBridge 171:3a7713b1edbc 80 *
AnnaBridge 171:3a7713b1edbc 81 * <b>Revision 3.00.005</b>
AnnaBridge 171:3a7713b1edbc 82 * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
AnnaBridge 171:3a7713b1edbc 83 * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
AnnaBridge 171:3a7713b1edbc 84 * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
AnnaBridge 171:3a7713b1edbc 85 * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
AnnaBridge 171:3a7713b1edbc 86 * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
AnnaBridge 171:3a7713b1edbc 87 * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
AnnaBridge 171:3a7713b1edbc 88 * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
AnnaBridge 171:3a7713b1edbc 89 * \li Fixed isochronous transfer bugs of USB Host library.
AnnaBridge 171:3a7713b1edbc 90 * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
AnnaBridge 171:3a7713b1edbc 91 * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
AnnaBridge 171:3a7713b1edbc 92 * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
AnnaBridge 171:3a7713b1edbc 93 * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
AnnaBridge 171:3a7713b1edbc 94 * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
AnnaBridge 171:3a7713b1edbc 95 * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
AnnaBridge 171:3a7713b1edbc 96 * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
AnnaBridge 171:3a7713b1edbc 97 * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
AnnaBridge 171:3a7713b1edbc 98 * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
AnnaBridge 171:3a7713b1edbc 99 * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
AnnaBridge 171:3a7713b1edbc 100 * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library.
AnnaBridge 171:3a7713b1edbc 101 * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
AnnaBridge 171:3a7713b1edbc 102 *
AnnaBridge 171:3a7713b1edbc 103 * <b>Revision 3.00.004</b>
AnnaBridge 171:3a7713b1edbc 104 * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
AnnaBridge 171:3a7713b1edbc 105 * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
AnnaBridge 171:3a7713b1edbc 106 * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
AnnaBridge 171:3a7713b1edbc 107 * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
AnnaBridge 171:3a7713b1edbc 108 * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
AnnaBridge 171:3a7713b1edbc 109 * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
AnnaBridge 171:3a7713b1edbc 110 * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
AnnaBridge 171:3a7713b1edbc 111 * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
AnnaBridge 171:3a7713b1edbc 112 * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
AnnaBridge 171:3a7713b1edbc 113 * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
AnnaBridge 171:3a7713b1edbc 114 * \li Fixed UART data transfer bug of USBD_VCOM sample code.
AnnaBridge 171:3a7713b1edbc 115 * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
AnnaBridge 171:3a7713b1edbc 116 * \li Updated USBD driver to pass USB-IF MSC test.
AnnaBridge 171:3a7713b1edbc 117 * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
AnnaBridge 171:3a7713b1edbc 118 * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
AnnaBridge 171:3a7713b1edbc 119 * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
AnnaBridge 171:3a7713b1edbc 120 * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
AnnaBridge 171:3a7713b1edbc 121 * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
AnnaBridge 171:3a7713b1edbc 122 *
AnnaBridge 171:3a7713b1edbc 123 * <b>Revision 3.00.003</b>
AnnaBridge 171:3a7713b1edbc 124 * \li Added USBD_Audio_HID_NAU8822 sample code.
AnnaBridge 171:3a7713b1edbc 125 *
AnnaBridge 171:3a7713b1edbc 126 * <b>Revision 3.00.002</b>
AnnaBridge 171:3a7713b1edbc 127 * \li Fixed serial number code in device descriptor.
AnnaBridge 171:3a7713b1edbc 128 * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
AnnaBridge 171:3a7713b1edbc 129 * \li Fixed SMBus bus time-out and Clock Lo time-out API.
AnnaBridge 171:3a7713b1edbc 130 * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
AnnaBridge 171:3a7713b1edbc 131 * \li Fixed include path of CMSIS.
AnnaBridge 171:3a7713b1edbc 132 * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
AnnaBridge 171:3a7713b1edbc 133 * \li Fixed USBD_INT_WAKEUP definition.
AnnaBridge 171:3a7713b1edbc 134 * \li Modified USBD driver to support USB remote wake-up function.
AnnaBridge 171:3a7713b1edbc 135 *
AnnaBridge 171:3a7713b1edbc 136 * <b>Revision 3.00.001</b>
AnnaBridge 171:3a7713b1edbc 137 * \li Initial Release.
AnnaBridge 171:3a7713b1edbc 138 */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #ifndef __M451SERIES_H__
AnnaBridge 171:3a7713b1edbc 141 #define __M451SERIES_H__
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 144 extern "C" {
AnnaBridge 171:3a7713b1edbc 145 #endif
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 148 /* Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 149 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 150 /** @addtogroup CMSIS Device CMSIS Definitions
AnnaBridge 171:3a7713b1edbc 151 Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 152 @{
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*
AnnaBridge 171:3a7713b1edbc 156 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 157 * ---------- Interrupt Number Definition -----------------------------------
AnnaBridge 171:3a7713b1edbc 158 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 159 */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 162 {
AnnaBridge 171:3a7713b1edbc 163 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
AnnaBridge 171:3a7713b1edbc 164 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 165 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 166 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 167 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 168 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 169 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 170 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 171 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /****** M451 Specific Interrupt Numbers ********************************************************/
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
AnnaBridge 171:3a7713b1edbc 176 IRC_IRQn = 1, /*!< Internal RC Interrupt */
AnnaBridge 171:3a7713b1edbc 177 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
AnnaBridge 171:3a7713b1edbc 178 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
AnnaBridge 171:3a7713b1edbc 179 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
AnnaBridge 171:3a7713b1edbc 180 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
AnnaBridge 171:3a7713b1edbc 181 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
AnnaBridge 171:3a7713b1edbc 182 WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 183 WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 184 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 185 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 186 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 187 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 188 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
AnnaBridge 171:3a7713b1edbc 189 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 190 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
AnnaBridge 171:3a7713b1edbc 191 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
AnnaBridge 171:3a7713b1edbc 192 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
AnnaBridge 171:3a7713b1edbc 193 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
AnnaBridge 171:3a7713b1edbc 194 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
AnnaBridge 171:3a7713b1edbc 195 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
AnnaBridge 171:3a7713b1edbc 196 SPI0_IRQn = 22, /*!< SPI0 Interrupt */
AnnaBridge 171:3a7713b1edbc 197 SPI1_IRQn = 23, /*!< SPI1 Interrupt */
AnnaBridge 171:3a7713b1edbc 198 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
AnnaBridge 171:3a7713b1edbc 199 PWM0P0_IRQn = 25, /*!< PWM0P0 Interrupt */
AnnaBridge 171:3a7713b1edbc 200 PWM0P1_IRQn = 26, /*!< PWM0P1 Interrupt */
AnnaBridge 171:3a7713b1edbc 201 PWM0P2_IRQn = 27, /*!< PWM0P2 Interrupt */
AnnaBridge 171:3a7713b1edbc 202 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
AnnaBridge 171:3a7713b1edbc 203 PWM1P0_IRQn = 29, /*!< PWM1P0 Interrupt */
AnnaBridge 171:3a7713b1edbc 204 PWM1P1_IRQn = 30, /*!< PWM1P1 Interrupt */
AnnaBridge 171:3a7713b1edbc 205 PWM1P2_IRQn = 31, /*!< PWM1P2 Interrupt */
AnnaBridge 171:3a7713b1edbc 206 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 207 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 208 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 209 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 210 UART0_IRQn = 36, /*!< UART 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 211 UART1_IRQn = 37, /*!< UART 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 212 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 213 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 214 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 215 DAC_IRQn = 41, /*!< DAC Interrupt */
AnnaBridge 171:3a7713b1edbc 216 ADC00_IRQn = 42, /*!< ADC0 Source 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 217 ADC01_IRQn = 43, /*!< ADC0 Source 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 218 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 219 ADC02_IRQn = 46, /*!< ADC0 Source 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 220 ADC03_IRQn = 47, /*!< ADC0 Source 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 221 UART2_IRQn = 48, /*!< UART2 Interrupt */
AnnaBridge 171:3a7713b1edbc 222 UART3_IRQn = 49, /*!< UART3 Interrupt */
AnnaBridge 171:3a7713b1edbc 223 SPI2_IRQn = 51, /*!< SPI2 Interrupt */
AnnaBridge 171:3a7713b1edbc 224 USBD_IRQn = 53, /*!< USB device Interrupt */
AnnaBridge 171:3a7713b1edbc 225 USBH_IRQn = 54, /*!< USB host Interrupt */
AnnaBridge 171:3a7713b1edbc 226 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
AnnaBridge 171:3a7713b1edbc 227 CAN0_IRQn = 56, /*!< CAN0 Interrupt */
AnnaBridge 171:3a7713b1edbc 228 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 229 TK_IRQn = 63 /*!< Touch Key Interrupt */
AnnaBridge 171:3a7713b1edbc 230 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /*
AnnaBridge 171:3a7713b1edbc 234 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 235 * ----------- Processor and Core Peripheral Section ------------------------
AnnaBridge 171:3a7713b1edbc 236 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /* Configuration of the Cortex-M# Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 240 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
AnnaBridge 171:3a7713b1edbc 241 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 242 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 243 #define __MPU_PRESENT 1 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 244 #define __FPU_PRESENT 1 /*!< FPU present or not */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /*@}*/ /* end of group CMSIS */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 249 #include "system_M451Series.h" /* M451 System include file */
AnnaBridge 171:3a7713b1edbc 250 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 255 /* Device Specific Peripheral registers structures */
AnnaBridge 171:3a7713b1edbc 256 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 /** @addtogroup REGISTER Control Register
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 @{
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /*---------------------- Analog Comparator Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 266 /**
AnnaBridge 171:3a7713b1edbc 267 @addtogroup ACMP Analog Comparator Controller(ACMP)
AnnaBridge 171:3a7713b1edbc 268 Memory Mapped Structure for ACMP Controller
AnnaBridge 171:3a7713b1edbc 269 @{ */
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 typedef struct
AnnaBridge 171:3a7713b1edbc 273 {
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 /**
AnnaBridge 171:3a7713b1edbc 277 * @var ACMP_T::CTL
AnnaBridge 171:3a7713b1edbc 278 * Offset: 0x00 Analog Comparator 0 Control Register
AnnaBridge 171:3a7713b1edbc 279 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 280 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 281 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 282 * |[0] |ACMPEN |Comparator Enable Bit
AnnaBridge 171:3a7713b1edbc 283 * | | |0 = Comparator 0 Disabled.
AnnaBridge 171:3a7713b1edbc 284 * | | |1 = Comparator 0 Enabled.
AnnaBridge 171:3a7713b1edbc 285 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 286 * | | |0 = Comparator 0 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 287 * | | |1 = Comparator 0 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 288 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
AnnaBridge 171:3a7713b1edbc 289 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
AnnaBridge 171:3a7713b1edbc 290 * | | |0 = Comparator 0 hysteresis Disabled.
AnnaBridge 171:3a7713b1edbc 291 * | | |1 = Comparator 0 hysteresis Enabled.
AnnaBridge 171:3a7713b1edbc 292 * |[3] |ACMPOINV |Comparator Output Inverse
AnnaBridge 171:3a7713b1edbc 293 * | | |0 = Comparator 0 output inverse Disabled.
AnnaBridge 171:3a7713b1edbc 294 * | | |1 = Comparator 0 output inverse Enabled.
AnnaBridge 171:3a7713b1edbc 295 * |[5:4] |NEGSEL |Comparator Negative Input Selection
AnnaBridge 171:3a7713b1edbc 296 * | | |00 = ACMP0_N pin.
AnnaBridge 171:3a7713b1edbc 297 * | | |01 = Internal comparator reference voltage (CRV).
AnnaBridge 171:3a7713b1edbc 298 * | | |10 = Band-gap voltage.
AnnaBridge 171:3a7713b1edbc 299 * | | |11 = DAC output.
AnnaBridge 171:3a7713b1edbc 300 * |[7:6] |POSSEL |Comparator Positive Input Selection
AnnaBridge 171:3a7713b1edbc 301 * | | |00 = Input from ACMP0_P0.
AnnaBridge 171:3a7713b1edbc 302 * | | |01 = Input from ACMP0_P1.
AnnaBridge 171:3a7713b1edbc 303 * | | |10 = Input from ACMP0_P2.
AnnaBridge 171:3a7713b1edbc 304 * | | |11 = Input from ACMP0_P3.
AnnaBridge 171:3a7713b1edbc 305 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
AnnaBridge 171:3a7713b1edbc 306 * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
AnnaBridge 171:3a7713b1edbc 307 * | | |00 = Rising edge or falling edge.
AnnaBridge 171:3a7713b1edbc 308 * | | |01 = Rising edge.
AnnaBridge 171:3a7713b1edbc 309 * | | |10 = Falling edge.
AnnaBridge 171:3a7713b1edbc 310 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 311 * |[12] |OUTSEL |Comparator Output Select
AnnaBridge 171:3a7713b1edbc 312 * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
AnnaBridge 171:3a7713b1edbc 313 * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
AnnaBridge 171:3a7713b1edbc 314 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
AnnaBridge 171:3a7713b1edbc 315 * | | |000 = Filter function is Disabled.
AnnaBridge 171:3a7713b1edbc 316 * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
AnnaBridge 171:3a7713b1edbc 317 * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 318 * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 319 * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 320 * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 321 * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 322 * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 323 * |[16] |WKEN |Power Down Wake-Up Enable Bit
AnnaBridge 171:3a7713b1edbc 324 * | | |0 = Wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 325 * | | |1 = Wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 326 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 327 * Offset: 0x04 Analog Comparator 1 Control Register
AnnaBridge 171:3a7713b1edbc 328 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 329 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 330 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 331 * |[0] |ACMPEN |Comparator Enable Bit
AnnaBridge 171:3a7713b1edbc 332 * | | |0 = Comparator 1 Disabled.
AnnaBridge 171:3a7713b1edbc 333 * | | |1 = Comparator 1 Enabled.
AnnaBridge 171:3a7713b1edbc 334 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 335 * | | |0 = Comparator 1 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 336 * | | |1 = Comparator 1 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 337 * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
AnnaBridge 171:3a7713b1edbc 338 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
AnnaBridge 171:3a7713b1edbc 339 * | | |0 = Comparator 1 hysteresis Disabled.
AnnaBridge 171:3a7713b1edbc 340 * | | |1 = Comparator 1 hysteresis Enabled.
AnnaBridge 171:3a7713b1edbc 341 * |[3] |ACMPOINV |Comparator Output Inverse Control
AnnaBridge 171:3a7713b1edbc 342 * | | |0 = Comparator 1 output inverse Disabled.
AnnaBridge 171:3a7713b1edbc 343 * | | |1 = Comparator 1 output inverse Enabled.
AnnaBridge 171:3a7713b1edbc 344 * |[5:4] |NEGSEL |Comparator Negative Input Selection
AnnaBridge 171:3a7713b1edbc 345 * | | |00 = ACMP1_N pin.
AnnaBridge 171:3a7713b1edbc 346 * | | |01 = Internal comparator reference voltage (CRV).
AnnaBridge 171:3a7713b1edbc 347 * | | |10 = Band-gap voltage.
AnnaBridge 171:3a7713b1edbc 348 * | | |11 = DAC output.
AnnaBridge 171:3a7713b1edbc 349 * |[7:6] |POSSEL |Comparator Positive Input Selection
AnnaBridge 171:3a7713b1edbc 350 * | | |00 = Input from ACMP1_P0.
AnnaBridge 171:3a7713b1edbc 351 * | | |01 = Input from ACMP1_P1.
AnnaBridge 171:3a7713b1edbc 352 * | | |10 = Input from ACMP1_P2.
AnnaBridge 171:3a7713b1edbc 353 * | | |11 = Input from ACMP1_P3.
AnnaBridge 171:3a7713b1edbc 354 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
AnnaBridge 171:3a7713b1edbc 355 * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
AnnaBridge 171:3a7713b1edbc 356 * | | |00 = Rising edge or falling edge.
AnnaBridge 171:3a7713b1edbc 357 * | | |01 = Rising edge.
AnnaBridge 171:3a7713b1edbc 358 * | | |10 = Falling edge.
AnnaBridge 171:3a7713b1edbc 359 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 360 * |[12] |OUTSEL |Comparator Output Select
AnnaBridge 171:3a7713b1edbc 361 * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
AnnaBridge 171:3a7713b1edbc 362 * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
AnnaBridge 171:3a7713b1edbc 363 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
AnnaBridge 171:3a7713b1edbc 364 * | | |000 = Filter function is Disabled.
AnnaBridge 171:3a7713b1edbc 365 * | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
AnnaBridge 171:3a7713b1edbc 366 * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 367 * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 368 * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 369 * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 370 * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 371 * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
AnnaBridge 171:3a7713b1edbc 372 * |[16] |WKEN |Power Down Wakeup Enable Bit
AnnaBridge 171:3a7713b1edbc 373 * | | |0 = Wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 374 * | | |1 = Wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 375 * @var ACMP_T::STATUS
AnnaBridge 171:3a7713b1edbc 376 * Offset: 0x08 Analog Comparator Status Register
AnnaBridge 171:3a7713b1edbc 377 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 378 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 379 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 380 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 381 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
AnnaBridge 171:3a7713b1edbc 382 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
AnnaBridge 171:3a7713b1edbc 383 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 384 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 385 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
AnnaBridge 171:3a7713b1edbc 386 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
AnnaBridge 171:3a7713b1edbc 387 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 388 * |[4] |ACMPO0 |Comparator 0 Output
AnnaBridge 171:3a7713b1edbc 389 * | | |Synchronized to the PCLK to allow reading by software.
AnnaBridge 171:3a7713b1edbc 390 * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
AnnaBridge 171:3a7713b1edbc 391 * |[5] |ACMPO1 |Comparator 1 Output
AnnaBridge 171:3a7713b1edbc 392 * | | |Synchronized to the PCLK to allow reading by software.
AnnaBridge 171:3a7713b1edbc 393 * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
AnnaBridge 171:3a7713b1edbc 394 * |[8] |WKIF0 |Comparator 0 Power Down Wake-Up Interrupt Flag
AnnaBridge 171:3a7713b1edbc 395 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
AnnaBridge 171:3a7713b1edbc 396 * | | |0 = No power down wake-up occurred.
AnnaBridge 171:3a7713b1edbc 397 * | | |1 = Power down wake-up occurred.
AnnaBridge 171:3a7713b1edbc 398 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 399 * |[9] |WKIF1 |Comparator 1 Power Down Wake-Up Interrupt Flag
AnnaBridge 171:3a7713b1edbc 400 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
AnnaBridge 171:3a7713b1edbc 401 * | | |0 = No power down wake-up occurred.
AnnaBridge 171:3a7713b1edbc 402 * | | |1 = Power down wake-up occurred.
AnnaBridge 171:3a7713b1edbc 403 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 404 * @var ACMP_T::VREF
AnnaBridge 171:3a7713b1edbc 405 * Offset: 0x0C Analog Comparator Reference Voltage Control Register
AnnaBridge 171:3a7713b1edbc 406 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 407 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 408 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 409 * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
AnnaBridge 171:3a7713b1edbc 410 * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
AnnaBridge 171:3a7713b1edbc 411 * |[6] |CRVSSEL |CRV Source Voltage Selection
AnnaBridge 171:3a7713b1edbc 412 * | | |0 = VDDA is selected as CRV source voltage.
AnnaBridge 171:3a7713b1edbc 413 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t CTL[2]; /* Offset: 0x00 Analog Comparator Control Register */
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t STATUS; /* Offset: 0x08 Analog Comparator Status Register */
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t VREF; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 } ACMP_T;
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /**
AnnaBridge 171:3a7713b1edbc 425 @addtogroup ACMP_CONST ACMP Bit Field Definition
AnnaBridge 171:3a7713b1edbc 426 Constant Definitions for ACMP Controller
AnnaBridge 171:3a7713b1edbc 427 @{ */
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
AnnaBridge 171:3a7713b1edbc 430 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
AnnaBridge 171:3a7713b1edbc 433 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 #define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
AnnaBridge 171:3a7713b1edbc 436 #define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
AnnaBridge 171:3a7713b1edbc 439 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
AnnaBridge 171:3a7713b1edbc 442 #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 #define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
AnnaBridge 171:3a7713b1edbc 445 #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
AnnaBridge 171:3a7713b1edbc 448 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
AnnaBridge 171:3a7713b1edbc 451 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
AnnaBridge 171:3a7713b1edbc 454 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
AnnaBridge 171:3a7713b1edbc 457 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
AnnaBridge 171:3a7713b1edbc 460 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
AnnaBridge 171:3a7713b1edbc 463 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
AnnaBridge 171:3a7713b1edbc 466 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
AnnaBridge 171:3a7713b1edbc 469 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
AnnaBridge 171:3a7713b1edbc 472 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
AnnaBridge 171:3a7713b1edbc 475 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 #define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
AnnaBridge 171:3a7713b1edbc 478 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 #define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
AnnaBridge 171:3a7713b1edbc 481 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /**@}*/ /* ACMP_CONST */
AnnaBridge 171:3a7713b1edbc 484 /**@}*/ /* end of ACMP register group */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/
AnnaBridge 171:3a7713b1edbc 488 /**
AnnaBridge 171:3a7713b1edbc 489 @addtogroup Enhanced Analog to Digital Converter(EADC)
AnnaBridge 171:3a7713b1edbc 490 Memory Mapped Structure for EADC Controller
AnnaBridge 171:3a7713b1edbc 491 @{ */
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 typedef struct
AnnaBridge 171:3a7713b1edbc 495 {
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 /**
AnnaBridge 171:3a7713b1edbc 499 * @var EADC_T::DAT
AnnaBridge 171:3a7713b1edbc 500 * Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18
AnnaBridge 171:3a7713b1edbc 501 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 502 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 503 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 504 * |[15:0] |RESULT |A/D Conversion Result
AnnaBridge 171:3a7713b1edbc 505 * | | |This field contains 12 bits conversion result.
AnnaBridge 171:3a7713b1edbc 506 * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
AnnaBridge 171:3a7713b1edbc 507 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
AnnaBridge 171:3a7713b1edbc 508 * |[16] |OV |Overrun Flag
AnnaBridge 171:3a7713b1edbc 509 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
AnnaBridge 171:3a7713b1edbc 510 * | | |0 = Data in RESULT[11:0] is recent conversion result.
AnnaBridge 171:3a7713b1edbc 511 * | | |1 = Data in RESULT[11:0] is overwrite.
AnnaBridge 171:3a7713b1edbc 512 * | | |Note: It is cleared by hardware after EADC_DAT register is read.
AnnaBridge 171:3a7713b1edbc 513 * |[17] |VALID |Valid Flag
AnnaBridge 171:3a7713b1edbc 514 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
AnnaBridge 171:3a7713b1edbc 515 * | | |0 = Data in RESULT[11:0] bits is not valid.
AnnaBridge 171:3a7713b1edbc 516 * | | |1 = Data in RESULT[11:0] bits is valid.
AnnaBridge 171:3a7713b1edbc 517 * @var EADC_T::CURDAT
AnnaBridge 171:3a7713b1edbc 518 * Offset: 0x4C EADC PDMA Current Transfer Data Register
AnnaBridge 171:3a7713b1edbc 519 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 520 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 521 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 522 * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
AnnaBridge 171:3a7713b1edbc 523 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
AnnaBridge 171:3a7713b1edbc 524 * | | |This is a read only register.
AnnaBridge 171:3a7713b1edbc 525 * @var EADC_T::CTL
AnnaBridge 171:3a7713b1edbc 526 * Offset: 0x50 A/D Control Register
AnnaBridge 171:3a7713b1edbc 527 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 528 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 529 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 530 * |[0] |ADCEN |A/D Converter Enable Bit
AnnaBridge 171:3a7713b1edbc 531 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 532 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 533 * | | |Note: Before starting A/D conversion function, this bit should be set to 1.
AnnaBridge 171:3a7713b1edbc 534 * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
AnnaBridge 171:3a7713b1edbc 535 * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
AnnaBridge 171:3a7713b1edbc 536 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 537 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
AnnaBridge 171:3a7713b1edbc 538 * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
AnnaBridge 171:3a7713b1edbc 539 * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 540 * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
AnnaBridge 171:3a7713b1edbc 541 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
AnnaBridge 171:3a7713b1edbc 542 * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
AnnaBridge 171:3a7713b1edbc 543 * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
AnnaBridge 171:3a7713b1edbc 544 * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 545 * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
AnnaBridge 171:3a7713b1edbc 546 * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
AnnaBridge 171:3a7713b1edbc 547 * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
AnnaBridge 171:3a7713b1edbc 548 * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
AnnaBridge 171:3a7713b1edbc 549 * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 550 * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
AnnaBridge 171:3a7713b1edbc 551 * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
AnnaBridge 171:3a7713b1edbc 552 * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
AnnaBridge 171:3a7713b1edbc 553 * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
AnnaBridge 171:3a7713b1edbc 554 * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 555 * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
AnnaBridge 171:3a7713b1edbc 556 * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
AnnaBridge 171:3a7713b1edbc 557 * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
AnnaBridge 171:3a7713b1edbc 558 * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
AnnaBridge 171:3a7713b1edbc 559 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 560 * | | |0 = Single-end analog input mode.
AnnaBridge 171:3a7713b1edbc 561 * | | |1 = Differential analog input mode.
AnnaBridge 171:3a7713b1edbc 562 * |[9] |DMOF |ADC Differential Input Mode Output Format
AnnaBridge 171:3a7713b1edbc 563 * | | |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
AnnaBridge 171:3a7713b1edbc 564 * | | |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
AnnaBridge 171:3a7713b1edbc 565 * |[11] |PDMAEN |PDMA Transfer Enable Bit
AnnaBridge 171:3a7713b1edbc 566 * | | |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
AnnaBridge 171:3a7713b1edbc 567 * | | |0 = PDMA data transfer Disabled.
AnnaBridge 171:3a7713b1edbc 568 * | | |1 = PDMA data transfer Enabled.
AnnaBridge 171:3a7713b1edbc 569 * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
AnnaBridge 171:3a7713b1edbc 570 * |[18:16] |SMPTSEL |ADC Internal Sampling Time Selection
AnnaBridge 171:3a7713b1edbc 571 * | | |ADC internal sampling cycle = SMPTSEL + 1.
AnnaBridge 171:3a7713b1edbc 572 * | | |000 = 1 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 573 * | | |001 = 2 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 574 * | | |010 = 3 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 575 * | | |011 = 4 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 576 * | | |100 = 5 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 577 * | | |101 = 6 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 578 * | | |110 = 7 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 579 * | | |111 = 8 ADC clock sampling time.
AnnaBridge 171:3a7713b1edbc 580 * @var EADC_T::SWTRG
AnnaBridge 171:3a7713b1edbc 581 * Offset: 0x54 A/D Sample Module Software Start Register
AnnaBridge 171:3a7713b1edbc 582 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 583 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 584 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 585 * |[18:0] |SWTRG |A/D Sample Module
AnnaBridge 171:3a7713b1edbc 586 * | | |0~18 Software Force To Start ADC Conversion
AnnaBridge 171:3a7713b1edbc 587 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 588 * | | |1 = Cause an ADC conversion when the priority is given to sample module.
AnnaBridge 171:3a7713b1edbc 589 * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
AnnaBridge 171:3a7713b1edbc 590 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
AnnaBridge 171:3a7713b1edbc 591 * @var EADC_T::PENDSTS
AnnaBridge 171:3a7713b1edbc 592 * Offset: 0x58 A/D Start of Conversion Pending Flag Register
AnnaBridge 171:3a7713b1edbc 593 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 594 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 595 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 596 * |[18:0] |STPF |A/D Sample Module 0~18 Start Of Conversion Pending Flag
AnnaBridge 171:3a7713b1edbc 597 * | | |Read:
AnnaBridge 171:3a7713b1edbc 598 * | | |0 = There is no pending conversion for sample module.
AnnaBridge 171:3a7713b1edbc 599 * | | |1 = Sample module ADC start of conversion is pending.
AnnaBridge 171:3a7713b1edbc 600 * | | |Write:
AnnaBridge 171:3a7713b1edbc 601 * | | |1 = clear pending flag and cancel the conversion for sample module.
AnnaBridge 171:3a7713b1edbc 602 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
AnnaBridge 171:3a7713b1edbc 603 * @var EADC_T::OVSTS
AnnaBridge 171:3a7713b1edbc 604 * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
AnnaBridge 171:3a7713b1edbc 605 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 606 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 607 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 608 * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
AnnaBridge 171:3a7713b1edbc 609 * | | |0 = No sample module event overrun.
AnnaBridge 171:3a7713b1edbc 610 * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
AnnaBridge 171:3a7713b1edbc 611 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 612 * @var EADC_T::SCTL
AnnaBridge 171:3a7713b1edbc 613 * Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3
AnnaBridge 171:3a7713b1edbc 614 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 615 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 616 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 617 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
AnnaBridge 171:3a7713b1edbc 618 * | | |00H = EADC_CH0.
AnnaBridge 171:3a7713b1edbc 619 * | | |01H = EADC_CH1.
AnnaBridge 171:3a7713b1edbc 620 * | | |02H = EADC_CH2.
AnnaBridge 171:3a7713b1edbc 621 * | | |03H = EADC_CH3.
AnnaBridge 171:3a7713b1edbc 622 * | | |04H = EADC_CH4.
AnnaBridge 171:3a7713b1edbc 623 * | | |05H = EADC_CH5.
AnnaBridge 171:3a7713b1edbc 624 * | | |06H = EADC_CH6.
AnnaBridge 171:3a7713b1edbc 625 * | | |07H = EADC_CH7.
AnnaBridge 171:3a7713b1edbc 626 * | | |08H = EADC_CH8.
AnnaBridge 171:3a7713b1edbc 627 * | | |09H = EADC_CH9.
AnnaBridge 171:3a7713b1edbc 628 * | | |0AH = EADC_CH10.
AnnaBridge 171:3a7713b1edbc 629 * | | |0BH = EADC_CH11.
AnnaBridge 171:3a7713b1edbc 630 * | | |0CH = EADC_CH12.
AnnaBridge 171:3a7713b1edbc 631 * | | |0DH = EADC_CH13.
AnnaBridge 171:3a7713b1edbc 632 * | | |0EH = EADC_CH14.
AnnaBridge 171:3a7713b1edbc 633 * | | |0FH = EADC_CH15.
AnnaBridge 171:3a7713b1edbc 634 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
AnnaBridge 171:3a7713b1edbc 635 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 636 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 637 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
AnnaBridge 171:3a7713b1edbc 638 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 639 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 640 * |[7:6] |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
AnnaBridge 171:3a7713b1edbc 641 * | | |Trigger delay clock frequency:
AnnaBridge 171:3a7713b1edbc 642 * | | |00 = ADC_CLK/1.
AnnaBridge 171:3a7713b1edbc 643 * | | |01 = ADC_CLK/2.
AnnaBridge 171:3a7713b1edbc 644 * | | |10 = ADC_CLK/4.
AnnaBridge 171:3a7713b1edbc 645 * | | |11 = ADC_CLK/16.
AnnaBridge 171:3a7713b1edbc 646 * |[15:8] |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
AnnaBridge 171:3a7713b1edbc 647 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
AnnaBridge 171:3a7713b1edbc 648 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
AnnaBridge 171:3a7713b1edbc 649 * | | |0H = Disable trigger.
AnnaBridge 171:3a7713b1edbc 650 * | | |1H = External trigger from STADC pin input.
AnnaBridge 171:3a7713b1edbc 651 * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
AnnaBridge 171:3a7713b1edbc 652 * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
AnnaBridge 171:3a7713b1edbc 653 * | | |4H = Timer0 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 654 * | | |5H = Timer1 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 655 * | | |6H = Timer2 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 656 * | | |7H = Timer3 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 657 * | | |8H = PWM0TG0.
AnnaBridge 171:3a7713b1edbc 658 * | | |9H = PWM0TG1.
AnnaBridge 171:3a7713b1edbc 659 * | | |AH = PWM0TG2.
AnnaBridge 171:3a7713b1edbc 660 * | | |BH = PWM0TG3.
AnnaBridge 171:3a7713b1edbc 661 * | | |CH = PWM0TG4.
AnnaBridge 171:3a7713b1edbc 662 * | | |DH = PWM0TG5.
AnnaBridge 171:3a7713b1edbc 663 * | | |EH = PWM1TG0.
AnnaBridge 171:3a7713b1edbc 664 * | | |FH = PWM1TG1.
AnnaBridge 171:3a7713b1edbc 665 * | | |10H = PWM1TG2.
AnnaBridge 171:3a7713b1edbc 666 * | | |11H = PWM1TG3.
AnnaBridge 171:3a7713b1edbc 667 * | | |12H = PWM1TG4.
AnnaBridge 171:3a7713b1edbc 668 * | | |13H = PWM1TG5.
AnnaBridge 171:3a7713b1edbc 669 * | | |other = Reserved.
AnnaBridge 171:3a7713b1edbc 670 * |[22] |INTPOS |Interrupt Flag Position Select
AnnaBridge 171:3a7713b1edbc 671 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
AnnaBridge 171:3a7713b1edbc 672 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
AnnaBridge 171:3a7713b1edbc 673 * |[23] |DBMEN |Double Buffer Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 674 * | | |0 = Sample has one sample result register. (default).
AnnaBridge 171:3a7713b1edbc 675 * | | |1 = Sample has two sample result registers.
AnnaBridge 171:3a7713b1edbc 676 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
AnnaBridge 171:3a7713b1edbc 677 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
AnnaBridge 171:3a7713b1edbc 678 * | | |The range of start delay time is from 0~255 ADC clock.
AnnaBridge 171:3a7713b1edbc 679 * @var EADC_T::SCTL
AnnaBridge 171:3a7713b1edbc 680 * Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15
AnnaBridge 171:3a7713b1edbc 681 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 682 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 683 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 684 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
AnnaBridge 171:3a7713b1edbc 685 * | | |00H = EADC_CH0.
AnnaBridge 171:3a7713b1edbc 686 * | | |01H = EADC_CH1.
AnnaBridge 171:3a7713b1edbc 687 * | | |02H = EADC_CH2.
AnnaBridge 171:3a7713b1edbc 688 * | | |03H = EADC_CH3.
AnnaBridge 171:3a7713b1edbc 689 * | | |04H = EADC_CH4.
AnnaBridge 171:3a7713b1edbc 690 * | | |05H = EADC_CH5.
AnnaBridge 171:3a7713b1edbc 691 * | | |06H = EADC_CH6.
AnnaBridge 171:3a7713b1edbc 692 * | | |07H = EADC_CH7.
AnnaBridge 171:3a7713b1edbc 693 * | | |08H = EADC_CH8.
AnnaBridge 171:3a7713b1edbc 694 * | | |09H = EADC_CH9.
AnnaBridge 171:3a7713b1edbc 695 * | | |0AH = EADC_CH10.
AnnaBridge 171:3a7713b1edbc 696 * | | |0BH = EADC_CH11.
AnnaBridge 171:3a7713b1edbc 697 * | | |0CH = EADC_CH12.
AnnaBridge 171:3a7713b1edbc 698 * | | |0DH = EADC_CH13.
AnnaBridge 171:3a7713b1edbc 699 * | | |0EH = EADC_CH14.
AnnaBridge 171:3a7713b1edbc 700 * | | |0FH = EADC_CH15.
AnnaBridge 171:3a7713b1edbc 701 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
AnnaBridge 171:3a7713b1edbc 702 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 703 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 704 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
AnnaBridge 171:3a7713b1edbc 705 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 706 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
AnnaBridge 171:3a7713b1edbc 707 * |[7:6] |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
AnnaBridge 171:3a7713b1edbc 708 * | | |Trigger delay clock frequency:
AnnaBridge 171:3a7713b1edbc 709 * | | |00 = ADC_CLK/1.
AnnaBridge 171:3a7713b1edbc 710 * | | |01 = ADC_CLK/2.
AnnaBridge 171:3a7713b1edbc 711 * | | |10 = ADC_CLK/4.
AnnaBridge 171:3a7713b1edbc 712 * | | |11 = ADC_CLK/16.
AnnaBridge 171:3a7713b1edbc 713 * |[15:8] |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
AnnaBridge 171:3a7713b1edbc 714 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
AnnaBridge 171:3a7713b1edbc 715 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
AnnaBridge 171:3a7713b1edbc 716 * | | |0H = Disable trigger.
AnnaBridge 171:3a7713b1edbc 717 * | | |1H = External trigger from STADC pin input.
AnnaBridge 171:3a7713b1edbc 718 * | | |2H = ADC ADINT0 interrupt EOC pulse trigger.
AnnaBridge 171:3a7713b1edbc 719 * | | |3H = ADC ADINT1 interrupt EOC pulse trigger.
AnnaBridge 171:3a7713b1edbc 720 * | | |4H = Timer0 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 721 * | | |5H = Timer1 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 722 * | | |6H = Timer2 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 723 * | | |7H = Timer3 overflow pulse trigger.
AnnaBridge 171:3a7713b1edbc 724 * | | |8H = PWM0TG0.
AnnaBridge 171:3a7713b1edbc 725 * | | |9H = PWM0TG1.
AnnaBridge 171:3a7713b1edbc 726 * | | |AH = PWM0TG2.
AnnaBridge 171:3a7713b1edbc 727 * | | |BH = PWM0TG3.
AnnaBridge 171:3a7713b1edbc 728 * | | |CH = PWM0TG4.
AnnaBridge 171:3a7713b1edbc 729 * | | |DH = PWM0TG5.
AnnaBridge 171:3a7713b1edbc 730 * | | |EH = PWM1TG0.
AnnaBridge 171:3a7713b1edbc 731 * | | |FH = PWM1TG1.
AnnaBridge 171:3a7713b1edbc 732 * | | |10H = PWM1TG2.
AnnaBridge 171:3a7713b1edbc 733 * | | |11H = PWM1TG3.
AnnaBridge 171:3a7713b1edbc 734 * | | |12H = PWM1TG4.
AnnaBridge 171:3a7713b1edbc 735 * | | |13H = PWM1TG5.
AnnaBridge 171:3a7713b1edbc 736 * | | |other = Reserved.
AnnaBridge 171:3a7713b1edbc 737 * |[22] |INTPOS |Interrupt Flag Position Select
AnnaBridge 171:3a7713b1edbc 738 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
AnnaBridge 171:3a7713b1edbc 739 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
AnnaBridge 171:3a7713b1edbc 740 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
AnnaBridge 171:3a7713b1edbc 741 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
AnnaBridge 171:3a7713b1edbc 742 * | | |The range of start delay time is from 0~255 ADC clock.
AnnaBridge 171:3a7713b1edbc 743 * @var EADC_T::SCTL
AnnaBridge 171:3a7713b1edbc 744 * Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18
AnnaBridge 171:3a7713b1edbc 745 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 746 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 747 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 748 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
AnnaBridge 171:3a7713b1edbc 749 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
AnnaBridge 171:3a7713b1edbc 750 * | | |The range of start delay time is from 0~255 ADC clock.
AnnaBridge 171:3a7713b1edbc 751 * @var EADC_T::INTSRC
AnnaBridge 171:3a7713b1edbc 752 * Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3
AnnaBridge 171:3a7713b1edbc 753 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 754 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 755 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 756 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 757 * | | |0 = Sample Module 0 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 758 * | | |1 = Sample Module 0 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 759 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 760 * | | |0 = Sample Module 1 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 761 * | | |1 = Sample Module 1 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 762 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 763 * | | |0 = Sample Module 2 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 764 * | | |1 = Sample Module 2 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 765 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 766 * | | |0 = Sample Module 3 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 767 * | | |1 = Sample Module 3 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 768 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 769 * | | |0 = Sample Module 4 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 770 * | | |1 = Sample Module 4 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 771 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 772 * | | |0 = Sample Module 5 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 773 * | | |1 = Sample Module 5 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 774 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 775 * | | |0 = Sample Module 6 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 776 * | | |1 = Sample Module 6 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 777 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 778 * | | |0 = Sample Module 7 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 779 * | | |1 = Sample Module 7 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 780 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 781 * | | |0 = Sample Module 8 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 782 * | | |1 = Sample Module 8 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 783 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 784 * | | |0 = Sample Module 9 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 785 * | | |1 = Sample Module 9 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 786 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 787 * | | |0 = Sample Module 10 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 788 * | | |1 = Sample Module 10 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 789 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 790 * | | |0 = Sample Module 11 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 791 * | | |1 = Sample Module 11 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 792 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 793 * | | |0 = Sample Module 12 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 794 * | | |1 = Sample Module 12 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 795 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 796 * | | |0 = Sample Module 13 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 797 * | | |1 = Sample Module 13 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 798 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 799 * | | |0 = Sample Module 14 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 800 * | | |1 = Sample Module 14 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 801 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 802 * | | |0 = Sample Module 15 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 803 * | | |1 = Sample Module 15 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 804 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 805 * | | |0 = Sample Module 16 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 806 * | | |1 = Sample Module 16 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 807 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 808 * | | |0 = Sample Module 17 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 809 * | | |1 = Sample Module 17 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 810 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 811 * | | |0 = Sample Module 18 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 812 * | | |1 = Sample Module 18 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 813 * @var EADC_T::CMP
AnnaBridge 171:3a7713b1edbc 814 * Offset: 0xEC A/D Result Compare Register n, n=0~3
AnnaBridge 171:3a7713b1edbc 815 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 816 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 817 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 818 * |[0] |ADCMPEN |A/D Result Compare Enable Bit
AnnaBridge 171:3a7713b1edbc 819 * | | |0 = Compare Disabled.
AnnaBridge 171:3a7713b1edbc 820 * | | |1 = Compare Enabled.
AnnaBridge 171:3a7713b1edbc 821 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
AnnaBridge 171:3a7713b1edbc 822 * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 823 * | | |0 = Compare function interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 824 * | | |1 = Compare function interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 825 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
AnnaBridge 171:3a7713b1edbc 826 * |[2] |CMPCOND |Compare Condition
AnnaBridge 171:3a7713b1edbc 827 * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
AnnaBridge 171:3a7713b1edbc 828 * | | |[27:16]), the internal match counter will increase one.
AnnaBridge 171:3a7713b1edbc 829 * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
AnnaBridge 171:3a7713b1edbc 830 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
AnnaBridge 171:3a7713b1edbc 831 * |[7:3] |CMPSPL |Compare Sample Module Selection
AnnaBridge 171:3a7713b1edbc 832 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 833 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 834 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 835 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 836 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 837 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 838 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 839 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 840 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 841 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 842 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 843 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 844 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 845 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 846 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 847 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 848 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 849 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 850 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
AnnaBridge 171:3a7713b1edbc 851 * |[11:8] |CMPMCNT |Compare Match Count
AnnaBridge 171:3a7713b1edbc 852 * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
AnnaBridge 171:3a7713b1edbc 853 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
AnnaBridge 171:3a7713b1edbc 854 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
AnnaBridge 171:3a7713b1edbc 855 * |[15] |CMPWEN |Compare Window Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 856 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
AnnaBridge 171:3a7713b1edbc 857 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
AnnaBridge 171:3a7713b1edbc 858 * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
AnnaBridge 171:3a7713b1edbc 859 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
AnnaBridge 171:3a7713b1edbc 860 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
AnnaBridge 171:3a7713b1edbc 861 * |[27:16] |CMPDAT |Comparison Data
AnnaBridge 171:3a7713b1edbc 862 * | | |The 12 bits data is used to compare with conversion result of specified sample module.
AnnaBridge 171:3a7713b1edbc 863 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
AnnaBridge 171:3a7713b1edbc 864 * @var EADC_T::STATUS0
AnnaBridge 171:3a7713b1edbc 865 * Offset: 0xF0 A/D Status Register 0
AnnaBridge 171:3a7713b1edbc 866 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 867 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 868 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 869 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
AnnaBridge 171:3a7713b1edbc 870 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
AnnaBridge 171:3a7713b1edbc 871 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
AnnaBridge 171:3a7713b1edbc 872 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
AnnaBridge 171:3a7713b1edbc 873 * @var EADC_T::STATUS1
AnnaBridge 171:3a7713b1edbc 874 * Offset: 0xF4 A/D Status Register 1
AnnaBridge 171:3a7713b1edbc 875 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 876 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 877 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 878 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
AnnaBridge 171:3a7713b1edbc 879 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
AnnaBridge 171:3a7713b1edbc 880 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
AnnaBridge 171:3a7713b1edbc 881 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
AnnaBridge 171:3a7713b1edbc 882 * @var EADC_T::STATUS2
AnnaBridge 171:3a7713b1edbc 883 * Offset: 0xF8 A/D Status Register 2
AnnaBridge 171:3a7713b1edbc 884 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 885 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 886 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 887 * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 888 * | | |0 = No ADINT0 interrupt pulse received.
AnnaBridge 171:3a7713b1edbc 889 * | | |1 = ADINT0 interrupt pulse has been received.
AnnaBridge 171:3a7713b1edbc 890 * | | |Note1: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 891 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
AnnaBridge 171:3a7713b1edbc 892 * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 893 * | | |0 = No ADINT1 interrupt pulse received.
AnnaBridge 171:3a7713b1edbc 894 * | | |1 = ADINT1 interrupt pulse has been received.
AnnaBridge 171:3a7713b1edbc 895 * | | |Note1: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 896 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
AnnaBridge 171:3a7713b1edbc 897 * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 898 * | | |0 = No ADINT2 interrupt pulse received.
AnnaBridge 171:3a7713b1edbc 899 * | | |1 = ADINT2 interrupt pulse has been received.
AnnaBridge 171:3a7713b1edbc 900 * | | |Note1: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 901 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
AnnaBridge 171:3a7713b1edbc 902 * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 903 * | | |0 = No ADINT3 interrupt pulse received.
AnnaBridge 171:3a7713b1edbc 904 * | | |1 = ADINT3 interrupt pulse has been received.
AnnaBridge 171:3a7713b1edbc 905 * | | |Note1: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 906 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
AnnaBridge 171:3a7713b1edbc 907 * |[4] |ADCMPF0 |ADC Compare 0 Flag
AnnaBridge 171:3a7713b1edbc 908 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 909 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
AnnaBridge 171:3a7713b1edbc 910 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
AnnaBridge 171:3a7713b1edbc 911 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 912 * |[5] |ADCMPF1 |ADC Compare 1 Flag
AnnaBridge 171:3a7713b1edbc 913 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 914 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
AnnaBridge 171:3a7713b1edbc 915 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
AnnaBridge 171:3a7713b1edbc 916 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 917 * |[6] |ADCMPF2 |ADC Compare 2 Flag
AnnaBridge 171:3a7713b1edbc 918 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 919 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
AnnaBridge 171:3a7713b1edbc 920 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
AnnaBridge 171:3a7713b1edbc 921 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 922 * |[7] |ADCMPF3 |ADC Compare 3 Flag
AnnaBridge 171:3a7713b1edbc 923 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 924 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
AnnaBridge 171:3a7713b1edbc 925 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
AnnaBridge 171:3a7713b1edbc 926 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 927 * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
AnnaBridge 171:3a7713b1edbc 928 * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
AnnaBridge 171:3a7713b1edbc 929 * | | |1 = ADINT0 interrupt flag is overwritten to 1.
AnnaBridge 171:3a7713b1edbc 930 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 931 * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
AnnaBridge 171:3a7713b1edbc 932 * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
AnnaBridge 171:3a7713b1edbc 933 * | | |1 = ADINT1 interrupt flag is overwritten to 1.
AnnaBridge 171:3a7713b1edbc 934 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 935 * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
AnnaBridge 171:3a7713b1edbc 936 * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
AnnaBridge 171:3a7713b1edbc 937 * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
AnnaBridge 171:3a7713b1edbc 938 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 939 * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
AnnaBridge 171:3a7713b1edbc 940 * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
AnnaBridge 171:3a7713b1edbc 941 * | | |1 = ADINT3 interrupt flag is overwritten to 1.
AnnaBridge 171:3a7713b1edbc 942 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 943 * |[12] |ADCMPO0 |ADC Compare 0 Output Status
AnnaBridge 171:3a7713b1edbc 944 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
AnnaBridge 171:3a7713b1edbc 945 * | | |User can use it to monitor the external analog input pin voltage status.
AnnaBridge 171:3a7713b1edbc 946 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
AnnaBridge 171:3a7713b1edbc 947 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
AnnaBridge 171:3a7713b1edbc 948 * | | |setting.
AnnaBridge 171:3a7713b1edbc 949 * |[13] |ADCMPO1 |ADC Compare 1 Output Status
AnnaBridge 171:3a7713b1edbc 950 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
AnnaBridge 171:3a7713b1edbc 951 * | | |User can use it to monitor the external analog input pin voltage status.
AnnaBridge 171:3a7713b1edbc 952 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
AnnaBridge 171:3a7713b1edbc 953 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
AnnaBridge 171:3a7713b1edbc 954 * | | |setting.
AnnaBridge 171:3a7713b1edbc 955 * |[14] |ADCMPO2 |ADC Compare 2 Output Status
AnnaBridge 171:3a7713b1edbc 956 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
AnnaBridge 171:3a7713b1edbc 957 * | | |User can use it to monitor the external analog input pin voltage status.
AnnaBridge 171:3a7713b1edbc 958 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
AnnaBridge 171:3a7713b1edbc 959 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
AnnaBridge 171:3a7713b1edbc 960 * | | |setting.
AnnaBridge 171:3a7713b1edbc 961 * |[15] |ADCMPO3 |ADC Compare 3 Output Status
AnnaBridge 171:3a7713b1edbc 962 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
AnnaBridge 171:3a7713b1edbc 963 * | | |User can use it to monitor the external analog input pin voltage status.
AnnaBridge 171:3a7713b1edbc 964 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
AnnaBridge 171:3a7713b1edbc 965 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
AnnaBridge 171:3a7713b1edbc 966 * | | |setting.
AnnaBridge 171:3a7713b1edbc 967 * |[20:16] |CHANNEL |Current Conversion Channel
AnnaBridge 171:3a7713b1edbc 968 * | | |This filed reflects ADC current conversion channel when BUSY=1.
AnnaBridge 171:3a7713b1edbc 969 * | | |It is read only.
AnnaBridge 171:3a7713b1edbc 970 * | | |00H = EADC_CH0.
AnnaBridge 171:3a7713b1edbc 971 * | | |01H = EADC_CH1.
AnnaBridge 171:3a7713b1edbc 972 * | | |02H = EADC_CH2.
AnnaBridge 171:3a7713b1edbc 973 * | | |03H = EADC_CH3.
AnnaBridge 171:3a7713b1edbc 974 * | | |04H = EADC_CH4.
AnnaBridge 171:3a7713b1edbc 975 * | | |05H = EADC_CH5.
AnnaBridge 171:3a7713b1edbc 976 * | | |06H = EADC_CH6.
AnnaBridge 171:3a7713b1edbc 977 * | | |07H = EADC_CH7.
AnnaBridge 171:3a7713b1edbc 978 * | | |08H = EADC_CH8.
AnnaBridge 171:3a7713b1edbc 979 * | | |09H = EADC_CH9.
AnnaBridge 171:3a7713b1edbc 980 * | | |0AH = EADC_CH10.
AnnaBridge 171:3a7713b1edbc 981 * | | |0BH = EADC_CH11.
AnnaBridge 171:3a7713b1edbc 982 * | | |0CH = EADC_CH12.
AnnaBridge 171:3a7713b1edbc 983 * | | |0DH = EADC_CH13.
AnnaBridge 171:3a7713b1edbc 984 * | | |0EH = EADC_CH14.
AnnaBridge 171:3a7713b1edbc 985 * | | |0FH = EADC_CH15.
AnnaBridge 171:3a7713b1edbc 986 * | | |10H = VBG.
AnnaBridge 171:3a7713b1edbc 987 * | | |11H = VTEMP.
AnnaBridge 171:3a7713b1edbc 988 * | | |12H = VBAT.
AnnaBridge 171:3a7713b1edbc 989 * |[23] |BUSY |Busy/Idle
AnnaBridge 171:3a7713b1edbc 990 * | | |0 = EADC is in idle state.
AnnaBridge 171:3a7713b1edbc 991 * | | |1 = EADC is busy at conversion.
AnnaBridge 171:3a7713b1edbc 992 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 993 * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
AnnaBridge 171:3a7713b1edbc 994 * | | |n=0~3.
AnnaBridge 171:3a7713b1edbc 995 * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
AnnaBridge 171:3a7713b1edbc 996 * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
AnnaBridge 171:3a7713b1edbc 997 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
AnnaBridge 171:3a7713b1edbc 998 * |[25] |STOVF |For All A/D Sample Module Start Of Conversion Overrun Flags Check
AnnaBridge 171:3a7713b1edbc 999 * | | |n=0~18.
AnnaBridge 171:3a7713b1edbc 1000 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1001 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1002 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
AnnaBridge 171:3a7713b1edbc 1003 * |[26] |AVALID |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
AnnaBridge 171:3a7713b1edbc 1004 * | | |n=0~18.
AnnaBridge 171:3a7713b1edbc 1005 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1006 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1007 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
AnnaBridge 171:3a7713b1edbc 1008 * |[27] |AOV |For All Sample Module A/D Result Data Register Overrun Flags Check
AnnaBridge 171:3a7713b1edbc 1009 * | | |n=0~18.
AnnaBridge 171:3a7713b1edbc 1010 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1011 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
AnnaBridge 171:3a7713b1edbc 1012 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
AnnaBridge 171:3a7713b1edbc 1013 * @var EADC_T::STATUS3
AnnaBridge 171:3a7713b1edbc 1014 * Offset: 0xFC A/D Status Register 3
AnnaBridge 171:3a7713b1edbc 1015 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1016 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1017 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1018 * |[4:0] |CURSPL |ADC Current Sample Module
AnnaBridge 171:3a7713b1edbc 1019 * | | |This register show the current ADC is controlled by which sample module control logic modules.
AnnaBridge 171:3a7713b1edbc 1020 * | | |If the ADC is Idle, this bit filed will set to 0x1F.
AnnaBridge 171:3a7713b1edbc 1021 * | | |This is a read only register.
AnnaBridge 171:3a7713b1edbc 1022 * @var EADC_T::DDAT
AnnaBridge 171:3a7713b1edbc 1023 * Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3
AnnaBridge 171:3a7713b1edbc 1024 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1025 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1026 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1027 * |[15:0] |RESULT |A/D Conversion Results
AnnaBridge 171:3a7713b1edbc 1028 * | | |This field contains 12 bits conversion results.
AnnaBridge 171:3a7713b1edbc 1029 * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
AnnaBridge 171:3a7713b1edbc 1030 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
AnnaBridge 171:3a7713b1edbc 1031 * |[16] |OV |Overrun Flag
AnnaBridge 171:3a7713b1edbc 1032 * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
AnnaBridge 171:3a7713b1edbc 1033 * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
AnnaBridge 171:3a7713b1edbc 1034 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
AnnaBridge 171:3a7713b1edbc 1035 * | | |It is cleared by hardware after EADC_DDAT register is read.
AnnaBridge 171:3a7713b1edbc 1036 * |[17] |VALID |Valid Flag
AnnaBridge 171:3a7713b1edbc 1037 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
AnnaBridge 171:3a7713b1edbc 1038 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
AnnaBridge 171:3a7713b1edbc 1039 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
AnnaBridge 171:3a7713b1edbc 1040 * | | |(n=0~3).
AnnaBridge 171:3a7713b1edbc 1041 */
AnnaBridge 171:3a7713b1edbc 1042
AnnaBridge 171:3a7713b1edbc 1043 __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
AnnaBridge 171:3a7713b1edbc 1044 __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
AnnaBridge 171:3a7713b1edbc 1045 __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
AnnaBridge 171:3a7713b1edbc 1046 __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
AnnaBridge 171:3a7713b1edbc 1047 __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
AnnaBridge 171:3a7713b1edbc 1048 __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
AnnaBridge 171:3a7713b1edbc 1049 __I uint32_t RESERVE0[8];
AnnaBridge 171:3a7713b1edbc 1050 __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
AnnaBridge 171:3a7713b1edbc 1051 __I uint32_t RESERVE1[1];
AnnaBridge 171:3a7713b1edbc 1052 __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
AnnaBridge 171:3a7713b1edbc 1053 __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
AnnaBridge 171:3a7713b1edbc 1054 __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
AnnaBridge 171:3a7713b1edbc 1055 __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
AnnaBridge 171:3a7713b1edbc 1056 __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
AnnaBridge 171:3a7713b1edbc 1057 __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
AnnaBridge 171:3a7713b1edbc 1058 __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 } EADC_T;
AnnaBridge 171:3a7713b1edbc 1061
AnnaBridge 171:3a7713b1edbc 1062
AnnaBridge 171:3a7713b1edbc 1063
AnnaBridge 171:3a7713b1edbc 1064 /**
AnnaBridge 171:3a7713b1edbc 1065 @addtogroup EADC_CONST EADC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 1066 Constant Definitions for EADC Controller
AnnaBridge 171:3a7713b1edbc 1067 @{ */
AnnaBridge 171:3a7713b1edbc 1068 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
AnnaBridge 171:3a7713b1edbc 1069 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
AnnaBridge 171:3a7713b1edbc 1072 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
AnnaBridge 171:3a7713b1edbc 1075 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
AnnaBridge 171:3a7713b1edbc 1076
AnnaBridge 171:3a7713b1edbc 1077 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
AnnaBridge 171:3a7713b1edbc 1078 #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
AnnaBridge 171:3a7713b1edbc 1079
AnnaBridge 171:3a7713b1edbc 1080 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
AnnaBridge 171:3a7713b1edbc 1081 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 #define EADC_CTL_ADRST_Pos (1) /*!< EADC_T::CTL: ADRST Position */
AnnaBridge 171:3a7713b1edbc 1084 #define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) /*!< EADC_T::CTL: ADRST Mask */
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
AnnaBridge 171:3a7713b1edbc 1087 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 1088
AnnaBridge 171:3a7713b1edbc 1089 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
AnnaBridge 171:3a7713b1edbc 1090 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 1091
AnnaBridge 171:3a7713b1edbc 1092 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
AnnaBridge 171:3a7713b1edbc 1093 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 1094
AnnaBridge 171:3a7713b1edbc 1095 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
AnnaBridge 171:3a7713b1edbc 1096 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 1097
AnnaBridge 171:3a7713b1edbc 1098 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
AnnaBridge 171:3a7713b1edbc 1099 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
AnnaBridge 171:3a7713b1edbc 1100
AnnaBridge 171:3a7713b1edbc 1101 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
AnnaBridge 171:3a7713b1edbc 1102 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
AnnaBridge 171:3a7713b1edbc 1103
AnnaBridge 171:3a7713b1edbc 1104 #define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
AnnaBridge 171:3a7713b1edbc 1105 #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107 #define EADC_CTL_SMPTSEL_Pos (16) /*!< EADC_T::CTL: SMPTSEL Position */
AnnaBridge 171:3a7713b1edbc 1108 #define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) /*!< EADC_T::CTL: SMPTSEL Mask */
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
AnnaBridge 171:3a7713b1edbc 1111 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
AnnaBridge 171:3a7713b1edbc 1114 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
AnnaBridge 171:3a7713b1edbc 1115
AnnaBridge 171:3a7713b1edbc 1116 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
AnnaBridge 171:3a7713b1edbc 1117 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
AnnaBridge 171:3a7713b1edbc 1118
AnnaBridge 171:3a7713b1edbc 1119 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
AnnaBridge 171:3a7713b1edbc 1120 #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122 #define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
AnnaBridge 171:3a7713b1edbc 1123 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
AnnaBridge 171:3a7713b1edbc 1124
AnnaBridge 171:3a7713b1edbc 1125 #define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
AnnaBridge 171:3a7713b1edbc 1126 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
AnnaBridge 171:3a7713b1edbc 1129 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
AnnaBridge 171:3a7713b1edbc 1130
AnnaBridge 171:3a7713b1edbc 1131 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
AnnaBridge 171:3a7713b1edbc 1132 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
AnnaBridge 171:3a7713b1edbc 1133
AnnaBridge 171:3a7713b1edbc 1134 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
AnnaBridge 171:3a7713b1edbc 1135 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
AnnaBridge 171:3a7713b1edbc 1136
AnnaBridge 171:3a7713b1edbc 1137 #define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
AnnaBridge 171:3a7713b1edbc 1138 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
AnnaBridge 171:3a7713b1edbc 1139
AnnaBridge 171:3a7713b1edbc 1140 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
AnnaBridge 171:3a7713b1edbc 1141 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
AnnaBridge 171:3a7713b1edbc 1142
AnnaBridge 171:3a7713b1edbc 1143 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
AnnaBridge 171:3a7713b1edbc 1144 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
AnnaBridge 171:3a7713b1edbc 1145
AnnaBridge 171:3a7713b1edbc 1146 #define EADC_INTSRC_SPLIE_Pos (0) /*!< EADC_T::INTSRC: SPLIE Position */
AnnaBridge 171:3a7713b1edbc 1147 #define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) /*!< EADC_T::INTSRC: SPLIE Mask */
AnnaBridge 171:3a7713b1edbc 1148
AnnaBridge 171:3a7713b1edbc 1149 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
AnnaBridge 171:3a7713b1edbc 1150 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
AnnaBridge 171:3a7713b1edbc 1151
AnnaBridge 171:3a7713b1edbc 1152 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
AnnaBridge 171:3a7713b1edbc 1153 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
AnnaBridge 171:3a7713b1edbc 1154
AnnaBridge 171:3a7713b1edbc 1155 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
AnnaBridge 171:3a7713b1edbc 1156 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
AnnaBridge 171:3a7713b1edbc 1157
AnnaBridge 171:3a7713b1edbc 1158 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
AnnaBridge 171:3a7713b1edbc 1159 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
AnnaBridge 171:3a7713b1edbc 1162 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
AnnaBridge 171:3a7713b1edbc 1163
AnnaBridge 171:3a7713b1edbc 1164 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
AnnaBridge 171:3a7713b1edbc 1165 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
AnnaBridge 171:3a7713b1edbc 1166
AnnaBridge 171:3a7713b1edbc 1167 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
AnnaBridge 171:3a7713b1edbc 1168 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
AnnaBridge 171:3a7713b1edbc 1169
AnnaBridge 171:3a7713b1edbc 1170 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
AnnaBridge 171:3a7713b1edbc 1171 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
AnnaBridge 171:3a7713b1edbc 1172
AnnaBridge 171:3a7713b1edbc 1173 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
AnnaBridge 171:3a7713b1edbc 1174 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
AnnaBridge 171:3a7713b1edbc 1175
AnnaBridge 171:3a7713b1edbc 1176 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
AnnaBridge 171:3a7713b1edbc 1177 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
AnnaBridge 171:3a7713b1edbc 1180 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
AnnaBridge 171:3a7713b1edbc 1181
AnnaBridge 171:3a7713b1edbc 1182 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
AnnaBridge 171:3a7713b1edbc 1183 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
AnnaBridge 171:3a7713b1edbc 1184
AnnaBridge 171:3a7713b1edbc 1185 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
AnnaBridge 171:3a7713b1edbc 1186 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
AnnaBridge 171:3a7713b1edbc 1187
AnnaBridge 171:3a7713b1edbc 1188 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
AnnaBridge 171:3a7713b1edbc 1189 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
AnnaBridge 171:3a7713b1edbc 1190
AnnaBridge 171:3a7713b1edbc 1191 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
AnnaBridge 171:3a7713b1edbc 1192 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
AnnaBridge 171:3a7713b1edbc 1193
AnnaBridge 171:3a7713b1edbc 1194 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
AnnaBridge 171:3a7713b1edbc 1195 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
AnnaBridge 171:3a7713b1edbc 1198 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
AnnaBridge 171:3a7713b1edbc 1201 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
AnnaBridge 171:3a7713b1edbc 1202
AnnaBridge 171:3a7713b1edbc 1203 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
AnnaBridge 171:3a7713b1edbc 1204 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
AnnaBridge 171:3a7713b1edbc 1205
AnnaBridge 171:3a7713b1edbc 1206 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
AnnaBridge 171:3a7713b1edbc 1207 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
AnnaBridge 171:3a7713b1edbc 1208
AnnaBridge 171:3a7713b1edbc 1209 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
AnnaBridge 171:3a7713b1edbc 1210 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
AnnaBridge 171:3a7713b1edbc 1211
AnnaBridge 171:3a7713b1edbc 1212 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
AnnaBridge 171:3a7713b1edbc 1213 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
AnnaBridge 171:3a7713b1edbc 1216 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
AnnaBridge 171:3a7713b1edbc 1217
AnnaBridge 171:3a7713b1edbc 1218 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
AnnaBridge 171:3a7713b1edbc 1219 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
AnnaBridge 171:3a7713b1edbc 1220
AnnaBridge 171:3a7713b1edbc 1221 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
AnnaBridge 171:3a7713b1edbc 1222 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
AnnaBridge 171:3a7713b1edbc 1223
AnnaBridge 171:3a7713b1edbc 1224 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
AnnaBridge 171:3a7713b1edbc 1225 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
AnnaBridge 171:3a7713b1edbc 1226
AnnaBridge 171:3a7713b1edbc 1227 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
AnnaBridge 171:3a7713b1edbc 1228 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
AnnaBridge 171:3a7713b1edbc 1231 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
AnnaBridge 171:3a7713b1edbc 1232
AnnaBridge 171:3a7713b1edbc 1233 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
AnnaBridge 171:3a7713b1edbc 1234 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 1235
AnnaBridge 171:3a7713b1edbc 1236 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
AnnaBridge 171:3a7713b1edbc 1237 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
AnnaBridge 171:3a7713b1edbc 1238
AnnaBridge 171:3a7713b1edbc 1239 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
AnnaBridge 171:3a7713b1edbc 1240 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
AnnaBridge 171:3a7713b1edbc 1241
AnnaBridge 171:3a7713b1edbc 1242 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
AnnaBridge 171:3a7713b1edbc 1243 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
AnnaBridge 171:3a7713b1edbc 1244
AnnaBridge 171:3a7713b1edbc 1245 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
AnnaBridge 171:3a7713b1edbc 1246 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
AnnaBridge 171:3a7713b1edbc 1247
AnnaBridge 171:3a7713b1edbc 1248 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
AnnaBridge 171:3a7713b1edbc 1249 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251 #define EADC_DDAT_RESULT_Pos (0) /*!< EADC_T::DDAT: RESULT Position */
AnnaBridge 171:3a7713b1edbc 1252 #define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) /*!< EADC_T::DDAT: RESULT Mask */
AnnaBridge 171:3a7713b1edbc 1253
AnnaBridge 171:3a7713b1edbc 1254 #define EADC_DDAT_OV_Pos (16) /*!< EADC_T::DDAT: OV Position */
AnnaBridge 171:3a7713b1edbc 1255 #define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) /*!< EADC_T::DDAT: OV Mask */
AnnaBridge 171:3a7713b1edbc 1256
AnnaBridge 171:3a7713b1edbc 1257 #define EADC_DDAT_VALID_Pos (17) /*!< EADC_T::DDAT: VALID Position */
AnnaBridge 171:3a7713b1edbc 1258 #define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /*!< EADC_T::DDAT: VALID Mask */
AnnaBridge 171:3a7713b1edbc 1259
AnnaBridge 171:3a7713b1edbc 1260
AnnaBridge 171:3a7713b1edbc 1261 /**@}*/ /* EADC_CONST */
AnnaBridge 171:3a7713b1edbc 1262 /**@}*/ /* end of EADC register group */
AnnaBridge 171:3a7713b1edbc 1263
AnnaBridge 171:3a7713b1edbc 1264
AnnaBridge 171:3a7713b1edbc 1265 /*---------------------- Controller Area Network Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 1266 /**
AnnaBridge 171:3a7713b1edbc 1267 @addtogroup CAN Controller Area Network Controller(CAN)
AnnaBridge 171:3a7713b1edbc 1268 Memory Mapped Structure for CAN Controller
AnnaBridge 171:3a7713b1edbc 1269 @{ */
AnnaBridge 171:3a7713b1edbc 1270
AnnaBridge 171:3a7713b1edbc 1271
AnnaBridge 171:3a7713b1edbc 1272 typedef struct
AnnaBridge 171:3a7713b1edbc 1273 {
AnnaBridge 171:3a7713b1edbc 1274
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /**
AnnaBridge 171:3a7713b1edbc 1278 * @var CAN_IF_T::CREQ
AnnaBridge 171:3a7713b1edbc 1279 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
AnnaBridge 171:3a7713b1edbc 1280 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1281 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1282 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1283 * |[5:0] |MessageNumber|Message Number
AnnaBridge 171:3a7713b1edbc 1284 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
AnnaBridge 171:3a7713b1edbc 1285 * | | |RAM is selected for data transfer.
AnnaBridge 171:3a7713b1edbc 1286 * | | |0x00: Not a valid Message Number, interpreted as 0x20.
AnnaBridge 171:3a7713b1edbc 1287 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
AnnaBridge 171:3a7713b1edbc 1288 * |[15] |Busy |Busy Flag
AnnaBridge 171:3a7713b1edbc 1289 * | | |0 = Read/write action has finished.
AnnaBridge 171:3a7713b1edbc 1290 * | | |1 = Writing to the IFn Command Request Register is in progress.
AnnaBridge 171:3a7713b1edbc 1291 * | | |This bit can only be read by the software.
AnnaBridge 171:3a7713b1edbc 1292 * @var CAN_IF_T::CMASK
AnnaBridge 171:3a7713b1edbc 1293 * Offset: 0x24, 0x84 IFn Command Mask Register
AnnaBridge 171:3a7713b1edbc 1294 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1295 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1296 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1297 * |[0] |DAT_B |Access Data Bytes [7:4]
AnnaBridge 171:3a7713b1edbc 1298 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1299 * | | |0 = Data Bytes [7:4] unchanged.
AnnaBridge 171:3a7713b1edbc 1300 * | | |1 = Transfer Data Bytes [7:4] to Message Object.
AnnaBridge 171:3a7713b1edbc 1301 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1302 * | | |0 = Data Bytes [7:4] unchanged.
AnnaBridge 171:3a7713b1edbc 1303 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
AnnaBridge 171:3a7713b1edbc 1304 * |[1] |DAT_A |Access Data Bytes [3:0]
AnnaBridge 171:3a7713b1edbc 1305 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1306 * | | |0 = Data Bytes [3:0] unchanged.
AnnaBridge 171:3a7713b1edbc 1307 * | | |1 = Transfer Data Bytes [3:0] to Message Object.
AnnaBridge 171:3a7713b1edbc 1308 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1309 * | | |0 = Data Bytes [3:0] unchanged.
AnnaBridge 171:3a7713b1edbc 1310 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
AnnaBridge 171:3a7713b1edbc 1311 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
AnnaBridge 171:3a7713b1edbc 1312 * | | |0 = TxRqst bit unchanged.
AnnaBridge 171:3a7713b1edbc 1313 * | | |1 = Set TxRqst bit.
AnnaBridge 171:3a7713b1edbc 1314 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
AnnaBridge 171:3a7713b1edbc 1315 * | | |Access New Data Bit when Read Operation.
AnnaBridge 171:3a7713b1edbc 1316 * | | |0 = NewDat bit remains unchanged.
AnnaBridge 171:3a7713b1edbc 1317 * | | |1 = Clear NewDat bit in the Message Object.
AnnaBridge 171:3a7713b1edbc 1318 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
AnnaBridge 171:3a7713b1edbc 1319 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
AnnaBridge 171:3a7713b1edbc 1320 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
AnnaBridge 171:3a7713b1edbc 1321 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1322 * | | |When writing to a Message Object, this bit is ignored.
AnnaBridge 171:3a7713b1edbc 1323 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1324 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
AnnaBridge 171:3a7713b1edbc 1325 * | | |1 = Clear IntPnd bit in the Message Object.
AnnaBridge 171:3a7713b1edbc 1326 * |[4] |Control |Control Access Control Bits
AnnaBridge 171:3a7713b1edbc 1327 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1328 * | | |0 = Control Bits unchanged.
AnnaBridge 171:3a7713b1edbc 1329 * | | |1 = Transfer Control Bits to Message Object.
AnnaBridge 171:3a7713b1edbc 1330 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1331 * | | |0 = Control Bits unchanged.
AnnaBridge 171:3a7713b1edbc 1332 * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
AnnaBridge 171:3a7713b1edbc 1333 * |[5] |Arb |Access Arbitration Bits
AnnaBridge 171:3a7713b1edbc 1334 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1335 * | | |0 = Arbitration bits unchanged.
AnnaBridge 171:3a7713b1edbc 1336 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
AnnaBridge 171:3a7713b1edbc 1337 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1338 * | | |0 = Arbitration bits unchanged.
AnnaBridge 171:3a7713b1edbc 1339 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
AnnaBridge 171:3a7713b1edbc 1340 * |[6] |Mask |Access Mask Bits
AnnaBridge 171:3a7713b1edbc 1341 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 1342 * | | |0 = Mask bits unchanged.
AnnaBridge 171:3a7713b1edbc 1343 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
AnnaBridge 171:3a7713b1edbc 1344 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 1345 * | | |0 = Mask bits unchanged.
AnnaBridge 171:3a7713b1edbc 1346 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
AnnaBridge 171:3a7713b1edbc 1347 * |[7] |WR_RD |Write / Read Mode
AnnaBridge 171:3a7713b1edbc 1348 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
AnnaBridge 171:3a7713b1edbc 1349 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
AnnaBridge 171:3a7713b1edbc 1350 * @var CAN_IF_T::MASK1
AnnaBridge 171:3a7713b1edbc 1351 * Offset: 0x28, 0x88 IFn Mask 1 Register
AnnaBridge 171:3a7713b1edbc 1352 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1353 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1354 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1355 * |[15:0] |Msk[15:0] |Identifier Mask 15-0
AnnaBridge 171:3a7713b1edbc 1356 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1357 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1358 * @var CAN_IF_T::MASK2
AnnaBridge 171:3a7713b1edbc 1359 * Offset: 0x2C, 0x8C IFn Mask 2 Register
AnnaBridge 171:3a7713b1edbc 1360 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1361 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1362 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1363 * |[12:0] |Msk[28:16]|Identifier Mask 28-16
AnnaBridge 171:3a7713b1edbc 1364 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1365 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1366 * |[14] |MDir |Mask Message Direction
AnnaBridge 171:3a7713b1edbc 1367 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1368 * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1369 * |[15] |MXtd |Mask Extended Identifier
AnnaBridge 171:3a7713b1edbc 1370 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1371 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1372 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
AnnaBridge 171:3a7713b1edbc 1373 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
AnnaBridge 171:3a7713b1edbc 1374 * @var CAN_IF_T::ARB1
AnnaBridge 171:3a7713b1edbc 1375 * Offset: 0x30, 0x90 IFn Arbitration 1 Register
AnnaBridge 171:3a7713b1edbc 1376 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1377 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1378 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1379 * |[15:0] |ID[15:0] |Message Identifier 15-0
AnnaBridge 171:3a7713b1edbc 1380 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
AnnaBridge 171:3a7713b1edbc 1381 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
AnnaBridge 171:3a7713b1edbc 1382 * @var CAN_IF_T::ARB2
AnnaBridge 171:3a7713b1edbc 1383 * Offset: 0x34, 0x94 IFn Arbitration 2 Register
AnnaBridge 171:3a7713b1edbc 1384 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1385 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1386 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1387 * |[12:0] |ID[28:16] |Message Identifier 28-16
AnnaBridge 171:3a7713b1edbc 1388 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
AnnaBridge 171:3a7713b1edbc 1389 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
AnnaBridge 171:3a7713b1edbc 1390 * |[13] |Dir |Message Direction
AnnaBridge 171:3a7713b1edbc 1391 * | | |0 = Direction is receive.
AnnaBridge 171:3a7713b1edbc 1392 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
AnnaBridge 171:3a7713b1edbc 1393 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
AnnaBridge 171:3a7713b1edbc 1394 * | | |1 = Direction is transmit.
AnnaBridge 171:3a7713b1edbc 1395 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
AnnaBridge 171:3a7713b1edbc 1396 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
AnnaBridge 171:3a7713b1edbc 1397 * |[14] |Xtd |Extended Identifier
AnnaBridge 171:3a7713b1edbc 1398 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
AnnaBridge 171:3a7713b1edbc 1399 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
AnnaBridge 171:3a7713b1edbc 1400 * |[15] |MsgVal |Message Valid
AnnaBridge 171:3a7713b1edbc 1401 * | | |0 = The Message Object is ignored by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1402 * | | |1 = The Message Object is configured and should be considered by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1403 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
AnnaBridge 171:3a7713b1edbc 1404 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
AnnaBridge 171:3a7713b1edbc 1405 * @var CAN_IF_T::MCON
AnnaBridge 171:3a7713b1edbc 1406 * Offset: 0x38, 0x98 IFn Message Control Register
AnnaBridge 171:3a7713b1edbc 1407 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1408 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1409 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1410 * |[3:0] |DLC |Data Length Code
AnnaBridge 171:3a7713b1edbc 1411 * | | |0-8: Data Frame has 0-8 data bytes.
AnnaBridge 171:3a7713b1edbc 1412 * | | |9-15: Data Frame has 8 data bytes
AnnaBridge 171:3a7713b1edbc 1413 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
AnnaBridge 171:3a7713b1edbc 1414 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
AnnaBridge 171:3a7713b1edbc 1415 * | | |Data 0: 1st data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1416 * | | |Data 1: 2nd data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1417 * | | |Data 2: 3rd data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1418 * | | |Data 3: 4th data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1419 * | | |Data 4: 5th data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1420 * | | |Data 5: 6th data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1421 * | | |Data 6: 7th data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1422 * | | |Data 7 : 8th data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1423 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
AnnaBridge 171:3a7713b1edbc 1424 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
AnnaBridge 171:3a7713b1edbc 1425 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
AnnaBridge 171:3a7713b1edbc 1426 * |[7] |EoB |End Of Buffer
AnnaBridge 171:3a7713b1edbc 1427 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
AnnaBridge 171:3a7713b1edbc 1428 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
AnnaBridge 171:3a7713b1edbc 1429 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
AnnaBridge 171:3a7713b1edbc 1430 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
AnnaBridge 171:3a7713b1edbc 1431 * |[8] |TxRqst |Transmit Request
AnnaBridge 171:3a7713b1edbc 1432 * | | |0 = This Message Object is not waiting for transmission.
AnnaBridge 171:3a7713b1edbc 1433 * | | |1 = The transmission of this Message Object is requested and is not yet done.
AnnaBridge 171:3a7713b1edbc 1434 * |[9] |RmtEn |Remote Enable Control
AnnaBridge 171:3a7713b1edbc 1435 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
AnnaBridge 171:3a7713b1edbc 1436 * | | |1 = At the reception of a Remote Frame, TxRqst is set.
AnnaBridge 171:3a7713b1edbc 1437 * |[10] |RxIE |Receive Interrupt Enable Control
AnnaBridge 171:3a7713b1edbc 1438 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
AnnaBridge 171:3a7713b1edbc 1439 * | | |1 = IntPnd will be set after a successful reception of a frame.
AnnaBridge 171:3a7713b1edbc 1440 * |[11] |TxIE |Transmit Interrupt Enable Control
AnnaBridge 171:3a7713b1edbc 1441 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
AnnaBridge 171:3a7713b1edbc 1442 * | | |1 = IntPnd will be set after a successful transmission of a frame.
AnnaBridge 171:3a7713b1edbc 1443 * |[12] |UMask |Use Acceptance Mask
AnnaBridge 171:3a7713b1edbc 1444 * | | |0 = Mask ignored.
AnnaBridge 171:3a7713b1edbc 1445 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
AnnaBridge 171:3a7713b1edbc 1446 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
AnnaBridge 171:3a7713b1edbc 1447 * |[13] |IntPnd |Interrupt Pending
AnnaBridge 171:3a7713b1edbc 1448 * | | |0 = This message object is not the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1449 * | | |1 = This message object is the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1450 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
AnnaBridge 171:3a7713b1edbc 1451 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
AnnaBridge 171:3a7713b1edbc 1452 * | | |0 = No message lost since last time this bit was reset by the CPU.
AnnaBridge 171:3a7713b1edbc 1453 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
AnnaBridge 171:3a7713b1edbc 1454 * |[15] |NewDat |New Data
AnnaBridge 171:3a7713b1edbc 1455 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
AnnaBridge 171:3a7713b1edbc 1456 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
AnnaBridge 171:3a7713b1edbc 1457 * @var CAN_IF_T::DAT_A1
AnnaBridge 171:3a7713b1edbc 1458 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
AnnaBridge 171:3a7713b1edbc 1459 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1460 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1461 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1462 * |[7:0] |Data0 |Data Byte 0
AnnaBridge 171:3a7713b1edbc 1463 * | | |1st data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1464 * |[15:8] |Data1 |Data Byte 1
AnnaBridge 171:3a7713b1edbc 1465 * | | |2nd data byte of a CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1466 * @var CAN_IF_T::DAT_A2
AnnaBridge 171:3a7713b1edbc 1467 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
AnnaBridge 171:3a7713b1edbc 1468 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1469 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1470 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1471 * |[7:0] |Data2 |Data Byte 2
AnnaBridge 171:3a7713b1edbc 1472 * | | |3rd data byte of CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1473 * |[15:8] |Data3 |Data Byte 3
AnnaBridge 171:3a7713b1edbc 1474 * | | |4th data byte of CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1475 * @var CAN_IF_T::DAT_B1
AnnaBridge 171:3a7713b1edbc 1476 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
AnnaBridge 171:3a7713b1edbc 1477 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1478 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1479 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1480 * |[7:0] |Data4 |Data Byte 4
AnnaBridge 171:3a7713b1edbc 1481 * | | |5th data byte of CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1482 * |[15:8] |Data5 |Data Byte 5
AnnaBridge 171:3a7713b1edbc 1483 * | | |6th data byte of CAN Data Frame
AnnaBridge 171:3a7713b1edbc 1484 * @var CAN_IF_T::DAT_B2
AnnaBridge 171:3a7713b1edbc 1485 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
AnnaBridge 171:3a7713b1edbc 1486 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1487 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1488 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1489 * |[7:0] |Data6 |Data Byte 6
AnnaBridge 171:3a7713b1edbc 1490 * | | |7th data byte of CAN Data Frame.
AnnaBridge 171:3a7713b1edbc 1491 * |[15:8] |Data7 |Data Byte 7
AnnaBridge 171:3a7713b1edbc 1492 * | | |8th data byte of CAN Data Frame.
AnnaBridge 171:3a7713b1edbc 1493 */
AnnaBridge 171:3a7713b1edbc 1494
AnnaBridge 171:3a7713b1edbc 1495 __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
AnnaBridge 171:3a7713b1edbc 1496 __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
AnnaBridge 171:3a7713b1edbc 1497 __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
AnnaBridge 171:3a7713b1edbc 1498 __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
AnnaBridge 171:3a7713b1edbc 1499 __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
AnnaBridge 171:3a7713b1edbc 1500 __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
AnnaBridge 171:3a7713b1edbc 1501 __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
AnnaBridge 171:3a7713b1edbc 1502 __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
AnnaBridge 171:3a7713b1edbc 1503 __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
AnnaBridge 171:3a7713b1edbc 1504 __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
AnnaBridge 171:3a7713b1edbc 1505 __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
AnnaBridge 171:3a7713b1edbc 1506 __I uint32_t RESERVE0[13];
AnnaBridge 171:3a7713b1edbc 1507
AnnaBridge 171:3a7713b1edbc 1508 } CAN_IF_T;
AnnaBridge 171:3a7713b1edbc 1509
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511
AnnaBridge 171:3a7713b1edbc 1512
AnnaBridge 171:3a7713b1edbc 1513 typedef struct
AnnaBridge 171:3a7713b1edbc 1514 {
AnnaBridge 171:3a7713b1edbc 1515
AnnaBridge 171:3a7713b1edbc 1516
AnnaBridge 171:3a7713b1edbc 1517
AnnaBridge 171:3a7713b1edbc 1518 /**
AnnaBridge 171:3a7713b1edbc 1519 * @var CAN_T::CON
AnnaBridge 171:3a7713b1edbc 1520 * Offset: 0x00 Control Register
AnnaBridge 171:3a7713b1edbc 1521 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1522 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1523 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1524 * |[0] |Init |Init Initialization
AnnaBridge 171:3a7713b1edbc 1525 * | | |0 = Normal Operation.
AnnaBridge 171:3a7713b1edbc 1526 * | | |1 = Initialization is started.
AnnaBridge 171:3a7713b1edbc 1527 * |[1] |IE |Module Interrupt Enable Control
AnnaBridge 171:3a7713b1edbc 1528 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 1529 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 1530 * |[2] |SIE |Status Change Interrupt Enable Control
AnnaBridge 171:3a7713b1edbc 1531 * | | |0 = Disabled - No Status Change Interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 1532 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
AnnaBridge 171:3a7713b1edbc 1533 * |[3] |EIE |Error Interrupt Enable Control
AnnaBridge 171:3a7713b1edbc 1534 * | | |0 = Disabled - No Error Status Interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 1535 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
AnnaBridge 171:3a7713b1edbc 1536 * |[5] |DAR |Automatic Re-Transmission Disable Control
AnnaBridge 171:3a7713b1edbc 1537 * | | |0 = Automatic Retransmission of disturbed messages enabled.
AnnaBridge 171:3a7713b1edbc 1538 * | | |1 = Automatic Retransmission disabled.
AnnaBridge 171:3a7713b1edbc 1539 * |[6] |CCE |Configuration Change Enable Control
AnnaBridge 171:3a7713b1edbc 1540 * | | |0 = No write access to the Bit Timing Register.
AnnaBridge 171:3a7713b1edbc 1541 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
AnnaBridge 171:3a7713b1edbc 1542 * |[7] |Test |Test Mode Enable Control
AnnaBridge 171:3a7713b1edbc 1543 * | | |0 = Normal Operation.
AnnaBridge 171:3a7713b1edbc 1544 * | | |1 = Test Mode.
AnnaBridge 171:3a7713b1edbc 1545 * @var CAN_T::STATUS
AnnaBridge 171:3a7713b1edbc 1546 * Offset: 0x04 Status Register
AnnaBridge 171:3a7713b1edbc 1547 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1548 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1549 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1550 * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
AnnaBridge 171:3a7713b1edbc 1551 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
AnnaBridge 171:3a7713b1edbc 1552 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
AnnaBridge 171:3a7713b1edbc 1553 * | | |The unused code '7' may be written by the CPU to check for updates.
AnnaBridge 171:3a7713b1edbc 1554 * | | |The following table describes the error code.
AnnaBridge 171:3a7713b1edbc 1555 * |[3] |TxOK |Transmitted A Message Successfully
AnnaBridge 171:3a7713b1edbc 1556 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
AnnaBridge 171:3a7713b1edbc 1557 * | | |This bit is never reset by the CAN Core.
AnnaBridge 171:3a7713b1edbc 1558 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
AnnaBridge 171:3a7713b1edbc 1559 * |[4] |RxOK |Received A Message Successfully
AnnaBridge 171:3a7713b1edbc 1560 * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
AnnaBridge 171:3a7713b1edbc 1561 * | | |This bit is never reset by the CAN Core.
AnnaBridge 171:3a7713b1edbc 1562 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
AnnaBridge 171:3a7713b1edbc 1563 * |[5] |EPass |Error Passive (Read Only)
AnnaBridge 171:3a7713b1edbc 1564 * | | |0 = The CAN Core is error active.
AnnaBridge 171:3a7713b1edbc 1565 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
AnnaBridge 171:3a7713b1edbc 1566 * |[6] |EWarn |Error Warning Status (Read Only)
AnnaBridge 171:3a7713b1edbc 1567 * | | |0 = Both error counters are below the error warning limit of 96.
AnnaBridge 171:3a7713b1edbc 1568 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
AnnaBridge 171:3a7713b1edbc 1569 * |[7] |BOff |Bus-Off Status (Read Only)
AnnaBridge 171:3a7713b1edbc 1570 * | | |0 = The CAN module is not in bus-off state.
AnnaBridge 171:3a7713b1edbc 1571 * | | |1 = The CAN module is in bus-off state.
AnnaBridge 171:3a7713b1edbc 1572 * @var CAN_T::ERR
AnnaBridge 171:3a7713b1edbc 1573 * Offset: 0x08 Error Counter Register
AnnaBridge 171:3a7713b1edbc 1574 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1575 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1576 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1577 * |[7:0] |TEC |Transmit Error Counter
AnnaBridge 171:3a7713b1edbc 1578 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
AnnaBridge 171:3a7713b1edbc 1579 * |[14:8] |REC |Receive Error Counter
AnnaBridge 171:3a7713b1edbc 1580 * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
AnnaBridge 171:3a7713b1edbc 1581 * |[15] |RP |Receive Error Passive
AnnaBridge 171:3a7713b1edbc 1582 * | | |0 = The Receive Error Counter is below the error passive level.
AnnaBridge 171:3a7713b1edbc 1583 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
AnnaBridge 171:3a7713b1edbc 1584 * @var CAN_T::BTIME
AnnaBridge 171:3a7713b1edbc 1585 * Offset: 0x0C Bit Timing Register
AnnaBridge 171:3a7713b1edbc 1586 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1587 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1588 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1589 * |[5:0] |BRP |Baud Rate Prescaler
AnnaBridge 171:3a7713b1edbc 1590 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
AnnaBridge 171:3a7713b1edbc 1591 * | | |The bit time is built up from a multiple of this quanta.
AnnaBridge 171:3a7713b1edbc 1592 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
AnnaBridge 171:3a7713b1edbc 1593 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
AnnaBridge 171:3a7713b1edbc 1594 * |[7:6] |SJW |(Re)Synchronization Jump Width
AnnaBridge 171:3a7713b1edbc 1595 * | | |0x0-0x3: Valid programmed values are [0 ... 3].
AnnaBridge 171:3a7713b1edbc 1596 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
AnnaBridge 171:3a7713b1edbc 1597 * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
AnnaBridge 171:3a7713b1edbc 1598 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
AnnaBridge 171:3a7713b1edbc 1599 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
AnnaBridge 171:3a7713b1edbc 1600 * |[14:12] |TSeg2 |Time Segment After Sample Point
AnnaBridge 171:3a7713b1edbc 1601 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
AnnaBridge 171:3a7713b1edbc 1602 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
AnnaBridge 171:3a7713b1edbc 1603 * @var CAN_T::IIDR
AnnaBridge 171:3a7713b1edbc 1604 * Offset: 0x10 Interrupt Identifier Register
AnnaBridge 171:3a7713b1edbc 1605 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1606 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1607 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1608 * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
AnnaBridge 171:3a7713b1edbc 1609 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
AnnaBridge 171:3a7713b1edbc 1610 * | | |An interrupt remains pending until the application software has cleared it.
AnnaBridge 171:3a7713b1edbc 1611 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
AnnaBridge 171:3a7713b1edbc 1612 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
AnnaBridge 171:3a7713b1edbc 1613 * | | |The Status Interrupt has the highest priority.
AnnaBridge 171:3a7713b1edbc 1614 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
AnnaBridge 171:3a7713b1edbc 1615 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
AnnaBridge 171:3a7713b1edbc 1616 * | | |The Status Interrupt is cleared by reading the Status Register.
AnnaBridge 171:3a7713b1edbc 1617 * @var CAN_T::TEST
AnnaBridge 171:3a7713b1edbc 1618 * Offset: 0x14 Test Register (Register Map Note 1)
AnnaBridge 171:3a7713b1edbc 1619 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1620 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1621 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1622 * |[1:0] |Res |Reserved
AnnaBridge 171:3a7713b1edbc 1623 * | | |There are reserved bits.
AnnaBridge 171:3a7713b1edbc 1624 * | | |These bits are always read as '0' and must always be written with '0'.
AnnaBridge 171:3a7713b1edbc 1625 * |[2] |Basic |Basic Mode
AnnaBridge 171:3a7713b1edbc 1626 * | | |0 = Basic Mode disabled.
AnnaBridge 171:3a7713b1edbc 1627 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
AnnaBridge 171:3a7713b1edbc 1628 * |[3] |Silent |Silent Mode
AnnaBridge 171:3a7713b1edbc 1629 * | | |0 = Normal operation.
AnnaBridge 171:3a7713b1edbc 1630 * | | |1 = The module is in Silent Mode.
AnnaBridge 171:3a7713b1edbc 1631 * |[4] |LBack |Loop Back Mode Enable Control
AnnaBridge 171:3a7713b1edbc 1632 * | | |0 = Loop Back Mode is disabled.
AnnaBridge 171:3a7713b1edbc 1633 * | | |1 = Loop Back Mode is enabled.
AnnaBridge 171:3a7713b1edbc 1634 * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
AnnaBridge 171:3a7713b1edbc 1635 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
AnnaBridge 171:3a7713b1edbc 1636 * | | |01 = Sample Point can be monitored at CAN_TX pin.
AnnaBridge 171:3a7713b1edbc 1637 * | | |10 = CAN_TX pin drives a dominant ('0') value.
AnnaBridge 171:3a7713b1edbc 1638 * | | |11 = CAN_TX pin drives a recessive ('1') value.
AnnaBridge 171:3a7713b1edbc 1639 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
AnnaBridge 171:3a7713b1edbc 1640 * | | |0 = The CAN bus is dominant (CAN_RX = '0').
AnnaBridge 171:3a7713b1edbc 1641 * | | |1 = The CAN bus is recessive (CAN_RX = '1').
AnnaBridge 171:3a7713b1edbc 1642 * @var CAN_T::BRPE
AnnaBridge 171:3a7713b1edbc 1643 * Offset: 0x18 Baud Rate Prescaler Extension Register
AnnaBridge 171:3a7713b1edbc 1644 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1645 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1646 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1647 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
AnnaBridge 171:3a7713b1edbc 1648 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
AnnaBridge 171:3a7713b1edbc 1649 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
AnnaBridge 171:3a7713b1edbc 1650 * @var CAN_T::IF
AnnaBridge 171:3a7713b1edbc 1651 * Offset: 0x20~0xFC CAN Interface Registers
AnnaBridge 171:3a7713b1edbc 1652 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1653 * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
AnnaBridge 171:3a7713b1edbc 1654 *
AnnaBridge 171:3a7713b1edbc 1655 * @var CAN_T::TXREQ1
AnnaBridge 171:3a7713b1edbc 1656 * Offset: 0x100 Transmission Request Register 1
AnnaBridge 171:3a7713b1edbc 1657 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1658 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1659 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1660 * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1661 * | | |0 = This Message Object is not waiting for transmission.
AnnaBridge 171:3a7713b1edbc 1662 * | | |1 = The transmission of this Message Object is requested and is not yet done.
AnnaBridge 171:3a7713b1edbc 1663 * | | |These bits are read only.
AnnaBridge 171:3a7713b1edbc 1664 * @var CAN_T::TXREQ2
AnnaBridge 171:3a7713b1edbc 1665 * Offset: 0x104 Transmission Request Register 2
AnnaBridge 171:3a7713b1edbc 1666 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1667 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1668 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1669 * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1670 * | | |0 = This Message Object is not waiting for transmission.
AnnaBridge 171:3a7713b1edbc 1671 * | | |1 = The transmission of this Message Object is requested and is not yet done.
AnnaBridge 171:3a7713b1edbc 1672 * | | |These bits are read only.
AnnaBridge 171:3a7713b1edbc 1673 * @var CAN_T::NDAT1
AnnaBridge 171:3a7713b1edbc 1674 * Offset: 0x120 New Data Register 1
AnnaBridge 171:3a7713b1edbc 1675 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1676 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1677 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1678 * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1679 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
AnnaBridge 171:3a7713b1edbc 1680 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
AnnaBridge 171:3a7713b1edbc 1681 * @var CAN_T::NDAT2
AnnaBridge 171:3a7713b1edbc 1682 * Offset: 0x124 New Data Register 2
AnnaBridge 171:3a7713b1edbc 1683 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1684 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1685 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1686 * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1687 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
AnnaBridge 171:3a7713b1edbc 1688 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
AnnaBridge 171:3a7713b1edbc 1689 * @var CAN_T::IPND1
AnnaBridge 171:3a7713b1edbc 1690 * Offset: 0x140 Interrupt Pending Register 1
AnnaBridge 171:3a7713b1edbc 1691 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1692 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1693 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1694 * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1695 * | | |0 = This message object is not the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1696 * | | |1 = This message object is the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1697 * @var CAN_T::IPND2
AnnaBridge 171:3a7713b1edbc 1698 * Offset: 0x144 Interrupt Pending Register 2
AnnaBridge 171:3a7713b1edbc 1699 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1700 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1701 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1702 * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
AnnaBridge 171:3a7713b1edbc 1703 * | | |0 = This message object is not the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1704 * | | |1 = This message object is the source of an interrupt.
AnnaBridge 171:3a7713b1edbc 1705 * @var CAN_T::MVLD1
AnnaBridge 171:3a7713b1edbc 1706 * Offset: 0x160 Message Valid Register 1
AnnaBridge 171:3a7713b1edbc 1707 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1708 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1709 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1710 * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
AnnaBridge 171:3a7713b1edbc 1711 * | | |0 = This Message Object is ignored by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1712 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1713 * | | |Ex.
AnnaBridge 171:3a7713b1edbc 1714 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
AnnaBridge 171:3a7713b1edbc 1715 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
AnnaBridge 171:3a7713b1edbc 1716 * @var CAN_T::MVLD2
AnnaBridge 171:3a7713b1edbc 1717 * Offset: 0x164 Message Valid Register 2
AnnaBridge 171:3a7713b1edbc 1718 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1719 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1720 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1721 * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
AnnaBridge 171:3a7713b1edbc 1722 * | | |0 = This Message Object is ignored by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1723 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
AnnaBridge 171:3a7713b1edbc 1724 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
AnnaBridge 171:3a7713b1edbc 1725 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
AnnaBridge 171:3a7713b1edbc 1726 * @var CAN_T::WU_EN
AnnaBridge 171:3a7713b1edbc 1727 * Offset: 0x168 Wake-up Enable Register
AnnaBridge 171:3a7713b1edbc 1728 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1729 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1730 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1731 * |[0] |WAKUP_EN |Wake-Up Enable Control
AnnaBridge 171:3a7713b1edbc 1732 * | | |0 = The wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 1733 * | | |1 = The wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 1734 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
AnnaBridge 171:3a7713b1edbc 1735 * @var CAN_T::WU_STATUS
AnnaBridge 171:3a7713b1edbc 1736 * Offset: 0x16C Wake-up Status Register
AnnaBridge 171:3a7713b1edbc 1737 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1738 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 1739 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 1740 * |[0] |WAKUP_STS |Wake-Up Status
AnnaBridge 171:3a7713b1edbc 1741 * | | |0 = No wake-up event occurred.
AnnaBridge 171:3a7713b1edbc 1742 * | | |1 = Wake-up event occurred.
AnnaBridge 171:3a7713b1edbc 1743 * | | |Note: This bit can be cleared by writing '0'.
AnnaBridge 171:3a7713b1edbc 1744 */
AnnaBridge 171:3a7713b1edbc 1745
AnnaBridge 171:3a7713b1edbc 1746 __IO uint32_t CON; /* Offset: 0x00 Control Register */
AnnaBridge 171:3a7713b1edbc 1747 __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
AnnaBridge 171:3a7713b1edbc 1748 __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
AnnaBridge 171:3a7713b1edbc 1749 __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
AnnaBridge 171:3a7713b1edbc 1750 __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
AnnaBridge 171:3a7713b1edbc 1751 __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
AnnaBridge 171:3a7713b1edbc 1752 __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
AnnaBridge 171:3a7713b1edbc 1753 __I uint32_t RESERVE0[1];
AnnaBridge 171:3a7713b1edbc 1754 __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
AnnaBridge 171:3a7713b1edbc 1755 __I uint32_t RESERVE1[8];
AnnaBridge 171:3a7713b1edbc 1756 __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
AnnaBridge 171:3a7713b1edbc 1757 __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
AnnaBridge 171:3a7713b1edbc 1758 __I uint32_t RESERVE3[6];
AnnaBridge 171:3a7713b1edbc 1759 __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
AnnaBridge 171:3a7713b1edbc 1760 __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
AnnaBridge 171:3a7713b1edbc 1761 __I uint32_t RESERVE4[6];
AnnaBridge 171:3a7713b1edbc 1762 __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
AnnaBridge 171:3a7713b1edbc 1763 __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
AnnaBridge 171:3a7713b1edbc 1764 __I uint32_t RESERVE5[6];
AnnaBridge 171:3a7713b1edbc 1765 __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
AnnaBridge 171:3a7713b1edbc 1766 __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
AnnaBridge 171:3a7713b1edbc 1767 __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
AnnaBridge 171:3a7713b1edbc 1768 __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
AnnaBridge 171:3a7713b1edbc 1769
AnnaBridge 171:3a7713b1edbc 1770 } CAN_T;
AnnaBridge 171:3a7713b1edbc 1771
AnnaBridge 171:3a7713b1edbc 1772
AnnaBridge 171:3a7713b1edbc 1773
AnnaBridge 171:3a7713b1edbc 1774 /**
AnnaBridge 171:3a7713b1edbc 1775 @addtogroup CAN_CONST CAN Bit Field Definition
AnnaBridge 171:3a7713b1edbc 1776 Constant Definitions for CAN Controller
AnnaBridge 171:3a7713b1edbc 1777 @{ */
AnnaBridge 171:3a7713b1edbc 1778 /* CAN CON Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1779 #define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
AnnaBridge 171:3a7713b1edbc 1780 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
AnnaBridge 171:3a7713b1edbc 1781
AnnaBridge 171:3a7713b1edbc 1782 #define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
AnnaBridge 171:3a7713b1edbc 1783 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
AnnaBridge 171:3a7713b1edbc 1784
AnnaBridge 171:3a7713b1edbc 1785 #define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
AnnaBridge 171:3a7713b1edbc 1786 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
AnnaBridge 171:3a7713b1edbc 1787
AnnaBridge 171:3a7713b1edbc 1788 #define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
AnnaBridge 171:3a7713b1edbc 1789 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
AnnaBridge 171:3a7713b1edbc 1790
AnnaBridge 171:3a7713b1edbc 1791 #define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
AnnaBridge 171:3a7713b1edbc 1792 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 #define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
AnnaBridge 171:3a7713b1edbc 1795 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
AnnaBridge 171:3a7713b1edbc 1796
AnnaBridge 171:3a7713b1edbc 1797 #define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
AnnaBridge 171:3a7713b1edbc 1798 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
AnnaBridge 171:3a7713b1edbc 1799
AnnaBridge 171:3a7713b1edbc 1800 /* CAN STATUS Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1801 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
AnnaBridge 171:3a7713b1edbc 1802 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
AnnaBridge 171:3a7713b1edbc 1803
AnnaBridge 171:3a7713b1edbc 1804 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
AnnaBridge 171:3a7713b1edbc 1805 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
AnnaBridge 171:3a7713b1edbc 1806
AnnaBridge 171:3a7713b1edbc 1807 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
AnnaBridge 171:3a7713b1edbc 1808 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
AnnaBridge 171:3a7713b1edbc 1809
AnnaBridge 171:3a7713b1edbc 1810 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
AnnaBridge 171:3a7713b1edbc 1811 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
AnnaBridge 171:3a7713b1edbc 1812
AnnaBridge 171:3a7713b1edbc 1813 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
AnnaBridge 171:3a7713b1edbc 1814 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
AnnaBridge 171:3a7713b1edbc 1815
AnnaBridge 171:3a7713b1edbc 1816 #define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
AnnaBridge 171:3a7713b1edbc 1817 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
AnnaBridge 171:3a7713b1edbc 1818
AnnaBridge 171:3a7713b1edbc 1819 /* CAN ERR Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1820 #define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
AnnaBridge 171:3a7713b1edbc 1821 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
AnnaBridge 171:3a7713b1edbc 1822
AnnaBridge 171:3a7713b1edbc 1823 #define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
AnnaBridge 171:3a7713b1edbc 1824 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
AnnaBridge 171:3a7713b1edbc 1825
AnnaBridge 171:3a7713b1edbc 1826 #define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
AnnaBridge 171:3a7713b1edbc 1827 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
AnnaBridge 171:3a7713b1edbc 1828
AnnaBridge 171:3a7713b1edbc 1829 /* CAN BTIME Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1830 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
AnnaBridge 171:3a7713b1edbc 1831 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
AnnaBridge 171:3a7713b1edbc 1832
AnnaBridge 171:3a7713b1edbc 1833 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
AnnaBridge 171:3a7713b1edbc 1834 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
AnnaBridge 171:3a7713b1edbc 1835
AnnaBridge 171:3a7713b1edbc 1836 #define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
AnnaBridge 171:3a7713b1edbc 1837 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
AnnaBridge 171:3a7713b1edbc 1838
AnnaBridge 171:3a7713b1edbc 1839 #define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
AnnaBridge 171:3a7713b1edbc 1840 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
AnnaBridge 171:3a7713b1edbc 1841
AnnaBridge 171:3a7713b1edbc 1842 /* CAN IIDR Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1843 #define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
AnnaBridge 171:3a7713b1edbc 1844 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
AnnaBridge 171:3a7713b1edbc 1845
AnnaBridge 171:3a7713b1edbc 1846 /* CAN TEST Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1847 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
AnnaBridge 171:3a7713b1edbc 1848 #define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
AnnaBridge 171:3a7713b1edbc 1849
AnnaBridge 171:3a7713b1edbc 1850 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
AnnaBridge 171:3a7713b1edbc 1851 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
AnnaBridge 171:3a7713b1edbc 1852
AnnaBridge 171:3a7713b1edbc 1853 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
AnnaBridge 171:3a7713b1edbc 1854 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
AnnaBridge 171:3a7713b1edbc 1855
AnnaBridge 171:3a7713b1edbc 1856 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
AnnaBridge 171:3a7713b1edbc 1857 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
AnnaBridge 171:3a7713b1edbc 1858
AnnaBridge 171:3a7713b1edbc 1859 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
AnnaBridge 171:3a7713b1edbc 1860 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
AnnaBridge 171:3a7713b1edbc 1861
AnnaBridge 171:3a7713b1edbc 1862 /* CAN BPRE Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1863 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
AnnaBridge 171:3a7713b1edbc 1864 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
AnnaBridge 171:3a7713b1edbc 1865
AnnaBridge 171:3a7713b1edbc 1866 /* CAN IFn_CREQ Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1867 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
AnnaBridge 171:3a7713b1edbc 1868 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 1869
AnnaBridge 171:3a7713b1edbc 1870 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
AnnaBridge 171:3a7713b1edbc 1871 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
AnnaBridge 171:3a7713b1edbc 1872
AnnaBridge 171:3a7713b1edbc 1873 /* CAN IFn_CMASK Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1874 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
AnnaBridge 171:3a7713b1edbc 1875 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
AnnaBridge 171:3a7713b1edbc 1876
AnnaBridge 171:3a7713b1edbc 1877 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
AnnaBridge 171:3a7713b1edbc 1878 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
AnnaBridge 171:3a7713b1edbc 1879
AnnaBridge 171:3a7713b1edbc 1880 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
AnnaBridge 171:3a7713b1edbc 1881 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
AnnaBridge 171:3a7713b1edbc 1884 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
AnnaBridge 171:3a7713b1edbc 1885
AnnaBridge 171:3a7713b1edbc 1886 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
AnnaBridge 171:3a7713b1edbc 1887 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
AnnaBridge 171:3a7713b1edbc 1888
AnnaBridge 171:3a7713b1edbc 1889 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
AnnaBridge 171:3a7713b1edbc 1890 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
AnnaBridge 171:3a7713b1edbc 1891
AnnaBridge 171:3a7713b1edbc 1892 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
AnnaBridge 171:3a7713b1edbc 1893 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
AnnaBridge 171:3a7713b1edbc 1894
AnnaBridge 171:3a7713b1edbc 1895 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
AnnaBridge 171:3a7713b1edbc 1896 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
AnnaBridge 171:3a7713b1edbc 1897
AnnaBridge 171:3a7713b1edbc 1898 /* CAN IFn_MASK1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1899 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
AnnaBridge 171:3a7713b1edbc 1900 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
AnnaBridge 171:3a7713b1edbc 1901
AnnaBridge 171:3a7713b1edbc 1902 /* CAN IFn_MASK2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1903 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
AnnaBridge 171:3a7713b1edbc 1904 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
AnnaBridge 171:3a7713b1edbc 1905
AnnaBridge 171:3a7713b1edbc 1906 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
AnnaBridge 171:3a7713b1edbc 1907 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
AnnaBridge 171:3a7713b1edbc 1908
AnnaBridge 171:3a7713b1edbc 1909 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
AnnaBridge 171:3a7713b1edbc 1910 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
AnnaBridge 171:3a7713b1edbc 1911
AnnaBridge 171:3a7713b1edbc 1912 /* CAN IFn_ARB1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1913 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
AnnaBridge 171:3a7713b1edbc 1914 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
AnnaBridge 171:3a7713b1edbc 1915
AnnaBridge 171:3a7713b1edbc 1916 /* CAN IFn_ARB2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1917 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
AnnaBridge 171:3a7713b1edbc 1918 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
AnnaBridge 171:3a7713b1edbc 1919
AnnaBridge 171:3a7713b1edbc 1920 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
AnnaBridge 171:3a7713b1edbc 1921 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
AnnaBridge 171:3a7713b1edbc 1922
AnnaBridge 171:3a7713b1edbc 1923 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
AnnaBridge 171:3a7713b1edbc 1924 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
AnnaBridge 171:3a7713b1edbc 1925
AnnaBridge 171:3a7713b1edbc 1926 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
AnnaBridge 171:3a7713b1edbc 1927 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
AnnaBridge 171:3a7713b1edbc 1928
AnnaBridge 171:3a7713b1edbc 1929 /* CAN IFn_MCON Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1930 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
AnnaBridge 171:3a7713b1edbc 1931 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
AnnaBridge 171:3a7713b1edbc 1932
AnnaBridge 171:3a7713b1edbc 1933 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
AnnaBridge 171:3a7713b1edbc 1934 #define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
AnnaBridge 171:3a7713b1edbc 1935
AnnaBridge 171:3a7713b1edbc 1936 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
AnnaBridge 171:3a7713b1edbc 1937 #define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
AnnaBridge 171:3a7713b1edbc 1938
AnnaBridge 171:3a7713b1edbc 1939 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
AnnaBridge 171:3a7713b1edbc 1940 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
AnnaBridge 171:3a7713b1edbc 1941
AnnaBridge 171:3a7713b1edbc 1942 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
AnnaBridge 171:3a7713b1edbc 1943 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
AnnaBridge 171:3a7713b1edbc 1944
AnnaBridge 171:3a7713b1edbc 1945 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
AnnaBridge 171:3a7713b1edbc 1946 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
AnnaBridge 171:3a7713b1edbc 1947
AnnaBridge 171:3a7713b1edbc 1948 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
AnnaBridge 171:3a7713b1edbc 1949 #define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
AnnaBridge 171:3a7713b1edbc 1950
AnnaBridge 171:3a7713b1edbc 1951 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
AnnaBridge 171:3a7713b1edbc 1952 #define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
AnnaBridge 171:3a7713b1edbc 1953
AnnaBridge 171:3a7713b1edbc 1954 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
AnnaBridge 171:3a7713b1edbc 1955 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
AnnaBridge 171:3a7713b1edbc 1956
AnnaBridge 171:3a7713b1edbc 1957 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
AnnaBridge 171:3a7713b1edbc 1958 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
AnnaBridge 171:3a7713b1edbc 1959
AnnaBridge 171:3a7713b1edbc 1960 /* CAN IFn_DATA_A1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1961 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
AnnaBridge 171:3a7713b1edbc 1962 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
AnnaBridge 171:3a7713b1edbc 1963
AnnaBridge 171:3a7713b1edbc 1964 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
AnnaBridge 171:3a7713b1edbc 1965 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
AnnaBridge 171:3a7713b1edbc 1966
AnnaBridge 171:3a7713b1edbc 1967 /* CAN IFn_DATA_A2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1968 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
AnnaBridge 171:3a7713b1edbc 1969 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
AnnaBridge 171:3a7713b1edbc 1970
AnnaBridge 171:3a7713b1edbc 1971 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
AnnaBridge 171:3a7713b1edbc 1972 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
AnnaBridge 171:3a7713b1edbc 1973
AnnaBridge 171:3a7713b1edbc 1974 /* CAN IFn_DATA_B1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1975 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
AnnaBridge 171:3a7713b1edbc 1976 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
AnnaBridge 171:3a7713b1edbc 1977
AnnaBridge 171:3a7713b1edbc 1978 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
AnnaBridge 171:3a7713b1edbc 1979 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
AnnaBridge 171:3a7713b1edbc 1980
AnnaBridge 171:3a7713b1edbc 1981 /* CAN IFn_DATA_B2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1982 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
AnnaBridge 171:3a7713b1edbc 1983 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
AnnaBridge 171:3a7713b1edbc 1984
AnnaBridge 171:3a7713b1edbc 1985 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
AnnaBridge 171:3a7713b1edbc 1986 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
AnnaBridge 171:3a7713b1edbc 1987
AnnaBridge 171:3a7713b1edbc 1988 /* CAN IFn_TXRQST1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1989 #define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
AnnaBridge 171:3a7713b1edbc 1990 #define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
AnnaBridge 171:3a7713b1edbc 1991
AnnaBridge 171:3a7713b1edbc 1992 /* CAN IFn_TXRQST2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1993 #define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
AnnaBridge 171:3a7713b1edbc 1994 #define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
AnnaBridge 171:3a7713b1edbc 1995
AnnaBridge 171:3a7713b1edbc 1996 /* CAN IFn_NDAT1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 1997 #define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
AnnaBridge 171:3a7713b1edbc 1998 #define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
AnnaBridge 171:3a7713b1edbc 1999
AnnaBridge 171:3a7713b1edbc 2000 /* CAN IFn_NDAT2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2001 #define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
AnnaBridge 171:3a7713b1edbc 2002 #define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
AnnaBridge 171:3a7713b1edbc 2003
AnnaBridge 171:3a7713b1edbc 2004 /* CAN IFn_IPND1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2005 #define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
AnnaBridge 171:3a7713b1edbc 2006 #define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
AnnaBridge 171:3a7713b1edbc 2007
AnnaBridge 171:3a7713b1edbc 2008 /* CAN IFn_IPND2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2009 #define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
AnnaBridge 171:3a7713b1edbc 2010 #define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
AnnaBridge 171:3a7713b1edbc 2011
AnnaBridge 171:3a7713b1edbc 2012 /* CAN IFn_MVLD1 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2013 #define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
AnnaBridge 171:3a7713b1edbc 2014 #define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
AnnaBridge 171:3a7713b1edbc 2015
AnnaBridge 171:3a7713b1edbc 2016 /* CAN IFn_MVLD2 Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2017 #define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
AnnaBridge 171:3a7713b1edbc 2018 #define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
AnnaBridge 171:3a7713b1edbc 2019
AnnaBridge 171:3a7713b1edbc 2020 /* CAN WUEN Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2021 #define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
AnnaBridge 171:3a7713b1edbc 2022 #define CAN_WUEN_WAKUP_EN_Msk (0x1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
AnnaBridge 171:3a7713b1edbc 2023
AnnaBridge 171:3a7713b1edbc 2024 /* CAN WUSTATUS Bit Field Definitions */
AnnaBridge 171:3a7713b1edbc 2025 #define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
AnnaBridge 171:3a7713b1edbc 2026 #define CAN_WUSTATUS_WAKUP_STS_Msk (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
AnnaBridge 171:3a7713b1edbc 2027
AnnaBridge 171:3a7713b1edbc 2028
AnnaBridge 171:3a7713b1edbc 2029 /**@}*/ /* CAN_CONST */
AnnaBridge 171:3a7713b1edbc 2030 /**@}*/ /* end of CAN register group */
AnnaBridge 171:3a7713b1edbc 2031
AnnaBridge 171:3a7713b1edbc 2032
AnnaBridge 171:3a7713b1edbc 2033 /*---------------------- System Clock Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 2034 /**
AnnaBridge 171:3a7713b1edbc 2035 @addtogroup CLK System Clock Controller(CLK)
AnnaBridge 171:3a7713b1edbc 2036 Memory Mapped Structure for CLK Controller
AnnaBridge 171:3a7713b1edbc 2037 @{ */
AnnaBridge 171:3a7713b1edbc 2038
AnnaBridge 171:3a7713b1edbc 2039
AnnaBridge 171:3a7713b1edbc 2040 typedef struct
AnnaBridge 171:3a7713b1edbc 2041 {
AnnaBridge 171:3a7713b1edbc 2042
AnnaBridge 171:3a7713b1edbc 2043
AnnaBridge 171:3a7713b1edbc 2044
AnnaBridge 171:3a7713b1edbc 2045
AnnaBridge 171:3a7713b1edbc 2046 /**
AnnaBridge 171:3a7713b1edbc 2047 * @var CLK_T::PWRCTL
AnnaBridge 171:3a7713b1edbc 2048 * Offset: 0x00 System Power-down Control Register
AnnaBridge 171:3a7713b1edbc 2049 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2050 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2051 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2052 * |[0] |HXTEN |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2053 * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
AnnaBridge 171:3a7713b1edbc 2054 * | | |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
AnnaBridge 171:3a7713b1edbc 2055 * | | |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
AnnaBridge 171:3a7713b1edbc 2056 * | | |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
AnnaBridge 171:3a7713b1edbc 2057 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2058 * |[1] |LXTEN |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2059 * | | |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
AnnaBridge 171:3a7713b1edbc 2060 * | | |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
AnnaBridge 171:3a7713b1edbc 2061 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2062 * |[2] |HIRCEN |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2063 * | | |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
AnnaBridge 171:3a7713b1edbc 2064 * | | |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
AnnaBridge 171:3a7713b1edbc 2065 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2066 * |[3] |LIRCEN |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2067 * | | |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
AnnaBridge 171:3a7713b1edbc 2068 * | | |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
AnnaBridge 171:3a7713b1edbc 2069 * |[4] |PDWKDLY |Enable The Wake-Up Delay Counter (Write Protect)
AnnaBridge 171:3a7713b1edbc 2070 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
AnnaBridge 171:3a7713b1edbc 2071 * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
AnnaBridge 171:3a7713b1edbc 2072 * | | |0 = Clock cycles delay Disabled.
AnnaBridge 171:3a7713b1edbc 2073 * | | |1 = Clock cycles delay Enabled.
AnnaBridge 171:3a7713b1edbc 2074 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2075 * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2076 * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 2077 * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 2078 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
AnnaBridge 171:3a7713b1edbc 2079 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2080 * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
AnnaBridge 171:3a7713b1edbc 2081 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
AnnaBridge 171:3a7713b1edbc 2082 * | | |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
AnnaBridge 171:3a7713b1edbc 2083 * | | |Note1: Write 1 to clear the bit to 0.
AnnaBridge 171:3a7713b1edbc 2084 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
AnnaBridge 171:3a7713b1edbc 2085 * |[7] |PDEN |System Power-Down Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 2086 * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
AnnaBridge 171:3a7713b1edbc 2087 * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
AnnaBridge 171:3a7713b1edbc 2088 * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
AnnaBridge 171:3a7713b1edbc 2089 * | | |When chip wakes up from Power-down mode, this bit is auto cleared.
AnnaBridge 171:3a7713b1edbc 2090 * | | |Users need to set this bit again for next Power-down.
AnnaBridge 171:3a7713b1edbc 2091 * | | |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
AnnaBridge 171:3a7713b1edbc 2092 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
AnnaBridge 171:3a7713b1edbc 2093 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
AnnaBridge 171:3a7713b1edbc 2094 * | | |0 = Chip operating normally or chip in idle mode because of WFI command.
AnnaBridge 171:3a7713b1edbc 2095 * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
AnnaBridge 171:3a7713b1edbc 2096 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2097 * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
AnnaBridge 171:3a7713b1edbc 2098 * | | |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
AnnaBridge 171:3a7713b1edbc 2099 * | | |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
AnnaBridge 171:3a7713b1edbc 2100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2101 * |[11:10] |HXTGAIN |4~24 MHz High-Speed Crystal Gain Control Bit
AnnaBridge 171:3a7713b1edbc 2102 * | | |(Write Protect)
AnnaBridge 171:3a7713b1edbc 2103 * | | |This is a protected register. Please refer to open lock sequence to program it.
AnnaBridge 171:3a7713b1edbc 2104 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
AnnaBridge 171:3a7713b1edbc 2105 * | | |If gain control is enabled, crystal will consume more power than gain control off.
AnnaBridge 171:3a7713b1edbc 2106 * | | |00 = HXT frequency is lower than from 8 MHz.
AnnaBridge 171:3a7713b1edbc 2107 * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
AnnaBridge 171:3a7713b1edbc 2108 * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
AnnaBridge 171:3a7713b1edbc 2109 * | | |11 = HXT frequency is higher than 16 MHz.
AnnaBridge 171:3a7713b1edbc 2110 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2111 * |[12] |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2112 * | | |This is a protected register. Please refer to open lock sequence to program it.
AnnaBridge 171:3a7713b1edbc 2113 * | | |0 = Select INV type.
AnnaBridge 171:3a7713b1edbc 2114 * | | |1 = Select GM type.
AnnaBridge 171:3a7713b1edbc 2115 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2116 * @var CLK_T::AHBCLK
AnnaBridge 171:3a7713b1edbc 2117 * Offset: 0x04 AHB Devices Clock Enable Control Register
AnnaBridge 171:3a7713b1edbc 2118 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2119 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2120 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2121 * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2122 * | | |0 = PDMA peripheral clock Disabled.
AnnaBridge 171:3a7713b1edbc 2123 * | | |1 = PDMA peripheral clock Enabled.
AnnaBridge 171:3a7713b1edbc 2124 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2125 * | | |0 = Flash ISP peripheral clock Disabled.
AnnaBridge 171:3a7713b1edbc 2126 * | | |1 = Flash ISP peripheral clock Enabled.
AnnaBridge 171:3a7713b1edbc 2127 * |[3] |EBICKEN |EBI Controller Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2128 * | | |0 = EBI peripheral clock Disabled.
AnnaBridge 171:3a7713b1edbc 2129 * | | |1 = EBI peripheral clock Enabled.
AnnaBridge 171:3a7713b1edbc 2130 * |[4] |USBHCKEN |USB HOST Controller Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2131 * | | |0 = USB HOST peripheral clock Disabled.
AnnaBridge 171:3a7713b1edbc 2132 * | | |1 = USB HOST peripheral clock Enabled.
AnnaBridge 171:3a7713b1edbc 2133 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2134 * | | |0 = CRC peripheral clock Disabled.
AnnaBridge 171:3a7713b1edbc 2135 * | | |1 = CRC peripheral clock Enabled.
AnnaBridge 171:3a7713b1edbc 2136 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit In IDLE Mode
AnnaBridge 171:3a7713b1edbc 2137 * | | |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
AnnaBridge 171:3a7713b1edbc 2138 * | | |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
AnnaBridge 171:3a7713b1edbc 2139 * @var CLK_T::APBCLK0
AnnaBridge 171:3a7713b1edbc 2140 * Offset: 0x08 APB Devices Clock Enable Control Register 0
AnnaBridge 171:3a7713b1edbc 2141 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2142 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2143 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2144 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 2145 * | | |0 = Watchdog Timer Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2146 * | | |1 = Watchdog Timer Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2147 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2148 * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2149 * | | |This bit is used to control the RTC APB clock only.
AnnaBridge 171:3a7713b1edbc 2150 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
AnnaBridge 171:3a7713b1edbc 2151 * | | |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
AnnaBridge 171:3a7713b1edbc 2152 * | | |0 = RTC Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2153 * | | |1 = RTC Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2154 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2155 * | | |0 = Timer0 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2156 * | | |1 = Timer0 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2157 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2158 * | | |0 = Timer1 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2159 * | | |1 = Timer1 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2160 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2161 * | | |0 = Timer2 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2162 * | | |1 = Timer2 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2163 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2164 * | | |0 = Timer3 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2165 * | | |1 = Timer3 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2166 * |[6] |CLKOCKEN |CLKO Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2167 * | | |0 = CLKO Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2168 * | | |1 = CLKO Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2169 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2170 * | | |0 = Analog Comparator 0/1 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2171 * | | |1 = Analog Comparator 0/1 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2172 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2173 * | | |0 = I2C0 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2174 * | | |1 = I2C0 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2175 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2176 * | | |0 = I2C1 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2177 * | | |1 = I2C1 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2178 * |[12] |SPI0CKEN |SPI0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2179 * | | |0 = SPI0 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2180 * | | |1 = SPI0 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2181 * |[13] |SPI1CKEN |SPI1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2182 * | | |0 = SPI1 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2183 * | | |1 = SPI1 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2184 * |[14] |SPI2CKEN |SPI2 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2185 * | | |0 = SPI2 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2186 * | | |1 = SPI2 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2187 * |[16] |UART0CKEN |UART0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2188 * | | |0 = UART0 clock Disabled.
AnnaBridge 171:3a7713b1edbc 2189 * | | |1 = UART0 clock Enabled.
AnnaBridge 171:3a7713b1edbc 2190 * |[17] |UART1CKEN |UART1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2191 * | | |0 = UART1 clock Disabled.
AnnaBridge 171:3a7713b1edbc 2192 * | | |1 = UART1 clock Enabled.
AnnaBridge 171:3a7713b1edbc 2193 * |[18] |UART2CKEN |UART2 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2194 * | | |0 = UART2 clock Disabled.
AnnaBridge 171:3a7713b1edbc 2195 * | | |1 = UART2 clock Enabled.
AnnaBridge 171:3a7713b1edbc 2196 * |[19] |UART3CKEN |UART3 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2197 * | | |0 = UART3 clock Disabled.
AnnaBridge 171:3a7713b1edbc 2198 * | | |1 = UART3 clock Enabled.
AnnaBridge 171:3a7713b1edbc 2199 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2200 * | | |0 = CAN0 clock Disabled.
AnnaBridge 171:3a7713b1edbc 2201 * | | |1 = CAN0 clock Enabled.
AnnaBridge 171:3a7713b1edbc 2202 * |[26] |OTGCKEN |USB OTG Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2203 * | | |0 = USB OTG clock Disabled.
AnnaBridge 171:3a7713b1edbc 2204 * | | |1 = USB OTG clock Enabled.
AnnaBridge 171:3a7713b1edbc 2205 * |[27] |USBDCKEN |USB Device Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2206 * | | |0 = USB Device clock Disabled.
AnnaBridge 171:3a7713b1edbc 2207 * | | |1 = USB Device clock Enabled.
AnnaBridge 171:3a7713b1edbc 2208 * |[28] |EADCCKEN |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2209 * | | |0 = EADC clock Disabled.
AnnaBridge 171:3a7713b1edbc 2210 * | | |1 = EADC clock Enabled.
AnnaBridge 171:3a7713b1edbc 2211 * @var CLK_T::APBCLK1
AnnaBridge 171:3a7713b1edbc 2212 * Offset: 0x0C APB Devices Clock Enable Control Register 1
AnnaBridge 171:3a7713b1edbc 2213 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2214 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2215 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2216 * |[0] |SC0CKEN |SC0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2217 * | | |0 = SC0 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2218 * | | |1 = SC0 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2219 * |[12] |DACCKEN |DAC Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2220 * | | |0 = DAC Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2221 * | | |1 = DAC Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2222 * |[16] |PWM0CKEN |PWM0 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2223 * | | |0 = PWM0 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2224 * | | |1 = PWM0 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2225 * |[17] |PWM1CKEN |PWM1 Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2226 * | | |0 = PWM1 Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2227 * | | |1 = PWM1 Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2228 * |[25] |TKCKEN |Touch Key Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 2229 * | | |0 = Touch Key Clock Disabled.
AnnaBridge 171:3a7713b1edbc 2230 * | | |1 = Touch key Clock Enabled.
AnnaBridge 171:3a7713b1edbc 2231 * @var CLK_T::CLKSEL0
AnnaBridge 171:3a7713b1edbc 2232 * Offset: 0x10 Clock Source Select Control Register 0
AnnaBridge 171:3a7713b1edbc 2233 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2234 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2235 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2236 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2237 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
AnnaBridge 171:3a7713b1edbc 2238 * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
AnnaBridge 171:3a7713b1edbc 2239 * | | |Therefore the default value is either 000b or 111b.
AnnaBridge 171:3a7713b1edbc 2240 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2241 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2242 * | | |010 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2243 * | | |011 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2244 * | | |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2245 * | | |Other = Reserved.
AnnaBridge 171:3a7713b1edbc 2246 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2247 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2248 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
AnnaBridge 171:3a7713b1edbc 2249 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2250 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2251 * | | |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
AnnaBridge 171:3a7713b1edbc 2252 * | | |011 = Clock source from HCLK/2.
AnnaBridge 171:3a7713b1edbc 2253 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
AnnaBridge 171:3a7713b1edbc 2254 * | | |Note: if SysTick clock source is not from HCLK (i.e.
AnnaBridge 171:3a7713b1edbc 2255 * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
AnnaBridge 171:3a7713b1edbc 2256 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2257 * |[6] |PCLK0SEL |PCLK0 Clock Source Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2258 * | | |0 = APB0 BUS clock source from HCLK.
AnnaBridge 171:3a7713b1edbc 2259 * | | |1 = APB0 BUS clock source from HCLK/2.
AnnaBridge 171:3a7713b1edbc 2260 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2261 * |[7] |PCLK1SEL |PCLK1 Clock Source Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2262 * | | |0 = APB1 BUS clock source from HCLK.
AnnaBridge 171:3a7713b1edbc 2263 * | | |1 = APB1 BUS clock source from HCLK/2.
AnnaBridge 171:3a7713b1edbc 2264 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 2265 * @var CLK_T::CLKSEL1
AnnaBridge 171:3a7713b1edbc 2266 * Offset: 0x14 Clock Source Select Control Register 1
AnnaBridge 171:3a7713b1edbc 2267 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2268 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2269 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2270 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2271 * | | |00 = Reserved.
AnnaBridge 171:3a7713b1edbc 2272 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2273 * | | |10 = Clock source from PCLK0/2048 clock.
AnnaBridge 171:3a7713b1edbc 2274 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2275 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2276 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2277 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2278 * | | |010 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2279 * | | |011 = Clock source from external clock T0 pin
AnnaBridge 171:3a7713b1edbc 2280 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2281 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2282 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 2283 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2284 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2285 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2286 * | | |010 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2287 * | | |011 = Clock source from external clock T1 pin
AnnaBridge 171:3a7713b1edbc 2288 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2289 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2290 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 2291 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2292 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2293 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2294 * | | |010 = Clock source from PCLK1.
AnnaBridge 171:3a7713b1edbc 2295 * | | |011 = Clock source from external clock T2 pin
AnnaBridge 171:3a7713b1edbc 2296 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2297 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2298 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 2299 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2300 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2301 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2302 * | | |010 = Clock source from PCLK1.
AnnaBridge 171:3a7713b1edbc 2303 * | | |011 = Clock source from external clock T3 pin.
AnnaBridge 171:3a7713b1edbc 2304 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2305 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2306 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 2307 * |[25:24] |UARTSEL |UART Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2308 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
AnnaBridge 171:3a7713b1edbc 2309 * | | |01 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2310 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
AnnaBridge 171:3a7713b1edbc 2311 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
AnnaBridge 171:3a7713b1edbc 2312 * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2313 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2314 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2315 * | | |10 = Clock source from HCLK.
AnnaBridge 171:3a7713b1edbc 2316 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2317 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2318 * | | |10 = Clock source from PCLK0/2048 clock.
AnnaBridge 171:3a7713b1edbc 2319 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2320 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 2321 * @var CLK_T::CLKSEL2
AnnaBridge 171:3a7713b1edbc 2322 * Offset: 0x18 Clock Source Select Control Register 2
AnnaBridge 171:3a7713b1edbc 2323 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2324 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2325 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2326 * |[0] |PWM0SEL |PWM0 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2327 * | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
AnnaBridge 171:3a7713b1edbc 2328 * | | |0 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2329 * | | |1 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2330 * |[1] |PWM1SEL |PWM1 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2331 * | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
AnnaBridge 171:3a7713b1edbc 2332 * | | |0 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2333 * | | |1 = Clock source from PCLK1.
AnnaBridge 171:3a7713b1edbc 2334 * |[3:2] |SPI0SEL |SPI0 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2335 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
AnnaBridge 171:3a7713b1edbc 2336 * | | |01 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2337 * | | |10 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2338 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2339 * |[5:4] |SPI1SEL |SPI1 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2340 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
AnnaBridge 171:3a7713b1edbc 2341 * | | |01 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2342 * | | |10 = Clock source from PCLK1.
AnnaBridge 171:3a7713b1edbc 2343 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2344 * |[7:6] |SPI2SEL |SPI2 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2345 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
AnnaBridge 171:3a7713b1edbc 2346 * | | |01 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2347 * | | |10 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2348 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2349 * @var CLK_T::CLKSEL3
AnnaBridge 171:3a7713b1edbc 2350 * Offset: 0x1C Clock Source Select Control Register 3
AnnaBridge 171:3a7713b1edbc 2351 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2352 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2353 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2354 * |[1:0] |SC0SEL |SC0 Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2355 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
AnnaBridge 171:3a7713b1edbc 2356 * | | |01 = Clock source from PLL clock.
AnnaBridge 171:3a7713b1edbc 2357 * | | |10 = Clock source from PCLK0.
AnnaBridge 171:3a7713b1edbc 2358 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
AnnaBridge 171:3a7713b1edbc 2359 * |[8] |RTCSEL |RTC Clock Source Selection
AnnaBridge 171:3a7713b1edbc 2360 * | | |0 = Clock source from external 32.768 kHz low-speed oscillator.
AnnaBridge 171:3a7713b1edbc 2361 * | | |1 = Clock source from internal 10 kHz low speed RC oscillator.
AnnaBridge 171:3a7713b1edbc 2362 * @var CLK_T::CLKDIV0
AnnaBridge 171:3a7713b1edbc 2363 * Offset: 0x20 Clock Divider Number Register 0
AnnaBridge 171:3a7713b1edbc 2364 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2365 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2366 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2367 * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
AnnaBridge 171:3a7713b1edbc 2368 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
AnnaBridge 171:3a7713b1edbc 2369 * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
AnnaBridge 171:3a7713b1edbc 2370 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
AnnaBridge 171:3a7713b1edbc 2371 * |[11:8] |UARTDIV |UART Clock Divide Number From UART Clock Source
AnnaBridge 171:3a7713b1edbc 2372 * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
AnnaBridge 171:3a7713b1edbc 2373 * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
AnnaBridge 171:3a7713b1edbc 2374 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
AnnaBridge 171:3a7713b1edbc 2375 * @var CLK_T::CLKDIV1
AnnaBridge 171:3a7713b1edbc 2376 * Offset: 0x24 Clock Divider Number Register 1
AnnaBridge 171:3a7713b1edbc 2377 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2378 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2379 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2380 * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
AnnaBridge 171:3a7713b1edbc 2381 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
AnnaBridge 171:3a7713b1edbc 2382 * @var CLK_T::PLLCTL
AnnaBridge 171:3a7713b1edbc 2383 * Offset: 0x40 PLL Control Register
AnnaBridge 171:3a7713b1edbc 2384 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2385 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2386 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2387 * |[8:0] |FBDIV |PLL Feedback Divider Control Pins (Write Protect)
AnnaBridge 171:3a7713b1edbc 2388 * | | |Refer to the formulas below the table.
AnnaBridge 171:3a7713b1edbc 2389 * |[13:9] |INDIV |PLL Input Divider Control Pins (Write Protect)
AnnaBridge 171:3a7713b1edbc 2390 * | | |Refer to the formulas below the table.
AnnaBridge 171:3a7713b1edbc 2391 * |[15:14] |OUTDIV |PLL Output Divider Control Pins (Write Protect)
AnnaBridge 171:3a7713b1edbc 2392 * | | |Refer to the formulas below the table.
AnnaBridge 171:3a7713b1edbc 2393 * |[16] |PD |Power-Down Mode (Write Protect)
AnnaBridge 171:3a7713b1edbc 2394 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
AnnaBridge 171:3a7713b1edbc 2395 * | | |0 = PLL is in normal mode.
AnnaBridge 171:3a7713b1edbc 2396 * | | |1 = PLL is in Power-down mode (default).
AnnaBridge 171:3a7713b1edbc 2397 * |[17] |BP |PLL Bypass Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 2398 * | | |0 = PLL is in normal mode (default).
AnnaBridge 171:3a7713b1edbc 2399 * | | |1 = PLL clock output is same as PLL input clock FIN.
AnnaBridge 171:3a7713b1edbc 2400 * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 2401 * | | |0 = PLL FOUT Enabled.
AnnaBridge 171:3a7713b1edbc 2402 * | | |1 = PLL FOUT is fixed low.
AnnaBridge 171:3a7713b1edbc 2403 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2404 * | | |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
AnnaBridge 171:3a7713b1edbc 2405 * | | |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
AnnaBridge 171:3a7713b1edbc 2406 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 2407 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
AnnaBridge 171:3a7713b1edbc 2408 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
AnnaBridge 171:3a7713b1edbc 2409 * @var CLK_T::STATUS
AnnaBridge 171:3a7713b1edbc 2410 * Offset: 0x50 Clock Status Monitor Register
AnnaBridge 171:3a7713b1edbc 2411 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2412 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2413 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2414 * |[0] |HXTSTB |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2415 * | | |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
AnnaBridge 171:3a7713b1edbc 2416 * | | |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
AnnaBridge 171:3a7713b1edbc 2417 * |[1] |LXTSTB |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2418 * | | |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
AnnaBridge 171:3a7713b1edbc 2419 * | | |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
AnnaBridge 171:3a7713b1edbc 2420 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2421 * | | |0 = Internal PLL clock is not stable or disabled.
AnnaBridge 171:3a7713b1edbc 2422 * | | |1 = Internal PLL clock is stable and enabled.
AnnaBridge 171:3a7713b1edbc 2423 * |[3] |LIRCSTB |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2424 * | | |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
AnnaBridge 171:3a7713b1edbc 2425 * | | |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
AnnaBridge 171:3a7713b1edbc 2426 * |[4] |HIRCSTB |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2427 * | | |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
AnnaBridge 171:3a7713b1edbc 2428 * | | |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
AnnaBridge 171:3a7713b1edbc 2429 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 2430 * | | |This bit is updated when software switches system clock source.
AnnaBridge 171:3a7713b1edbc 2431 * | | |If switch target clock is stable, this bit will be set to 0.
AnnaBridge 171:3a7713b1edbc 2432 * | | |If switch target clock is not stable, this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 2433 * | | |0 = Clock switching success.
AnnaBridge 171:3a7713b1edbc 2434 * | | |1 = Clock switching failure.
AnnaBridge 171:3a7713b1edbc 2435 * | | |Note: Write 1 to clear the bit to 0.
AnnaBridge 171:3a7713b1edbc 2436 * @var CLK_T::CLKOCTL
AnnaBridge 171:3a7713b1edbc 2437 * Offset: 0x60 Clock Output Control Register
AnnaBridge 171:3a7713b1edbc 2438 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2439 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2440 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2441 * |[3:0] |FREQSEL |Clock Output Frequency Selection
AnnaBridge 171:3a7713b1edbc 2442 * | | |The formula of output frequency is
AnnaBridge 171:3a7713b1edbc 2443 * | | |Fout = Fin/2(N+1).
AnnaBridge 171:3a7713b1edbc 2444 * | | |Fin is the input clock frequency.
AnnaBridge 171:3a7713b1edbc 2445 * | | |Fout is the frequency of divider output clock.
AnnaBridge 171:3a7713b1edbc 2446 * | | |N is the 4-bit value of FREQSEL[3:0].
AnnaBridge 171:3a7713b1edbc 2447 * |[4] |CLKOEN |Clock Output Enable Bit
AnnaBridge 171:3a7713b1edbc 2448 * | | |0 =Clock Output function Disabled.
AnnaBridge 171:3a7713b1edbc 2449 * | | |1 = Clock Output function Enabled.
AnnaBridge 171:3a7713b1edbc 2450 * |[5] |DIV1EN |Clock Output Divide One Enable Bit
AnnaBridge 171:3a7713b1edbc 2451 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
AnnaBridge 171:3a7713b1edbc 2452 * | | |1 = Clock Output will output clock with source frequency.
AnnaBridge 171:3a7713b1edbc 2453 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
AnnaBridge 171:3a7713b1edbc 2454 * | | |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
AnnaBridge 171:3a7713b1edbc 2455 * | | |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
AnnaBridge 171:3a7713b1edbc 2456 * @var CLK_T::CLKDCTL
AnnaBridge 171:3a7713b1edbc 2457 * Offset: 0x70 Clock Fail Detector Control Register
AnnaBridge 171:3a7713b1edbc 2458 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2459 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2460 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2461 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
AnnaBridge 171:3a7713b1edbc 2462 * | | |0 = HXT clock Fail detector Disabled.
AnnaBridge 171:3a7713b1edbc 2463 * | | |1 = HXT clock Fail detector Enabled.
AnnaBridge 171:3a7713b1edbc 2464 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 2465 * | | |0 = HXT clock Fail interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 2466 * | | |1 = HXT clock Fail interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 2467 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
AnnaBridge 171:3a7713b1edbc 2468 * | | |0 = LXT clock Fail detector Disabled.
AnnaBridge 171:3a7713b1edbc 2469 * | | |1 = LXT clock Fail detector Enabled.
AnnaBridge 171:3a7713b1edbc 2470 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 2471 * | | |0 = LXT clock Fail interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 2472 * | | |1 = LXT clock Fail interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 2473 * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit
AnnaBridge 171:3a7713b1edbc 2474 * | | |0 = HXT clock frequency monitor Disabled.
AnnaBridge 171:3a7713b1edbc 2475 * | | |1 = HXT clock frequency monitor Enabled.
AnnaBridge 171:3a7713b1edbc 2476 * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 2477 * | | |0 = HXT clock frequency monitor fail interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 2478 * | | |1 = HXT clock frequency monitor fail interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 2479 * @var CLK_T::CLKDSTS
AnnaBridge 171:3a7713b1edbc 2480 * Offset: 0x74 Clock Fail Detector Status Register
AnnaBridge 171:3a7713b1edbc 2481 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2482 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2483 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2484 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
AnnaBridge 171:3a7713b1edbc 2485 * | | |0 = HXT clock normal.
AnnaBridge 171:3a7713b1edbc 2486 * | | |1 = HXT clock stop
AnnaBridge 171:3a7713b1edbc 2487 * | | |Note: Write 1 to clear the bit to 0.
AnnaBridge 171:3a7713b1edbc 2488 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
AnnaBridge 171:3a7713b1edbc 2489 * | | |0 = LXT clock normal.
AnnaBridge 171:3a7713b1edbc 2490 * | | |1 = LXT stop
AnnaBridge 171:3a7713b1edbc 2491 * | | |Note: Write 1 to clear the bit to 0.
AnnaBridge 171:3a7713b1edbc 2492 * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag
AnnaBridge 171:3a7713b1edbc 2493 * | | |0 = HXT clock normal.
AnnaBridge 171:3a7713b1edbc 2494 * | | |1 = HXT clock frequency abnormal
AnnaBridge 171:3a7713b1edbc 2495 * | | |Note: Write 1 to clear the bit to 0.
AnnaBridge 171:3a7713b1edbc 2496 * @var CLK_T::CDUPB
AnnaBridge 171:3a7713b1edbc 2497 * Offset: 0x78 Clock Frequency Detector Upper Boundary Register
AnnaBridge 171:3a7713b1edbc 2498 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2499 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2500 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2501 * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary
AnnaBridge 171:3a7713b1edbc 2502 * | | |The bits define the high value of frequency monitor window.
AnnaBridge 171:3a7713b1edbc 2503 * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
AnnaBridge 171:3a7713b1edbc 2504 * @var CLK_T::CDLOWB
AnnaBridge 171:3a7713b1edbc 2505 * Offset: 0x7C Clock Frequency Detector Low Boundary Register
AnnaBridge 171:3a7713b1edbc 2506 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2507 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2508 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2509 * |[9:0] |LOWERBD |HXT Clock Frequency Detector Low Boundary
AnnaBridge 171:3a7713b1edbc 2510 * | | |The bits define the low value of frequency monitor window.
AnnaBridge 171:3a7713b1edbc 2511 * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
AnnaBridge 171:3a7713b1edbc 2512 */
AnnaBridge 171:3a7713b1edbc 2513
AnnaBridge 171:3a7713b1edbc 2514 __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
AnnaBridge 171:3a7713b1edbc 2515 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
AnnaBridge 171:3a7713b1edbc 2516 __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
AnnaBridge 171:3a7713b1edbc 2517 __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
AnnaBridge 171:3a7713b1edbc 2518 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
AnnaBridge 171:3a7713b1edbc 2519 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
AnnaBridge 171:3a7713b1edbc 2520 __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
AnnaBridge 171:3a7713b1edbc 2521 __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
AnnaBridge 171:3a7713b1edbc 2522 __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
AnnaBridge 171:3a7713b1edbc 2523 __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
AnnaBridge 171:3a7713b1edbc 2524 __I uint32_t RESERVE0[6];
AnnaBridge 171:3a7713b1edbc 2525 __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
AnnaBridge 171:3a7713b1edbc 2526 __I uint32_t RESERVE1[3];
AnnaBridge 171:3a7713b1edbc 2527 __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
AnnaBridge 171:3a7713b1edbc 2528 __I uint32_t RESERVE2[3];
AnnaBridge 171:3a7713b1edbc 2529 __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
AnnaBridge 171:3a7713b1edbc 2530 __I uint32_t RESERVE3[3];
AnnaBridge 171:3a7713b1edbc 2531 __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
AnnaBridge 171:3a7713b1edbc 2532 __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
AnnaBridge 171:3a7713b1edbc 2533 __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
AnnaBridge 171:3a7713b1edbc 2534 __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
AnnaBridge 171:3a7713b1edbc 2535
AnnaBridge 171:3a7713b1edbc 2536 } CLK_T;
AnnaBridge 171:3a7713b1edbc 2537
AnnaBridge 171:3a7713b1edbc 2538
AnnaBridge 171:3a7713b1edbc 2539
AnnaBridge 171:3a7713b1edbc 2540 /**
AnnaBridge 171:3a7713b1edbc 2541 @addtogroup CLK_CONST CLK Bit Field Definition
AnnaBridge 171:3a7713b1edbc 2542 Constant Definitions for CLK Controller
AnnaBridge 171:3a7713b1edbc 2543 @{ */
AnnaBridge 171:3a7713b1edbc 2544
AnnaBridge 171:3a7713b1edbc 2545 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
AnnaBridge 171:3a7713b1edbc 2546 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
AnnaBridge 171:3a7713b1edbc 2547
AnnaBridge 171:3a7713b1edbc 2548 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
AnnaBridge 171:3a7713b1edbc 2549 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
AnnaBridge 171:3a7713b1edbc 2550
AnnaBridge 171:3a7713b1edbc 2551 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
AnnaBridge 171:3a7713b1edbc 2552 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
AnnaBridge 171:3a7713b1edbc 2553
AnnaBridge 171:3a7713b1edbc 2554 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
AnnaBridge 171:3a7713b1edbc 2555 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
AnnaBridge 171:3a7713b1edbc 2556
AnnaBridge 171:3a7713b1edbc 2557 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
AnnaBridge 171:3a7713b1edbc 2558 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
AnnaBridge 171:3a7713b1edbc 2559
AnnaBridge 171:3a7713b1edbc 2560 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
AnnaBridge 171:3a7713b1edbc 2561 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
AnnaBridge 171:3a7713b1edbc 2562
AnnaBridge 171:3a7713b1edbc 2563 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
AnnaBridge 171:3a7713b1edbc 2564 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
AnnaBridge 171:3a7713b1edbc 2565
AnnaBridge 171:3a7713b1edbc 2566 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
AnnaBridge 171:3a7713b1edbc 2567 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
AnnaBridge 171:3a7713b1edbc 2568
AnnaBridge 171:3a7713b1edbc 2569 #define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK_T::PWRCTL: PDWTCPU Position */
AnnaBridge 171:3a7713b1edbc 2570 #define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK_T::PWRCTL: PDWTCPU Mask */
AnnaBridge 171:3a7713b1edbc 2571
AnnaBridge 171:3a7713b1edbc 2572 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
AnnaBridge 171:3a7713b1edbc 2573 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
AnnaBridge 171:3a7713b1edbc 2574
AnnaBridge 171:3a7713b1edbc 2575 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
AnnaBridge 171:3a7713b1edbc 2576 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
AnnaBridge 171:3a7713b1edbc 2577
AnnaBridge 171:3a7713b1edbc 2578 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
AnnaBridge 171:3a7713b1edbc 2579 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
AnnaBridge 171:3a7713b1edbc 2580
AnnaBridge 171:3a7713b1edbc 2581 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
AnnaBridge 171:3a7713b1edbc 2582 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2583
AnnaBridge 171:3a7713b1edbc 2584 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
AnnaBridge 171:3a7713b1edbc 2585 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
AnnaBridge 171:3a7713b1edbc 2586
AnnaBridge 171:3a7713b1edbc 2587 #define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK_T::AHBCLK: USBHCKEN Position */
AnnaBridge 171:3a7713b1edbc 2588 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2589
AnnaBridge 171:3a7713b1edbc 2590 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
AnnaBridge 171:3a7713b1edbc 2591 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2592
AnnaBridge 171:3a7713b1edbc 2593 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
AnnaBridge 171:3a7713b1edbc 2594 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
AnnaBridge 171:3a7713b1edbc 2595
AnnaBridge 171:3a7713b1edbc 2596 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
AnnaBridge 171:3a7713b1edbc 2597 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2598
AnnaBridge 171:3a7713b1edbc 2599 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
AnnaBridge 171:3a7713b1edbc 2600 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2601
AnnaBridge 171:3a7713b1edbc 2602 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2603 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2604
AnnaBridge 171:3a7713b1edbc 2605 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
AnnaBridge 171:3a7713b1edbc 2606 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2607
AnnaBridge 171:3a7713b1edbc 2608 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
AnnaBridge 171:3a7713b1edbc 2609 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2610
AnnaBridge 171:3a7713b1edbc 2611 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
AnnaBridge 171:3a7713b1edbc 2612 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2613
AnnaBridge 171:3a7713b1edbc 2614 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
AnnaBridge 171:3a7713b1edbc 2615 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2616
AnnaBridge 171:3a7713b1edbc 2617 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
AnnaBridge 171:3a7713b1edbc 2618 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2619
AnnaBridge 171:3a7713b1edbc 2620 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2621 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2622
AnnaBridge 171:3a7713b1edbc 2623 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
AnnaBridge 171:3a7713b1edbc 2624 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2625
AnnaBridge 171:3a7713b1edbc 2626 #define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2627 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2628
AnnaBridge 171:3a7713b1edbc 2629 #define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
AnnaBridge 171:3a7713b1edbc 2630 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2631
AnnaBridge 171:3a7713b1edbc 2632 #define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
AnnaBridge 171:3a7713b1edbc 2633 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2634
AnnaBridge 171:3a7713b1edbc 2635 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2636 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2637
AnnaBridge 171:3a7713b1edbc 2638 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
AnnaBridge 171:3a7713b1edbc 2639 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2640
AnnaBridge 171:3a7713b1edbc 2641 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
AnnaBridge 171:3a7713b1edbc 2642 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2643
AnnaBridge 171:3a7713b1edbc 2644 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
AnnaBridge 171:3a7713b1edbc 2645 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2646
AnnaBridge 171:3a7713b1edbc 2647 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2648 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2649
AnnaBridge 171:3a7713b1edbc 2650 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
AnnaBridge 171:3a7713b1edbc 2651 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2652
AnnaBridge 171:3a7713b1edbc 2653 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
AnnaBridge 171:3a7713b1edbc 2654 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2655
AnnaBridge 171:3a7713b1edbc 2656 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
AnnaBridge 171:3a7713b1edbc 2657 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2658
AnnaBridge 171:3a7713b1edbc 2659 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2660 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2661
AnnaBridge 171:3a7713b1edbc 2662 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
AnnaBridge 171:3a7713b1edbc 2663 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2664
AnnaBridge 171:3a7713b1edbc 2665 #define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
AnnaBridge 171:3a7713b1edbc 2666 #define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2667
AnnaBridge 171:3a7713b1edbc 2668 #define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
AnnaBridge 171:3a7713b1edbc 2669 #define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
AnnaBridge 171:3a7713b1edbc 2670
AnnaBridge 171:3a7713b1edbc 2671 #define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */
AnnaBridge 171:3a7713b1edbc 2672 #define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */
AnnaBridge 171:3a7713b1edbc 2673
AnnaBridge 171:3a7713b1edbc 2674 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
AnnaBridge 171:3a7713b1edbc 2675 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
AnnaBridge 171:3a7713b1edbc 2676
AnnaBridge 171:3a7713b1edbc 2677 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
AnnaBridge 171:3a7713b1edbc 2678 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
AnnaBridge 171:3a7713b1edbc 2679
AnnaBridge 171:3a7713b1edbc 2680 #define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
AnnaBridge 171:3a7713b1edbc 2681 #define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
AnnaBridge 171:3a7713b1edbc 2682
AnnaBridge 171:3a7713b1edbc 2683 #define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
AnnaBridge 171:3a7713b1edbc 2684 #define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
AnnaBridge 171:3a7713b1edbc 2685
AnnaBridge 171:3a7713b1edbc 2686 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
AnnaBridge 171:3a7713b1edbc 2687 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
AnnaBridge 171:3a7713b1edbc 2688
AnnaBridge 171:3a7713b1edbc 2689 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
AnnaBridge 171:3a7713b1edbc 2690 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
AnnaBridge 171:3a7713b1edbc 2691
AnnaBridge 171:3a7713b1edbc 2692 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
AnnaBridge 171:3a7713b1edbc 2693 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
AnnaBridge 171:3a7713b1edbc 2694
AnnaBridge 171:3a7713b1edbc 2695 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
AnnaBridge 171:3a7713b1edbc 2696 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
AnnaBridge 171:3a7713b1edbc 2697
AnnaBridge 171:3a7713b1edbc 2698 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
AnnaBridge 171:3a7713b1edbc 2699 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
AnnaBridge 171:3a7713b1edbc 2700
AnnaBridge 171:3a7713b1edbc 2701 #define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK_T::CLKSEL1: UARTSEL Position */
AnnaBridge 171:3a7713b1edbc 2702 #define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK_T::CLKSEL1: UARTSEL Mask */
AnnaBridge 171:3a7713b1edbc 2703
AnnaBridge 171:3a7713b1edbc 2704 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
AnnaBridge 171:3a7713b1edbc 2705 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
AnnaBridge 171:3a7713b1edbc 2706
AnnaBridge 171:3a7713b1edbc 2707 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
AnnaBridge 171:3a7713b1edbc 2708 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
AnnaBridge 171:3a7713b1edbc 2709
AnnaBridge 171:3a7713b1edbc 2710 #define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
AnnaBridge 171:3a7713b1edbc 2711 #define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
AnnaBridge 171:3a7713b1edbc 2712
AnnaBridge 171:3a7713b1edbc 2713 #define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
AnnaBridge 171:3a7713b1edbc 2714 #define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
AnnaBridge 171:3a7713b1edbc 2715
AnnaBridge 171:3a7713b1edbc 2716 #define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
AnnaBridge 171:3a7713b1edbc 2717 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
AnnaBridge 171:3a7713b1edbc 2718
AnnaBridge 171:3a7713b1edbc 2719 #define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
AnnaBridge 171:3a7713b1edbc 2720 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
AnnaBridge 171:3a7713b1edbc 2721
AnnaBridge 171:3a7713b1edbc 2722 #define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
AnnaBridge 171:3a7713b1edbc 2723 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
AnnaBridge 171:3a7713b1edbc 2724
AnnaBridge 171:3a7713b1edbc 2725 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
AnnaBridge 171:3a7713b1edbc 2726 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
AnnaBridge 171:3a7713b1edbc 2727
AnnaBridge 171:3a7713b1edbc 2728 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
AnnaBridge 171:3a7713b1edbc 2729 #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
AnnaBridge 171:3a7713b1edbc 2730
AnnaBridge 171:3a7713b1edbc 2731 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
AnnaBridge 171:3a7713b1edbc 2732 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
AnnaBridge 171:3a7713b1edbc 2733
AnnaBridge 171:3a7713b1edbc 2734 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
AnnaBridge 171:3a7713b1edbc 2735 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
AnnaBridge 171:3a7713b1edbc 2736
AnnaBridge 171:3a7713b1edbc 2737 #define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK_T::CLKDIV0: UARTDIV Position */
AnnaBridge 171:3a7713b1edbc 2738 #define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK_T::CLKDIV0: UARTDIV Mask */
AnnaBridge 171:3a7713b1edbc 2739
AnnaBridge 171:3a7713b1edbc 2740 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
AnnaBridge 171:3a7713b1edbc 2741 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
AnnaBridge 171:3a7713b1edbc 2742
AnnaBridge 171:3a7713b1edbc 2743 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
AnnaBridge 171:3a7713b1edbc 2744 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
AnnaBridge 171:3a7713b1edbc 2745
AnnaBridge 171:3a7713b1edbc 2746 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
AnnaBridge 171:3a7713b1edbc 2747 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
AnnaBridge 171:3a7713b1edbc 2748
AnnaBridge 171:3a7713b1edbc 2749 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
AnnaBridge 171:3a7713b1edbc 2750 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
AnnaBridge 171:3a7713b1edbc 2751
AnnaBridge 171:3a7713b1edbc 2752 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
AnnaBridge 171:3a7713b1edbc 2753 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
AnnaBridge 171:3a7713b1edbc 2754
AnnaBridge 171:3a7713b1edbc 2755 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
AnnaBridge 171:3a7713b1edbc 2756 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
AnnaBridge 171:3a7713b1edbc 2757
AnnaBridge 171:3a7713b1edbc 2758 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
AnnaBridge 171:3a7713b1edbc 2759 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
AnnaBridge 171:3a7713b1edbc 2760
AnnaBridge 171:3a7713b1edbc 2761 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
AnnaBridge 171:3a7713b1edbc 2762 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
AnnaBridge 171:3a7713b1edbc 2763
AnnaBridge 171:3a7713b1edbc 2764 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
AnnaBridge 171:3a7713b1edbc 2765 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
AnnaBridge 171:3a7713b1edbc 2766
AnnaBridge 171:3a7713b1edbc 2767 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
AnnaBridge 171:3a7713b1edbc 2768 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
AnnaBridge 171:3a7713b1edbc 2769
AnnaBridge 171:3a7713b1edbc 2770 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
AnnaBridge 171:3a7713b1edbc 2771 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
AnnaBridge 171:3a7713b1edbc 2772
AnnaBridge 171:3a7713b1edbc 2773 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
AnnaBridge 171:3a7713b1edbc 2774 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
AnnaBridge 171:3a7713b1edbc 2775
AnnaBridge 171:3a7713b1edbc 2776 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
AnnaBridge 171:3a7713b1edbc 2777 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
AnnaBridge 171:3a7713b1edbc 2778
AnnaBridge 171:3a7713b1edbc 2779 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
AnnaBridge 171:3a7713b1edbc 2780 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
AnnaBridge 171:3a7713b1edbc 2781
AnnaBridge 171:3a7713b1edbc 2782 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
AnnaBridge 171:3a7713b1edbc 2783 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
AnnaBridge 171:3a7713b1edbc 2784
AnnaBridge 171:3a7713b1edbc 2785 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
AnnaBridge 171:3a7713b1edbc 2786 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
AnnaBridge 171:3a7713b1edbc 2787
AnnaBridge 171:3a7713b1edbc 2788 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
AnnaBridge 171:3a7713b1edbc 2789 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
AnnaBridge 171:3a7713b1edbc 2790
AnnaBridge 171:3a7713b1edbc 2791 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
AnnaBridge 171:3a7713b1edbc 2792 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
AnnaBridge 171:3a7713b1edbc 2793
AnnaBridge 171:3a7713b1edbc 2794 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
AnnaBridge 171:3a7713b1edbc 2795 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
AnnaBridge 171:3a7713b1edbc 2796
AnnaBridge 171:3a7713b1edbc 2797 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
AnnaBridge 171:3a7713b1edbc 2798 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
AnnaBridge 171:3a7713b1edbc 2799
AnnaBridge 171:3a7713b1edbc 2800 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
AnnaBridge 171:3a7713b1edbc 2801 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
AnnaBridge 171:3a7713b1edbc 2802
AnnaBridge 171:3a7713b1edbc 2803 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
AnnaBridge 171:3a7713b1edbc 2804 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
AnnaBridge 171:3a7713b1edbc 2805
AnnaBridge 171:3a7713b1edbc 2806 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
AnnaBridge 171:3a7713b1edbc 2807 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
AnnaBridge 171:3a7713b1edbc 2808
AnnaBridge 171:3a7713b1edbc 2809 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
AnnaBridge 171:3a7713b1edbc 2810 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
AnnaBridge 171:3a7713b1edbc 2811
AnnaBridge 171:3a7713b1edbc 2812 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
AnnaBridge 171:3a7713b1edbc 2813 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
AnnaBridge 171:3a7713b1edbc 2814
AnnaBridge 171:3a7713b1edbc 2815 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
AnnaBridge 171:3a7713b1edbc 2816 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
AnnaBridge 171:3a7713b1edbc 2817
AnnaBridge 171:3a7713b1edbc 2818 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
AnnaBridge 171:3a7713b1edbc 2819 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
AnnaBridge 171:3a7713b1edbc 2820
AnnaBridge 171:3a7713b1edbc 2821 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
AnnaBridge 171:3a7713b1edbc 2822 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
AnnaBridge 171:3a7713b1edbc 2823
AnnaBridge 171:3a7713b1edbc 2824 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
AnnaBridge 171:3a7713b1edbc 2825 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
AnnaBridge 171:3a7713b1edbc 2826
AnnaBridge 171:3a7713b1edbc 2827 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
AnnaBridge 171:3a7713b1edbc 2828 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
AnnaBridge 171:3a7713b1edbc 2829
AnnaBridge 171:3a7713b1edbc 2830 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
AnnaBridge 171:3a7713b1edbc 2831 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
AnnaBridge 171:3a7713b1edbc 2832
AnnaBridge 171:3a7713b1edbc 2833
AnnaBridge 171:3a7713b1edbc 2834 /**@}*/ /* CLK_CONST */
AnnaBridge 171:3a7713b1edbc 2835 /**@}*/ /* end of CLK register group */
AnnaBridge 171:3a7713b1edbc 2836
AnnaBridge 171:3a7713b1edbc 2837
AnnaBridge 171:3a7713b1edbc 2838
AnnaBridge 171:3a7713b1edbc 2839 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 2840 /**
AnnaBridge 171:3a7713b1edbc 2841 @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
AnnaBridge 171:3a7713b1edbc 2842 Memory Mapped Structure for CRC Controller
AnnaBridge 171:3a7713b1edbc 2843 @{ */
AnnaBridge 171:3a7713b1edbc 2844
AnnaBridge 171:3a7713b1edbc 2845
AnnaBridge 171:3a7713b1edbc 2846 typedef struct
AnnaBridge 171:3a7713b1edbc 2847 {
AnnaBridge 171:3a7713b1edbc 2848
AnnaBridge 171:3a7713b1edbc 2849
AnnaBridge 171:3a7713b1edbc 2850
AnnaBridge 171:3a7713b1edbc 2851
AnnaBridge 171:3a7713b1edbc 2852 /**
AnnaBridge 171:3a7713b1edbc 2853 * @var CRC_T::CTL
AnnaBridge 171:3a7713b1edbc 2854 * Offset: 0x00 CRC Control Register
AnnaBridge 171:3a7713b1edbc 2855 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2856 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2857 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2858 * |[0] |CRCEN |CRC Channel Enable Bit
AnnaBridge 171:3a7713b1edbc 2859 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 2860 * | | |1 = CRC operation Enabled.
AnnaBridge 171:3a7713b1edbc 2861 * |[1] |CRCRST |CRC Engine Reset
AnnaBridge 171:3a7713b1edbc 2862 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 2863 * | | |1 = Reset the internal CRC state machine and internal buffer.
AnnaBridge 171:3a7713b1edbc 2864 * | | |The others contents of CRC_CTL register will not be cleared.
AnnaBridge 171:3a7713b1edbc 2865 * | | |Note1: This bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 2866 * | | |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
AnnaBridge 171:3a7713b1edbc 2867 * |[24] |DATREV |Write Data Bit Order Reverse
AnnaBridge 171:3a7713b1edbc 2868 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
AnnaBridge 171:3a7713b1edbc 2869 * | | |0 = Bit order reversed for CRC write data in Disabled.
AnnaBridge 171:3a7713b1edbc 2870 * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
AnnaBridge 171:3a7713b1edbc 2871 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
AnnaBridge 171:3a7713b1edbc 2872 * |[25] |CHKSREV |Checksum Bit Order Reverse
AnnaBridge 171:3a7713b1edbc 2873 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
AnnaBridge 171:3a7713b1edbc 2874 * | | |0 = Bit order reverse for CRC checksum Disabled.
AnnaBridge 171:3a7713b1edbc 2875 * | | |1 = Bit order reverse for CRC checksum Enabled.
AnnaBridge 171:3a7713b1edbc 2876 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
AnnaBridge 171:3a7713b1edbc 2877 * |[26] |DATFMT |Write Data 1's Complement
AnnaBridge 171:3a7713b1edbc 2878 * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
AnnaBridge 171:3a7713b1edbc 2879 * | | |0 = 1's complement for CRC writes data in Disabled.
AnnaBridge 171:3a7713b1edbc 2880 * | | |1 = 1's complement for CRC writes data in Enabled.
AnnaBridge 171:3a7713b1edbc 2881 * |[27] |CHKSFMT |Checksum 1's Complement
AnnaBridge 171:3a7713b1edbc 2882 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
AnnaBridge 171:3a7713b1edbc 2883 * | | |0 = 1's complement for CRC checksum Disabled.
AnnaBridge 171:3a7713b1edbc 2884 * | | |1 = 1's complement for CRC checksum Enabled.
AnnaBridge 171:3a7713b1edbc 2885 * |[29:28] |DATLEN |CPU Write Data Length
AnnaBridge 171:3a7713b1edbc 2886 * | | |This field indicates the write data length.
AnnaBridge 171:3a7713b1edbc 2887 * | | |00 = Data length is 8-bit mode.
AnnaBridge 171:3a7713b1edbc 2888 * | | |01 = Data length is 16-bit mode.
AnnaBridge 171:3a7713b1edbc 2889 * | | |1x = Data length is 32-bit mode.
AnnaBridge 171:3a7713b1edbc 2890 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
AnnaBridge 171:3a7713b1edbc 2891 * |[31:30] |CRCMODE |CRC Polynomial Mode
AnnaBridge 171:3a7713b1edbc 2892 * | | |This field indicates the CRC operation polynomial mode.
AnnaBridge 171:3a7713b1edbc 2893 * | | |00 = CRC-CCITT Polynomial mode.
AnnaBridge 171:3a7713b1edbc 2894 * | | |01 = CRC-8 Polynomial mode.
AnnaBridge 171:3a7713b1edbc 2895 * | | |10 = CRC-16 Polynomial mode.
AnnaBridge 171:3a7713b1edbc 2896 * | | |11 = CRC-32 Polynomial mode.
AnnaBridge 171:3a7713b1edbc 2897 * @var CRC_T::DAT
AnnaBridge 171:3a7713b1edbc 2898 * Offset: 0x04 CRC Write Data Register
AnnaBridge 171:3a7713b1edbc 2899 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2900 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2901 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2902 * |[31:0] |DATA |CRC Write Data Bits
AnnaBridge 171:3a7713b1edbc 2903 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
AnnaBridge 171:3a7713b1edbc 2904 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
AnnaBridge 171:3a7713b1edbc 2905 * @var CRC_T::SEED
AnnaBridge 171:3a7713b1edbc 2906 * Offset: 0x08 CRC Seed Register
AnnaBridge 171:3a7713b1edbc 2907 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2908 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2909 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2910 * |[31:0] |SEED |CRC Seed Value
AnnaBridge 171:3a7713b1edbc 2911 * | | |This field indicates the CRC seed value.
AnnaBridge 171:3a7713b1edbc 2912 * @var CRC_T::CHECKSUM
AnnaBridge 171:3a7713b1edbc 2913 * Offset: 0x0C CRC Checksum Register
AnnaBridge 171:3a7713b1edbc 2914 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2915 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2916 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2917 * |[31:0] |CHECKSUM |CRC Checksum Results
AnnaBridge 171:3a7713b1edbc 2918 * | | |This field indicates the CRC checksum result.
AnnaBridge 171:3a7713b1edbc 2919 */
AnnaBridge 171:3a7713b1edbc 2920
AnnaBridge 171:3a7713b1edbc 2921 __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
AnnaBridge 171:3a7713b1edbc 2922 __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
AnnaBridge 171:3a7713b1edbc 2923 __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
AnnaBridge 171:3a7713b1edbc 2924 __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
AnnaBridge 171:3a7713b1edbc 2925
AnnaBridge 171:3a7713b1edbc 2926 } CRC_T;
AnnaBridge 171:3a7713b1edbc 2927
AnnaBridge 171:3a7713b1edbc 2928
AnnaBridge 171:3a7713b1edbc 2929
AnnaBridge 171:3a7713b1edbc 2930 /**
AnnaBridge 171:3a7713b1edbc 2931 @addtogroup CRC_CONST CRC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 2932 Constant Definitions for CRC Controller
AnnaBridge 171:3a7713b1edbc 2933 @{ */
AnnaBridge 171:3a7713b1edbc 2934
AnnaBridge 171:3a7713b1edbc 2935 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
AnnaBridge 171:3a7713b1edbc 2936 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
AnnaBridge 171:3a7713b1edbc 2937
AnnaBridge 171:3a7713b1edbc 2938 #define CRC_CTL_CRCRST_Pos (1) /*!< CRC_T::CTL: CRCRST Position */
AnnaBridge 171:3a7713b1edbc 2939 #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC_T::CTL: CRCRST Mask */
AnnaBridge 171:3a7713b1edbc 2940
AnnaBridge 171:3a7713b1edbc 2941 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
AnnaBridge 171:3a7713b1edbc 2942 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
AnnaBridge 171:3a7713b1edbc 2943
AnnaBridge 171:3a7713b1edbc 2944 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
AnnaBridge 171:3a7713b1edbc 2945 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
AnnaBridge 171:3a7713b1edbc 2946
AnnaBridge 171:3a7713b1edbc 2947 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
AnnaBridge 171:3a7713b1edbc 2948 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
AnnaBridge 171:3a7713b1edbc 2949
AnnaBridge 171:3a7713b1edbc 2950 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
AnnaBridge 171:3a7713b1edbc 2951 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
AnnaBridge 171:3a7713b1edbc 2952
AnnaBridge 171:3a7713b1edbc 2953 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
AnnaBridge 171:3a7713b1edbc 2954 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
AnnaBridge 171:3a7713b1edbc 2955
AnnaBridge 171:3a7713b1edbc 2956 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
AnnaBridge 171:3a7713b1edbc 2957 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
AnnaBridge 171:3a7713b1edbc 2958
AnnaBridge 171:3a7713b1edbc 2959 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
AnnaBridge 171:3a7713b1edbc 2960 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
AnnaBridge 171:3a7713b1edbc 2961
AnnaBridge 171:3a7713b1edbc 2962 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
AnnaBridge 171:3a7713b1edbc 2963 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
AnnaBridge 171:3a7713b1edbc 2964
AnnaBridge 171:3a7713b1edbc 2965 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
AnnaBridge 171:3a7713b1edbc 2966 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
AnnaBridge 171:3a7713b1edbc 2967
AnnaBridge 171:3a7713b1edbc 2968 /**@}*/ /* CRC_CONST */
AnnaBridge 171:3a7713b1edbc 2969 /**@}*/ /* end of CRC register group */
AnnaBridge 171:3a7713b1edbc 2970
AnnaBridge 171:3a7713b1edbc 2971
AnnaBridge 171:3a7713b1edbc 2972 /*---------------------- Digital to Analog Converter -------------------------*/
AnnaBridge 171:3a7713b1edbc 2973 /**
AnnaBridge 171:3a7713b1edbc 2974 @addtogroup DAC Digital to Analog Converter(DAC)
AnnaBridge 171:3a7713b1edbc 2975 Memory Mapped Structure for DAC Controller
AnnaBridge 171:3a7713b1edbc 2976 @{ */
AnnaBridge 171:3a7713b1edbc 2977
AnnaBridge 171:3a7713b1edbc 2978
AnnaBridge 171:3a7713b1edbc 2979 typedef struct
AnnaBridge 171:3a7713b1edbc 2980 {
AnnaBridge 171:3a7713b1edbc 2981
AnnaBridge 171:3a7713b1edbc 2982
AnnaBridge 171:3a7713b1edbc 2983
AnnaBridge 171:3a7713b1edbc 2984 /**
AnnaBridge 171:3a7713b1edbc 2985 * @var DAC_T::CTL
AnnaBridge 171:3a7713b1edbc 2986 * Offset: 0x00 DAC Control Register
AnnaBridge 171:3a7713b1edbc 2987 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2988 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 2989 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 2990 * |[0] |DACEN |DAC Enable Bit
AnnaBridge 171:3a7713b1edbc 2991 * | | |0 = DAC is Disabled.
AnnaBridge 171:3a7713b1edbc 2992 * | | |1 = DAC is Enabled.
AnnaBridge 171:3a7713b1edbc 2993 * |[1] |DACIEN |DAC Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 2994 * | | |0 = Interrupt is Disabled.
AnnaBridge 171:3a7713b1edbc 2995 * | | |1 = Interrupt is Enabled.
AnnaBridge 171:3a7713b1edbc 2996 * |[2] |DMAEN |DMA Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 2997 * | | |0 = DMA mode Disabled.
AnnaBridge 171:3a7713b1edbc 2998 * | | |1 = DMA mode Enabled.
AnnaBridge 171:3a7713b1edbc 2999 * |[3] |DMAURIEN |DMA Under-Run Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 3000 * | | |0 = DMA under run interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 3001 * | | |1 = DMA under run interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 3002 * |[4] |TRGEN |Trigger Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 3003 * | | |0 = DAC event trigger mode Disabled.
AnnaBridge 171:3a7713b1edbc 3004 * | | |1 = DAC event trigger mode Enabled.
AnnaBridge 171:3a7713b1edbc 3005 * |[7:5] |TRGSEL |Trigger Source Selection
AnnaBridge 171:3a7713b1edbc 3006 * | | |000 = Software trigger.
AnnaBridge 171:3a7713b1edbc 3007 * | | |001 = External pin STDAC trigger.
AnnaBridge 171:3a7713b1edbc 3008 * | | |010 = Timer 0 trigger.
AnnaBridge 171:3a7713b1edbc 3009 * | | |011 = Timer 1 trigger.
AnnaBridge 171:3a7713b1edbc 3010 * | | |100 = Timer 2 trigger.
AnnaBridge 171:3a7713b1edbc 3011 * | | |101 = Timer 3 trigger.
AnnaBridge 171:3a7713b1edbc 3012 * | | |110 = PWM0 trigger.
AnnaBridge 171:3a7713b1edbc 3013 * | | |111 = PWM1 trigger.
AnnaBridge 171:3a7713b1edbc 3014 * |[8] |BYPASS |Bypass Buffer Mode
AnnaBridge 171:3a7713b1edbc 3015 * | | |0 = Output voltage buffer Enabled.
AnnaBridge 171:3a7713b1edbc 3016 * | | |1 = Output voltage buffer Disabled.
AnnaBridge 171:3a7713b1edbc 3017 * |[10] |LALIGN |DAC Data Left-Aligned Enabled Control
AnnaBridge 171:3a7713b1edbc 3018 * | | |0 = Right alignment.
AnnaBridge 171:3a7713b1edbc 3019 * | | |1 = Left alignment.
AnnaBridge 171:3a7713b1edbc 3020 * |[13:12] |ETRGSEL |External Pin Trigger Selection
AnnaBridge 171:3a7713b1edbc 3021 * | | |00 = Low level trigger.
AnnaBridge 171:3a7713b1edbc 3022 * | | |01 = High level trigger.
AnnaBridge 171:3a7713b1edbc 3023 * | | |10 = Falling edge trigger.
AnnaBridge 171:3a7713b1edbc 3024 * | | |11 = Rising edge trigger.
AnnaBridge 171:3a7713b1edbc 3025 * @var DAC_T::SWTRG
AnnaBridge 171:3a7713b1edbc 3026 * Offset: 0x04 DAC Software Trigger Control Register
AnnaBridge 171:3a7713b1edbc 3027 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3028 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3029 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3030 * |[0] |SWTRG |Software Trigger
AnnaBridge 171:3a7713b1edbc 3031 * | | |0 = Software trigger Disabled.
AnnaBridge 171:3a7713b1edbc 3032 * | | |1 = Software trigger Enabled.
AnnaBridge 171:3a7713b1edbc 3033 * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
AnnaBridge 171:3a7713b1edbc 3034 * @var DAC_T::DAT
AnnaBridge 171:3a7713b1edbc 3035 * Offset: 0x08 DAC Data Holding Register
AnnaBridge 171:3a7713b1edbc 3036 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3037 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3038 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3039 * |[15:0] |DAC_DAT |DAC 12-Bit Holding Data
AnnaBridge 171:3a7713b1edbc 3040 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
AnnaBridge 171:3a7713b1edbc 3041 * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
AnnaBridge 171:3a7713b1edbc 3042 * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
AnnaBridge 171:3a7713b1edbc 3043 * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
AnnaBridge 171:3a7713b1edbc 3044 * @var DAC_T::DATOUT
AnnaBridge 171:3a7713b1edbc 3045 * Offset: 0x0C DAC Data Output Register
AnnaBridge 171:3a7713b1edbc 3046 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3047 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3048 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3049 * |[11:0] |DATOUT |DAC 12-Bit Output Data
AnnaBridge 171:3a7713b1edbc 3050 * | | |These bits are current digital data for DAC output conversion.
AnnaBridge 171:3a7713b1edbc 3051 * | | |It is loaded from DAC_DAT register and user cannot write it directly.
AnnaBridge 171:3a7713b1edbc 3052 * @var DAC_T::STATUS
AnnaBridge 171:3a7713b1edbc 3053 * Offset: 0x10 DAC Status Register
AnnaBridge 171:3a7713b1edbc 3054 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3055 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3056 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3057 * |[0] |FINISH |DAC Conversion Complete Finish Flag
AnnaBridge 171:3a7713b1edbc 3058 * | | |0 = DAC is in conversion state.
AnnaBridge 171:3a7713b1edbc 3059 * | | |1 = DAC conversion finish.
AnnaBridge 171:3a7713b1edbc 3060 * | | |This bit set to 1 when conversion time counter counts to SETTLET.
AnnaBridge 171:3a7713b1edbc 3061 * | | |It is cleared to 0 when DAC starts a new conversion.
AnnaBridge 171:3a7713b1edbc 3062 * | | |User writes 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 3063 * |[1] |DMAUDR |DMA Under Run Interrupt Flag
AnnaBridge 171:3a7713b1edbc 3064 * | | |0 = No DMA under-run error condition occurred.
AnnaBridge 171:3a7713b1edbc 3065 * | | |1 = DMA under-run error condition occurred.
AnnaBridge 171:3a7713b1edbc 3066 * | | |User writes 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 3067 * |[8] |BUSY |DAC Busy Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3068 * | | |0 = DAC is ready for next conversion.
AnnaBridge 171:3a7713b1edbc 3069 * | | |1 = DAC is busy in conversion.
AnnaBridge 171:3a7713b1edbc 3070 * | | |This is read only bit.
AnnaBridge 171:3a7713b1edbc 3071 * @var DAC_T::TCTL
AnnaBridge 171:3a7713b1edbc 3072 * Offset: 0x14 DAC Timing Control Register
AnnaBridge 171:3a7713b1edbc 3073 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3074 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3075 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3076 * |[9:0] |SETTLET |DAC Output Settling Time
AnnaBridge 171:3a7713b1edbc 3077 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
AnnaBridge 171:3a7713b1edbc 3078 * | | |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
AnnaBridge 171:3a7713b1edbc 3079 */
AnnaBridge 171:3a7713b1edbc 3080
AnnaBridge 171:3a7713b1edbc 3081 __IO uint32_t CTL; /* Offset: 0x00 DAC Control Register */
AnnaBridge 171:3a7713b1edbc 3082 __IO uint32_t SWTRG; /* Offset: 0x04 DAC Software Trigger Control Register */
AnnaBridge 171:3a7713b1edbc 3083 __IO uint32_t DAT; /* Offset: 0x08 DAC Data Holding Register */
AnnaBridge 171:3a7713b1edbc 3084 __I uint32_t DATOUT; /* Offset: 0x0C DAC Data Output Register */
AnnaBridge 171:3a7713b1edbc 3085 __IO uint32_t STATUS; /* Offset: 0x10 DAC Status Register */
AnnaBridge 171:3a7713b1edbc 3086 __IO uint32_t TCTL; /* Offset: 0x14 DAC Timing Control Register */
AnnaBridge 171:3a7713b1edbc 3087
AnnaBridge 171:3a7713b1edbc 3088 } DAC_T;
AnnaBridge 171:3a7713b1edbc 3089
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091
AnnaBridge 171:3a7713b1edbc 3092 /**
AnnaBridge 171:3a7713b1edbc 3093 @addtogroup DAC_CONST DAC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 3094 Constant Definitions for DAC Controller
AnnaBridge 171:3a7713b1edbc 3095 @{ */
AnnaBridge 171:3a7713b1edbc 3096
AnnaBridge 171:3a7713b1edbc 3097 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
AnnaBridge 171:3a7713b1edbc 3098 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
AnnaBridge 171:3a7713b1edbc 3099
AnnaBridge 171:3a7713b1edbc 3100 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
AnnaBridge 171:3a7713b1edbc 3101 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
AnnaBridge 171:3a7713b1edbc 3102
AnnaBridge 171:3a7713b1edbc 3103 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
AnnaBridge 171:3a7713b1edbc 3104 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
AnnaBridge 171:3a7713b1edbc 3105
AnnaBridge 171:3a7713b1edbc 3106 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
AnnaBridge 171:3a7713b1edbc 3107 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
AnnaBridge 171:3a7713b1edbc 3108
AnnaBridge 171:3a7713b1edbc 3109 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
AnnaBridge 171:3a7713b1edbc 3110 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
AnnaBridge 171:3a7713b1edbc 3111
AnnaBridge 171:3a7713b1edbc 3112 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
AnnaBridge 171:3a7713b1edbc 3113 #define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
AnnaBridge 171:3a7713b1edbc 3114
AnnaBridge 171:3a7713b1edbc 3115 #define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
AnnaBridge 171:3a7713b1edbc 3116 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
AnnaBridge 171:3a7713b1edbc 3117
AnnaBridge 171:3a7713b1edbc 3118 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
AnnaBridge 171:3a7713b1edbc 3119 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
AnnaBridge 171:3a7713b1edbc 3120
AnnaBridge 171:3a7713b1edbc 3121 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
AnnaBridge 171:3a7713b1edbc 3122 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
AnnaBridge 171:3a7713b1edbc 3123
AnnaBridge 171:3a7713b1edbc 3124 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
AnnaBridge 171:3a7713b1edbc 3125 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
AnnaBridge 171:3a7713b1edbc 3126
AnnaBridge 171:3a7713b1edbc 3127 #define DAC_DAT_DAC_DAT_Pos (0) /*!< DAC_T::DAT: DAC_DAT Position */
AnnaBridge 171:3a7713b1edbc 3128 #define DAC_DAT_DAC_DAT_Msk (0xfffful << DAC_DAT_DAC_DAT_Pos) /*!< DAC_T::DAT: DAC_DAT Mask */
AnnaBridge 171:3a7713b1edbc 3129
AnnaBridge 171:3a7713b1edbc 3130 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
AnnaBridge 171:3a7713b1edbc 3131 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
AnnaBridge 171:3a7713b1edbc 3132
AnnaBridge 171:3a7713b1edbc 3133 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
AnnaBridge 171:3a7713b1edbc 3134 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
AnnaBridge 171:3a7713b1edbc 3135
AnnaBridge 171:3a7713b1edbc 3136 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
AnnaBridge 171:3a7713b1edbc 3137 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
AnnaBridge 171:3a7713b1edbc 3138
AnnaBridge 171:3a7713b1edbc 3139 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
AnnaBridge 171:3a7713b1edbc 3140 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 3141
AnnaBridge 171:3a7713b1edbc 3142 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
AnnaBridge 171:3a7713b1edbc 3143 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
AnnaBridge 171:3a7713b1edbc 3144
AnnaBridge 171:3a7713b1edbc 3145 /**@}*/ /* DAC_CONST */
AnnaBridge 171:3a7713b1edbc 3146 /**@}*/ /* end of DAC register group */
AnnaBridge 171:3a7713b1edbc 3147
AnnaBridge 171:3a7713b1edbc 3148
AnnaBridge 171:3a7713b1edbc 3149 /*---------------------- External Bus Interface Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 3150 /**
AnnaBridge 171:3a7713b1edbc 3151 @addtogroup EBI External Bus Interface Controller(EBI)
AnnaBridge 171:3a7713b1edbc 3152 Memory Mapped Structure for EBI Controller
AnnaBridge 171:3a7713b1edbc 3153 @{ */
AnnaBridge 171:3a7713b1edbc 3154
AnnaBridge 171:3a7713b1edbc 3155
AnnaBridge 171:3a7713b1edbc 3156 typedef struct
AnnaBridge 171:3a7713b1edbc 3157 {
AnnaBridge 171:3a7713b1edbc 3158
AnnaBridge 171:3a7713b1edbc 3159
AnnaBridge 171:3a7713b1edbc 3160
AnnaBridge 171:3a7713b1edbc 3161
AnnaBridge 171:3a7713b1edbc 3162 /**
AnnaBridge 171:3a7713b1edbc 3163 * @var EBI_T::CTL0
AnnaBridge 171:3a7713b1edbc 3164 * Offset: 0x00 External Bus Interface Bank0 Control Register
AnnaBridge 171:3a7713b1edbc 3165 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3166 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3167 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3168 * |[0] |EN |EBI Enable Bit
AnnaBridge 171:3a7713b1edbc 3169 * | | |This bit is the functional enable bit for EBI.
AnnaBridge 171:3a7713b1edbc 3170 * | | |0 = EBI function Disabled.
AnnaBridge 171:3a7713b1edbc 3171 * | | |1 = EBI function Enabled.
AnnaBridge 171:3a7713b1edbc 3172 * |[1] |DW16 |EBI Data Width 16-Bit Select
AnnaBridge 171:3a7713b1edbc 3173 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
AnnaBridge 171:3a7713b1edbc 3174 * | | |0 = EBI data width is 8-bit.
AnnaBridge 171:3a7713b1edbc 3175 * | | |1 = EBI data width is 16-bit.
AnnaBridge 171:3a7713b1edbc 3176 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
AnnaBridge 171:3a7713b1edbc 3177 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
AnnaBridge 171:3a7713b1edbc 3178 * | | |0 = Chip select pin (EBI_nCS) is active low.
AnnaBridge 171:3a7713b1edbc 3179 * | | |1 = Chip select pin (EBI_nCS) is active high.
AnnaBridge 171:3a7713b1edbc 3180 * |[10:8] |MCLKDIV |External Output Clock Divider
AnnaBridge 171:3a7713b1edbc 3181 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
AnnaBridge 171:3a7713b1edbc 3182 * | | |000 = HCLK/1.
AnnaBridge 171:3a7713b1edbc 3183 * | | |001 = HCLK/2.
AnnaBridge 171:3a7713b1edbc 3184 * | | |010 = HCLK/4.
AnnaBridge 171:3a7713b1edbc 3185 * | | |011 = HCLK/8.
AnnaBridge 171:3a7713b1edbc 3186 * | | |100 = HCLK/16.
AnnaBridge 171:3a7713b1edbc 3187 * | | |101 = HCLK/32.
AnnaBridge 171:3a7713b1edbc 3188 * | | |110 = Reserved.
AnnaBridge 171:3a7713b1edbc 3189 * | | |111 = Reserved.
AnnaBridge 171:3a7713b1edbc 3190 * |[18:16] |TALE |Extend Time Of ALE
AnnaBridge 171:3a7713b1edbc 3191 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
AnnaBridge 171:3a7713b1edbc 3192 * | | |tALE = (TALE+1)*EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3193 * | | |Note: This field only available in EBI_CTL0 register
AnnaBridge 171:3a7713b1edbc 3194 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
AnnaBridge 171:3a7713b1edbc 3195 * | | |0 = EBI write buffer Disabled.
AnnaBridge 171:3a7713b1edbc 3196 * | | |1 = EBI write buffer Enabled.
AnnaBridge 171:3a7713b1edbc 3197 * | | |Note: This bit only available in EBI_CTL0 register
AnnaBridge 171:3a7713b1edbc 3198 * @var EBI_T::TCTL0
AnnaBridge 171:3a7713b1edbc 3199 * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
AnnaBridge 171:3a7713b1edbc 3200 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3201 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3202 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3203 * |[7:3] |TACC |EBI Data Access Time
AnnaBridge 171:3a7713b1edbc 3204 * | | |TACC define data access time (tACC).
AnnaBridge 171:3a7713b1edbc 3205 * | | |tACC = (TACC +1) * EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3206 * |[10:8] |TAHD |EBI Data Access Hold Time
AnnaBridge 171:3a7713b1edbc 3207 * | | |TAHD define data access hold time (tAHD).
AnnaBridge 171:3a7713b1edbc 3208 * | | |tAHD = (TAHD +1) * EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3209 * |[15:12] |W2X |Idle Cycle After Write
AnnaBridge 171:3a7713b1edbc 3210 * | | |This field defines the number of W2X idle cycle.
AnnaBridge 171:3a7713b1edbc 3211 * | | |W2X idle cycle = (W2X * EBI_MCLK).
AnnaBridge 171:3a7713b1edbc 3212 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
AnnaBridge 171:3a7713b1edbc 3213 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
AnnaBridge 171:3a7713b1edbc 3214 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
AnnaBridge 171:3a7713b1edbc 3215 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
AnnaBridge 171:3a7713b1edbc 3216 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
AnnaBridge 171:3a7713b1edbc 3217 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
AnnaBridge 171:3a7713b1edbc 3218 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
AnnaBridge 171:3a7713b1edbc 3219 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
AnnaBridge 171:3a7713b1edbc 3220 * | | |This field defines the number of R2R idle cycle.
AnnaBridge 171:3a7713b1edbc 3221 * | | |R2R idle cycle = (R2R * EBI_MCLK).
AnnaBridge 171:3a7713b1edbc 3222 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
AnnaBridge 171:3a7713b1edbc 3223 * @var EBI_T::CTL1
AnnaBridge 171:3a7713b1edbc 3224 * Offset: 0x10 External Bus Interface Bank1 Control Register
AnnaBridge 171:3a7713b1edbc 3225 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3226 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3227 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3228 * |[0] |EN |EBI Enable Bit
AnnaBridge 171:3a7713b1edbc 3229 * | | |This bit is the functional enable bit for EBI.
AnnaBridge 171:3a7713b1edbc 3230 * | | |0 = EBI function Disabled.
AnnaBridge 171:3a7713b1edbc 3231 * | | |1 = EBI function Enabled.
AnnaBridge 171:3a7713b1edbc 3232 * |[1] |DW16 |EBI Data Width 16-Bit Select
AnnaBridge 171:3a7713b1edbc 3233 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
AnnaBridge 171:3a7713b1edbc 3234 * | | |0 = EBI data width is 8-bit.
AnnaBridge 171:3a7713b1edbc 3235 * | | |1 = EBI data width is 16-bit.
AnnaBridge 171:3a7713b1edbc 3236 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
AnnaBridge 171:3a7713b1edbc 3237 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
AnnaBridge 171:3a7713b1edbc 3238 * | | |0 = Chip select pin (EBI_nCS) is active low.
AnnaBridge 171:3a7713b1edbc 3239 * | | |1 = Chip select pin (EBI_nCS) is active high.
AnnaBridge 171:3a7713b1edbc 3240 * |[10:8] |MCLKDIV |External Output Clock Divider
AnnaBridge 171:3a7713b1edbc 3241 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
AnnaBridge 171:3a7713b1edbc 3242 * | | |000 = HCLK/1.
AnnaBridge 171:3a7713b1edbc 3243 * | | |001 = HCLK/2.
AnnaBridge 171:3a7713b1edbc 3244 * | | |010 = HCLK/4.
AnnaBridge 171:3a7713b1edbc 3245 * | | |011 = HCLK/8.
AnnaBridge 171:3a7713b1edbc 3246 * | | |100 = HCLK/16.
AnnaBridge 171:3a7713b1edbc 3247 * | | |101 = HCLK/32.
AnnaBridge 171:3a7713b1edbc 3248 * | | |110 = Reserved.
AnnaBridge 171:3a7713b1edbc 3249 * | | |111 = Reserved.
AnnaBridge 171:3a7713b1edbc 3250 * |[18:16] |TALE |Extend Time Of ALE
AnnaBridge 171:3a7713b1edbc 3251 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
AnnaBridge 171:3a7713b1edbc 3252 * | | |tALE = (TALE+1)*EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3253 * | | |Note: This field only available in EBI_CTL0 register
AnnaBridge 171:3a7713b1edbc 3254 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
AnnaBridge 171:3a7713b1edbc 3255 * | | |0 = EBI write buffer Disabled.
AnnaBridge 171:3a7713b1edbc 3256 * | | |1 = EBI write buffer Enabled.
AnnaBridge 171:3a7713b1edbc 3257 * | | |Note: This bit only available in EBI_CTL0 register
AnnaBridge 171:3a7713b1edbc 3258 * @var EBI_T::TCTL1
AnnaBridge 171:3a7713b1edbc 3259 * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
AnnaBridge 171:3a7713b1edbc 3260 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3261 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3262 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3263 * |[7:3] |TACC |EBI Data Access Time
AnnaBridge 171:3a7713b1edbc 3264 * | | |TACC define data access time (tACC).
AnnaBridge 171:3a7713b1edbc 3265 * | | |tACC = (TACC +1) * EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3266 * |[10:8] |TAHD |EBI Data Access Hold Time
AnnaBridge 171:3a7713b1edbc 3267 * | | |TAHD define data access hold time (tAHD).
AnnaBridge 171:3a7713b1edbc 3268 * | | |tAHD = (TAHD +1) * EBI_MCLK.
AnnaBridge 171:3a7713b1edbc 3269 * |[15:12] |W2X |Idle Cycle After Write
AnnaBridge 171:3a7713b1edbc 3270 * | | |This field defines the number of W2X idle cycle.
AnnaBridge 171:3a7713b1edbc 3271 * | | |W2X idle cycle = (W2X * EBI_MCLK).
AnnaBridge 171:3a7713b1edbc 3272 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
AnnaBridge 171:3a7713b1edbc 3273 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
AnnaBridge 171:3a7713b1edbc 3274 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
AnnaBridge 171:3a7713b1edbc 3275 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
AnnaBridge 171:3a7713b1edbc 3276 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
AnnaBridge 171:3a7713b1edbc 3277 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
AnnaBridge 171:3a7713b1edbc 3278 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
AnnaBridge 171:3a7713b1edbc 3279 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
AnnaBridge 171:3a7713b1edbc 3280 * | | |This field defines the number of R2R idle cycle.
AnnaBridge 171:3a7713b1edbc 3281 * | | |R2R idle cycle = (R2R * EBI_MCLK).
AnnaBridge 171:3a7713b1edbc 3282 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
AnnaBridge 171:3a7713b1edbc 3283 */
AnnaBridge 171:3a7713b1edbc 3284
AnnaBridge 171:3a7713b1edbc 3285 __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
AnnaBridge 171:3a7713b1edbc 3286 __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
AnnaBridge 171:3a7713b1edbc 3287 __I uint32_t RESERVE0[2];
AnnaBridge 171:3a7713b1edbc 3288 __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
AnnaBridge 171:3a7713b1edbc 3289 __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
AnnaBridge 171:3a7713b1edbc 3290
AnnaBridge 171:3a7713b1edbc 3291 } EBI_T;
AnnaBridge 171:3a7713b1edbc 3292
AnnaBridge 171:3a7713b1edbc 3293
AnnaBridge 171:3a7713b1edbc 3294
AnnaBridge 171:3a7713b1edbc 3295 /**
AnnaBridge 171:3a7713b1edbc 3296 @addtogroup EBI_CONST EBI Bit Field Definition
AnnaBridge 171:3a7713b1edbc 3297 Constant Definitions for EBI Controller
AnnaBridge 171:3a7713b1edbc 3298 @{ */
AnnaBridge 171:3a7713b1edbc 3299
AnnaBridge 171:3a7713b1edbc 3300 #define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
AnnaBridge 171:3a7713b1edbc 3301 #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
AnnaBridge 171:3a7713b1edbc 3302
AnnaBridge 171:3a7713b1edbc 3303 #define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
AnnaBridge 171:3a7713b1edbc 3304 #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
AnnaBridge 171:3a7713b1edbc 3305
AnnaBridge 171:3a7713b1edbc 3306 #define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
AnnaBridge 171:3a7713b1edbc 3307 #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
AnnaBridge 171:3a7713b1edbc 3308
AnnaBridge 171:3a7713b1edbc 3309 #define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
AnnaBridge 171:3a7713b1edbc 3310 #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
AnnaBridge 171:3a7713b1edbc 3311
AnnaBridge 171:3a7713b1edbc 3312 #define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
AnnaBridge 171:3a7713b1edbc 3313 #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
AnnaBridge 171:3a7713b1edbc 3314
AnnaBridge 171:3a7713b1edbc 3315 #define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
AnnaBridge 171:3a7713b1edbc 3316 #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
AnnaBridge 171:3a7713b1edbc 3317
AnnaBridge 171:3a7713b1edbc 3318 #define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
AnnaBridge 171:3a7713b1edbc 3319 #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
AnnaBridge 171:3a7713b1edbc 3320
AnnaBridge 171:3a7713b1edbc 3321 #define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
AnnaBridge 171:3a7713b1edbc 3322 #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
AnnaBridge 171:3a7713b1edbc 3323
AnnaBridge 171:3a7713b1edbc 3324 #define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
AnnaBridge 171:3a7713b1edbc 3325 #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
AnnaBridge 171:3a7713b1edbc 3326
AnnaBridge 171:3a7713b1edbc 3327 #define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
AnnaBridge 171:3a7713b1edbc 3328 #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
AnnaBridge 171:3a7713b1edbc 3329
AnnaBridge 171:3a7713b1edbc 3330 #define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
AnnaBridge 171:3a7713b1edbc 3331 #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
AnnaBridge 171:3a7713b1edbc 3332
AnnaBridge 171:3a7713b1edbc 3333 #define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
AnnaBridge 171:3a7713b1edbc 3334 #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
AnnaBridge 171:3a7713b1edbc 3335
AnnaBridge 171:3a7713b1edbc 3336 #define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
AnnaBridge 171:3a7713b1edbc 3337 #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
AnnaBridge 171:3a7713b1edbc 3338
AnnaBridge 171:3a7713b1edbc 3339 #define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
AnnaBridge 171:3a7713b1edbc 3340 #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
AnnaBridge 171:3a7713b1edbc 3341
AnnaBridge 171:3a7713b1edbc 3342 #define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
AnnaBridge 171:3a7713b1edbc 3343 #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
AnnaBridge 171:3a7713b1edbc 3344
AnnaBridge 171:3a7713b1edbc 3345 #define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
AnnaBridge 171:3a7713b1edbc 3346 #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
AnnaBridge 171:3a7713b1edbc 3347
AnnaBridge 171:3a7713b1edbc 3348 #define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
AnnaBridge 171:3a7713b1edbc 3349 #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
AnnaBridge 171:3a7713b1edbc 3350
AnnaBridge 171:3a7713b1edbc 3351 #define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
AnnaBridge 171:3a7713b1edbc 3352 #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
AnnaBridge 171:3a7713b1edbc 3353
AnnaBridge 171:3a7713b1edbc 3354 #define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
AnnaBridge 171:3a7713b1edbc 3355 #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
AnnaBridge 171:3a7713b1edbc 3356
AnnaBridge 171:3a7713b1edbc 3357 #define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
AnnaBridge 171:3a7713b1edbc 3358 #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
AnnaBridge 171:3a7713b1edbc 3359
AnnaBridge 171:3a7713b1edbc 3360 #define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
AnnaBridge 171:3a7713b1edbc 3361 #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
AnnaBridge 171:3a7713b1edbc 3362
AnnaBridge 171:3a7713b1edbc 3363 #define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
AnnaBridge 171:3a7713b1edbc 3364 #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
AnnaBridge 171:3a7713b1edbc 3365
AnnaBridge 171:3a7713b1edbc 3366 #define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
AnnaBridge 171:3a7713b1edbc 3367 #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
AnnaBridge 171:3a7713b1edbc 3368
AnnaBridge 171:3a7713b1edbc 3369 #define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
AnnaBridge 171:3a7713b1edbc 3370 #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
AnnaBridge 171:3a7713b1edbc 3371
AnnaBridge 171:3a7713b1edbc 3372 /**@}*/ /* EBI_CONST */
AnnaBridge 171:3a7713b1edbc 3373 /**@}*/ /* end of EBI register group */
AnnaBridge 171:3a7713b1edbc 3374
AnnaBridge 171:3a7713b1edbc 3375
AnnaBridge 171:3a7713b1edbc 3376 /*---------------------- Flash Memory Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 3377 /**
AnnaBridge 171:3a7713b1edbc 3378 @addtogroup FMC Flash Memory Controller(FMC)
AnnaBridge 171:3a7713b1edbc 3379 Memory Mapped Structure for FMC Controller
AnnaBridge 171:3a7713b1edbc 3380 @{ */
AnnaBridge 171:3a7713b1edbc 3381
AnnaBridge 171:3a7713b1edbc 3382
AnnaBridge 171:3a7713b1edbc 3383 typedef struct
AnnaBridge 171:3a7713b1edbc 3384 {
AnnaBridge 171:3a7713b1edbc 3385
AnnaBridge 171:3a7713b1edbc 3386
AnnaBridge 171:3a7713b1edbc 3387
AnnaBridge 171:3a7713b1edbc 3388
AnnaBridge 171:3a7713b1edbc 3389 /**
AnnaBridge 171:3a7713b1edbc 3390 * @var FMC_T::ISPCTL
AnnaBridge 171:3a7713b1edbc 3391 * Offset: 0x00 ISP Control Register
AnnaBridge 171:3a7713b1edbc 3392 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3393 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3394 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3395 * |[0] |ISPEN |ISP Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 3396 * | | |ISP function enable bit. Set this bit to enable ISP function.
AnnaBridge 171:3a7713b1edbc 3397 * | | |0 = ISP function Disabled.
AnnaBridge 171:3a7713b1edbc 3398 * | | |1 = ISP function Enabled.
AnnaBridge 171:3a7713b1edbc 3399 * |[1] |BS |Boot Select (Write Protect)
AnnaBridge 171:3a7713b1edbc 3400 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
AnnaBridge 171:3a7713b1edbc 3401 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
AnnaBridge 171:3a7713b1edbc 3402 * | | |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
AnnaBridge 171:3a7713b1edbc 3403 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
AnnaBridge 171:3a7713b1edbc 3404 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
AnnaBridge 171:3a7713b1edbc 3405 * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 3406 * | | |0 = APROM cannot be updated when the chip runs in APROM.
AnnaBridge 171:3a7713b1edbc 3407 * | | |1 = APROM can be updated when the chip runs in APROM.
AnnaBridge 171:3a7713b1edbc 3408 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 3409 * | | |0 = CONFIG cannot be updated.
AnnaBridge 171:3a7713b1edbc 3410 * | | |1 = CONFIG can be updated.
AnnaBridge 171:3a7713b1edbc 3411 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 3412 * | | |LDROM update enable bit.
AnnaBridge 171:3a7713b1edbc 3413 * | | |0 = LDROM cannot be updated.
AnnaBridge 171:3a7713b1edbc 3414 * | | |1 = LDROM can be updated.
AnnaBridge 171:3a7713b1edbc 3415 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 3416 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
AnnaBridge 171:3a7713b1edbc 3417 * | | |This bit needs to be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 3418 * | | |(1) APROM writes to itself if APUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3419 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3420 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3421 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
AnnaBridge 171:3a7713b1edbc 3422 * | | |(5) SPROM is programmed at SPROM secured mode.
AnnaBridge 171:3a7713b1edbc 3423 * | | |(6) Page Erase command at LOCK mode with ICE connection
AnnaBridge 171:3a7713b1edbc 3424 * | | |(7) Erase or Program command at brown-out detected
AnnaBridge 171:3a7713b1edbc 3425 * | | |(8) Destination address is illegal, such as over an available range.
AnnaBridge 171:3a7713b1edbc 3426 * | | |(9) Invalid ISP commands
AnnaBridge 171:3a7713b1edbc 3427 * |[16] |BL |Boot Loader Booting (Write Protect)
AnnaBridge 171:3a7713b1edbc 3428 * | | |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
AnnaBridge 171:3a7713b1edbc 3429 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
AnnaBridge 171:3a7713b1edbc 3430 * | | |This bit is used to check chip boot from Boot Loader or not.
AnnaBridge 171:3a7713b1edbc 3431 * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
AnnaBridge 171:3a7713b1edbc 3432 * | | |0 = Booting from APROM or LDROM.
AnnaBridge 171:3a7713b1edbc 3433 * | | |1 = Booting from Boot Loader.
AnnaBridge 171:3a7713b1edbc 3434 * @var FMC_T::ISPADDR
AnnaBridge 171:3a7713b1edbc 3435 * Offset: 0x04 ISP Address Register
AnnaBridge 171:3a7713b1edbc 3436 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3437 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3438 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3439 * |[31:0] |ISPADDR |ISP Address
AnnaBridge 171:3a7713b1edbc 3440 * | | |The NuMicro M451 series is equipped with embedded flash.
AnnaBridge 171:3a7713b1edbc 3441 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
AnnaBridge 171:3a7713b1edbc 3442 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
AnnaBridge 171:3a7713b1edbc 3443 * | | |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
AnnaBridge 171:3a7713b1edbc 3444 * @var FMC_T::ISPDAT
AnnaBridge 171:3a7713b1edbc 3445 * Offset: 0x08 ISP Data Register
AnnaBridge 171:3a7713b1edbc 3446 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3447 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3448 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3449 * |[31:0] |ISPDAT |ISP Data
AnnaBridge 171:3a7713b1edbc 3450 * | | |Write data to this register before ISP program operation.
AnnaBridge 171:3a7713b1edbc 3451 * | | |Read data from this register after ISP read operation.
AnnaBridge 171:3a7713b1edbc 3452 * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
AnnaBridge 171:3a7713b1edbc 3453 * | | |For ISP Read Checksum command, ISPDAT is the checksum result.
AnnaBridge 171:3a7713b1edbc 3454 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
AnnaBridge 171:3a7713b1edbc 3455 * @var FMC_T::ISPCMD
AnnaBridge 171:3a7713b1edbc 3456 * Offset: 0x0C ISP CMD Register
AnnaBridge 171:3a7713b1edbc 3457 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3458 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3459 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3460 * |[6:0] |CMD |ISP CMD
AnnaBridge 171:3a7713b1edbc 3461 * | | |ISP command table is shown below:
AnnaBridge 171:3a7713b1edbc 3462 * | | |0x00= FLASH Read.
AnnaBridge 171:3a7713b1edbc 3463 * | | |0x04= Read Unique ID.
AnnaBridge 171:3a7713b1edbc 3464 * | | |0x0B= Read Company ID.
AnnaBridge 171:3a7713b1edbc 3465 * | | |0x0C= Read Device ID.
AnnaBridge 171:3a7713b1edbc 3466 * | | |0x0D= Read Checksum.
AnnaBridge 171:3a7713b1edbc 3467 * | | |0x21= FLASH 32-bit Program.
AnnaBridge 171:3a7713b1edbc 3468 * | | |0x22= FLASH Page Erase.
AnnaBridge 171:3a7713b1edbc 3469 * | | |0x27= FLASH Multi-Word Program.
AnnaBridge 171:3a7713b1edbc 3470 * | | |0x2D= Run Checksum Calculation.
AnnaBridge 171:3a7713b1edbc 3471 * | | |0x2E= Vector Remap.
AnnaBridge 171:3a7713b1edbc 3472 * | | |0x61= FLASH 64-bit Program.
AnnaBridge 171:3a7713b1edbc 3473 * | | |The other commands are invalid.
AnnaBridge 171:3a7713b1edbc 3474 * @var FMC_T::ISPTRG
AnnaBridge 171:3a7713b1edbc 3475 * Offset: 0x10 ISP Trigger Control Register
AnnaBridge 171:3a7713b1edbc 3476 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3477 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3478 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3479 * |[0] |ISPGO |ISP Start Trigger (Write Protect)
AnnaBridge 171:3a7713b1edbc 3480 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
AnnaBridge 171:3a7713b1edbc 3481 * | | |0 = ISP operation is finished.
AnnaBridge 171:3a7713b1edbc 3482 * | | |1 = ISP is progressed.
AnnaBridge 171:3a7713b1edbc 3483 * @var FMC_T::DFBA
AnnaBridge 171:3a7713b1edbc 3484 * Offset: 0x14 Data Flash Base Address
AnnaBridge 171:3a7713b1edbc 3485 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3486 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3487 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3488 * |[31:0] |DFBA |Data Flash Base Address
AnnaBridge 171:3a7713b1edbc 3489 * | | |This register indicates Data Flash start address. It is a read only register.
AnnaBridge 171:3a7713b1edbc 3490 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
AnnaBridge 171:3a7713b1edbc 3491 * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
AnnaBridge 171:3a7713b1edbc 3492 * @var FMC_T::FTCTL
AnnaBridge 171:3a7713b1edbc 3493 * Offset: 0x18 Flash Access Time Control Register
AnnaBridge 171:3a7713b1edbc 3494 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3495 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3496 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3497 * |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
AnnaBridge 171:3a7713b1edbc 3498 * | | |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
AnnaBridge 171:3a7713b1edbc 3499 * | | |001 = Frequency <= 12MHz.
AnnaBridge 171:3a7713b1edbc 3500 * | | |010 = Frequency <= 36MHz.
AnnaBridge 171:3a7713b1edbc 3501 * | | |100 = Frequency <= 60MHz.
AnnaBridge 171:3a7713b1edbc 3502 * | | |Others = Frequency <= 72MHz.
AnnaBridge 171:3a7713b1edbc 3503 * @var FMC_T::ISPSTS
AnnaBridge 171:3a7713b1edbc 3504 * Offset: 0x40 ISP Status Register
AnnaBridge 171:3a7713b1edbc 3505 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3506 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3507 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3508 * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3509 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
AnnaBridge 171:3a7713b1edbc 3510 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
AnnaBridge 171:3a7713b1edbc 3511 * | | |0 = ISP operation is finished.
AnnaBridge 171:3a7713b1edbc 3512 * | | |1 = ISP is progressed.
AnnaBridge 171:3a7713b1edbc 3513 * |[2:1] |CBS |Boot Selection Of CONFIG (Read Only)
AnnaBridge 171:3a7713b1edbc 3514 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
AnnaBridge 171:3a7713b1edbc 3515 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
AnnaBridge 171:3a7713b1edbc 3516 * | | |00 = LDROM with IAP mode.
AnnaBridge 171:3a7713b1edbc 3517 * | | |01 = LDROM without IAP mode.
AnnaBridge 171:3a7713b1edbc 3518 * | | |10 = APROM with IAP mode.
AnnaBridge 171:3a7713b1edbc 3519 * | | |11 = APROM without IAP mode.
AnnaBridge 171:3a7713b1edbc 3520 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3521 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
AnnaBridge 171:3a7713b1edbc 3522 * | | |0 = Booting from Boot Loader.
AnnaBridge 171:3a7713b1edbc 3523 * | | |1 = Booting
AnnaBridge 171:3a7713b1edbc 3524 * | | |from LDROM/APROM.(see CBS bit setting)
AnnaBridge 171:3a7713b1edbc 3525 * |[5] |PGFF |Flash Program With Fast Verification Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3526 * | | |This bit is set if data is mismatched at ISP programming verification.
AnnaBridge 171:3a7713b1edbc 3527 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation.
AnnaBridge 171:3a7713b1edbc 3528 * | | |0 = Flash Program is success.
AnnaBridge 171:3a7713b1edbc 3529 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
AnnaBridge 171:3a7713b1edbc 3530 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 3531 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
AnnaBridge 171:3a7713b1edbc 3532 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
AnnaBridge 171:3a7713b1edbc 3533 * | | |(1) APROM writes to itself if APUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3534 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3535 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3536 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
AnnaBridge 171:3a7713b1edbc 3537 * | | |(5) SPROM is programmed at SPROM secured mode.
AnnaBridge 171:3a7713b1edbc 3538 * | | |(6) Page Erase command at LOCK mode with ICE connection
AnnaBridge 171:3a7713b1edbc 3539 * | | |(7) Erase or Program command at brown-out detected
AnnaBridge 171:3a7713b1edbc 3540 * | | |(8) Destination address is illegal, such as over an available range.
AnnaBridge 171:3a7713b1edbc 3541 * | | |(9) Invalid ISP commands
AnnaBridge 171:3a7713b1edbc 3542 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
AnnaBridge 171:3a7713b1edbc 3543 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
AnnaBridge 171:3a7713b1edbc 3544 * @var FMC_T::MPDAT0
AnnaBridge 171:3a7713b1edbc 3545 * Offset: 0x80 ISP Data0 Register
AnnaBridge 171:3a7713b1edbc 3546 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3547 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3548 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3549 * |[31:0] |ISPDAT0 |ISP Data 0
AnnaBridge 171:3a7713b1edbc 3550 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
AnnaBridge 171:3a7713b1edbc 3551 * @var FMC_T::MPDAT1
AnnaBridge 171:3a7713b1edbc 3552 * Offset: 0x84 ISP Data1 Register
AnnaBridge 171:3a7713b1edbc 3553 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3554 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3555 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3556 * |[31:0] |ISPDAT1 |ISP Data 1
AnnaBridge 171:3a7713b1edbc 3557 * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
AnnaBridge 171:3a7713b1edbc 3558 * @var FMC_T::MPDAT2
AnnaBridge 171:3a7713b1edbc 3559 * Offset: 0x88 ISP Data2 Register
AnnaBridge 171:3a7713b1edbc 3560 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3561 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3562 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3563 * |[31:0] |ISPDAT2 |ISP Data 2
AnnaBridge 171:3a7713b1edbc 3564 * | | |This register is the third 32-bit data for multi-word programming.
AnnaBridge 171:3a7713b1edbc 3565 * @var FMC_T::MPDAT3
AnnaBridge 171:3a7713b1edbc 3566 * Offset: 0x8C ISP Data3 Register
AnnaBridge 171:3a7713b1edbc 3567 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3568 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3569 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3570 * |[31:0] |ISPDAT3 |ISP Data 3
AnnaBridge 171:3a7713b1edbc 3571 * | | |This register is the fourth 32-bit data for multi-word programming.
AnnaBridge 171:3a7713b1edbc 3572 * @var FMC_T::MPSTS
AnnaBridge 171:3a7713b1edbc 3573 * Offset: 0xC0 ISP Multi-Program Status Register
AnnaBridge 171:3a7713b1edbc 3574 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3575 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3576 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3577 * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3578 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
AnnaBridge 171:3a7713b1edbc 3579 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
AnnaBridge 171:3a7713b1edbc 3580 * | | |0 = ISP Multi-Word program operation is finished.
AnnaBridge 171:3a7713b1edbc 3581 * | | |1 = ISP Multi-Word program operation
AnnaBridge 171:3a7713b1edbc 3582 * | | |is progressed.
AnnaBridge 171:3a7713b1edbc 3583 * |[1] |PPGO |ISP Multi-Program Status (Read Only)
AnnaBridge 171:3a7713b1edbc 3584 * | | |0 = ISP multi-word program operation is not active.
AnnaBridge 171:3a7713b1edbc 3585 * | | |1 = ISP multi-word program operation is in progress.
AnnaBridge 171:3a7713b1edbc 3586 * |[2] |ISPFF |ISP Fail Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3587 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
AnnaBridge 171:3a7713b1edbc 3588 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
AnnaBridge 171:3a7713b1edbc 3589 * | | |(1) APROM writes to itself if APUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3590 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3591 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
AnnaBridge 171:3a7713b1edbc 3592 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
AnnaBridge 171:3a7713b1edbc 3593 * | | |(5) SPROM is programmed at SPROM secured mode.
AnnaBridge 171:3a7713b1edbc 3594 * | | |(6) Page Erase command at LOCK mode with ICE connection
AnnaBridge 171:3a7713b1edbc 3595 * | | |(7) Erase or Program command at brown-out detected
AnnaBridge 171:3a7713b1edbc 3596 * | | |(8) Destination address is illegal, such as over an available range.
AnnaBridge 171:3a7713b1edbc 3597 * | | |(9) Invalid ISP commands
AnnaBridge 171:3a7713b1edbc 3598 * |[4] |D0 |ISP DATA 0 Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3599 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
AnnaBridge 171:3a7713b1edbc 3600 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
AnnaBridge 171:3a7713b1edbc 3601 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
AnnaBridge 171:3a7713b1edbc 3602 * |[5] |D1 |ISP DATA 1 Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3603 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
AnnaBridge 171:3a7713b1edbc 3604 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
AnnaBridge 171:3a7713b1edbc 3605 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
AnnaBridge 171:3a7713b1edbc 3606 * |[6] |D2 |ISP DATA 2 Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3607 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
AnnaBridge 171:3a7713b1edbc 3608 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
AnnaBridge 171:3a7713b1edbc 3609 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
AnnaBridge 171:3a7713b1edbc 3610 * |[7] |D3 |ISP DATA 3 Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 3611 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
AnnaBridge 171:3a7713b1edbc 3612 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
AnnaBridge 171:3a7713b1edbc 3613 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
AnnaBridge 171:3a7713b1edbc 3614 * @var FMC_T::MPADDR
AnnaBridge 171:3a7713b1edbc 3615 * Offset: 0xC4 ISP Multi-Program Address Register
AnnaBridge 171:3a7713b1edbc 3616 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3617 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3618 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3619 * |[31:0] |MPADDR |ISP Multi-Word Program Address
AnnaBridge 171:3a7713b1edbc 3620 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
AnnaBridge 171:3a7713b1edbc 3621 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
AnnaBridge 171:3a7713b1edbc 3622 */
AnnaBridge 171:3a7713b1edbc 3623
AnnaBridge 171:3a7713b1edbc 3624 __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
AnnaBridge 171:3a7713b1edbc 3625 __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
AnnaBridge 171:3a7713b1edbc 3626 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
AnnaBridge 171:3a7713b1edbc 3627 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
AnnaBridge 171:3a7713b1edbc 3628 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
AnnaBridge 171:3a7713b1edbc 3629 __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
AnnaBridge 171:3a7713b1edbc 3630 __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
AnnaBridge 171:3a7713b1edbc 3631 __I uint32_t RESERVE0[9];
AnnaBridge 171:3a7713b1edbc 3632 __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
AnnaBridge 171:3a7713b1edbc 3633 __I uint32_t RESERVE1[15];
AnnaBridge 171:3a7713b1edbc 3634 __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
AnnaBridge 171:3a7713b1edbc 3635 __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
AnnaBridge 171:3a7713b1edbc 3636 __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
AnnaBridge 171:3a7713b1edbc 3637 __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
AnnaBridge 171:3a7713b1edbc 3638 __I uint32_t RESERVE2[12];
AnnaBridge 171:3a7713b1edbc 3639 __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
AnnaBridge 171:3a7713b1edbc 3640 __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
AnnaBridge 171:3a7713b1edbc 3641
AnnaBridge 171:3a7713b1edbc 3642 } FMC_T;
AnnaBridge 171:3a7713b1edbc 3643
AnnaBridge 171:3a7713b1edbc 3644
AnnaBridge 171:3a7713b1edbc 3645
AnnaBridge 171:3a7713b1edbc 3646
AnnaBridge 171:3a7713b1edbc 3647 /**
AnnaBridge 171:3a7713b1edbc 3648 @addtogroup FMC_CONST FMC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 3649 Constant Definitions for FMC Controller
AnnaBridge 171:3a7713b1edbc 3650 @{ */
AnnaBridge 171:3a7713b1edbc 3651
AnnaBridge 171:3a7713b1edbc 3652 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
AnnaBridge 171:3a7713b1edbc 3653 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
AnnaBridge 171:3a7713b1edbc 3654
AnnaBridge 171:3a7713b1edbc 3655 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
AnnaBridge 171:3a7713b1edbc 3656 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
AnnaBridge 171:3a7713b1edbc 3657
AnnaBridge 171:3a7713b1edbc 3658 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
AnnaBridge 171:3a7713b1edbc 3659 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
AnnaBridge 171:3a7713b1edbc 3660
AnnaBridge 171:3a7713b1edbc 3661 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
AnnaBridge 171:3a7713b1edbc 3662 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
AnnaBridge 171:3a7713b1edbc 3663
AnnaBridge 171:3a7713b1edbc 3664 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
AnnaBridge 171:3a7713b1edbc 3665 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
AnnaBridge 171:3a7713b1edbc 3666
AnnaBridge 171:3a7713b1edbc 3667 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
AnnaBridge 171:3a7713b1edbc 3668 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
AnnaBridge 171:3a7713b1edbc 3669
AnnaBridge 171:3a7713b1edbc 3670 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
AnnaBridge 171:3a7713b1edbc 3671 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
AnnaBridge 171:3a7713b1edbc 3672
AnnaBridge 171:3a7713b1edbc 3673 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
AnnaBridge 171:3a7713b1edbc 3674 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
AnnaBridge 171:3a7713b1edbc 3675
AnnaBridge 171:3a7713b1edbc 3676 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
AnnaBridge 171:3a7713b1edbc 3677 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
AnnaBridge 171:3a7713b1edbc 3678
AnnaBridge 171:3a7713b1edbc 3679 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
AnnaBridge 171:3a7713b1edbc 3680 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
AnnaBridge 171:3a7713b1edbc 3681
AnnaBridge 171:3a7713b1edbc 3682 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
AnnaBridge 171:3a7713b1edbc 3683 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
AnnaBridge 171:3a7713b1edbc 3684
AnnaBridge 171:3a7713b1edbc 3685 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
AnnaBridge 171:3a7713b1edbc 3686 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688 #define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
AnnaBridge 171:3a7713b1edbc 3689 #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
AnnaBridge 171:3a7713b1edbc 3690
AnnaBridge 171:3a7713b1edbc 3691 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
AnnaBridge 171:3a7713b1edbc 3692 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
AnnaBridge 171:3a7713b1edbc 3693
AnnaBridge 171:3a7713b1edbc 3694 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
AnnaBridge 171:3a7713b1edbc 3695 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
AnnaBridge 171:3a7713b1edbc 3696
AnnaBridge 171:3a7713b1edbc 3697 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
AnnaBridge 171:3a7713b1edbc 3698 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
AnnaBridge 171:3a7713b1edbc 3699
AnnaBridge 171:3a7713b1edbc 3700 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
AnnaBridge 171:3a7713b1edbc 3701 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
AnnaBridge 171:3a7713b1edbc 3702
AnnaBridge 171:3a7713b1edbc 3703 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
AnnaBridge 171:3a7713b1edbc 3704 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
AnnaBridge 171:3a7713b1edbc 3705
AnnaBridge 171:3a7713b1edbc 3706 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
AnnaBridge 171:3a7713b1edbc 3707 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
AnnaBridge 171:3a7713b1edbc 3708
AnnaBridge 171:3a7713b1edbc 3709 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
AnnaBridge 171:3a7713b1edbc 3710 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
AnnaBridge 171:3a7713b1edbc 3711
AnnaBridge 171:3a7713b1edbc 3712 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
AnnaBridge 171:3a7713b1edbc 3713 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
AnnaBridge 171:3a7713b1edbc 3716 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
AnnaBridge 171:3a7713b1edbc 3717
AnnaBridge 171:3a7713b1edbc 3718 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
AnnaBridge 171:3a7713b1edbc 3719 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
AnnaBridge 171:3a7713b1edbc 3720
AnnaBridge 171:3a7713b1edbc 3721 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
AnnaBridge 171:3a7713b1edbc 3722 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
AnnaBridge 171:3a7713b1edbc 3723
AnnaBridge 171:3a7713b1edbc 3724 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
AnnaBridge 171:3a7713b1edbc 3725 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
AnnaBridge 171:3a7713b1edbc 3726
AnnaBridge 171:3a7713b1edbc 3727 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
AnnaBridge 171:3a7713b1edbc 3728 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
AnnaBridge 171:3a7713b1edbc 3729
AnnaBridge 171:3a7713b1edbc 3730 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
AnnaBridge 171:3a7713b1edbc 3731 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
AnnaBridge 171:3a7713b1edbc 3732
AnnaBridge 171:3a7713b1edbc 3733 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
AnnaBridge 171:3a7713b1edbc 3734 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
AnnaBridge 171:3a7713b1edbc 3735
AnnaBridge 171:3a7713b1edbc 3736 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
AnnaBridge 171:3a7713b1edbc 3737 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
AnnaBridge 171:3a7713b1edbc 3738
AnnaBridge 171:3a7713b1edbc 3739 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
AnnaBridge 171:3a7713b1edbc 3740 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
AnnaBridge 171:3a7713b1edbc 3741
AnnaBridge 171:3a7713b1edbc 3742 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
AnnaBridge 171:3a7713b1edbc 3743 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
AnnaBridge 171:3a7713b1edbc 3744
AnnaBridge 171:3a7713b1edbc 3745 /**@}*/ /* FMC_CONST */
AnnaBridge 171:3a7713b1edbc 3746 /**@}*/ /* end of FMC register group */
AnnaBridge 171:3a7713b1edbc 3747
AnnaBridge 171:3a7713b1edbc 3748
AnnaBridge 171:3a7713b1edbc 3749 /*---------------------- General Purpose Input/Output Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 3750 /**
AnnaBridge 171:3a7713b1edbc 3751 @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
AnnaBridge 171:3a7713b1edbc 3752 Memory Mapped Structure for GPIO Controller
AnnaBridge 171:3a7713b1edbc 3753 @{ */
AnnaBridge 171:3a7713b1edbc 3754
AnnaBridge 171:3a7713b1edbc 3755
AnnaBridge 171:3a7713b1edbc 3756 typedef struct
AnnaBridge 171:3a7713b1edbc 3757 {
AnnaBridge 171:3a7713b1edbc 3758
AnnaBridge 171:3a7713b1edbc 3759
AnnaBridge 171:3a7713b1edbc 3760
AnnaBridge 171:3a7713b1edbc 3761 /**
AnnaBridge 171:3a7713b1edbc 3762 * @var GPIO_T::MODE
AnnaBridge 171:3a7713b1edbc 3763 * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
AnnaBridge 171:3a7713b1edbc 3764 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3765 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3766 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3767 * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
AnnaBridge 171:3a7713b1edbc 3768 * | | |Determine each I/O mode of Px.n pins.
AnnaBridge 171:3a7713b1edbc 3769 * | | |00 = Px.n is in Input mode.
AnnaBridge 171:3a7713b1edbc 3770 * | | |01 = Px.n is in Push-pull Output mode.
AnnaBridge 171:3a7713b1edbc 3771 * | | |10 = Px.n is in Open-drain Output mode.
AnnaBridge 171:3a7713b1edbc 3772 * | | |11 = Px.n is in Quasi-bidirectional mode.
AnnaBridge 171:3a7713b1edbc 3773 * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
AnnaBridge 171:3a7713b1edbc 3774 * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
AnnaBridge 171:3a7713b1edbc 3775 * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
AnnaBridge 171:3a7713b1edbc 3776 * | | |input mode after chip powered on.
AnnaBridge 171:3a7713b1edbc 3777 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 3778 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3779 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3780 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3781 * @var GPIO_T::DINOFF
AnnaBridge 171:3a7713b1edbc 3782 * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
AnnaBridge 171:3a7713b1edbc 3783 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3784 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3785 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3786 * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Control
AnnaBridge 171:3a7713b1edbc 3787 * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
AnnaBridge 171:3a7713b1edbc 3788 * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
AnnaBridge 171:3a7713b1edbc 3789 * | | |0 = Px.n digital input path Enabled.
AnnaBridge 171:3a7713b1edbc 3790 * | | |1 = Px.n digital input path Disabled (digital input tied to low).
AnnaBridge 171:3a7713b1edbc 3791 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3792 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3793 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3794 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3795 * @var GPIO_T::DOUT
AnnaBridge 171:3a7713b1edbc 3796 * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
AnnaBridge 171:3a7713b1edbc 3797 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3798 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3799 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3800 * |[n] |DOUTn |Port A-F Pin[n] Output Value
AnnaBridge 171:3a7713b1edbc 3801 * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
AnnaBridge 171:3a7713b1edbc 3802 * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
AnnaBridge 171:3a7713b1edbc 3803 * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
AnnaBridge 171:3a7713b1edbc 3804 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3805 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3806 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3807 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3808 * @var GPIO_T::DATMSK
AnnaBridge 171:3a7713b1edbc 3809 * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
AnnaBridge 171:3a7713b1edbc 3810 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3811 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3812 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3813 * |[n] |DMASKn |Port A-F Pin[n] Data Output Write Mask
AnnaBridge 171:3a7713b1edbc 3814 * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
AnnaBridge 171:3a7713b1edbc 3815 * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
AnnaBridge 171:3a7713b1edbc 3816 * | | |If the write signal is masked, writing data to the protect bit is ignored.
AnnaBridge 171:3a7713b1edbc 3817 * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
AnnaBridge 171:3a7713b1edbc 3818 * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
AnnaBridge 171:3a7713b1edbc 3819 * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
AnnaBridge 171:3a7713b1edbc 3820 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 3821 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3822 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3823 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3824 * @var GPIO_T::PIN
AnnaBridge 171:3a7713b1edbc 3825 * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value
AnnaBridge 171:3a7713b1edbc 3826 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3827 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3828 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3829 * |[n] |PINn |Port A-F Pin[n] Pin Value
AnnaBridge 171:3a7713b1edbc 3830 * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
AnnaBridge 171:3a7713b1edbc 3831 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
AnnaBridge 171:3a7713b1edbc 3832 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3833 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3834 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3835 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3836 * @var GPIO_T::DBEN
AnnaBridge 171:3a7713b1edbc 3837 * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
AnnaBridge 171:3a7713b1edbc 3838 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3839 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3840 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3841 * |[n] |DBENn |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
AnnaBridge 171:3a7713b1edbc 3842 * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
AnnaBridge 171:3a7713b1edbc 3843 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
AnnaBridge 171:3a7713b1edbc 3844 * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
AnnaBridge 171:3a7713b1edbc 3845 * | | |0 = Px.n de-bounce function Disabled.
AnnaBridge 171:3a7713b1edbc 3846 * | | |1 = Px.n de-bounce function Enabled.
AnnaBridge 171:3a7713b1edbc 3847 * | | |The de-bounce function is valid only for edge triggered interrupt.
AnnaBridge 171:3a7713b1edbc 3848 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
AnnaBridge 171:3a7713b1edbc 3849 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3850 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3851 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3852 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3853 * @var GPIO_T::INTTYPE
AnnaBridge 171:3a7713b1edbc 3854 * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
AnnaBridge 171:3a7713b1edbc 3855 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3856 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3857 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3858 * |[n] |TYPEn |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
AnnaBridge 171:3a7713b1edbc 3859 * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
AnnaBridge 171:3a7713b1edbc 3860 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
AnnaBridge 171:3a7713b1edbc 3861 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
AnnaBridge 171:3a7713b1edbc 3862 * | | |0 = Edge trigger interrupt.
AnnaBridge 171:3a7713b1edbc 3863 * | | |1 = Level trigger interrupt.
AnnaBridge 171:3a7713b1edbc 3864 * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
AnnaBridge 171:3a7713b1edbc 3865 * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
AnnaBridge 171:3a7713b1edbc 3866 * | | |The de-bounce function is valid only for edge triggered interrupt.
AnnaBridge 171:3a7713b1edbc 3867 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
AnnaBridge 171:3a7713b1edbc 3868 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3869 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3870 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3871 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3872 * @var GPIO_T::INTEN
AnnaBridge 171:3a7713b1edbc 3873 * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
AnnaBridge 171:3a7713b1edbc 3874 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3875 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3876 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3877 * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
AnnaBridge 171:3a7713b1edbc 3878 * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
AnnaBridge 171:3a7713b1edbc 3879 * | | |Set bit to 1 also enable the pin wake-up function.
AnnaBridge 171:3a7713b1edbc 3880 * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
AnnaBridge 171:3a7713b1edbc 3881 * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
AnnaBridge 171:3a7713b1edbc 3882 * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
AnnaBridge 171:3a7713b1edbc 3883 * | | |0 = Px.n level low or high to low interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 3884 * | | |1 = Px.n level low or high to low interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 3885 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3886 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3887 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3888 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3889 * @var GPIO_T::INTSRC
AnnaBridge 171:3a7713b1edbc 3890 * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
AnnaBridge 171:3a7713b1edbc 3891 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3892 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3893 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3894 * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
AnnaBridge 171:3a7713b1edbc 3895 * | | |Write Operation :
AnnaBridge 171:3a7713b1edbc 3896 * | | |0 = No action.
AnnaBridge 171:3a7713b1edbc 3897 * | | |1 = Clear the corresponding pending interrupt.
AnnaBridge 171:3a7713b1edbc 3898 * | | |Read Operation :
AnnaBridge 171:3a7713b1edbc 3899 * | | |0 = No interrupt at Px.n.
AnnaBridge 171:3a7713b1edbc 3900 * | | |1 = Px.n generates an interrupt.
AnnaBridge 171:3a7713b1edbc 3901 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3902 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3903 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3904 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3905 * @var GPIO_T::SMTEN
AnnaBridge 171:3a7713b1edbc 3906 * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
AnnaBridge 171:3a7713b1edbc 3907 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3908 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3909 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3910 * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
AnnaBridge 171:3a7713b1edbc 3911 * | | |0 = Px.n input Schmitt trigger function Disabled.
AnnaBridge 171:3a7713b1edbc 3912 * | | |1 = Px.n input Schmitt trigger function Enabled.
AnnaBridge 171:3a7713b1edbc 3913 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3914 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3915 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3916 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3917 * @var GPIO_T::SLEWCTL
AnnaBridge 171:3a7713b1edbc 3918 * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
AnnaBridge 171:3a7713b1edbc 3919 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3920 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3921 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3922 * |[n] |HSRENn |Port A-F Pin[n] High Slew Rate Control
AnnaBridge 171:3a7713b1edbc 3923 * | | |0 = Px.n output with basic slew rate.
AnnaBridge 171:3a7713b1edbc 3924 * | | |1 = Px.n output with higher slew rate.
AnnaBridge 171:3a7713b1edbc 3925 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3926 * | | |n=0~15 for port A/B/C/D.
AnnaBridge 171:3a7713b1edbc 3927 * | | |n=0~14 for port E.
AnnaBridge 171:3a7713b1edbc 3928 * | | |n=0~7 for port F.
AnnaBridge 171:3a7713b1edbc 3929 * @var GPIO_T::DRVCTL
AnnaBridge 171:3a7713b1edbc 3930 * Offset: 0x2C Port E High Drive Strength Control Register
AnnaBridge 171:3a7713b1edbc 3931 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3932 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3933 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3934 * |[n] |HDRVENn |Port E Pin[n] Driving Strength Control
AnnaBridge 171:3a7713b1edbc 3935 * | | |0 = Px.n output with basic driving strength.
AnnaBridge 171:3a7713b1edbc 3936 * | | |1 = Px.n output with high driving strength.
AnnaBridge 171:3a7713b1edbc 3937 * | | |Note:
AnnaBridge 171:3a7713b1edbc 3938 * | | |n=8,9..13 for port E.
AnnaBridge 171:3a7713b1edbc 3939 */
AnnaBridge 171:3a7713b1edbc 3940
AnnaBridge 171:3a7713b1edbc 3941 __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
AnnaBridge 171:3a7713b1edbc 3942 __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
AnnaBridge 171:3a7713b1edbc 3943 __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
AnnaBridge 171:3a7713b1edbc 3944 __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
AnnaBridge 171:3a7713b1edbc 3945 __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
AnnaBridge 171:3a7713b1edbc 3946 __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
AnnaBridge 171:3a7713b1edbc 3947 __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
AnnaBridge 171:3a7713b1edbc 3948 __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
AnnaBridge 171:3a7713b1edbc 3949 __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
AnnaBridge 171:3a7713b1edbc 3950 __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
AnnaBridge 171:3a7713b1edbc 3951 __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
AnnaBridge 171:3a7713b1edbc 3952 __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
AnnaBridge 171:3a7713b1edbc 3953
AnnaBridge 171:3a7713b1edbc 3954 } GPIO_T;
AnnaBridge 171:3a7713b1edbc 3955
AnnaBridge 171:3a7713b1edbc 3956
AnnaBridge 171:3a7713b1edbc 3957
AnnaBridge 171:3a7713b1edbc 3958
AnnaBridge 171:3a7713b1edbc 3959 typedef struct
AnnaBridge 171:3a7713b1edbc 3960 {
AnnaBridge 171:3a7713b1edbc 3961
AnnaBridge 171:3a7713b1edbc 3962
AnnaBridge 171:3a7713b1edbc 3963
AnnaBridge 171:3a7713b1edbc 3964 /**
AnnaBridge 171:3a7713b1edbc 3965 * @var GPIO_DBCTL_T::DBCTL
AnnaBridge 171:3a7713b1edbc 3966 * Offset: 0x440 Interrupt De-bounce Control Register
AnnaBridge 171:3a7713b1edbc 3967 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3968 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 3969 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 3970 * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
AnnaBridge 171:3a7713b1edbc 3971 * | | |0000 = Sample interrupt input once per 1 clocks.
AnnaBridge 171:3a7713b1edbc 3972 * | | |0001 = Sample interrupt input once per 2 clocks.
AnnaBridge 171:3a7713b1edbc 3973 * | | |0010 = Sample interrupt input once per 4 clocks.
AnnaBridge 171:3a7713b1edbc 3974 * | | |0011 = Sample interrupt input once per 8 clocks.
AnnaBridge 171:3a7713b1edbc 3975 * | | |0100 = Sample interrupt input once per 16 clocks.
AnnaBridge 171:3a7713b1edbc 3976 * | | |0101 = Sample interrupt input once per 32 clocks.
AnnaBridge 171:3a7713b1edbc 3977 * | | |0110 = Sample interrupt input once per 64 clocks.
AnnaBridge 171:3a7713b1edbc 3978 * | | |0111 = Sample interrupt input once per 128 clocks.
AnnaBridge 171:3a7713b1edbc 3979 * | | |1000 = Sample interrupt input once per 256 clocks.
AnnaBridge 171:3a7713b1edbc 3980 * | | |1001 = Sample interrupt input once per 2*256 clocks.
AnnaBridge 171:3a7713b1edbc 3981 * | | |1010 = Sample interrupt input once per 4*256 clocks.
AnnaBridge 171:3a7713b1edbc 3982 * | | |1011 = Sample interrupt input once per 8*256 clocks.
AnnaBridge 171:3a7713b1edbc 3983 * | | |1100 = Sample interrupt input once per 16*256 clocks.
AnnaBridge 171:3a7713b1edbc 3984 * | | |1101 = Sample interrupt input once per 32*256 clocks.
AnnaBridge 171:3a7713b1edbc 3985 * | | |1110 = Sample interrupt input once per 64*256 clocks.
AnnaBridge 171:3a7713b1edbc 3986 * | | |1111 = Sample interrupt input once per 128*256 clocks.
AnnaBridge 171:3a7713b1edbc 3987 * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
AnnaBridge 171:3a7713b1edbc 3988 * | | |0 = De-bounce counter clock source is the HCLK.
AnnaBridge 171:3a7713b1edbc 3989 * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
AnnaBridge 171:3a7713b1edbc 3990 * |[5] |ICLKON |Interrupt Clock On Mode
AnnaBridge 171:3a7713b1edbc 3991 * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
AnnaBridge 171:3a7713b1edbc 3992 * | | |1 = All I/O pins edge detection circuit is always active after reset.
AnnaBridge 171:3a7713b1edbc 3993 * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
AnnaBridge 171:3a7713b1edbc 3994 */
AnnaBridge 171:3a7713b1edbc 3995
AnnaBridge 171:3a7713b1edbc 3996 __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
AnnaBridge 171:3a7713b1edbc 3997
AnnaBridge 171:3a7713b1edbc 3998 } GPIO_DBCTL_T;
AnnaBridge 171:3a7713b1edbc 3999
AnnaBridge 171:3a7713b1edbc 4000
AnnaBridge 171:3a7713b1edbc 4001
AnnaBridge 171:3a7713b1edbc 4002
AnnaBridge 171:3a7713b1edbc 4003 /**
AnnaBridge 171:3a7713b1edbc 4004 @addtogroup GPIO_CONST GPIO Bit Field Definition
AnnaBridge 171:3a7713b1edbc 4005 Constant Definitions for GPIO Controller
AnnaBridge 171:3a7713b1edbc 4006 @{ */
AnnaBridge 171:3a7713b1edbc 4007
AnnaBridge 171:3a7713b1edbc 4008 #define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
AnnaBridge 171:3a7713b1edbc 4009 #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
AnnaBridge 171:3a7713b1edbc 4010
AnnaBridge 171:3a7713b1edbc 4011 #define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
AnnaBridge 171:3a7713b1edbc 4012 #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
AnnaBridge 171:3a7713b1edbc 4013
AnnaBridge 171:3a7713b1edbc 4014 #define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
AnnaBridge 171:3a7713b1edbc 4015 #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
AnnaBridge 171:3a7713b1edbc 4016
AnnaBridge 171:3a7713b1edbc 4017 #define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
AnnaBridge 171:3a7713b1edbc 4018 #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
AnnaBridge 171:3a7713b1edbc 4019
AnnaBridge 171:3a7713b1edbc 4020 #define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
AnnaBridge 171:3a7713b1edbc 4021 #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
AnnaBridge 171:3a7713b1edbc 4022
AnnaBridge 171:3a7713b1edbc 4023 #define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
AnnaBridge 171:3a7713b1edbc 4024 #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
AnnaBridge 171:3a7713b1edbc 4025
AnnaBridge 171:3a7713b1edbc 4026 #define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
AnnaBridge 171:3a7713b1edbc 4027 #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
AnnaBridge 171:3a7713b1edbc 4028
AnnaBridge 171:3a7713b1edbc 4029 #define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
AnnaBridge 171:3a7713b1edbc 4030 #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
AnnaBridge 171:3a7713b1edbc 4031
AnnaBridge 171:3a7713b1edbc 4032 #define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
AnnaBridge 171:3a7713b1edbc 4033 #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
AnnaBridge 171:3a7713b1edbc 4034
AnnaBridge 171:3a7713b1edbc 4035 #define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
AnnaBridge 171:3a7713b1edbc 4036 #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
AnnaBridge 171:3a7713b1edbc 4037
AnnaBridge 171:3a7713b1edbc 4038 #define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
AnnaBridge 171:3a7713b1edbc 4039 #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
AnnaBridge 171:3a7713b1edbc 4040
AnnaBridge 171:3a7713b1edbc 4041 #define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
AnnaBridge 171:3a7713b1edbc 4042 #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
AnnaBridge 171:3a7713b1edbc 4043
AnnaBridge 171:3a7713b1edbc 4044 #define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
AnnaBridge 171:3a7713b1edbc 4045 #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
AnnaBridge 171:3a7713b1edbc 4046
AnnaBridge 171:3a7713b1edbc 4047 #define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
AnnaBridge 171:3a7713b1edbc 4048 #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
AnnaBridge 171:3a7713b1edbc 4049
AnnaBridge 171:3a7713b1edbc 4050 #define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
AnnaBridge 171:3a7713b1edbc 4051 #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
AnnaBridge 171:3a7713b1edbc 4052
AnnaBridge 171:3a7713b1edbc 4053 #define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
AnnaBridge 171:3a7713b1edbc 4054 #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
AnnaBridge 171:3a7713b1edbc 4055
AnnaBridge 171:3a7713b1edbc 4056 #define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
AnnaBridge 171:3a7713b1edbc 4057 #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
AnnaBridge 171:3a7713b1edbc 4058
AnnaBridge 171:3a7713b1edbc 4059 #define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
AnnaBridge 171:3a7713b1edbc 4060 #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
AnnaBridge 171:3a7713b1edbc 4061
AnnaBridge 171:3a7713b1edbc 4062 #define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
AnnaBridge 171:3a7713b1edbc 4063 #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
AnnaBridge 171:3a7713b1edbc 4064
AnnaBridge 171:3a7713b1edbc 4065 #define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
AnnaBridge 171:3a7713b1edbc 4066 #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
AnnaBridge 171:3a7713b1edbc 4067
AnnaBridge 171:3a7713b1edbc 4068 #define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
AnnaBridge 171:3a7713b1edbc 4069 #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
AnnaBridge 171:3a7713b1edbc 4070
AnnaBridge 171:3a7713b1edbc 4071 #define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
AnnaBridge 171:3a7713b1edbc 4072 #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
AnnaBridge 171:3a7713b1edbc 4073
AnnaBridge 171:3a7713b1edbc 4074 #define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
AnnaBridge 171:3a7713b1edbc 4075 #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
AnnaBridge 171:3a7713b1edbc 4076
AnnaBridge 171:3a7713b1edbc 4077 #define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
AnnaBridge 171:3a7713b1edbc 4078 #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
AnnaBridge 171:3a7713b1edbc 4079
AnnaBridge 171:3a7713b1edbc 4080 #define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
AnnaBridge 171:3a7713b1edbc 4081 #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
AnnaBridge 171:3a7713b1edbc 4082
AnnaBridge 171:3a7713b1edbc 4083 #define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
AnnaBridge 171:3a7713b1edbc 4084 #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
AnnaBridge 171:3a7713b1edbc 4085
AnnaBridge 171:3a7713b1edbc 4086 #define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
AnnaBridge 171:3a7713b1edbc 4087 #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
AnnaBridge 171:3a7713b1edbc 4088
AnnaBridge 171:3a7713b1edbc 4089 #define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
AnnaBridge 171:3a7713b1edbc 4090 #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
AnnaBridge 171:3a7713b1edbc 4091
AnnaBridge 171:3a7713b1edbc 4092 #define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
AnnaBridge 171:3a7713b1edbc 4093 #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
AnnaBridge 171:3a7713b1edbc 4094
AnnaBridge 171:3a7713b1edbc 4095 #define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
AnnaBridge 171:3a7713b1edbc 4096 #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
AnnaBridge 171:3a7713b1edbc 4097
AnnaBridge 171:3a7713b1edbc 4098 #define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
AnnaBridge 171:3a7713b1edbc 4099 #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
AnnaBridge 171:3a7713b1edbc 4100
AnnaBridge 171:3a7713b1edbc 4101 #define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
AnnaBridge 171:3a7713b1edbc 4102 #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
AnnaBridge 171:3a7713b1edbc 4103
AnnaBridge 171:3a7713b1edbc 4104 #define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
AnnaBridge 171:3a7713b1edbc 4105 #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
AnnaBridge 171:3a7713b1edbc 4106
AnnaBridge 171:3a7713b1edbc 4107 #define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
AnnaBridge 171:3a7713b1edbc 4108 #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
AnnaBridge 171:3a7713b1edbc 4109
AnnaBridge 171:3a7713b1edbc 4110 #define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
AnnaBridge 171:3a7713b1edbc 4111 #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
AnnaBridge 171:3a7713b1edbc 4112
AnnaBridge 171:3a7713b1edbc 4113 #define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
AnnaBridge 171:3a7713b1edbc 4114 #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
AnnaBridge 171:3a7713b1edbc 4115
AnnaBridge 171:3a7713b1edbc 4116 #define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
AnnaBridge 171:3a7713b1edbc 4117 #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
AnnaBridge 171:3a7713b1edbc 4118
AnnaBridge 171:3a7713b1edbc 4119 #define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
AnnaBridge 171:3a7713b1edbc 4120 #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
AnnaBridge 171:3a7713b1edbc 4121
AnnaBridge 171:3a7713b1edbc 4122 #define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
AnnaBridge 171:3a7713b1edbc 4123 #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
AnnaBridge 171:3a7713b1edbc 4124
AnnaBridge 171:3a7713b1edbc 4125 #define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
AnnaBridge 171:3a7713b1edbc 4126 #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
AnnaBridge 171:3a7713b1edbc 4127
AnnaBridge 171:3a7713b1edbc 4128 #define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
AnnaBridge 171:3a7713b1edbc 4129 #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
AnnaBridge 171:3a7713b1edbc 4130
AnnaBridge 171:3a7713b1edbc 4131 #define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
AnnaBridge 171:3a7713b1edbc 4132 #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
AnnaBridge 171:3a7713b1edbc 4133
AnnaBridge 171:3a7713b1edbc 4134 #define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
AnnaBridge 171:3a7713b1edbc 4135 #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
AnnaBridge 171:3a7713b1edbc 4136
AnnaBridge 171:3a7713b1edbc 4137 #define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
AnnaBridge 171:3a7713b1edbc 4138 #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
AnnaBridge 171:3a7713b1edbc 4139
AnnaBridge 171:3a7713b1edbc 4140 #define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
AnnaBridge 171:3a7713b1edbc 4141 #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
AnnaBridge 171:3a7713b1edbc 4142
AnnaBridge 171:3a7713b1edbc 4143 #define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
AnnaBridge 171:3a7713b1edbc 4144 #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
AnnaBridge 171:3a7713b1edbc 4145
AnnaBridge 171:3a7713b1edbc 4146 #define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
AnnaBridge 171:3a7713b1edbc 4147 #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
AnnaBridge 171:3a7713b1edbc 4148
AnnaBridge 171:3a7713b1edbc 4149 #define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
AnnaBridge 171:3a7713b1edbc 4150 #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
AnnaBridge 171:3a7713b1edbc 4151
AnnaBridge 171:3a7713b1edbc 4152 #define GPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */
AnnaBridge 171:3a7713b1edbc 4153 #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */
AnnaBridge 171:3a7713b1edbc 4154
AnnaBridge 171:3a7713b1edbc 4155 #define GPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */
AnnaBridge 171:3a7713b1edbc 4156 #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */
AnnaBridge 171:3a7713b1edbc 4157
AnnaBridge 171:3a7713b1edbc 4158 #define GPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */
AnnaBridge 171:3a7713b1edbc 4159 #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */
AnnaBridge 171:3a7713b1edbc 4160
AnnaBridge 171:3a7713b1edbc 4161 #define GPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */
AnnaBridge 171:3a7713b1edbc 4162 #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */
AnnaBridge 171:3a7713b1edbc 4163
AnnaBridge 171:3a7713b1edbc 4164 #define GPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */
AnnaBridge 171:3a7713b1edbc 4165 #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */
AnnaBridge 171:3a7713b1edbc 4166
AnnaBridge 171:3a7713b1edbc 4167 #define GPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */
AnnaBridge 171:3a7713b1edbc 4168 #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */
AnnaBridge 171:3a7713b1edbc 4169
AnnaBridge 171:3a7713b1edbc 4170 #define GPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */
AnnaBridge 171:3a7713b1edbc 4171 #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */
AnnaBridge 171:3a7713b1edbc 4172
AnnaBridge 171:3a7713b1edbc 4173 #define GPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */
AnnaBridge 171:3a7713b1edbc 4174 #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */
AnnaBridge 171:3a7713b1edbc 4175
AnnaBridge 171:3a7713b1edbc 4176 #define GPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */
AnnaBridge 171:3a7713b1edbc 4177 #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */
AnnaBridge 171:3a7713b1edbc 4178
AnnaBridge 171:3a7713b1edbc 4179 #define GPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */
AnnaBridge 171:3a7713b1edbc 4180 #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */
AnnaBridge 171:3a7713b1edbc 4181
AnnaBridge 171:3a7713b1edbc 4182 #define GPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */
AnnaBridge 171:3a7713b1edbc 4183 #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */
AnnaBridge 171:3a7713b1edbc 4184
AnnaBridge 171:3a7713b1edbc 4185 #define GPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */
AnnaBridge 171:3a7713b1edbc 4186 #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */
AnnaBridge 171:3a7713b1edbc 4187
AnnaBridge 171:3a7713b1edbc 4188 #define GPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */
AnnaBridge 171:3a7713b1edbc 4189 #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */
AnnaBridge 171:3a7713b1edbc 4190
AnnaBridge 171:3a7713b1edbc 4191 #define GPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */
AnnaBridge 171:3a7713b1edbc 4192 #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */
AnnaBridge 171:3a7713b1edbc 4193
AnnaBridge 171:3a7713b1edbc 4194 #define GPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */
AnnaBridge 171:3a7713b1edbc 4195 #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */
AnnaBridge 171:3a7713b1edbc 4196
AnnaBridge 171:3a7713b1edbc 4197 #define GPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */
AnnaBridge 171:3a7713b1edbc 4198 #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */
AnnaBridge 171:3a7713b1edbc 4199
AnnaBridge 171:3a7713b1edbc 4200 #define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
AnnaBridge 171:3a7713b1edbc 4201 #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 4202
AnnaBridge 171:3a7713b1edbc 4203 #define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
AnnaBridge 171:3a7713b1edbc 4204 #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 4205
AnnaBridge 171:3a7713b1edbc 4206 #define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
AnnaBridge 171:3a7713b1edbc 4207 #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 4208
AnnaBridge 171:3a7713b1edbc 4209 #define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
AnnaBridge 171:3a7713b1edbc 4210 #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 4211
AnnaBridge 171:3a7713b1edbc 4212 #define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
AnnaBridge 171:3a7713b1edbc 4213 #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 4214
AnnaBridge 171:3a7713b1edbc 4215 #define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
AnnaBridge 171:3a7713b1edbc 4216 #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 4217
AnnaBridge 171:3a7713b1edbc 4218 #define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
AnnaBridge 171:3a7713b1edbc 4219 #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 4220
AnnaBridge 171:3a7713b1edbc 4221 #define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
AnnaBridge 171:3a7713b1edbc 4222 #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 4223
AnnaBridge 171:3a7713b1edbc 4224 #define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
AnnaBridge 171:3a7713b1edbc 4225 #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
AnnaBridge 171:3a7713b1edbc 4226
AnnaBridge 171:3a7713b1edbc 4227 #define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
AnnaBridge 171:3a7713b1edbc 4228 #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
AnnaBridge 171:3a7713b1edbc 4229
AnnaBridge 171:3a7713b1edbc 4230 #define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
AnnaBridge 171:3a7713b1edbc 4231 #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
AnnaBridge 171:3a7713b1edbc 4232
AnnaBridge 171:3a7713b1edbc 4233 #define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
AnnaBridge 171:3a7713b1edbc 4234 #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
AnnaBridge 171:3a7713b1edbc 4235
AnnaBridge 171:3a7713b1edbc 4236 #define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
AnnaBridge 171:3a7713b1edbc 4237 #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
AnnaBridge 171:3a7713b1edbc 4238
AnnaBridge 171:3a7713b1edbc 4239 #define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
AnnaBridge 171:3a7713b1edbc 4240 #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
AnnaBridge 171:3a7713b1edbc 4241
AnnaBridge 171:3a7713b1edbc 4242 #define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
AnnaBridge 171:3a7713b1edbc 4243 #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
AnnaBridge 171:3a7713b1edbc 4244
AnnaBridge 171:3a7713b1edbc 4245 #define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
AnnaBridge 171:3a7713b1edbc 4246 #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
AnnaBridge 171:3a7713b1edbc 4247
AnnaBridge 171:3a7713b1edbc 4248 #define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
AnnaBridge 171:3a7713b1edbc 4249 #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
AnnaBridge 171:3a7713b1edbc 4250
AnnaBridge 171:3a7713b1edbc 4251 #define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
AnnaBridge 171:3a7713b1edbc 4252 #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
AnnaBridge 171:3a7713b1edbc 4253
AnnaBridge 171:3a7713b1edbc 4254 #define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
AnnaBridge 171:3a7713b1edbc 4255 #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
AnnaBridge 171:3a7713b1edbc 4256
AnnaBridge 171:3a7713b1edbc 4257 #define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
AnnaBridge 171:3a7713b1edbc 4258 #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
AnnaBridge 171:3a7713b1edbc 4259
AnnaBridge 171:3a7713b1edbc 4260 #define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
AnnaBridge 171:3a7713b1edbc 4261 #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
AnnaBridge 171:3a7713b1edbc 4262
AnnaBridge 171:3a7713b1edbc 4263 #define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
AnnaBridge 171:3a7713b1edbc 4264 #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
AnnaBridge 171:3a7713b1edbc 4265
AnnaBridge 171:3a7713b1edbc 4266 #define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
AnnaBridge 171:3a7713b1edbc 4267 #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
AnnaBridge 171:3a7713b1edbc 4268
AnnaBridge 171:3a7713b1edbc 4269 #define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
AnnaBridge 171:3a7713b1edbc 4270 #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
AnnaBridge 171:3a7713b1edbc 4271
AnnaBridge 171:3a7713b1edbc 4272 #define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
AnnaBridge 171:3a7713b1edbc 4273 #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
AnnaBridge 171:3a7713b1edbc 4274
AnnaBridge 171:3a7713b1edbc 4275 #define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
AnnaBridge 171:3a7713b1edbc 4276 #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
AnnaBridge 171:3a7713b1edbc 4277
AnnaBridge 171:3a7713b1edbc 4278 #define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
AnnaBridge 171:3a7713b1edbc 4279 #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
AnnaBridge 171:3a7713b1edbc 4280
AnnaBridge 171:3a7713b1edbc 4281 #define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
AnnaBridge 171:3a7713b1edbc 4282 #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
AnnaBridge 171:3a7713b1edbc 4283
AnnaBridge 171:3a7713b1edbc 4284 #define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
AnnaBridge 171:3a7713b1edbc 4285 #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
AnnaBridge 171:3a7713b1edbc 4286
AnnaBridge 171:3a7713b1edbc 4287 #define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
AnnaBridge 171:3a7713b1edbc 4288 #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
AnnaBridge 171:3a7713b1edbc 4289
AnnaBridge 171:3a7713b1edbc 4290 #define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
AnnaBridge 171:3a7713b1edbc 4291 #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
AnnaBridge 171:3a7713b1edbc 4292
AnnaBridge 171:3a7713b1edbc 4293 #define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
AnnaBridge 171:3a7713b1edbc 4294 #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
AnnaBridge 171:3a7713b1edbc 4295
AnnaBridge 171:3a7713b1edbc 4296 #define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
AnnaBridge 171:3a7713b1edbc 4297 #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
AnnaBridge 171:3a7713b1edbc 4298
AnnaBridge 171:3a7713b1edbc 4299 #define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
AnnaBridge 171:3a7713b1edbc 4300 #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
AnnaBridge 171:3a7713b1edbc 4301
AnnaBridge 171:3a7713b1edbc 4302 #define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
AnnaBridge 171:3a7713b1edbc 4303 #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
AnnaBridge 171:3a7713b1edbc 4304
AnnaBridge 171:3a7713b1edbc 4305 #define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
AnnaBridge 171:3a7713b1edbc 4306 #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
AnnaBridge 171:3a7713b1edbc 4307
AnnaBridge 171:3a7713b1edbc 4308 #define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
AnnaBridge 171:3a7713b1edbc 4309 #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
AnnaBridge 171:3a7713b1edbc 4310
AnnaBridge 171:3a7713b1edbc 4311 #define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
AnnaBridge 171:3a7713b1edbc 4312 #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
AnnaBridge 171:3a7713b1edbc 4313
AnnaBridge 171:3a7713b1edbc 4314 #define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
AnnaBridge 171:3a7713b1edbc 4315 #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
AnnaBridge 171:3a7713b1edbc 4316
AnnaBridge 171:3a7713b1edbc 4317 #define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
AnnaBridge 171:3a7713b1edbc 4318 #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
AnnaBridge 171:3a7713b1edbc 4319
AnnaBridge 171:3a7713b1edbc 4320 #define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
AnnaBridge 171:3a7713b1edbc 4321 #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
AnnaBridge 171:3a7713b1edbc 4322
AnnaBridge 171:3a7713b1edbc 4323 #define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
AnnaBridge 171:3a7713b1edbc 4324 #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
AnnaBridge 171:3a7713b1edbc 4325
AnnaBridge 171:3a7713b1edbc 4326 #define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
AnnaBridge 171:3a7713b1edbc 4327 #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
AnnaBridge 171:3a7713b1edbc 4328
AnnaBridge 171:3a7713b1edbc 4329 #define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
AnnaBridge 171:3a7713b1edbc 4330 #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
AnnaBridge 171:3a7713b1edbc 4331
AnnaBridge 171:3a7713b1edbc 4332 #define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
AnnaBridge 171:3a7713b1edbc 4333 #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
AnnaBridge 171:3a7713b1edbc 4334
AnnaBridge 171:3a7713b1edbc 4335 #define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
AnnaBridge 171:3a7713b1edbc 4336 #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
AnnaBridge 171:3a7713b1edbc 4337
AnnaBridge 171:3a7713b1edbc 4338 #define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
AnnaBridge 171:3a7713b1edbc 4339 #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
AnnaBridge 171:3a7713b1edbc 4340
AnnaBridge 171:3a7713b1edbc 4341 #define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
AnnaBridge 171:3a7713b1edbc 4342 #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
AnnaBridge 171:3a7713b1edbc 4343
AnnaBridge 171:3a7713b1edbc 4344 #define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
AnnaBridge 171:3a7713b1edbc 4345 #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 4346
AnnaBridge 171:3a7713b1edbc 4347 #define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
AnnaBridge 171:3a7713b1edbc 4348 #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 4349
AnnaBridge 171:3a7713b1edbc 4350 #define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
AnnaBridge 171:3a7713b1edbc 4351 #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 4352
AnnaBridge 171:3a7713b1edbc 4353 #define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
AnnaBridge 171:3a7713b1edbc 4354 #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 4355
AnnaBridge 171:3a7713b1edbc 4356 #define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
AnnaBridge 171:3a7713b1edbc 4357 #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 4358
AnnaBridge 171:3a7713b1edbc 4359 #define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
AnnaBridge 171:3a7713b1edbc 4360 #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 4361
AnnaBridge 171:3a7713b1edbc 4362 #define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
AnnaBridge 171:3a7713b1edbc 4363 #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
AnnaBridge 171:3a7713b1edbc 4364
AnnaBridge 171:3a7713b1edbc 4365 #define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
AnnaBridge 171:3a7713b1edbc 4366 #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
AnnaBridge 171:3a7713b1edbc 4367
AnnaBridge 171:3a7713b1edbc 4368 #define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
AnnaBridge 171:3a7713b1edbc 4369 #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
AnnaBridge 171:3a7713b1edbc 4370
AnnaBridge 171:3a7713b1edbc 4371 #define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
AnnaBridge 171:3a7713b1edbc 4372 #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
AnnaBridge 171:3a7713b1edbc 4373
AnnaBridge 171:3a7713b1edbc 4374 #define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
AnnaBridge 171:3a7713b1edbc 4375 #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
AnnaBridge 171:3a7713b1edbc 4376
AnnaBridge 171:3a7713b1edbc 4377 #define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
AnnaBridge 171:3a7713b1edbc 4378 #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
AnnaBridge 171:3a7713b1edbc 4379
AnnaBridge 171:3a7713b1edbc 4380 #define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
AnnaBridge 171:3a7713b1edbc 4381 #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
AnnaBridge 171:3a7713b1edbc 4382
AnnaBridge 171:3a7713b1edbc 4383 #define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
AnnaBridge 171:3a7713b1edbc 4384 #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
AnnaBridge 171:3a7713b1edbc 4385
AnnaBridge 171:3a7713b1edbc 4386 #define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
AnnaBridge 171:3a7713b1edbc 4387 #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
AnnaBridge 171:3a7713b1edbc 4388
AnnaBridge 171:3a7713b1edbc 4389 #define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
AnnaBridge 171:3a7713b1edbc 4390 #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
AnnaBridge 171:3a7713b1edbc 4391
AnnaBridge 171:3a7713b1edbc 4392 #define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
AnnaBridge 171:3a7713b1edbc 4393 #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 4394
AnnaBridge 171:3a7713b1edbc 4395 #define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
AnnaBridge 171:3a7713b1edbc 4396 #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 4397
AnnaBridge 171:3a7713b1edbc 4398 #define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
AnnaBridge 171:3a7713b1edbc 4399 #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 4400
AnnaBridge 171:3a7713b1edbc 4401 #define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
AnnaBridge 171:3a7713b1edbc 4402 #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 4403
AnnaBridge 171:3a7713b1edbc 4404 #define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
AnnaBridge 171:3a7713b1edbc 4405 #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 4406
AnnaBridge 171:3a7713b1edbc 4407 #define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
AnnaBridge 171:3a7713b1edbc 4408 #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 4409
AnnaBridge 171:3a7713b1edbc 4410 #define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
AnnaBridge 171:3a7713b1edbc 4411 #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
AnnaBridge 171:3a7713b1edbc 4412
AnnaBridge 171:3a7713b1edbc 4413 #define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
AnnaBridge 171:3a7713b1edbc 4414 #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
AnnaBridge 171:3a7713b1edbc 4415
AnnaBridge 171:3a7713b1edbc 4416 #define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
AnnaBridge 171:3a7713b1edbc 4417 #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
AnnaBridge 171:3a7713b1edbc 4418
AnnaBridge 171:3a7713b1edbc 4419 #define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
AnnaBridge 171:3a7713b1edbc 4420 #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
AnnaBridge 171:3a7713b1edbc 4421
AnnaBridge 171:3a7713b1edbc 4422 #define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
AnnaBridge 171:3a7713b1edbc 4423 #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
AnnaBridge 171:3a7713b1edbc 4424
AnnaBridge 171:3a7713b1edbc 4425 #define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
AnnaBridge 171:3a7713b1edbc 4426 #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
AnnaBridge 171:3a7713b1edbc 4427
AnnaBridge 171:3a7713b1edbc 4428 #define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
AnnaBridge 171:3a7713b1edbc 4429 #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
AnnaBridge 171:3a7713b1edbc 4430
AnnaBridge 171:3a7713b1edbc 4431 #define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
AnnaBridge 171:3a7713b1edbc 4432 #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
AnnaBridge 171:3a7713b1edbc 4433
AnnaBridge 171:3a7713b1edbc 4434 #define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
AnnaBridge 171:3a7713b1edbc 4435 #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
AnnaBridge 171:3a7713b1edbc 4436
AnnaBridge 171:3a7713b1edbc 4437 #define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
AnnaBridge 171:3a7713b1edbc 4438 #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
AnnaBridge 171:3a7713b1edbc 4439
AnnaBridge 171:3a7713b1edbc 4440 #define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
AnnaBridge 171:3a7713b1edbc 4441 #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
AnnaBridge 171:3a7713b1edbc 4442
AnnaBridge 171:3a7713b1edbc 4443 #define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
AnnaBridge 171:3a7713b1edbc 4444 #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
AnnaBridge 171:3a7713b1edbc 4445
AnnaBridge 171:3a7713b1edbc 4446 #define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
AnnaBridge 171:3a7713b1edbc 4447 #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
AnnaBridge 171:3a7713b1edbc 4448
AnnaBridge 171:3a7713b1edbc 4449 #define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
AnnaBridge 171:3a7713b1edbc 4450 #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
AnnaBridge 171:3a7713b1edbc 4451
AnnaBridge 171:3a7713b1edbc 4452 #define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
AnnaBridge 171:3a7713b1edbc 4453 #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
AnnaBridge 171:3a7713b1edbc 4454
AnnaBridge 171:3a7713b1edbc 4455 #define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
AnnaBridge 171:3a7713b1edbc 4456 #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
AnnaBridge 171:3a7713b1edbc 4457
AnnaBridge 171:3a7713b1edbc 4458 #define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
AnnaBridge 171:3a7713b1edbc 4459 #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
AnnaBridge 171:3a7713b1edbc 4460
AnnaBridge 171:3a7713b1edbc 4461 #define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
AnnaBridge 171:3a7713b1edbc 4462 #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
AnnaBridge 171:3a7713b1edbc 4463
AnnaBridge 171:3a7713b1edbc 4464 #define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
AnnaBridge 171:3a7713b1edbc 4465 #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
AnnaBridge 171:3a7713b1edbc 4466
AnnaBridge 171:3a7713b1edbc 4467 #define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
AnnaBridge 171:3a7713b1edbc 4468 #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
AnnaBridge 171:3a7713b1edbc 4469
AnnaBridge 171:3a7713b1edbc 4470 #define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
AnnaBridge 171:3a7713b1edbc 4471 #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
AnnaBridge 171:3a7713b1edbc 4472
AnnaBridge 171:3a7713b1edbc 4473 #define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
AnnaBridge 171:3a7713b1edbc 4474 #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
AnnaBridge 171:3a7713b1edbc 4475
AnnaBridge 171:3a7713b1edbc 4476 #define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
AnnaBridge 171:3a7713b1edbc 4477 #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
AnnaBridge 171:3a7713b1edbc 4478
AnnaBridge 171:3a7713b1edbc 4479 #define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
AnnaBridge 171:3a7713b1edbc 4480 #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
AnnaBridge 171:3a7713b1edbc 4481
AnnaBridge 171:3a7713b1edbc 4482 #define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
AnnaBridge 171:3a7713b1edbc 4483 #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
AnnaBridge 171:3a7713b1edbc 4484
AnnaBridge 171:3a7713b1edbc 4485 #define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
AnnaBridge 171:3a7713b1edbc 4486 #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
AnnaBridge 171:3a7713b1edbc 4487
AnnaBridge 171:3a7713b1edbc 4488 #define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
AnnaBridge 171:3a7713b1edbc 4489 #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
AnnaBridge 171:3a7713b1edbc 4490
AnnaBridge 171:3a7713b1edbc 4491 #define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
AnnaBridge 171:3a7713b1edbc 4492 #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
AnnaBridge 171:3a7713b1edbc 4493
AnnaBridge 171:3a7713b1edbc 4494 #define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
AnnaBridge 171:3a7713b1edbc 4495 #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
AnnaBridge 171:3a7713b1edbc 4496
AnnaBridge 171:3a7713b1edbc 4497 #define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
AnnaBridge 171:3a7713b1edbc 4498 #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
AnnaBridge 171:3a7713b1edbc 4499
AnnaBridge 171:3a7713b1edbc 4500 #define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
AnnaBridge 171:3a7713b1edbc 4501 #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
AnnaBridge 171:3a7713b1edbc 4502
AnnaBridge 171:3a7713b1edbc 4503 #define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
AnnaBridge 171:3a7713b1edbc 4504 #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
AnnaBridge 171:3a7713b1edbc 4505
AnnaBridge 171:3a7713b1edbc 4506 #define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
AnnaBridge 171:3a7713b1edbc 4507 #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
AnnaBridge 171:3a7713b1edbc 4508
AnnaBridge 171:3a7713b1edbc 4509 #define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
AnnaBridge 171:3a7713b1edbc 4510 #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
AnnaBridge 171:3a7713b1edbc 4511
AnnaBridge 171:3a7713b1edbc 4512 #define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
AnnaBridge 171:3a7713b1edbc 4513 #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
AnnaBridge 171:3a7713b1edbc 4514
AnnaBridge 171:3a7713b1edbc 4515 #define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
AnnaBridge 171:3a7713b1edbc 4516 #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
AnnaBridge 171:3a7713b1edbc 4517
AnnaBridge 171:3a7713b1edbc 4518 #define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
AnnaBridge 171:3a7713b1edbc 4519 #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
AnnaBridge 171:3a7713b1edbc 4520
AnnaBridge 171:3a7713b1edbc 4521 #define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
AnnaBridge 171:3a7713b1edbc 4522 #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
AnnaBridge 171:3a7713b1edbc 4523
AnnaBridge 171:3a7713b1edbc 4524 #define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
AnnaBridge 171:3a7713b1edbc 4525 #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
AnnaBridge 171:3a7713b1edbc 4526
AnnaBridge 171:3a7713b1edbc 4527 #define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
AnnaBridge 171:3a7713b1edbc 4528 #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
AnnaBridge 171:3a7713b1edbc 4529
AnnaBridge 171:3a7713b1edbc 4530 #define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
AnnaBridge 171:3a7713b1edbc 4531 #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
AnnaBridge 171:3a7713b1edbc 4532
AnnaBridge 171:3a7713b1edbc 4533 #define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
AnnaBridge 171:3a7713b1edbc 4534 #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
AnnaBridge 171:3a7713b1edbc 4535
AnnaBridge 171:3a7713b1edbc 4536 #define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
AnnaBridge 171:3a7713b1edbc 4537 #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
AnnaBridge 171:3a7713b1edbc 4538
AnnaBridge 171:3a7713b1edbc 4539 #define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
AnnaBridge 171:3a7713b1edbc 4540 #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
AnnaBridge 171:3a7713b1edbc 4541
AnnaBridge 171:3a7713b1edbc 4542 #define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
AnnaBridge 171:3a7713b1edbc 4543 #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
AnnaBridge 171:3a7713b1edbc 4544
AnnaBridge 171:3a7713b1edbc 4545 #define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
AnnaBridge 171:3a7713b1edbc 4546 #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
AnnaBridge 171:3a7713b1edbc 4547
AnnaBridge 171:3a7713b1edbc 4548 #define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
AnnaBridge 171:3a7713b1edbc 4549 #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
AnnaBridge 171:3a7713b1edbc 4550
AnnaBridge 171:3a7713b1edbc 4551 #define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
AnnaBridge 171:3a7713b1edbc 4552 #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
AnnaBridge 171:3a7713b1edbc 4553
AnnaBridge 171:3a7713b1edbc 4554 #define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
AnnaBridge 171:3a7713b1edbc 4555 #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
AnnaBridge 171:3a7713b1edbc 4556
AnnaBridge 171:3a7713b1edbc 4557 #define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
AnnaBridge 171:3a7713b1edbc 4558 #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
AnnaBridge 171:3a7713b1edbc 4559
AnnaBridge 171:3a7713b1edbc 4560 #define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
AnnaBridge 171:3a7713b1edbc 4561 #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
AnnaBridge 171:3a7713b1edbc 4562
AnnaBridge 171:3a7713b1edbc 4563 #define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
AnnaBridge 171:3a7713b1edbc 4564 #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
AnnaBridge 171:3a7713b1edbc 4565
AnnaBridge 171:3a7713b1edbc 4566 #define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
AnnaBridge 171:3a7713b1edbc 4567 #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
AnnaBridge 171:3a7713b1edbc 4568
AnnaBridge 171:3a7713b1edbc 4569 #define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
AnnaBridge 171:3a7713b1edbc 4570 #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
AnnaBridge 171:3a7713b1edbc 4571
AnnaBridge 171:3a7713b1edbc 4572 #define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
AnnaBridge 171:3a7713b1edbc 4573 #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
AnnaBridge 171:3a7713b1edbc 4574
AnnaBridge 171:3a7713b1edbc 4575 #define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
AnnaBridge 171:3a7713b1edbc 4576 #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
AnnaBridge 171:3a7713b1edbc 4577
AnnaBridge 171:3a7713b1edbc 4578 #define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
AnnaBridge 171:3a7713b1edbc 4579 #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
AnnaBridge 171:3a7713b1edbc 4580
AnnaBridge 171:3a7713b1edbc 4581 #define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
AnnaBridge 171:3a7713b1edbc 4582 #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
AnnaBridge 171:3a7713b1edbc 4583
AnnaBridge 171:3a7713b1edbc 4584 #define GPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */
AnnaBridge 171:3a7713b1edbc 4585 #define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */
AnnaBridge 171:3a7713b1edbc 4586
AnnaBridge 171:3a7713b1edbc 4587 #define GPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */
AnnaBridge 171:3a7713b1edbc 4588 #define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */
AnnaBridge 171:3a7713b1edbc 4589
AnnaBridge 171:3a7713b1edbc 4590 #define GPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */
AnnaBridge 171:3a7713b1edbc 4591 #define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */
AnnaBridge 171:3a7713b1edbc 4592
AnnaBridge 171:3a7713b1edbc 4593 #define GPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */
AnnaBridge 171:3a7713b1edbc 4594 #define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */
AnnaBridge 171:3a7713b1edbc 4595
AnnaBridge 171:3a7713b1edbc 4596 #define GPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */
AnnaBridge 171:3a7713b1edbc 4597 #define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */
AnnaBridge 171:3a7713b1edbc 4598
AnnaBridge 171:3a7713b1edbc 4599 #define GPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */
AnnaBridge 171:3a7713b1edbc 4600 #define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */
AnnaBridge 171:3a7713b1edbc 4601
AnnaBridge 171:3a7713b1edbc 4602 #define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
AnnaBridge 171:3a7713b1edbc 4603 #define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
AnnaBridge 171:3a7713b1edbc 4604
AnnaBridge 171:3a7713b1edbc 4605 #define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
AnnaBridge 171:3a7713b1edbc 4606 #define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
AnnaBridge 171:3a7713b1edbc 4607
AnnaBridge 171:3a7713b1edbc 4608 #define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
AnnaBridge 171:3a7713b1edbc 4609 #define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
AnnaBridge 171:3a7713b1edbc 4610
AnnaBridge 171:3a7713b1edbc 4611
AnnaBridge 171:3a7713b1edbc 4612 /**@}*/ /* GPIO_CONST */
AnnaBridge 171:3a7713b1edbc 4613 /**@}*/ /* end of GPIO register group */
AnnaBridge 171:3a7713b1edbc 4614
AnnaBridge 171:3a7713b1edbc 4615
AnnaBridge 171:3a7713b1edbc 4616 /*---------------------- Inter-IC Bus Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 4617 /**
AnnaBridge 171:3a7713b1edbc 4618 @addtogroup I2C Inter-IC Bus Controller(I2C)
AnnaBridge 171:3a7713b1edbc 4619 Memory Mapped Structure for I2C Controller
AnnaBridge 171:3a7713b1edbc 4620 @{ */
AnnaBridge 171:3a7713b1edbc 4621
AnnaBridge 171:3a7713b1edbc 4622
AnnaBridge 171:3a7713b1edbc 4623 typedef struct
AnnaBridge 171:3a7713b1edbc 4624 {
AnnaBridge 171:3a7713b1edbc 4625
AnnaBridge 171:3a7713b1edbc 4626
AnnaBridge 171:3a7713b1edbc 4627
AnnaBridge 171:3a7713b1edbc 4628
AnnaBridge 171:3a7713b1edbc 4629 /**
AnnaBridge 171:3a7713b1edbc 4630 * @var I2C_T::CTL
AnnaBridge 171:3a7713b1edbc 4631 * Offset: 0x00 I2C Control Register
AnnaBridge 171:3a7713b1edbc 4632 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4633 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4634 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4635 * |[2] |AA |Assert Acknowledge Control
AnnaBridge 171:3a7713b1edbc 4636 * | | |When AA =1 prior to address or data is received,
AnnaBridge 171:3a7713b1edbc 4637 * | | |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
AnnaBridge 171:3a7713b1edbc 4638 * | | |1. A slave is acknowledging the address sent from master.
AnnaBridge 171:3a7713b1edbc 4639 * | | |2. The receiver devices are acknowledging the data sent by transmitter.
AnnaBridge 171:3a7713b1edbc 4640 * | | |When AA=0 prior to address or data received,
AnnaBridge 171:3a7713b1edbc 4641 * | | |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
AnnaBridge 171:3a7713b1edbc 4642 * |[3] |SI |I2C Interrupt Flag
AnnaBridge 171:3a7713b1edbc 4643 * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
AnnaBridge 171:3a7713b1edbc 4644 * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
AnnaBridge 171:3a7713b1edbc 4645 * | | |SI must be cleared by software.
AnnaBridge 171:3a7713b1edbc 4646 * | | |Clear SI by writing 1 to this bit.
AnnaBridge 171:3a7713b1edbc 4647 * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
AnnaBridge 171:3a7713b1edbc 4648 * |[4] |STO |I2C STOP Control
AnnaBridge 171:3a7713b1edbc 4649 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
AnnaBridge 171:3a7713b1edbc 4650 * | | |This bit will be cleared by hardware automatically.
AnnaBridge 171:3a7713b1edbc 4651 * |[5] |STA |I2C START Control
AnnaBridge 171:3a7713b1edbc 4652 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
AnnaBridge 171:3a7713b1edbc 4653 * |[6] |I2CEN |I2C Controller Enable Bit
AnnaBridge 171:3a7713b1edbc 4654 * | | |Set to enable I2C serial function controller.
AnnaBridge 171:3a7713b1edbc 4655 * | | |When I2CEN=1 the I2C serial function enable.
AnnaBridge 171:3a7713b1edbc 4656 * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
AnnaBridge 171:3a7713b1edbc 4657 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 4658 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 4659 * |[7] |INTEN |Enable Interrupt
AnnaBridge 171:3a7713b1edbc 4660 * | | |0 = I2C interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 4661 * | | |1 = I2C interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 4662 * @var I2C_T::ADDR0
AnnaBridge 171:3a7713b1edbc 4663 * Offset: 0x04 I2C Slave Address Register0
AnnaBridge 171:3a7713b1edbc 4664 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4665 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4666 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4667 * |[0] |GC |General Call Function
AnnaBridge 171:3a7713b1edbc 4668 * | | |0 = General Call Function Disabled.
AnnaBridge 171:3a7713b1edbc 4669 * | | |1 = General Call Function Enabled.
AnnaBridge 171:3a7713b1edbc 4670 * |[7:1] |ADDR |I2C Address
AnnaBridge 171:3a7713b1edbc 4671 * | | |The content of this register is irrelevant when I2C is in Master mode.
AnnaBridge 171:3a7713b1edbc 4672 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
AnnaBridge 171:3a7713b1edbc 4673 * | | |The I2C hardware will react if either of the address is matched.
AnnaBridge 171:3a7713b1edbc 4674 * @var I2C_T::DAT
AnnaBridge 171:3a7713b1edbc 4675 * Offset: 0x08 I2C Data Register
AnnaBridge 171:3a7713b1edbc 4676 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4677 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4678 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4679 * |[7:0] |DAT |I2C Data
AnnaBridge 171:3a7713b1edbc 4680 * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
AnnaBridge 171:3a7713b1edbc 4681 * @var I2C_T::STATUS
AnnaBridge 171:3a7713b1edbc 4682 * Offset: 0x0C I2C Status Register
AnnaBridge 171:3a7713b1edbc 4683 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4684 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4685 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4686 * |[7:0] |STATUS |I2C Status
AnnaBridge 171:3a7713b1edbc 4687 * | | |The three least significant bits are always 0.
AnnaBridge 171:3a7713b1edbc 4688 * | | |The five most significant bits contain the status code.
AnnaBridge 171:3a7713b1edbc 4689 * | | |There are 28 possible status codes.
AnnaBridge 171:3a7713b1edbc 4690 * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
AnnaBridge 171:3a7713b1edbc 4691 * | | |Others I2C_STATUS values correspond to defined I2C states.
AnnaBridge 171:3a7713b1edbc 4692 * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
AnnaBridge 171:3a7713b1edbc 4693 * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
AnnaBridge 171:3a7713b1edbc 4694 * | | |In addition, states 00H stands for a Bus Error.
AnnaBridge 171:3a7713b1edbc 4695 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
AnnaBridge 171:3a7713b1edbc 4696 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
AnnaBridge 171:3a7713b1edbc 4697 * | | |Note:
AnnaBridge 171:3a7713b1edbc 4698 * | | |1.
AnnaBridge 171:3a7713b1edbc 4699 * | | |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
AnnaBridge 171:3a7713b1edbc 4700 * | | |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
AnnaBridge 171:3a7713b1edbc 4701 * | | |2.
AnnaBridge 171:3a7713b1edbc 4702 * | | |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
AnnaBridge 171:3a7713b1edbc 4703 * @var I2C_T::CLKDIV
AnnaBridge 171:3a7713b1edbc 4704 * Offset: 0x10 I2C Clock Divided Register
AnnaBridge 171:3a7713b1edbc 4705 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4706 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4707 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4708 * |[7:0] |DIVIDER |I2C Clock Divided
AnnaBridge 171:3a7713b1edbc 4709 * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
AnnaBridge 171:3a7713b1edbc 4710 * | | |Note: The minimum value of I2C_CLKDIV is 4.
AnnaBridge 171:3a7713b1edbc 4711 * @var I2C_T::TOCTL
AnnaBridge 171:3a7713b1edbc 4712 * Offset: 0x14 I2C Time-out Control Register
AnnaBridge 171:3a7713b1edbc 4713 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4714 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4715 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4716 * |[0] |TOIF |Time-Out Flag
AnnaBridge 171:3a7713b1edbc 4717 * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
AnnaBridge 171:3a7713b1edbc 4718 * | | |Note: Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4719 * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
AnnaBridge 171:3a7713b1edbc 4720 * | | |When Enabled, The time-out period is extend 4 times.
AnnaBridge 171:3a7713b1edbc 4721 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 4722 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 4723 * |[2] |TOCEN |Time-Out Counter Enable Bit
AnnaBridge 171:3a7713b1edbc 4724 * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
AnnaBridge 171:3a7713b1edbc 4725 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
AnnaBridge 171:3a7713b1edbc 4726 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 4727 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 4728 * @var I2C_T::ADDR1
AnnaBridge 171:3a7713b1edbc 4729 * Offset: 0x18 I2C Slave Address Register1
AnnaBridge 171:3a7713b1edbc 4730 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4731 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4732 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4733 * |[0] |GC |General Call Function
AnnaBridge 171:3a7713b1edbc 4734 * | | |0 = General Call Function Disabled.
AnnaBridge 171:3a7713b1edbc 4735 * | | |1 = General Call Function Enabled.
AnnaBridge 171:3a7713b1edbc 4736 * |[7:1] |ADDR |I2C Address
AnnaBridge 171:3a7713b1edbc 4737 * | | |The content of this register is irrelevant when I2C is in Master mode.
AnnaBridge 171:3a7713b1edbc 4738 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
AnnaBridge 171:3a7713b1edbc 4739 * | | |The I2C hardware will react if either of the address is matched.
AnnaBridge 171:3a7713b1edbc 4740 * @var I2C_T::ADDR2
AnnaBridge 171:3a7713b1edbc 4741 * Offset: 0x1C I2C Slave Address Register2
AnnaBridge 171:3a7713b1edbc 4742 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4743 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4744 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4745 * |[0] |GC |General Call Function
AnnaBridge 171:3a7713b1edbc 4746 * | | |0 = General Call Function Disabled.
AnnaBridge 171:3a7713b1edbc 4747 * | | |1 = General Call Function Enabled.
AnnaBridge 171:3a7713b1edbc 4748 * |[7:1] |ADDR |I2C Address
AnnaBridge 171:3a7713b1edbc 4749 * | | |The content of this register is irrelevant when I2C is in Master mode.
AnnaBridge 171:3a7713b1edbc 4750 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
AnnaBridge 171:3a7713b1edbc 4751 * | | |The I2C hardware will react if either of the address is matched.
AnnaBridge 171:3a7713b1edbc 4752 * @var I2C_T::ADDR3
AnnaBridge 171:3a7713b1edbc 4753 * Offset: 0x20 I2C Slave Address Register3
AnnaBridge 171:3a7713b1edbc 4754 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4755 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4756 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4757 * |[0] |GC |General Call Function
AnnaBridge 171:3a7713b1edbc 4758 * | | |0 = General Call Function Disabled.
AnnaBridge 171:3a7713b1edbc 4759 * | | |1 = General Call Function Enabled.
AnnaBridge 171:3a7713b1edbc 4760 * |[7:1] |ADDR |I2C Address
AnnaBridge 171:3a7713b1edbc 4761 * | | |The content of this register is irrelevant when I2C is in Master mode.
AnnaBridge 171:3a7713b1edbc 4762 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
AnnaBridge 171:3a7713b1edbc 4763 * | | |The I2C hardware will react if either of the address is matched.
AnnaBridge 171:3a7713b1edbc 4764 * @var I2C_T::ADDRMSK0
AnnaBridge 171:3a7713b1edbc 4765 * Offset: 0x24 I2C Slave Address Mask Register0
AnnaBridge 171:3a7713b1edbc 4766 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4767 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4768 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4769 * |[7:1] |ADDRMSK |I2C Address Mask
AnnaBridge 171:3a7713b1edbc 4770 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
AnnaBridge 171:3a7713b1edbc 4771 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
AnnaBridge 171:3a7713b1edbc 4772 * | | |I2C bus controllers support multiple address recognition with four address mask register.
AnnaBridge 171:3a7713b1edbc 4773 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
AnnaBridge 171:3a7713b1edbc 4774 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
AnnaBridge 171:3a7713b1edbc 4775 * @var I2C_T::ADDRMSK1
AnnaBridge 171:3a7713b1edbc 4776 * Offset: 0x28 I2C Slave Address Mask Register1
AnnaBridge 171:3a7713b1edbc 4777 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4778 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4779 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4780 * |[7:1] |ADDRMSK |I2C Address Mask
AnnaBridge 171:3a7713b1edbc 4781 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
AnnaBridge 171:3a7713b1edbc 4782 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
AnnaBridge 171:3a7713b1edbc 4783 * | | |I2C bus controllers support multiple address recognition with four address mask register.
AnnaBridge 171:3a7713b1edbc 4784 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
AnnaBridge 171:3a7713b1edbc 4785 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
AnnaBridge 171:3a7713b1edbc 4786 * @var I2C_T::ADDRMSK2
AnnaBridge 171:3a7713b1edbc 4787 * Offset: 0x2C I2C Slave Address Mask Register2
AnnaBridge 171:3a7713b1edbc 4788 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4789 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4790 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4791 * |[7:1] |ADDRMSK |I2C Address Mask
AnnaBridge 171:3a7713b1edbc 4792 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
AnnaBridge 171:3a7713b1edbc 4793 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
AnnaBridge 171:3a7713b1edbc 4794 * | | |I2C bus controllers support multiple address recognition with four address mask register.
AnnaBridge 171:3a7713b1edbc 4795 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
AnnaBridge 171:3a7713b1edbc 4796 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
AnnaBridge 171:3a7713b1edbc 4797 * @var I2C_T::ADDRMSK3
AnnaBridge 171:3a7713b1edbc 4798 * Offset: 0x30 I2C Slave Address Mask Register3
AnnaBridge 171:3a7713b1edbc 4799 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4800 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4801 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4802 * |[7:1] |ADDRMSK |I2C Address Mask
AnnaBridge 171:3a7713b1edbc 4803 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
AnnaBridge 171:3a7713b1edbc 4804 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
AnnaBridge 171:3a7713b1edbc 4805 * | | |I2C bus controllers support multiple address recognition with four address mask register.
AnnaBridge 171:3a7713b1edbc 4806 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
AnnaBridge 171:3a7713b1edbc 4807 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
AnnaBridge 171:3a7713b1edbc 4808 * @var I2C_T::WKCTL
AnnaBridge 171:3a7713b1edbc 4809 * Offset: 0x3C I2C Wake-up Control Register
AnnaBridge 171:3a7713b1edbc 4810 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4811 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4812 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4813 * |[0] |WKEN |I2C Wake-Up Enable Bit
AnnaBridge 171:3a7713b1edbc 4814 * | | |0 = I2C wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 4815 * | | |1= I2C wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 4816 * @var I2C_T::WKSTS
AnnaBridge 171:3a7713b1edbc 4817 * Offset: 0x40 I2C Wake-up Status Register
AnnaBridge 171:3a7713b1edbc 4818 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4819 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4820 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4821 * |[0] |WKIF |I2C Wake-Up Flag
AnnaBridge 171:3a7713b1edbc 4822 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 4823 * | | |Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4824 * @var I2C_T::BUSCTL
AnnaBridge 171:3a7713b1edbc 4825 * Offset: 0x44 I2C Bus Management Control Register
AnnaBridge 171:3a7713b1edbc 4826 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4827 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4828 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4829 * |[0] |ACKMEN |Acknowledge Control By Manual
AnnaBridge 171:3a7713b1edbc 4830 * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
AnnaBridge 171:3a7713b1edbc 4831 * | | |0 = Slave byte control Disabled.
AnnaBridge 171:3a7713b1edbc 4832 * | | |1 = Slave byte control Enabled.
AnnaBridge 171:3a7713b1edbc 4833 * | | |The 9th bit can response the ACK or NACK according the received data by user.
AnnaBridge 171:3a7713b1edbc 4834 * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
AnnaBridge 171:3a7713b1edbc 4835 * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
AnnaBridge 171:3a7713b1edbc 4836 * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
AnnaBridge 171:3a7713b1edbc 4837 * | | |0 = Packet Error Checking Calculation Disabled.
AnnaBridge 171:3a7713b1edbc 4838 * | | |1 = Packet Error Checking Calculation Enabled.
AnnaBridge 171:3a7713b1edbc 4839 * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
AnnaBridge 171:3a7713b1edbc 4840 * | | |0 = Device default address Disable.
AnnaBridge 171:3a7713b1edbc 4841 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
AnnaBridge 171:3a7713b1edbc 4842 * | | |1 = Device default address Enabled.
AnnaBridge 171:3a7713b1edbc 4843 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
AnnaBridge 171:3a7713b1edbc 4844 * |[3] |BMHEN |Bus Management Host Enable Bit
AnnaBridge 171:3a7713b1edbc 4845 * | | |0 = Host function Disabled.
AnnaBridge 171:3a7713b1edbc 4846 * | | |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
AnnaBridge 171:3a7713b1edbc 4847 * |[4] |ALERTEN |Bus Management Alert Enable Bit
AnnaBridge 171:3a7713b1edbc 4848 * | | |Device Mode (BMHEN =0).
AnnaBridge 171:3a7713b1edbc 4849 * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
AnnaBridge 171:3a7713b1edbc 4850 * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
AnnaBridge 171:3a7713b1edbc 4851 * | | |Host Mode (BMHEN =1).
AnnaBridge 171:3a7713b1edbc 4852 * | | |0 = BM_ALERT pin not supported.
AnnaBridge 171:3a7713b1edbc 4853 * | | |1 = BM_ALERT pin supported.
AnnaBridge 171:3a7713b1edbc 4854 * |[5] |SCTLOSTS |Suspend/Control Data Output Status
AnnaBridge 171:3a7713b1edbc 4855 * | | |0 = The output of SUSCON pin is low.
AnnaBridge 171:3a7713b1edbc 4856 * | | |1 = The output of SUSCON pin is high.
AnnaBridge 171:3a7713b1edbc 4857 * |[6] |SCTLOEN |Suspend Or Control Pin Output Enable Bit
AnnaBridge 171:3a7713b1edbc 4858 * | | |0 = The SUSCON pin in input.
AnnaBridge 171:3a7713b1edbc 4859 * | | |1 = The output enable is active on the SUSCON pin.
AnnaBridge 171:3a7713b1edbc 4860 * |[7] |BUSEN |BUS Enable Bit
AnnaBridge 171:3a7713b1edbc 4861 * | | |0 = The system management function is Disabled.
AnnaBridge 171:3a7713b1edbc 4862 * | | |1 = The system management function is Enable.
AnnaBridge 171:3a7713b1edbc 4863 * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
AnnaBridge 171:3a7713b1edbc 4864 * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
AnnaBridge 171:3a7713b1edbc 4865 * | | |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
AnnaBridge 171:3a7713b1edbc 4866 * | | |0 = No PEC transfer.
AnnaBridge 171:3a7713b1edbc 4867 * | | |1 = PEC transmission/reception is requested.
AnnaBridge 171:3a7713b1edbc 4868 * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
AnnaBridge 171:3a7713b1edbc 4869 * |[9] |TIDLE |Timer Check In Idle State
AnnaBridge 171:3a7713b1edbc 4870 * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
AnnaBridge 171:3a7713b1edbc 4871 * | | |This bit is used to define which condition is enabled.
AnnaBridge 171:3a7713b1edbc 4872 * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
AnnaBridge 171:3a7713b1edbc 4873 * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
AnnaBridge 171:3a7713b1edbc 4874 * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
AnnaBridge 171:3a7713b1edbc 4875 * |[10] |PECCLR |PEC Clear At Repeat Start
AnnaBridge 171:3a7713b1edbc 4876 * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
AnnaBridge 171:3a7713b1edbc 4877 * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
AnnaBridge 171:3a7713b1edbc 4878 * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
AnnaBridge 171:3a7713b1edbc 4879 * | | |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
AnnaBridge 171:3a7713b1edbc 4880 * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
AnnaBridge 171:3a7713b1edbc 4881 * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
AnnaBridge 171:3a7713b1edbc 4882 * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
AnnaBridge 171:3a7713b1edbc 4883 * @var I2C_T::BUSTCTL
AnnaBridge 171:3a7713b1edbc 4884 * Offset: 0x48 I2C Bus Management Timer Control Register
AnnaBridge 171:3a7713b1edbc 4885 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4886 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4887 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4888 * |[0] |BUSTOEN |Bus Time Out Enable Bit
AnnaBridge 171:3a7713b1edbc 4889 * | | |0 = Indicates the bus clock low time-out detection is Disabled.
AnnaBridge 171:3a7713b1edbc 4890 * | | |1 = Indicates the bus clock low time-out detection is Enabled
AnnaBridge 171:3a7713b1edbc 4891 * | | |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
AnnaBridge 171:3a7713b1edbc 4892 * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
AnnaBridge 171:3a7713b1edbc 4893 * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
AnnaBridge 171:3a7713b1edbc 4894 * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
AnnaBridge 171:3a7713b1edbc 4895 * | | |For Master, it calculates the period from START to ACK
AnnaBridge 171:3a7713b1edbc 4896 * | | |For Slave, it calculates the period from START to STOP
AnnaBridge 171:3a7713b1edbc 4897 * |[2] |BUSTOIEN |Time-Out Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 4898 * | | |BUSY =1.
AnnaBridge 171:3a7713b1edbc 4899 * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
AnnaBridge 171:3a7713b1edbc 4900 * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
AnnaBridge 171:3a7713b1edbc 4901 * | | |BUSY =0.
AnnaBridge 171:3a7713b1edbc 4902 * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
AnnaBridge 171:3a7713b1edbc 4903 * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
AnnaBridge 171:3a7713b1edbc 4904 * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 4905 * | | |0 = Indicates the time extended interrupt is Disabled.
AnnaBridge 171:3a7713b1edbc 4906 * | | |1 = Indicates the time extended interrupt is Enabled.
AnnaBridge 171:3a7713b1edbc 4907 * |[4] |TORSTEN |Time Out Reset Enable Bit
AnnaBridge 171:3a7713b1edbc 4908 * | | |0 = Indicates the I2C state machine reset is Disable.
AnnaBridge 171:3a7713b1edbc 4909 * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
AnnaBridge 171:3a7713b1edbc 4910 * |[5] |PECIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 4911 * | | |0 = Indicates the byte count done interrupt is Disabled.
AnnaBridge 171:3a7713b1edbc 4912 * | | |1 = Indicates the byte count done interrupt is Enabled.
AnnaBridge 171:3a7713b1edbc 4913 * | | |Note: This bit is used in PECEN =1.
AnnaBridge 171:3a7713b1edbc 4914 * @var I2C_T::BUSSTS
AnnaBridge 171:3a7713b1edbc 4915 * Offset: 0x4C I2C Bus Management Status Register
AnnaBridge 171:3a7713b1edbc 4916 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4917 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4918 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4919 * |[0] |BUSY |Bus Busy
AnnaBridge 171:3a7713b1edbc 4920 * | | |Indicates that a communication is in progress on the bus.
AnnaBridge 171:3a7713b1edbc 4921 * | | |It is set by hardware when a START condition is detected.
AnnaBridge 171:3a7713b1edbc 4922 * | | |It is cleared by hardware when a STOP condition is detected.
AnnaBridge 171:3a7713b1edbc 4923 * | | |0 = The bus is IDLE (both SCLK and SDA High).
AnnaBridge 171:3a7713b1edbc 4924 * | | |1 = The bus is busy.
AnnaBridge 171:3a7713b1edbc 4925 * |[1] |BCDONE |Byte Count Transmission/Receive Done
AnnaBridge 171:3a7713b1edbc 4926 * | | |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
AnnaBridge 171:3a7713b1edbc 4927 * | | |1 = Indicates the transmission/ receive is finished when the PECEN is set.
AnnaBridge 171:3a7713b1edbc 4928 * | | |Note: Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4929 * |[2] |PECERR |PEC Error In Reception
AnnaBridge 171:3a7713b1edbc 4930 * | | |0 = Indicates the PEC value equal the received PEC data packet.
AnnaBridge 171:3a7713b1edbc 4931 * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
AnnaBridge 171:3a7713b1edbc 4932 * | | |Note: Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4933 * |[3] |ALERT |SMBus Alert Status
AnnaBridge 171:3a7713b1edbc 4934 * | | |Device Mode (BMHEN =0).
AnnaBridge 171:3a7713b1edbc 4935 * | | |0 = Indicates SMALERT pin state is low.
AnnaBridge 171:3a7713b1edbc 4936 * | | |1 = Indicates SMALERT pin state is high
AnnaBridge 171:3a7713b1edbc 4937 * | | |Host Mode (BMHEN =1).
AnnaBridge 171:3a7713b1edbc 4938 * | | |0 = No SMBALERT event.
AnnaBridge 171:3a7713b1edbc 4939 * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
AnnaBridge 171:3a7713b1edbc 4940 * | | |Note: 1.
AnnaBridge 171:3a7713b1edbc 4941 * | | |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
AnnaBridge 171:3a7713b1edbc 4942 * | | |2.
AnnaBridge 171:3a7713b1edbc 4943 * | | |Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4944 * |[4] |SCTLDIN |Bus Suspend Or Control Signal Input Status
AnnaBridge 171:3a7713b1edbc 4945 * | | |0 = The input status of SUSCON pin is 0.
AnnaBridge 171:3a7713b1edbc 4946 * | | |1 = The input status of SUSCON pin is 1.
AnnaBridge 171:3a7713b1edbc 4947 * |[5] |BUSTO |Bus Time-out Status
AnnaBridge 171:3a7713b1edbc 4948 * | | |0 = Indicates that there is no any time-out or external clock time-out.
AnnaBridge 171:3a7713b1edbc 4949 * | | |1 = Indicates that a time-out or external clock time-out occurred.
AnnaBridge 171:3a7713b1edbc 4950 * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
AnnaBridge 171:3a7713b1edbc 4951 * | | |Note: Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4952 * |[6] |CLKTO |Clock Low Cumulate Time-out Status
AnnaBridge 171:3a7713b1edbc 4953 * | | |0 = Indicates that the cumulative clock low is no any time-out.
AnnaBridge 171:3a7713b1edbc 4954 * | | |1 = Indicates that the cumulative clock low time-out occurred.
AnnaBridge 171:3a7713b1edbc 4955 * | | |Note: Software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 4956 * @var I2C_T::PKTSIZE
AnnaBridge 171:3a7713b1edbc 4957 * Offset: 0x50 I2C Packet Error Checking Byte Number Register
AnnaBridge 171:3a7713b1edbc 4958 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4959 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4960 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4961 * |[7:0] |PLDSIZE |Transfer Byte Number
AnnaBridge 171:3a7713b1edbc 4962 * | | |The transmission or receive byte number in one transaction when the PECEN is set.
AnnaBridge 171:3a7713b1edbc 4963 * | | |The maximum transaction or receive byte is 255 Bytes.
AnnaBridge 171:3a7713b1edbc 4964 * @var I2C_T::PKTCRC
AnnaBridge 171:3a7713b1edbc 4965 * Offset: 0x54 I2C Packet Error Checking Byte Value Register
AnnaBridge 171:3a7713b1edbc 4966 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4967 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4968 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4969 * |[7:0] |PECCRC |Packet Error Checking Byte Value
AnnaBridge 171:3a7713b1edbc 4970 * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
AnnaBridge 171:3a7713b1edbc 4971 * | | |I t is read only.
AnnaBridge 171:3a7713b1edbc 4972 * @var I2C_T::BUSTOUT
AnnaBridge 171:3a7713b1edbc 4973 * Offset: 0x58 I2C Bus Management Timer Register
AnnaBridge 171:3a7713b1edbc 4974 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4975 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4976 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4977 * |[7:0] |BUSTO |Bus Management Time-out Value
AnnaBridge 171:3a7713b1edbc 4978 * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
AnnaBridge 171:3a7713b1edbc 4979 * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
AnnaBridge 171:3a7713b1edbc 4980 * @var I2C_T::CLKTOUT
AnnaBridge 171:3a7713b1edbc 4981 * Offset: 0x5C I2C Bus Management Clock Low Timer Register
AnnaBridge 171:3a7713b1edbc 4982 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4983 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 4984 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 4985 * |[7:0] |CLKTO |Bus Clock Low Timer
AnnaBridge 171:3a7713b1edbc 4986 * | | |The field is used to configure the cumulative clock extension time-out.
AnnaBridge 171:3a7713b1edbc 4987 * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
AnnaBridge 171:3a7713b1edbc 4988 */
AnnaBridge 171:3a7713b1edbc 4989
AnnaBridge 171:3a7713b1edbc 4990 __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
AnnaBridge 171:3a7713b1edbc 4991 __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
AnnaBridge 171:3a7713b1edbc 4992 __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
AnnaBridge 171:3a7713b1edbc 4993 __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
AnnaBridge 171:3a7713b1edbc 4994 __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
AnnaBridge 171:3a7713b1edbc 4995 __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
AnnaBridge 171:3a7713b1edbc 4996 __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
AnnaBridge 171:3a7713b1edbc 4997 __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
AnnaBridge 171:3a7713b1edbc 4998 __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
AnnaBridge 171:3a7713b1edbc 4999 __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
AnnaBridge 171:3a7713b1edbc 5000 __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
AnnaBridge 171:3a7713b1edbc 5001 __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
AnnaBridge 171:3a7713b1edbc 5002 __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
AnnaBridge 171:3a7713b1edbc 5003 __I uint32_t RESERVE0[2];
AnnaBridge 171:3a7713b1edbc 5004 __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
AnnaBridge 171:3a7713b1edbc 5005 __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
AnnaBridge 171:3a7713b1edbc 5006 __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
AnnaBridge 171:3a7713b1edbc 5007 __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
AnnaBridge 171:3a7713b1edbc 5008 __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
AnnaBridge 171:3a7713b1edbc 5009 __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
AnnaBridge 171:3a7713b1edbc 5010 __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
AnnaBridge 171:3a7713b1edbc 5011 __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
AnnaBridge 171:3a7713b1edbc 5012 __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
AnnaBridge 171:3a7713b1edbc 5013
AnnaBridge 171:3a7713b1edbc 5014 } I2C_T;
AnnaBridge 171:3a7713b1edbc 5015
AnnaBridge 171:3a7713b1edbc 5016
AnnaBridge 171:3a7713b1edbc 5017
AnnaBridge 171:3a7713b1edbc 5018 /**
AnnaBridge 171:3a7713b1edbc 5019 @addtogroup I2C_CONST I2C Bit Field Definition
AnnaBridge 171:3a7713b1edbc 5020 Constant Definitions for I2C Controller
AnnaBridge 171:3a7713b1edbc 5021 @{ */
AnnaBridge 171:3a7713b1edbc 5022
AnnaBridge 171:3a7713b1edbc 5023 #define I2C_CTL_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
AnnaBridge 171:3a7713b1edbc 5024 #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C_T::CTL: AA Mask */
AnnaBridge 171:3a7713b1edbc 5025
AnnaBridge 171:3a7713b1edbc 5026 #define I2C_CTL_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
AnnaBridge 171:3a7713b1edbc 5027 #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C_T::CTL: SI Mask */
AnnaBridge 171:3a7713b1edbc 5028
AnnaBridge 171:3a7713b1edbc 5029 #define I2C_CTL_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
AnnaBridge 171:3a7713b1edbc 5030 #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C_T::CTL: STO Mask */
AnnaBridge 171:3a7713b1edbc 5031
AnnaBridge 171:3a7713b1edbc 5032 #define I2C_CTL_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
AnnaBridge 171:3a7713b1edbc 5033 #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C_T::CTL: STA Mask */
AnnaBridge 171:3a7713b1edbc 5034
AnnaBridge 171:3a7713b1edbc 5035 #define I2C_CTL_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
AnnaBridge 171:3a7713b1edbc 5036 #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
AnnaBridge 171:3a7713b1edbc 5037
AnnaBridge 171:3a7713b1edbc 5038 #define I2C_CTL_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
AnnaBridge 171:3a7713b1edbc 5039 #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 5040
AnnaBridge 171:3a7713b1edbc 5041 #define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
AnnaBridge 171:3a7713b1edbc 5042 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
AnnaBridge 171:3a7713b1edbc 5043
AnnaBridge 171:3a7713b1edbc 5044 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
AnnaBridge 171:3a7713b1edbc 5045 #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 5046
AnnaBridge 171:3a7713b1edbc 5047 #define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
AnnaBridge 171:3a7713b1edbc 5048 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
AnnaBridge 171:3a7713b1edbc 5049
AnnaBridge 171:3a7713b1edbc 5050 #define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
AnnaBridge 171:3a7713b1edbc 5051 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
AnnaBridge 171:3a7713b1edbc 5052
AnnaBridge 171:3a7713b1edbc 5053 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
AnnaBridge 171:3a7713b1edbc 5054 #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
AnnaBridge 171:3a7713b1edbc 5055
AnnaBridge 171:3a7713b1edbc 5056 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
AnnaBridge 171:3a7713b1edbc 5057 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
AnnaBridge 171:3a7713b1edbc 5058
AnnaBridge 171:3a7713b1edbc 5059 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
AnnaBridge 171:3a7713b1edbc 5060 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
AnnaBridge 171:3a7713b1edbc 5061
AnnaBridge 171:3a7713b1edbc 5062 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
AnnaBridge 171:3a7713b1edbc 5063 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
AnnaBridge 171:3a7713b1edbc 5064
AnnaBridge 171:3a7713b1edbc 5065 #define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
AnnaBridge 171:3a7713b1edbc 5066 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
AnnaBridge 171:3a7713b1edbc 5067
AnnaBridge 171:3a7713b1edbc 5068 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
AnnaBridge 171:3a7713b1edbc 5069 #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 5070
AnnaBridge 171:3a7713b1edbc 5071 #define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
AnnaBridge 171:3a7713b1edbc 5072 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
AnnaBridge 171:3a7713b1edbc 5073
AnnaBridge 171:3a7713b1edbc 5074 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
AnnaBridge 171:3a7713b1edbc 5075 #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 5076
AnnaBridge 171:3a7713b1edbc 5077 #define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
AnnaBridge 171:3a7713b1edbc 5078 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
AnnaBridge 171:3a7713b1edbc 5079
AnnaBridge 171:3a7713b1edbc 5080 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
AnnaBridge 171:3a7713b1edbc 5081 #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 5082
AnnaBridge 171:3a7713b1edbc 5083 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
AnnaBridge 171:3a7713b1edbc 5084 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
AnnaBridge 171:3a7713b1edbc 5085
AnnaBridge 171:3a7713b1edbc 5086 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
AnnaBridge 171:3a7713b1edbc 5087 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
AnnaBridge 171:3a7713b1edbc 5088
AnnaBridge 171:3a7713b1edbc 5089 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
AnnaBridge 171:3a7713b1edbc 5090 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
AnnaBridge 171:3a7713b1edbc 5091
AnnaBridge 171:3a7713b1edbc 5092 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
AnnaBridge 171:3a7713b1edbc 5093 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
AnnaBridge 171:3a7713b1edbc 5094
AnnaBridge 171:3a7713b1edbc 5095 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
AnnaBridge 171:3a7713b1edbc 5096 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 5097
AnnaBridge 171:3a7713b1edbc 5098 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
AnnaBridge 171:3a7713b1edbc 5099 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
AnnaBridge 171:3a7713b1edbc 5100
AnnaBridge 171:3a7713b1edbc 5101 #define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
AnnaBridge 171:3a7713b1edbc 5102 #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
AnnaBridge 171:3a7713b1edbc 5103
AnnaBridge 171:3a7713b1edbc 5104 #define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
AnnaBridge 171:3a7713b1edbc 5105 #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
AnnaBridge 171:3a7713b1edbc 5106
AnnaBridge 171:3a7713b1edbc 5107 #define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
AnnaBridge 171:3a7713b1edbc 5108 #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
AnnaBridge 171:3a7713b1edbc 5109
AnnaBridge 171:3a7713b1edbc 5110 #define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
AnnaBridge 171:3a7713b1edbc 5111 #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
AnnaBridge 171:3a7713b1edbc 5112
AnnaBridge 171:3a7713b1edbc 5113 #define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
AnnaBridge 171:3a7713b1edbc 5114 #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
AnnaBridge 171:3a7713b1edbc 5115
AnnaBridge 171:3a7713b1edbc 5116 #define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
AnnaBridge 171:3a7713b1edbc 5117 #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
AnnaBridge 171:3a7713b1edbc 5118
AnnaBridge 171:3a7713b1edbc 5119 #define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
AnnaBridge 171:3a7713b1edbc 5120 #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
AnnaBridge 171:3a7713b1edbc 5121
AnnaBridge 171:3a7713b1edbc 5122 #define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
AnnaBridge 171:3a7713b1edbc 5123 #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
AnnaBridge 171:3a7713b1edbc 5124
AnnaBridge 171:3a7713b1edbc 5125 #define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
AnnaBridge 171:3a7713b1edbc 5126 #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
AnnaBridge 171:3a7713b1edbc 5127
AnnaBridge 171:3a7713b1edbc 5128 #define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
AnnaBridge 171:3a7713b1edbc 5129 #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
AnnaBridge 171:3a7713b1edbc 5130
AnnaBridge 171:3a7713b1edbc 5131 #define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
AnnaBridge 171:3a7713b1edbc 5132 #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
AnnaBridge 171:3a7713b1edbc 5133
AnnaBridge 171:3a7713b1edbc 5134 #define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
AnnaBridge 171:3a7713b1edbc 5135 #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
AnnaBridge 171:3a7713b1edbc 5136
AnnaBridge 171:3a7713b1edbc 5137 #define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
AnnaBridge 171:3a7713b1edbc 5138 #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
AnnaBridge 171:3a7713b1edbc 5139
AnnaBridge 171:3a7713b1edbc 5140 #define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
AnnaBridge 171:3a7713b1edbc 5141 #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
AnnaBridge 171:3a7713b1edbc 5142
AnnaBridge 171:3a7713b1edbc 5143 #define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
AnnaBridge 171:3a7713b1edbc 5144 #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
AnnaBridge 171:3a7713b1edbc 5145
AnnaBridge 171:3a7713b1edbc 5146 #define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
AnnaBridge 171:3a7713b1edbc 5147 #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
AnnaBridge 171:3a7713b1edbc 5148
AnnaBridge 171:3a7713b1edbc 5149 #define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
AnnaBridge 171:3a7713b1edbc 5150 #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
AnnaBridge 171:3a7713b1edbc 5151
AnnaBridge 171:3a7713b1edbc 5152 #define I2C_BUSTCTL_PECIEN_Pos (5) /*!< I2C_T::BUSTCTL: PECIEN Position */
AnnaBridge 171:3a7713b1edbc 5153 #define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) /*!< I2C_T::BUSTCTL: PECIEN Mask */
AnnaBridge 171:3a7713b1edbc 5154
AnnaBridge 171:3a7713b1edbc 5155 #define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
AnnaBridge 171:3a7713b1edbc 5156 #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 5157
AnnaBridge 171:3a7713b1edbc 5158 #define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
AnnaBridge 171:3a7713b1edbc 5159 #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
AnnaBridge 171:3a7713b1edbc 5160
AnnaBridge 171:3a7713b1edbc 5161 #define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
AnnaBridge 171:3a7713b1edbc 5162 #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
AnnaBridge 171:3a7713b1edbc 5163
AnnaBridge 171:3a7713b1edbc 5164 #define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
AnnaBridge 171:3a7713b1edbc 5165 #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
AnnaBridge 171:3a7713b1edbc 5166
AnnaBridge 171:3a7713b1edbc 5167 #define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
AnnaBridge 171:3a7713b1edbc 5168 #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
AnnaBridge 171:3a7713b1edbc 5169
AnnaBridge 171:3a7713b1edbc 5170 #define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
AnnaBridge 171:3a7713b1edbc 5171 #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
AnnaBridge 171:3a7713b1edbc 5172
AnnaBridge 171:3a7713b1edbc 5173 #define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
AnnaBridge 171:3a7713b1edbc 5174 #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
AnnaBridge 171:3a7713b1edbc 5175
AnnaBridge 171:3a7713b1edbc 5176 #define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
AnnaBridge 171:3a7713b1edbc 5177 #define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
AnnaBridge 171:3a7713b1edbc 5178
AnnaBridge 171:3a7713b1edbc 5179 #define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
AnnaBridge 171:3a7713b1edbc 5180 #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
AnnaBridge 171:3a7713b1edbc 5181
AnnaBridge 171:3a7713b1edbc 5182 #define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
AnnaBridge 171:3a7713b1edbc 5183 #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
AnnaBridge 171:3a7713b1edbc 5184
AnnaBridge 171:3a7713b1edbc 5185 #define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
AnnaBridge 171:3a7713b1edbc 5186 #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
AnnaBridge 171:3a7713b1edbc 5187
AnnaBridge 171:3a7713b1edbc 5188
AnnaBridge 171:3a7713b1edbc 5189 /**@}*/ /* I2C_CONST */
AnnaBridge 171:3a7713b1edbc 5190 /**@}*/ /* end of I2C register group */
AnnaBridge 171:3a7713b1edbc 5191
AnnaBridge 171:3a7713b1edbc 5192 /*---------------------- USB On-The-Go Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 5193 /**
AnnaBridge 171:3a7713b1edbc 5194 @addtogroup OTG USB On-The-Go Controller(OTG)
AnnaBridge 171:3a7713b1edbc 5195 Memory Mapped Structure for OTG Controller
AnnaBridge 171:3a7713b1edbc 5196 @{ */
AnnaBridge 171:3a7713b1edbc 5197
AnnaBridge 171:3a7713b1edbc 5198
AnnaBridge 171:3a7713b1edbc 5199 typedef struct
AnnaBridge 171:3a7713b1edbc 5200 {
AnnaBridge 171:3a7713b1edbc 5201
AnnaBridge 171:3a7713b1edbc 5202
AnnaBridge 171:3a7713b1edbc 5203 /**
AnnaBridge 171:3a7713b1edbc 5204 * @var OTG_T::CTL
AnnaBridge 171:3a7713b1edbc 5205 * Offset: 0x00 OTG Control Register
AnnaBridge 171:3a7713b1edbc 5206 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5207 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5208 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5209 * |[0] |VBUSDROP |Drop VBUS Control
AnnaBridge 171:3a7713b1edbc 5210 * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
AnnaBridge 171:3a7713b1edbc 5211 * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
AnnaBridge 171:3a7713b1edbc 5212 * | | |0 = Not drop the VBUS.
AnnaBridge 171:3a7713b1edbc 5213 * | | |1 = Drop the VBUS.
AnnaBridge 171:3a7713b1edbc 5214 * |[1] |BUSREQ |OTG Bus Request
AnnaBridge 171:3a7713b1edbc 5215 * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
AnnaBridge 171:3a7713b1edbc 5216 * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
AnnaBridge 171:3a7713b1edbc 5217 * | | |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
AnnaBridge 171:3a7713b1edbc 5218 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
AnnaBridge 171:3a7713b1edbc 5219 * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
AnnaBridge 171:3a7713b1edbc 5220 * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
AnnaBridge 171:3a7713b1edbc 5221 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
AnnaBridge 171:3a7713b1edbc 5222 * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
AnnaBridge 171:3a7713b1edbc 5223 * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
AnnaBridge 171:3a7713b1edbc 5224 * |[2] |HNPREQEN |OTG HNP Request Enable Bit
AnnaBridge 171:3a7713b1edbc 5225 * | | |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
AnnaBridge 171:3a7713b1edbc 5226 * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
AnnaBridge 171:3a7713b1edbc 5227 * | | |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
AnnaBridge 171:3a7713b1edbc 5228 * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
AnnaBridge 171:3a7713b1edbc 5229 * | | |0 = HNP request Disabled.
AnnaBridge 171:3a7713b1edbc 5230 * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
AnnaBridge 171:3a7713b1edbc 5231 * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
AnnaBridge 171:3a7713b1edbc 5232 * |[4] |OTGEN |OTG Function Enable Bit
AnnaBridge 171:3a7713b1edbc 5233 * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
AnnaBridge 171:3a7713b1edbc 5234 * | | |When USB frame not configured as OTG device, this bit is must be low.
AnnaBridge 171:3a7713b1edbc 5235 * | | |0 = OTG function Disabled.
AnnaBridge 171:3a7713b1edbc 5236 * | | |1 = OTG function Enabled.
AnnaBridge 171:3a7713b1edbc 5237 * |[5] |WKEN |OTG ID Pin Wake-Up Enable Bit
AnnaBridge 171:3a7713b1edbc 5238 * | | |0 = OTG ID pin status change wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 5239 * | | |1 = OTG ID pin status change wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 5240 * @var OTG_T::PHYCTL
AnnaBridge 171:3a7713b1edbc 5241 * Offset: 0x04 OTG PHY Control Register
AnnaBridge 171:3a7713b1edbc 5242 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5243 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5244 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5245 * |[0] |OTGPHYEN |OTG PHY Enable
AnnaBridge 171:3a7713b1edbc 5246 * | | |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
AnnaBridge 171:3a7713b1edbc 5247 * | | |If device is not configured as OTG-device, this bit is "don't care".
AnnaBridge 171:3a7713b1edbc 5248 * | | |0 = OTG PHY Disabled.
AnnaBridge 171:3a7713b1edbc 5249 * | | |1 = OTG PHY Enabled.
AnnaBridge 171:3a7713b1edbc 5250 * |[1] |IDDETEN |ID Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 5251 * | | |0 = Detect ID pin status Disabled.
AnnaBridge 171:3a7713b1edbc 5252 * | | |1 = Detect ID pin status Enabled.
AnnaBridge 171:3a7713b1edbc 5253 * |[4] |VBENPOL |Off-Chip USB VBUS Power Switch Enable Polarity
AnnaBridge 171:3a7713b1edbc 5254 * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
AnnaBridge 171:3a7713b1edbc 5255 * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
AnnaBridge 171:3a7713b1edbc 5256 * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
AnnaBridge 171:3a7713b1edbc 5257 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
AnnaBridge 171:3a7713b1edbc 5258 * | | |0 = The off-chip USB VBUS power switch enable is active high.
AnnaBridge 171:3a7713b1edbc 5259 * | | |1 = The off-chip USB VBUS power switch enable is active low.
AnnaBridge 171:3a7713b1edbc 5260 * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Switch Status Polarity
AnnaBridge 171:3a7713b1edbc 5261 * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
AnnaBridge 171:3a7713b1edbc 5262 * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
AnnaBridge 171:3a7713b1edbc 5263 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
AnnaBridge 171:3a7713b1edbc 5264 * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
AnnaBridge 171:3a7713b1edbc 5265 * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
AnnaBridge 171:3a7713b1edbc 5266 * @var OTG_T::INTEN
AnnaBridge 171:3a7713b1edbc 5267 * Offset: 0x08 OTG Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 5268 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5269 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5270 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5271 * |[0] |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5272 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5273 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5274 * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5275 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5276 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5277 * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
AnnaBridge 171:3a7713b1edbc 5278 * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5279 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5280 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5281 * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5282 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5283 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5284 * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5285 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5286 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5287 * | | |Note: Going to idle state means going to a_idle or b_idle state.
AnnaBridge 171:3a7713b1edbc 5288 * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
AnnaBridge 171:3a7713b1edbc 5289 * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5290 * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5291 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5292 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5293 * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5294 * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5295 * | | |0 = This device as a peripheral interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5296 * | | |1 = This device as a peripheral interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5297 * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5298 * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5299 * | | |0 = This device as a host interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5300 * | | |1 = This device as a host interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5301 * |[8] |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5302 * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5303 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5304 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5305 * |[9] |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5306 * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5307 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5308 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5309 * |[10] |VBCHGIEN |VBUSVLD Status Changed
AnnaBridge 171:3a7713b1edbc 5310 * | | |Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5311 * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5312 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5313 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5314 * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5315 * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
AnnaBridge 171:3a7713b1edbc 5316 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5317 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5318 * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 5319 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5320 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5321 * @var OTG_T::INTSTS
AnnaBridge 171:3a7713b1edbc 5322 * Offset: 0x0C OTG Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 5323 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5324 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5325 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5326 * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5327 * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
AnnaBridge 171:3a7713b1edbc 5328 * | | |0 = OTG device role not changed.
AnnaBridge 171:3a7713b1edbc 5329 * | | |1 = OTG device role changed.
AnnaBridge 171:3a7713b1edbc 5330 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5331 * |[1] |VBEIF |VBUS Error Interrupt Status
AnnaBridge 171:3a7713b1edbc 5332 * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
AnnaBridge 171:3a7713b1edbc 5333 * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
AnnaBridge 171:3a7713b1edbc 5334 * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
AnnaBridge 171:3a7713b1edbc 5335 * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
AnnaBridge 171:3a7713b1edbc 5336 * |[2] |SRPFIF |SRP Fail Interrupt Status
AnnaBridge 171:3a7713b1edbc 5337 * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
AnnaBridge 171:3a7713b1edbc 5338 * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
AnnaBridge 171:3a7713b1edbc 5339 * | | |0 = OTG B-device gets VBUS high before this interval.
AnnaBridge 171:3a7713b1edbc 5340 * | | |1 = OTG B-device does not get VBUS high before this interval.
AnnaBridge 171:3a7713b1edbc 5341 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5342 * |[3] |HNPFIF |HNP Fail Interrupt Status
AnnaBridge 171:3a7713b1edbc 5343 * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
AnnaBridge 171:3a7713b1edbc 5344 * | | |0 = A-device connects to B-device before specified interval expires.
AnnaBridge 171:3a7713b1edbc 5345 * | | |1 = A-device does not connect to B-device before specified interval expires.
AnnaBridge 171:3a7713b1edbc 5346 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5347 * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
AnnaBridge 171:3a7713b1edbc 5348 * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
AnnaBridge 171:3a7713b1edbc 5349 * | | |The OTG device will be neither a host nor a peripheral.
AnnaBridge 171:3a7713b1edbc 5350 * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
AnnaBridge 171:3a7713b1edbc 5351 * | | |1 = OTG device goes back to idle state (a_idle or b_idle).
AnnaBridge 171:3a7713b1edbc 5352 * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
AnnaBridge 171:3a7713b1edbc 5353 * | | |Note 2: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5354 * |[5] |IDCHGIF |ID State Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5355 * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
AnnaBridge 171:3a7713b1edbc 5356 * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
AnnaBridge 171:3a7713b1edbc 5357 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5358 * |[6] |PDEVIF |Act As Peripheral Interrupt Status
AnnaBridge 171:3a7713b1edbc 5359 * | | |0 = This device does not act as a peripheral.
AnnaBridge 171:3a7713b1edbc 5360 * | | |1 = This device acts as a peripheral.
AnnaBridge 171:3a7713b1edbc 5361 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5362 * |[7] |HOSTIF |Act As Host Interrupt Status
AnnaBridge 171:3a7713b1edbc 5363 * | | |0 = This device does not act as a host.
AnnaBridge 171:3a7713b1edbc 5364 * | | |1 = This device acts as a host.
AnnaBridge 171:3a7713b1edbc 5365 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5366 * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5367 * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
AnnaBridge 171:3a7713b1edbc 5368 * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
AnnaBridge 171:3a7713b1edbc 5369 * | | |Note: Write 1 to clear this status.
AnnaBridge 171:3a7713b1edbc 5370 * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5371 * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
AnnaBridge 171:3a7713b1edbc 5372 * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
AnnaBridge 171:3a7713b1edbc 5373 * | | |Note: Write 1 to clear this status.
AnnaBridge 171:3a7713b1edbc 5374 * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5375 * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
AnnaBridge 171:3a7713b1edbc 5376 * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
AnnaBridge 171:3a7713b1edbc 5377 * | | |Note: Write 1 to clear this status.
AnnaBridge 171:3a7713b1edbc 5378 * |[11] |SECHGIF |SESSEND State Change Interrupt Status
AnnaBridge 171:3a7713b1edbc 5379 * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
AnnaBridge 171:3a7713b1edbc 5380 * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
AnnaBridge 171:3a7713b1edbc 5381 * | | |Note: Write 1 to clear this flag.
AnnaBridge 171:3a7713b1edbc 5382 * |[13] |SRPDETIF |SRP Detected Interrupt Status
AnnaBridge 171:3a7713b1edbc 5383 * | | |0 = SRP not detected.
AnnaBridge 171:3a7713b1edbc 5384 * | | |1 = SRP detected.
AnnaBridge 171:3a7713b1edbc 5385 * | | |Note: Write 1 to clear this status.
AnnaBridge 171:3a7713b1edbc 5386 * @var OTG_T::STATUS
AnnaBridge 171:3a7713b1edbc 5387 * Offset: 0x10 OTG Status Register
AnnaBridge 171:3a7713b1edbc 5388 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5389 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5390 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5391 * |[0] |OVERCUR |Over Current Condition
AnnaBridge 171:3a7713b1edbc 5392 * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
AnnaBridge 171:3a7713b1edbc 5393 * | | |0 = OTG A-device drives VBUS successfully.
AnnaBridge 171:3a7713b1edbc 5394 * | | |1 = OTG A-device cannot drives VBUS high in this interval.
AnnaBridge 171:3a7713b1edbc 5395 * |[1] |IDSTS |USB_ID Pin State Of Mini-B/Micro-Plug
AnnaBridge 171:3a7713b1edbc 5396 * | | |0 = Mini-A/Micro-A plug is attached.
AnnaBridge 171:3a7713b1edbc 5397 * | | |1 = Mini-B/Micro-B plug is attached.
AnnaBridge 171:3a7713b1edbc 5398 * |[2] |SESSEND |Session End Status
AnnaBridge 171:3a7713b1edbc 5399 * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 5400 * | | |Session end means no meaningful power on VBUS.
AnnaBridge 171:3a7713b1edbc 5401 * | | |0 = Session is not end.
AnnaBridge 171:3a7713b1edbc 5402 * | | |1 = Session is end.
AnnaBridge 171:3a7713b1edbc 5403 * |[3] |BVLD |B-Device Session Valid Status
AnnaBridge 171:3a7713b1edbc 5404 * | | |0 = B-device session is not valid.
AnnaBridge 171:3a7713b1edbc 5405 * | | |1 = B-device session is valid.
AnnaBridge 171:3a7713b1edbc 5406 * |[4] |AVLD |A-Device Session Valid Status
AnnaBridge 171:3a7713b1edbc 5407 * | | |0 = A-device session is not valid.
AnnaBridge 171:3a7713b1edbc 5408 * | | |1 = A-device session is valid.
AnnaBridge 171:3a7713b1edbc 5409 * |[5] |VBUSVLD |VBUS Valid Status
AnnaBridge 171:3a7713b1edbc 5410 * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 5411 * | | |0 = VBUS is not valid.
AnnaBridge 171:3a7713b1edbc 5412 * | | |1 = VBUS is valid.
AnnaBridge 171:3a7713b1edbc 5413 */
AnnaBridge 171:3a7713b1edbc 5414
AnnaBridge 171:3a7713b1edbc 5415 __IO uint32_t CTL; /* Offset: 0x00 OTG Control Register */
AnnaBridge 171:3a7713b1edbc 5416 __IO uint32_t PHYCTL; /* Offset: 0x04 OTG PHY Control Register */
AnnaBridge 171:3a7713b1edbc 5417 __IO uint32_t INTEN; /* Offset: 0x08 OTG Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 5418 __IO uint32_t INTSTS; /* Offset: 0x0C OTG Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 5419 __I uint32_t STATUS; /* Offset: 0x10 OTG Status Register */
AnnaBridge 171:3a7713b1edbc 5420
AnnaBridge 171:3a7713b1edbc 5421 } OTG_T;
AnnaBridge 171:3a7713b1edbc 5422
AnnaBridge 171:3a7713b1edbc 5423
AnnaBridge 171:3a7713b1edbc 5424
AnnaBridge 171:3a7713b1edbc 5425 /**
AnnaBridge 171:3a7713b1edbc 5426 @addtogroup OTG_CONST OTG Bit Field Definition
AnnaBridge 171:3a7713b1edbc 5427 Constant Definitions for OTG Controller
AnnaBridge 171:3a7713b1edbc 5428 @{ */
AnnaBridge 171:3a7713b1edbc 5429
AnnaBridge 171:3a7713b1edbc 5430 #define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
AnnaBridge 171:3a7713b1edbc 5431 #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
AnnaBridge 171:3a7713b1edbc 5432
AnnaBridge 171:3a7713b1edbc 5433 #define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
AnnaBridge 171:3a7713b1edbc 5434 #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
AnnaBridge 171:3a7713b1edbc 5435
AnnaBridge 171:3a7713b1edbc 5436 #define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
AnnaBridge 171:3a7713b1edbc 5437 #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
AnnaBridge 171:3a7713b1edbc 5438
AnnaBridge 171:3a7713b1edbc 5439 #define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
AnnaBridge 171:3a7713b1edbc 5440 #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
AnnaBridge 171:3a7713b1edbc 5441
AnnaBridge 171:3a7713b1edbc 5442 #define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
AnnaBridge 171:3a7713b1edbc 5443 #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 5444
AnnaBridge 171:3a7713b1edbc 5445 #define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
AnnaBridge 171:3a7713b1edbc 5446 #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
AnnaBridge 171:3a7713b1edbc 5447
AnnaBridge 171:3a7713b1edbc 5448 #define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
AnnaBridge 171:3a7713b1edbc 5449 #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
AnnaBridge 171:3a7713b1edbc 5450
AnnaBridge 171:3a7713b1edbc 5451 #define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
AnnaBridge 171:3a7713b1edbc 5452 #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
AnnaBridge 171:3a7713b1edbc 5453
AnnaBridge 171:3a7713b1edbc 5454 #define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
AnnaBridge 171:3a7713b1edbc 5455 #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
AnnaBridge 171:3a7713b1edbc 5456
AnnaBridge 171:3a7713b1edbc 5457 #define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5458 #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5459
AnnaBridge 171:3a7713b1edbc 5460 #define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
AnnaBridge 171:3a7713b1edbc 5461 #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
AnnaBridge 171:3a7713b1edbc 5462
AnnaBridge 171:3a7713b1edbc 5463 #define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
AnnaBridge 171:3a7713b1edbc 5464 #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
AnnaBridge 171:3a7713b1edbc 5465
AnnaBridge 171:3a7713b1edbc 5466 #define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
AnnaBridge 171:3a7713b1edbc 5467 #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
AnnaBridge 171:3a7713b1edbc 5468
AnnaBridge 171:3a7713b1edbc 5469 #define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
AnnaBridge 171:3a7713b1edbc 5470 #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
AnnaBridge 171:3a7713b1edbc 5471
AnnaBridge 171:3a7713b1edbc 5472 #define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5473 #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5474
AnnaBridge 171:3a7713b1edbc 5475 #define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
AnnaBridge 171:3a7713b1edbc 5476 #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
AnnaBridge 171:3a7713b1edbc 5477
AnnaBridge 171:3a7713b1edbc 5478 #define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
AnnaBridge 171:3a7713b1edbc 5479 #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
AnnaBridge 171:3a7713b1edbc 5480
AnnaBridge 171:3a7713b1edbc 5481 #define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5482 #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5483
AnnaBridge 171:3a7713b1edbc 5484 #define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5485 #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5486
AnnaBridge 171:3a7713b1edbc 5487 #define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5488 #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5489
AnnaBridge 171:3a7713b1edbc 5490 #define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
AnnaBridge 171:3a7713b1edbc 5491 #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
AnnaBridge 171:3a7713b1edbc 5492
AnnaBridge 171:3a7713b1edbc 5493 #define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
AnnaBridge 171:3a7713b1edbc 5494 #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
AnnaBridge 171:3a7713b1edbc 5495
AnnaBridge 171:3a7713b1edbc 5496 #define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
AnnaBridge 171:3a7713b1edbc 5497 #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5498
AnnaBridge 171:3a7713b1edbc 5499 #define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
AnnaBridge 171:3a7713b1edbc 5500 #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
AnnaBridge 171:3a7713b1edbc 5501
AnnaBridge 171:3a7713b1edbc 5502 #define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
AnnaBridge 171:3a7713b1edbc 5503 #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
AnnaBridge 171:3a7713b1edbc 5504
AnnaBridge 171:3a7713b1edbc 5505 #define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
AnnaBridge 171:3a7713b1edbc 5506 #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
AnnaBridge 171:3a7713b1edbc 5507
AnnaBridge 171:3a7713b1edbc 5508 #define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
AnnaBridge 171:3a7713b1edbc 5509 #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
AnnaBridge 171:3a7713b1edbc 5510
AnnaBridge 171:3a7713b1edbc 5511 #define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
AnnaBridge 171:3a7713b1edbc 5512 #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5513
AnnaBridge 171:3a7713b1edbc 5514 #define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
AnnaBridge 171:3a7713b1edbc 5515 #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
AnnaBridge 171:3a7713b1edbc 5516
AnnaBridge 171:3a7713b1edbc 5517 #define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
AnnaBridge 171:3a7713b1edbc 5518 #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
AnnaBridge 171:3a7713b1edbc 5519
AnnaBridge 171:3a7713b1edbc 5520 #define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
AnnaBridge 171:3a7713b1edbc 5521 #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5522
AnnaBridge 171:3a7713b1edbc 5523 #define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
AnnaBridge 171:3a7713b1edbc 5524 #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5525
AnnaBridge 171:3a7713b1edbc 5526 #define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
AnnaBridge 171:3a7713b1edbc 5527 #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5528
AnnaBridge 171:3a7713b1edbc 5529 #define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
AnnaBridge 171:3a7713b1edbc 5530 #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
AnnaBridge 171:3a7713b1edbc 5531
AnnaBridge 171:3a7713b1edbc 5532 #define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
AnnaBridge 171:3a7713b1edbc 5533 #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
AnnaBridge 171:3a7713b1edbc 5534
AnnaBridge 171:3a7713b1edbc 5535 #define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
AnnaBridge 171:3a7713b1edbc 5536 #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
AnnaBridge 171:3a7713b1edbc 5537
AnnaBridge 171:3a7713b1edbc 5538 #define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
AnnaBridge 171:3a7713b1edbc 5539 #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
AnnaBridge 171:3a7713b1edbc 5540
AnnaBridge 171:3a7713b1edbc 5541 #define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
AnnaBridge 171:3a7713b1edbc 5542 #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
AnnaBridge 171:3a7713b1edbc 5543
AnnaBridge 171:3a7713b1edbc 5544 #define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
AnnaBridge 171:3a7713b1edbc 5545 #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
AnnaBridge 171:3a7713b1edbc 5546
AnnaBridge 171:3a7713b1edbc 5547 #define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
AnnaBridge 171:3a7713b1edbc 5548 #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
AnnaBridge 171:3a7713b1edbc 5549
AnnaBridge 171:3a7713b1edbc 5550 #define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
AnnaBridge 171:3a7713b1edbc 5551 #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
AnnaBridge 171:3a7713b1edbc 5552
AnnaBridge 171:3a7713b1edbc 5553 /**@}*/ /* OTG_CONST */
AnnaBridge 171:3a7713b1edbc 5554 /**@}*/ /* end of OTG register group */
AnnaBridge 171:3a7713b1edbc 5555
AnnaBridge 171:3a7713b1edbc 5556
AnnaBridge 171:3a7713b1edbc 5557 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 5558 /**
AnnaBridge 171:3a7713b1edbc 5559 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
AnnaBridge 171:3a7713b1edbc 5560 Memory Mapped Structure for PDMA Controller
AnnaBridge 171:3a7713b1edbc 5561 @{ */
AnnaBridge 171:3a7713b1edbc 5562
AnnaBridge 171:3a7713b1edbc 5563
AnnaBridge 171:3a7713b1edbc 5564 typedef struct
AnnaBridge 171:3a7713b1edbc 5565 {
AnnaBridge 171:3a7713b1edbc 5566
AnnaBridge 171:3a7713b1edbc 5567
AnnaBridge 171:3a7713b1edbc 5568 /**
AnnaBridge 171:3a7713b1edbc 5569 * @var DSCT_T::CTL
AnnaBridge 171:3a7713b1edbc 5570 * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11
AnnaBridge 171:3a7713b1edbc 5571 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5572 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5573 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5574 * |[1:0] |OPMODE |PDMA Operation Mode Selection
AnnaBridge 171:3a7713b1edbc 5575 * | | |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
AnnaBridge 171:3a7713b1edbc 5576 * | | |1 = Basic mode: The descriptor table only has one task.
AnnaBridge 171:3a7713b1edbc 5577 * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
AnnaBridge 171:3a7713b1edbc 5578 * | | |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
AnnaBridge 171:3a7713b1edbc 5579 * | | |3 = Reserved.
AnnaBridge 171:3a7713b1edbc 5580 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
AnnaBridge 171:3a7713b1edbc 5581 * |[2] |TXTYPE |Transfer Type
AnnaBridge 171:3a7713b1edbc 5582 * | | |0 = Burst transfer type.
AnnaBridge 171:3a7713b1edbc 5583 * | | |1 = Single transfer type.
AnnaBridge 171:3a7713b1edbc 5584 * |[6:4] |BURSIZE |Burst Size
AnnaBridge 171:3a7713b1edbc 5585 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
AnnaBridge 171:3a7713b1edbc 5586 * | | |000 = 128 Transfers.
AnnaBridge 171:3a7713b1edbc 5587 * | | |001 = 64 Transfers.
AnnaBridge 171:3a7713b1edbc 5588 * | | |010 = 32 Transfers.
AnnaBridge 171:3a7713b1edbc 5589 * | | |011 = 16 Transfers.
AnnaBridge 171:3a7713b1edbc 5590 * | | |100 = 8 Transfers.
AnnaBridge 171:3a7713b1edbc 5591 * | | |101 = 4 Transfers.
AnnaBridge 171:3a7713b1edbc 5592 * | | |110 = 2 Transfers.
AnnaBridge 171:3a7713b1edbc 5593 * | | |111 = 1 Transfers.
AnnaBridge 171:3a7713b1edbc 5594 * | | |Note: This field is only useful in burst transfer type.
AnnaBridge 171:3a7713b1edbc 5595 * |[7] |TBINTDIS |Table Interrupt Disable
AnnaBridge 171:3a7713b1edbc 5596 * | | |This field can be used to decide whether to enable table interrupt or not.
AnnaBridge 171:3a7713b1edbc 5597 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
AnnaBridge 171:3a7713b1edbc 5598 * | | |0 = Table interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5599 * | | |1 = Table interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5600 * | | |Note: If this bit set to '1', the TEMPTYF will not be set.
AnnaBridge 171:3a7713b1edbc 5601 * |[9:8] |SAINC |Source Address Increment
AnnaBridge 171:3a7713b1edbc 5602 * | | |This field is used to set the source address increment size.
AnnaBridge 171:3a7713b1edbc 5603 * | | |11 = No increment (fixed address).
AnnaBridge 171:3a7713b1edbc 5604 * | | |Others = Increment and size is depended on TXWIDTH selection.
AnnaBridge 171:3a7713b1edbc 5605 * |[11:10] |DAINC |Destination Address Increment
AnnaBridge 171:3a7713b1edbc 5606 * | | |This field is used to set the destination address increment size.
AnnaBridge 171:3a7713b1edbc 5607 * | | |11 = No increment (fixed address).
AnnaBridge 171:3a7713b1edbc 5608 * | | |Others = Increment and size is depended on TXWIDTH selection.
AnnaBridge 171:3a7713b1edbc 5609 * |[13:12] |TXWIDTH |Transfer Width Selection
AnnaBridge 171:3a7713b1edbc 5610 * | | |This field is used for transfer width.
AnnaBridge 171:3a7713b1edbc 5611 * | | |00 = One byte (8 bit) is transferred for every operation.
AnnaBridge 171:3a7713b1edbc 5612 * | | |01= One half-word (16 bit) is transferred for every operation.
AnnaBridge 171:3a7713b1edbc 5613 * | | |10 = One word (32-bit) is transferred for every operation.
AnnaBridge 171:3a7713b1edbc 5614 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 5615 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
AnnaBridge 171:3a7713b1edbc 5616 * |[29:16] |TXCNT |Transfer Count
AnnaBridge 171:3a7713b1edbc 5617 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
AnnaBridge 171:3a7713b1edbc 5618 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
AnnaBridge 171:3a7713b1edbc 5619 * @var DSCT_T::SA
AnnaBridge 171:3a7713b1edbc 5620 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11
AnnaBridge 171:3a7713b1edbc 5621 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5622 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5623 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5624 * |[31:0] |SA |PDMA Transfer Source Address Register
AnnaBridge 171:3a7713b1edbc 5625 * | | |This field indicates a 32-bit source address of PDMA controller.
AnnaBridge 171:3a7713b1edbc 5626 * @var DSCT_T::DA
AnnaBridge 171:3a7713b1edbc 5627 * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11
AnnaBridge 171:3a7713b1edbc 5628 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5629 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5630 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5631 * |[31:0] |DA |PDMA Transfer Destination Address Register
AnnaBridge 171:3a7713b1edbc 5632 * | | |This field indicates a 32-bit destination address of PDMA controller.
AnnaBridge 171:3a7713b1edbc 5633 * @var DSCT_T::NEXT
AnnaBridge 171:3a7713b1edbc 5634 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
AnnaBridge 171:3a7713b1edbc 5635 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5636 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5637 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5638 * |[15:2] |NEXT |PDMA Next Descriptor Table Offset Address Register
AnnaBridge 171:3a7713b1edbc 5639 * | | |This field indicates the offset of next descriptor table address in system memory.
AnnaBridge 171:3a7713b1edbc 5640 * | | |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
AnnaBridge 171:3a7713b1edbc 5641 * | | |Note1: The next descriptor table address must be word boundary.
AnnaBridge 171:3a7713b1edbc 5642 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
AnnaBridge 171:3a7713b1edbc 5643 */
AnnaBridge 171:3a7713b1edbc 5644
AnnaBridge 171:3a7713b1edbc 5645 __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
AnnaBridge 171:3a7713b1edbc 5646 __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
AnnaBridge 171:3a7713b1edbc 5647 __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
AnnaBridge 171:3a7713b1edbc 5648 __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
AnnaBridge 171:3a7713b1edbc 5649
AnnaBridge 171:3a7713b1edbc 5650 } DSCT_T;
AnnaBridge 171:3a7713b1edbc 5651
AnnaBridge 171:3a7713b1edbc 5652
AnnaBridge 171:3a7713b1edbc 5653
AnnaBridge 171:3a7713b1edbc 5654
AnnaBridge 171:3a7713b1edbc 5655 typedef struct
AnnaBridge 171:3a7713b1edbc 5656 {
AnnaBridge 171:3a7713b1edbc 5657
AnnaBridge 171:3a7713b1edbc 5658
AnnaBridge 171:3a7713b1edbc 5659 /**
AnnaBridge 171:3a7713b1edbc 5660 * @var PDMA_T::DSCT
AnnaBridge 171:3a7713b1edbc 5661 * Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11
AnnaBridge 171:3a7713b1edbc 5662 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5663 * @var PDMA_T::CURSCAT
AnnaBridge 171:3a7713b1edbc 5664 * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
AnnaBridge 171:3a7713b1edbc 5665 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5666 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5667 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5668 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
AnnaBridge 171:3a7713b1edbc 5669 * | | |This field indicates a 32-bit current external description address of PDMA controller.
AnnaBridge 171:3a7713b1edbc 5670 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
AnnaBridge 171:3a7713b1edbc 5671 * @var PDMA_T::CHCTL
AnnaBridge 171:3a7713b1edbc 5672 * Offset: 0x400 PDMA Channel Control Register
AnnaBridge 171:3a7713b1edbc 5673 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5674 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5675 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5676 * |[11:0] |CHENn |PDMA Channel Enable Bit
AnnaBridge 171:3a7713b1edbc 5677 * | | |Set this bit to 1 to enable PDMAn operation.
AnnaBridge 171:3a7713b1edbc 5678 * | | |If each channel is not set as enabled, each channel cannot be active.
AnnaBridge 171:3a7713b1edbc 5679 * | | |0 = PDMA channel [n] Disabled.
AnnaBridge 171:3a7713b1edbc 5680 * | | |1 = PDMA channel [n] Enabled.
AnnaBridge 171:3a7713b1edbc 5681 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
AnnaBridge 171:3a7713b1edbc 5682 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
AnnaBridge 171:3a7713b1edbc 5683 * @var PDMA_T::STOP
AnnaBridge 171:3a7713b1edbc 5684 * Offset: 0x404 PDMA Transfer Stop Control Register
AnnaBridge 171:3a7713b1edbc 5685 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5686 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5687 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5688 * |[11:0] |STOPn |PDMA Transfer Stop Control Register (Write Only)
AnnaBridge 171:3a7713b1edbc 5689 * | | |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
AnnaBridge 171:3a7713b1edbc 5690 * | | |By bit field:
AnnaBridge 171:3a7713b1edbc 5691 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 5692 * | | |1 = Stop PDMA transfer[n].
AnnaBridge 171:3a7713b1edbc 5693 * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
AnnaBridge 171:3a7713b1edbc 5694 * | | |By write 0xFFFF_FFFF to PDMA_STOP:
AnnaBridge 171:3a7713b1edbc 5695 * | | |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
AnnaBridge 171:3a7713b1edbc 5696 * | | |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
AnnaBridge 171:3a7713b1edbc 5697 * | | |Note: User can poll channel enable bit to know if the on-going transfer is finished.
AnnaBridge 171:3a7713b1edbc 5698 * @var PDMA_T::SWREQ
AnnaBridge 171:3a7713b1edbc 5699 * Offset: 0x408 PDMA Software Request Register
AnnaBridge 171:3a7713b1edbc 5700 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5701 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5702 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5703 * |[11:0] |SWREQn |PDMA Software Request Register (Write Only)
AnnaBridge 171:3a7713b1edbc 5704 * | | |Set this bit to 1 to generate a software request to PDMA [n].
AnnaBridge 171:3a7713b1edbc 5705 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 5706 * | | |1 = Generate a software request.
AnnaBridge 171:3a7713b1edbc 5707 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
AnnaBridge 171:3a7713b1edbc 5708 * | | |Active flag may be triggered by software request or peripheral request.
AnnaBridge 171:3a7713b1edbc 5709 * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
AnnaBridge 171:3a7713b1edbc 5710 * @var PDMA_T::TRGSTS
AnnaBridge 171:3a7713b1edbc 5711 * Offset: 0x40C PDMA Channel Request Status Register
AnnaBridge 171:3a7713b1edbc 5712 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5713 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5714 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5715 * |[11:0] |REQSTSn |PDMA Channel Request Status (Read Only)
AnnaBridge 171:3a7713b1edbc 5716 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
AnnaBridge 171:3a7713b1edbc 5717 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 5718 * | | |0 = PDMA Channel n has no request.
AnnaBridge 171:3a7713b1edbc 5719 * | | |1 = PDMA Channel n has a request.
AnnaBridge 171:3a7713b1edbc 5720 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
AnnaBridge 171:3a7713b1edbc 5721 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
AnnaBridge 171:3a7713b1edbc 5722 * @var PDMA_T::PRISET
AnnaBridge 171:3a7713b1edbc 5723 * Offset: 0x410 PDMA Fixed Priority Setting Register
AnnaBridge 171:3a7713b1edbc 5724 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5725 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5726 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5727 * |[11:0] |FPRISETn |PDMA Fixed Priority Setting Register
AnnaBridge 171:3a7713b1edbc 5728 * | | |Set this bit to 1 to enable fixed priority level.
AnnaBridge 171:3a7713b1edbc 5729 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 5730 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 5731 * | | |1 = Set PDMA channel [n] to fixed priority channel.
AnnaBridge 171:3a7713b1edbc 5732 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 5733 * | | |0 = Corresponding PDMA channel is round-robin priority.
AnnaBridge 171:3a7713b1edbc 5734 * | | |1 = Corresponding PDMA channel is fixed priority.
AnnaBridge 171:3a7713b1edbc 5735 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
AnnaBridge 171:3a7713b1edbc 5736 * @var PDMA_T::PRICLR
AnnaBridge 171:3a7713b1edbc 5737 * Offset: 0x414 PDMA Fixed Priority Clear Register
AnnaBridge 171:3a7713b1edbc 5738 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5739 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5740 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5741 * |[11:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
AnnaBridge 171:3a7713b1edbc 5742 * | | |Set this bit to 1 to clear fixed priority level.
AnnaBridge 171:3a7713b1edbc 5743 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 5744 * | | |1 = Clear PDMA channel [n] fixed priority setting.
AnnaBridge 171:3a7713b1edbc 5745 * | | |Note: User can read PDMA_PRISET register to know the channel priority.
AnnaBridge 171:3a7713b1edbc 5746 * @var PDMA_T::INTEN
AnnaBridge 171:3a7713b1edbc 5747 * Offset: 0x418 PDMA Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 5748 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5749 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5750 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5751 * |[11:0] |INTENn |PDMA Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 5752 * | | |This field is used for enabling PDMA channel[n] interrupt.
AnnaBridge 171:3a7713b1edbc 5753 * | | |0 = PDMA channel n interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 5754 * | | |1 = PDMA channel n interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 5755 * |[31:12] |Reserved |should be keep 0.
AnnaBridge 171:3a7713b1edbc 5756 * @var PDMA_T::INTSTS
AnnaBridge 171:3a7713b1edbc 5757 * Offset: 0x41C PDMA Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 5758 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5759 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5760 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5761 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
AnnaBridge 171:3a7713b1edbc 5762 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
AnnaBridge 171:3a7713b1edbc 5763 * | | |0 = No AHB bus ERROR response received.
AnnaBridge 171:3a7713b1edbc 5764 * | | |1 = AHB bus ERROR response received.
AnnaBridge 171:3a7713b1edbc 5765 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 5766 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
AnnaBridge 171:3a7713b1edbc 5767 * | | |0 = Not finished yet.
AnnaBridge 171:3a7713b1edbc 5768 * | | |1 = PDMA channel has finished transmission.
AnnaBridge 171:3a7713b1edbc 5769 * |[2] |TEIF |Table Empty Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 5770 * | | |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
AnnaBridge 171:3a7713b1edbc 5771 * | | |User can read TEIF register to indicate which channel finished transfer.
AnnaBridge 171:3a7713b1edbc 5772 * | | |0 = PDMA channel transfer is not finished.
AnnaBridge 171:3a7713b1edbc 5773 * | | |1 = PDMA channel transfer is finished and the operation is in idle state.
AnnaBridge 171:3a7713b1edbc 5774 * |[8:15] |REQTOFn |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 5775 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
AnnaBridge 171:3a7713b1edbc 5776 * | | |0 = No request time-out.
AnnaBridge 171:3a7713b1edbc 5777 * | | |1 = Peripheral request time-out.
AnnaBridge 171:3a7713b1edbc 5778 * @var PDMA_T::ABTSTS
AnnaBridge 171:3a7713b1edbc 5779 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
AnnaBridge 171:3a7713b1edbc 5780 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5781 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5782 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5783 * |[11:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
AnnaBridge 171:3a7713b1edbc 5784 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
AnnaBridge 171:3a7713b1edbc 5785 * | | |0 = No AHB bus ERROR response received when channel n transfer.
AnnaBridge 171:3a7713b1edbc 5786 * | | |1 = AHB bus ERROR response received when channel n transfer.
AnnaBridge 171:3a7713b1edbc 5787 * @var PDMA_T::TDSTS
AnnaBridge 171:3a7713b1edbc 5788 * Offset: 0x424 PDMA Channel Transfer Done Flag Register
AnnaBridge 171:3a7713b1edbc 5789 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5790 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5791 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5792 * |[11:0] |TDIFn |Transfer Done Flag Register
AnnaBridge 171:3a7713b1edbc 5793 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
AnnaBridge 171:3a7713b1edbc 5794 * | | |0 = PDMA channel transfer has not finished.
AnnaBridge 171:3a7713b1edbc 5795 * | | |1 = PDMA channel has finished transmission.
AnnaBridge 171:3a7713b1edbc 5796 * @var PDMA_T::SCATSTS
AnnaBridge 171:3a7713b1edbc 5797 * Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register
AnnaBridge 171:3a7713b1edbc 5798 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5799 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5800 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5801 * |[11:0] |TEMPTYFn |Scatter-Gather Table Empty Flag Register
AnnaBridge 171:3a7713b1edbc 5802 * | | |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
AnnaBridge 171:3a7713b1edbc 5803 * | | |User can write 1 to clear these bits.
AnnaBridge 171:3a7713b1edbc 5804 * | | |0 = PDMA channel scatter-gather table is not empty.
AnnaBridge 171:3a7713b1edbc 5805 * | | |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
AnnaBridge 171:3a7713b1edbc 5806 * @var PDMA_T::TACTSTS
AnnaBridge 171:3a7713b1edbc 5807 * Offset: 0x42C PDMA Transfer Active Flag Register
AnnaBridge 171:3a7713b1edbc 5808 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5809 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5810 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5811 * |[11:0] |TXACTFn |Transfer On Active Flag Register (Read Only)
AnnaBridge 171:3a7713b1edbc 5812 * | | |This bit indicates which PDMA channel is in active.
AnnaBridge 171:3a7713b1edbc 5813 * | | |0 = PDMA channel is not finished.
AnnaBridge 171:3a7713b1edbc 5814 * | | |1 = PDMA channel is active.
AnnaBridge 171:3a7713b1edbc 5815 * @var PDMA_T::TOUTEN
AnnaBridge 171:3a7713b1edbc 5816 * Offset: 0x434 PDMA Time-out Enable register
AnnaBridge 171:3a7713b1edbc 5817 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5818 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5819 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5820 * |[7:0] |TOUTENn |PDMA Time-Out Enable Bits
AnnaBridge 171:3a7713b1edbc 5821 * | | |0 = PDMA Channel n time-out function Disable.
AnnaBridge 171:3a7713b1edbc 5822 * | | |1 = PDMA Channel n time-out function Enable.
AnnaBridge 171:3a7713b1edbc 5823 * @var PDMA_T::TOUTIEN
AnnaBridge 171:3a7713b1edbc 5824 * Offset: 0x438 PDMA Time-out Interrupt Enable register
AnnaBridge 171:3a7713b1edbc 5825 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5826 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5827 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5828 * |[7:0] |TOUTIENn |PDMA Time-Out Interrupt Enable Bits
AnnaBridge 171:3a7713b1edbc 5829 * | | |0 = PDMA Channel n time-out interrupt Disable.
AnnaBridge 171:3a7713b1edbc 5830 * | | |1 = PDMA Channel n time-out interrupt Enable.
AnnaBridge 171:3a7713b1edbc 5831 * @var PDMA_T::SCATBA
AnnaBridge 171:3a7713b1edbc 5832 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
AnnaBridge 171:3a7713b1edbc 5833 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5834 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5835 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5836 * |[31:16] |SCATBA |PDMA Scatter-Gather Descriptor Table Address Register
AnnaBridge 171:3a7713b1edbc 5837 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
AnnaBridge 171:3a7713b1edbc 5838 * | | |The next link address equation is.
AnnaBridge 171:3a7713b1edbc 5839 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
AnnaBridge 171:3a7713b1edbc 5840 * | | |Note: Only useful in Scatter-Gather mode.
AnnaBridge 171:3a7713b1edbc 5841 * @var PDMA_T::TOC0_1
AnnaBridge 171:3a7713b1edbc 5842 * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
AnnaBridge 171:3a7713b1edbc 5843 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5844 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5845 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5846 * |[31:16] |TOC1 |Time-Out Counter For Channel 1
AnnaBridge 171:3a7713b1edbc 5847 * | | |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5848 * |[15:0] |TOC0 |Time-Out Counter For Channel 0
AnnaBridge 171:3a7713b1edbc 5849 * | | |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5850 * @var PDMA_T::TOC2_3
AnnaBridge 171:3a7713b1edbc 5851 * Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register
AnnaBridge 171:3a7713b1edbc 5852 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5853 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5854 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5855 * |[31:16] |TOC3 |Time-Out Counter For Channel 3
AnnaBridge 171:3a7713b1edbc 5856 * | | |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5857 * |[15:0] |TOC2 |Time-Out Counter For Channel 2
AnnaBridge 171:3a7713b1edbc 5858 * | | |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5859 * @var PDMA_T::TOC4_5
AnnaBridge 171:3a7713b1edbc 5860 * Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register
AnnaBridge 171:3a7713b1edbc 5861 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5862 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5863 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5864 * |[31:16] |TOC5 |Time-Out Counter For Channel 5
AnnaBridge 171:3a7713b1edbc 5865 * | | |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5866 * |[15:0] |TOC4 |Time-Out Counter For Channel 4
AnnaBridge 171:3a7713b1edbc 5867 * | | |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5868 * @var PDMA_T::TOC6_7
AnnaBridge 171:3a7713b1edbc 5869 * Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register
AnnaBridge 171:3a7713b1edbc 5870 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5871 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5872 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5873 * |[31:16] |TOC7 |Time-Out Counter For Channel 7
AnnaBridge 171:3a7713b1edbc 5874 * | | |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5875 * |[15:0] |TOC6 |Time-Out Counter For Channel 6
AnnaBridge 171:3a7713b1edbc 5876 * | | |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
AnnaBridge 171:3a7713b1edbc 5877 * @var PDMA_T::REQSEL0_3
AnnaBridge 171:3a7713b1edbc 5878 * Offset: 0x480 PDMA Request Source Select Register 0
AnnaBridge 171:3a7713b1edbc 5879 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5880 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5881 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5882 * |[4:0] |REQSRC0 |Channel 0 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5883 * | | |This filed defines which peripheral is connected to PDMA channel 0.
AnnaBridge 171:3a7713b1edbc 5884 * | | |User can configure the peripheral by setting REQSRC0.
AnnaBridge 171:3a7713b1edbc 5885 * | | |1 = Channel connects to SPI0_TX.
AnnaBridge 171:3a7713b1edbc 5886 * | | |2 = Channel connects to SPI1_TX.
AnnaBridge 171:3a7713b1edbc 5887 * | | |3 = Channel connects to SPI2_TX.
AnnaBridge 171:3a7713b1edbc 5888 * | | |4 = Channel connects to UART0_TX.
AnnaBridge 171:3a7713b1edbc 5889 * | | |5 = Channel connects to UART1_TX.
AnnaBridge 171:3a7713b1edbc 5890 * | | |6 = Channel connects to UART2_TX.
AnnaBridge 171:3a7713b1edbc 5891 * | | |7 = Channel connects to UART3_TX.
AnnaBridge 171:3a7713b1edbc 5892 * | | |8 = Channel connects to DAC_TX.
AnnaBridge 171:3a7713b1edbc 5893 * | | |9 = Channel connects to ADC_RX.
AnnaBridge 171:3a7713b1edbc 5894 * | | |11 = Channel connects to PWM0_P1_RX.
AnnaBridge 171:3a7713b1edbc 5895 * | | |12 = Channel connects to PWM0_P2_RX.
AnnaBridge 171:3a7713b1edbc 5896 * | | |13 = Channel connects to PWM0_P3_RX.
AnnaBridge 171:3a7713b1edbc 5897 * | | |14 = Channel connects to PWM1_P1_RX.
AnnaBridge 171:3a7713b1edbc 5898 * | | |15 = Channel connects to PWM1_P2_RX.
AnnaBridge 171:3a7713b1edbc 5899 * | | |16 = Channel connects to PWM1_P3_RX.
AnnaBridge 171:3a7713b1edbc 5900 * | | |17 = Channel connects to SPI0_RX.
AnnaBridge 171:3a7713b1edbc 5901 * | | |18 = Channel connects to SPI1_RX.
AnnaBridge 171:3a7713b1edbc 5902 * | | |19 = Channel connects to SPI2_RX.
AnnaBridge 171:3a7713b1edbc 5903 * | | |20 = Channel connects to UART0_RX.
AnnaBridge 171:3a7713b1edbc 5904 * | | |21 = Channel connects to UART1_RX.
AnnaBridge 171:3a7713b1edbc 5905 * | | |22 = Channel connects to UART2_RX.
AnnaBridge 171:3a7713b1edbc 5906 * | | |23 = Channel connects to UART3_RX.
AnnaBridge 171:3a7713b1edbc 5907 * | | |31 = Disable PDMA.
AnnaBridge 171:3a7713b1edbc 5908 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 5909 * | | |Note 1: A peripheral can't assign to two channels at the same time.
AnnaBridge 171:3a7713b1edbc 5910 * | | |Note 2: This field is useless when transfer between memory and memory.
AnnaBridge 171:3a7713b1edbc 5911 * |[12:8] |REQSRC1 |Channel 1 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5912 * | | |This filed defines which peripheral is connected to PDMA channel 1.
AnnaBridge 171:3a7713b1edbc 5913 * | | |User can configure the peripheral setting by REQSRC1.
AnnaBridge 171:3a7713b1edbc 5914 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5915 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5916 * |[20:16] |REQSRC2 |Channel 2 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5917 * | | |This filed defines which peripheral is connected to PDMA channel 2.
AnnaBridge 171:3a7713b1edbc 5918 * | | |User can configure the peripheral setting by REQSRC2.
AnnaBridge 171:3a7713b1edbc 5919 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5920 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5921 * |[28:24] |REQSRC3 |Channel 3 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5922 * | | |This filed defines which peripheral is connected to PDMA channel 3.
AnnaBridge 171:3a7713b1edbc 5923 * | | |User can configure the peripheral setting by REQSRC3.
AnnaBridge 171:3a7713b1edbc 5924 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5925 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5926 * @var PDMA_T::REQSEL4_7
AnnaBridge 171:3a7713b1edbc 5927 * Offset: 0x484 PDMA Request Source Select Register 1
AnnaBridge 171:3a7713b1edbc 5928 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5929 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5930 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5931 * |[4:0] |REQSRC4 |Channel 4 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5932 * | | |This filed defines which peripheral is connected to PDMA channel 4.
AnnaBridge 171:3a7713b1edbc 5933 * | | |User can configure the peripheral setting by REQSRC4.
AnnaBridge 171:3a7713b1edbc 5934 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5935 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5936 * |[12:8] |REQSRC5 |Channel 5 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5937 * | | |This filed defines which peripheral is connected to PDMA channel 5.
AnnaBridge 171:3a7713b1edbc 5938 * | | |User can configure the peripheral setting by REQSRC5.
AnnaBridge 171:3a7713b1edbc 5939 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5940 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5941 * |[20:16] |REQSRC6 |Channel 6 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5942 * | | |This filed defines which peripheral is connected to PDMA channel 6.
AnnaBridge 171:3a7713b1edbc 5943 * | | |User can configure the peripheral setting by REQSRC6.
AnnaBridge 171:3a7713b1edbc 5944 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5945 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5946 * |[28:24] |REQSRC7 |Channel 7 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5947 * | | |This filed defines which peripheral is connected to PDMA channel 7.
AnnaBridge 171:3a7713b1edbc 5948 * | | |User can configure the peripheral setting by REQSRC7.
AnnaBridge 171:3a7713b1edbc 5949 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5950 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5951 * @var PDMA_T::REQSEL8_11
AnnaBridge 171:3a7713b1edbc 5952 * Offset: 0x488 PDMA Request Source Select Register 2
AnnaBridge 171:3a7713b1edbc 5953 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5954 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 5955 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 5956 * |[4:0] |REQSRC8 |Channel 8 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5957 * | | |This filed defines which peripheral is connected to PDMA channel 8.
AnnaBridge 171:3a7713b1edbc 5958 * | | |User can configure the peripheral setting by REQSRC8.
AnnaBridge 171:3a7713b1edbc 5959 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5960 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5961 * |[12:8] |REQSRC9 |Channel 9 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5962 * | | |This filed defines which peripheral is connected to PDMA channel 9.
AnnaBridge 171:3a7713b1edbc 5963 * | | |User can configure the peripheral setting by REQSRC9.
AnnaBridge 171:3a7713b1edbc 5964 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5965 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5966 * |[20:16] |REQSRC10 |Channel 10 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5967 * | | |This filed defines which peripheral is connected to PDMA channel 10.
AnnaBridge 171:3a7713b1edbc 5968 * | | |User can configure the peripheral setting by REQSRC10.
AnnaBridge 171:3a7713b1edbc 5969 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5970 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5971 * |[28:24] |REQSRC11 |Channel 11 Request Source Selection
AnnaBridge 171:3a7713b1edbc 5972 * | | |This filed defines which peripheral is connected to PDMA channel 11.
AnnaBridge 171:3a7713b1edbc 5973 * | | |User can configure the peripheral setting by REQSRC11.
AnnaBridge 171:3a7713b1edbc 5974 * | | |Note: The channel configuration is the same as REQSRC0 field.
AnnaBridge 171:3a7713b1edbc 5975 * | | |Please refer to the explanation of REQSRC0.
AnnaBridge 171:3a7713b1edbc 5976 */
AnnaBridge 171:3a7713b1edbc 5977
AnnaBridge 171:3a7713b1edbc 5978 DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
AnnaBridge 171:3a7713b1edbc 5979 __I uint32_t CURSCAT[12];
AnnaBridge 171:3a7713b1edbc 5980 __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
AnnaBridge 171:3a7713b1edbc 5981 __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
AnnaBridge 171:3a7713b1edbc 5982 __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
AnnaBridge 171:3a7713b1edbc 5983 __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
AnnaBridge 171:3a7713b1edbc 5984 __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
AnnaBridge 171:3a7713b1edbc 5985 __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
AnnaBridge 171:3a7713b1edbc 5986 __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
AnnaBridge 171:3a7713b1edbc 5987 __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 5988 __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 5989 __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
AnnaBridge 171:3a7713b1edbc 5990 __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
AnnaBridge 171:3a7713b1edbc 5991 __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
AnnaBridge 171:3a7713b1edbc 5992 __I uint32_t TACTSTS;
AnnaBridge 171:3a7713b1edbc 5993 __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
AnnaBridge 171:3a7713b1edbc 5994 __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
AnnaBridge 171:3a7713b1edbc 5995 __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 5996 __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
AnnaBridge 171:3a7713b1edbc 5997 __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
AnnaBridge 171:3a7713b1edbc 5998 __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
AnnaBridge 171:3a7713b1edbc 5999 __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
AnnaBridge 171:3a7713b1edbc 6000 __IO uint32_t TOC6_7;
AnnaBridge 171:3a7713b1edbc 6001 __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
AnnaBridge 171:3a7713b1edbc 6002 __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
AnnaBridge 171:3a7713b1edbc 6003 __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
AnnaBridge 171:3a7713b1edbc 6004 __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
AnnaBridge 171:3a7713b1edbc 6005
AnnaBridge 171:3a7713b1edbc 6006 } PDMA_T;
AnnaBridge 171:3a7713b1edbc 6007
AnnaBridge 171:3a7713b1edbc 6008
AnnaBridge 171:3a7713b1edbc 6009
AnnaBridge 171:3a7713b1edbc 6010 /**
AnnaBridge 171:3a7713b1edbc 6011 @addtogroup PDMA_CONST PDMA Bit Field Definition
AnnaBridge 171:3a7713b1edbc 6012 Constant Definitions for PDMA Controller
AnnaBridge 171:3a7713b1edbc 6013 @{ */
AnnaBridge 171:3a7713b1edbc 6014
AnnaBridge 171:3a7713b1edbc 6015 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 6016 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
AnnaBridge 171:3a7713b1edbc 6017
AnnaBridge 171:3a7713b1edbc 6018 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
AnnaBridge 171:3a7713b1edbc 6019 #define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
AnnaBridge 171:3a7713b1edbc 6020
AnnaBridge 171:3a7713b1edbc 6021 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
AnnaBridge 171:3a7713b1edbc 6022 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
AnnaBridge 171:3a7713b1edbc 6023
AnnaBridge 171:3a7713b1edbc 6024 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
AnnaBridge 171:3a7713b1edbc 6025 #define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
AnnaBridge 171:3a7713b1edbc 6026
AnnaBridge 171:3a7713b1edbc 6027 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
AnnaBridge 171:3a7713b1edbc 6028 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
AnnaBridge 171:3a7713b1edbc 6029
AnnaBridge 171:3a7713b1edbc 6030 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
AnnaBridge 171:3a7713b1edbc 6031 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
AnnaBridge 171:3a7713b1edbc 6032
AnnaBridge 171:3a7713b1edbc 6033 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
AnnaBridge 171:3a7713b1edbc 6034 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
AnnaBridge 171:3a7713b1edbc 6035
AnnaBridge 171:3a7713b1edbc 6036 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
AnnaBridge 171:3a7713b1edbc 6037 #define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
AnnaBridge 171:3a7713b1edbc 6038
AnnaBridge 171:3a7713b1edbc 6039 #define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
AnnaBridge 171:3a7713b1edbc 6040 #define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
AnnaBridge 171:3a7713b1edbc 6041
AnnaBridge 171:3a7713b1edbc 6042 #define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
AnnaBridge 171:3a7713b1edbc 6043 #define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
AnnaBridge 171:3a7713b1edbc 6044
AnnaBridge 171:3a7713b1edbc 6045 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
AnnaBridge 171:3a7713b1edbc 6046 #define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
AnnaBridge 171:3a7713b1edbc 6047
AnnaBridge 171:3a7713b1edbc 6048 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
AnnaBridge 171:3a7713b1edbc 6049 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
AnnaBridge 171:3a7713b1edbc 6050
AnnaBridge 171:3a7713b1edbc 6051 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
AnnaBridge 171:3a7713b1edbc 6052 #define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
AnnaBridge 171:3a7713b1edbc 6053
AnnaBridge 171:3a7713b1edbc 6054 #define PDMA_STOP_STOPn_Pos (0) /*!< PDMA_T::STOP: STOPn Position */
AnnaBridge 171:3a7713b1edbc 6055 #define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) /*!< PDMA_T::STOP: STOPn Mask */
AnnaBridge 171:3a7713b1edbc 6056
AnnaBridge 171:3a7713b1edbc 6057 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
AnnaBridge 171:3a7713b1edbc 6058 #define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
AnnaBridge 171:3a7713b1edbc 6059
AnnaBridge 171:3a7713b1edbc 6060 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
AnnaBridge 171:3a7713b1edbc 6061 #define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
AnnaBridge 171:3a7713b1edbc 6062
AnnaBridge 171:3a7713b1edbc 6063 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
AnnaBridge 171:3a7713b1edbc 6064 #define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
AnnaBridge 171:3a7713b1edbc 6065
AnnaBridge 171:3a7713b1edbc 6066 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
AnnaBridge 171:3a7713b1edbc 6067 #define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
AnnaBridge 171:3a7713b1edbc 6068
AnnaBridge 171:3a7713b1edbc 6069 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
AnnaBridge 171:3a7713b1edbc 6070 #define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
AnnaBridge 171:3a7713b1edbc 6071
AnnaBridge 171:3a7713b1edbc 6072 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
AnnaBridge 171:3a7713b1edbc 6073 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
AnnaBridge 171:3a7713b1edbc 6074
AnnaBridge 171:3a7713b1edbc 6075 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
AnnaBridge 171:3a7713b1edbc 6076 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
AnnaBridge 171:3a7713b1edbc 6077
AnnaBridge 171:3a7713b1edbc 6078 #define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA_T::INTSTS: TEIF Position */
AnnaBridge 171:3a7713b1edbc 6079 #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA_T::INTSTS: TEIF Mask */
AnnaBridge 171:3a7713b1edbc 6080
AnnaBridge 171:3a7713b1edbc 6081 #define PDMA_INTSTS_REQTOFn_Pos (8) /*!< PDMA_T::INTSTS: REQTOFn Position */
AnnaBridge 171:3a7713b1edbc 6082 #define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) /*!< PDMA_T::INTSTS: REQTOFn Mask */
AnnaBridge 171:3a7713b1edbc 6083
AnnaBridge 171:3a7713b1edbc 6084 #define PDMA_ABTSTS_ABTIFn_Pos (0) /*!< PDMA_T::ABTSTS: ABTIFn Position */
AnnaBridge 171:3a7713b1edbc 6085 #define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) /*!< PDMA_T::ABTSTS: ABTIFn Mask */
AnnaBridge 171:3a7713b1edbc 6086
AnnaBridge 171:3a7713b1edbc 6087 #define PDMA_TDSTS_TDIFn_Pos (0) /*!< PDMA_T::TDSTS: TDIFn Position */
AnnaBridge 171:3a7713b1edbc 6088 #define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) /*!< PDMA_T::TDSTS: TDIFn Mask */
AnnaBridge 171:3a7713b1edbc 6089
AnnaBridge 171:3a7713b1edbc 6090 #define PDMA_SCATSTS_TEMPTYFn_Pos (0) /*!< PDMA_T::SCATSTS: TEMPTYFn Position */
AnnaBridge 171:3a7713b1edbc 6091 #define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) /*!< PDMA_T::SCATSTS: TEMPTYFn Mask */
AnnaBridge 171:3a7713b1edbc 6092
AnnaBridge 171:3a7713b1edbc 6093 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
AnnaBridge 171:3a7713b1edbc 6094 #define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
AnnaBridge 171:3a7713b1edbc 6095
AnnaBridge 171:3a7713b1edbc 6096 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
AnnaBridge 171:3a7713b1edbc 6097 #define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
AnnaBridge 171:3a7713b1edbc 6098
AnnaBridge 171:3a7713b1edbc 6099 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
AnnaBridge 171:3a7713b1edbc 6100 #define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
AnnaBridge 171:3a7713b1edbc 6101
AnnaBridge 171:3a7713b1edbc 6102 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
AnnaBridge 171:3a7713b1edbc 6103 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
AnnaBridge 171:3a7713b1edbc 6104
AnnaBridge 171:3a7713b1edbc 6105 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
AnnaBridge 171:3a7713b1edbc 6106 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
AnnaBridge 171:3a7713b1edbc 6107
AnnaBridge 171:3a7713b1edbc 6108 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
AnnaBridge 171:3a7713b1edbc 6109 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
AnnaBridge 171:3a7713b1edbc 6110
AnnaBridge 171:3a7713b1edbc 6111 #define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */
AnnaBridge 171:3a7713b1edbc 6112 #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */
AnnaBridge 171:3a7713b1edbc 6113
AnnaBridge 171:3a7713b1edbc 6114 #define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */
AnnaBridge 171:3a7713b1edbc 6115 #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */
AnnaBridge 171:3a7713b1edbc 6116
AnnaBridge 171:3a7713b1edbc 6117 #define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */
AnnaBridge 171:3a7713b1edbc 6118 #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */
AnnaBridge 171:3a7713b1edbc 6119
AnnaBridge 171:3a7713b1edbc 6120 #define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */
AnnaBridge 171:3a7713b1edbc 6121 #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */
AnnaBridge 171:3a7713b1edbc 6122
AnnaBridge 171:3a7713b1edbc 6123 #define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */
AnnaBridge 171:3a7713b1edbc 6124 #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */
AnnaBridge 171:3a7713b1edbc 6125
AnnaBridge 171:3a7713b1edbc 6126 #define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */
AnnaBridge 171:3a7713b1edbc 6127 #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */
AnnaBridge 171:3a7713b1edbc 6128
AnnaBridge 171:3a7713b1edbc 6129 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
AnnaBridge 171:3a7713b1edbc 6130 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
AnnaBridge 171:3a7713b1edbc 6131
AnnaBridge 171:3a7713b1edbc 6132 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
AnnaBridge 171:3a7713b1edbc 6133 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
AnnaBridge 171:3a7713b1edbc 6134
AnnaBridge 171:3a7713b1edbc 6135 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
AnnaBridge 171:3a7713b1edbc 6136 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
AnnaBridge 171:3a7713b1edbc 6137
AnnaBridge 171:3a7713b1edbc 6138 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
AnnaBridge 171:3a7713b1edbc 6139 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
AnnaBridge 171:3a7713b1edbc 6140
AnnaBridge 171:3a7713b1edbc 6141 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
AnnaBridge 171:3a7713b1edbc 6142 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
AnnaBridge 171:3a7713b1edbc 6143
AnnaBridge 171:3a7713b1edbc 6144 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
AnnaBridge 171:3a7713b1edbc 6145 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
AnnaBridge 171:3a7713b1edbc 6146
AnnaBridge 171:3a7713b1edbc 6147 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
AnnaBridge 171:3a7713b1edbc 6148 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
AnnaBridge 171:3a7713b1edbc 6149
AnnaBridge 171:3a7713b1edbc 6150 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
AnnaBridge 171:3a7713b1edbc 6151 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
AnnaBridge 171:3a7713b1edbc 6152
AnnaBridge 171:3a7713b1edbc 6153 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
AnnaBridge 171:3a7713b1edbc 6154 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
AnnaBridge 171:3a7713b1edbc 6155
AnnaBridge 171:3a7713b1edbc 6156 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
AnnaBridge 171:3a7713b1edbc 6157 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
AnnaBridge 171:3a7713b1edbc 6158
AnnaBridge 171:3a7713b1edbc 6159 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
AnnaBridge 171:3a7713b1edbc 6160 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
AnnaBridge 171:3a7713b1edbc 6161
AnnaBridge 171:3a7713b1edbc 6162 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
AnnaBridge 171:3a7713b1edbc 6163 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
AnnaBridge 171:3a7713b1edbc 6164
AnnaBridge 171:3a7713b1edbc 6165 /**@}*/ /* PDMA_CONST */
AnnaBridge 171:3a7713b1edbc 6166 /**@}*/ /* end of PDMA register group */
AnnaBridge 171:3a7713b1edbc 6167
AnnaBridge 171:3a7713b1edbc 6168
AnnaBridge 171:3a7713b1edbc 6169 /*---------------------- Pulse Width Modulation Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 6170 /**
AnnaBridge 171:3a7713b1edbc 6171 @addtogroup PWM Pulse Width Modulation Controller(PWM)
AnnaBridge 171:3a7713b1edbc 6172 Memory Mapped Structure for PWM Controller
AnnaBridge 171:3a7713b1edbc 6173 @{ */
AnnaBridge 171:3a7713b1edbc 6174
AnnaBridge 171:3a7713b1edbc 6175
AnnaBridge 171:3a7713b1edbc 6176 typedef struct
AnnaBridge 171:3a7713b1edbc 6177 {
AnnaBridge 171:3a7713b1edbc 6178
AnnaBridge 171:3a7713b1edbc 6179
AnnaBridge 171:3a7713b1edbc 6180 /**
AnnaBridge 171:3a7713b1edbc 6181 * @var PWM_T::CTL0
AnnaBridge 171:3a7713b1edbc 6182 * Offset: 0x00 PWM Control Register 0
AnnaBridge 171:3a7713b1edbc 6183 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6184 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6185 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6186 * |[5:0] |CTRLDn |Center Re-Load
AnnaBridge 171:3a7713b1edbc 6187 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6188 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
AnnaBridge 171:3a7713b1edbc 6189 * | | |CMPDAT will load to CMPBUF at the center point of a period.
AnnaBridge 171:3a7713b1edbc 6190 * |[13:8] |WINLDENn |Window Load Enable
AnnaBridge 171:3a7713b1edbc 6191 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6192 * | | |0 = PERIOD will load to PBUF at the end point of each period.
AnnaBridge 171:3a7713b1edbc 6193 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 171:3a7713b1edbc 6194 * | | |1 = PERIOD will load to PBUF at the end point of each period.
AnnaBridge 171:3a7713b1edbc 6195 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
AnnaBridge 171:3a7713b1edbc 6196 * | | |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
AnnaBridge 171:3a7713b1edbc 6197 * |[21:16] |IMMLDENn |Immediately Load Enable
AnnaBridge 171:3a7713b1edbc 6198 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6199 * | | |0 = PERIOD will load to PBUF at the end point of each period.
AnnaBridge 171:3a7713b1edbc 6200 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 171:3a7713b1edbc 6201 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 171:3a7713b1edbc 6202 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 171:3a7713b1edbc 6203 * |[24] |GROUPEN |Group Function Enable
AnnaBridge 171:3a7713b1edbc 6204 * | | |0 = The output waveform of each PWM channel are independent.
AnnaBridge 171:3a7713b1edbc 6205 * | | |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
AnnaBridge 171:3a7713b1edbc 6206 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
AnnaBridge 171:3a7713b1edbc 6207 * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
AnnaBridge 171:3a7713b1edbc 6208 * | | |0 = ICE debug mode counter halt disable.
AnnaBridge 171:3a7713b1edbc 6209 * | | |1 = ICE debug mode counter halt enable.
AnnaBridge 171:3a7713b1edbc 6210 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6211 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
AnnaBridge 171:3a7713b1edbc 6212 * | | |0 = ICE debug mode acknowledgement effects PWM output.
AnnaBridge 171:3a7713b1edbc 6213 * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
AnnaBridge 171:3a7713b1edbc 6214 * | | |1 = ICE debug mode acknowledgement disabled.
AnnaBridge 171:3a7713b1edbc 6215 * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
AnnaBridge 171:3a7713b1edbc 6216 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6217 * @var PWM_T::CTL1
AnnaBridge 171:3a7713b1edbc 6218 * Offset: 0x04 PWM Control Register 1
AnnaBridge 171:3a7713b1edbc 6219 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6220 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6221 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6222 * |[11:0] |CNTTYPEn |PWM Counter Behavior Type
AnnaBridge 171:3a7713b1edbc 6223 * | | |Each bit n controls corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6224 * | | |00 = Up counter type (supports in capture mode).
AnnaBridge 171:3a7713b1edbc 6225 * | | |01 = Down count type (supports in capture mode).
AnnaBridge 171:3a7713b1edbc 6226 * | | |10 = Up-down counter type.
AnnaBridge 171:3a7713b1edbc 6227 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 6228 * |[21:16] |CNTMODEn |PWM Counter Mode
AnnaBridge 171:3a7713b1edbc 6229 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6230 * | | |0 = Auto-reload mode.
AnnaBridge 171:3a7713b1edbc 6231 * | | |1 = One-shot mode.
AnnaBridge 171:3a7713b1edbc 6232 * |[26:24] |OUTMODEn |PWM Output Mode
AnnaBridge 171:3a7713b1edbc 6233 * | | |Each bit n controls the
AnnaBridge 171:3a7713b1edbc 6234 * | | |output mode of
AnnaBridge 171:3a7713b1edbc 6235 * | | |corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6236 * | | |0 = PWM independent mode.
AnnaBridge 171:3a7713b1edbc 6237 * | | |1 = PWM complementary mode.
AnnaBridge 171:3a7713b1edbc 6238 * | | |Note: When operating in group function, these bits must all set to the same mode.
AnnaBridge 171:3a7713b1edbc 6239 * @var PWM_T::SYNC
AnnaBridge 171:3a7713b1edbc 6240 * Offset: 0x08 PWM Synchronization Register
AnnaBridge 171:3a7713b1edbc 6241 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6242 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6243 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6244 * |[2:0] |PHSENn |SYNC Phase Enable
AnnaBridge 171:3a7713b1edbc 6245 * | | |Each bit n controls corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6246 * | | |0 = PWM counter disable to load PHS value.
AnnaBridge 171:3a7713b1edbc 6247 * | | |1 = PWM counter enable to load PHS value.
AnnaBridge 171:3a7713b1edbc 6248 * |[13:8] |SINSRCn |PWM_SYNC_IN Source Selection
AnnaBridge 171:3a7713b1edbc 6249 * | | |Each bit n controls corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6250 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
AnnaBridge 171:3a7713b1edbc 6251 * | | |01 = Counter equal to 0.
AnnaBridge 171:3a7713b1edbc 6252 * | | |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
AnnaBridge 171:3a7713b1edbc 6253 * | | |11 = SYNC_OUT will not be generated.
AnnaBridge 171:3a7713b1edbc 6254 * |[16] |SNFLTEN |PWM_SYNC_IN Noise Filter Enable
AnnaBridge 171:3a7713b1edbc 6255 * | | |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
AnnaBridge 171:3a7713b1edbc 6256 * | | |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
AnnaBridge 171:3a7713b1edbc 6257 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
AnnaBridge 171:3a7713b1edbc 6258 * | | |000 = Filter clock = HCLK.
AnnaBridge 171:3a7713b1edbc 6259 * | | |001 = Filter clock = HCLK/2.
AnnaBridge 171:3a7713b1edbc 6260 * | | |010 = Filter clock = HCLK/4.
AnnaBridge 171:3a7713b1edbc 6261 * | | |011 = Filter clock = HCLK/8.
AnnaBridge 171:3a7713b1edbc 6262 * | | |100 = Filter clock = HCLK/16.
AnnaBridge 171:3a7713b1edbc 6263 * | | |101 = Filter clock = HCLK/32.
AnnaBridge 171:3a7713b1edbc 6264 * | | |110 = Filter clock = HCLK/64.
AnnaBridge 171:3a7713b1edbc 6265 * | | |111 = Filter clock = HCLK/128.
AnnaBridge 171:3a7713b1edbc 6266 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
AnnaBridge 171:3a7713b1edbc 6267 * | | |The register bits control the counter number of edge detector.
AnnaBridge 171:3a7713b1edbc 6268 * |[23] |SINPINV |SYNC Input Pin Inverse
AnnaBridge 171:3a7713b1edbc 6269 * | | |0 = The state of pin SYNC is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6270 * | | |1 = The inverted state of pin SYNC is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6271 * |[26:24] |PHSDIRn |PWM Phase Direction Control
AnnaBridge 171:3a7713b1edbc 6272 * | | |Each bit n controls corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6273 * | | |0 = Control PWM counter count decrement after synchronizing.
AnnaBridge 171:3a7713b1edbc 6274 * | | |1 = Control PWM counter count increment after synchronizing.
AnnaBridge 171:3a7713b1edbc 6275 * @var PWM_T::SWSYNC
AnnaBridge 171:3a7713b1edbc 6276 * Offset: 0x0C PWM Software Control Synchronization Register
AnnaBridge 171:3a7713b1edbc 6277 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6278 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6279 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6280 * |[2:0] |SWSYNCn |Software SYNC Function
AnnaBridge 171:3a7713b1edbc 6281 * | | |Each bit n controls corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6282 * | | |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
AnnaBridge 171:3a7713b1edbc 6283 * @var PWM_T::CLKSRC
AnnaBridge 171:3a7713b1edbc 6284 * Offset: 0x10 PWM Clock Source Register
AnnaBridge 171:3a7713b1edbc 6285 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6286 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6287 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6288 * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select
AnnaBridge 171:3a7713b1edbc 6289 * | | |000 = PWMx_CLK, x denotes 0 or 1.
AnnaBridge 171:3a7713b1edbc 6290 * | | |001 = TIMER0 overflow.
AnnaBridge 171:3a7713b1edbc 6291 * | | |010 = TIMER1 overflow.
AnnaBridge 171:3a7713b1edbc 6292 * | | |011 = TIMER2 overflow.
AnnaBridge 171:3a7713b1edbc 6293 * | | |100 = TIMER3 overflow.
AnnaBridge 171:3a7713b1edbc 6294 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 6295 * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select
AnnaBridge 171:3a7713b1edbc 6296 * | | |000 = PWMx_CLK, x denotes 0 or 1.
AnnaBridge 171:3a7713b1edbc 6297 * | | |001 = TIMER0 overflow.
AnnaBridge 171:3a7713b1edbc 6298 * | | |010 = TIMER1 overflow.
AnnaBridge 171:3a7713b1edbc 6299 * | | |011 = TIMER2 overflow.
AnnaBridge 171:3a7713b1edbc 6300 * | | |100 = TIMER3 overflow.
AnnaBridge 171:3a7713b1edbc 6301 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 6302 * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select
AnnaBridge 171:3a7713b1edbc 6303 * | | |000 = PWMx_CLK, x denotes 0 or 1.
AnnaBridge 171:3a7713b1edbc 6304 * | | |001 = TIMER0 overflow.
AnnaBridge 171:3a7713b1edbc 6305 * | | |010 = TIMER1 overflow.
AnnaBridge 171:3a7713b1edbc 6306 * | | |011 = TIMER2 overflow.
AnnaBridge 171:3a7713b1edbc 6307 * | | |100 = TIMER3 overflow.
AnnaBridge 171:3a7713b1edbc 6308 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 6309 * @var PWM_T::CLKPSC0_1
AnnaBridge 171:3a7713b1edbc 6310 * Offset: 0x14 PWM Clock Pre-scale Register 0
AnnaBridge 171:3a7713b1edbc 6311 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6312 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6313 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6314 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
AnnaBridge 171:3a7713b1edbc 6315 * | | |The clock of PWM counter is decided by clock prescaler.
AnnaBridge 171:3a7713b1edbc 6316 * | | |Each PWM pair share one PWM counter clock prescaler.
AnnaBridge 171:3a7713b1edbc 6317 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
AnnaBridge 171:3a7713b1edbc 6318 * @var PWM_T::CLKPSC2_3
AnnaBridge 171:3a7713b1edbc 6319 * Offset: 0x18 PWM Clock Pre-scale Register 2
AnnaBridge 171:3a7713b1edbc 6320 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6321 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6322 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6323 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
AnnaBridge 171:3a7713b1edbc 6324 * | | |The clock of PWM counter is decided by clock prescaler.
AnnaBridge 171:3a7713b1edbc 6325 * | | |Each PWM pair share one PWM counter clock prescaler.
AnnaBridge 171:3a7713b1edbc 6326 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
AnnaBridge 171:3a7713b1edbc 6327 * @var PWM_T::CLKPSC4_5
AnnaBridge 171:3a7713b1edbc 6328 * Offset: 0x1C PWM Clock Pre-scale Register 4
AnnaBridge 171:3a7713b1edbc 6329 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6330 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6331 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6332 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
AnnaBridge 171:3a7713b1edbc 6333 * | | |The clock of PWM counter is decided by clock prescaler.
AnnaBridge 171:3a7713b1edbc 6334 * | | |Each PWM pair share one PWM counter clock prescaler.
AnnaBridge 171:3a7713b1edbc 6335 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
AnnaBridge 171:3a7713b1edbc 6336 * @var PWM_T::CNTEN
AnnaBridge 171:3a7713b1edbc 6337 * Offset: 0x20 PWM Counter Enable Register
AnnaBridge 171:3a7713b1edbc 6338 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6339 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6340 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6341 * |[5:0] |CNTENn |PWM Counter Enable
AnnaBridge 171:3a7713b1edbc 6342 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6343 * | | |0 = PWM Counter and clock prescaler Stop Running.
AnnaBridge 171:3a7713b1edbc 6344 * | | |1 = PWM Counter and clock prescaler Start Running.
AnnaBridge 171:3a7713b1edbc 6345 * @var PWM_T::CNTCLR
AnnaBridge 171:3a7713b1edbc 6346 * Offset: 0x24 PWM Clear Counter Register
AnnaBridge 171:3a7713b1edbc 6347 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6348 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6349 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6350 * |[5:0] |CNTCLRn |Clear PWM Counter Control Bit
AnnaBridge 171:3a7713b1edbc 6351 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6352 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 6353 * | | |1 = Clear 16-bit PWM counter to 0000H.
AnnaBridge 171:3a7713b1edbc 6354 * @var PWM_T::LOAD
AnnaBridge 171:3a7713b1edbc 6355 * Offset: 0x28 PWM Load Register
AnnaBridge 171:3a7713b1edbc 6356 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6357 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6358 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6359 * |[5:0] |LOADn |Re-Load PWM Comparator Register (CMPDAT) Control Bit
AnnaBridge 171:3a7713b1edbc 6360 * | | |This bit is software write, hardware clear when current PWM period end.
AnnaBridge 171:3a7713b1edbc 6361 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6362 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 6363 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 6364 * | | |1 = Set load window of window loading mode.
AnnaBridge 171:3a7713b1edbc 6365 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 6366 * | | |0 = No load window is set.
AnnaBridge 171:3a7713b1edbc 6367 * | | |1 = Load window is set.
AnnaBridge 171:3a7713b1edbc 6368 * | | |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
AnnaBridge 171:3a7713b1edbc 6369 * @var PWM_T::PERIOD
AnnaBridge 171:3a7713b1edbc 6370 * Offset: 0x30~0x44 PWM Period Register 0~5
AnnaBridge 171:3a7713b1edbc 6371 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6372 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6373 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6374 * |[15:0] |PERIOD |PWM Period Register
AnnaBridge 171:3a7713b1edbc 6375 * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
AnnaBridge 171:3a7713b1edbc 6376 * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
AnnaBridge 171:3a7713b1edbc 6377 * | | |PWM period time = (PERIOD+1) * PWM_CLK period.
AnnaBridge 171:3a7713b1edbc 6378 * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
AnnaBridge 171:3a7713b1edbc 6379 * | | |PWM period time = 2 * PERIOD * PWM_CLK period.
AnnaBridge 171:3a7713b1edbc 6380 * @var PWM_T::CMPDAT
AnnaBridge 171:3a7713b1edbc 6381 * Offset: 0x50~0x64 PWM Comparator Register 0~5
AnnaBridge 171:3a7713b1edbc 6382 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6383 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6384 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6385 * |[15:0] |CMP |PWM Comparator Register
AnnaBridge 171:3a7713b1edbc 6386 * | | |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
AnnaBridge 171:3a7713b1edbc 6387 * | | |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
AnnaBridge 171:3a7713b1edbc 6388 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
AnnaBridge 171:3a7713b1edbc 6389 * @var PWM_T::DTCTL0_1
AnnaBridge 171:3a7713b1edbc 6390 * Offset: 0x70 PWM Dead-Time Control Register 0
AnnaBridge 171:3a7713b1edbc 6391 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6392 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6393 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6394 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
AnnaBridge 171:3a7713b1edbc 6395 * | | |The dead-time can be calculated from the following formula:
AnnaBridge 171:3a7713b1edbc 6396 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
AnnaBridge 171:3a7713b1edbc 6397 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6398 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
AnnaBridge 171:3a7713b1edbc 6399 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
AnnaBridge 171:3a7713b1edbc 6400 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
AnnaBridge 171:3a7713b1edbc 6401 * | | |0 = Dead-time insertion Disabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6402 * | | |1 = Dead-time insertion Enabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6403 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6404 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6405 * | | |0 = Dead-time clock source from PWM_CLK.
AnnaBridge 171:3a7713b1edbc 6406 * | | |1 = Dead-time clock source from prescaler output.
AnnaBridge 171:3a7713b1edbc 6407 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6408 * @var PWM_T::DTCTL2_3
AnnaBridge 171:3a7713b1edbc 6409 * Offset: 0x74 PWM Dead-Time Control Register 2
AnnaBridge 171:3a7713b1edbc 6410 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6411 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6412 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6413 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
AnnaBridge 171:3a7713b1edbc 6414 * | | |The dead-time can be calculated from the following formula:
AnnaBridge 171:3a7713b1edbc 6415 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
AnnaBridge 171:3a7713b1edbc 6416 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6417 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
AnnaBridge 171:3a7713b1edbc 6418 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
AnnaBridge 171:3a7713b1edbc 6419 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
AnnaBridge 171:3a7713b1edbc 6420 * | | |0 = Dead-time insertion Disabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6421 * | | |1 = Dead-time insertion Enabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6422 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6423 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6424 * | | |0 = Dead-time clock source from PWM_CLK.
AnnaBridge 171:3a7713b1edbc 6425 * | | |1 = Dead-time clock source from prescaler output.
AnnaBridge 171:3a7713b1edbc 6426 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6427 * @var PWM_T::DTCTL4_5
AnnaBridge 171:3a7713b1edbc 6428 * Offset: 0x78 PWM Dead-Time Control Register 4
AnnaBridge 171:3a7713b1edbc 6429 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6430 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6431 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6432 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
AnnaBridge 171:3a7713b1edbc 6433 * | | |The dead-time can be calculated from the following formula:
AnnaBridge 171:3a7713b1edbc 6434 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
AnnaBridge 171:3a7713b1edbc 6435 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6436 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
AnnaBridge 171:3a7713b1edbc 6437 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
AnnaBridge 171:3a7713b1edbc 6438 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
AnnaBridge 171:3a7713b1edbc 6439 * | | |0 = Dead-time insertion Disabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6440 * | | |1 = Dead-time insertion Enabled on the pin pair.
AnnaBridge 171:3a7713b1edbc 6441 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6442 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6443 * | | |0 = Dead-time clock source from PWM_CLK.
AnnaBridge 171:3a7713b1edbc 6444 * | | |1 = Dead-time clock source from prescaler output.
AnnaBridge 171:3a7713b1edbc 6445 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6446 * @var PWM_T::PHS0_1
AnnaBridge 171:3a7713b1edbc 6447 * Offset: 0x80 PWM Counter Phase Register 0
AnnaBridge 171:3a7713b1edbc 6448 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6449 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6450 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6451 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
AnnaBridge 171:3a7713b1edbc 6452 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
AnnaBridge 171:3a7713b1edbc 6453 * @var PWM_T::PHS2_3
AnnaBridge 171:3a7713b1edbc 6454 * Offset: 0x84 PWM Counter Phase Register 2
AnnaBridge 171:3a7713b1edbc 6455 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6456 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6457 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6458 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
AnnaBridge 171:3a7713b1edbc 6459 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
AnnaBridge 171:3a7713b1edbc 6460 * @var PWM_T::PHS4_5
AnnaBridge 171:3a7713b1edbc 6461 * Offset: 0x88 PWM Counter Phase Register 4
AnnaBridge 171:3a7713b1edbc 6462 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6463 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6464 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6465 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
AnnaBridge 171:3a7713b1edbc 6466 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
AnnaBridge 171:3a7713b1edbc 6467 * @var PWM_T::CNT
AnnaBridge 171:3a7713b1edbc 6468 * Offset: 0x90~0xA4 PWM Counter Register 0~5
AnnaBridge 171:3a7713b1edbc 6469 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6470 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6471 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6472 * |[15:0] |CNT |PWM Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 6473 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
AnnaBridge 171:3a7713b1edbc 6474 * |[16] |DIRF |PWM Direction Indicator Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 6475 * | | |0 = Counter is Down count.
AnnaBridge 171:3a7713b1edbc 6476 * | | |1 = Counter is UP count.
AnnaBridge 171:3a7713b1edbc 6477 * @var PWM_T::WGCTL0
AnnaBridge 171:3a7713b1edbc 6478 * Offset: 0xB0 PWM Generation Register 0
AnnaBridge 171:3a7713b1edbc 6479 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6480 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6481 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6482 * |[11:0] |ZPCTLn |PWM Zero Point Control
AnnaBridge 171:3a7713b1edbc 6483 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6484 * | | |00 = Do nothing.
AnnaBridge 171:3a7713b1edbc 6485 * | | |01 = PWM zero point output Low.
AnnaBridge 171:3a7713b1edbc 6486 * | | |10 = PWM zero point output High.
AnnaBridge 171:3a7713b1edbc 6487 * | | |11 = PWM zero point output Toggle.
AnnaBridge 171:3a7713b1edbc 6488 * | | |PWM can control output level when PWM counter count to zero.
AnnaBridge 171:3a7713b1edbc 6489 * |[27:16] |PRDPCTLn |PWM Period (Center) Point Control
AnnaBridge 171:3a7713b1edbc 6490 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6491 * | | |00 = Do nothing.
AnnaBridge 171:3a7713b1edbc 6492 * | | |01 = PWM period (center) point output Low.
AnnaBridge 171:3a7713b1edbc 6493 * | | |10 = PWM period (center) point output High.
AnnaBridge 171:3a7713b1edbc 6494 * | | |11 = PWM period (center) point output Toggle.
AnnaBridge 171:3a7713b1edbc 6495 * | | |PWM can control output level when PWM counter count to (PERIODn+1).
AnnaBridge 171:3a7713b1edbc 6496 * | | |Note: This bit is center point control when PWM counter operating in up-down counter type.
AnnaBridge 171:3a7713b1edbc 6497 * @var PWM_T::WGCTL1
AnnaBridge 171:3a7713b1edbc 6498 * Offset: 0xB4 PWM Generation Register 1
AnnaBridge 171:3a7713b1edbc 6499 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6500 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6501 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6502 * |[11:0] |CMPUCTLn |PWM Compare Up Point Control
AnnaBridge 171:3a7713b1edbc 6503 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6504 * | | |00 = Do nothing.
AnnaBridge 171:3a7713b1edbc 6505 * | | |01 = PWM compare up point output Low.
AnnaBridge 171:3a7713b1edbc 6506 * | | |10 = PWM compare up point output High.
AnnaBridge 171:3a7713b1edbc 6507 * | | |11 = PWM compare up point output Toggle.
AnnaBridge 171:3a7713b1edbc 6508 * | | |PWM can control output level when PWM counter up count to CMPDAT.
AnnaBridge 171:3a7713b1edbc 6509 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6510 * |[27:16] |CMPDCTLn |PWM Compare Down Point Control
AnnaBridge 171:3a7713b1edbc 6511 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6512 * | | |00 = Do nothing.
AnnaBridge 171:3a7713b1edbc 6513 * | | |01 = PWM compare down point output Low.
AnnaBridge 171:3a7713b1edbc 6514 * | | |10 = PWM compare down point output High.
AnnaBridge 171:3a7713b1edbc 6515 * | | |11 = PWM compare down point output Toggle.
AnnaBridge 171:3a7713b1edbc 6516 * | | |PWM can control output level when PWM counter down count to CMPDAT.
AnnaBridge 171:3a7713b1edbc 6517 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6518 * @var PWM_T::MSKEN
AnnaBridge 171:3a7713b1edbc 6519 * Offset: 0xB8 PWM Mask Enable Register
AnnaBridge 171:3a7713b1edbc 6520 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6521 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6522 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6523 * |[5:0] |MSKENn |PWM Mask Enable
AnnaBridge 171:3a7713b1edbc 6524 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6525 * | | |The PWM output signal will be masked when this bit is enabled.
AnnaBridge 171:3a7713b1edbc 6526 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
AnnaBridge 171:3a7713b1edbc 6527 * | | |0 = PWM output signal is non-masked.
AnnaBridge 171:3a7713b1edbc 6528 * | | |1 = PWM output signal is masked and output MSKDATn data.
AnnaBridge 171:3a7713b1edbc 6529 * @var PWM_T::MSK
AnnaBridge 171:3a7713b1edbc 6530 * Offset: 0xBC PWM Mask Data Register
AnnaBridge 171:3a7713b1edbc 6531 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6532 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6533 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6534 * |[5:0] |MSKDATn |PWM Mask Data Bit
AnnaBridge 171:3a7713b1edbc 6535 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
AnnaBridge 171:3a7713b1edbc 6536 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6537 * | | |0 = Output logic low to PWMn.
AnnaBridge 171:3a7713b1edbc 6538 * | | |1 = Output logic high to PWMn.
AnnaBridge 171:3a7713b1edbc 6539 * @var PWM_T::BNF
AnnaBridge 171:3a7713b1edbc 6540 * Offset: 0xC0 PWM Brake Noise Filter Register
AnnaBridge 171:3a7713b1edbc 6541 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6542 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6543 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6544 * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable
AnnaBridge 171:3a7713b1edbc 6545 * | | |0 = Noise filter of PWM Brake 0 Disabled.
AnnaBridge 171:3a7713b1edbc 6546 * | | |1 = Noise filter of PWM Brake 0 Enabled.
AnnaBridge 171:3a7713b1edbc 6547 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
AnnaBridge 171:3a7713b1edbc 6548 * | | |000 = Filter clock = HCLK.
AnnaBridge 171:3a7713b1edbc 6549 * | | |001 = Filter clock = HCLK/2.
AnnaBridge 171:3a7713b1edbc 6550 * | | |010 = Filter clock = HCLK/4.
AnnaBridge 171:3a7713b1edbc 6551 * | | |011 = Filter clock = HCLK/8.
AnnaBridge 171:3a7713b1edbc 6552 * | | |100 = Filter clock = HCLK/16.
AnnaBridge 171:3a7713b1edbc 6553 * | | |101 = Filter clock = HCLK/32.
AnnaBridge 171:3a7713b1edbc 6554 * | | |110 = Filter clock = HCLK/64.
AnnaBridge 171:3a7713b1edbc 6555 * | | |111 = Filter clock = HCLK/128.
AnnaBridge 171:3a7713b1edbc 6556 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
AnnaBridge 171:3a7713b1edbc 6557 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
AnnaBridge 171:3a7713b1edbc 6558 * |[7] |BRK0PINV |Brake 0 Pin Inverse
AnnaBridge 171:3a7713b1edbc 6559 * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6560 * | | |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6561 * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable
AnnaBridge 171:3a7713b1edbc 6562 * | | |0 = Noise filter of PWM Brake 1 Disabled.
AnnaBridge 171:3a7713b1edbc 6563 * | | |1 = Noise filter of PWM Brake 1 Enabled.
AnnaBridge 171:3a7713b1edbc 6564 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
AnnaBridge 171:3a7713b1edbc 6565 * | | |000 = Filter clock = HCLK.
AnnaBridge 171:3a7713b1edbc 6566 * | | |001 = Filter clock = HCLK/2.
AnnaBridge 171:3a7713b1edbc 6567 * | | |010 = Filter clock = HCLK/4.
AnnaBridge 171:3a7713b1edbc 6568 * | | |011 = Filter clock = HCLK/8.
AnnaBridge 171:3a7713b1edbc 6569 * | | |100 = Filter clock = HCLK/16.
AnnaBridge 171:3a7713b1edbc 6570 * | | |101 = Filter clock = HCLK/32.
AnnaBridge 171:3a7713b1edbc 6571 * | | |110 = Filter clock = HCLK/64.
AnnaBridge 171:3a7713b1edbc 6572 * | | |111 = Filter clock = HCLK/128.
AnnaBridge 171:3a7713b1edbc 6573 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
AnnaBridge 171:3a7713b1edbc 6574 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
AnnaBridge 171:3a7713b1edbc 6575 * |[15] |BRK1PINV |Brake 1 Pin Inverse
AnnaBridge 171:3a7713b1edbc 6576 * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6577 * | | |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
AnnaBridge 171:3a7713b1edbc 6578 * |[16] |BK0SRC |Brake 0 Pin Source Select (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6579 * | | |For PWM0 setting:
AnnaBridge 171:3a7713b1edbc 6580 * | | |0 = Brake 0 pin source come from PWM0_BRAKE0.
AnnaBridge 171:3a7713b1edbc 6581 * | | |1 = Brake 0 pin source come from PWM1_BRAKE0.
AnnaBridge 171:3a7713b1edbc 6582 * | | |For PWM1 setting:
AnnaBridge 171:3a7713b1edbc 6583 * | | |0 = Brake 0 pin source come from PWM1_BRAKE0.
AnnaBridge 171:3a7713b1edbc 6584 * | | |1 = Brake 0 pin source come from PWM0_BRAKE0.
AnnaBridge 171:3a7713b1edbc 6585 * |[24] |BK1SRC |Brake 1 Pin Source Select (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6586 * | | |For PWM0 setting:
AnnaBridge 171:3a7713b1edbc 6587 * | | |0 = Brake 1 pin source come from PWM0_BRAKE1.
AnnaBridge 171:3a7713b1edbc 6588 * | | |1 = Brake 1 pin source come from PWM1_BRAKE1.
AnnaBridge 171:3a7713b1edbc 6589 * | | |For PWM1 setting:
AnnaBridge 171:3a7713b1edbc 6590 * | | |0 = Brake 1 pin source come from PWM1_BRAKE1.
AnnaBridge 171:3a7713b1edbc 6591 * | | |1 = Brake 1 pin source come from PWM0_BRAKE1.
AnnaBridge 171:3a7713b1edbc 6592 * @var PWM_T::FAILBRK
AnnaBridge 171:3a7713b1edbc 6593 * Offset: 0xC4 PWM System Fail Brake Control Register
AnnaBridge 171:3a7713b1edbc 6594 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6595 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6596 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6597 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable
AnnaBridge 171:3a7713b1edbc 6598 * | | |0 = Brake Function triggered by CSS detection Disabled.
AnnaBridge 171:3a7713b1edbc 6599 * | | |1 = Brake Function triggered by CSS detection Enabled.
AnnaBridge 171:3a7713b1edbc 6600 * |[1] |BODBRKEN |Brown-Out Detection Trigger PWM Brake Function 0 Enable
AnnaBridge 171:3a7713b1edbc 6601 * | | |0 = Brake Function triggered by BOD Disabled.
AnnaBridge 171:3a7713b1edbc 6602 * | | |1 = Brake Function triggered by BOD Enabled.
AnnaBridge 171:3a7713b1edbc 6603 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
AnnaBridge 171:3a7713b1edbc 6604 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
AnnaBridge 171:3a7713b1edbc 6605 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
AnnaBridge 171:3a7713b1edbc 6606 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable
AnnaBridge 171:3a7713b1edbc 6607 * | | |0 = Brake Function triggered by Core lockup detection Disabled.
AnnaBridge 171:3a7713b1edbc 6608 * | | |1 = Brake Function triggered by Core lockup detection Enabled.
AnnaBridge 171:3a7713b1edbc 6609 * @var PWM_T::BRKCTL0_1
AnnaBridge 171:3a7713b1edbc 6610 * Offset: 0xC8 PWM Brake Edge Detect Control Register 0
AnnaBridge 171:3a7713b1edbc 6611 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6612 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6613 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6614 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6615 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6616 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6617 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6618 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6619 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6620 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6621 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6622 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6623 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6624 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6625 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6626 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6627 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6628 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6629 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6630 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6631 * | | |0 = System Fail condition as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6632 * | | |1 = System Fail condition as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6633 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6634 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6635 * | | |0 = ACMP0_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6636 * | | |1 = ACMP0_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6637 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6638 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6639 * | | |0 = ACMP1_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6640 * | | |1 = ACMP1_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6641 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6642 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6643 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6644 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6645 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6646 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6647 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6648 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6649 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6650 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6651 * | | |0 = System Fail condition as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6652 * | | |1 = System Fail condition as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6653 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6654 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6655 * | | |00 = PWM even channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6656 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6657 * | | |10 = PWM even channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6658 * | | |11 = PWM even channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6659 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6660 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6661 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6662 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6663 * | | |10 = PWM odd channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6664 * | | |11 = PWM odd channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6665 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6666 * @var PWM_T::BRKCTL2_3
AnnaBridge 171:3a7713b1edbc 6667 * Offset: 0xCC PWM Brake Edge Detect Control Register 2
AnnaBridge 171:3a7713b1edbc 6668 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6669 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6670 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6671 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6672 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6673 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6674 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6675 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6676 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6677 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6678 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6679 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6680 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6681 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6682 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6683 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6684 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6685 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6686 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6687 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6688 * | | |0 = System Fail condition as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6689 * | | |1 = System Fail condition as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6690 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6691 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6692 * | | |0 = ACMP0_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6693 * | | |1 = ACMP0_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6694 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6695 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6696 * | | |0 = ACMP1_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6697 * | | |1 = ACMP1_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6698 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6699 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6700 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6701 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6702 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6703 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6704 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6705 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6706 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6707 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6708 * | | |0 = System Fail condition as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6709 * | | |1 = System Fail condition as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6710 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6711 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6712 * | | |00 = PWM even channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6713 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6714 * | | |10 = PWM even channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6715 * | | |11 = PWM even channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6716 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6717 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6718 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6719 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6720 * | | |10 = PWM odd channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6721 * | | |11 = PWM odd channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6722 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6723 * @var PWM_T::BRKCTL4_5
AnnaBridge 171:3a7713b1edbc 6724 * Offset: 0xD0 PWM Brake Edge Detect Control Register 4
AnnaBridge 171:3a7713b1edbc 6725 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6726 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6727 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6728 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6729 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6730 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6731 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6732 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6733 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6734 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6735 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6736 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6737 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6738 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6739 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6740 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6741 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6742 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6743 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6744 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6745 * | | |0 = System Fail condition as edge-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6746 * | | |1 = System Fail condition as edge-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6747 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6748 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6749 * | | |0 = ACMP0_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6750 * | | |1 = ACMP0_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6751 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6752 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6753 * | | |0 = ACMP1_O as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6754 * | | |1 = ACMP1_O as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6755 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6756 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6757 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6758 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6759 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6760 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6761 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6762 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6763 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6764 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
AnnaBridge 171:3a7713b1edbc 6765 * | | |0 = System Fail condition as level-detect brake source Disabled.
AnnaBridge 171:3a7713b1edbc 6766 * | | |1 = System Fail condition as level-detect brake source Enabled.
AnnaBridge 171:3a7713b1edbc 6767 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6768 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6769 * | | |00 = PWM even channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6770 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6771 * | | |10 = PWM even channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6772 * | | |11 = PWM even channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6773 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6774 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
AnnaBridge 171:3a7713b1edbc 6775 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
AnnaBridge 171:3a7713b1edbc 6776 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6777 * | | |10 = PWM odd channel output low level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6778 * | | |11 = PWM odd channel output high level when level-detect brake happened.
AnnaBridge 171:3a7713b1edbc 6779 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6780 * @var PWM_T::POLCTL
AnnaBridge 171:3a7713b1edbc 6781 * Offset: 0xD4 PWM Pin Polar Inverse Register
AnnaBridge 171:3a7713b1edbc 6782 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6783 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6784 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6785 * |[5:0] |PINVn |PWM PIN Polar Inverse Control
AnnaBridge 171:3a7713b1edbc 6786 * | | |The register controls polarity state of PWM output.
AnnaBridge 171:3a7713b1edbc 6787 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6788 * | | |0 = PWM output polar inverse Disabled.
AnnaBridge 171:3a7713b1edbc 6789 * | | |1 = PWM output polar inverse Enabled.
AnnaBridge 171:3a7713b1edbc 6790 * @var PWM_T::POEN
AnnaBridge 171:3a7713b1edbc 6791 * Offset: 0xD8 PWM Output Enable Register
AnnaBridge 171:3a7713b1edbc 6792 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6793 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6794 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6795 * |[5:0] |POENn |PWM Pin Output Enable
AnnaBridge 171:3a7713b1edbc 6796 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6797 * | | |0 = PWM pin at tri-state.
AnnaBridge 171:3a7713b1edbc 6798 * | | |1 = PWM pin in output mode.
AnnaBridge 171:3a7713b1edbc 6799 * @var PWM_T::SWBRK
AnnaBridge 171:3a7713b1edbc 6800 * Offset: 0xDC PWM Software Brake Control Register
AnnaBridge 171:3a7713b1edbc 6801 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6802 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6803 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6804 * |[2:0] |BRKETRGn |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 6805 * | | |Each bit n controls the corresponding PWM pair n.
AnnaBridge 171:3a7713b1edbc 6806 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
AnnaBridge 171:3a7713b1edbc 6807 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6808 * |[10:8] |BRKLTRGn |PWM Level Brake Software Trigger (Write Only) (Write Protect)
AnnaBridge 171:3a7713b1edbc 6809 * | | |Each bit n controls the corresponding PWM pair n.
AnnaBridge 171:3a7713b1edbc 6810 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
AnnaBridge 171:3a7713b1edbc 6811 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6812 * @var PWM_T::INTEN0
AnnaBridge 171:3a7713b1edbc 6813 * Offset: 0xE0 PWM Interrupt Enable Register 0
AnnaBridge 171:3a7713b1edbc 6814 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6815 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6816 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6817 * |[5:0] |ZIENn |PWM Zero Point Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6818 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6819 * | | |0 = Zero point interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6820 * | | |1 = Zero point interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6821 * | | |Note: Odd channels will read always 0 at complementary mode.
AnnaBridge 171:3a7713b1edbc 6822 * |[7] |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6823 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6824 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6825 * |[13:8] |PIENn |PWM Period Point Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6826 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6827 * | | |0 = Period point interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6828 * | | |1 = Period point interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6829 * | | |Note1: When up-down counter type period point means center point.
AnnaBridge 171:3a7713b1edbc 6830 * | | |Note2: Odd channels will read always 0 at complementary mode.
AnnaBridge 171:3a7713b1edbc 6831 * |[15] |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6832 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6833 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6834 * |[21:16] |CMPUIENn |PWM Compare Up Count Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6835 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6836 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6837 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6838 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6839 * |[23] |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6840 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6841 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6842 * |[29:24] |CMPDIENn |PWM Compare Down Count Interrupt Enable
AnnaBridge 171:3a7713b1edbc 6843 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6844 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 6845 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 6846 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6847 * @var PWM_T::INTEN1
AnnaBridge 171:3a7713b1edbc 6848 * Offset: 0xE4 PWM Interrupt Enable Register 1
AnnaBridge 171:3a7713b1edbc 6849 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6850 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6851 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6852 * |[0] |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6853 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
AnnaBridge 171:3a7713b1edbc 6854 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
AnnaBridge 171:3a7713b1edbc 6855 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6856 * |[1] |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6857 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
AnnaBridge 171:3a7713b1edbc 6858 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
AnnaBridge 171:3a7713b1edbc 6859 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6860 * |[2] |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6861 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
AnnaBridge 171:3a7713b1edbc 6862 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
AnnaBridge 171:3a7713b1edbc 6863 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6864 * |[8] |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6865 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
AnnaBridge 171:3a7713b1edbc 6866 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
AnnaBridge 171:3a7713b1edbc 6867 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6868 * |[9] |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6869 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
AnnaBridge 171:3a7713b1edbc 6870 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
AnnaBridge 171:3a7713b1edbc 6871 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6872 * |[10] |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
AnnaBridge 171:3a7713b1edbc 6873 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
AnnaBridge 171:3a7713b1edbc 6874 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
AnnaBridge 171:3a7713b1edbc 6875 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6876 * @var PWM_T::INTSTS0
AnnaBridge 171:3a7713b1edbc 6877 * Offset: 0xE8 PWM Interrupt Flag Register 0
AnnaBridge 171:3a7713b1edbc 6878 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6879 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6880 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6881 * |[5:0] |ZIFn |PWM Zero Point Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6882 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6883 * | | |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 6884 * |[7] |IFAIF0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6885 * | | |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 6886 * |[13:8] |PIFn |PWM Period Point Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6887 * | | |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 6888 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6889 * |[15] |IFAIF2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6890 * | | |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 6891 * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6892 * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 6893 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6894 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 171:3a7713b1edbc 6895 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6896 * |[23] |IFAIF4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6897 * | | |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 6898 * |[29:24] |CMPDIFn |PWM Compare Down Count Interrupt Flag
AnnaBridge 171:3a7713b1edbc 6899 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 6900 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 6901 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 171:3a7713b1edbc 6902 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 6903 * @var PWM_T::INTSTS1
AnnaBridge 171:3a7713b1edbc 6904 * Offset: 0xEC PWM Interrupt Flag Register 1
AnnaBridge 171:3a7713b1edbc 6905 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6906 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 6907 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 6908 * |[0] |BRKEIF0 |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6909 * | | |0 = PWM channel0 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6910 * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6911 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6912 * |[1] |BRKEIF1 |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6913 * | | |0 = PWM channel1 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6914 * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6915 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6916 * |[2] |BRKEIF2 |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6917 * | | |0 = PWM channel2 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6918 * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6919 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6920 * |[3] |BRKEIF3 |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6921 * | | |0 = PWM channel3 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6922 * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6923 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6924 * |[4] |BRKEIF4 |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6925 * | | |0 = PWM channel4 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6926 * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6927 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6928 * |[5] |BRKEIF5 |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6929 * | | |0 = PWM channel5 edge-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6930 * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6931 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6932 * |[8] |BRKLIF0 |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6933 * | | |0 = PWM channel0 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6934 * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6935 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6936 * |[9] |BRKLIF1 |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6937 * | | |0 = PWM channel1 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6938 * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6939 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6940 * |[10] |BRKLIF2 |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6941 * | | |0 = PWM channel2 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6942 * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6943 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6944 * |[11] |BRKLIF3 |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6945 * | | |0 = PWM channel3 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6946 * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6947 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6948 * |[12] |BRKLIF4 |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6949 * | | |0 = PWM channel4 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6950 * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6951 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6952 * |[13] |BRKLIF5 |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
AnnaBridge 171:3a7713b1edbc 6953 * | | |0 = PWM channel5 level-detect brake event do not happened.
AnnaBridge 171:3a7713b1edbc 6954 * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6955 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 6956 * |[16] |BRKESTS0 |PWM Channel0 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6957 * | | |0 = PWM channel0 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6958 * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6959 * |[17] |BRKESTS1 |PWM Channel1 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6960 * | | |0 = PWM channel1 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6961 * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6962 * |[18] |BRKESTS2 |PWM Channel2 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6963 * | | |0 = PWM channel2 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6964 * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6965 * |[19] |BRKESTS3 |PWM Channel3 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6966 * | | |0 = PWM channel3 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6967 * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6968 * |[20] |BRKESTS4 |PWM Channel4 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6969 * | | |0 = PWM channel4 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6970 * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6971 * |[21] |BRKESTS5 |PWM Channel5 Edge-Detect Brake Status
AnnaBridge 171:3a7713b1edbc 6972 * | | |0 = PWM channel5 edge-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6973 * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
AnnaBridge 171:3a7713b1edbc 6974 * |[24] |BRKLSTS0 |PWM Channel0 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 6975 * | | |0 = PWM channel0 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6976 * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
AnnaBridge 171:3a7713b1edbc 6977 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 6978 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 6979 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 6980 * |[25] |BRKLSTS1 |PWM Channel1 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 6981 * | | |0 = PWM channel1 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6982 * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
AnnaBridge 171:3a7713b1edbc 6983 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 6984 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 6985 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 6986 * |[26] |BRKLSTS2 |PWM Channel2 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 6987 * | | |0 = PWM channel2 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6988 * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
AnnaBridge 171:3a7713b1edbc 6989 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 6990 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 6991 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 6992 * |[27] |BRKLSTS3 |PWM Channel3 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 6993 * | | |0 = PWM channel3 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 6994 * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
AnnaBridge 171:3a7713b1edbc 6995 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 6996 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 6997 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 6998 * |[28] |BRKLSTS4 |PWM Channel4 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 6999 * | | |0 = PWM channel4 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 7000 * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
AnnaBridge 171:3a7713b1edbc 7001 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 7002 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 7003 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 7004 * |[29] |BRKLSTS5 |PWM Channel5 Level-Detect Brake Status (Read Only)
AnnaBridge 171:3a7713b1edbc 7005 * | | |0 = PWM channel5 level-detect brake state is released.
AnnaBridge 171:3a7713b1edbc 7006 * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
AnnaBridge 171:3a7713b1edbc 7007 * | | |Note: This bit is read only and auto cleared by hardware.
AnnaBridge 171:3a7713b1edbc 7008 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
AnnaBridge 171:3a7713b1edbc 7009 * | | |The PWM waveform will start output from next full PWM period.
AnnaBridge 171:3a7713b1edbc 7010 * @var PWM_T::IFA
AnnaBridge 171:3a7713b1edbc 7011 * Offset: 0xF0 PWM Interrupt Flag Accumulator Register
AnnaBridge 171:3a7713b1edbc 7012 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7013 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7014 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7015 * |[3:0] |IFCNT0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
AnnaBridge 171:3a7713b1edbc 7016 * | | |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
AnnaBridge 171:3a7713b1edbc 7017 * | | |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
AnnaBridge 171:3a7713b1edbc 7018 * |[6:4] |IFSEL0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
AnnaBridge 171:3a7713b1edbc 7019 * | | |000 = CNT equal to Zero in channel 0.
AnnaBridge 171:3a7713b1edbc 7020 * | | |001 = CNT equal to PERIOD in channel 0.
AnnaBridge 171:3a7713b1edbc 7021 * | | |010 = CNT equal to CMPU in channel 0.
AnnaBridge 171:3a7713b1edbc 7022 * | | |011 = CNT equal to CMPD in channel 0.
AnnaBridge 171:3a7713b1edbc 7023 * | | |100 = CNT equal to Zero in channel 1.
AnnaBridge 171:3a7713b1edbc 7024 * | | |101 = CNT equal to PERIOD in channel 1.
AnnaBridge 171:3a7713b1edbc 7025 * | | |110 = CNT equal to CMPU in channel 1.
AnnaBridge 171:3a7713b1edbc 7026 * | | |111 = CNT equal to CMPD in channel 1.
AnnaBridge 171:3a7713b1edbc 7027 * |[7] |IFAEN0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
AnnaBridge 171:3a7713b1edbc 7028 * | | |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
AnnaBridge 171:3a7713b1edbc 7029 * | | |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
AnnaBridge 171:3a7713b1edbc 7030 * |[11:8] |IFCNT2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
AnnaBridge 171:3a7713b1edbc 7031 * | | |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
AnnaBridge 171:3a7713b1edbc 7032 * | | |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
AnnaBridge 171:3a7713b1edbc 7033 * |[14:12] |IFSEL2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
AnnaBridge 171:3a7713b1edbc 7034 * | | |000 = CNT equal to Zero in channel 2.
AnnaBridge 171:3a7713b1edbc 7035 * | | |001 = CNT equal to PERIOD in channel 2.
AnnaBridge 171:3a7713b1edbc 7036 * | | |010 = CNT equal to CMPU in channel 2.
AnnaBridge 171:3a7713b1edbc 7037 * | | |011 = CNT equal to CMPD in channel 2.
AnnaBridge 171:3a7713b1edbc 7038 * | | |100 = CNT equal to Zero in channel 3.
AnnaBridge 171:3a7713b1edbc 7039 * | | |101 = CNT equal to PERIOD in channel 3.
AnnaBridge 171:3a7713b1edbc 7040 * | | |110 = CNT equal to CMPU in channel 3.
AnnaBridge 171:3a7713b1edbc 7041 * | | |111 = CNT equal to CMPD in channel 3.
AnnaBridge 171:3a7713b1edbc 7042 * |[15] |IFAEN2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
AnnaBridge 171:3a7713b1edbc 7043 * | | |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
AnnaBridge 171:3a7713b1edbc 7044 * | | |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
AnnaBridge 171:3a7713b1edbc 7045 * |[19:16] |IFCNT4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
AnnaBridge 171:3a7713b1edbc 7046 * | | |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
AnnaBridge 171:3a7713b1edbc 7047 * | | |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
AnnaBridge 171:3a7713b1edbc 7048 * |[22:20] |IFSEL4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
AnnaBridge 171:3a7713b1edbc 7049 * | | |000 = CNT equal to Zero in channel 4.
AnnaBridge 171:3a7713b1edbc 7050 * | | |001 = CNT equal to PERIOD in channel 4.
AnnaBridge 171:3a7713b1edbc 7051 * | | |010 = CNT equal to CMPU in channel 4.
AnnaBridge 171:3a7713b1edbc 7052 * | | |011 = CNT equal to CMPD in channel 4.
AnnaBridge 171:3a7713b1edbc 7053 * | | |100 = CNT equal to Zero in channel 5.
AnnaBridge 171:3a7713b1edbc 7054 * | | |101 = CNT equal to PERIOD in channel 5.
AnnaBridge 171:3a7713b1edbc 7055 * | | |110 = CNT equal to CMPU in channel 5.
AnnaBridge 171:3a7713b1edbc 7056 * | | |111 = CNT equal to CMPD in channel 5.
AnnaBridge 171:3a7713b1edbc 7057 * |[23] |IFAEN4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
AnnaBridge 171:3a7713b1edbc 7058 * | | |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
AnnaBridge 171:3a7713b1edbc 7059 * | | |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
AnnaBridge 171:3a7713b1edbc 7060 * @var PWM_T::DACTRGEN
AnnaBridge 171:3a7713b1edbc 7061 * Offset: 0xF4 PWM Trigger DAC Enable Register
AnnaBridge 171:3a7713b1edbc 7062 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7063 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7064 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7065 * |[5:0] |ZTEn |PWM Zero Point Trigger DAC Enable
AnnaBridge 171:3a7713b1edbc 7066 * | | |0 = PWM period point trigger DAC function Disabled.
AnnaBridge 171:3a7713b1edbc 7067 * | | |1 = PWM period point trigger DAC function Enabled.
AnnaBridge 171:3a7713b1edbc 7068 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 7069 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7070 * |[13:8] |PTEn |PWM Period Point Trigger DAC Enable
AnnaBridge 171:3a7713b1edbc 7071 * | | |0 = PWM period point trigger DAC function Disabled.
AnnaBridge 171:3a7713b1edbc 7072 * | | |1 = PWM period point trigger DAC function Enabled.
AnnaBridge 171:3a7713b1edbc 7073 * | | |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 7074 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7075 * |[21:16] |CUTRGEn |PWM Compare Up Count Point Trigger DAC Enable
AnnaBridge 171:3a7713b1edbc 7076 * | | |0 = PWM Compare Up point trigger DAC function Disabled.
AnnaBridge 171:3a7713b1edbc 7077 * | | |1 = PWM Compare Up point trigger DAC function Enabled.
AnnaBridge 171:3a7713b1edbc 7078 * | | |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 7079 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7080 * | | |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
AnnaBridge 171:3a7713b1edbc 7081 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 7082 * |[29:24] |CDTRGEn |PWM Compare Down Count Point Trigger DAC Enable
AnnaBridge 171:3a7713b1edbc 7083 * | | |0 = PWM Compare Down count point trigger DAC function Disabled.
AnnaBridge 171:3a7713b1edbc 7084 * | | |1 = PWM Compare Down count point trigger DAC function Enabled.
AnnaBridge 171:3a7713b1edbc 7085 * | | |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 7086 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7087 * | | |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
AnnaBridge 171:3a7713b1edbc 7088 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
AnnaBridge 171:3a7713b1edbc 7089 * @var PWM_T::EADCTS0
AnnaBridge 171:3a7713b1edbc 7090 * Offset: 0xF8 PWM Trigger EADC Source Select Register 0
AnnaBridge 171:3a7713b1edbc 7091 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7092 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7093 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7094 * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7095 * | | |0000 = PWM_CH0 zero point.
AnnaBridge 171:3a7713b1edbc 7096 * | | |0001 = PWM_CH0 period point.
AnnaBridge 171:3a7713b1edbc 7097 * | | |0010 = PWM_CH0 zero or period point.
AnnaBridge 171:3a7713b1edbc 7098 * | | |0011 = PWM_CH0 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7099 * | | |0100 = PWM_CH0 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7100 * | | |0101 = PWM_CH1 zero point.
AnnaBridge 171:3a7713b1edbc 7101 * | | |0110 = PWM_CH1 period point.
AnnaBridge 171:3a7713b1edbc 7102 * | | |0111 = PWM_CH1 zero or period point.
AnnaBridge 171:3a7713b1edbc 7103 * | | |1000 = PWM_CH1 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7104 * | | |1001 = PWM_CH1 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7105 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7106 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7107 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7108 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7109 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7110 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7111 * |[7] |TRGEN0 |PWM_CH0 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7112 * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7113 * | | |0000 = PWM_CH0 zero point.
AnnaBridge 171:3a7713b1edbc 7114 * | | |0001 = PWM_CH0 period point.
AnnaBridge 171:3a7713b1edbc 7115 * | | |0010 = PWM_CH0 zero or period point.
AnnaBridge 171:3a7713b1edbc 7116 * | | |0011 = PWM_CH0 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7117 * | | |0100 = PWM_CH0 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7118 * | | |0101 = PWM_CH1 zero point.
AnnaBridge 171:3a7713b1edbc 7119 * | | |0110 = PWM_CH1 period point.
AnnaBridge 171:3a7713b1edbc 7120 * | | |0111 = PWM_CH1 zero or period point.
AnnaBridge 171:3a7713b1edbc 7121 * | | |1000 = PWM_CH1 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7122 * | | |1001 = PWM_CH1 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7123 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7124 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7125 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7126 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7127 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7128 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7129 * |[15] |TRGEN1 |PWM_CH1 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7130 * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7131 * | | |0000 = PWM_CH2 zero point.
AnnaBridge 171:3a7713b1edbc 7132 * | | |0001 = PWM_CH2 period point.
AnnaBridge 171:3a7713b1edbc 7133 * | | |0010 = PWM_CH2 zero or period point.
AnnaBridge 171:3a7713b1edbc 7134 * | | |0011 = PWM_CH2 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7135 * | | |0100 = PWM_CH2 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7136 * | | |0101 = PWM_CH3 zero point.
AnnaBridge 171:3a7713b1edbc 7137 * | | |0110 = PWM_CH3 period point.
AnnaBridge 171:3a7713b1edbc 7138 * | | |0111 = PWM_CH3 zero or period point.
AnnaBridge 171:3a7713b1edbc 7139 * | | |1000 = PWM_CH3 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7140 * | | |1001 = PWM_CH3 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7141 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7142 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7143 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7144 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7145 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7146 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7147 * |[23] |TRGEN2 |PWM_CH2 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7148 * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7149 * | | |0000 = PWM_CH2 zero point.
AnnaBridge 171:3a7713b1edbc 7150 * | | |0001 = PWM_CH2 period point.
AnnaBridge 171:3a7713b1edbc 7151 * | | |0010 = PWM_CH2 zero or period point.
AnnaBridge 171:3a7713b1edbc 7152 * | | |0011 = PWM_CH2 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7153 * | | |0100 = PWM_CH2 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7154 * | | |0101 = PWM_CH3 zero point.
AnnaBridge 171:3a7713b1edbc 7155 * | | |0110 = PWM_CH3 period point.
AnnaBridge 171:3a7713b1edbc 7156 * | | |0111 = PWM_CH3 zero or period point.
AnnaBridge 171:3a7713b1edbc 7157 * | | |1000 = PWM_CH3 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7158 * | | |1001 = PWM_CH3 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7159 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7160 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7161 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7162 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7163 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7164 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7165 * |[31] |TRGEN3 |PWM_CH3 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7166 * @var PWM_T::EADCTS1
AnnaBridge 171:3a7713b1edbc 7167 * Offset: 0xFC PWM Trigger EADC Source Select Register 1
AnnaBridge 171:3a7713b1edbc 7168 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7169 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7170 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7171 * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7172 * | | |0000 = PWM_CH4 zero point.
AnnaBridge 171:3a7713b1edbc 7173 * | | |0001 = PWM_CH4 period point.
AnnaBridge 171:3a7713b1edbc 7174 * | | |0010 = PWM_CH4 zero or period point.
AnnaBridge 171:3a7713b1edbc 7175 * | | |0011 = PWM_CH4 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7176 * | | |0100 = PWM_CH4 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7177 * | | |0101 = PWM_CH5 zero point.
AnnaBridge 171:3a7713b1edbc 7178 * | | |0110 = PWM_CH5 period point.
AnnaBridge 171:3a7713b1edbc 7179 * | | |0111 = PWM_CH5 zero or period point.
AnnaBridge 171:3a7713b1edbc 7180 * | | |1000 = PWM_CH5 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7181 * | | |1001 = PWM_CH5 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7182 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7183 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7184 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7185 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7186 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7187 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7188 * |[7] |TRGEN4 |PWM_CH4 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7189 * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select
AnnaBridge 171:3a7713b1edbc 7190 * | | |0000 = PWM_CH4 zero point.
AnnaBridge 171:3a7713b1edbc 7191 * | | |0001 = PWM_CH4 period point.
AnnaBridge 171:3a7713b1edbc 7192 * | | |0010 = PWM_CH4 zero or period point.
AnnaBridge 171:3a7713b1edbc 7193 * | | |0011 = PWM_CH4 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7194 * | | |0100 = PWM_CH4 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7195 * | | |0101 = PWM_CH5 zero point.
AnnaBridge 171:3a7713b1edbc 7196 * | | |0110 = PWM_CH5 period point.
AnnaBridge 171:3a7713b1edbc 7197 * | | |0111 = PWM_CH5 zero or period point.
AnnaBridge 171:3a7713b1edbc 7198 * | | |1000 = PWM_CH5 up-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7199 * | | |1001 = PWM_CH5 down-count CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7200 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7201 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7202 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7203 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7204 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7205 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
AnnaBridge 171:3a7713b1edbc 7206 * |[15] |TRGEN5 |PWM_CH5 Trigger EADC enable bit
AnnaBridge 171:3a7713b1edbc 7207 * @var PWM_T::FTCMPDAT0_1
AnnaBridge 171:3a7713b1edbc 7208 * Offset: 0x100 PWM Free Trigger Compare Register 0
AnnaBridge 171:3a7713b1edbc 7209 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7210 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7211 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7212 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
AnnaBridge 171:3a7713b1edbc 7213 * | | |FTCMP use to compare with even CNTR to trigger EADC.
AnnaBridge 171:3a7713b1edbc 7214 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
AnnaBridge 171:3a7713b1edbc 7215 * @var PWM_T::FTCMPDAT2_3
AnnaBridge 171:3a7713b1edbc 7216 * Offset: 0x104 PWM Free Trigger Compare Register 2
AnnaBridge 171:3a7713b1edbc 7217 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7218 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7219 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7220 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
AnnaBridge 171:3a7713b1edbc 7221 * | | |FTCMP use to compare with even CNTR to trigger EADC.
AnnaBridge 171:3a7713b1edbc 7222 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
AnnaBridge 171:3a7713b1edbc 7223 * @var PWM_T::FTCMPDAT4_5
AnnaBridge 171:3a7713b1edbc 7224 * Offset: 0x108 PWM Free Trigger Compare Register 4
AnnaBridge 171:3a7713b1edbc 7225 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7226 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7227 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7228 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
AnnaBridge 171:3a7713b1edbc 7229 * | | |FTCMP use to compare with even CNTR to trigger EADC.
AnnaBridge 171:3a7713b1edbc 7230 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
AnnaBridge 171:3a7713b1edbc 7231 * @var PWM_T::SSCTL
AnnaBridge 171:3a7713b1edbc 7232 * Offset: 0x110 PWM Synchronous Start Control Register
AnnaBridge 171:3a7713b1edbc 7233 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7234 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7235 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7236 * |[5:0] |SSENn |PWM Synchronous Start Function Enable
AnnaBridge 171:3a7713b1edbc 7237 * | | |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
AnnaBridge 171:3a7713b1edbc 7238 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7239 * | | |0 = PWM synchronous start function Disabled.
AnnaBridge 171:3a7713b1edbc 7240 * | | |1 = PWM synchronous start function Enabled.
AnnaBridge 171:3a7713b1edbc 7241 * @var PWM_T::SSTRG
AnnaBridge 171:3a7713b1edbc 7242 * Offset: 0x114 PWM Synchronous Start Trigger Register
AnnaBridge 171:3a7713b1edbc 7243 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7244 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7245 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7246 * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only)
AnnaBridge 171:3a7713b1edbc 7247 * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
AnnaBridge 171:3a7713b1edbc 7248 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
AnnaBridge 171:3a7713b1edbc 7249 * | | |Note: This bit only present in PWM0_BA.
AnnaBridge 171:3a7713b1edbc 7250 * @var PWM_T::STATUS
AnnaBridge 171:3a7713b1edbc 7251 * Offset: 0x120 PWM Status Register
AnnaBridge 171:3a7713b1edbc 7252 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7253 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7254 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7255 * |[5:0] |CNTMAXFn |Time-Base Counter Equal To 0xFFFF Latched Flag
AnnaBridge 171:3a7713b1edbc 7256 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7257 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
AnnaBridge 171:3a7713b1edbc 7258 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 7259 * |[10:8] |SYNCINFn |Input Synchronization Latched Flag
AnnaBridge 171:3a7713b1edbc 7260 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7261 * | | |0 = Indicates no SYNC_IN event has occurred.
AnnaBridge 171:3a7713b1edbc 7262 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 7263 * |[21:16] |ADCTRGFn |EADC Start Of Conversion Flag
AnnaBridge 171:3a7713b1edbc 7264 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7265 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 171:3a7713b1edbc 7266 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 7267 * |[24] |DACTRGF |DAC Start Of Conversion Flag
AnnaBridge 171:3a7713b1edbc 7268 * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
AnnaBridge 171:3a7713b1edbc 7269 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
AnnaBridge 171:3a7713b1edbc 7270 * @var PWM_T::CAPINEN
AnnaBridge 171:3a7713b1edbc 7271 * Offset: 0x200 PWM Capture Input Enable Register
AnnaBridge 171:3a7713b1edbc 7272 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7273 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7274 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7275 * |[5:0] |CAPINENn |Capture Input Enable
AnnaBridge 171:3a7713b1edbc 7276 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7277 * | | |0 = PWM Channel capture input path Disabled.
AnnaBridge 171:3a7713b1edbc 7278 * | | |The input of PWM channel capture function is always regarded as 0.
AnnaBridge 171:3a7713b1edbc 7279 * | | |1 = PWM Channel capture input path Enabled.
AnnaBridge 171:3a7713b1edbc 7280 * | | |The input of PWM channel capture function comes from correlative multifunction pin.
AnnaBridge 171:3a7713b1edbc 7281 * @var PWM_T::CAPCTL
AnnaBridge 171:3a7713b1edbc 7282 * Offset: 0x204 PWM Capture Control Register
AnnaBridge 171:3a7713b1edbc 7283 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7284 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7285 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7286 * |[5:0] |CAPENn |Capture Function Enable
AnnaBridge 171:3a7713b1edbc 7287 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7288 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 171:3a7713b1edbc 7289 * | | |1 = Capture function Enabled.
AnnaBridge 171:3a7713b1edbc 7290 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 171:3a7713b1edbc 7291 * |[13:8] |CAPINVn |Capture Inverter Enable
AnnaBridge 171:3a7713b1edbc 7292 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7293 * | | |0 = Capture source inverter Disabled.
AnnaBridge 171:3a7713b1edbc 7294 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 171:3a7713b1edbc 7295 * |[21:16] |RCRLDENn |Rising Capture Reload Enable
AnnaBridge 171:3a7713b1edbc 7296 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7297 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 171:3a7713b1edbc 7298 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 171:3a7713b1edbc 7299 * |[29:24] |FCRLDENn |Falling Capture Reload Enable
AnnaBridge 171:3a7713b1edbc 7300 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7301 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 171:3a7713b1edbc 7302 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 171:3a7713b1edbc 7303 * @var PWM_T::CAPSTS
AnnaBridge 171:3a7713b1edbc 7304 * Offset: 0x208 PWM Capture Status Register
AnnaBridge 171:3a7713b1edbc 7305 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7306 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7307 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7308 * |[5:0] |CRLIFOVn |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
AnnaBridge 171:3a7713b1edbc 7309 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
AnnaBridge 171:3a7713b1edbc 7310 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7311 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
AnnaBridge 171:3a7713b1edbc 7312 * |[13:8] |CFLIFOVn |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
AnnaBridge 171:3a7713b1edbc 7313 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
AnnaBridge 171:3a7713b1edbc 7314 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7315 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
AnnaBridge 171:3a7713b1edbc 7316 * @var PWM_T::RCAPDAT0
AnnaBridge 171:3a7713b1edbc 7317 * Offset: 0x20C PWM Rising Capture Data Register 0
AnnaBridge 171:3a7713b1edbc 7318 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7319 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7320 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7321 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7322 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7323 * @var PWM_T::FCAPDAT0
AnnaBridge 171:3a7713b1edbc 7324 * Offset: 0x210 PWM Falling Capture Data Register 0
AnnaBridge 171:3a7713b1edbc 7325 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7326 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7327 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7328 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7329 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7330 * @var PWM_T::RCAPDAT1
AnnaBridge 171:3a7713b1edbc 7331 * Offset: 0x214 PWM Rising Capture Data Register 1
AnnaBridge 171:3a7713b1edbc 7332 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7333 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7334 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7335 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7336 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7337 * @var PWM_T::FCAPDAT1
AnnaBridge 171:3a7713b1edbc 7338 * Offset: 0x218 PWM Falling Capture Data Register 1
AnnaBridge 171:3a7713b1edbc 7339 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7340 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7341 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7342 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7343 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7344 * @var PWM_T::RCAPDAT2
AnnaBridge 171:3a7713b1edbc 7345 * Offset: 0x21C PWM Rising Capture Data Register 2
AnnaBridge 171:3a7713b1edbc 7346 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7347 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7348 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7349 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7350 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7351 * @var PWM_T::FCAPDAT2
AnnaBridge 171:3a7713b1edbc 7352 * Offset: 0x220 PWM Falling Capture Data Register 2
AnnaBridge 171:3a7713b1edbc 7353 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7354 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7355 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7356 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7357 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7358 * @var PWM_T::RCAPDAT3
AnnaBridge 171:3a7713b1edbc 7359 * Offset: 0x224 PWM Rising Capture Data Register 3
AnnaBridge 171:3a7713b1edbc 7360 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7361 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7362 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7363 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7364 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7365 * @var PWM_T::FCAPDAT3
AnnaBridge 171:3a7713b1edbc 7366 * Offset: 0x228 PWM Falling Capture Data Register 3
AnnaBridge 171:3a7713b1edbc 7367 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7368 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7369 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7370 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7371 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7372 * @var PWM_T::RCAPDAT4
AnnaBridge 171:3a7713b1edbc 7373 * Offset: 0x22C PWM Rising Capture Data Register 4
AnnaBridge 171:3a7713b1edbc 7374 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7375 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7376 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7377 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7378 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7379 * @var PWM_T::FCAPDAT4
AnnaBridge 171:3a7713b1edbc 7380 * Offset: 0x230 PWM Falling Capture Data Register 4
AnnaBridge 171:3a7713b1edbc 7381 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7382 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7383 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7384 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7385 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7386 * @var PWM_T::RCAPDAT5
AnnaBridge 171:3a7713b1edbc 7387 * Offset: 0x234 PWM Rising Capture Data Register 5
AnnaBridge 171:3a7713b1edbc 7388 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7389 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7390 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7391 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7392 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7393 * @var PWM_T::FCAPDAT5
AnnaBridge 171:3a7713b1edbc 7394 * Offset: 0x238 PWM Falling Capture Data Register 5
AnnaBridge 171:3a7713b1edbc 7395 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7396 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7397 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7398 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
AnnaBridge 171:3a7713b1edbc 7399 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
AnnaBridge 171:3a7713b1edbc 7400 * @var PWM_T::PDMACTL
AnnaBridge 171:3a7713b1edbc 7401 * Offset: 0x23C PWM PDMA Control Register
AnnaBridge 171:3a7713b1edbc 7402 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7403 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7404 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7405 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
AnnaBridge 171:3a7713b1edbc 7406 * | | |0 = Channel 0/1 PDMA function Disabled.
AnnaBridge 171:3a7713b1edbc 7407 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
AnnaBridge 171:3a7713b1edbc 7408 * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7409 * | | |00 = Reserved.
AnnaBridge 171:3a7713b1edbc 7410 * | | |01 = PWM_RCAPDAT0/1.
AnnaBridge 171:3a7713b1edbc 7411 * | | |10 = PWM_FCAPDAT0/1.
AnnaBridge 171:3a7713b1edbc 7412 * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
AnnaBridge 171:3a7713b1edbc 7413 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
AnnaBridge 171:3a7713b1edbc 7414 * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
AnnaBridge 171:3a7713b1edbc 7415 * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7416 * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7417 * |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7418 * | | |0 = Channel0.
AnnaBridge 171:3a7713b1edbc 7419 * | | |1 = Channel1.
AnnaBridge 171:3a7713b1edbc 7420 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
AnnaBridge 171:3a7713b1edbc 7421 * | | |0 = Channel 2/3 PDMA function Disabled.
AnnaBridge 171:3a7713b1edbc 7422 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
AnnaBridge 171:3a7713b1edbc 7423 * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7424 * | | |00 = Reserved.
AnnaBridge 171:3a7713b1edbc 7425 * | | |01 = PWM_RCAPDAT2/3.
AnnaBridge 171:3a7713b1edbc 7426 * | | |10 = PWM_FCAPDAT2/3.
AnnaBridge 171:3a7713b1edbc 7427 * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
AnnaBridge 171:3a7713b1edbc 7428 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
AnnaBridge 171:3a7713b1edbc 7429 * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
AnnaBridge 171:3a7713b1edbc 7430 * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7431 * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7432 * |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7433 * | | |0 = Channel2.
AnnaBridge 171:3a7713b1edbc 7434 * | | |1 = Channel3.
AnnaBridge 171:3a7713b1edbc 7435 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
AnnaBridge 171:3a7713b1edbc 7436 * | | |0 = Channel 4/5 PDMA function Disabled.
AnnaBridge 171:3a7713b1edbc 7437 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
AnnaBridge 171:3a7713b1edbc 7438 * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7439 * | | |00 = Reserved.
AnnaBridge 171:3a7713b1edbc 7440 * | | |01 = PWM_RCAPDAT4/5.
AnnaBridge 171:3a7713b1edbc 7441 * | | |10 = PWM_FCAPDAT4/5.
AnnaBridge 171:3a7713b1edbc 7442 * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
AnnaBridge 171:3a7713b1edbc 7443 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
AnnaBridge 171:3a7713b1edbc 7444 * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
AnnaBridge 171:3a7713b1edbc 7445 * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7446 * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
AnnaBridge 171:3a7713b1edbc 7447 * |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer
AnnaBridge 171:3a7713b1edbc 7448 * | | |0 = Channel4.
AnnaBridge 171:3a7713b1edbc 7449 * | | |1 = Channel5.
AnnaBridge 171:3a7713b1edbc 7450 * @var PWM_T::PDMACAP0_1
AnnaBridge 171:3a7713b1edbc 7451 * Offset: 0x240 PWM Capture Channel 01 PDMA Register
AnnaBridge 171:3a7713b1edbc 7452 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7453 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7454 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7455 * |[15:0] |CAPBUF |PWM Capture PDMA Register
AnnaBridge 171:3a7713b1edbc 7456 * | | |(Read Only)
AnnaBridge 171:3a7713b1edbc 7457 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
AnnaBridge 171:3a7713b1edbc 7458 * @var PWM_T::PDMACAP2_3
AnnaBridge 171:3a7713b1edbc 7459 * Offset: 0x244 PWM Capture Channel 23 PDMA Register
AnnaBridge 171:3a7713b1edbc 7460 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7461 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7462 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7463 * |[15:0] |CAPBUF |PWM Capture PDMA Register
AnnaBridge 171:3a7713b1edbc 7464 * | | |(Read Only)
AnnaBridge 171:3a7713b1edbc 7465 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
AnnaBridge 171:3a7713b1edbc 7466 * @var PWM_T::PDMACAP4_5
AnnaBridge 171:3a7713b1edbc 7467 * Offset: 0x248 PWM Capture Channel 45 PDMA Register
AnnaBridge 171:3a7713b1edbc 7468 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7469 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7470 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7471 * |[15:0] |CAPBUF |PWM Capture PDMA Register
AnnaBridge 171:3a7713b1edbc 7472 * | | |(Read Only)
AnnaBridge 171:3a7713b1edbc 7473 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
AnnaBridge 171:3a7713b1edbc 7474 * @var PWM_T::CAPIEN
AnnaBridge 171:3a7713b1edbc 7475 * Offset: 0x250 PWM Capture Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 7476 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7477 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7478 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7479 * |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable
AnnaBridge 171:3a7713b1edbc 7480 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7481 * | | |0 = Capture rising edge latch interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 7482 * | | |1 = Capture rising edge latch interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 7483 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
AnnaBridge 171:3a7713b1edbc 7484 * |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable
AnnaBridge 171:3a7713b1edbc 7485 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7486 * | | |0 = Capture falling edge latch interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 7487 * | | |1 = Capture falling edge latch interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 7488 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
AnnaBridge 171:3a7713b1edbc 7489 * @var PWM_T::CAPIF
AnnaBridge 171:3a7713b1edbc 7490 * Offset: 0x254 PWM Capture Interrupt Flag Register
AnnaBridge 171:3a7713b1edbc 7491 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7492 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7493 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7494 * |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag
AnnaBridge 171:3a7713b1edbc 7495 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7496 * | | |0 = No capture rising latch condition happened.
AnnaBridge 171:3a7713b1edbc 7497 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 171:3a7713b1edbc 7498 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
AnnaBridge 171:3a7713b1edbc 7499 * |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag
AnnaBridge 171:3a7713b1edbc 7500 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7501 * | | |0 = No capture falling latch condition happened.
AnnaBridge 171:3a7713b1edbc 7502 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 171:3a7713b1edbc 7503 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
AnnaBridge 171:3a7713b1edbc 7504 * @var PWM_T::PBUF
AnnaBridge 171:3a7713b1edbc 7505 * Offset: 0x304~0x318 PWM PERIOD0~5 Buffer
AnnaBridge 171:3a7713b1edbc 7506 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7507 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7508 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7509 * |[15:0] |PBUF |PWM Period Register Buffer
AnnaBridge 171:3a7713b1edbc 7510 * | | |(Read Only)
AnnaBridge 171:3a7713b1edbc 7511 * | | |Used as PERIOD active register.
AnnaBridge 171:3a7713b1edbc 7512 * @var PWM_T::CMPBUF
AnnaBridge 171:3a7713b1edbc 7513 * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer
AnnaBridge 171:3a7713b1edbc 7514 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7515 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7516 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7517 * |[15:0] |CMPBUF |PWM Comparator Register Buffer
AnnaBridge 171:3a7713b1edbc 7518 * | | |(Read Only)
AnnaBridge 171:3a7713b1edbc 7519 * | | |Used as CMP active register.
AnnaBridge 171:3a7713b1edbc 7520 * @var PWM_T::FTCBUF0_1
AnnaBridge 171:3a7713b1edbc 7521 * Offset: 0x340 PWM FTCMPDAT0_1 Buffer
AnnaBridge 171:3a7713b1edbc 7522 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7523 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7524 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7525 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
AnnaBridge 171:3a7713b1edbc 7526 * | | |Used as FTCMPDAT active register.
AnnaBridge 171:3a7713b1edbc 7527 * @var PWM_T::FTCBUF2_3
AnnaBridge 171:3a7713b1edbc 7528 * Offset: 0x344 PWM FTCMPDAT2_3 Buffer
AnnaBridge 171:3a7713b1edbc 7529 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7530 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7531 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7532 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
AnnaBridge 171:3a7713b1edbc 7533 * | | |Used as FTCMPDAT active register.
AnnaBridge 171:3a7713b1edbc 7534 * @var PWM_T::FTCBUF4_5
AnnaBridge 171:3a7713b1edbc 7535 * Offset: 0x348 PWM FTCMPDAT4_5 Buffer
AnnaBridge 171:3a7713b1edbc 7536 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7537 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7538 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7539 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
AnnaBridge 171:3a7713b1edbc 7540 * | | |Used as FTCMPDAT active register.
AnnaBridge 171:3a7713b1edbc 7541 * @var PWM_T::FTCI
AnnaBridge 171:3a7713b1edbc 7542 * Offset: 0x34C PWM FTCMPDAT Indicator Register
AnnaBridge 171:3a7713b1edbc 7543 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7544 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 7545 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 7546 * |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator
AnnaBridge 171:3a7713b1edbc 7547 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 7548 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7549 * |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator
AnnaBridge 171:3a7713b1edbc 7550 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 7551 * | | |Each bit n controls the corresponding PWM channel n.
AnnaBridge 171:3a7713b1edbc 7552 */
AnnaBridge 171:3a7713b1edbc 7553
AnnaBridge 171:3a7713b1edbc 7554 __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
AnnaBridge 171:3a7713b1edbc 7555 __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
AnnaBridge 171:3a7713b1edbc 7556 __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
AnnaBridge 171:3a7713b1edbc 7557 __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
AnnaBridge 171:3a7713b1edbc 7558 __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
AnnaBridge 171:3a7713b1edbc 7559 __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
AnnaBridge 171:3a7713b1edbc 7560 __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
AnnaBridge 171:3a7713b1edbc 7561 __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
AnnaBridge 171:3a7713b1edbc 7562 __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
AnnaBridge 171:3a7713b1edbc 7563 __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
AnnaBridge 171:3a7713b1edbc 7564 __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
AnnaBridge 171:3a7713b1edbc 7565 __I uint32_t RESERVE0[1];
AnnaBridge 171:3a7713b1edbc 7566 __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
AnnaBridge 171:3a7713b1edbc 7567 __I uint32_t RESERVE1[2];
AnnaBridge 171:3a7713b1edbc 7568 __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
AnnaBridge 171:3a7713b1edbc 7569 __I uint32_t RESERVE2[2];
AnnaBridge 171:3a7713b1edbc 7570 __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
AnnaBridge 171:3a7713b1edbc 7571 __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
AnnaBridge 171:3a7713b1edbc 7572 __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
AnnaBridge 171:3a7713b1edbc 7573 __I uint32_t RESERVE3[1];
AnnaBridge 171:3a7713b1edbc 7574 __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
AnnaBridge 171:3a7713b1edbc 7575 __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
AnnaBridge 171:3a7713b1edbc 7576 __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
AnnaBridge 171:3a7713b1edbc 7577 __I uint32_t RESERVE4[1];
AnnaBridge 171:3a7713b1edbc 7578 __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
AnnaBridge 171:3a7713b1edbc 7579 __I uint32_t RESERVE5[2];
AnnaBridge 171:3a7713b1edbc 7580 __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
AnnaBridge 171:3a7713b1edbc 7581 __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
AnnaBridge 171:3a7713b1edbc 7582 __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
AnnaBridge 171:3a7713b1edbc 7583 __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
AnnaBridge 171:3a7713b1edbc 7584 __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
AnnaBridge 171:3a7713b1edbc 7585 __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
AnnaBridge 171:3a7713b1edbc 7586 __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
AnnaBridge 171:3a7713b1edbc 7587 __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
AnnaBridge 171:3a7713b1edbc 7588 __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
AnnaBridge 171:3a7713b1edbc 7589 __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
AnnaBridge 171:3a7713b1edbc 7590 __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
AnnaBridge 171:3a7713b1edbc 7591 __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
AnnaBridge 171:3a7713b1edbc 7592 __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
AnnaBridge 171:3a7713b1edbc 7593 __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
AnnaBridge 171:3a7713b1edbc 7594 __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
AnnaBridge 171:3a7713b1edbc 7595 __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
AnnaBridge 171:3a7713b1edbc 7596 __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
AnnaBridge 171:3a7713b1edbc 7597 __IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */
AnnaBridge 171:3a7713b1edbc 7598 __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
AnnaBridge 171:3a7713b1edbc 7599 __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
AnnaBridge 171:3a7713b1edbc 7600 __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
AnnaBridge 171:3a7713b1edbc 7601 __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
AnnaBridge 171:3a7713b1edbc 7602 __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
AnnaBridge 171:3a7713b1edbc 7603 __I uint32_t RESERVE6[1];
AnnaBridge 171:3a7713b1edbc 7604 __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
AnnaBridge 171:3a7713b1edbc 7605 __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
AnnaBridge 171:3a7713b1edbc 7606 __I uint32_t RESERVE7[2];
AnnaBridge 171:3a7713b1edbc 7607 __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
AnnaBridge 171:3a7713b1edbc 7608 __I uint32_t RESERVE8[55];
AnnaBridge 171:3a7713b1edbc 7609 __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
AnnaBridge 171:3a7713b1edbc 7610 __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
AnnaBridge 171:3a7713b1edbc 7611 __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
AnnaBridge 171:3a7713b1edbc 7612 __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
AnnaBridge 171:3a7713b1edbc 7613 __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
AnnaBridge 171:3a7713b1edbc 7614 __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
AnnaBridge 171:3a7713b1edbc 7615 __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
AnnaBridge 171:3a7713b1edbc 7616 __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
AnnaBridge 171:3a7713b1edbc 7617 __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
AnnaBridge 171:3a7713b1edbc 7618 __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
AnnaBridge 171:3a7713b1edbc 7619 __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
AnnaBridge 171:3a7713b1edbc 7620 __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
AnnaBridge 171:3a7713b1edbc 7621 __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
AnnaBridge 171:3a7713b1edbc 7622 __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
AnnaBridge 171:3a7713b1edbc 7623 __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
AnnaBridge 171:3a7713b1edbc 7624 __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
AnnaBridge 171:3a7713b1edbc 7625 __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
AnnaBridge 171:3a7713b1edbc 7626 __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
AnnaBridge 171:3a7713b1edbc 7627 __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
AnnaBridge 171:3a7713b1edbc 7628 __I uint32_t RESERVE9[1];
AnnaBridge 171:3a7713b1edbc 7629 __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 7630 __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 7631 __I uint32_t RESERVE10[43];
AnnaBridge 171:3a7713b1edbc 7632 __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
AnnaBridge 171:3a7713b1edbc 7633 __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
AnnaBridge 171:3a7713b1edbc 7634 __I uint32_t RESERVE11[3];
AnnaBridge 171:3a7713b1edbc 7635 __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
AnnaBridge 171:3a7713b1edbc 7636 __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
AnnaBridge 171:3a7713b1edbc 7637 __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
AnnaBridge 171:3a7713b1edbc 7638 __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
AnnaBridge 171:3a7713b1edbc 7639
AnnaBridge 171:3a7713b1edbc 7640 } PWM_T;
AnnaBridge 171:3a7713b1edbc 7641
AnnaBridge 171:3a7713b1edbc 7642
AnnaBridge 171:3a7713b1edbc 7643
AnnaBridge 171:3a7713b1edbc 7644 /**
AnnaBridge 171:3a7713b1edbc 7645 @addtogroup PWM_CONST PWM Bit Field Definition
AnnaBridge 171:3a7713b1edbc 7646 Constant Definitions for PWM Controller
AnnaBridge 171:3a7713b1edbc 7647 @{ */
AnnaBridge 171:3a7713b1edbc 7648
AnnaBridge 171:3a7713b1edbc 7649 #define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */
AnnaBridge 171:3a7713b1edbc 7650 #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */
AnnaBridge 171:3a7713b1edbc 7651
AnnaBridge 171:3a7713b1edbc 7652 #define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */
AnnaBridge 171:3a7713b1edbc 7653 #define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */
AnnaBridge 171:3a7713b1edbc 7654
AnnaBridge 171:3a7713b1edbc 7655 #define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */
AnnaBridge 171:3a7713b1edbc 7656 #define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */
AnnaBridge 171:3a7713b1edbc 7657
AnnaBridge 171:3a7713b1edbc 7658 #define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */
AnnaBridge 171:3a7713b1edbc 7659 #define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */
AnnaBridge 171:3a7713b1edbc 7660
AnnaBridge 171:3a7713b1edbc 7661 #define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */
AnnaBridge 171:3a7713b1edbc 7662 #define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */
AnnaBridge 171:3a7713b1edbc 7663
AnnaBridge 171:3a7713b1edbc 7664 #define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */
AnnaBridge 171:3a7713b1edbc 7665 #define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */
AnnaBridge 171:3a7713b1edbc 7666
AnnaBridge 171:3a7713b1edbc 7667 #define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */
AnnaBridge 171:3a7713b1edbc 7668 #define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */
AnnaBridge 171:3a7713b1edbc 7669
AnnaBridge 171:3a7713b1edbc 7670 #define PWM_CTL0_WINLDENn_Pos (8) /*!< PWM_T::CTL0: WINLDENn Position */
AnnaBridge 171:3a7713b1edbc 7671 #define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) /*!< PWM_T::CTL0: WINLDENn Mask */
AnnaBridge 171:3a7713b1edbc 7672
AnnaBridge 171:3a7713b1edbc 7673 #define PWM_CTL0_WINLDEN0_Pos (8) /*!< PWM_T::CTL0: WINLDEN0 Position */
AnnaBridge 171:3a7713b1edbc 7674 #define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) /*!< PWM_T::CTL0: WINLDEN0 Mask */
AnnaBridge 171:3a7713b1edbc 7675
AnnaBridge 171:3a7713b1edbc 7676 #define PWM_CTL0_WINLDEN1_Pos (9) /*!< PWM_T::CTL0: WINLDEN1 Position */
AnnaBridge 171:3a7713b1edbc 7677 #define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) /*!< PWM_T::CTL0: WINLDEN1 Mask */
AnnaBridge 171:3a7713b1edbc 7678
AnnaBridge 171:3a7713b1edbc 7679 #define PWM_CTL0_WINLDEN2_Pos (10) /*!< PWM_T::CTL0: WINLDEN2 Position */
AnnaBridge 171:3a7713b1edbc 7680 #define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) /*!< PWM_T::CTL0: WINLDEN2 Mask */
AnnaBridge 171:3a7713b1edbc 7681
AnnaBridge 171:3a7713b1edbc 7682 #define PWM_CTL0_WINLDEN3_Pos (11) /*!< PWM_T::CTL0: WINLDEN3 Position */
AnnaBridge 171:3a7713b1edbc 7683 #define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) /*!< PWM_T::CTL0: WINLDEN3 Mask */
AnnaBridge 171:3a7713b1edbc 7684
AnnaBridge 171:3a7713b1edbc 7685 #define PWM_CTL0_WINLDEN4_Pos (12) /*!< PWM_T::CTL0: WINLDEN4 Position */
AnnaBridge 171:3a7713b1edbc 7686 #define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) /*!< PWM_T::CTL0: WINLDEN4 Mask */
AnnaBridge 171:3a7713b1edbc 7687
AnnaBridge 171:3a7713b1edbc 7688 #define PWM_CTL0_WINLDEN5_Pos (13) /*!< PWM_T::CTL0: WINLDEN5 Position */
AnnaBridge 171:3a7713b1edbc 7689 #define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) /*!< PWM_T::CTL0: WINLDEN5 Mask */
AnnaBridge 171:3a7713b1edbc 7690
AnnaBridge 171:3a7713b1edbc 7691 #define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */
AnnaBridge 171:3a7713b1edbc 7692 #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */
AnnaBridge 171:3a7713b1edbc 7693
AnnaBridge 171:3a7713b1edbc 7694 #define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */
AnnaBridge 171:3a7713b1edbc 7695 #define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */
AnnaBridge 171:3a7713b1edbc 7696
AnnaBridge 171:3a7713b1edbc 7697 #define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */
AnnaBridge 171:3a7713b1edbc 7698 #define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */
AnnaBridge 171:3a7713b1edbc 7699
AnnaBridge 171:3a7713b1edbc 7700 #define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */
AnnaBridge 171:3a7713b1edbc 7701 #define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */
AnnaBridge 171:3a7713b1edbc 7702
AnnaBridge 171:3a7713b1edbc 7703 #define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */
AnnaBridge 171:3a7713b1edbc 7704 #define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */
AnnaBridge 171:3a7713b1edbc 7705
AnnaBridge 171:3a7713b1edbc 7706 #define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */
AnnaBridge 171:3a7713b1edbc 7707 #define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */
AnnaBridge 171:3a7713b1edbc 7708
AnnaBridge 171:3a7713b1edbc 7709 #define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */
AnnaBridge 171:3a7713b1edbc 7710 #define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */
AnnaBridge 171:3a7713b1edbc 7711
AnnaBridge 171:3a7713b1edbc 7712 #define PWM_CTL0_GROUPEN_Pos (24) /*!< PWM_T::CTL0: GROUPEN Position */
AnnaBridge 171:3a7713b1edbc 7713 #define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) /*!< PWM_T::CTL0: GROUPEN Mask */
AnnaBridge 171:3a7713b1edbc 7714
AnnaBridge 171:3a7713b1edbc 7715 #define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */
AnnaBridge 171:3a7713b1edbc 7716 #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */
AnnaBridge 171:3a7713b1edbc 7717
AnnaBridge 171:3a7713b1edbc 7718 #define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */
AnnaBridge 171:3a7713b1edbc 7719 #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */
AnnaBridge 171:3a7713b1edbc 7720
AnnaBridge 171:3a7713b1edbc 7721 #define PWM_CTL1_CNTTYPEn_Pos (0) /*!< PWM_T::CTL1: CNTTYPEn Position */
AnnaBridge 171:3a7713b1edbc 7722 #define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) /*!< PWM_T::CTL1: CNTTYPEn Mask */
AnnaBridge 171:3a7713b1edbc 7723
AnnaBridge 171:3a7713b1edbc 7724 #define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */
AnnaBridge 171:3a7713b1edbc 7725 #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */
AnnaBridge 171:3a7713b1edbc 7726
AnnaBridge 171:3a7713b1edbc 7727 #define PWM_CTL1_CNTTYPE1_Pos (2) /*!< PWM_T::CTL1: CNTTYPE1 Position */
AnnaBridge 171:3a7713b1edbc 7728 #define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) /*!< PWM_T::CTL1: CNTTYPE1 Mask */
AnnaBridge 171:3a7713b1edbc 7729
AnnaBridge 171:3a7713b1edbc 7730 #define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */
AnnaBridge 171:3a7713b1edbc 7731 #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */
AnnaBridge 171:3a7713b1edbc 7732
AnnaBridge 171:3a7713b1edbc 7733 #define PWM_CTL1_CNTTYPE3_Pos (6) /*!< PWM_T::CTL1: CNTTYPE3 Position */
AnnaBridge 171:3a7713b1edbc 7734 #define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) /*!< PWM_T::CTL1: CNTTYPE3 Mask */
AnnaBridge 171:3a7713b1edbc 7735
AnnaBridge 171:3a7713b1edbc 7736 #define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */
AnnaBridge 171:3a7713b1edbc 7737 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */
AnnaBridge 171:3a7713b1edbc 7738
AnnaBridge 171:3a7713b1edbc 7739 #define PWM_CTL1_CNTTYPE5_Pos (10) /*!< PWM_T::CTL1: CNTTYPE5 Position */
AnnaBridge 171:3a7713b1edbc 7740 #define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) /*!< PWM_T::CTL1: CNTTYPE5 Mask */
AnnaBridge 171:3a7713b1edbc 7741
AnnaBridge 171:3a7713b1edbc 7742 #define PWM_CTL1_CNTMODEn_Pos (16) /*!< PWM_T::CTL1: CNTMODEn Position */
AnnaBridge 171:3a7713b1edbc 7743 #define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) /*!< PWM_T::CTL1: CNTMODEn Mask */
AnnaBridge 171:3a7713b1edbc 7744
AnnaBridge 171:3a7713b1edbc 7745 #define PWM_CTL1_CNTMODE0_Pos (16) /*!< PWM_T::CTL1: CNTMODE0 Position */
AnnaBridge 171:3a7713b1edbc 7746 #define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) /*!< PWM_T::CTL1: CNTMODE0 Mask */
AnnaBridge 171:3a7713b1edbc 7747
AnnaBridge 171:3a7713b1edbc 7748 #define PWM_CTL1_CNTMODE1_Pos (17) /*!< PWM_T::CTL1: CNTMODE1 Position */
AnnaBridge 171:3a7713b1edbc 7749 #define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) /*!< PWM_T::CTL1: CNTMODE1 Mask */
AnnaBridge 171:3a7713b1edbc 7750
AnnaBridge 171:3a7713b1edbc 7751 #define PWM_CTL1_CNTMODE2_Pos (18) /*!< PWM_T::CTL1: CNTMODE2 Position */
AnnaBridge 171:3a7713b1edbc 7752 #define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) /*!< PWM_T::CTL1: CNTMODE2 Mask */
AnnaBridge 171:3a7713b1edbc 7753
AnnaBridge 171:3a7713b1edbc 7754 #define PWM_CTL1_CNTMODE3_Pos (19) /*!< PWM_T::CTL1: CNTMODE3 Position */
AnnaBridge 171:3a7713b1edbc 7755 #define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) /*!< PWM_T::CTL1: CNTMODE3 Mask */
AnnaBridge 171:3a7713b1edbc 7756
AnnaBridge 171:3a7713b1edbc 7757 #define PWM_CTL1_CNTMODE4_Pos (20) /*!< PWM_T::CTL1: CNTMODE4 Position */
AnnaBridge 171:3a7713b1edbc 7758 #define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) /*!< PWM_T::CTL1: CNTMODE4 Mask */
AnnaBridge 171:3a7713b1edbc 7759
AnnaBridge 171:3a7713b1edbc 7760 #define PWM_CTL1_CNTMODE5_Pos (21) /*!< PWM_T::CTL1: CNTMODE5 Position */
AnnaBridge 171:3a7713b1edbc 7761 #define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) /*!< PWM_T::CTL1: CNTMODE5 Mask */
AnnaBridge 171:3a7713b1edbc 7762
AnnaBridge 171:3a7713b1edbc 7763 #define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */
AnnaBridge 171:3a7713b1edbc 7764 #define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */
AnnaBridge 171:3a7713b1edbc 7765
AnnaBridge 171:3a7713b1edbc 7766 #define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */
AnnaBridge 171:3a7713b1edbc 7767 #define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */
AnnaBridge 171:3a7713b1edbc 7768
AnnaBridge 171:3a7713b1edbc 7769 #define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */
AnnaBridge 171:3a7713b1edbc 7770 #define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */
AnnaBridge 171:3a7713b1edbc 7771
AnnaBridge 171:3a7713b1edbc 7772 #define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */
AnnaBridge 171:3a7713b1edbc 7773 #define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */
AnnaBridge 171:3a7713b1edbc 7774
AnnaBridge 171:3a7713b1edbc 7775 #define PWM_SYNC_PHSENn_Pos (0) /*!< PWM_T::SYNC: PHSENn Position */
AnnaBridge 171:3a7713b1edbc 7776 #define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) /*!< PWM_T::SYNC: PHSENn Mask */
AnnaBridge 171:3a7713b1edbc 7777
AnnaBridge 171:3a7713b1edbc 7778 #define PWM_SYNC_PHSEN0_Pos (0) /*!< PWM_T::SYNC: PHSEN0 Position */
AnnaBridge 171:3a7713b1edbc 7779 #define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) /*!< PWM_T::SYNC: PHSEN0 Mask */
AnnaBridge 171:3a7713b1edbc 7780
AnnaBridge 171:3a7713b1edbc 7781 #define PWM_SYNC_PHSEN2_Pos (1) /*!< PWM_T::SYNC: PHSEN2 Position */
AnnaBridge 171:3a7713b1edbc 7782 #define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) /*!< PWM_T::SYNC: PHSEN2 Mask */
AnnaBridge 171:3a7713b1edbc 7783
AnnaBridge 171:3a7713b1edbc 7784 #define PWM_SYNC_PHSEN4_Pos (2) /*!< PWM_T::SYNC: PHSEN4 Position */
AnnaBridge 171:3a7713b1edbc 7785 #define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) /*!< PWM_T::SYNC: PHSEN4 Mask */
AnnaBridge 171:3a7713b1edbc 7786
AnnaBridge 171:3a7713b1edbc 7787 #define PWM_SYNC_SINSRCn_Pos (8) /*!< PWM_T::SYNC: SINSRCn Position */
AnnaBridge 171:3a7713b1edbc 7788 #define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) /*!< PWM_T::SYNC: SINSRCn Mask */
AnnaBridge 171:3a7713b1edbc 7789
AnnaBridge 171:3a7713b1edbc 7790 #define PWM_SYNC_SINSRC0_Pos (8) /*!< PWM_T::SYNC: SINSRC0 Position */
AnnaBridge 171:3a7713b1edbc 7791 #define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) /*!< PWM_T::SYNC: SINSRC0 Mask */
AnnaBridge 171:3a7713b1edbc 7792
AnnaBridge 171:3a7713b1edbc 7793 #define PWM_SYNC_SINSRC2_Pos (10) /*!< PWM_T::SYNC: SINSRC2 Position */
AnnaBridge 171:3a7713b1edbc 7794 #define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) /*!< PWM_T::SYNC: SINSRC2 Mask */
AnnaBridge 171:3a7713b1edbc 7795
AnnaBridge 171:3a7713b1edbc 7796 #define PWM_SYNC_SINSRC4_Pos (12) /*!< PWM_T::SYNC: SINSRC4 Position */
AnnaBridge 171:3a7713b1edbc 7797 #define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) /*!< PWM_T::SYNC: SINSRC4 Mask */
AnnaBridge 171:3a7713b1edbc 7798
AnnaBridge 171:3a7713b1edbc 7799 #define PWM_SYNC_SNFLTEN_Pos (16) /*!< PWM_T::SYNC: SNFLTEN Position */
AnnaBridge 171:3a7713b1edbc 7800 #define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) /*!< PWM_T::SYNC: SNFLTEN Mask */
AnnaBridge 171:3a7713b1edbc 7801
AnnaBridge 171:3a7713b1edbc 7802 #define PWM_SYNC_SFLTCSEL_Pos (17) /*!< PWM_T::SYNC: SFLTCSEL Position */
AnnaBridge 171:3a7713b1edbc 7803 #define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) /*!< PWM_T::SYNC: SFLTCSEL Mask */
AnnaBridge 171:3a7713b1edbc 7804
AnnaBridge 171:3a7713b1edbc 7805 #define PWM_SYNC_SFLTCNT_Pos (20) /*!< PWM_T::SYNC: SFLTCNT Position */
AnnaBridge 171:3a7713b1edbc 7806 #define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) /*!< PWM_T::SYNC: SFLTCNT Mask */
AnnaBridge 171:3a7713b1edbc 7807
AnnaBridge 171:3a7713b1edbc 7808 #define PWM_SYNC_SINPINV_Pos (23) /*!< PWM_T::SYNC: SINPINV Position */
AnnaBridge 171:3a7713b1edbc 7809 #define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) /*!< PWM_T::SYNC: SINPINV Mask */
AnnaBridge 171:3a7713b1edbc 7810
AnnaBridge 171:3a7713b1edbc 7811 #define PWM_SYNC_PHSDIRn_Pos (24) /*!< PWM_T::SYNC: PHSDIRn Position */
AnnaBridge 171:3a7713b1edbc 7812 #define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) /*!< PWM_T::SYNC: PHSDIRn Mask */
AnnaBridge 171:3a7713b1edbc 7813
AnnaBridge 171:3a7713b1edbc 7814 #define PWM_SYNC_PHSDIR0_Pos (24) /*!< PWM_T::SYNC: PHSDIR0 Position */
AnnaBridge 171:3a7713b1edbc 7815 #define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) /*!< PWM_T::SYNC: PHSDIR0 Mask */
AnnaBridge 171:3a7713b1edbc 7816
AnnaBridge 171:3a7713b1edbc 7817 #define PWM_SYNC_PHSDIR2_Pos (25) /*!< PWM_T::SYNC: PHSDIR2 Position */
AnnaBridge 171:3a7713b1edbc 7818 #define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) /*!< PWM_T::SYNC: PHSDIR2 Mask */
AnnaBridge 171:3a7713b1edbc 7819
AnnaBridge 171:3a7713b1edbc 7820 #define PWM_SYNC_PHSDIR4_Pos (26) /*!< PWM_T::SYNC: PHSDIR4 Position */
AnnaBridge 171:3a7713b1edbc 7821 #define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) /*!< PWM_T::SYNC: PHSDIR4 Mask */
AnnaBridge 171:3a7713b1edbc 7822
AnnaBridge 171:3a7713b1edbc 7823 #define PWM_SWSYNC_SWSYNCn_Pos (0) /*!< PWM_T::SWSYNC: SWSYNCn Position */
AnnaBridge 171:3a7713b1edbc 7824 #define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) /*!< PWM_T::SWSYNC: SWSYNCn Mask */
AnnaBridge 171:3a7713b1edbc 7825
AnnaBridge 171:3a7713b1edbc 7826 #define PWM_SWSYNC_SWSYNC0_Pos (0) /*!< PWM_T::SWSYNC: SWSYNC0 Position */
AnnaBridge 171:3a7713b1edbc 7827 #define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) /*!< PWM_T::SWSYNC: SWSYNC0 Mask */
AnnaBridge 171:3a7713b1edbc 7828
AnnaBridge 171:3a7713b1edbc 7829 #define PWM_SWSYNC_SWSYNC2_Pos (1) /*!< PWM_T::SWSYNC: SWSYNC2 Position */
AnnaBridge 171:3a7713b1edbc 7830 #define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) /*!< PWM_T::SWSYNC: SWSYNC2 Mask */
AnnaBridge 171:3a7713b1edbc 7831
AnnaBridge 171:3a7713b1edbc 7832 #define PWM_SWSYNC_SWSYNC4_Pos (2) /*!< PWM_T::SWSYNC: SWSYNC4 Position */
AnnaBridge 171:3a7713b1edbc 7833 #define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) /*!< PWM_T::SWSYNC: SWSYNC4 Mask */
AnnaBridge 171:3a7713b1edbc 7834
AnnaBridge 171:3a7713b1edbc 7835 #define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */
AnnaBridge 171:3a7713b1edbc 7836 #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */
AnnaBridge 171:3a7713b1edbc 7837
AnnaBridge 171:3a7713b1edbc 7838 #define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */
AnnaBridge 171:3a7713b1edbc 7839 #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */
AnnaBridge 171:3a7713b1edbc 7840
AnnaBridge 171:3a7713b1edbc 7841 #define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */
AnnaBridge 171:3a7713b1edbc 7842 #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */
AnnaBridge 171:3a7713b1edbc 7843
AnnaBridge 171:3a7713b1edbc 7844 #define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */
AnnaBridge 171:3a7713b1edbc 7845 #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */
AnnaBridge 171:3a7713b1edbc 7846
AnnaBridge 171:3a7713b1edbc 7847 #define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */
AnnaBridge 171:3a7713b1edbc 7848 #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */
AnnaBridge 171:3a7713b1edbc 7849
AnnaBridge 171:3a7713b1edbc 7850 #define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */
AnnaBridge 171:3a7713b1edbc 7851 #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */
AnnaBridge 171:3a7713b1edbc 7852
AnnaBridge 171:3a7713b1edbc 7853 #define PWM_CNTEN_CNTENn_Pos (0) /*!< PWM_T::CNTEN: CNTENn Position */
AnnaBridge 171:3a7713b1edbc 7854 #define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) /*!< PWM_T::CNTEN: CNTENn Mask */
AnnaBridge 171:3a7713b1edbc 7855
AnnaBridge 171:3a7713b1edbc 7856 #define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */
AnnaBridge 171:3a7713b1edbc 7857 #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */
AnnaBridge 171:3a7713b1edbc 7858
AnnaBridge 171:3a7713b1edbc 7859 #define PWM_CNTEN_CNTEN1_Pos (1) /*!< PWM_T::CNTEN: CNTEN1 Position */
AnnaBridge 171:3a7713b1edbc 7860 #define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) /*!< PWM_T::CNTEN: CNTEN1 Mask */
AnnaBridge 171:3a7713b1edbc 7861
AnnaBridge 171:3a7713b1edbc 7862 #define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */
AnnaBridge 171:3a7713b1edbc 7863 #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */
AnnaBridge 171:3a7713b1edbc 7864
AnnaBridge 171:3a7713b1edbc 7865 #define PWM_CNTEN_CNTEN3_Pos (3) /*!< PWM_T::CNTEN: CNTEN3 Position */
AnnaBridge 171:3a7713b1edbc 7866 #define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) /*!< PWM_T::CNTEN: CNTEN3 Mask */
AnnaBridge 171:3a7713b1edbc 7867
AnnaBridge 171:3a7713b1edbc 7868 #define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */
AnnaBridge 171:3a7713b1edbc 7869 #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */
AnnaBridge 171:3a7713b1edbc 7870
AnnaBridge 171:3a7713b1edbc 7871 #define PWM_CNTEN_CNTEN5_Pos (5) /*!< PWM_T::CNTEN: CNTEN5 Position */
AnnaBridge 171:3a7713b1edbc 7872 #define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) /*!< PWM_T::CNTEN: CNTEN5 Mask */
AnnaBridge 171:3a7713b1edbc 7873
AnnaBridge 171:3a7713b1edbc 7874 #define PWM_CNTCLR_CNTCLRn_Pos (0) /*!< PWM_T::CNTCLR: CNTCLRn Position */
AnnaBridge 171:3a7713b1edbc 7875 #define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) /*!< PWM_T::CNTCLR: CNTCLRn Mask */
AnnaBridge 171:3a7713b1edbc 7876
AnnaBridge 171:3a7713b1edbc 7877 #define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */
AnnaBridge 171:3a7713b1edbc 7878 #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */
AnnaBridge 171:3a7713b1edbc 7879
AnnaBridge 171:3a7713b1edbc 7880 #define PWM_CNTCLR_CNTCLR1_Pos (1) /*!< PWM_T::CNTCLR: CNTCLR1 Position */
AnnaBridge 171:3a7713b1edbc 7881 #define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) /*!< PWM_T::CNTCLR: CNTCLR1 Mask */
AnnaBridge 171:3a7713b1edbc 7882
AnnaBridge 171:3a7713b1edbc 7883 #define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */
AnnaBridge 171:3a7713b1edbc 7884 #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */
AnnaBridge 171:3a7713b1edbc 7885
AnnaBridge 171:3a7713b1edbc 7886 #define PWM_CNTCLR_CNTCLR3_Pos (3) /*!< PWM_T::CNTCLR: CNTCLR3 Position */
AnnaBridge 171:3a7713b1edbc 7887 #define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) /*!< PWM_T::CNTCLR: CNTCLR3 Mask */
AnnaBridge 171:3a7713b1edbc 7888
AnnaBridge 171:3a7713b1edbc 7889 #define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */
AnnaBridge 171:3a7713b1edbc 7890 #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */
AnnaBridge 171:3a7713b1edbc 7891
AnnaBridge 171:3a7713b1edbc 7892 #define PWM_CNTCLR_CNTCLR5_Pos (5) /*!< PWM_T::CNTCLR: CNTCLR5 Position */
AnnaBridge 171:3a7713b1edbc 7893 #define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) /*!< PWM_T::CNTCLR: CNTCLR5 Mask */
AnnaBridge 171:3a7713b1edbc 7894
AnnaBridge 171:3a7713b1edbc 7895 #define PWM_LOAD_LOADn_Pos (0) /*!< PWM_T::LOAD: LOADn Position */
AnnaBridge 171:3a7713b1edbc 7896 #define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) /*!< PWM_T::LOAD: LOADn Mask */
AnnaBridge 171:3a7713b1edbc 7897
AnnaBridge 171:3a7713b1edbc 7898 #define PWM_LOAD_LOAD0_Pos (0) /*!< PWM_T::LOAD: LOAD0 Position */
AnnaBridge 171:3a7713b1edbc 7899 #define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) /*!< PWM_T::LOAD: LOAD0 Mask */
AnnaBridge 171:3a7713b1edbc 7900
AnnaBridge 171:3a7713b1edbc 7901 #define PWM_LOAD_LOAD1_Pos (1) /*!< PWM_T::LOAD: LOAD1 Position */
AnnaBridge 171:3a7713b1edbc 7902 #define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) /*!< PWM_T::LOAD: LOAD1 Mask */
AnnaBridge 171:3a7713b1edbc 7903
AnnaBridge 171:3a7713b1edbc 7904 #define PWM_LOAD_LOAD2_Pos (2) /*!< PWM_T::LOAD: LOAD2 Position */
AnnaBridge 171:3a7713b1edbc 7905 #define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) /*!< PWM_T::LOAD: LOAD2 Mask */
AnnaBridge 171:3a7713b1edbc 7906
AnnaBridge 171:3a7713b1edbc 7907 #define PWM_LOAD_LOAD3_Pos (3) /*!< PWM_T::LOAD: LOAD3 Position */
AnnaBridge 171:3a7713b1edbc 7908 #define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) /*!< PWM_T::LOAD: LOAD3 Mask */
AnnaBridge 171:3a7713b1edbc 7909
AnnaBridge 171:3a7713b1edbc 7910 #define PWM_LOAD_LOAD4_Pos (4) /*!< PWM_T::LOAD: LOAD4 Position */
AnnaBridge 171:3a7713b1edbc 7911 #define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) /*!< PWM_T::LOAD: LOAD4 Mask */
AnnaBridge 171:3a7713b1edbc 7912
AnnaBridge 171:3a7713b1edbc 7913 #define PWM_LOAD_LOAD5_Pos (5) /*!< PWM_T::LOAD: LOAD5 Position */
AnnaBridge 171:3a7713b1edbc 7914 #define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) /*!< PWM_T::LOAD: LOAD5 Mask */
AnnaBridge 171:3a7713b1edbc 7915
AnnaBridge 171:3a7713b1edbc 7916 #define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */
AnnaBridge 171:3a7713b1edbc 7917 #define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */
AnnaBridge 171:3a7713b1edbc 7918
AnnaBridge 171:3a7713b1edbc 7919 #define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */
AnnaBridge 171:3a7713b1edbc 7920 #define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */
AnnaBridge 171:3a7713b1edbc 7921
AnnaBridge 171:3a7713b1edbc 7922 #define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */
AnnaBridge 171:3a7713b1edbc 7923 #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */
AnnaBridge 171:3a7713b1edbc 7924
AnnaBridge 171:3a7713b1edbc 7925 #define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */
AnnaBridge 171:3a7713b1edbc 7926 #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */
AnnaBridge 171:3a7713b1edbc 7927
AnnaBridge 171:3a7713b1edbc 7928 #define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */
AnnaBridge 171:3a7713b1edbc 7929 #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */
AnnaBridge 171:3a7713b1edbc 7930
AnnaBridge 171:3a7713b1edbc 7931 #define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */
AnnaBridge 171:3a7713b1edbc 7932 #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */
AnnaBridge 171:3a7713b1edbc 7933
AnnaBridge 171:3a7713b1edbc 7934 #define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */
AnnaBridge 171:3a7713b1edbc 7935 #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */
AnnaBridge 171:3a7713b1edbc 7936
AnnaBridge 171:3a7713b1edbc 7937 #define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */
AnnaBridge 171:3a7713b1edbc 7938 #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */
AnnaBridge 171:3a7713b1edbc 7939
AnnaBridge 171:3a7713b1edbc 7940 #define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */
AnnaBridge 171:3a7713b1edbc 7941 #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */
AnnaBridge 171:3a7713b1edbc 7942
AnnaBridge 171:3a7713b1edbc 7943 #define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */
AnnaBridge 171:3a7713b1edbc 7944 #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */
AnnaBridge 171:3a7713b1edbc 7945
AnnaBridge 171:3a7713b1edbc 7946 #define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */
AnnaBridge 171:3a7713b1edbc 7947 #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */
AnnaBridge 171:3a7713b1edbc 7948
AnnaBridge 171:3a7713b1edbc 7949 #define PWM_PHS0_1_PHS_Pos (0) /*!< PWM_T::PHS0_1: PHS Position */
AnnaBridge 171:3a7713b1edbc 7950 #define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) /*!< PWM_T::PHS0_1: PHS Mask */
AnnaBridge 171:3a7713b1edbc 7951
AnnaBridge 171:3a7713b1edbc 7952 #define PWM_PHS2_3_PHS_Pos (0) /*!< PWM_T::PHS2_3: PHS Position */
AnnaBridge 171:3a7713b1edbc 7953 #define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) /*!< PWM_T::PHS2_3: PHS Mask */
AnnaBridge 171:3a7713b1edbc 7954
AnnaBridge 171:3a7713b1edbc 7955 #define PWM_PHS4_5_PHS_Pos (0) /*!< PWM_T::PHS4_5: PHS Position */
AnnaBridge 171:3a7713b1edbc 7956 #define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) /*!< PWM_T::PHS4_5: PHS Mask */
AnnaBridge 171:3a7713b1edbc 7957
AnnaBridge 171:3a7713b1edbc 7958 #define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */
AnnaBridge 171:3a7713b1edbc 7959 #define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */
AnnaBridge 171:3a7713b1edbc 7960
AnnaBridge 171:3a7713b1edbc 7961 #define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */
AnnaBridge 171:3a7713b1edbc 7962 #define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */
AnnaBridge 171:3a7713b1edbc 7963
AnnaBridge 171:3a7713b1edbc 7964 #define PWM_WGCTL0_ZPCTLn_Pos (0) /*!< PWM_T::WGCTL0: ZPCTLn Position */
AnnaBridge 171:3a7713b1edbc 7965 #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) /*!< PWM_T::WGCTL0: ZPCTLn Mask */
AnnaBridge 171:3a7713b1edbc 7966
AnnaBridge 171:3a7713b1edbc 7967 #define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */
AnnaBridge 171:3a7713b1edbc 7968 #define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */
AnnaBridge 171:3a7713b1edbc 7969
AnnaBridge 171:3a7713b1edbc 7970 #define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */
AnnaBridge 171:3a7713b1edbc 7971 #define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */
AnnaBridge 171:3a7713b1edbc 7972
AnnaBridge 171:3a7713b1edbc 7973 #define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */
AnnaBridge 171:3a7713b1edbc 7974 #define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */
AnnaBridge 171:3a7713b1edbc 7975
AnnaBridge 171:3a7713b1edbc 7976 #define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */
AnnaBridge 171:3a7713b1edbc 7977 #define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */
AnnaBridge 171:3a7713b1edbc 7978
AnnaBridge 171:3a7713b1edbc 7979 #define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */
AnnaBridge 171:3a7713b1edbc 7980 #define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */
AnnaBridge 171:3a7713b1edbc 7981
AnnaBridge 171:3a7713b1edbc 7982 #define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */
AnnaBridge 171:3a7713b1edbc 7983 #define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */
AnnaBridge 171:3a7713b1edbc 7984
AnnaBridge 171:3a7713b1edbc 7985 #define PWM_WGCTL0_PRDPCTLn_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTLn Position */
AnnaBridge 171:3a7713b1edbc 7986 #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) /*!< PWM_T::WGCTL0: PRDPCTLn Mask */
AnnaBridge 171:3a7713b1edbc 7987
AnnaBridge 171:3a7713b1edbc 7988 #define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */
AnnaBridge 171:3a7713b1edbc 7989 #define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */
AnnaBridge 171:3a7713b1edbc 7990
AnnaBridge 171:3a7713b1edbc 7991 #define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */
AnnaBridge 171:3a7713b1edbc 7992 #define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */
AnnaBridge 171:3a7713b1edbc 7993
AnnaBridge 171:3a7713b1edbc 7994 #define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */
AnnaBridge 171:3a7713b1edbc 7995 #define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */
AnnaBridge 171:3a7713b1edbc 7996
AnnaBridge 171:3a7713b1edbc 7997 #define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */
AnnaBridge 171:3a7713b1edbc 7998 #define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */
AnnaBridge 171:3a7713b1edbc 7999
AnnaBridge 171:3a7713b1edbc 8000 #define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */
AnnaBridge 171:3a7713b1edbc 8001 #define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */
AnnaBridge 171:3a7713b1edbc 8002
AnnaBridge 171:3a7713b1edbc 8003 #define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */
AnnaBridge 171:3a7713b1edbc 8004 #define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */
AnnaBridge 171:3a7713b1edbc 8005
AnnaBridge 171:3a7713b1edbc 8006 #define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */
AnnaBridge 171:3a7713b1edbc 8007 #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */
AnnaBridge 171:3a7713b1edbc 8008
AnnaBridge 171:3a7713b1edbc 8009 #define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */
AnnaBridge 171:3a7713b1edbc 8010 #define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */
AnnaBridge 171:3a7713b1edbc 8011
AnnaBridge 171:3a7713b1edbc 8012 #define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */
AnnaBridge 171:3a7713b1edbc 8013 #define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */
AnnaBridge 171:3a7713b1edbc 8014
AnnaBridge 171:3a7713b1edbc 8015 #define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */
AnnaBridge 171:3a7713b1edbc 8016 #define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */
AnnaBridge 171:3a7713b1edbc 8017
AnnaBridge 171:3a7713b1edbc 8018 #define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */
AnnaBridge 171:3a7713b1edbc 8019 #define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */
AnnaBridge 171:3a7713b1edbc 8020
AnnaBridge 171:3a7713b1edbc 8021 #define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */
AnnaBridge 171:3a7713b1edbc 8022 #define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */
AnnaBridge 171:3a7713b1edbc 8023
AnnaBridge 171:3a7713b1edbc 8024 #define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */
AnnaBridge 171:3a7713b1edbc 8025 #define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */
AnnaBridge 171:3a7713b1edbc 8026
AnnaBridge 171:3a7713b1edbc 8027 #define PWM_WGCTL1_CMPDCTLn_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTLn Position */
AnnaBridge 171:3a7713b1edbc 8028 #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) /*!< PWM_T::WGCTL1: CMPDCTLn Mask */
AnnaBridge 171:3a7713b1edbc 8029
AnnaBridge 171:3a7713b1edbc 8030 #define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */
AnnaBridge 171:3a7713b1edbc 8031 #define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */
AnnaBridge 171:3a7713b1edbc 8032
AnnaBridge 171:3a7713b1edbc 8033 #define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */
AnnaBridge 171:3a7713b1edbc 8034 #define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */
AnnaBridge 171:3a7713b1edbc 8035
AnnaBridge 171:3a7713b1edbc 8036 #define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */
AnnaBridge 171:3a7713b1edbc 8037 #define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */
AnnaBridge 171:3a7713b1edbc 8038
AnnaBridge 171:3a7713b1edbc 8039 #define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */
AnnaBridge 171:3a7713b1edbc 8040 #define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */
AnnaBridge 171:3a7713b1edbc 8041
AnnaBridge 171:3a7713b1edbc 8042 #define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */
AnnaBridge 171:3a7713b1edbc 8043 #define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */
AnnaBridge 171:3a7713b1edbc 8044
AnnaBridge 171:3a7713b1edbc 8045 #define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */
AnnaBridge 171:3a7713b1edbc 8046 #define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */
AnnaBridge 171:3a7713b1edbc 8047
AnnaBridge 171:3a7713b1edbc 8048 #define PWM_MSKEN_MSKENn_Pos (0) /*!< PWM_T::MSKEN: MSKENn Position */
AnnaBridge 171:3a7713b1edbc 8049 #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) /*!< PWM_T::MSKEN: MSKENn Mask */
AnnaBridge 171:3a7713b1edbc 8050
AnnaBridge 171:3a7713b1edbc 8051 #define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */
AnnaBridge 171:3a7713b1edbc 8052 #define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8053
AnnaBridge 171:3a7713b1edbc 8054 #define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */
AnnaBridge 171:3a7713b1edbc 8055 #define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8056
AnnaBridge 171:3a7713b1edbc 8057 #define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */
AnnaBridge 171:3a7713b1edbc 8058 #define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8059
AnnaBridge 171:3a7713b1edbc 8060 #define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */
AnnaBridge 171:3a7713b1edbc 8061 #define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8062
AnnaBridge 171:3a7713b1edbc 8063 #define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */
AnnaBridge 171:3a7713b1edbc 8064 #define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8065
AnnaBridge 171:3a7713b1edbc 8066 #define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */
AnnaBridge 171:3a7713b1edbc 8067 #define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8068
AnnaBridge 171:3a7713b1edbc 8069 #define PWM_MSK_MSKDATn_Pos (0) /*!< PWM_T::MSK: MSKDATn Position */
AnnaBridge 171:3a7713b1edbc 8070 #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) /*!< PWM_T::MSK: MSKDATn Mask */
AnnaBridge 171:3a7713b1edbc 8071
AnnaBridge 171:3a7713b1edbc 8072 #define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */
AnnaBridge 171:3a7713b1edbc 8073 #define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */
AnnaBridge 171:3a7713b1edbc 8074
AnnaBridge 171:3a7713b1edbc 8075 #define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */
AnnaBridge 171:3a7713b1edbc 8076 #define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */
AnnaBridge 171:3a7713b1edbc 8077
AnnaBridge 171:3a7713b1edbc 8078 #define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */
AnnaBridge 171:3a7713b1edbc 8079 #define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */
AnnaBridge 171:3a7713b1edbc 8080
AnnaBridge 171:3a7713b1edbc 8081 #define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */
AnnaBridge 171:3a7713b1edbc 8082 #define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */
AnnaBridge 171:3a7713b1edbc 8083
AnnaBridge 171:3a7713b1edbc 8084 #define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */
AnnaBridge 171:3a7713b1edbc 8085 #define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */
AnnaBridge 171:3a7713b1edbc 8086
AnnaBridge 171:3a7713b1edbc 8087 #define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */
AnnaBridge 171:3a7713b1edbc 8088 #define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */
AnnaBridge 171:3a7713b1edbc 8089
AnnaBridge 171:3a7713b1edbc 8090 #define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */
AnnaBridge 171:3a7713b1edbc 8091 #define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */
AnnaBridge 171:3a7713b1edbc 8092
AnnaBridge 171:3a7713b1edbc 8093 #define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */
AnnaBridge 171:3a7713b1edbc 8094 #define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */
AnnaBridge 171:3a7713b1edbc 8095
AnnaBridge 171:3a7713b1edbc 8096 #define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */
AnnaBridge 171:3a7713b1edbc 8097 #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */
AnnaBridge 171:3a7713b1edbc 8098
AnnaBridge 171:3a7713b1edbc 8099 #define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */
AnnaBridge 171:3a7713b1edbc 8100 #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */
AnnaBridge 171:3a7713b1edbc 8101
AnnaBridge 171:3a7713b1edbc 8102 #define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */
AnnaBridge 171:3a7713b1edbc 8103 #define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */
AnnaBridge 171:3a7713b1edbc 8104
AnnaBridge 171:3a7713b1edbc 8105 #define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */
AnnaBridge 171:3a7713b1edbc 8106 #define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */
AnnaBridge 171:3a7713b1edbc 8107
AnnaBridge 171:3a7713b1edbc 8108 #define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */
AnnaBridge 171:3a7713b1edbc 8109 #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */
AnnaBridge 171:3a7713b1edbc 8110
AnnaBridge 171:3a7713b1edbc 8111 #define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */
AnnaBridge 171:3a7713b1edbc 8112 #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */
AnnaBridge 171:3a7713b1edbc 8113
AnnaBridge 171:3a7713b1edbc 8114 #define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */
AnnaBridge 171:3a7713b1edbc 8115 #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */
AnnaBridge 171:3a7713b1edbc 8116
AnnaBridge 171:3a7713b1edbc 8117 #define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */
AnnaBridge 171:3a7713b1edbc 8118 #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */
AnnaBridge 171:3a7713b1edbc 8119
AnnaBridge 171:3a7713b1edbc 8120 #define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */
AnnaBridge 171:3a7713b1edbc 8121 #define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */
AnnaBridge 171:3a7713b1edbc 8122
AnnaBridge 171:3a7713b1edbc 8123 #define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */
AnnaBridge 171:3a7713b1edbc 8124 #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */
AnnaBridge 171:3a7713b1edbc 8125
AnnaBridge 171:3a7713b1edbc 8126 #define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */
AnnaBridge 171:3a7713b1edbc 8127 #define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */
AnnaBridge 171:3a7713b1edbc 8128
AnnaBridge 171:3a7713b1edbc 8129 #define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */
AnnaBridge 171:3a7713b1edbc 8130 #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */
AnnaBridge 171:3a7713b1edbc 8131
AnnaBridge 171:3a7713b1edbc 8132 #define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */
AnnaBridge 171:3a7713b1edbc 8133 #define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8134
AnnaBridge 171:3a7713b1edbc 8135 #define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */
AnnaBridge 171:3a7713b1edbc 8136 #define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8137
AnnaBridge 171:3a7713b1edbc 8138 #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */
AnnaBridge 171:3a7713b1edbc 8139 #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */
AnnaBridge 171:3a7713b1edbc 8140
AnnaBridge 171:3a7713b1edbc 8141 #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */
AnnaBridge 171:3a7713b1edbc 8142 #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */
AnnaBridge 171:3a7713b1edbc 8143
AnnaBridge 171:3a7713b1edbc 8144 #define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */
AnnaBridge 171:3a7713b1edbc 8145 #define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */
AnnaBridge 171:3a7713b1edbc 8146
AnnaBridge 171:3a7713b1edbc 8147 #define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */
AnnaBridge 171:3a7713b1edbc 8148 #define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8149
AnnaBridge 171:3a7713b1edbc 8150 #define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */
AnnaBridge 171:3a7713b1edbc 8151 #define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8152
AnnaBridge 171:3a7713b1edbc 8153 #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */
AnnaBridge 171:3a7713b1edbc 8154 #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */
AnnaBridge 171:3a7713b1edbc 8155
AnnaBridge 171:3a7713b1edbc 8156 #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */
AnnaBridge 171:3a7713b1edbc 8157 #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */
AnnaBridge 171:3a7713b1edbc 8158
AnnaBridge 171:3a7713b1edbc 8159 #define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */
AnnaBridge 171:3a7713b1edbc 8160 #define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */
AnnaBridge 171:3a7713b1edbc 8161
AnnaBridge 171:3a7713b1edbc 8162 #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */
AnnaBridge 171:3a7713b1edbc 8163 #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */
AnnaBridge 171:3a7713b1edbc 8164
AnnaBridge 171:3a7713b1edbc 8165 #define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */
AnnaBridge 171:3a7713b1edbc 8166 #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */
AnnaBridge 171:3a7713b1edbc 8167
AnnaBridge 171:3a7713b1edbc 8168 #define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */
AnnaBridge 171:3a7713b1edbc 8169 #define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8170
AnnaBridge 171:3a7713b1edbc 8171 #define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */
AnnaBridge 171:3a7713b1edbc 8172 #define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8173
AnnaBridge 171:3a7713b1edbc 8174 #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */
AnnaBridge 171:3a7713b1edbc 8175 #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */
AnnaBridge 171:3a7713b1edbc 8176
AnnaBridge 171:3a7713b1edbc 8177 #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */
AnnaBridge 171:3a7713b1edbc 8178 #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */
AnnaBridge 171:3a7713b1edbc 8179
AnnaBridge 171:3a7713b1edbc 8180 #define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */
AnnaBridge 171:3a7713b1edbc 8181 #define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */
AnnaBridge 171:3a7713b1edbc 8182
AnnaBridge 171:3a7713b1edbc 8183 #define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */
AnnaBridge 171:3a7713b1edbc 8184 #define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8185
AnnaBridge 171:3a7713b1edbc 8186 #define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */
AnnaBridge 171:3a7713b1edbc 8187 #define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8188
AnnaBridge 171:3a7713b1edbc 8189 #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */
AnnaBridge 171:3a7713b1edbc 8190 #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */
AnnaBridge 171:3a7713b1edbc 8191
AnnaBridge 171:3a7713b1edbc 8192 #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */
AnnaBridge 171:3a7713b1edbc 8193 #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */
AnnaBridge 171:3a7713b1edbc 8194
AnnaBridge 171:3a7713b1edbc 8195 #define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */
AnnaBridge 171:3a7713b1edbc 8196 #define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */
AnnaBridge 171:3a7713b1edbc 8197
AnnaBridge 171:3a7713b1edbc 8198 #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */
AnnaBridge 171:3a7713b1edbc 8199 #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */
AnnaBridge 171:3a7713b1edbc 8200
AnnaBridge 171:3a7713b1edbc 8201 #define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */
AnnaBridge 171:3a7713b1edbc 8202 #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */
AnnaBridge 171:3a7713b1edbc 8203
AnnaBridge 171:3a7713b1edbc 8204 #define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */
AnnaBridge 171:3a7713b1edbc 8205 #define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8206
AnnaBridge 171:3a7713b1edbc 8207 #define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */
AnnaBridge 171:3a7713b1edbc 8208 #define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */
AnnaBridge 171:3a7713b1edbc 8209
AnnaBridge 171:3a7713b1edbc 8210 #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */
AnnaBridge 171:3a7713b1edbc 8211 #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */
AnnaBridge 171:3a7713b1edbc 8212
AnnaBridge 171:3a7713b1edbc 8213 #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */
AnnaBridge 171:3a7713b1edbc 8214 #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */
AnnaBridge 171:3a7713b1edbc 8215
AnnaBridge 171:3a7713b1edbc 8216 #define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */
AnnaBridge 171:3a7713b1edbc 8217 #define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */
AnnaBridge 171:3a7713b1edbc 8218
AnnaBridge 171:3a7713b1edbc 8219 #define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */
AnnaBridge 171:3a7713b1edbc 8220 #define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8221
AnnaBridge 171:3a7713b1edbc 8222 #define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */
AnnaBridge 171:3a7713b1edbc 8223 #define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */
AnnaBridge 171:3a7713b1edbc 8224
AnnaBridge 171:3a7713b1edbc 8225 #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */
AnnaBridge 171:3a7713b1edbc 8226 #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */
AnnaBridge 171:3a7713b1edbc 8227
AnnaBridge 171:3a7713b1edbc 8228 #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */
AnnaBridge 171:3a7713b1edbc 8229 #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */
AnnaBridge 171:3a7713b1edbc 8230
AnnaBridge 171:3a7713b1edbc 8231 #define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */
AnnaBridge 171:3a7713b1edbc 8232 #define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */
AnnaBridge 171:3a7713b1edbc 8233
AnnaBridge 171:3a7713b1edbc 8234 #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */
AnnaBridge 171:3a7713b1edbc 8235 #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */
AnnaBridge 171:3a7713b1edbc 8236
AnnaBridge 171:3a7713b1edbc 8237 #define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */
AnnaBridge 171:3a7713b1edbc 8238 #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */
AnnaBridge 171:3a7713b1edbc 8239
AnnaBridge 171:3a7713b1edbc 8240 #define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */
AnnaBridge 171:3a7713b1edbc 8241 #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */
AnnaBridge 171:3a7713b1edbc 8242
AnnaBridge 171:3a7713b1edbc 8243 #define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */
AnnaBridge 171:3a7713b1edbc 8244 #define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */
AnnaBridge 171:3a7713b1edbc 8245
AnnaBridge 171:3a7713b1edbc 8246 #define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */
AnnaBridge 171:3a7713b1edbc 8247 #define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */
AnnaBridge 171:3a7713b1edbc 8248
AnnaBridge 171:3a7713b1edbc 8249 #define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */
AnnaBridge 171:3a7713b1edbc 8250 #define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */
AnnaBridge 171:3a7713b1edbc 8251
AnnaBridge 171:3a7713b1edbc 8252 #define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */
AnnaBridge 171:3a7713b1edbc 8253 #define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */
AnnaBridge 171:3a7713b1edbc 8254
AnnaBridge 171:3a7713b1edbc 8255 #define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */
AnnaBridge 171:3a7713b1edbc 8256 #define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */
AnnaBridge 171:3a7713b1edbc 8257
AnnaBridge 171:3a7713b1edbc 8258 #define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */
AnnaBridge 171:3a7713b1edbc 8259 #define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */
AnnaBridge 171:3a7713b1edbc 8260
AnnaBridge 171:3a7713b1edbc 8261 #define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */
AnnaBridge 171:3a7713b1edbc 8262 #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */
AnnaBridge 171:3a7713b1edbc 8263
AnnaBridge 171:3a7713b1edbc 8264 #define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */
AnnaBridge 171:3a7713b1edbc 8265 #define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8266
AnnaBridge 171:3a7713b1edbc 8267 #define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */
AnnaBridge 171:3a7713b1edbc 8268 #define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8269
AnnaBridge 171:3a7713b1edbc 8270 #define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */
AnnaBridge 171:3a7713b1edbc 8271 #define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8272
AnnaBridge 171:3a7713b1edbc 8273 #define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */
AnnaBridge 171:3a7713b1edbc 8274 #define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8275
AnnaBridge 171:3a7713b1edbc 8276 #define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */
AnnaBridge 171:3a7713b1edbc 8277 #define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8278
AnnaBridge 171:3a7713b1edbc 8279 #define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */
AnnaBridge 171:3a7713b1edbc 8280 #define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8281
AnnaBridge 171:3a7713b1edbc 8282 #define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */
AnnaBridge 171:3a7713b1edbc 8283 #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */
AnnaBridge 171:3a7713b1edbc 8284
AnnaBridge 171:3a7713b1edbc 8285 #define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */
AnnaBridge 171:3a7713b1edbc 8286 #define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */
AnnaBridge 171:3a7713b1edbc 8287
AnnaBridge 171:3a7713b1edbc 8288 #define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */
AnnaBridge 171:3a7713b1edbc 8289 #define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */
AnnaBridge 171:3a7713b1edbc 8290
AnnaBridge 171:3a7713b1edbc 8291 #define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */
AnnaBridge 171:3a7713b1edbc 8292 #define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */
AnnaBridge 171:3a7713b1edbc 8293
AnnaBridge 171:3a7713b1edbc 8294 #define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */
AnnaBridge 171:3a7713b1edbc 8295 #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */
AnnaBridge 171:3a7713b1edbc 8296
AnnaBridge 171:3a7713b1edbc 8297 #define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */
AnnaBridge 171:3a7713b1edbc 8298 #define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */
AnnaBridge 171:3a7713b1edbc 8299
AnnaBridge 171:3a7713b1edbc 8300 #define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */
AnnaBridge 171:3a7713b1edbc 8301 #define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */
AnnaBridge 171:3a7713b1edbc 8302
AnnaBridge 171:3a7713b1edbc 8303 #define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */
AnnaBridge 171:3a7713b1edbc 8304 #define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */
AnnaBridge 171:3a7713b1edbc 8305
AnnaBridge 171:3a7713b1edbc 8306 #define PWM_INTEN0_ZIENn_Pos (0) /*!< PWM_T::INTEN0: ZIENn Position */
AnnaBridge 171:3a7713b1edbc 8307 #define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) /*!< PWM_T::INTEN0: ZIENn Mask */
AnnaBridge 171:3a7713b1edbc 8308
AnnaBridge 171:3a7713b1edbc 8309 #define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */
AnnaBridge 171:3a7713b1edbc 8310 #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8311
AnnaBridge 171:3a7713b1edbc 8312 #define PWM_INTEN0_ZIEN1_Pos (1) /*!< PWM_T::INTEN0: ZIEN1 Position */
AnnaBridge 171:3a7713b1edbc 8313 #define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) /*!< PWM_T::INTEN0: ZIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8314
AnnaBridge 171:3a7713b1edbc 8315 #define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */
AnnaBridge 171:3a7713b1edbc 8316 #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8317
AnnaBridge 171:3a7713b1edbc 8318 #define PWM_INTEN0_ZIEN3_Pos (3) /*!< PWM_T::INTEN0: ZIEN3 Position */
AnnaBridge 171:3a7713b1edbc 8319 #define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) /*!< PWM_T::INTEN0: ZIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8320
AnnaBridge 171:3a7713b1edbc 8321 #define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */
AnnaBridge 171:3a7713b1edbc 8322 #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8323
AnnaBridge 171:3a7713b1edbc 8324 #define PWM_INTEN0_ZIEN5_Pos (5) /*!< PWM_T::INTEN0: ZIEN5 Position */
AnnaBridge 171:3a7713b1edbc 8325 #define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) /*!< PWM_T::INTEN0: ZIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8326
AnnaBridge 171:3a7713b1edbc 8327 #define PWM_INTEN0_IFAIEN0_1_Pos (7) /*!< PWM_T::INTEN0: IFAIEN0_1 Position */
AnnaBridge 171:3a7713b1edbc 8328 #define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) /*!< PWM_T::INTEN0: IFAIEN0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8329
AnnaBridge 171:3a7713b1edbc 8330 #define PWM_INTEN0_PIENn_Pos (8) /*!< PWM_T::INTEN0: PIENn Position */
AnnaBridge 171:3a7713b1edbc 8331 #define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) /*!< PWM_T::INTEN0: PIENn Mask */
AnnaBridge 171:3a7713b1edbc 8332
AnnaBridge 171:3a7713b1edbc 8333 #define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */
AnnaBridge 171:3a7713b1edbc 8334 #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8335
AnnaBridge 171:3a7713b1edbc 8336 #define PWM_INTEN0_PIEN1_Pos (9) /*!< PWM_T::INTEN0: PIEN1 Position */
AnnaBridge 171:3a7713b1edbc 8337 #define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) /*!< PWM_T::INTEN0: PIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8338
AnnaBridge 171:3a7713b1edbc 8339 #define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */
AnnaBridge 171:3a7713b1edbc 8340 #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8341
AnnaBridge 171:3a7713b1edbc 8342 #define PWM_INTEN0_PIEN3_Pos (11) /*!< PWM_T::INTEN0: PIEN3 Position */
AnnaBridge 171:3a7713b1edbc 8343 #define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) /*!< PWM_T::INTEN0: PIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8344
AnnaBridge 171:3a7713b1edbc 8345 #define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */
AnnaBridge 171:3a7713b1edbc 8346 #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8347
AnnaBridge 171:3a7713b1edbc 8348 #define PWM_INTEN0_PIEN5_Pos (13) /*!< PWM_T::INTEN0: PIEN5 Position */
AnnaBridge 171:3a7713b1edbc 8349 #define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) /*!< PWM_T::INTEN0: PIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8350
AnnaBridge 171:3a7713b1edbc 8351 #define PWM_INTEN0_IFAIEN2_3_Pos (15) /*!< PWM_T::INTEN0: IFAIEN2_3 Position */
AnnaBridge 171:3a7713b1edbc 8352 #define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) /*!< PWM_T::INTEN0: IFAIEN2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8353
AnnaBridge 171:3a7713b1edbc 8354 #define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */
AnnaBridge 171:3a7713b1edbc 8355 #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */
AnnaBridge 171:3a7713b1edbc 8356
AnnaBridge 171:3a7713b1edbc 8357 #define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */
AnnaBridge 171:3a7713b1edbc 8358 #define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8359
AnnaBridge 171:3a7713b1edbc 8360 #define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */
AnnaBridge 171:3a7713b1edbc 8361 #define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8362
AnnaBridge 171:3a7713b1edbc 8363 #define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */
AnnaBridge 171:3a7713b1edbc 8364 #define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8365
AnnaBridge 171:3a7713b1edbc 8366 #define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */
AnnaBridge 171:3a7713b1edbc 8367 #define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8368
AnnaBridge 171:3a7713b1edbc 8369 #define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */
AnnaBridge 171:3a7713b1edbc 8370 #define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8371
AnnaBridge 171:3a7713b1edbc 8372 #define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */
AnnaBridge 171:3a7713b1edbc 8373 #define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8374
AnnaBridge 171:3a7713b1edbc 8375 #define PWM_INTEN0_IFAIEN4_5_Pos (23) /*!< PWM_T::INTEN0: IFAIEN4_5 Position */
AnnaBridge 171:3a7713b1edbc 8376 #define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) /*!< PWM_T::INTEN0: IFAIEN4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8377
AnnaBridge 171:3a7713b1edbc 8378 #define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */
AnnaBridge 171:3a7713b1edbc 8379 #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */
AnnaBridge 171:3a7713b1edbc 8380
AnnaBridge 171:3a7713b1edbc 8381 #define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */
AnnaBridge 171:3a7713b1edbc 8382 #define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8383
AnnaBridge 171:3a7713b1edbc 8384 #define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */
AnnaBridge 171:3a7713b1edbc 8385 #define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8386
AnnaBridge 171:3a7713b1edbc 8387 #define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */
AnnaBridge 171:3a7713b1edbc 8388 #define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8389
AnnaBridge 171:3a7713b1edbc 8390 #define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */
AnnaBridge 171:3a7713b1edbc 8391 #define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8392
AnnaBridge 171:3a7713b1edbc 8393 #define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */
AnnaBridge 171:3a7713b1edbc 8394 #define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8395
AnnaBridge 171:3a7713b1edbc 8396 #define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */
AnnaBridge 171:3a7713b1edbc 8397 #define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8398
AnnaBridge 171:3a7713b1edbc 8399 #define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */
AnnaBridge 171:3a7713b1edbc 8400 #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8401
AnnaBridge 171:3a7713b1edbc 8402 #define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */
AnnaBridge 171:3a7713b1edbc 8403 #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8404
AnnaBridge 171:3a7713b1edbc 8405 #define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */
AnnaBridge 171:3a7713b1edbc 8406 #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8407
AnnaBridge 171:3a7713b1edbc 8408 #define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */
AnnaBridge 171:3a7713b1edbc 8409 #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8410
AnnaBridge 171:3a7713b1edbc 8411 #define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */
AnnaBridge 171:3a7713b1edbc 8412 #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8413
AnnaBridge 171:3a7713b1edbc 8414 #define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */
AnnaBridge 171:3a7713b1edbc 8415 #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8416
AnnaBridge 171:3a7713b1edbc 8417 #define PWM_INTSTS0_ZIFn_Pos (0) /*!< PWM_T::INTSTS0: ZIFn Position */
AnnaBridge 171:3a7713b1edbc 8418 #define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) /*!< PWM_T::INTSTS0: ZIFn Mask */
AnnaBridge 171:3a7713b1edbc 8419
AnnaBridge 171:3a7713b1edbc 8420 #define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */
AnnaBridge 171:3a7713b1edbc 8421 #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8422
AnnaBridge 171:3a7713b1edbc 8423 #define PWM_INTSTS0_ZIF1_Pos (1) /*!< PWM_T::INTSTS0: ZIF1 Position */
AnnaBridge 171:3a7713b1edbc 8424 #define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) /*!< PWM_T::INTSTS0: ZIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8425
AnnaBridge 171:3a7713b1edbc 8426 #define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */
AnnaBridge 171:3a7713b1edbc 8427 #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8428
AnnaBridge 171:3a7713b1edbc 8429 #define PWM_INTSTS0_ZIF3_Pos (3) /*!< PWM_T::INTSTS0: ZIF3 Position */
AnnaBridge 171:3a7713b1edbc 8430 #define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) /*!< PWM_T::INTSTS0: ZIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8431
AnnaBridge 171:3a7713b1edbc 8432 #define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */
AnnaBridge 171:3a7713b1edbc 8433 #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8434
AnnaBridge 171:3a7713b1edbc 8435 #define PWM_INTSTS0_ZIF5_Pos (5) /*!< PWM_T::INTSTS0: ZIF5 Position */
AnnaBridge 171:3a7713b1edbc 8436 #define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) /*!< PWM_T::INTSTS0: ZIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8437
AnnaBridge 171:3a7713b1edbc 8438 #define PWM_INTSTS0_IFAIF0_1_Pos (7) /*!< PWM_T::INTSTS0: IFAIF0_1 Position */
AnnaBridge 171:3a7713b1edbc 8439 #define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) /*!< PWM_T::INTSTS0: IFAIF0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8440
AnnaBridge 171:3a7713b1edbc 8441 #define PWM_INTSTS0_PIFn_Pos (8) /*!< PWM_T::INTSTS0: PIFn Position */
AnnaBridge 171:3a7713b1edbc 8442 #define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) /*!< PWM_T::INTSTS0: PIFn Mask */
AnnaBridge 171:3a7713b1edbc 8443
AnnaBridge 171:3a7713b1edbc 8444 #define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */
AnnaBridge 171:3a7713b1edbc 8445 #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8446
AnnaBridge 171:3a7713b1edbc 8447 #define PWM_INTSTS0_PIF1_Pos (9) /*!< PWM_T::INTSTS0: PIF1 Position */
AnnaBridge 171:3a7713b1edbc 8448 #define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) /*!< PWM_T::INTSTS0: PIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8449
AnnaBridge 171:3a7713b1edbc 8450 #define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */
AnnaBridge 171:3a7713b1edbc 8451 #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8452
AnnaBridge 171:3a7713b1edbc 8453 #define PWM_INTSTS0_PIF3_Pos (11) /*!< PWM_T::INTSTS0: PIF3 Position */
AnnaBridge 171:3a7713b1edbc 8454 #define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) /*!< PWM_T::INTSTS0: PIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8455
AnnaBridge 171:3a7713b1edbc 8456 #define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */
AnnaBridge 171:3a7713b1edbc 8457 #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8458
AnnaBridge 171:3a7713b1edbc 8459 #define PWM_INTSTS0_PIF5_Pos (13) /*!< PWM_T::INTSTS0: PIF5 Position */
AnnaBridge 171:3a7713b1edbc 8460 #define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) /*!< PWM_T::INTSTS0: PIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8461
AnnaBridge 171:3a7713b1edbc 8462 #define PWM_INTSTS0_IFAIF2_3_Pos (15) /*!< PWM_T::INTSTS0: IFAIF2_3 Position */
AnnaBridge 171:3a7713b1edbc 8463 #define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) /*!< PWM_T::INTSTS0: IFAIF2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8464
AnnaBridge 171:3a7713b1edbc 8465 #define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */
AnnaBridge 171:3a7713b1edbc 8466 #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */
AnnaBridge 171:3a7713b1edbc 8467
AnnaBridge 171:3a7713b1edbc 8468 #define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */
AnnaBridge 171:3a7713b1edbc 8469 #define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8470
AnnaBridge 171:3a7713b1edbc 8471 #define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */
AnnaBridge 171:3a7713b1edbc 8472 #define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8473
AnnaBridge 171:3a7713b1edbc 8474 #define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */
AnnaBridge 171:3a7713b1edbc 8475 #define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8476
AnnaBridge 171:3a7713b1edbc 8477 #define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */
AnnaBridge 171:3a7713b1edbc 8478 #define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8479
AnnaBridge 171:3a7713b1edbc 8480 #define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */
AnnaBridge 171:3a7713b1edbc 8481 #define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8482
AnnaBridge 171:3a7713b1edbc 8483 #define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */
AnnaBridge 171:3a7713b1edbc 8484 #define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8485
AnnaBridge 171:3a7713b1edbc 8486 #define PWM_INTSTS0_IFAIF4_5_Pos (23) /*!< PWM_T::INTSTS0: IFAIF4_5 Position */
AnnaBridge 171:3a7713b1edbc 8487 #define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) /*!< PWM_T::INTSTS0: IFAIF4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8488
AnnaBridge 171:3a7713b1edbc 8489 #define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */
AnnaBridge 171:3a7713b1edbc 8490 #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */
AnnaBridge 171:3a7713b1edbc 8491
AnnaBridge 171:3a7713b1edbc 8492 #define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */
AnnaBridge 171:3a7713b1edbc 8493 #define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8494
AnnaBridge 171:3a7713b1edbc 8495 #define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */
AnnaBridge 171:3a7713b1edbc 8496 #define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8497
AnnaBridge 171:3a7713b1edbc 8498 #define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */
AnnaBridge 171:3a7713b1edbc 8499 #define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8500
AnnaBridge 171:3a7713b1edbc 8501 #define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */
AnnaBridge 171:3a7713b1edbc 8502 #define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8503
AnnaBridge 171:3a7713b1edbc 8504 #define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */
AnnaBridge 171:3a7713b1edbc 8505 #define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8506
AnnaBridge 171:3a7713b1edbc 8507 #define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */
AnnaBridge 171:3a7713b1edbc 8508 #define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8509
AnnaBridge 171:3a7713b1edbc 8510 #define PWM_INTSTS1_BRKEIFn_Pos (0) /*!< PWM_T::INTSTS1: BRKEIFn Position */
AnnaBridge 171:3a7713b1edbc 8511 #define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) /*!< PWM_T::INTSTS1: BRKEIFn Mask */
AnnaBridge 171:3a7713b1edbc 8512
AnnaBridge 171:3a7713b1edbc 8513 #define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */
AnnaBridge 171:3a7713b1edbc 8514 #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8515
AnnaBridge 171:3a7713b1edbc 8516 #define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */
AnnaBridge 171:3a7713b1edbc 8517 #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8518
AnnaBridge 171:3a7713b1edbc 8519 #define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */
AnnaBridge 171:3a7713b1edbc 8520 #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8521
AnnaBridge 171:3a7713b1edbc 8522 #define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */
AnnaBridge 171:3a7713b1edbc 8523 #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8524
AnnaBridge 171:3a7713b1edbc 8525 #define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */
AnnaBridge 171:3a7713b1edbc 8526 #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8527
AnnaBridge 171:3a7713b1edbc 8528 #define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */
AnnaBridge 171:3a7713b1edbc 8529 #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8530
AnnaBridge 171:3a7713b1edbc 8531 #define PWM_INTSTS1_BRKLIFn_Pos (8) /*!< PWM_T::INTSTS1: BRKLIFn Position */
AnnaBridge 171:3a7713b1edbc 8532 #define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) /*!< PWM_T::INTSTS1: BRKLIFn Mask */
AnnaBridge 171:3a7713b1edbc 8533
AnnaBridge 171:3a7713b1edbc 8534 #define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */
AnnaBridge 171:3a7713b1edbc 8535 #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */
AnnaBridge 171:3a7713b1edbc 8536
AnnaBridge 171:3a7713b1edbc 8537 #define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */
AnnaBridge 171:3a7713b1edbc 8538 #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */
AnnaBridge 171:3a7713b1edbc 8539
AnnaBridge 171:3a7713b1edbc 8540 #define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */
AnnaBridge 171:3a7713b1edbc 8541 #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */
AnnaBridge 171:3a7713b1edbc 8542
AnnaBridge 171:3a7713b1edbc 8543 #define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */
AnnaBridge 171:3a7713b1edbc 8544 #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */
AnnaBridge 171:3a7713b1edbc 8545
AnnaBridge 171:3a7713b1edbc 8546 #define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */
AnnaBridge 171:3a7713b1edbc 8547 #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */
AnnaBridge 171:3a7713b1edbc 8548
AnnaBridge 171:3a7713b1edbc 8549 #define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */
AnnaBridge 171:3a7713b1edbc 8550 #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */
AnnaBridge 171:3a7713b1edbc 8551
AnnaBridge 171:3a7713b1edbc 8552 #define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */
AnnaBridge 171:3a7713b1edbc 8553 #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */
AnnaBridge 171:3a7713b1edbc 8554
AnnaBridge 171:3a7713b1edbc 8555 #define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */
AnnaBridge 171:3a7713b1edbc 8556 #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */
AnnaBridge 171:3a7713b1edbc 8557
AnnaBridge 171:3a7713b1edbc 8558 #define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */
AnnaBridge 171:3a7713b1edbc 8559 #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */
AnnaBridge 171:3a7713b1edbc 8560
AnnaBridge 171:3a7713b1edbc 8561 #define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */
AnnaBridge 171:3a7713b1edbc 8562 #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */
AnnaBridge 171:3a7713b1edbc 8563
AnnaBridge 171:3a7713b1edbc 8564 #define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */
AnnaBridge 171:3a7713b1edbc 8565 #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */
AnnaBridge 171:3a7713b1edbc 8566
AnnaBridge 171:3a7713b1edbc 8567 #define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */
AnnaBridge 171:3a7713b1edbc 8568 #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */
AnnaBridge 171:3a7713b1edbc 8569
AnnaBridge 171:3a7713b1edbc 8570 #define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */
AnnaBridge 171:3a7713b1edbc 8571 #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */
AnnaBridge 171:3a7713b1edbc 8572
AnnaBridge 171:3a7713b1edbc 8573 #define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */
AnnaBridge 171:3a7713b1edbc 8574 #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */
AnnaBridge 171:3a7713b1edbc 8575
AnnaBridge 171:3a7713b1edbc 8576 #define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */
AnnaBridge 171:3a7713b1edbc 8577 #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */
AnnaBridge 171:3a7713b1edbc 8578
AnnaBridge 171:3a7713b1edbc 8579 #define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */
AnnaBridge 171:3a7713b1edbc 8580 #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */
AnnaBridge 171:3a7713b1edbc 8581
AnnaBridge 171:3a7713b1edbc 8582 #define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */
AnnaBridge 171:3a7713b1edbc 8583 #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */
AnnaBridge 171:3a7713b1edbc 8584
AnnaBridge 171:3a7713b1edbc 8585 #define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */
AnnaBridge 171:3a7713b1edbc 8586 #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */
AnnaBridge 171:3a7713b1edbc 8587
AnnaBridge 171:3a7713b1edbc 8588 #define PWM_IFA_IFCNT0_1_Pos (0) /*!< PWM_T::IFA: IFCNT0_1 Position */
AnnaBridge 171:3a7713b1edbc 8589 #define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) /*!< PWM_T::IFA: IFCNT0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8590
AnnaBridge 171:3a7713b1edbc 8591 #define PWM_IFA_IFSEL0_1_Pos (4) /*!< PWM_T::IFA: IFSEL0_1 Position */
AnnaBridge 171:3a7713b1edbc 8592 #define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) /*!< PWM_T::IFA: IFSEL0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8593
AnnaBridge 171:3a7713b1edbc 8594 #define PWM_IFA_IFAEN0_1_Pos (7) /*!< PWM_T::IFA: IFAEN0_1 Position */
AnnaBridge 171:3a7713b1edbc 8595 #define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) /*!< PWM_T::IFA: IFAEN0_1 Mask */
AnnaBridge 171:3a7713b1edbc 8596
AnnaBridge 171:3a7713b1edbc 8597 #define PWM_IFA_IFCNT2_3_Pos (8) /*!< PWM_T::IFA: IFCNT2_3 Position */
AnnaBridge 171:3a7713b1edbc 8598 #define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) /*!< PWM_T::IFA: IFCNT2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8599
AnnaBridge 171:3a7713b1edbc 8600 #define PWM_IFA_IFSEL2_3_Pos (12) /*!< PWM_T::IFA: IFSEL2_3 Position */
AnnaBridge 171:3a7713b1edbc 8601 #define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) /*!< PWM_T::IFA: IFSEL2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8602
AnnaBridge 171:3a7713b1edbc 8603 #define PWM_IFA_IFAEN2_3_Pos (15) /*!< PWM_T::IFA: IFAEN2_3 Position */
AnnaBridge 171:3a7713b1edbc 8604 #define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) /*!< PWM_T::IFA: IFAEN2_3 Mask */
AnnaBridge 171:3a7713b1edbc 8605
AnnaBridge 171:3a7713b1edbc 8606 #define PWM_IFA_IFCNT4_5_Pos (16) /*!< PWM_T::IFA: IFCNT4_5 Position */
AnnaBridge 171:3a7713b1edbc 8607 #define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) /*!< PWM_T::IFA: IFCNT4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8608
AnnaBridge 171:3a7713b1edbc 8609 #define PWM_IFA_IFSEL4_5_Pos (20) /*!< PWM_T::IFA: IFSEL4_5 Position */
AnnaBridge 171:3a7713b1edbc 8610 #define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) /*!< PWM_T::IFA: IFSEL4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8611
AnnaBridge 171:3a7713b1edbc 8612 #define PWM_IFA_IFAEN4_5_Pos (23) /*!< PWM_T::IFA: IFAEN4_5 Position */
AnnaBridge 171:3a7713b1edbc 8613 #define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) /*!< PWM_T::IFA: IFAEN4_5 Mask */
AnnaBridge 171:3a7713b1edbc 8614
AnnaBridge 171:3a7713b1edbc 8615 #define PWM_DACTRGEN_ZTEn_Pos (0) /*!< PWM_T::DACTRGEN: ZTEn Position */
AnnaBridge 171:3a7713b1edbc 8616 #define PWM_DACTRGEN_ZTEn_Msk (0x3ful << PWM_DACTRGEN_ZTEn_Pos) /*!< PWM_T::DACTRGEN: ZTEn Mask */
AnnaBridge 171:3a7713b1edbc 8617
AnnaBridge 171:3a7713b1edbc 8618 #define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */
AnnaBridge 171:3a7713b1edbc 8619 #define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */
AnnaBridge 171:3a7713b1edbc 8620
AnnaBridge 171:3a7713b1edbc 8621 #define PWM_DACTRGEN_ZTE1_Pos (1) /*!< PWM_T::DACTRGEN: ZTE1 Position */
AnnaBridge 171:3a7713b1edbc 8622 #define PWM_DACTRGEN_ZTE1_Msk (0x1ul << PWM_DACTRGEN_ZTE1_Pos) /*!< PWM_T::DACTRGEN: ZTE1 Mask */
AnnaBridge 171:3a7713b1edbc 8623
AnnaBridge 171:3a7713b1edbc 8624 #define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */
AnnaBridge 171:3a7713b1edbc 8625 #define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */
AnnaBridge 171:3a7713b1edbc 8626
AnnaBridge 171:3a7713b1edbc 8627 #define PWM_DACTRGEN_ZTE3_Pos (3) /*!< PWM_T::DACTRGEN: ZTE3 Position */
AnnaBridge 171:3a7713b1edbc 8628 #define PWM_DACTRGEN_ZTE3_Msk (0x1ul << PWM_DACTRGEN_ZTE3_Pos) /*!< PWM_T::DACTRGEN: ZTE3 Mask */
AnnaBridge 171:3a7713b1edbc 8629
AnnaBridge 171:3a7713b1edbc 8630 #define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */
AnnaBridge 171:3a7713b1edbc 8631 #define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */
AnnaBridge 171:3a7713b1edbc 8632
AnnaBridge 171:3a7713b1edbc 8633 #define PWM_DACTRGEN_ZTE5_Pos (5) /*!< PWM_T::DACTRGEN: ZTE5 Position */
AnnaBridge 171:3a7713b1edbc 8634 #define PWM_DACTRGEN_ZTE5_Msk (0x1ul << PWM_DACTRGEN_ZTE5_Pos) /*!< PWM_T::DACTRGEN: ZTE5 Mask */
AnnaBridge 171:3a7713b1edbc 8635
AnnaBridge 171:3a7713b1edbc 8636 #define PWM_DACTRGEN_PTEn_Pos (8) /*!< PWM_T::DACTRGEN: PTEn Position */
AnnaBridge 171:3a7713b1edbc 8637 #define PWM_DACTRGEN_PTEn_Msk (0x3ful << PWM_DACTRGEN_PTEn_Pos) /*!< PWM_T::DACTRGEN: PTEn Mask */
AnnaBridge 171:3a7713b1edbc 8638
AnnaBridge 171:3a7713b1edbc 8639 #define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */
AnnaBridge 171:3a7713b1edbc 8640 #define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */
AnnaBridge 171:3a7713b1edbc 8641
AnnaBridge 171:3a7713b1edbc 8642 #define PWM_DACTRGEN_PTE1_Pos (9) /*!< PWM_T::DACTRGEN: PTE1 Position */
AnnaBridge 171:3a7713b1edbc 8643 #define PWM_DACTRGEN_PTE1_Msk (0x1ul << PWM_DACTRGEN_PTE1_Pos) /*!< PWM_T::DACTRGEN: PTE1 Mask */
AnnaBridge 171:3a7713b1edbc 8644
AnnaBridge 171:3a7713b1edbc 8645 #define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */
AnnaBridge 171:3a7713b1edbc 8646 #define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */
AnnaBridge 171:3a7713b1edbc 8647
AnnaBridge 171:3a7713b1edbc 8648 #define PWM_DACTRGEN_PTE3_Pos (11) /*!< PWM_T::DACTRGEN: PTE3 Position */
AnnaBridge 171:3a7713b1edbc 8649 #define PWM_DACTRGEN_PTE3_Msk (0x1ul << PWM_DACTRGEN_PTE3_Pos) /*!< PWM_T::DACTRGEN: PTE3 Mask */
AnnaBridge 171:3a7713b1edbc 8650
AnnaBridge 171:3a7713b1edbc 8651 #define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */
AnnaBridge 171:3a7713b1edbc 8652 #define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */
AnnaBridge 171:3a7713b1edbc 8653
AnnaBridge 171:3a7713b1edbc 8654 #define PWM_DACTRGEN_PTE5_Pos (13) /*!< PWM_T::DACTRGEN: PTE5 Position */
AnnaBridge 171:3a7713b1edbc 8655 #define PWM_DACTRGEN_PTE5_Msk (0x1ul << PWM_DACTRGEN_PTE5_Pos) /*!< PWM_T::DACTRGEN: PTE5 Mask */
AnnaBridge 171:3a7713b1edbc 8656
AnnaBridge 171:3a7713b1edbc 8657 #define PWM_DACTRGEN_CUTRGEn_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEn Position */
AnnaBridge 171:3a7713b1edbc 8658 #define PWM_DACTRGEN_CUTRGEn_Msk (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos) /*!< PWM_T::DACTRGEN: CUTRGEn Mask */
AnnaBridge 171:3a7713b1edbc 8659
AnnaBridge 171:3a7713b1edbc 8660 #define PWM_DACTRGEN_CUTRGE0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGE0 Position */
AnnaBridge 171:3a7713b1edbc 8661 #define PWM_DACTRGEN_CUTRGE0_Msk (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos) /*!< PWM_T::DACTRGEN: CUTRGE0 Mask */
AnnaBridge 171:3a7713b1edbc 8662
AnnaBridge 171:3a7713b1edbc 8663 #define PWM_DACTRGEN_CUTRGE1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGE1 Position */
AnnaBridge 171:3a7713b1edbc 8664 #define PWM_DACTRGEN_CUTRGE1_Msk (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos) /*!< PWM_T::DACTRGEN: CUTRGE1 Mask */
AnnaBridge 171:3a7713b1edbc 8665
AnnaBridge 171:3a7713b1edbc 8666 #define PWM_DACTRGEN_CUTRGE2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGE2 Position */
AnnaBridge 171:3a7713b1edbc 8667 #define PWM_DACTRGEN_CUTRGE2_Msk (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos) /*!< PWM_T::DACTRGEN: CUTRGE2 Mask */
AnnaBridge 171:3a7713b1edbc 8668
AnnaBridge 171:3a7713b1edbc 8669 #define PWM_DACTRGEN_CUTRGE3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGE3 Position */
AnnaBridge 171:3a7713b1edbc 8670 #define PWM_DACTRGEN_CUTRGE3_Msk (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos) /*!< PWM_T::DACTRGEN: CUTRGE3 Mask */
AnnaBridge 171:3a7713b1edbc 8671
AnnaBridge 171:3a7713b1edbc 8672 #define PWM_DACTRGEN_CUTRGE4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGE4 Position */
AnnaBridge 171:3a7713b1edbc 8673 #define PWM_DACTRGEN_CUTRGE4_Msk (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos) /*!< PWM_T::DACTRGEN: CUTRGE4 Mask */
AnnaBridge 171:3a7713b1edbc 8674
AnnaBridge 171:3a7713b1edbc 8675 #define PWM_DACTRGEN_CUTRGE5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGE5 Position */
AnnaBridge 171:3a7713b1edbc 8676 #define PWM_DACTRGEN_CUTRGE5_Msk (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos) /*!< PWM_T::DACTRGEN: CUTRGE5 Mask */
AnnaBridge 171:3a7713b1edbc 8677
AnnaBridge 171:3a7713b1edbc 8678 #define PWM_DACTRGEN_CDTRGEn_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEn Position */
AnnaBridge 171:3a7713b1edbc 8679 #define PWM_DACTRGEN_CDTRGEn_Msk (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos) /*!< PWM_T::DACTRGEN: CDTRGEn Mask */
AnnaBridge 171:3a7713b1edbc 8680
AnnaBridge 171:3a7713b1edbc 8681 #define PWM_DACTRGEN_CDTRGE0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGE0 Position */
AnnaBridge 171:3a7713b1edbc 8682 #define PWM_DACTRGEN_CDTRGE0_Msk (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos) /*!< PWM_T::DACTRGEN: CDTRGE0 Mask */
AnnaBridge 171:3a7713b1edbc 8683
AnnaBridge 171:3a7713b1edbc 8684 #define PWM_DACTRGEN_CDTRGE1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGE1 Position */
AnnaBridge 171:3a7713b1edbc 8685 #define PWM_DACTRGEN_CDTRGE1_Msk (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos) /*!< PWM_T::DACTRGEN: CDTRGE1 Mask */
AnnaBridge 171:3a7713b1edbc 8686
AnnaBridge 171:3a7713b1edbc 8687 #define PWM_DACTRGEN_CDTRGE2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGE2 Position */
AnnaBridge 171:3a7713b1edbc 8688 #define PWM_DACTRGEN_CDTRGE2_Msk (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos) /*!< PWM_T::DACTRGEN: CDTRGE2 Mask */
AnnaBridge 171:3a7713b1edbc 8689
AnnaBridge 171:3a7713b1edbc 8690 #define PWM_DACTRGEN_CDTRGE3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGE3 Position */
AnnaBridge 171:3a7713b1edbc 8691 #define PWM_DACTRGEN_CDTRGE3_Msk (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos) /*!< PWM_T::DACTRGEN: CDTRGE3 Mask */
AnnaBridge 171:3a7713b1edbc 8692
AnnaBridge 171:3a7713b1edbc 8693 #define PWM_DACTRGEN_CDTRGE4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGE4 Position */
AnnaBridge 171:3a7713b1edbc 8694 #define PWM_DACTRGEN_CDTRGE4_Msk (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos) /*!< PWM_T::DACTRGEN: CDTRGE4 Mask */
AnnaBridge 171:3a7713b1edbc 8695
AnnaBridge 171:3a7713b1edbc 8696 #define PWM_DACTRGEN_CDTRGE5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGE5 Position */
AnnaBridge 171:3a7713b1edbc 8697 #define PWM_DACTRGEN_CDTRGE5_Msk (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos) /*!< PWM_T::DACTRGEN: CDTRGE5 Mask */
AnnaBridge 171:3a7713b1edbc 8698
AnnaBridge 171:3a7713b1edbc 8699 #define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */
AnnaBridge 171:3a7713b1edbc 8700 #define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */
AnnaBridge 171:3a7713b1edbc 8701
AnnaBridge 171:3a7713b1edbc 8702 #define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */
AnnaBridge 171:3a7713b1edbc 8703 #define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8704
AnnaBridge 171:3a7713b1edbc 8705 #define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */
AnnaBridge 171:3a7713b1edbc 8706 #define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */
AnnaBridge 171:3a7713b1edbc 8707
AnnaBridge 171:3a7713b1edbc 8708 #define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */
AnnaBridge 171:3a7713b1edbc 8709 #define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8710
AnnaBridge 171:3a7713b1edbc 8711 #define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */
AnnaBridge 171:3a7713b1edbc 8712 #define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */
AnnaBridge 171:3a7713b1edbc 8713
AnnaBridge 171:3a7713b1edbc 8714 #define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */
AnnaBridge 171:3a7713b1edbc 8715 #define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8716
AnnaBridge 171:3a7713b1edbc 8717 #define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */
AnnaBridge 171:3a7713b1edbc 8718 #define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */
AnnaBridge 171:3a7713b1edbc 8719
AnnaBridge 171:3a7713b1edbc 8720 #define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */
AnnaBridge 171:3a7713b1edbc 8721 #define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8722
AnnaBridge 171:3a7713b1edbc 8723 #define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */
AnnaBridge 171:3a7713b1edbc 8724 #define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */
AnnaBridge 171:3a7713b1edbc 8725
AnnaBridge 171:3a7713b1edbc 8726 #define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */
AnnaBridge 171:3a7713b1edbc 8727 #define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8728
AnnaBridge 171:3a7713b1edbc 8729 #define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */
AnnaBridge 171:3a7713b1edbc 8730 #define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */
AnnaBridge 171:3a7713b1edbc 8731
AnnaBridge 171:3a7713b1edbc 8732 #define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */
AnnaBridge 171:3a7713b1edbc 8733 #define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8734
AnnaBridge 171:3a7713b1edbc 8735 #define PWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT0_1: FTCMP Position */
AnnaBridge 171:3a7713b1edbc 8736 #define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask */
AnnaBridge 171:3a7713b1edbc 8737
AnnaBridge 171:3a7713b1edbc 8738 #define PWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT2_3: FTCMP Position */
AnnaBridge 171:3a7713b1edbc 8739 #define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask */
AnnaBridge 171:3a7713b1edbc 8740
AnnaBridge 171:3a7713b1edbc 8741 #define PWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT4_5: FTCMP Position */
AnnaBridge 171:3a7713b1edbc 8742 #define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask */
AnnaBridge 171:3a7713b1edbc 8743
AnnaBridge 171:3a7713b1edbc 8744 #define PWM_SSCTL_SSENn_Pos (0) /*!< PWM_T::SSCTL: SSENn Position */
AnnaBridge 171:3a7713b1edbc 8745 #define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) /*!< PWM_T::SSCTL: SSENn Mask */
AnnaBridge 171:3a7713b1edbc 8746
AnnaBridge 171:3a7713b1edbc 8747 #define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */
AnnaBridge 171:3a7713b1edbc 8748 #define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8749
AnnaBridge 171:3a7713b1edbc 8750 #define PWM_SSCTL_SSEN1_Pos (1) /*!< PWM_T::SSCTL: SSEN1 Position */
AnnaBridge 171:3a7713b1edbc 8751 #define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) /*!< PWM_T::SSCTL: SSEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8752
AnnaBridge 171:3a7713b1edbc 8753 #define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */
AnnaBridge 171:3a7713b1edbc 8754 #define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8755
AnnaBridge 171:3a7713b1edbc 8756 #define PWM_SSCTL_SSEN3_Pos (3) /*!< PWM_T::SSCTL: SSEN3 Position */
AnnaBridge 171:3a7713b1edbc 8757 #define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) /*!< PWM_T::SSCTL: SSEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8758
AnnaBridge 171:3a7713b1edbc 8759 #define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */
AnnaBridge 171:3a7713b1edbc 8760 #define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8761
AnnaBridge 171:3a7713b1edbc 8762 #define PWM_SSCTL_SSEN5_Pos (5) /*!< PWM_T::SSCTL: SSEN5 Position */
AnnaBridge 171:3a7713b1edbc 8763 #define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) /*!< PWM_T::SSCTL: SSEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8764
AnnaBridge 171:3a7713b1edbc 8765 #define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */
AnnaBridge 171:3a7713b1edbc 8766 #define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */
AnnaBridge 171:3a7713b1edbc 8767
AnnaBridge 171:3a7713b1edbc 8768 #define PWM_STATUS_CNTMAXFn_Pos (0) /*!< PWM_T::STATUS: CNTMAXFn Position */
AnnaBridge 171:3a7713b1edbc 8769 #define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) /*!< PWM_T::STATUS: CNTMAXFn Mask */
AnnaBridge 171:3a7713b1edbc 8770
AnnaBridge 171:3a7713b1edbc 8771 #define PWM_STATUS_CNTMAXF0_Pos (0) /*!< PWM_T::STATUS: CNTMAXF0 Position */
AnnaBridge 171:3a7713b1edbc 8772 #define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) /*!< PWM_T::STATUS: CNTMAXF0 Mask */
AnnaBridge 171:3a7713b1edbc 8773
AnnaBridge 171:3a7713b1edbc 8774 #define PWM_STATUS_CNTMAXF1_Pos (1) /*!< PWM_T::STATUS: CNTMAXF1 Position */
AnnaBridge 171:3a7713b1edbc 8775 #define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) /*!< PWM_T::STATUS: CNTMAXF1 Mask */
AnnaBridge 171:3a7713b1edbc 8776
AnnaBridge 171:3a7713b1edbc 8777 #define PWM_STATUS_CNTMAXF2_Pos (2) /*!< PWM_T::STATUS: CNTMAXF2 Position */
AnnaBridge 171:3a7713b1edbc 8778 #define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) /*!< PWM_T::STATUS: CNTMAXF2 Mask */
AnnaBridge 171:3a7713b1edbc 8779
AnnaBridge 171:3a7713b1edbc 8780 #define PWM_STATUS_CNTMAXF3_Pos (3) /*!< PWM_T::STATUS: CNTMAXF3 Position */
AnnaBridge 171:3a7713b1edbc 8781 #define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) /*!< PWM_T::STATUS: CNTMAXF3 Mask */
AnnaBridge 171:3a7713b1edbc 8782
AnnaBridge 171:3a7713b1edbc 8783 #define PWM_STATUS_CNTMAXF4_Pos (4) /*!< PWM_T::STATUS: CNTMAXF4 Position */
AnnaBridge 171:3a7713b1edbc 8784 #define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) /*!< PWM_T::STATUS: CNTMAXF4 Mask */
AnnaBridge 171:3a7713b1edbc 8785
AnnaBridge 171:3a7713b1edbc 8786 #define PWM_STATUS_CNTMAXF5_Pos (5) /*!< PWM_T::STATUS: CNTMAXF5 Position */
AnnaBridge 171:3a7713b1edbc 8787 #define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) /*!< PWM_T::STATUS: CNTMAXF5 Mask */
AnnaBridge 171:3a7713b1edbc 8788
AnnaBridge 171:3a7713b1edbc 8789 #define PWM_STATUS_SYNCINFn_Pos (8) /*!< PWM_T::STATUS: SYNCINFn Position */
AnnaBridge 171:3a7713b1edbc 8790 #define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) /*!< PWM_T::STATUS: SYNCINFn Mask */
AnnaBridge 171:3a7713b1edbc 8791
AnnaBridge 171:3a7713b1edbc 8792 #define PWM_STATUS_SYNCINF0_Pos (8) /*!< PWM_T::STATUS: SYNCINF0 Position */
AnnaBridge 171:3a7713b1edbc 8793 #define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) /*!< PWM_T::STATUS: SYNCINF0 Mask */
AnnaBridge 171:3a7713b1edbc 8794
AnnaBridge 171:3a7713b1edbc 8795 #define PWM_STATUS_SYNCINF2_Pos (9) /*!< PWM_T::STATUS: SYNCINF2 Position */
AnnaBridge 171:3a7713b1edbc 8796 #define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) /*!< PWM_T::STATUS: SYNCINF2 Mask */
AnnaBridge 171:3a7713b1edbc 8797
AnnaBridge 171:3a7713b1edbc 8798 #define PWM_STATUS_SYNCINF4_Pos (10) /*!< PWM_T::STATUS: SYNCINF4 Position */
AnnaBridge 171:3a7713b1edbc 8799 #define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) /*!< PWM_T::STATUS: SYNCINF4 Mask */
AnnaBridge 171:3a7713b1edbc 8800
AnnaBridge 171:3a7713b1edbc 8801 #define PWM_STATUS_ADCTRGFn_Pos (16) /*!< PWM_T::STATUS: ADCTRGFn Position */
AnnaBridge 171:3a7713b1edbc 8802 #define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) /*!< PWM_T::STATUS: ADCTRGFn Mask */
AnnaBridge 171:3a7713b1edbc 8803
AnnaBridge 171:3a7713b1edbc 8804 #define PWM_STATUS_ADCTRGF0_Pos (16) /*!< PWM_T::STATUS: ADCTRGF0 Position */
AnnaBridge 171:3a7713b1edbc 8805 #define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) /*!< PWM_T::STATUS: ADCTRGF0 Mask */
AnnaBridge 171:3a7713b1edbc 8806
AnnaBridge 171:3a7713b1edbc 8807 #define PWM_STATUS_ADCTRGF1_Pos (17) /*!< PWM_T::STATUS: ADCTRGF1 Position */
AnnaBridge 171:3a7713b1edbc 8808 #define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) /*!< PWM_T::STATUS: ADCTRGF1 Mask */
AnnaBridge 171:3a7713b1edbc 8809
AnnaBridge 171:3a7713b1edbc 8810 #define PWM_STATUS_ADCTRGF2_Pos (18) /*!< PWM_T::STATUS: ADCTRGF2 Position */
AnnaBridge 171:3a7713b1edbc 8811 #define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) /*!< PWM_T::STATUS: ADCTRGF2 Mask */
AnnaBridge 171:3a7713b1edbc 8812
AnnaBridge 171:3a7713b1edbc 8813 #define PWM_STATUS_ADCTRGF3_Pos (19) /*!< PWM_T::STATUS: ADCTRGF3 Position */
AnnaBridge 171:3a7713b1edbc 8814 #define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) /*!< PWM_T::STATUS: ADCTRGF3 Mask */
AnnaBridge 171:3a7713b1edbc 8815
AnnaBridge 171:3a7713b1edbc 8816 #define PWM_STATUS_ADCTRGF4_Pos (20) /*!< PWM_T::STATUS: ADCTRGF4 Position */
AnnaBridge 171:3a7713b1edbc 8817 #define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) /*!< PWM_T::STATUS: ADCTRGF4 Mask */
AnnaBridge 171:3a7713b1edbc 8818
AnnaBridge 171:3a7713b1edbc 8819 #define PWM_STATUS_ADCTRGF5_Pos (21) /*!< PWM_T::STATUS: ADCTRGF5 Position */
AnnaBridge 171:3a7713b1edbc 8820 #define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) /*!< PWM_T::STATUS: ADCTRGF5 Mask */
AnnaBridge 171:3a7713b1edbc 8821
AnnaBridge 171:3a7713b1edbc 8822 #define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */
AnnaBridge 171:3a7713b1edbc 8823 #define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */
AnnaBridge 171:3a7713b1edbc 8824
AnnaBridge 171:3a7713b1edbc 8825 #define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */
AnnaBridge 171:3a7713b1edbc 8826 #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */
AnnaBridge 171:3a7713b1edbc 8827
AnnaBridge 171:3a7713b1edbc 8828 #define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */
AnnaBridge 171:3a7713b1edbc 8829 #define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8830
AnnaBridge 171:3a7713b1edbc 8831 #define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */
AnnaBridge 171:3a7713b1edbc 8832 #define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8833
AnnaBridge 171:3a7713b1edbc 8834 #define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */
AnnaBridge 171:3a7713b1edbc 8835 #define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8836
AnnaBridge 171:3a7713b1edbc 8837 #define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */
AnnaBridge 171:3a7713b1edbc 8838 #define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8839
AnnaBridge 171:3a7713b1edbc 8840 #define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */
AnnaBridge 171:3a7713b1edbc 8841 #define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8842
AnnaBridge 171:3a7713b1edbc 8843 #define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */
AnnaBridge 171:3a7713b1edbc 8844 #define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8845
AnnaBridge 171:3a7713b1edbc 8846 #define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */
AnnaBridge 171:3a7713b1edbc 8847 #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */
AnnaBridge 171:3a7713b1edbc 8848
AnnaBridge 171:3a7713b1edbc 8849 #define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */
AnnaBridge 171:3a7713b1edbc 8850 #define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8851
AnnaBridge 171:3a7713b1edbc 8852 #define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */
AnnaBridge 171:3a7713b1edbc 8853 #define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8854
AnnaBridge 171:3a7713b1edbc 8855 #define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */
AnnaBridge 171:3a7713b1edbc 8856 #define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8857
AnnaBridge 171:3a7713b1edbc 8858 #define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */
AnnaBridge 171:3a7713b1edbc 8859 #define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8860
AnnaBridge 171:3a7713b1edbc 8861 #define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */
AnnaBridge 171:3a7713b1edbc 8862 #define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8863
AnnaBridge 171:3a7713b1edbc 8864 #define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */
AnnaBridge 171:3a7713b1edbc 8865 #define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8866
AnnaBridge 171:3a7713b1edbc 8867 #define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */
AnnaBridge 171:3a7713b1edbc 8868 #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */
AnnaBridge 171:3a7713b1edbc 8869
AnnaBridge 171:3a7713b1edbc 8870 #define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */
AnnaBridge 171:3a7713b1edbc 8871 #define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */
AnnaBridge 171:3a7713b1edbc 8872
AnnaBridge 171:3a7713b1edbc 8873 #define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */
AnnaBridge 171:3a7713b1edbc 8874 #define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */
AnnaBridge 171:3a7713b1edbc 8875
AnnaBridge 171:3a7713b1edbc 8876 #define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */
AnnaBridge 171:3a7713b1edbc 8877 #define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */
AnnaBridge 171:3a7713b1edbc 8878
AnnaBridge 171:3a7713b1edbc 8879 #define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */
AnnaBridge 171:3a7713b1edbc 8880 #define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */
AnnaBridge 171:3a7713b1edbc 8881
AnnaBridge 171:3a7713b1edbc 8882 #define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */
AnnaBridge 171:3a7713b1edbc 8883 #define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */
AnnaBridge 171:3a7713b1edbc 8884
AnnaBridge 171:3a7713b1edbc 8885 #define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */
AnnaBridge 171:3a7713b1edbc 8886 #define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */
AnnaBridge 171:3a7713b1edbc 8887
AnnaBridge 171:3a7713b1edbc 8888 #define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */
AnnaBridge 171:3a7713b1edbc 8889 #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */
AnnaBridge 171:3a7713b1edbc 8890
AnnaBridge 171:3a7713b1edbc 8891 #define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */
AnnaBridge 171:3a7713b1edbc 8892 #define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8893
AnnaBridge 171:3a7713b1edbc 8894 #define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */
AnnaBridge 171:3a7713b1edbc 8895 #define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8896
AnnaBridge 171:3a7713b1edbc 8897 #define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */
AnnaBridge 171:3a7713b1edbc 8898 #define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8899
AnnaBridge 171:3a7713b1edbc 8900 #define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */
AnnaBridge 171:3a7713b1edbc 8901 #define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8902
AnnaBridge 171:3a7713b1edbc 8903 #define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */
AnnaBridge 171:3a7713b1edbc 8904 #define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8905
AnnaBridge 171:3a7713b1edbc 8906 #define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */
AnnaBridge 171:3a7713b1edbc 8907 #define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8908
AnnaBridge 171:3a7713b1edbc 8909 #define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */
AnnaBridge 171:3a7713b1edbc 8910 #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */
AnnaBridge 171:3a7713b1edbc 8911
AnnaBridge 171:3a7713b1edbc 8912 #define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */
AnnaBridge 171:3a7713b1edbc 8913 #define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */
AnnaBridge 171:3a7713b1edbc 8914
AnnaBridge 171:3a7713b1edbc 8915 #define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */
AnnaBridge 171:3a7713b1edbc 8916 #define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */
AnnaBridge 171:3a7713b1edbc 8917
AnnaBridge 171:3a7713b1edbc 8918 #define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */
AnnaBridge 171:3a7713b1edbc 8919 #define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */
AnnaBridge 171:3a7713b1edbc 8920
AnnaBridge 171:3a7713b1edbc 8921 #define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */
AnnaBridge 171:3a7713b1edbc 8922 #define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */
AnnaBridge 171:3a7713b1edbc 8923
AnnaBridge 171:3a7713b1edbc 8924 #define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */
AnnaBridge 171:3a7713b1edbc 8925 #define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */
AnnaBridge 171:3a7713b1edbc 8926
AnnaBridge 171:3a7713b1edbc 8927 #define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */
AnnaBridge 171:3a7713b1edbc 8928 #define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */
AnnaBridge 171:3a7713b1edbc 8929
AnnaBridge 171:3a7713b1edbc 8930 #define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */
AnnaBridge 171:3a7713b1edbc 8931 #define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */
AnnaBridge 171:3a7713b1edbc 8932
AnnaBridge 171:3a7713b1edbc 8933 #define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */
AnnaBridge 171:3a7713b1edbc 8934 #define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */
AnnaBridge 171:3a7713b1edbc 8935
AnnaBridge 171:3a7713b1edbc 8936 #define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */
AnnaBridge 171:3a7713b1edbc 8937 #define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */
AnnaBridge 171:3a7713b1edbc 8938
AnnaBridge 171:3a7713b1edbc 8939 #define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */
AnnaBridge 171:3a7713b1edbc 8940 #define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */
AnnaBridge 171:3a7713b1edbc 8941
AnnaBridge 171:3a7713b1edbc 8942 #define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */
AnnaBridge 171:3a7713b1edbc 8943 #define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */
AnnaBridge 171:3a7713b1edbc 8944
AnnaBridge 171:3a7713b1edbc 8945 #define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */
AnnaBridge 171:3a7713b1edbc 8946 #define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */
AnnaBridge 171:3a7713b1edbc 8947
AnnaBridge 171:3a7713b1edbc 8948 #define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */
AnnaBridge 171:3a7713b1edbc 8949 #define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */
AnnaBridge 171:3a7713b1edbc 8950
AnnaBridge 171:3a7713b1edbc 8951 #define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */
AnnaBridge 171:3a7713b1edbc 8952 #define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */
AnnaBridge 171:3a7713b1edbc 8953
AnnaBridge 171:3a7713b1edbc 8954 #define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */
AnnaBridge 171:3a7713b1edbc 8955 #define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */
AnnaBridge 171:3a7713b1edbc 8956
AnnaBridge 171:3a7713b1edbc 8957 #define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */
AnnaBridge 171:3a7713b1edbc 8958 #define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */
AnnaBridge 171:3a7713b1edbc 8959
AnnaBridge 171:3a7713b1edbc 8960 #define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */
AnnaBridge 171:3a7713b1edbc 8961 #define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */
AnnaBridge 171:3a7713b1edbc 8962
AnnaBridge 171:3a7713b1edbc 8963 #define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */
AnnaBridge 171:3a7713b1edbc 8964 #define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */
AnnaBridge 171:3a7713b1edbc 8965
AnnaBridge 171:3a7713b1edbc 8966 #define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */
AnnaBridge 171:3a7713b1edbc 8967 #define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */
AnnaBridge 171:3a7713b1edbc 8968
AnnaBridge 171:3a7713b1edbc 8969 #define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */
AnnaBridge 171:3a7713b1edbc 8970 #define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */
AnnaBridge 171:3a7713b1edbc 8971
AnnaBridge 171:3a7713b1edbc 8972 #define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8973 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8974
AnnaBridge 171:3a7713b1edbc 8975 #define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8976 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8977
AnnaBridge 171:3a7713b1edbc 8978 #define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8979 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8980
AnnaBridge 171:3a7713b1edbc 8981 #define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8982 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8983
AnnaBridge 171:3a7713b1edbc 8984 #define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8985 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8986
AnnaBridge 171:3a7713b1edbc 8987 #define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8988 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8989
AnnaBridge 171:3a7713b1edbc 8990 #define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8991 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8992
AnnaBridge 171:3a7713b1edbc 8993 #define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8994 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8995
AnnaBridge 171:3a7713b1edbc 8996 #define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 8997 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 8998
AnnaBridge 171:3a7713b1edbc 8999 #define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 9000 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 9001
AnnaBridge 171:3a7713b1edbc 9002 #define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 9003 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 9004
AnnaBridge 171:3a7713b1edbc 9005 #define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */
AnnaBridge 171:3a7713b1edbc 9006 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 9007
AnnaBridge 171:3a7713b1edbc 9008 #define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */
AnnaBridge 171:3a7713b1edbc 9009 #define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */
AnnaBridge 171:3a7713b1edbc 9010
AnnaBridge 171:3a7713b1edbc 9011 #define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */
AnnaBridge 171:3a7713b1edbc 9012 #define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */
AnnaBridge 171:3a7713b1edbc 9013
AnnaBridge 171:3a7713b1edbc 9014 #define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */
AnnaBridge 171:3a7713b1edbc 9015 #define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */
AnnaBridge 171:3a7713b1edbc 9016
AnnaBridge 171:3a7713b1edbc 9017 #define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */
AnnaBridge 171:3a7713b1edbc 9018 #define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */
AnnaBridge 171:3a7713b1edbc 9019
AnnaBridge 171:3a7713b1edbc 9020 #define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */
AnnaBridge 171:3a7713b1edbc 9021 #define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */
AnnaBridge 171:3a7713b1edbc 9022
AnnaBridge 171:3a7713b1edbc 9023 #define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */
AnnaBridge 171:3a7713b1edbc 9024 #define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */
AnnaBridge 171:3a7713b1edbc 9025
AnnaBridge 171:3a7713b1edbc 9026 #define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */
AnnaBridge 171:3a7713b1edbc 9027 #define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */
AnnaBridge 171:3a7713b1edbc 9028
AnnaBridge 171:3a7713b1edbc 9029 #define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */
AnnaBridge 171:3a7713b1edbc 9030 #define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */
AnnaBridge 171:3a7713b1edbc 9031
AnnaBridge 171:3a7713b1edbc 9032 #define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */
AnnaBridge 171:3a7713b1edbc 9033 #define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */
AnnaBridge 171:3a7713b1edbc 9034
AnnaBridge 171:3a7713b1edbc 9035 #define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */
AnnaBridge 171:3a7713b1edbc 9036 #define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */
AnnaBridge 171:3a7713b1edbc 9037
AnnaBridge 171:3a7713b1edbc 9038 #define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */
AnnaBridge 171:3a7713b1edbc 9039 #define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */
AnnaBridge 171:3a7713b1edbc 9040
AnnaBridge 171:3a7713b1edbc 9041 #define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */
AnnaBridge 171:3a7713b1edbc 9042 #define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */
AnnaBridge 171:3a7713b1edbc 9043
AnnaBridge 171:3a7713b1edbc 9044 #define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */
AnnaBridge 171:3a7713b1edbc 9045 #define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9046
AnnaBridge 171:3a7713b1edbc 9047 #define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */
AnnaBridge 171:3a7713b1edbc 9048 #define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9049
AnnaBridge 171:3a7713b1edbc 9050 #define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */
AnnaBridge 171:3a7713b1edbc 9051 #define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9052
AnnaBridge 171:3a7713b1edbc 9053 #define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */
AnnaBridge 171:3a7713b1edbc 9054 #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */
AnnaBridge 171:3a7713b1edbc 9055
AnnaBridge 171:3a7713b1edbc 9056 #define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */
AnnaBridge 171:3a7713b1edbc 9057 #define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 9058
AnnaBridge 171:3a7713b1edbc 9059 #define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */
AnnaBridge 171:3a7713b1edbc 9060 #define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 9061
AnnaBridge 171:3a7713b1edbc 9062 #define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */
AnnaBridge 171:3a7713b1edbc 9063 #define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 9064
AnnaBridge 171:3a7713b1edbc 9065 #define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */
AnnaBridge 171:3a7713b1edbc 9066 #define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 9067
AnnaBridge 171:3a7713b1edbc 9068 #define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */
AnnaBridge 171:3a7713b1edbc 9069 #define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 9070
AnnaBridge 171:3a7713b1edbc 9071 #define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */
AnnaBridge 171:3a7713b1edbc 9072 #define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 9073
AnnaBridge 171:3a7713b1edbc 9074 #define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */
AnnaBridge 171:3a7713b1edbc 9075 #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */
AnnaBridge 171:3a7713b1edbc 9076
AnnaBridge 171:3a7713b1edbc 9077 #define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */
AnnaBridge 171:3a7713b1edbc 9078 #define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */
AnnaBridge 171:3a7713b1edbc 9079
AnnaBridge 171:3a7713b1edbc 9080 #define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */
AnnaBridge 171:3a7713b1edbc 9081 #define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */
AnnaBridge 171:3a7713b1edbc 9082
AnnaBridge 171:3a7713b1edbc 9083 #define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */
AnnaBridge 171:3a7713b1edbc 9084 #define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */
AnnaBridge 171:3a7713b1edbc 9085
AnnaBridge 171:3a7713b1edbc 9086 #define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */
AnnaBridge 171:3a7713b1edbc 9087 #define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */
AnnaBridge 171:3a7713b1edbc 9088
AnnaBridge 171:3a7713b1edbc 9089 #define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */
AnnaBridge 171:3a7713b1edbc 9090 #define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */
AnnaBridge 171:3a7713b1edbc 9091
AnnaBridge 171:3a7713b1edbc 9092 #define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */
AnnaBridge 171:3a7713b1edbc 9093 #define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */
AnnaBridge 171:3a7713b1edbc 9094
AnnaBridge 171:3a7713b1edbc 9095 #define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */
AnnaBridge 171:3a7713b1edbc 9096 #define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */
AnnaBridge 171:3a7713b1edbc 9097
AnnaBridge 171:3a7713b1edbc 9098 #define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */
AnnaBridge 171:3a7713b1edbc 9099 #define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */
AnnaBridge 171:3a7713b1edbc 9100
AnnaBridge 171:3a7713b1edbc 9101 #define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */
AnnaBridge 171:3a7713b1edbc 9102 #define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */
AnnaBridge 171:3a7713b1edbc 9103
AnnaBridge 171:3a7713b1edbc 9104 #define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */
AnnaBridge 171:3a7713b1edbc 9105 #define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */
AnnaBridge 171:3a7713b1edbc 9106
AnnaBridge 171:3a7713b1edbc 9107 #define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */
AnnaBridge 171:3a7713b1edbc 9108 #define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */
AnnaBridge 171:3a7713b1edbc 9109
AnnaBridge 171:3a7713b1edbc 9110 #define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */
AnnaBridge 171:3a7713b1edbc 9111 #define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */
AnnaBridge 171:3a7713b1edbc 9112
AnnaBridge 171:3a7713b1edbc 9113 #define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */
AnnaBridge 171:3a7713b1edbc 9114 #define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */
AnnaBridge 171:3a7713b1edbc 9115
AnnaBridge 171:3a7713b1edbc 9116 #define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */
AnnaBridge 171:3a7713b1edbc 9117 #define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */
AnnaBridge 171:3a7713b1edbc 9118
AnnaBridge 171:3a7713b1edbc 9119 #define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */
AnnaBridge 171:3a7713b1edbc 9120 #define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */
AnnaBridge 171:3a7713b1edbc 9121
AnnaBridge 171:3a7713b1edbc 9122 #define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */
AnnaBridge 171:3a7713b1edbc 9123 #define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */
AnnaBridge 171:3a7713b1edbc 9124
AnnaBridge 171:3a7713b1edbc 9125 #define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */
AnnaBridge 171:3a7713b1edbc 9126 #define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */
AnnaBridge 171:3a7713b1edbc 9127
AnnaBridge 171:3a7713b1edbc 9128 #define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */
AnnaBridge 171:3a7713b1edbc 9129 #define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */
AnnaBridge 171:3a7713b1edbc 9130
AnnaBridge 171:3a7713b1edbc 9131 #define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */
AnnaBridge 171:3a7713b1edbc 9132 #define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */
AnnaBridge 171:3a7713b1edbc 9133
AnnaBridge 171:3a7713b1edbc 9134 #define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */
AnnaBridge 171:3a7713b1edbc 9135 #define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */
AnnaBridge 171:3a7713b1edbc 9136
AnnaBridge 171:3a7713b1edbc 9137 #define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF: PBUF Position */
AnnaBridge 171:3a7713b1edbc 9138 #define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF: PBUF Mask */
AnnaBridge 171:3a7713b1edbc 9139
AnnaBridge 171:3a7713b1edbc 9140 #define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF: CMPBUF Position */
AnnaBridge 171:3a7713b1edbc 9141 #define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF: CMPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9142
AnnaBridge 171:3a7713b1edbc 9143 #define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position */
AnnaBridge 171:3a7713b1edbc 9144 #define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9145
AnnaBridge 171:3a7713b1edbc 9146 #define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position */
AnnaBridge 171:3a7713b1edbc 9147 #define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9148
AnnaBridge 171:3a7713b1edbc 9149 #define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position */
AnnaBridge 171:3a7713b1edbc 9150 #define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask */
AnnaBridge 171:3a7713b1edbc 9151
AnnaBridge 171:3a7713b1edbc 9152 #define PWM_FTCI_FTCMUn_Pos (0) /*!< PWM_T::FTCI: FTCMUn Position */
AnnaBridge 171:3a7713b1edbc 9153 #define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) /*!< PWM_T::FTCI: FTCMUn Mask */
AnnaBridge 171:3a7713b1edbc 9154
AnnaBridge 171:3a7713b1edbc 9155 #define PWM_FTCI_FTCMU0_Pos (0) /*!< PWM_T::FTCI: FTCMU0 Position */
AnnaBridge 171:3a7713b1edbc 9156 #define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) /*!< PWM_T::FTCI: FTCMU0 Mask */
AnnaBridge 171:3a7713b1edbc 9157
AnnaBridge 171:3a7713b1edbc 9158 #define PWM_FTCI_FTCMU2_Pos (1) /*!< PWM_T::FTCI: FTCMU2 Position */
AnnaBridge 171:3a7713b1edbc 9159 #define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) /*!< PWM_T::FTCI: FTCMU2 Mask */
AnnaBridge 171:3a7713b1edbc 9160
AnnaBridge 171:3a7713b1edbc 9161 #define PWM_FTCI_FTCMU4_Pos (2) /*!< PWM_T::FTCI: FTCMU4 Position */
AnnaBridge 171:3a7713b1edbc 9162 #define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) /*!< PWM_T::FTCI: FTCMU4 Mask */
AnnaBridge 171:3a7713b1edbc 9163
AnnaBridge 171:3a7713b1edbc 9164 #define PWM_FTCI_FTCMDn_Pos (8) /*!< PWM_T::FTCI: FTCMDn Position */
AnnaBridge 171:3a7713b1edbc 9165 #define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) /*!< PWM_T::FTCI: FTCMDn Mask */
AnnaBridge 171:3a7713b1edbc 9166
AnnaBridge 171:3a7713b1edbc 9167 #define PWM_FTCI_FTCMD0_Pos (8) /*!< PWM_T::FTCI: FTCMD0 Position */
AnnaBridge 171:3a7713b1edbc 9168 #define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) /*!< PWM_T::FTCI: FTCMD0 Mask */
AnnaBridge 171:3a7713b1edbc 9169
AnnaBridge 171:3a7713b1edbc 9170 #define PWM_FTCI_FTCMD2_Pos (9) /*!< PWM_T::FTCI: FTCMD2 Position */
AnnaBridge 171:3a7713b1edbc 9171 #define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) /*!< PWM_T::FTCI: FTCMD2 Mask */
AnnaBridge 171:3a7713b1edbc 9172
AnnaBridge 171:3a7713b1edbc 9173 #define PWM_FTCI_FTCMD4_Pos (10) /*!< PWM_T::FTCI: FTCMD4 Position */
AnnaBridge 171:3a7713b1edbc 9174 #define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /*!< PWM_T::FTCI: FTCMD4 Mask */
AnnaBridge 171:3a7713b1edbc 9175
AnnaBridge 171:3a7713b1edbc 9176 /**@}*/ /* PWM_CONST */
AnnaBridge 171:3a7713b1edbc 9177 /**@}*/ /* end of PWM register group */
AnnaBridge 171:3a7713b1edbc 9178
AnnaBridge 171:3a7713b1edbc 9179
AnnaBridge 171:3a7713b1edbc 9180 /*---------------------- Real Time Clock Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 9181 /**
AnnaBridge 171:3a7713b1edbc 9182 @addtogroup RTC Real Time Clock Controller(RTC)
AnnaBridge 171:3a7713b1edbc 9183 Memory Mapped Structure for RTC Controller
AnnaBridge 171:3a7713b1edbc 9184 @{ */
AnnaBridge 171:3a7713b1edbc 9185
AnnaBridge 171:3a7713b1edbc 9186
AnnaBridge 171:3a7713b1edbc 9187 typedef struct
AnnaBridge 171:3a7713b1edbc 9188 {
AnnaBridge 171:3a7713b1edbc 9189
AnnaBridge 171:3a7713b1edbc 9190
AnnaBridge 171:3a7713b1edbc 9191
AnnaBridge 171:3a7713b1edbc 9192
AnnaBridge 171:3a7713b1edbc 9193 /**
AnnaBridge 171:3a7713b1edbc 9194 * @var RTC_T::INIT
AnnaBridge 171:3a7713b1edbc 9195 * Offset: 0x00 RTC Initiation Register
AnnaBridge 171:3a7713b1edbc 9196 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9197 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9198 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9199 * |[0] |INIT[0]/ACTIVE|RTC Active Status (Read Only)
AnnaBridge 171:3a7713b1edbc 9200 * | | |0 = RTC is at reset state.
AnnaBridge 171:3a7713b1edbc 9201 * | | |1 = RTC is at normal active state.
AnnaBridge 171:3a7713b1edbc 9202 * |[31:1] |INIT[31:1]|RTC Initiation
AnnaBridge 171:3a7713b1edbc 9203 * | | |When RTC block is powered on, RTC is at reset state.
AnnaBridge 171:3a7713b1edbc 9204 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
AnnaBridge 171:3a7713b1edbc 9205 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
AnnaBridge 171:3a7713b1edbc 9206 * | | |The INIT is a write-only field and read value will be always 0.
AnnaBridge 171:3a7713b1edbc 9207 * @var RTC_T::RWEN
AnnaBridge 171:3a7713b1edbc 9208 * Offset: 0x04 RTC Access Enable Register
AnnaBridge 171:3a7713b1edbc 9209 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9210 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9211 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9212 * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
AnnaBridge 171:3a7713b1edbc 9213 * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
AnnaBridge 171:3a7713b1edbc 9214 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 9215 * | | |0 = RTC register read/write Disabled.
AnnaBridge 171:3a7713b1edbc 9216 * | | |1 = RTC register read/write Enabled.
AnnaBridge 171:3a7713b1edbc 9217 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
AnnaBridge 171:3a7713b1edbc 9218 * @var RTC_T::FREQADJ
AnnaBridge 171:3a7713b1edbc 9219 * Offset: 0x08 RTC Frequency Compensation Register
AnnaBridge 171:3a7713b1edbc 9220 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9221 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9222 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9223 * |[5:0] |FRACTION |Fraction Part
AnnaBridge 171:3a7713b1edbc 9224 * | | |Formula = (fraction part of detected value) x 60.
AnnaBridge 171:3a7713b1edbc 9225 * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
AnnaBridge 171:3a7713b1edbc 9226 * |[11:8] |INTEGER |Integer Part
AnnaBridge 171:3a7713b1edbc 9227 * @var RTC_T::TIME
AnnaBridge 171:3a7713b1edbc 9228 * Offset: 0x0C Time Loading Register
AnnaBridge 171:3a7713b1edbc 9229 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9230 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9231 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9232 * |[3:0] |SEC |1-Sec Time Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9233 * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
AnnaBridge 171:3a7713b1edbc 9234 * |[11:8] |MIN |1-Min Time Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9235 * |[14:12] |TENMIN |10-Min Time Digit (0~5)
AnnaBridge 171:3a7713b1edbc 9236 * |[19:16] |HR |1-Hour Time Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9237 * |[21:20] |TENHR |10-Hour Time Digit (0~2)
AnnaBridge 171:3a7713b1edbc 9238 * @var RTC_T::CAL
AnnaBridge 171:3a7713b1edbc 9239 * Offset: 0x10 RTC Calendar Loading Register
AnnaBridge 171:3a7713b1edbc 9240 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9241 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9242 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9243 * |[3:0] |DAY |1-Day Calendar Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9244 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
AnnaBridge 171:3a7713b1edbc 9245 * |[11:8] |MON |1-Month Calendar Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9246 * |[12] |TENMON |10-Month Calendar Digit (0~1)
AnnaBridge 171:3a7713b1edbc 9247 * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9248 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
AnnaBridge 171:3a7713b1edbc 9249 * @var RTC_T::CLKFMT
AnnaBridge 171:3a7713b1edbc 9250 * Offset: 0x14 Time Scale Selection Register
AnnaBridge 171:3a7713b1edbc 9251 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9252 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9253 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9254 * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
AnnaBridge 171:3a7713b1edbc 9255 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
AnnaBridge 171:3a7713b1edbc 9256 * | | |0 = 12-hour time scale with AM and PM indication selected.
AnnaBridge 171:3a7713b1edbc 9257 * | | |1 = 24-hour time scale selected.
AnnaBridge 171:3a7713b1edbc 9258 * @var RTC_T::WEEKDAY
AnnaBridge 171:3a7713b1edbc 9259 * Offset: 0x18 Day of the Week Register
AnnaBridge 171:3a7713b1edbc 9260 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9261 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9262 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9263 * |[2:0] |WEEKDAY |Day Of The Week Register
AnnaBridge 171:3a7713b1edbc 9264 * | | |000 = Sunday.
AnnaBridge 171:3a7713b1edbc 9265 * | | |001 = Monday.
AnnaBridge 171:3a7713b1edbc 9266 * | | |010 = Tuesday.
AnnaBridge 171:3a7713b1edbc 9267 * | | |011 = Wednesday.
AnnaBridge 171:3a7713b1edbc 9268 * | | |100 = Thursday.
AnnaBridge 171:3a7713b1edbc 9269 * | | |101 = Friday.
AnnaBridge 171:3a7713b1edbc 9270 * | | |110 = Saturday.
AnnaBridge 171:3a7713b1edbc 9271 * | | |111 = Reserved.
AnnaBridge 171:3a7713b1edbc 9272 * @var RTC_T::TALM
AnnaBridge 171:3a7713b1edbc 9273 * Offset: 0x1C Time Alarm Register
AnnaBridge 171:3a7713b1edbc 9274 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9275 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9276 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9277 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9278 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
AnnaBridge 171:3a7713b1edbc 9279 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9280 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
AnnaBridge 171:3a7713b1edbc 9281 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9282 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
AnnaBridge 171:3a7713b1edbc 9283 * @var RTC_T::CALM
AnnaBridge 171:3a7713b1edbc 9284 * Offset: 0x20 Calendar Alarm Register
AnnaBridge 171:3a7713b1edbc 9285 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9286 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9287 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9288 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9289 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
AnnaBridge 171:3a7713b1edbc 9290 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9291 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
AnnaBridge 171:3a7713b1edbc 9292 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9293 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9294 * @var RTC_T::LEAPYEAR
AnnaBridge 171:3a7713b1edbc 9295 * Offset: 0x24 RTC Leap Year Indicator Register
AnnaBridge 171:3a7713b1edbc 9296 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9297 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9298 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9299 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
AnnaBridge 171:3a7713b1edbc 9300 * | | |0 = This year is not a leap year.
AnnaBridge 171:3a7713b1edbc 9301 * | | |1 = This year is leap year.
AnnaBridge 171:3a7713b1edbc 9302 * @var RTC_T::INTEN
AnnaBridge 171:3a7713b1edbc 9303 * Offset: 0x28 RTC Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 9304 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9305 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9306 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9307 * |[0] |ALMIEN |Alarm Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 9308 * | | |0 = RTC Alarm interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 9309 * | | |1 = RTC Alarm interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 9310 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 9311 * | | |0 = RTC Time Tick interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 9312 * | | |1 = RTC Time Tick interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 9313 * |[2] |SNPDIEN |Snoop Detection Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 9314 * | | |0 = Snoop detected interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 9315 * | | |1 = Snoop detected interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 9316 * @var RTC_T::INTSTS
AnnaBridge 171:3a7713b1edbc 9317 * Offset: 0x2C RTC Interrupt Indicator Register
AnnaBridge 171:3a7713b1edbc 9318 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9319 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9320 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9321 * |[0] |ALMIF |RTC Alarm Interrupt Flag
AnnaBridge 171:3a7713b1edbc 9322 * | | |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
AnnaBridge 171:3a7713b1edbc 9323 * | | |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
AnnaBridge 171:3a7713b1edbc 9324 * | | |0 = Alarm condition is not matched.
AnnaBridge 171:3a7713b1edbc 9325 * | | |1 = Alarm condition is matched.
AnnaBridge 171:3a7713b1edbc 9326 * | | |Note: Write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 9327 * |[1] |TICKIF |RTC Time Tick Interrupt Flag
AnnaBridge 171:3a7713b1edbc 9328 * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
AnnaBridge 171:3a7713b1edbc 9329 * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
AnnaBridge 171:3a7713b1edbc 9330 * | | |0 = Tick condition does not occur.
AnnaBridge 171:3a7713b1edbc 9331 * | | |1 = Tick condition occur.
AnnaBridge 171:3a7713b1edbc 9332 * | | |Note: Write 1 to clear to clear this bit.
AnnaBridge 171:3a7713b1edbc 9333 * |[2] |SNPDIF |Snoop Detect Interrupt Flag
AnnaBridge 171:3a7713b1edbc 9334 * | | |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
AnnaBridge 171:3a7713b1edbc 9335 * | | |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 9336 * | | |0 = No snoop event is detected.
AnnaBridge 171:3a7713b1edbc 9337 * | | |1 = Snoop event is detected.
AnnaBridge 171:3a7713b1edbc 9338 * | | |Note: Write 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 9339 * @var RTC_T::TICK
AnnaBridge 171:3a7713b1edbc 9340 * Offset: 0x30 RTC Time Tick Register
AnnaBridge 171:3a7713b1edbc 9341 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9342 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9343 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9344 * |[2:0] |TICK |Time Tick Register
AnnaBridge 171:3a7713b1edbc 9345 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
AnnaBridge 171:3a7713b1edbc 9346 * | | |000 = Time tick is 1 second.
AnnaBridge 171:3a7713b1edbc 9347 * | | |001 = Time tick is 1/2 second.
AnnaBridge 171:3a7713b1edbc 9348 * | | |010 = Time tick is 1/4 second.
AnnaBridge 171:3a7713b1edbc 9349 * | | |011 = Time tick is 1/8 second.
AnnaBridge 171:3a7713b1edbc 9350 * | | |100 = Time tick is 1/16 second.
AnnaBridge 171:3a7713b1edbc 9351 * | | |101 = Time tick is 1/32 second.
AnnaBridge 171:3a7713b1edbc 9352 * | | |110 = Time tick is 1/64 second.
AnnaBridge 171:3a7713b1edbc 9353 * | | |111 = Time tick is 1/28 second.
AnnaBridge 171:3a7713b1edbc 9354 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
AnnaBridge 171:3a7713b1edbc 9355 * @var RTC_T::TAMSK
AnnaBridge 171:3a7713b1edbc 9356 * Offset: 0x34 Time Alarm Mask Register
AnnaBridge 171:3a7713b1edbc 9357 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9358 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9359 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9360 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9361 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
AnnaBridge 171:3a7713b1edbc 9362 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9363 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
AnnaBridge 171:3a7713b1edbc 9364 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9365 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
AnnaBridge 171:3a7713b1edbc 9366 * @var RTC_T::CAMSK
AnnaBridge 171:3a7713b1edbc 9367 * Offset: 0x38 Calendar Alarm Mask Register
AnnaBridge 171:3a7713b1edbc 9368 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9369 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9370 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9371 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9372 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
AnnaBridge 171:3a7713b1edbc 9373 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9374 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
AnnaBridge 171:3a7713b1edbc 9375 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9376 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
AnnaBridge 171:3a7713b1edbc 9377 * @var RTC_T::SPRCTL
AnnaBridge 171:3a7713b1edbc 9378 * Offset: 0x3C RTC Spare Functional Control Register
AnnaBridge 171:3a7713b1edbc 9379 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9380 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9381 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9382 * |[0] |SNPDEN |Snoop Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 9383 * | | |0 = TAMPER pin detection is Disabled.
AnnaBridge 171:3a7713b1edbc 9384 * | | |1 = TAMPER pin detection is Enabled.
AnnaBridge 171:3a7713b1edbc 9385 * |[1] |SNPTYPE0 |Snoop Detection Level
AnnaBridge 171:3a7713b1edbc 9386 * | | |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
AnnaBridge 171:3a7713b1edbc 9387 * | | |0 = Low level/Falling edge detection.
AnnaBridge 171:3a7713b1edbc 9388 * | | |1 = High level/Rising edge detection.
AnnaBridge 171:3a7713b1edbc 9389 * |[2] |SPRRWEN |Spare Register Enable Bit
AnnaBridge 171:3a7713b1edbc 9390 * | | |0 = Spare register is Disabled.
AnnaBridge 171:3a7713b1edbc 9391 * | | |1 = Spare register is Enabled.
AnnaBridge 171:3a7713b1edbc 9392 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
AnnaBridge 171:3a7713b1edbc 9393 * |[3] |SNPTYPE1 |Snoop Detection Mode
AnnaBridge 171:3a7713b1edbc 9394 * | | |This bit controls TAMPER pin is edge or level detection
AnnaBridge 171:3a7713b1edbc 9395 * | | |0 = Level detection.
AnnaBridge 171:3a7713b1edbc 9396 * | | |1 = Edge detection.
AnnaBridge 171:3a7713b1edbc 9397 * |[5] |SPRCSTS |SPR Clear Flag
AnnaBridge 171:3a7713b1edbc 9398 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
AnnaBridge 171:3a7713b1edbc 9399 * | | |0 = Spare register content is not cleared.
AnnaBridge 171:3a7713b1edbc 9400 * | | |1 = Spare register content is cleared.
AnnaBridge 171:3a7713b1edbc 9401 * | | |Writes 1 to clear this bit.
AnnaBridge 171:3a7713b1edbc 9402 * |[7] |SPRRWRDY |SPR Register Ready
AnnaBridge 171:3a7713b1edbc 9403 * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
AnnaBridge 171:3a7713b1edbc 9404 * | | |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
AnnaBridge 171:3a7713b1edbc 9405 * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
AnnaBridge 171:3a7713b1edbc 9406 * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
AnnaBridge 171:3a7713b1edbc 9407 * | | |Note: This bit is read only and any write to it won't take any effect.
AnnaBridge 171:3a7713b1edbc 9408 * @var RTC_T::SPR
AnnaBridge 171:3a7713b1edbc 9409 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
AnnaBridge 171:3a7713b1edbc 9410 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9411 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9412 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9413 * |[31:0] |SPARE |Spare Register
AnnaBridge 171:3a7713b1edbc 9414 * | | |This field is used to store back-up information defined by user.
AnnaBridge 171:3a7713b1edbc 9415 * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
AnnaBridge 171:3a7713b1edbc 9416 * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
AnnaBridge 171:3a7713b1edbc 9417 * @var RTC_T::LXTCTL
AnnaBridge 171:3a7713b1edbc 9418 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
AnnaBridge 171:3a7713b1edbc 9419 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9420 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9421 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9422 * |[0] |LXTEN |Backup Domain 32K Oscillator Enable Bit
AnnaBridge 171:3a7713b1edbc 9423 * | | |0 = Oscillator is Disabled.
AnnaBridge 171:3a7713b1edbc 9424 * | | |1 = Oscillator is Enabled.
AnnaBridge 171:3a7713b1edbc 9425 * | | |This bit controls 32 kHz oscillator on/off.
AnnaBridge 171:3a7713b1edbc 9426 * | | |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
AnnaBridge 171:3a7713b1edbc 9427 * | | |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
AnnaBridge 171:3a7713b1edbc 9428 * |[3:1] |GAIN |Oscillator Gain Option
AnnaBridge 171:3a7713b1edbc 9429 * | | |User can select oscillator gain according to crystal external loading and operating temperature range.
AnnaBridge 171:3a7713b1edbc 9430 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
AnnaBridge 171:3a7713b1edbc 9431 * | | |000 = L0 mode.
AnnaBridge 171:3a7713b1edbc 9432 * | | |001 = L1 mode.
AnnaBridge 171:3a7713b1edbc 9433 * | | |010 = L2 mode.
AnnaBridge 171:3a7713b1edbc 9434 * | | |011 = L3 mode.
AnnaBridge 171:3a7713b1edbc 9435 * | | |100 = L4 mode.
AnnaBridge 171:3a7713b1edbc 9436 * | | |101 = L5 mode.
AnnaBridge 171:3a7713b1edbc 9437 * | | |110 = L6 mode.
AnnaBridge 171:3a7713b1edbc 9438 * | | |111 = L7 mode (Default).
AnnaBridge 171:3a7713b1edbc 9439 * @var RTC_T::LXTOCTL
AnnaBridge 171:3a7713b1edbc 9440 * Offset: 0x104 X32KO Pin Control Register
AnnaBridge 171:3a7713b1edbc 9441 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9442 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9443 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9444 * |[1:0] |OPMODE |GPF0 Operation Mode
AnnaBridge 171:3a7713b1edbc 9445 * | | |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
AnnaBridge 171:3a7713b1edbc 9446 * | | |01 = X32KO (PF.0) is output push pull mode.
AnnaBridge 171:3a7713b1edbc 9447 * | | |10 = X32KO (PF.0) is open drain mode.
AnnaBridge 171:3a7713b1edbc 9448 * | | |11 = X32KO (PF.0) is input only mode with internal pull up.
AnnaBridge 171:3a7713b1edbc 9449 * |[2] |DOUT |IO Output Data
AnnaBridge 171:3a7713b1edbc 9450 * | | |0 = X32KO (PF.0) output low.
AnnaBridge 171:3a7713b1edbc 9451 * | | |1 = X32KO (PF.0) output high.
AnnaBridge 171:3a7713b1edbc 9452 * |[3] |CTLSEL |IO Pin State Backup Selection
AnnaBridge 171:3a7713b1edbc 9453 * | | |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
AnnaBridge 171:3a7713b1edbc 9454 * | | |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
AnnaBridge 171:3a7713b1edbc 9455 * | | |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
AnnaBridge 171:3a7713b1edbc 9456 * | | |It becomes floating when system power is turned off.
AnnaBridge 171:3a7713b1edbc 9457 * | | |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
AnnaBridge 171:3a7713b1edbc 9458 * | | |I/O pin keeps the previous state after system power is turned off.
AnnaBridge 171:3a7713b1edbc 9459 * @var RTC_T::LXTICTL
AnnaBridge 171:3a7713b1edbc 9460 * Offset: 0x108 X32KI Pin Control Register
AnnaBridge 171:3a7713b1edbc 9461 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9462 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9463 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9464 * |[1:0] |OPMODE |IO Operation Mode
AnnaBridge 171:3a7713b1edbc 9465 * | | |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
AnnaBridge 171:3a7713b1edbc 9466 * | | |01 = X32KI (PF.1) is output push pull mode.
AnnaBridge 171:3a7713b1edbc 9467 * | | |10 = X32KI (PF.1) is open drain mode.
AnnaBridge 171:3a7713b1edbc 9468 * | | |11 = X32KI (PF.1) is input only mode with internal pull up.
AnnaBridge 171:3a7713b1edbc 9469 * |[2] |DOUT |IO Output Data
AnnaBridge 171:3a7713b1edbc 9470 * | | |0 = X32KI (PF.1) output low.
AnnaBridge 171:3a7713b1edbc 9471 * | | |1 = X32KI (PF.1) output high.
AnnaBridge 171:3a7713b1edbc 9472 * |[3] |CTLSEL |IO Pin State Backup Selection
AnnaBridge 171:3a7713b1edbc 9473 * | | |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
AnnaBridge 171:3a7713b1edbc 9474 * | | |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
AnnaBridge 171:3a7713b1edbc 9475 * | | |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
AnnaBridge 171:3a7713b1edbc 9476 * | | |It becomes floating state when system power is turned off.
AnnaBridge 171:3a7713b1edbc 9477 * | | |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
AnnaBridge 171:3a7713b1edbc 9478 * | | |I/O pin keeps the previous state after system power is turned off.
AnnaBridge 171:3a7713b1edbc 9479 * @var RTC_T::TAMPCTL
AnnaBridge 171:3a7713b1edbc 9480 * Offset: 0x10C TAMPER Pin Control Register
AnnaBridge 171:3a7713b1edbc 9481 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9482 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9483 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9484 * |[1:0] |OPMODE |IO Operation Mode
AnnaBridge 171:3a7713b1edbc 9485 * | | |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
AnnaBridge 171:3a7713b1edbc 9486 * | | |01 = TAMPER (PF.2) is output push pull mode.
AnnaBridge 171:3a7713b1edbc 9487 * | | |10 = TAMPER (PF.2) is open drain mode.
AnnaBridge 171:3a7713b1edbc 9488 * | | |11 = TAMPER (PF.2) is input only mode with internal pull up.
AnnaBridge 171:3a7713b1edbc 9489 * |[2] |DOUT |IO Output Data
AnnaBridge 171:3a7713b1edbc 9490 * | | |0 = TAMPER (PF.2) output low.
AnnaBridge 171:3a7713b1edbc 9491 * | | |1 = TAMPER (PF.2) output high.
AnnaBridge 171:3a7713b1edbc 9492 * |[3] |CTLSEL |IO Pin State Backup Selection
AnnaBridge 171:3a7713b1edbc 9493 * | | |When tamper function is disabled, TAMPER pin can be used as GPIO function.
AnnaBridge 171:3a7713b1edbc 9494 * | | |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
AnnaBridge 171:3a7713b1edbc 9495 * | | |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
AnnaBridge 171:3a7713b1edbc 9496 * | | |It becomes floating state when system power is turned off.
AnnaBridge 171:3a7713b1edbc 9497 * | | |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
AnnaBridge 171:3a7713b1edbc 9498 * | | |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
AnnaBridge 171:3a7713b1edbc 9499 * | | |I/O pin state keeps previous state after system power is turned off.
AnnaBridge 171:3a7713b1edbc 9500 */
AnnaBridge 171:3a7713b1edbc 9501
AnnaBridge 171:3a7713b1edbc 9502 __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
AnnaBridge 171:3a7713b1edbc 9503 __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
AnnaBridge 171:3a7713b1edbc 9504 __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
AnnaBridge 171:3a7713b1edbc 9505 __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
AnnaBridge 171:3a7713b1edbc 9506 __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
AnnaBridge 171:3a7713b1edbc 9507 __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
AnnaBridge 171:3a7713b1edbc 9508 __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
AnnaBridge 171:3a7713b1edbc 9509 __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 9510 __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
AnnaBridge 171:3a7713b1edbc 9511 __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
AnnaBridge 171:3a7713b1edbc 9512 __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 9513 __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
AnnaBridge 171:3a7713b1edbc 9514 __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
AnnaBridge 171:3a7713b1edbc 9515 __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
AnnaBridge 171:3a7713b1edbc 9516 __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
AnnaBridge 171:3a7713b1edbc 9517 __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
AnnaBridge 171:3a7713b1edbc 9518 __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
AnnaBridge 171:3a7713b1edbc 9519 __I uint32_t RESERVE0[28];
AnnaBridge 171:3a7713b1edbc 9520 __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
AnnaBridge 171:3a7713b1edbc 9521 __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
AnnaBridge 171:3a7713b1edbc 9522 __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
AnnaBridge 171:3a7713b1edbc 9523 __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
AnnaBridge 171:3a7713b1edbc 9524
AnnaBridge 171:3a7713b1edbc 9525 } RTC_T;
AnnaBridge 171:3a7713b1edbc 9526
AnnaBridge 171:3a7713b1edbc 9527
AnnaBridge 171:3a7713b1edbc 9528
AnnaBridge 171:3a7713b1edbc 9529 /**
AnnaBridge 171:3a7713b1edbc 9530 @addtogroup RTC_CONST RTC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 9531 Constant Definitions for RTC Controller
AnnaBridge 171:3a7713b1edbc 9532 @{ */
AnnaBridge 171:3a7713b1edbc 9533
AnnaBridge 171:3a7713b1edbc 9534 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 9535 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 9536
AnnaBridge 171:3a7713b1edbc 9537 #define RTC_INIT_INIT_Pos (0) /*!< RTC_T::INIT: INIT Position */
AnnaBridge 171:3a7713b1edbc 9538 #define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
AnnaBridge 171:3a7713b1edbc 9539
AnnaBridge 171:3a7713b1edbc 9540 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
AnnaBridge 171:3a7713b1edbc 9541 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
AnnaBridge 171:3a7713b1edbc 9542
AnnaBridge 171:3a7713b1edbc 9543 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
AnnaBridge 171:3a7713b1edbc 9544 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
AnnaBridge 171:3a7713b1edbc 9545
AnnaBridge 171:3a7713b1edbc 9546 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
AnnaBridge 171:3a7713b1edbc 9547 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
AnnaBridge 171:3a7713b1edbc 9548
AnnaBridge 171:3a7713b1edbc 9549 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
AnnaBridge 171:3a7713b1edbc 9550 #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
AnnaBridge 171:3a7713b1edbc 9551
AnnaBridge 171:3a7713b1edbc 9552 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
AnnaBridge 171:3a7713b1edbc 9553 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
AnnaBridge 171:3a7713b1edbc 9554
AnnaBridge 171:3a7713b1edbc 9555 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
AnnaBridge 171:3a7713b1edbc 9556 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
AnnaBridge 171:3a7713b1edbc 9557
AnnaBridge 171:3a7713b1edbc 9558 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
AnnaBridge 171:3a7713b1edbc 9559 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
AnnaBridge 171:3a7713b1edbc 9560
AnnaBridge 171:3a7713b1edbc 9561 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
AnnaBridge 171:3a7713b1edbc 9562 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
AnnaBridge 171:3a7713b1edbc 9563
AnnaBridge 171:3a7713b1edbc 9564 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
AnnaBridge 171:3a7713b1edbc 9565 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
AnnaBridge 171:3a7713b1edbc 9566
AnnaBridge 171:3a7713b1edbc 9567 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
AnnaBridge 171:3a7713b1edbc 9568 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
AnnaBridge 171:3a7713b1edbc 9569
AnnaBridge 171:3a7713b1edbc 9570 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
AnnaBridge 171:3a7713b1edbc 9571 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
AnnaBridge 171:3a7713b1edbc 9572
AnnaBridge 171:3a7713b1edbc 9573 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
AnnaBridge 171:3a7713b1edbc 9574 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
AnnaBridge 171:3a7713b1edbc 9575
AnnaBridge 171:3a7713b1edbc 9576 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
AnnaBridge 171:3a7713b1edbc 9577 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
AnnaBridge 171:3a7713b1edbc 9578
AnnaBridge 171:3a7713b1edbc 9579 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
AnnaBridge 171:3a7713b1edbc 9580 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
AnnaBridge 171:3a7713b1edbc 9581
AnnaBridge 171:3a7713b1edbc 9582 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
AnnaBridge 171:3a7713b1edbc 9583 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
AnnaBridge 171:3a7713b1edbc 9584
AnnaBridge 171:3a7713b1edbc 9585 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
AnnaBridge 171:3a7713b1edbc 9586 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
AnnaBridge 171:3a7713b1edbc 9587
AnnaBridge 171:3a7713b1edbc 9588 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
AnnaBridge 171:3a7713b1edbc 9589 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
AnnaBridge 171:3a7713b1edbc 9590
AnnaBridge 171:3a7713b1edbc 9591 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
AnnaBridge 171:3a7713b1edbc 9592 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
AnnaBridge 171:3a7713b1edbc 9593
AnnaBridge 171:3a7713b1edbc 9594 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
AnnaBridge 171:3a7713b1edbc 9595 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
AnnaBridge 171:3a7713b1edbc 9596
AnnaBridge 171:3a7713b1edbc 9597 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
AnnaBridge 171:3a7713b1edbc 9598 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
AnnaBridge 171:3a7713b1edbc 9599
AnnaBridge 171:3a7713b1edbc 9600 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
AnnaBridge 171:3a7713b1edbc 9601 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
AnnaBridge 171:3a7713b1edbc 9602
AnnaBridge 171:3a7713b1edbc 9603 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
AnnaBridge 171:3a7713b1edbc 9604 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
AnnaBridge 171:3a7713b1edbc 9605
AnnaBridge 171:3a7713b1edbc 9606 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
AnnaBridge 171:3a7713b1edbc 9607 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
AnnaBridge 171:3a7713b1edbc 9608
AnnaBridge 171:3a7713b1edbc 9609 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
AnnaBridge 171:3a7713b1edbc 9610 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
AnnaBridge 171:3a7713b1edbc 9611
AnnaBridge 171:3a7713b1edbc 9612 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
AnnaBridge 171:3a7713b1edbc 9613 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
AnnaBridge 171:3a7713b1edbc 9614
AnnaBridge 171:3a7713b1edbc 9615 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
AnnaBridge 171:3a7713b1edbc 9616 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
AnnaBridge 171:3a7713b1edbc 9617
AnnaBridge 171:3a7713b1edbc 9618 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
AnnaBridge 171:3a7713b1edbc 9619 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
AnnaBridge 171:3a7713b1edbc 9620
AnnaBridge 171:3a7713b1edbc 9621 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
AnnaBridge 171:3a7713b1edbc 9622 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
AnnaBridge 171:3a7713b1edbc 9623
AnnaBridge 171:3a7713b1edbc 9624 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
AnnaBridge 171:3a7713b1edbc 9625 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
AnnaBridge 171:3a7713b1edbc 9626
AnnaBridge 171:3a7713b1edbc 9627 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
AnnaBridge 171:3a7713b1edbc 9628 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
AnnaBridge 171:3a7713b1edbc 9629
AnnaBridge 171:3a7713b1edbc 9630 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
AnnaBridge 171:3a7713b1edbc 9631 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
AnnaBridge 171:3a7713b1edbc 9632
AnnaBridge 171:3a7713b1edbc 9633 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
AnnaBridge 171:3a7713b1edbc 9634 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
AnnaBridge 171:3a7713b1edbc 9635
AnnaBridge 171:3a7713b1edbc 9636 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
AnnaBridge 171:3a7713b1edbc 9637 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
AnnaBridge 171:3a7713b1edbc 9638
AnnaBridge 171:3a7713b1edbc 9639 #define RTC_INTEN_SNPDIEN_Pos (2) /*!< RTC_T::INTEN: SNPDIEN Position */
AnnaBridge 171:3a7713b1edbc 9640 #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) /*!< RTC_T::INTEN: SNPDIEN Mask */
AnnaBridge 171:3a7713b1edbc 9641
AnnaBridge 171:3a7713b1edbc 9642 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
AnnaBridge 171:3a7713b1edbc 9643 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
AnnaBridge 171:3a7713b1edbc 9644
AnnaBridge 171:3a7713b1edbc 9645 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
AnnaBridge 171:3a7713b1edbc 9646 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
AnnaBridge 171:3a7713b1edbc 9647
AnnaBridge 171:3a7713b1edbc 9648 #define RTC_INTSTS_SNPDIF_Pos (2) /*!< RTC_T::INTSTS: SNPDIF Position */
AnnaBridge 171:3a7713b1edbc 9649 #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) /*!< RTC_T::INTSTS: SNPDIF Mask */
AnnaBridge 171:3a7713b1edbc 9650
AnnaBridge 171:3a7713b1edbc 9651 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
AnnaBridge 171:3a7713b1edbc 9652 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
AnnaBridge 171:3a7713b1edbc 9653
AnnaBridge 171:3a7713b1edbc 9654 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
AnnaBridge 171:3a7713b1edbc 9655 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
AnnaBridge 171:3a7713b1edbc 9656
AnnaBridge 171:3a7713b1edbc 9657 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
AnnaBridge 171:3a7713b1edbc 9658 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
AnnaBridge 171:3a7713b1edbc 9659
AnnaBridge 171:3a7713b1edbc 9660 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
AnnaBridge 171:3a7713b1edbc 9661 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
AnnaBridge 171:3a7713b1edbc 9662
AnnaBridge 171:3a7713b1edbc 9663 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
AnnaBridge 171:3a7713b1edbc 9664 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
AnnaBridge 171:3a7713b1edbc 9665
AnnaBridge 171:3a7713b1edbc 9666 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
AnnaBridge 171:3a7713b1edbc 9667 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
AnnaBridge 171:3a7713b1edbc 9668
AnnaBridge 171:3a7713b1edbc 9669 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
AnnaBridge 171:3a7713b1edbc 9670 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
AnnaBridge 171:3a7713b1edbc 9671
AnnaBridge 171:3a7713b1edbc 9672 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
AnnaBridge 171:3a7713b1edbc 9673 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
AnnaBridge 171:3a7713b1edbc 9674
AnnaBridge 171:3a7713b1edbc 9675 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
AnnaBridge 171:3a7713b1edbc 9676 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
AnnaBridge 171:3a7713b1edbc 9677
AnnaBridge 171:3a7713b1edbc 9678 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
AnnaBridge 171:3a7713b1edbc 9679 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
AnnaBridge 171:3a7713b1edbc 9680
AnnaBridge 171:3a7713b1edbc 9681 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
AnnaBridge 171:3a7713b1edbc 9682 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
AnnaBridge 171:3a7713b1edbc 9683
AnnaBridge 171:3a7713b1edbc 9684 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
AnnaBridge 171:3a7713b1edbc 9685 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
AnnaBridge 171:3a7713b1edbc 9686
AnnaBridge 171:3a7713b1edbc 9687 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
AnnaBridge 171:3a7713b1edbc 9688 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
AnnaBridge 171:3a7713b1edbc 9689
AnnaBridge 171:3a7713b1edbc 9690 #define RTC_SPRCTL_SNPDEN_Pos (0) /*!< RTC_T::SPRCTL: SNPDEN Position */
AnnaBridge 171:3a7713b1edbc 9691 #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) /*!< RTC_T::SPRCTL: SNPDEN Mask */
AnnaBridge 171:3a7713b1edbc 9692
AnnaBridge 171:3a7713b1edbc 9693 #define RTC_SPRCTL_SNPTYPE0_Pos (1) /*!< RTC_T::SPRCTL: SNPTYPE0 Position */
AnnaBridge 171:3a7713b1edbc 9694 #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) /*!< RTC_T::SPRCTL: SNPTYPE0 Mask */
AnnaBridge 171:3a7713b1edbc 9695
AnnaBridge 171:3a7713b1edbc 9696 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
AnnaBridge 171:3a7713b1edbc 9697 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
AnnaBridge 171:3a7713b1edbc 9698
AnnaBridge 171:3a7713b1edbc 9699 #define RTC_SPRCTL_SNPTYPE1_Pos (3) /*!< RTC_T::SPRCTL: SNPTYPE1 Position */
AnnaBridge 171:3a7713b1edbc 9700 #define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) /*!< RTC_T::SPRCTL: SNPTYPE1 Mask */
AnnaBridge 171:3a7713b1edbc 9701
AnnaBridge 171:3a7713b1edbc 9702 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
AnnaBridge 171:3a7713b1edbc 9703 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
AnnaBridge 171:3a7713b1edbc 9704
AnnaBridge 171:3a7713b1edbc 9705 #define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRWRDY Position */
AnnaBridge 171:3a7713b1edbc 9706 #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC_T::SPRCTL: SPRRWRDY Mask */
AnnaBridge 171:3a7713b1edbc 9707
AnnaBridge 171:3a7713b1edbc 9708 #define RTC_SPR_SPARE_Pos (0) /*!< RTC_T::SPR: SPARE Position */
AnnaBridge 171:3a7713b1edbc 9709 #define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) /*!< RTC_T::SPR: SPARE Mask */
AnnaBridge 171:3a7713b1edbc 9710
AnnaBridge 171:3a7713b1edbc 9711 #define RTC_LXTCTL_LXTEN_Pos (0) /*!< RTC_T::LXTCTL: LXTEN Position */
AnnaBridge 171:3a7713b1edbc 9712 #define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) /*!< RTC_T::LXTCTL: LXTEN Mask */
AnnaBridge 171:3a7713b1edbc 9713
AnnaBridge 171:3a7713b1edbc 9714 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
AnnaBridge 171:3a7713b1edbc 9715 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
AnnaBridge 171:3a7713b1edbc 9716
AnnaBridge 171:3a7713b1edbc 9717 #define RTC_LXTOCTL_OPMODE_Pos (0) /*!< RTC_T::LXTOCTL: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 9718 #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) /*!< RTC_T::LXTOCTL: OPMODE Mask */
AnnaBridge 171:3a7713b1edbc 9719
AnnaBridge 171:3a7713b1edbc 9720 #define RTC_LXTOCTL_DOUT_Pos (2) /*!< RTC_T::LXTOCTL: DOUT Position */
AnnaBridge 171:3a7713b1edbc 9721 #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) /*!< RTC_T::LXTOCTL: DOUT Mask */
AnnaBridge 171:3a7713b1edbc 9722
AnnaBridge 171:3a7713b1edbc 9723 #define RTC_LXTOCTL_CTLSEL_Pos (3) /*!< RTC_T::LXTOCTL: CTLSEL Position */
AnnaBridge 171:3a7713b1edbc 9724 #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) /*!< RTC_T::LXTOCTL: CTLSEL Mask */
AnnaBridge 171:3a7713b1edbc 9725
AnnaBridge 171:3a7713b1edbc 9726 #define RTC_LXTICTL_OPMODE_Pos (0) /*!< RTC_T::LXTICTL: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 9727 #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) /*!< RTC_T::LXTICTL: OPMODE Mask */
AnnaBridge 171:3a7713b1edbc 9728
AnnaBridge 171:3a7713b1edbc 9729 #define RTC_LXTICTL_DOUT_Pos (2) /*!< RTC_T::LXTICTL: DOUT Position */
AnnaBridge 171:3a7713b1edbc 9730 #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) /*!< RTC_T::LXTICTL: DOUT Mask */
AnnaBridge 171:3a7713b1edbc 9731
AnnaBridge 171:3a7713b1edbc 9732 #define RTC_LXTICTL_CTLSEL_Pos (3) /*!< RTC_T::LXTICTL: CTLSEL Position */
AnnaBridge 171:3a7713b1edbc 9733 #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) /*!< RTC_T::LXTICTL: CTLSEL Mask */
AnnaBridge 171:3a7713b1edbc 9734
AnnaBridge 171:3a7713b1edbc 9735 #define RTC_TAMPCTL_OPMODE_Pos (0) /*!< RTC_T::TAMPCTL: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 9736 #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) /*!< RTC_T::TAMPCTL: OPMODE Mask */
AnnaBridge 171:3a7713b1edbc 9737
AnnaBridge 171:3a7713b1edbc 9738 #define RTC_TAMPCTL_DOUT_Pos (2) /*!< RTC_T::TAMPCTL: DOUT Position */
AnnaBridge 171:3a7713b1edbc 9739 #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) /*!< RTC_T::TAMPCTL: DOUT Mask */
AnnaBridge 171:3a7713b1edbc 9740
AnnaBridge 171:3a7713b1edbc 9741 #define RTC_TAMPCTL_CTLSEL_Pos (3) /*!< RTC_T::TAMPCTL: CTLSEL Position */
AnnaBridge 171:3a7713b1edbc 9742 #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /*!< RTC_T::TAMPCTL: CTLSEL Mask */
AnnaBridge 171:3a7713b1edbc 9743
AnnaBridge 171:3a7713b1edbc 9744 /**@}*/ /* RTC_CONST */
AnnaBridge 171:3a7713b1edbc 9745 /**@}*/ /* end of RTC register group */
AnnaBridge 171:3a7713b1edbc 9746
AnnaBridge 171:3a7713b1edbc 9747
AnnaBridge 171:3a7713b1edbc 9748 /*---------------------- Smart Card Host Interface Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 9749 /**
AnnaBridge 171:3a7713b1edbc 9750 @addtogroup SC Smart Card Host Interface Controller(SC)
AnnaBridge 171:3a7713b1edbc 9751 Memory Mapped Structure for SC Controller
AnnaBridge 171:3a7713b1edbc 9752 @{ */
AnnaBridge 171:3a7713b1edbc 9753
AnnaBridge 171:3a7713b1edbc 9754
AnnaBridge 171:3a7713b1edbc 9755 typedef struct
AnnaBridge 171:3a7713b1edbc 9756 {
AnnaBridge 171:3a7713b1edbc 9757
AnnaBridge 171:3a7713b1edbc 9758
AnnaBridge 171:3a7713b1edbc 9759 /**
AnnaBridge 171:3a7713b1edbc 9760 * @var SC_T::DAT
AnnaBridge 171:3a7713b1edbc 9761 * Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.
AnnaBridge 171:3a7713b1edbc 9762 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9763 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9764 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9765 * |[7:0] |DAT |Receiving/ Transmit Holding Buffer
AnnaBridge 171:3a7713b1edbc 9766 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 9767 * | | |By writing data to DAT, the SC will send out an 8-bit data.
AnnaBridge 171:3a7713b1edbc 9768 * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9769 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 9770 * | | |By reading DAT, the SC will return an 8-bit received data.
AnnaBridge 171:3a7713b1edbc 9771 * @var SC_T::CTL
AnnaBridge 171:3a7713b1edbc 9772 * Offset: 0x04 SC Control Register.
AnnaBridge 171:3a7713b1edbc 9773 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9774 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9775 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9776 * |[0] |SCEN |SC Engine Enable Bit
AnnaBridge 171:3a7713b1edbc 9777 * | | |Set this bit to 1 to enable SC operation.
AnnaBridge 171:3a7713b1edbc 9778 * | | |If this bit is cleared, SC will force all transition to IDLE state.
AnnaBridge 171:3a7713b1edbc 9779 * |[1] |RXOFF |RX Transition Disable Control
AnnaBridge 171:3a7713b1edbc 9780 * | | |0 = The receiver Enabled.
AnnaBridge 171:3a7713b1edbc 9781 * | | |1 = The receiver Disabled.
AnnaBridge 171:3a7713b1edbc 9782 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9783 * | | |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
AnnaBridge 171:3a7713b1edbc 9784 * |[2] |TXOFF |TX Transition Disable Control
AnnaBridge 171:3a7713b1edbc 9785 * | | |0 = The transceiver Enabled.
AnnaBridge 171:3a7713b1edbc 9786 * | | |1 = The transceiver Disabled.
AnnaBridge 171:3a7713b1edbc 9787 * |[3] |AUTOCEN |Auto Convention Enable Bit
AnnaBridge 171:3a7713b1edbc 9788 * | | |0 = Auto-convention Disabled.
AnnaBridge 171:3a7713b1edbc 9789 * | | |1 = Auto-convention Enabled.
AnnaBridge 171:3a7713b1edbc 9790 * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
AnnaBridge 171:3a7713b1edbc 9791 * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
AnnaBridge 171:3a7713b1edbc 9792 * | | |After hardware received first data and stored it at buffer,
AnnaBridge 171:3a7713b1edbc 9793 * | | |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
AnnaBridge 171:3a7713b1edbc 9794 * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
AnnaBridge 171:3a7713b1edbc 9795 * |[5:4] |CONSEL |Convention Selection
AnnaBridge 171:3a7713b1edbc 9796 * | | |00 = Direct convention.
AnnaBridge 171:3a7713b1edbc 9797 * | | |01 = Reserved.
AnnaBridge 171:3a7713b1edbc 9798 * | | |10 = Reserved.
AnnaBridge 171:3a7713b1edbc 9799 * | | |11 = Inverse convention.
AnnaBridge 171:3a7713b1edbc 9800 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9801 * | | |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
AnnaBridge 171:3a7713b1edbc 9802 * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
AnnaBridge 171:3a7713b1edbc 9803 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
AnnaBridge 171:3a7713b1edbc 9804 * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
AnnaBridge 171:3a7713b1edbc 9805 * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
AnnaBridge 171:3a7713b1edbc 9806 * | | |10 = INTR_RDA Trigger Level with 03 Bytes.
AnnaBridge 171:3a7713b1edbc 9807 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 9808 * |[12:8] |BGT |Block Guard Time (BGT)
AnnaBridge 171:3a7713b1edbc 9809 * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
AnnaBridge 171:3a7713b1edbc 9810 * | | |This field indicates the counter for the bit length of block guard time.
AnnaBridge 171:3a7713b1edbc 9811 * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
AnnaBridge 171:3a7713b1edbc 9812 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9813 * | | |The real block guard time is BGT + 1.
AnnaBridge 171:3a7713b1edbc 9814 * |[14:13] |TMRSEL |Timer Selection
AnnaBridge 171:3a7713b1edbc 9815 * | | |00 = All internal timer function Disabled.
AnnaBridge 171:3a7713b1edbc 9816 * | | |01 = Internal 24 bit timer Enabled.
AnnaBridge 171:3a7713b1edbc 9817 * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
AnnaBridge 171:3a7713b1edbc 9818 * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
AnnaBridge 171:3a7713b1edbc 9819 * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
AnnaBridge 171:3a7713b1edbc 9820 * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
AnnaBridge 171:3a7713b1edbc 9821 * | | |SC_TMRCTL2 will be ignored in this mode.
AnnaBridge 171:3a7713b1edbc 9822 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
AnnaBridge 171:3a7713b1edbc 9823 * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
AnnaBridge 171:3a7713b1edbc 9824 * |[15] |NSB |Stop Bit Length
AnnaBridge 171:3a7713b1edbc 9825 * | | |This field indicates the length of stop bit.
AnnaBridge 171:3a7713b1edbc 9826 * | | |0 = The stop bit length is 2 ETU.
AnnaBridge 171:3a7713b1edbc 9827 * | | |1= The stop bit length is 1 ETU.
AnnaBridge 171:3a7713b1edbc 9828 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9829 * | | |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
AnnaBridge 171:3a7713b1edbc 9830 * |[18:16] |RXRTY |RX Error Retry Count Number
AnnaBridge 171:3a7713b1edbc 9831 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
AnnaBridge 171:3a7713b1edbc 9832 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
AnnaBridge 171:3a7713b1edbc 9833 * | | |Note2: This field cannot be changed when RXRTYEN enabled.
AnnaBridge 171:3a7713b1edbc 9834 * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
AnnaBridge 171:3a7713b1edbc 9835 * |[19] |RXRTYEN |RX Error Retry Enable Bit
AnnaBridge 171:3a7713b1edbc 9836 * | | |This bit enables receiver retry function when parity error has occurred.
AnnaBridge 171:3a7713b1edbc 9837 * | | |0 = RX error retry function Disabled.
AnnaBridge 171:3a7713b1edbc 9838 * | | |1 = RX error retry function Enabled.
AnnaBridge 171:3a7713b1edbc 9839 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9840 * | | |Software must fill in the RXRTY value before enabling this bit.
AnnaBridge 171:3a7713b1edbc 9841 * |[22:20] |TXRTY |TX Error Retry Count Number
AnnaBridge 171:3a7713b1edbc 9842 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
AnnaBridge 171:3a7713b1edbc 9843 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
AnnaBridge 171:3a7713b1edbc 9844 * | | |Note2: This field cannot be changed when TXRTYEN enabled.
AnnaBridge 171:3a7713b1edbc 9845 * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
AnnaBridge 171:3a7713b1edbc 9846 * |[23] |TXRTYEN |TX Error Retry Enable Bit
AnnaBridge 171:3a7713b1edbc 9847 * | | |This bit enables transmitter retry function when parity error has occurred.
AnnaBridge 171:3a7713b1edbc 9848 * | | |0 = TX error retry function Disabled.
AnnaBridge 171:3a7713b1edbc 9849 * | | |1 = TX error retry function Enabled.
AnnaBridge 171:3a7713b1edbc 9850 * |[25:24] |CDDBSEL |Card Detect De-Bounce Selection
AnnaBridge 171:3a7713b1edbc 9851 * | | |This field indicates the card detect de-bounce selection.
AnnaBridge 171:3a7713b1edbc 9852 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
AnnaBridge 171:3a7713b1edbc 9853 * | | |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
AnnaBridge 171:3a7713b1edbc 9854 * | | |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
AnnaBridge 171:3a7713b1edbc 9855 * | | |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
AnnaBridge 171:3a7713b1edbc 9856 * |[26] |CDLV |Card Detect Level
AnnaBridge 171:3a7713b1edbc 9857 * | | |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
AnnaBridge 171:3a7713b1edbc 9858 * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
AnnaBridge 171:3a7713b1edbc 9859 * | | |Note: Software must select card detect level before Smart Card engine enabled.
AnnaBridge 171:3a7713b1edbc 9860 * |[30] |SYNC |SYNC Flag Indicator
AnnaBridge 171:3a7713b1edbc 9861 * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
AnnaBridge 171:3a7713b1edbc 9862 * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
AnnaBridge 171:3a7713b1edbc 9863 * | | |1 = Last value is synchronizing.
AnnaBridge 171:3a7713b1edbc 9864 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 9865 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
AnnaBridge 171:3a7713b1edbc 9866 * | | |0 = ICE debug mode acknowledgement affects SC counting.
AnnaBridge 171:3a7713b1edbc 9867 * | | |SC internal counter will be held while CPU is held by ICE.
AnnaBridge 171:3a7713b1edbc 9868 * | | |1 = ICE debug mode acknowledgement Disabled.
AnnaBridge 171:3a7713b1edbc 9869 * | | |SC internal counter will keep going no matter CPU is held by ICE or not.
AnnaBridge 171:3a7713b1edbc 9870 * @var SC_T::ALTCTL
AnnaBridge 171:3a7713b1edbc 9871 * Offset: 0x08 SC Alternate Control Register.
AnnaBridge 171:3a7713b1edbc 9872 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9873 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9874 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9875 * |[0] |TXRST |TX Software Reset
AnnaBridge 171:3a7713b1edbc 9876 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
AnnaBridge 171:3a7713b1edbc 9877 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 9878 * | | |1 = Reset the TX internal state machine and pointers.
AnnaBridge 171:3a7713b1edbc 9879 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9880 * | | |This bit will be auto cleared after reset is complete.
AnnaBridge 171:3a7713b1edbc 9881 * |[1] |RXRST |Rx Software Reset
AnnaBridge 171:3a7713b1edbc 9882 * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
AnnaBridge 171:3a7713b1edbc 9883 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 9884 * | | |1 = Reset the Rx internal state machine and pointers.
AnnaBridge 171:3a7713b1edbc 9885 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9886 * | | |This bit will be auto cleared after reset is complete.
AnnaBridge 171:3a7713b1edbc 9887 * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
AnnaBridge 171:3a7713b1edbc 9888 * | | |This bit enables SC controller to initiate the card by deactivation sequence
AnnaBridge 171:3a7713b1edbc 9889 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 9890 * | | |1 = Deactivation sequence generator Enabled.
AnnaBridge 171:3a7713b1edbc 9891 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9892 * | | |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
AnnaBridge 171:3a7713b1edbc 9893 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9894 * | | |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
AnnaBridge 171:3a7713b1edbc 9895 * | | |So don't fill this bit, TXRST, and RXRST at the same time.
AnnaBridge 171:3a7713b1edbc 9896 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9897 * | | |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9898 * |[3] |ACTEN |Activation Sequence Generator Enable Bit
AnnaBridge 171:3a7713b1edbc 9899 * | | |This bit enables SC controller to initiate the card by activation sequence
AnnaBridge 171:3a7713b1edbc 9900 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 9901 * | | |1 = Activation sequence generator Enabled.
AnnaBridge 171:3a7713b1edbc 9902 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9903 * | | |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
AnnaBridge 171:3a7713b1edbc 9904 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9905 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
AnnaBridge 171:3a7713b1edbc 9906 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9907 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9908 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
AnnaBridge 171:3a7713b1edbc 9909 * | | |This bit enables SC controller to initiate the card by warm reset sequence
AnnaBridge 171:3a7713b1edbc 9910 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 9911 * | | |1 = Warm reset sequence generator Enabled.
AnnaBridge 171:3a7713b1edbc 9912 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9913 * | | |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
AnnaBridge 171:3a7713b1edbc 9914 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9915 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
AnnaBridge 171:3a7713b1edbc 9916 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9917 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9918 * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
AnnaBridge 171:3a7713b1edbc 9919 * | | |This bit enables Timer 0 to start counting.
AnnaBridge 171:3a7713b1edbc 9920 * | | |Software can fill 0 to stop it and set 1 to reload and count.
AnnaBridge 171:3a7713b1edbc 9921 * | | |0 = Stops counting.
AnnaBridge 171:3a7713b1edbc 9922 * | | |1 = Start counting.
AnnaBridge 171:3a7713b1edbc 9923 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9924 * | | |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
AnnaBridge 171:3a7713b1edbc 9925 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9926 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
AnnaBridge 171:3a7713b1edbc 9927 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9928 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
AnnaBridge 171:3a7713b1edbc 9929 * | | |So don't fill this bit, TXRST and RXRST at the same time.
AnnaBridge 171:3a7713b1edbc 9930 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9931 * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
AnnaBridge 171:3a7713b1edbc 9932 * | | |This bit enables Timer 1 to start counting.
AnnaBridge 171:3a7713b1edbc 9933 * | | |Software can fill 0 to stop it and set 1 to reload and count.
AnnaBridge 171:3a7713b1edbc 9934 * | | |0 = Stops counting.
AnnaBridge 171:3a7713b1edbc 9935 * | | |1 = Start counting.
AnnaBridge 171:3a7713b1edbc 9936 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9937 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
AnnaBridge 171:3a7713b1edbc 9938 * | | |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
AnnaBridge 171:3a7713b1edbc 9939 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9940 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
AnnaBridge 171:3a7713b1edbc 9941 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9942 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
AnnaBridge 171:3a7713b1edbc 9943 * | | |Note4:
AnnaBridge 171:3a7713b1edbc 9944 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9945 * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
AnnaBridge 171:3a7713b1edbc 9946 * | | |This bit enables Timer 2 to start counting.
AnnaBridge 171:3a7713b1edbc 9947 * | | |Software can fill 0 to stop it and set 1 to reload and count.
AnnaBridge 171:3a7713b1edbc 9948 * | | |0 = Stops counting.
AnnaBridge 171:3a7713b1edbc 9949 * | | |1 = Start counting.
AnnaBridge 171:3a7713b1edbc 9950 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 9951 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
AnnaBridge 171:3a7713b1edbc 9952 * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
AnnaBridge 171:3a7713b1edbc 9953 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 9954 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
AnnaBridge 171:3a7713b1edbc 9955 * | | |Note3:
AnnaBridge 171:3a7713b1edbc 9956 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
AnnaBridge 171:3a7713b1edbc 9957 * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
AnnaBridge 171:3a7713b1edbc 9958 * | | |Note4:
AnnaBridge 171:3a7713b1edbc 9959 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
AnnaBridge 171:3a7713b1edbc 9960 * |[9:8] |INITSEL |Initial Timing Selection
AnnaBridge 171:3a7713b1edbc 9961 * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
AnnaBridge 171:3a7713b1edbc 9962 * | | |Unit: SC clock
AnnaBridge 171:3a7713b1edbc 9963 * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4
AnnaBridge 171:3a7713b1edbc 9964 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
AnnaBridge 171:3a7713b1edbc 9965 * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
AnnaBridge 171:3a7713b1edbc 9966 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
AnnaBridge 171:3a7713b1edbc 9967 * | | |0 = Receiver block guard time function Disabled.
AnnaBridge 171:3a7713b1edbc 9968 * | | |1 = Receiver block guard time function Enabled.
AnnaBridge 171:3a7713b1edbc 9969 * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
AnnaBridge 171:3a7713b1edbc 9970 * | | |This bit indicates the timer counter status of timer0.
AnnaBridge 171:3a7713b1edbc 9971 * | | |0 = Timer0 is not active.
AnnaBridge 171:3a7713b1edbc 9972 * | | |1 = Timer0 is active.
AnnaBridge 171:3a7713b1edbc 9973 * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
AnnaBridge 171:3a7713b1edbc 9974 * | | |This bit indicates the timer counter status of timer1.
AnnaBridge 171:3a7713b1edbc 9975 * | | |0 = Timer1 is not active.
AnnaBridge 171:3a7713b1edbc 9976 * | | |1 = Timer1 is active.
AnnaBridge 171:3a7713b1edbc 9977 * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
AnnaBridge 171:3a7713b1edbc 9978 * | | |This bit indicates the timer counter status of timer2.
AnnaBridge 171:3a7713b1edbc 9979 * | | |0 = Timer2 is not active.
AnnaBridge 171:3a7713b1edbc 9980 * | | |1 = Timer2 is active.
AnnaBridge 171:3a7713b1edbc 9981 * @var SC_T::EGT
AnnaBridge 171:3a7713b1edbc 9982 * Offset: 0x0C SC Extend Guard Time Register.
AnnaBridge 171:3a7713b1edbc 9983 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9984 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9985 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9986 * |[7:0] |EGT |Extended Guard Time
AnnaBridge 171:3a7713b1edbc 9987 * | | |This field indicates the extended guard timer value.
AnnaBridge 171:3a7713b1edbc 9988 * | | |Note:
AnnaBridge 171:3a7713b1edbc 9989 * | | |The counter is ETU base and the real extended guard time is EGT.
AnnaBridge 171:3a7713b1edbc 9990 * @var SC_T::RXTOUT
AnnaBridge 171:3a7713b1edbc 9991 * Offset: 0x10 SC Receive buffer Time-out Register.
AnnaBridge 171:3a7713b1edbc 9992 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9993 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 9994 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 9995 * |[8:0] |RFTM |SC Receiver FIFO Time-out (ETU Base)
AnnaBridge 171:3a7713b1edbc 9996 * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
AnnaBridge 171:3a7713b1edbc 9997 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
AnnaBridge 171:3a7713b1edbc 9998 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
AnnaBridge 171:3a7713b1edbc 9999 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 10000 * | | |Filling all 0 to this field indicates to disable this function.
AnnaBridge 171:3a7713b1edbc 10001 * @var SC_T::ETUCTL
AnnaBridge 171:3a7713b1edbc 10002 * Offset: 0x14 SC ETU Control Register.
AnnaBridge 171:3a7713b1edbc 10003 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10004 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10005 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10006 * |[11:0] |ETURDIV |ETU Rate Divider
AnnaBridge 171:3a7713b1edbc 10007 * | | |The field indicates the clock rate divider.
AnnaBridge 171:3a7713b1edbc 10008 * | | |The real ETU is ETURDIV + 1.
AnnaBridge 171:3a7713b1edbc 10009 * | | |Note:
AnnaBridge 171:3a7713b1edbc 10010 * | | |Software can configure this field, but this field must be greater than 0x004.
AnnaBridge 171:3a7713b1edbc 10011 * |[15] |CMPEN |Compensation Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 10012 * | | |This bit enables clock compensation function.
AnnaBridge 171:3a7713b1edbc 10013 * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
AnnaBridge 171:3a7713b1edbc 10014 * | | |0 = Compensation function Disabled.
AnnaBridge 171:3a7713b1edbc 10015 * | | |1 = Compensation function Enabled.
AnnaBridge 171:3a7713b1edbc 10016 * @var SC_T::INTEN
AnnaBridge 171:3a7713b1edbc 10017 * Offset: 0x18 SC Interrupt Enable Control Register.
AnnaBridge 171:3a7713b1edbc 10018 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10019 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10020 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10021 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10022 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
AnnaBridge 171:3a7713b1edbc 10023 * | | |0 = Receive data reach trigger level interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10024 * | | |1 = Receive data reach trigger level interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10025 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10026 * | | |This field is used for transmit buffer empty interrupt enable.
AnnaBridge 171:3a7713b1edbc 10027 * | | |0 = Transmit buffer empty interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10028 * | | |1 = Transmit buffer empty interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10029 * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10030 * | | |This field is used for transfer error interrupt enable.
AnnaBridge 171:3a7713b1edbc 10031 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
AnnaBridge 171:3a7713b1edbc 10032 * | | |0 = Transfer error interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10033 * | | |1 = Transfer error interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10034 * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10035 * | | |This field is used to enable TMR0 interrupt enable.
AnnaBridge 171:3a7713b1edbc 10036 * | | |0 = Timer0 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10037 * | | |1 = Timer0 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10038 * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10039 * | | |This field is used to enable the TMR1 interrupt.
AnnaBridge 171:3a7713b1edbc 10040 * | | |0 = Timer1 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10041 * | | |1 = Timer1 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10042 * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10043 * | | |This field is used for TMR2 interrupt enable.
AnnaBridge 171:3a7713b1edbc 10044 * | | |0 = Timer2 interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10045 * | | |1 = Timer2 interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10046 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10047 * | | |This field is used for block guard time interrupt enable.
AnnaBridge 171:3a7713b1edbc 10048 * | | |0 = Block guard time Disabled.
AnnaBridge 171:3a7713b1edbc 10049 * | | |1 = Block guard time Enabled.
AnnaBridge 171:3a7713b1edbc 10050 * |[7] |CDIEN |Card Detect Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10051 * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
AnnaBridge 171:3a7713b1edbc 10052 * | | |0 = Card detect interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10053 * | | |1 = Card detect interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10054 * |[8] |INITIEN |Initial End Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10055 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
AnnaBridge 171:3a7713b1edbc 10056 * | | |0 = Initial end interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10057 * | | |1 = Initial end interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10058 * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10059 * | | |This field is used for receiver buffer time-out interrupt enable.
AnnaBridge 171:3a7713b1edbc 10060 * | | |0 = Receiver buffer time-out interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10061 * | | |1 = Receiver buffer time-out interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10062 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10063 * | | |This field is used for auto-convention error interrupt enable.
AnnaBridge 171:3a7713b1edbc 10064 * | | |0 = Auto-convention error interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10065 * | | |1 = Auto-convention error interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10066 * @var SC_T::INTSTS
AnnaBridge 171:3a7713b1edbc 10067 * Offset: 0x1C SC Interrupt Status Register.
AnnaBridge 171:3a7713b1edbc 10068 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10069 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10070 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10071 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10072 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10073 * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
AnnaBridge 171:3a7713b1edbc 10074 * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 10075 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10076 * | | |This field is used for transmit buffer empty interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10077 * | | |Note: This field is the status flag of transmit buffer empty state.
AnnaBridge 171:3a7713b1edbc 10078 * | | |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 10079 * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10080 * | | |This field is used for transfer error interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10081 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
AnnaBridge 171:3a7713b1edbc 10082 * | | |Note: This field is the status flag of
AnnaBridge 171:3a7713b1edbc 10083 * | | |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
AnnaBridge 171:3a7713b1edbc 10084 * | | |So, if software wants to clear this bit, software must write 1 to each field.
AnnaBridge 171:3a7713b1edbc 10085 * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10086 * | | |This field is used for TMR0 interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10087 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10088 * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10089 * | | |This field is used for TMR1 interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10090 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10091 * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10092 * | | |This field is used for TMR2 interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10093 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10094 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10095 * | | |This field is used for block guard time interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10096 * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
AnnaBridge 171:3a7713b1edbc 10097 * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 10098 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10099 * | | |This field is used for card detect interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10100 * | | |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
AnnaBridge 171:3a7713b1edbc 10101 * | | |Note:
AnnaBridge 171:3a7713b1edbc 10102 * | | |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
AnnaBridge 171:3a7713b1edbc 10103 * | | |So if software wants to clear this bit, software must write 1 to this field.
AnnaBridge 171:3a7713b1edbc 10104 * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10105 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10106 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10107 * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10108 * | | |This field is used for receiver buffer time-out interrupt status flag.
AnnaBridge 171:3a7713b1edbc 10109 * | | |Note: This field is the status flag of receiver buffer time-out state.
AnnaBridge 171:3a7713b1edbc 10110 * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
AnnaBridge 171:3a7713b1edbc 10111 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10112 * | | |This field indicates auto convention sequence error.
AnnaBridge 171:3a7713b1edbc 10113 * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
AnnaBridge 171:3a7713b1edbc 10114 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10115 * @var SC_T::STATUS
AnnaBridge 171:3a7713b1edbc 10116 * Offset: 0x20 SC Status Register.
AnnaBridge 171:3a7713b1edbc 10117 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10118 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10119 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10120 * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10121 * | | |This bit is set when RX buffer overflow.
AnnaBridge 171:3a7713b1edbc 10122 * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
AnnaBridge 171:3a7713b1edbc 10123 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10124 * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
AnnaBridge 171:3a7713b1edbc 10125 * | | |This bit indicates RX buffer empty or not.
AnnaBridge 171:3a7713b1edbc 10126 * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
AnnaBridge 171:3a7713b1edbc 10127 * | | |It will be cleared when SC receives any new data.
AnnaBridge 171:3a7713b1edbc 10128 * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10129 * | | |This bit indicates RX buffer full or not.
AnnaBridge 171:3a7713b1edbc 10130 * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
AnnaBridge 171:3a7713b1edbc 10131 * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10132 * | | |This bit is set to logic 1 whenever the received character does not have a valid
AnnaBridge 171:3a7713b1edbc 10133 * | | |"parity bit".
AnnaBridge 171:3a7713b1edbc 10134 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 10135 * | | |This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10136 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 10137 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
AnnaBridge 171:3a7713b1edbc 10138 * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10139 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
AnnaBridge 171:3a7713b1edbc 10140 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 10141 * | | |This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10142 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 10143 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
AnnaBridge 171:3a7713b1edbc 10144 * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10145 * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
AnnaBridge 171:3a7713b1edbc 10146 * | | |.
AnnaBridge 171:3a7713b1edbc 10147 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 10148 * | | |This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10149 * | | |Note2:
AnnaBridge 171:3a7713b1edbc 10150 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
AnnaBridge 171:3a7713b1edbc 10151 * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10152 * | | |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
AnnaBridge 171:3a7713b1edbc 10153 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10154 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10155 * | | |This bit indicates TX buffer empty or not.
AnnaBridge 171:3a7713b1edbc 10156 * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
AnnaBridge 171:3a7713b1edbc 10157 * | | |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
AnnaBridge 171:3a7713b1edbc 10158 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10159 * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
AnnaBridge 171:3a7713b1edbc 10160 * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
AnnaBridge 171:3a7713b1edbc 10161 * | | |This bit is set whenever card has been removal.
AnnaBridge 171:3a7713b1edbc 10162 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10163 * | | |1 = Card removed.
AnnaBridge 171:3a7713b1edbc 10164 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 10165 * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
AnnaBridge 171:3a7713b1edbc 10166 * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
AnnaBridge 171:3a7713b1edbc 10167 * | | |This bit is set whenever card has been inserted.
AnnaBridge 171:3a7713b1edbc 10168 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10169 * | | |1 = Card insert.
AnnaBridge 171:3a7713b1edbc 10170 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 10171 * | | |Note2: The
AnnaBridge 171:3a7713b1edbc 10172 * | | |card detect engine will start after SCEN (SC_CTL[0]) set.
AnnaBridge 171:3a7713b1edbc 10173 * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
AnnaBridge 171:3a7713b1edbc 10174 * | | |This bit is the pin status flag of SC_CD
AnnaBridge 171:3a7713b1edbc 10175 * | | |0 = The SC_CD pin state at low.
AnnaBridge 171:3a7713b1edbc 10176 * | | |1 = The SC_CD pin state at high.
AnnaBridge 171:3a7713b1edbc 10177 * |[17:16] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10178 * | | |This field indicates the RX buffer pointer status flag.
AnnaBridge 171:3a7713b1edbc 10179 * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
AnnaBridge 171:3a7713b1edbc 10180 * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
AnnaBridge 171:3a7713b1edbc 10181 * |[21] |RXRERR |Receiver Retry Error (Read Only)
AnnaBridge 171:3a7713b1edbc 10182 * | | |This bit is set by hardware when RX has any error and retries transfer.
AnnaBridge 171:3a7713b1edbc 10183 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10184 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 10185 * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
AnnaBridge 171:3a7713b1edbc 10186 * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
AnnaBridge 171:3a7713b1edbc 10187 * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
AnnaBridge 171:3a7713b1edbc 10188 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10189 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
AnnaBridge 171:3a7713b1edbc 10190 * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10191 * | | |This bit is set by hardware when RX transfer is in active.
AnnaBridge 171:3a7713b1edbc 10192 * | | |This bit is cleared automatically when RX transfer is finished.
AnnaBridge 171:3a7713b1edbc 10193 * |[25:24] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10194 * | | |This field indicates the TX buffer pointer status flag.
AnnaBridge 171:3a7713b1edbc 10195 * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
AnnaBridge 171:3a7713b1edbc 10196 * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
AnnaBridge 171:3a7713b1edbc 10197 * |[29] |TXRERR |Transmitter Retry Error (Read Only)
AnnaBridge 171:3a7713b1edbc 10198 * | | |This bit is set by hardware when transmitter re-transmits.
AnnaBridge 171:3a7713b1edbc 10199 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10200 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 10201 * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
AnnaBridge 171:3a7713b1edbc 10202 * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
AnnaBridge 171:3a7713b1edbc 10203 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10204 * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10205 * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
AnnaBridge 171:3a7713b1edbc 10206 * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
AnnaBridge 171:3a7713b1edbc 10207 * @var SC_T::PINCTL
AnnaBridge 171:3a7713b1edbc 10208 * Offset: 0x24 SC Pin Control State Register.
AnnaBridge 171:3a7713b1edbc 10209 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10210 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10211 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10212 * |[0] |PWREN |SC_PWREN Pin Signal
AnnaBridge 171:3a7713b1edbc 10213 * | | |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
AnnaBridge 171:3a7713b1edbc 10214 * | | |Write this field to drive SC_PWR pin
AnnaBridge 171:3a7713b1edbc 10215 * | | |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
AnnaBridge 171:3a7713b1edbc 10216 * | | |Read this field to get SC_PWR pin status.
AnnaBridge 171:3a7713b1edbc 10217 * | | |0 = SC_PWR pin status is low.
AnnaBridge 171:3a7713b1edbc 10218 * | | |1 = SC_PWR pin status is high.
AnnaBridge 171:3a7713b1edbc 10219 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10220 * | | |So don't fill this field when operating in these modes.
AnnaBridge 171:3a7713b1edbc 10221 * |[1] |SCRST |SC_RST Pin Signal
AnnaBridge 171:3a7713b1edbc 10222 * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
AnnaBridge 171:3a7713b1edbc 10223 * | | |Write this field to drive SC_RST pin.
AnnaBridge 171:3a7713b1edbc 10224 * | | |0 = Drive SC_RST pin to low.
AnnaBridge 171:3a7713b1edbc 10225 * | | |1 = Drive SC_RST pin to high.
AnnaBridge 171:3a7713b1edbc 10226 * | | |Read this field to get SC_RST pin status.
AnnaBridge 171:3a7713b1edbc 10227 * | | |0 = SC_RST pin status is low.
AnnaBridge 171:3a7713b1edbc 10228 * | | |1 = SC_RST pin status is high.
AnnaBridge 171:3a7713b1edbc 10229 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10230 * | | |So don't fill this field when operating in these modes.
AnnaBridge 171:3a7713b1edbc 10231 * |[5] |CSTOPLV |SC Clock Stop Level
AnnaBridge 171:3a7713b1edbc 10232 * | | |This field indicates the clock polarity control in clock stop mode.
AnnaBridge 171:3a7713b1edbc 10233 * | | |0 = SC_CLK stopped in low level.
AnnaBridge 171:3a7713b1edbc 10234 * | | |1 = SC_CLK stopped in high level.
AnnaBridge 171:3a7713b1edbc 10235 * |[6] |CLKKEEP |SC Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 10236 * | | |0 = SC clock generation Disabled.
AnnaBridge 171:3a7713b1edbc 10237 * | | |1 = SC clock always keeps free running.
AnnaBridge 171:3a7713b1edbc 10238 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10239 * | | |So don't fill this field when operating in these modes.
AnnaBridge 171:3a7713b1edbc 10240 * |[9] |SCDOUT |SC Data Output Pin
AnnaBridge 171:3a7713b1edbc 10241 * | | |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
AnnaBridge 171:3a7713b1edbc 10242 * | | |0 = Drive SCDATOUT pin to low.
AnnaBridge 171:3a7713b1edbc 10243 * | | |1 = Drive SCDATOUT pin to high.
AnnaBridge 171:3a7713b1edbc 10244 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10245 * | | |So don't fill this field when SC is in these modes.
AnnaBridge 171:3a7713b1edbc 10246 * |[11] |PWRINV |SC_POW Pin Inverse
AnnaBridge 171:3a7713b1edbc 10247 * | | |This bit is used for inverse the SC_POW pin.
AnnaBridge 171:3a7713b1edbc 10248 * | | |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
AnnaBridge 171:3a7713b1edbc 10249 * | | |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
AnnaBridge 171:3a7713b1edbc 10250 * | | |00 = SC_POW_ Pin is 0.
AnnaBridge 171:3a7713b1edbc 10251 * | | |01 = SC_POW _Pin is 1.
AnnaBridge 171:3a7713b1edbc 10252 * | | |10 = SC_POW _Pin is 1.
AnnaBridge 171:3a7713b1edbc 10253 * | | |11 = SC_POW_ Pin is 0.
AnnaBridge 171:3a7713b1edbc 10254 * | | |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
AnnaBridge 171:3a7713b1edbc 10255 * |[12] |SCDOSTS |SC Data Pin Output Status
AnnaBridge 171:3a7713b1edbc 10256 * | | |This bit is the pin status of SCDATOUT
AnnaBridge 171:3a7713b1edbc 10257 * | | |0 = SCDATOUT pin to low.
AnnaBridge 171:3a7713b1edbc 10258 * | | |1 = SCDATOUT pin to high.
AnnaBridge 171:3a7713b1edbc 10259 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10260 * | | |This bit is not allowed to program when SC is operated at these modes.
AnnaBridge 171:3a7713b1edbc 10261 * |[16] |DATSTS |This bit is the pin status of SC_DAT
AnnaBridge 171:3a7713b1edbc 10262 * | | |0 = The SC_DAT pin is low.
AnnaBridge 171:3a7713b1edbc 10263 * | | |1 = The SC_DAT pin is high.
AnnaBridge 171:3a7713b1edbc 10264 * |[17] |PWRSTS |SC_PWR Pin Signal
AnnaBridge 171:3a7713b1edbc 10265 * | | |This bit is the pin status of SC_PWR
AnnaBridge 171:3a7713b1edbc 10266 * | | |0 = SC_PWR pin to low.
AnnaBridge 171:3a7713b1edbc 10267 * | | |1 = SC_PWR pin to high.
AnnaBridge 171:3a7713b1edbc 10268 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10269 * | | |This bit is not allowed to program when SC is operated at these modes.
AnnaBridge 171:3a7713b1edbc 10270 * |[18] |RSTSTS |SCRST Pin Signals
AnnaBridge 171:3a7713b1edbc 10271 * | | |This bit is the pin status of SC_RST
AnnaBridge 171:3a7713b1edbc 10272 * | | |0 = SC_RST pin is low.
AnnaBridge 171:3a7713b1edbc 10273 * | | |1 = SC_RST pin is high.
AnnaBridge 171:3a7713b1edbc 10274 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
AnnaBridge 171:3a7713b1edbc 10275 * | | |This bit is not allowed to program when SC is operated at these modes.
AnnaBridge 171:3a7713b1edbc 10276 * |[30] |SYNC |SYNC Flag Indicator
AnnaBridge 171:3a7713b1edbc 10277 * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
AnnaBridge 171:3a7713b1edbc 10278 * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
AnnaBridge 171:3a7713b1edbc 10279 * | | |1 = Last value is synchronizing.
AnnaBridge 171:3a7713b1edbc 10280 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 10281 * |[31] |LOOPBK |Loop Back Test
AnnaBridge 171:3a7713b1edbc 10282 * | | |0 = loop back test Disabled.
AnnaBridge 171:3a7713b1edbc 10283 * | | |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
AnnaBridge 171:3a7713b1edbc 10284 * @var SC_T::TMRCTL0
AnnaBridge 171:3a7713b1edbc 10285 * Offset: 0x28 SC Internal Timer Control Register 0.
AnnaBridge 171:3a7713b1edbc 10286 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10287 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10288 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10289 * |[23:0] |CNT |Timer 0 Counter Value (ETU Base)
AnnaBridge 171:3a7713b1edbc 10290 * | | |This field indicates the internal timer operation values.
AnnaBridge 171:3a7713b1edbc 10291 * |[27:24] |OPMODE |Timer 0 Operation Mode Selection
AnnaBridge 171:3a7713b1edbc 10292 * | | |This field indicates the internal 24-bit timer operation selection.
AnnaBridge 171:3a7713b1edbc 10293 * | | |Refer to 6.17.5.4 for programming Timer0
AnnaBridge 171:3a7713b1edbc 10294 * @var SC_T::TMRCTL1
AnnaBridge 171:3a7713b1edbc 10295 * Offset: 0x2C SC Internal Timer Control Register 1.
AnnaBridge 171:3a7713b1edbc 10296 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10297 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10298 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10299 * |[7:0] |CNT |Timer 1 Counter Value (ETU Base)
AnnaBridge 171:3a7713b1edbc 10300 * | | |This field indicates the internal timer operation values.
AnnaBridge 171:3a7713b1edbc 10301 * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
AnnaBridge 171:3a7713b1edbc 10302 * | | |This field indicates the internal 8-bit timer operation selection.
AnnaBridge 171:3a7713b1edbc 10303 * | | |Refer to 6.17.5.4 for programming Timer1
AnnaBridge 171:3a7713b1edbc 10304 * @var SC_T::TMRCTL2
AnnaBridge 171:3a7713b1edbc 10305 * Offset: 0x30 SC Internal Timer Control Register 2.
AnnaBridge 171:3a7713b1edbc 10306 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10307 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10308 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10309 * |[7:0] |CNT |Timer 2 Counter Value (ETU Base)
AnnaBridge 171:3a7713b1edbc 10310 * | | |This field indicates the internal timer operation values.
AnnaBridge 171:3a7713b1edbc 10311 * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
AnnaBridge 171:3a7713b1edbc 10312 * | | |This field indicates the internal 8-bit timer operation selection
AnnaBridge 171:3a7713b1edbc 10313 * | | |Refer to 6.17.5.4 for programming Timer2
AnnaBridge 171:3a7713b1edbc 10314 * @var SC_T::UARTCTL
AnnaBridge 171:3a7713b1edbc 10315 * Offset: 0x34 SC UART Mode Control Register.
AnnaBridge 171:3a7713b1edbc 10316 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10317 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10318 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10319 * |[0] |UARTEN |UART Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 10320 * | | |0 = Smart Card mode.
AnnaBridge 171:3a7713b1edbc 10321 * | | |1 = UART mode.
AnnaBridge 171:3a7713b1edbc 10322 * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
AnnaBridge 171:3a7713b1edbc 10323 * | | |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
AnnaBridge 171:3a7713b1edbc 10324 * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
AnnaBridge 171:3a7713b1edbc 10325 * |[5:4] |WLS10 |Word Length Selection
AnnaBridge 171:3a7713b1edbc 10326 * | | |00 = Word length is 8 bits.
AnnaBridge 171:3a7713b1edbc 10327 * | | |01 = Word length is 7 bits.
AnnaBridge 171:3a7713b1edbc 10328 * | | |10 = Word length is 6 bits.
AnnaBridge 171:3a7713b1edbc 10329 * | | |11 = Word length is 5 bits.
AnnaBridge 171:3a7713b1edbc 10330 * | | |Note: In smart card mode, this WLS must be '00'
AnnaBridge 171:3a7713b1edbc 10331 * |[6] |PBOFF |Parity Bit Disable Control
AnnaBridge 171:3a7713b1edbc 10332 * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
AnnaBridge 171:3a7713b1edbc 10333 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
AnnaBridge 171:3a7713b1edbc 10334 * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
AnnaBridge 171:3a7713b1edbc 10335 * |[7] |OPE |Odd Parity Enable Bit
AnnaBridge 171:3a7713b1edbc 10336 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
AnnaBridge 171:3a7713b1edbc 10337 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
AnnaBridge 171:3a7713b1edbc 10338 * | | |Note: This bit has effect only when PBOFF bit is '0'.
AnnaBridge 171:3a7713b1edbc 10339 * @var SC_T::TMRDAT0
AnnaBridge 171:3a7713b1edbc 10340 * Offset: 0x38 SC Timer Current Data Register A.
AnnaBridge 171:3a7713b1edbc 10341 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10342 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10343 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10344 * |[23:0] |CNT0 |Timer0 Current Data Value (Read Only)
AnnaBridge 171:3a7713b1edbc 10345 * | | |This field indicates the current count values of timer0.
AnnaBridge 171:3a7713b1edbc 10346 * @var SC_T::TMRDAT1_2
AnnaBridge 171:3a7713b1edbc 10347 * Offset: 0x3C SC Timer Current Data Register B.
AnnaBridge 171:3a7713b1edbc 10348 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10349 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10350 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10351 * |[7:0] |CNT1 |Timer1 Current Data Value (Read Only)
AnnaBridge 171:3a7713b1edbc 10352 * | | |This field indicates the current count values of timer1.
AnnaBridge 171:3a7713b1edbc 10353 * |[15:8] |CNT2 |Timer2 Current Data Value (Read Only)
AnnaBridge 171:3a7713b1edbc 10354 * | | |This field indicates the current count values of timer2.
AnnaBridge 171:3a7713b1edbc 10355 */
AnnaBridge 171:3a7713b1edbc 10356
AnnaBridge 171:3a7713b1edbc 10357 __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
AnnaBridge 171:3a7713b1edbc 10358 __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
AnnaBridge 171:3a7713b1edbc 10359 __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
AnnaBridge 171:3a7713b1edbc 10360 __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
AnnaBridge 171:3a7713b1edbc 10361 __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
AnnaBridge 171:3a7713b1edbc 10362 __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
AnnaBridge 171:3a7713b1edbc 10363 __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
AnnaBridge 171:3a7713b1edbc 10364 __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
AnnaBridge 171:3a7713b1edbc 10365 __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
AnnaBridge 171:3a7713b1edbc 10366 __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
AnnaBridge 171:3a7713b1edbc 10367 __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
AnnaBridge 171:3a7713b1edbc 10368 __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
AnnaBridge 171:3a7713b1edbc 10369 __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
AnnaBridge 171:3a7713b1edbc 10370 __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
AnnaBridge 171:3a7713b1edbc 10371 __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
AnnaBridge 171:3a7713b1edbc 10372 __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
AnnaBridge 171:3a7713b1edbc 10373
AnnaBridge 171:3a7713b1edbc 10374 } SC_T;
AnnaBridge 171:3a7713b1edbc 10375
AnnaBridge 171:3a7713b1edbc 10376
AnnaBridge 171:3a7713b1edbc 10377
AnnaBridge 171:3a7713b1edbc 10378 /**
AnnaBridge 171:3a7713b1edbc 10379 @addtogroup SC_CONST SC Bit Field Definition
AnnaBridge 171:3a7713b1edbc 10380 Constant Definitions for SC Controller
AnnaBridge 171:3a7713b1edbc 10381 @{ */
AnnaBridge 171:3a7713b1edbc 10382
AnnaBridge 171:3a7713b1edbc 10383 #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
AnnaBridge 171:3a7713b1edbc 10384 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
AnnaBridge 171:3a7713b1edbc 10385
AnnaBridge 171:3a7713b1edbc 10386 #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
AnnaBridge 171:3a7713b1edbc 10387 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
AnnaBridge 171:3a7713b1edbc 10388
AnnaBridge 171:3a7713b1edbc 10389 #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
AnnaBridge 171:3a7713b1edbc 10390 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
AnnaBridge 171:3a7713b1edbc 10391
AnnaBridge 171:3a7713b1edbc 10392 #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
AnnaBridge 171:3a7713b1edbc 10393 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
AnnaBridge 171:3a7713b1edbc 10394
AnnaBridge 171:3a7713b1edbc 10395 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
AnnaBridge 171:3a7713b1edbc 10396 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
AnnaBridge 171:3a7713b1edbc 10397
AnnaBridge 171:3a7713b1edbc 10398 #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
AnnaBridge 171:3a7713b1edbc 10399 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
AnnaBridge 171:3a7713b1edbc 10400
AnnaBridge 171:3a7713b1edbc 10401 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
AnnaBridge 171:3a7713b1edbc 10402 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
AnnaBridge 171:3a7713b1edbc 10403
AnnaBridge 171:3a7713b1edbc 10404 #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
AnnaBridge 171:3a7713b1edbc 10405 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
AnnaBridge 171:3a7713b1edbc 10406
AnnaBridge 171:3a7713b1edbc 10407 #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
AnnaBridge 171:3a7713b1edbc 10408 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
AnnaBridge 171:3a7713b1edbc 10409
AnnaBridge 171:3a7713b1edbc 10410 #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
AnnaBridge 171:3a7713b1edbc 10411 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
AnnaBridge 171:3a7713b1edbc 10412
AnnaBridge 171:3a7713b1edbc 10413 #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
AnnaBridge 171:3a7713b1edbc 10414 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
AnnaBridge 171:3a7713b1edbc 10415
AnnaBridge 171:3a7713b1edbc 10416 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
AnnaBridge 171:3a7713b1edbc 10417 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
AnnaBridge 171:3a7713b1edbc 10418
AnnaBridge 171:3a7713b1edbc 10419 #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
AnnaBridge 171:3a7713b1edbc 10420 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
AnnaBridge 171:3a7713b1edbc 10421
AnnaBridge 171:3a7713b1edbc 10422 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
AnnaBridge 171:3a7713b1edbc 10423 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
AnnaBridge 171:3a7713b1edbc 10424
AnnaBridge 171:3a7713b1edbc 10425 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
AnnaBridge 171:3a7713b1edbc 10426 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
AnnaBridge 171:3a7713b1edbc 10427
AnnaBridge 171:3a7713b1edbc 10428 #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
AnnaBridge 171:3a7713b1edbc 10429 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
AnnaBridge 171:3a7713b1edbc 10430
AnnaBridge 171:3a7713b1edbc 10431 #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
AnnaBridge 171:3a7713b1edbc 10432 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
AnnaBridge 171:3a7713b1edbc 10433
AnnaBridge 171:3a7713b1edbc 10434 #define SC_CTL_ICEDEBUG_Pos (31) /*!< SC_T::CTL: ICEDEBUG Position */
AnnaBridge 171:3a7713b1edbc 10435 #define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) /*!< SC_T::CTL: ICEDEBUG Mask */
AnnaBridge 171:3a7713b1edbc 10436
AnnaBridge 171:3a7713b1edbc 10437 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
AnnaBridge 171:3a7713b1edbc 10438 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
AnnaBridge 171:3a7713b1edbc 10439
AnnaBridge 171:3a7713b1edbc 10440 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
AnnaBridge 171:3a7713b1edbc 10441 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
AnnaBridge 171:3a7713b1edbc 10442
AnnaBridge 171:3a7713b1edbc 10443 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
AnnaBridge 171:3a7713b1edbc 10444 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
AnnaBridge 171:3a7713b1edbc 10445
AnnaBridge 171:3a7713b1edbc 10446 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
AnnaBridge 171:3a7713b1edbc 10447 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
AnnaBridge 171:3a7713b1edbc 10448
AnnaBridge 171:3a7713b1edbc 10449 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
AnnaBridge 171:3a7713b1edbc 10450 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
AnnaBridge 171:3a7713b1edbc 10451
AnnaBridge 171:3a7713b1edbc 10452 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
AnnaBridge 171:3a7713b1edbc 10453 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
AnnaBridge 171:3a7713b1edbc 10454
AnnaBridge 171:3a7713b1edbc 10455 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
AnnaBridge 171:3a7713b1edbc 10456 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
AnnaBridge 171:3a7713b1edbc 10457
AnnaBridge 171:3a7713b1edbc 10458 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
AnnaBridge 171:3a7713b1edbc 10459 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
AnnaBridge 171:3a7713b1edbc 10460
AnnaBridge 171:3a7713b1edbc 10461 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
AnnaBridge 171:3a7713b1edbc 10462 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
AnnaBridge 171:3a7713b1edbc 10463
AnnaBridge 171:3a7713b1edbc 10464 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
AnnaBridge 171:3a7713b1edbc 10465 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
AnnaBridge 171:3a7713b1edbc 10466
AnnaBridge 171:3a7713b1edbc 10467 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
AnnaBridge 171:3a7713b1edbc 10468 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
AnnaBridge 171:3a7713b1edbc 10469
AnnaBridge 171:3a7713b1edbc 10470 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
AnnaBridge 171:3a7713b1edbc 10471 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
AnnaBridge 171:3a7713b1edbc 10472
AnnaBridge 171:3a7713b1edbc 10473 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
AnnaBridge 171:3a7713b1edbc 10474 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
AnnaBridge 171:3a7713b1edbc 10475
AnnaBridge 171:3a7713b1edbc 10476 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
AnnaBridge 171:3a7713b1edbc 10477 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
AnnaBridge 171:3a7713b1edbc 10478
AnnaBridge 171:3a7713b1edbc 10479 #define SC_ALTCTL_OUTSEL_Pos (16) /*!< SC_T::ALTCTL: OUTSEL Position */
AnnaBridge 171:3a7713b1edbc 10480 #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */
AnnaBridge 171:3a7713b1edbc 10481
AnnaBridge 171:3a7713b1edbc 10482 #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
AnnaBridge 171:3a7713b1edbc 10483 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
AnnaBridge 171:3a7713b1edbc 10484
AnnaBridge 171:3a7713b1edbc 10485 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
AnnaBridge 171:3a7713b1edbc 10486 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
AnnaBridge 171:3a7713b1edbc 10487
AnnaBridge 171:3a7713b1edbc 10488 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV_ Position */
AnnaBridge 171:3a7713b1edbc 10489 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV_ Mask */
AnnaBridge 171:3a7713b1edbc 10490
AnnaBridge 171:3a7713b1edbc 10491 #define SC_ETUCTL_CMPEN_Pos (15) /*!< SC_T::ETUCTL: CMPEN_ Position */
AnnaBridge 171:3a7713b1edbc 10492 #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC_T::ETUCTL: CMPEN_ Mask */
AnnaBridge 171:3a7713b1edbc 10493
AnnaBridge 171:3a7713b1edbc 10494 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
AnnaBridge 171:3a7713b1edbc 10495 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
AnnaBridge 171:3a7713b1edbc 10496
AnnaBridge 171:3a7713b1edbc 10497 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
AnnaBridge 171:3a7713b1edbc 10498 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
AnnaBridge 171:3a7713b1edbc 10499
AnnaBridge 171:3a7713b1edbc 10500 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
AnnaBridge 171:3a7713b1edbc 10501 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
AnnaBridge 171:3a7713b1edbc 10502
AnnaBridge 171:3a7713b1edbc 10503 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN_Position */
AnnaBridge 171:3a7713b1edbc 10504 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
AnnaBridge 171:3a7713b1edbc 10505
AnnaBridge 171:3a7713b1edbc 10506 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
AnnaBridge 171:3a7713b1edbc 10507 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
AnnaBridge 171:3a7713b1edbc 10508
AnnaBridge 171:3a7713b1edbc 10509 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
AnnaBridge 171:3a7713b1edbc 10510 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
AnnaBridge 171:3a7713b1edbc 10511
AnnaBridge 171:3a7713b1edbc 10512 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
AnnaBridge 171:3a7713b1edbc 10513 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
AnnaBridge 171:3a7713b1edbc 10514
AnnaBridge 171:3a7713b1edbc 10515 #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
AnnaBridge 171:3a7713b1edbc 10516 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
AnnaBridge 171:3a7713b1edbc 10517
AnnaBridge 171:3a7713b1edbc 10518 #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
AnnaBridge 171:3a7713b1edbc 10519 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
AnnaBridge 171:3a7713b1edbc 10520
AnnaBridge 171:3a7713b1edbc 10521 #define SC_INTEN_RXTOIF_Pos (9) /*!< SC_T::INTEN: RXTOIF Position */
AnnaBridge 171:3a7713b1edbc 10522 #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC_T::INTEN: RXTOIF Mask */
AnnaBridge 171:3a7713b1edbc 10523
AnnaBridge 171:3a7713b1edbc 10524 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
AnnaBridge 171:3a7713b1edbc 10525 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
AnnaBridge 171:3a7713b1edbc 10526
AnnaBridge 171:3a7713b1edbc 10527 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
AnnaBridge 171:3a7713b1edbc 10528 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
AnnaBridge 171:3a7713b1edbc 10529
AnnaBridge 171:3a7713b1edbc 10530 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
AnnaBridge 171:3a7713b1edbc 10531 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
AnnaBridge 171:3a7713b1edbc 10532
AnnaBridge 171:3a7713b1edbc 10533 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
AnnaBridge 171:3a7713b1edbc 10534 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
AnnaBridge 171:3a7713b1edbc 10535
AnnaBridge 171:3a7713b1edbc 10536 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
AnnaBridge 171:3a7713b1edbc 10537 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
AnnaBridge 171:3a7713b1edbc 10538
AnnaBridge 171:3a7713b1edbc 10539 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
AnnaBridge 171:3a7713b1edbc 10540 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
AnnaBridge 171:3a7713b1edbc 10541
AnnaBridge 171:3a7713b1edbc 10542 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
AnnaBridge 171:3a7713b1edbc 10543 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
AnnaBridge 171:3a7713b1edbc 10544
AnnaBridge 171:3a7713b1edbc 10545 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
AnnaBridge 171:3a7713b1edbc 10546 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
AnnaBridge 171:3a7713b1edbc 10547
AnnaBridge 171:3a7713b1edbc 10548 #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
AnnaBridge 171:3a7713b1edbc 10549 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
AnnaBridge 171:3a7713b1edbc 10550
AnnaBridge 171:3a7713b1edbc 10551 #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
AnnaBridge 171:3a7713b1edbc 10552 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
AnnaBridge 171:3a7713b1edbc 10553
AnnaBridge 171:3a7713b1edbc 10554 #define SC_INTSTS_RBTOIF_Pos (9) /*!< SC_T::INTSTS: RBTOIF Position */
AnnaBridge 171:3a7713b1edbc 10555 #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC_T::INTSTS: RBTOIF Mask */
AnnaBridge 171:3a7713b1edbc 10556
AnnaBridge 171:3a7713b1edbc 10557 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
AnnaBridge 171:3a7713b1edbc 10558 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
AnnaBridge 171:3a7713b1edbc 10559
AnnaBridge 171:3a7713b1edbc 10560 #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXO Position */
AnnaBridge 171:3a7713b1edbc 10561 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXO Mask */
AnnaBridge 171:3a7713b1edbc 10562
AnnaBridge 171:3a7713b1edbc 10563 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 10564 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 10565
AnnaBridge 171:3a7713b1edbc 10566 #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
AnnaBridge 171:3a7713b1edbc 10567 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
AnnaBridge 171:3a7713b1edbc 10568
AnnaBridge 171:3a7713b1edbc 10569 #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
AnnaBridge 171:3a7713b1edbc 10570 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
AnnaBridge 171:3a7713b1edbc 10571
AnnaBridge 171:3a7713b1edbc 10572 #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
AnnaBridge 171:3a7713b1edbc 10573 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
AnnaBridge 171:3a7713b1edbc 10574
AnnaBridge 171:3a7713b1edbc 10575 #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
AnnaBridge 171:3a7713b1edbc 10576 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
AnnaBridge 171:3a7713b1edbc 10577
AnnaBridge 171:3a7713b1edbc 10578 #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
AnnaBridge 171:3a7713b1edbc 10579 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
AnnaBridge 171:3a7713b1edbc 10580
AnnaBridge 171:3a7713b1edbc 10581 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 10582 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 10583
AnnaBridge 171:3a7713b1edbc 10584 #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
AnnaBridge 171:3a7713b1edbc 10585 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
AnnaBridge 171:3a7713b1edbc 10586
AnnaBridge 171:3a7713b1edbc 10587 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
AnnaBridge 171:3a7713b1edbc 10588 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
AnnaBridge 171:3a7713b1edbc 10589
AnnaBridge 171:3a7713b1edbc 10590 #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
AnnaBridge 171:3a7713b1edbc 10591 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
AnnaBridge 171:3a7713b1edbc 10592
AnnaBridge 171:3a7713b1edbc 10593 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
AnnaBridge 171:3a7713b1edbc 10594 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
AnnaBridge 171:3a7713b1edbc 10595
AnnaBridge 171:3a7713b1edbc 10596 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
AnnaBridge 171:3a7713b1edbc 10597 #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
AnnaBridge 171:3a7713b1edbc 10598
AnnaBridge 171:3a7713b1edbc 10599 #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
AnnaBridge 171:3a7713b1edbc 10600 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
AnnaBridge 171:3a7713b1edbc 10601
AnnaBridge 171:3a7713b1edbc 10602 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
AnnaBridge 171:3a7713b1edbc 10603 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
AnnaBridge 171:3a7713b1edbc 10604
AnnaBridge 171:3a7713b1edbc 10605 #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
AnnaBridge 171:3a7713b1edbc 10606 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Msk */
AnnaBridge 171:3a7713b1edbc 10607
AnnaBridge 171:3a7713b1edbc 10608 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
AnnaBridge 171:3a7713b1edbc 10609 #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Msk */
AnnaBridge 171:3a7713b1edbc 10610
AnnaBridge 171:3a7713b1edbc 10611 #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
AnnaBridge 171:3a7713b1edbc 10612 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Msk */
AnnaBridge 171:3a7713b1edbc 10613
AnnaBridge 171:3a7713b1edbc 10614 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR_ Position */
AnnaBridge 171:3a7713b1edbc 10615 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR_ Msk */
AnnaBridge 171:3a7713b1edbc 10616
AnnaBridge 171:3a7713b1edbc 10617 #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
AnnaBridge 171:3a7713b1edbc 10618 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Msk */
AnnaBridge 171:3a7713b1edbc 10619
AnnaBridge 171:3a7713b1edbc 10620 #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
AnnaBridge 171:3a7713b1edbc 10621 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Msk */
AnnaBridge 171:3a7713b1edbc 10622
AnnaBridge 171:3a7713b1edbc 10623 #define SC_PINCTL_SCRST_Pos (1) /*!< SC_T::PINCTL: SCRST Position */
AnnaBridge 171:3a7713b1edbc 10624 #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC_T::PINCTL: SCRST Msk */
AnnaBridge 171:3a7713b1edbc 10625
AnnaBridge 171:3a7713b1edbc 10626 #define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
AnnaBridge 171:3a7713b1edbc 10627 #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Msk */
AnnaBridge 171:3a7713b1edbc 10628
AnnaBridge 171:3a7713b1edbc 10629 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
AnnaBridge 171:3a7713b1edbc 10630 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Msk */
AnnaBridge 171:3a7713b1edbc 10631
AnnaBridge 171:3a7713b1edbc 10632 #define SC_PINCTL_SCDOUT_Pos (9) /*!< SC_T::PINCTL: SCDOUT Position */
AnnaBridge 171:3a7713b1edbc 10633 #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC_T::PINCTL: SCDOUT Msk */
AnnaBridge 171:3a7713b1edbc 10634
AnnaBridge 171:3a7713b1edbc 10635 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
AnnaBridge 171:3a7713b1edbc 10636 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Msk */
AnnaBridge 171:3a7713b1edbc 10637
AnnaBridge 171:3a7713b1edbc 10638 #define SC_PINCTL_SCDOSTS_Pos (12) /*!< SC_T::PINCTL: SCDOSTS Position */
AnnaBridge 171:3a7713b1edbc 10639 #define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) /*!< SC_T::PINCTL: SCDOSTS Msk */
AnnaBridge 171:3a7713b1edbc 10640
AnnaBridge 171:3a7713b1edbc 10641 #define SC_PINCTL_DATSTS_Pos (16) /*!< SC_T::PINCTL: DATSTS Position */
AnnaBridge 171:3a7713b1edbc 10642 #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC_T::PINCTL: DATSTS Msk */
AnnaBridge 171:3a7713b1edbc 10643
AnnaBridge 171:3a7713b1edbc 10644 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
AnnaBridge 171:3a7713b1edbc 10645 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Msk */
AnnaBridge 171:3a7713b1edbc 10646
AnnaBridge 171:3a7713b1edbc 10647 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
AnnaBridge 171:3a7713b1edbc 10648 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Msk */
AnnaBridge 171:3a7713b1edbc 10649
AnnaBridge 171:3a7713b1edbc 10650 #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
AnnaBridge 171:3a7713b1edbc 10651 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Msk */
AnnaBridge 171:3a7713b1edbc 10652
AnnaBridge 171:3a7713b1edbc 10653 #define SC_PINCTL_LOOPBK_Pos (31) /*!< SC_T::PINCTL: LOOPBK Position */
AnnaBridge 171:3a7713b1edbc 10654 #define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) /*!< SC_T::PINCTL: LOOPBK Msk */
AnnaBridge 171:3a7713b1edbc 10655
AnnaBridge 171:3a7713b1edbc 10656 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
AnnaBridge 171:3a7713b1edbc 10657 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Msk */
AnnaBridge 171:3a7713b1edbc 10658
AnnaBridge 171:3a7713b1edbc 10659 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 10660 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Msk */
AnnaBridge 171:3a7713b1edbc 10661
AnnaBridge 171:3a7713b1edbc 10662 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
AnnaBridge 171:3a7713b1edbc 10663 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Msk */
AnnaBridge 171:3a7713b1edbc 10664
AnnaBridge 171:3a7713b1edbc 10665 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 10666 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Msk */
AnnaBridge 171:3a7713b1edbc 10667
AnnaBridge 171:3a7713b1edbc 10668 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
AnnaBridge 171:3a7713b1edbc 10669 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Msk */
AnnaBridge 171:3a7713b1edbc 10670
AnnaBridge 171:3a7713b1edbc 10671 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 10672 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Msk */
AnnaBridge 171:3a7713b1edbc 10673
AnnaBridge 171:3a7713b1edbc 10674 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
AnnaBridge 171:3a7713b1edbc 10675 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Msk */
AnnaBridge 171:3a7713b1edbc 10676
AnnaBridge 171:3a7713b1edbc 10677 #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
AnnaBridge 171:3a7713b1edbc 10678 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) /*!< SC_T::UARTCTL: WLS Msk */
AnnaBridge 171:3a7713b1edbc 10679
AnnaBridge 171:3a7713b1edbc 10680 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
AnnaBridge 171:3a7713b1edbc 10681 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Msk */
AnnaBridge 171:3a7713b1edbc 10682
AnnaBridge 171:3a7713b1edbc 10683 #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
AnnaBridge 171:3a7713b1edbc 10684 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Msk */
AnnaBridge 171:3a7713b1edbc 10685
AnnaBridge 171:3a7713b1edbc 10686 #define SC_TMRDAT0_CNT0_Pos (0) /*!< SC_T::TMRDAT0: CNT0 Position */
AnnaBridge 171:3a7713b1edbc 10687 #define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) /*!< SC_T::TMRDAT0: CNT0 Msk */
AnnaBridge 171:3a7713b1edbc 10688
AnnaBridge 171:3a7713b1edbc 10689 #define SC_TMRDAT1_2_CNT1_Pos (0) /*!< SC_T::TMRDAT1_2: CNT1 Position */
AnnaBridge 171:3a7713b1edbc 10690 #define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) /*!< SC_T::TMRDAT1_2: CNT1 Msk */
AnnaBridge 171:3a7713b1edbc 10691
AnnaBridge 171:3a7713b1edbc 10692 #define SC_TMRDAT1_2_CNT2_Pos (8) /*!< SC_T::TMRDAT1_2: CNT2 Position */
AnnaBridge 171:3a7713b1edbc 10693 #define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /*!< SC_T::TMRDAT1_2: CNT2 Msk */
AnnaBridge 171:3a7713b1edbc 10694
AnnaBridge 171:3a7713b1edbc 10695 /**@}*/ /* SC_CONST */
AnnaBridge 171:3a7713b1edbc 10696 /**@}*/ /* end of SC register group */
AnnaBridge 171:3a7713b1edbc 10697
AnnaBridge 171:3a7713b1edbc 10698
AnnaBridge 171:3a7713b1edbc 10699 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 10700 /**
AnnaBridge 171:3a7713b1edbc 10701 @addtogroup SPI Serial Peripheral Interface Controller(SPI)
AnnaBridge 171:3a7713b1edbc 10702 Memory Mapped Structure for SPI Controller
AnnaBridge 171:3a7713b1edbc 10703 @{ */
AnnaBridge 171:3a7713b1edbc 10704
AnnaBridge 171:3a7713b1edbc 10705
AnnaBridge 171:3a7713b1edbc 10706 typedef struct
AnnaBridge 171:3a7713b1edbc 10707 {
AnnaBridge 171:3a7713b1edbc 10708
AnnaBridge 171:3a7713b1edbc 10709
AnnaBridge 171:3a7713b1edbc 10710 /**
AnnaBridge 171:3a7713b1edbc 10711 * @var SPI_T::CTL
AnnaBridge 171:3a7713b1edbc 10712 * Offset: 0x00 Control Register
AnnaBridge 171:3a7713b1edbc 10713 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10714 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10715 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10716 * |[0] |SPIEN |SPI Transfer Control Enable Bit
AnnaBridge 171:3a7713b1edbc 10717 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
AnnaBridge 171:3a7713b1edbc 10718 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
AnnaBridge 171:3a7713b1edbc 10719 * | | |0 = Transfer control Disabled.
AnnaBridge 171:3a7713b1edbc 10720 * | | |1 = Transfer control Enabled.
AnnaBridge 171:3a7713b1edbc 10721 * | | |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
AnnaBridge 171:3a7713b1edbc 10722 * |[1] |RXNEG |Receive On Negative Edge
AnnaBridge 171:3a7713b1edbc 10723 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
AnnaBridge 171:3a7713b1edbc 10724 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
AnnaBridge 171:3a7713b1edbc 10725 * |[2] |TXNEG |Transmit On Negative Edge
AnnaBridge 171:3a7713b1edbc 10726 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
AnnaBridge 171:3a7713b1edbc 10727 * | | |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
AnnaBridge 171:3a7713b1edbc 10728 * |[3] |CLKPOL |Clock Polarity
AnnaBridge 171:3a7713b1edbc 10729 * | | |0 = SPI bus clock is idle low.
AnnaBridge 171:3a7713b1edbc 10730 * | | |1 = SPI bus clock is idle high.
AnnaBridge 171:3a7713b1edbc 10731 * |[7:4] |SUSPITV |Suspend Interval (Master Only)
AnnaBridge 171:3a7713b1edbc 10732 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
AnnaBridge 171:3a7713b1edbc 10733 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
AnnaBridge 171:3a7713b1edbc 10734 * | | |The default value is 0x3.
AnnaBridge 171:3a7713b1edbc 10735 * | | |The period of the suspend interval is obtained according to the following equation.
AnnaBridge 171:3a7713b1edbc 10736 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
AnnaBridge 171:3a7713b1edbc 10737 * | | |Example:
AnnaBridge 171:3a7713b1edbc 10738 * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
AnnaBridge 171:3a7713b1edbc 10739 * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
AnnaBridge 171:3a7713b1edbc 10740 * | | |...
AnnaBridge 171:3a7713b1edbc 10741 * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
AnnaBridge 171:3a7713b1edbc 10742 * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
AnnaBridge 171:3a7713b1edbc 10743 * |[12:8] |DWIDTH |Data Width
AnnaBridge 171:3a7713b1edbc 10744 * | | |This field specifies how many bits can be transmitted / received in one transaction.
AnnaBridge 171:3a7713b1edbc 10745 * | | |The minimum bit length is 8 bits and can up to 32 bits.
AnnaBridge 171:3a7713b1edbc 10746 * | | |DWIDTH = 0x08 ... 8 bits.
AnnaBridge 171:3a7713b1edbc 10747 * | | |DWIDTH = 0x09 ... 9 bits.
AnnaBridge 171:3a7713b1edbc 10748 * | | |...
AnnaBridge 171:3a7713b1edbc 10749 * | | |DWIDTH = 0x1F ... 31 bits.
AnnaBridge 171:3a7713b1edbc 10750 * | | |DWIDTH = 0x00 ... 32 bits.
AnnaBridge 171:3a7713b1edbc 10751 * |[13] |LSB |Send LSB First
AnnaBridge 171:3a7713b1edbc 10752 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
AnnaBridge 171:3a7713b1edbc 10753 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
AnnaBridge 171:3a7713b1edbc 10754 * |[16] |TWOBIT |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10755 * | | |0 = 2-Bit Transfer mode Disabled.
AnnaBridge 171:3a7713b1edbc 10756 * | | |1 = 2-Bit Transfer mode Enabled.
AnnaBridge 171:3a7713b1edbc 10757 * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
AnnaBridge 171:3a7713b1edbc 10758 * | | |serial transmitted bit data is from the second FIFO buffer data.
AnnaBridge 171:3a7713b1edbc 10759 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
AnnaBridge 171:3a7713b1edbc 10760 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10761 * | | |0 = SPI unit transfer interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10762 * | | |1 = SPI unit transfer interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10763 * |[18] |SLAVE |Slave Mode Control
AnnaBridge 171:3a7713b1edbc 10764 * | | |0 = Master mode.
AnnaBridge 171:3a7713b1edbc 10765 * | | |1 = Slave mode.
AnnaBridge 171:3a7713b1edbc 10766 * |[19] |REORDER |Byte Reorder Function Enable Bit
AnnaBridge 171:3a7713b1edbc 10767 * | | |0 = Byte Reorder function Disabled.
AnnaBridge 171:3a7713b1edbc 10768 * | | |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
AnnaBridge 171:3a7713b1edbc 10769 * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
AnnaBridge 171:3a7713b1edbc 10770 * | | |Note:
AnnaBridge 171:3a7713b1edbc 10771 * | | |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
AnnaBridge 171:3a7713b1edbc 10772 * | | |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
AnnaBridge 171:3a7713b1edbc 10773 * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10774 * | | |0 = Quad or Dual Input mode.
AnnaBridge 171:3a7713b1edbc 10775 * | | |1 = Quad or Dual Output mode.
AnnaBridge 171:3a7713b1edbc 10776 * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10777 * | | |0 = Dual I/O mode Disabled.
AnnaBridge 171:3a7713b1edbc 10778 * | | |1 = Dual I/O mode Enabled.
AnnaBridge 171:3a7713b1edbc 10779 * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10780 * | | |0 = Quad I/O mode Disabled.
AnnaBridge 171:3a7713b1edbc 10781 * | | |1 = Quad I/O mode Enabled.
AnnaBridge 171:3a7713b1edbc 10782 * @var SPI_T::CLKDIV
AnnaBridge 171:3a7713b1edbc 10783 * Offset: 0x04 Clock Divider Register
AnnaBridge 171:3a7713b1edbc 10784 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10785 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10786 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10787 * |[7:0] |DIVIDER |Clock Divider
AnnaBridge 171:3a7713b1edbc 10788 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
AnnaBridge 171:3a7713b1edbc 10789 * | | |The frequency is obtained according to the following equation.
AnnaBridge 171:3a7713b1edbc 10790 * | | | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
AnnaBridge 171:3a7713b1edbc 10791 * | | |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
AnnaBridge 171:3a7713b1edbc 10792 * @var SPI_T::SSCTL
AnnaBridge 171:3a7713b1edbc 10793 * Offset: 0x08 Slave Select Control Register
AnnaBridge 171:3a7713b1edbc 10794 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10795 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10796 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10797 * |[0] |SS |Slave Selection Control (Master Only)
AnnaBridge 171:3a7713b1edbc 10798 * | | |If AUTOSS bit is cleared to 0,
AnnaBridge 171:3a7713b1edbc 10799 * | | |0 = set the SPIn_SS line to inactive state.
AnnaBridge 171:3a7713b1edbc 10800 * | | |1 = set the SPIn_SS line to active state
AnnaBridge 171:3a7713b1edbc 10801 * | | |If the AUTOSS bit is set to 1,
AnnaBridge 171:3a7713b1edbc 10802 * | | |0 = Keep the SPIn_SS line at inactive state.
AnnaBridge 171:3a7713b1edbc 10803 * | | |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
AnnaBridge 171:3a7713b1edbc 10804 * | | |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
AnnaBridge 171:3a7713b1edbc 10805 * |[2] |SSACTPOL |Slave Selection Active Polarity
AnnaBridge 171:3a7713b1edbc 10806 * | | |This bit defines the active polarity of slave selection signal (SPIn_SS).
AnnaBridge 171:3a7713b1edbc 10807 * | | |0 = The slave selection signal SPIn_SS is active low.
AnnaBridge 171:3a7713b1edbc 10808 * | | |1 = The slave selection signal SPIn_SS is active high.
AnnaBridge 171:3a7713b1edbc 10809 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
AnnaBridge 171:3a7713b1edbc 10810 * | | |0 = Automatic slave selection function Disabled.
AnnaBridge 171:3a7713b1edbc 10811 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
AnnaBridge 171:3a7713b1edbc 10812 * | | |1 = Automatic slave selection function Enabled.
AnnaBridge 171:3a7713b1edbc 10813 * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 10814 * | | |Slave 3-wire mode is only available in SPI0.
AnnaBridge 171:3a7713b1edbc 10815 * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
AnnaBridge 171:3a7713b1edbc 10816 * | | |0 = 4-wire bi-direction interface.
AnnaBridge 171:3a7713b1edbc 10817 * | | |1 = 3-wire bi-direction interface.
AnnaBridge 171:3a7713b1edbc 10818 * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10819 * | | |0 = Slave mode time-out interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10820 * | | |1 = Slave mode time-out interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10821 * |[6] |SLVTORST |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10822 * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
AnnaBridge 171:3a7713b1edbc 10823 * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
AnnaBridge 171:3a7713b1edbc 10824 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10825 * | | |0 = Slave mode bit count error interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10826 * | | |1 = Slave mode bit count error interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10827 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10828 * | | |0 = Slave mode TX under run interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10829 * | | |1 = Slave mode TX under run interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10830 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10831 * | | |0 = Slave select active interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10832 * | | |1 = Slave select active interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10833 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10834 * | | |0 = Slave select inactive interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10835 * | | |1 = Slave select inactive interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10836 * |[31:16] |SLVTOCNT |Slave Mode Time-Out Period (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10837 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
AnnaBridge 171:3a7713b1edbc 10838 * | | |The clock source of the time-out counter is Slave peripheral clock.
AnnaBridge 171:3a7713b1edbc 10839 * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
AnnaBridge 171:3a7713b1edbc 10840 * @var SPI_T::PDMACTL
AnnaBridge 171:3a7713b1edbc 10841 * Offset: 0x0C SPI PDMA Control Register
AnnaBridge 171:3a7713b1edbc 10842 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10843 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10844 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10845 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
AnnaBridge 171:3a7713b1edbc 10846 * | | |0 = Transmit PDMA function Disabled.
AnnaBridge 171:3a7713b1edbc 10847 * | | |1 = Transmit PDMA function Enabled.
AnnaBridge 171:3a7713b1edbc 10848 * | | |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
AnnaBridge 171:3a7713b1edbc 10849 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
AnnaBridge 171:3a7713b1edbc 10850 * |[1] |RXPDMAEN |Receive PDMA Enable Bit
AnnaBridge 171:3a7713b1edbc 10851 * | | |0 = Receiver PDMA function Disabled.
AnnaBridge 171:3a7713b1edbc 10852 * | | |1 = Receiver PDMA function Enabled.
AnnaBridge 171:3a7713b1edbc 10853 * |[2] |PDMARST |PDMA Reset
AnnaBridge 171:3a7713b1edbc 10854 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10855 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
AnnaBridge 171:3a7713b1edbc 10856 * @var SPI_T::FIFOCTL
AnnaBridge 171:3a7713b1edbc 10857 * Offset: 0x10 SPI FIFO Control Register
AnnaBridge 171:3a7713b1edbc 10858 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10859 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10860 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10861 * |[0] |RXRST |Receive Reset
AnnaBridge 171:3a7713b1edbc 10862 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10863 * | | |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 10864 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
AnnaBridge 171:3a7713b1edbc 10865 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
AnnaBridge 171:3a7713b1edbc 10866 * | | |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
AnnaBridge 171:3a7713b1edbc 10867 * |[1] |TXRST |Transmit Reset
AnnaBridge 171:3a7713b1edbc 10868 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10869 * | | |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 10870 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
AnnaBridge 171:3a7713b1edbc 10871 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
AnnaBridge 171:3a7713b1edbc 10872 * | | |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
AnnaBridge 171:3a7713b1edbc 10873 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10874 * | | |0 = RX FIFO threshold interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10875 * | | |1 = RX FIFO threshold interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10876 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10877 * | | |0 = TX FIFO threshold interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10878 * | | |1 = TX FIFO threshold interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10879 * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10880 * | | |0 = Receive time-out interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10881 * | | |1 = Receive time-out interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10882 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10883 * | | |0 = Receive FIFO overrun interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10884 * | | |1 = Receive FIFO overrun interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10885 * |[6] |TXUFPOL |TX Underflow Data Polarity
AnnaBridge 171:3a7713b1edbc 10886 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
AnnaBridge 171:3a7713b1edbc 10887 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
AnnaBridge 171:3a7713b1edbc 10888 * | | |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
AnnaBridge 171:3a7713b1edbc 10889 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 10890 * | | |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
AnnaBridge 171:3a7713b1edbc 10891 * | | |0 = Slave TX underflow interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 10892 * | | |1 = Slave TX underflow interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 10893 * |[8] |RXFBCLR |Receive FIFO Buffer Clear
AnnaBridge 171:3a7713b1edbc 10894 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10895 * | | |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 10896 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
AnnaBridge 171:3a7713b1edbc 10897 * | | |Note: The RX shift register will not be cleared.
AnnaBridge 171:3a7713b1edbc 10898 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
AnnaBridge 171:3a7713b1edbc 10899 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10900 * | | |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 10901 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
AnnaBridge 171:3a7713b1edbc 10902 * | | |Note: The TX shift register will not be cleared.
AnnaBridge 171:3a7713b1edbc 10903 * |[26:24] |RXTH |Receive FIFO Threshold
AnnaBridge 171:3a7713b1edbc 10904 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
AnnaBridge 171:3a7713b1edbc 10905 * | | |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
AnnaBridge 171:3a7713b1edbc 10906 * |[30:28] |TXTH |Transmit FIFO Threshold
AnnaBridge 171:3a7713b1edbc 10907 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
AnnaBridge 171:3a7713b1edbc 10908 * | | |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
AnnaBridge 171:3a7713b1edbc 10909 * @var SPI_T::STATUS
AnnaBridge 171:3a7713b1edbc 10910 * Offset: 0x14 SPI Status Register
AnnaBridge 171:3a7713b1edbc 10911 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10912 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 10913 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 10914 * |[0] |BUSY |Busy Status (Read Only)
AnnaBridge 171:3a7713b1edbc 10915 * | | |0 = SPI controller is in idle state.
AnnaBridge 171:3a7713b1edbc 10916 * | | |1 = SPI controller is in busy state.
AnnaBridge 171:3a7713b1edbc 10917 * | | |The following listing are the bus busy conditions:
AnnaBridge 171:3a7713b1edbc 10918 * | | |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
AnnaBridge 171:3a7713b1edbc 10919 * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
AnnaBridge 171:3a7713b1edbc 10920 * | | |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
AnnaBridge 171:3a7713b1edbc 10921 * | | |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
AnnaBridge 171:3a7713b1edbc 10922 * |[1] |UNITIF |Unit Transfer Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10923 * | | |0 = No transaction has been finished since this bit was cleared to 0.
AnnaBridge 171:3a7713b1edbc 10924 * | | |1 = SPI controller has finished one unit transfer.
AnnaBridge 171:3a7713b1edbc 10925 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10926 * |[2] |SSACTIF |Slave Select Active Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10927 * | | |0 = Slave select active interrupt was cleared or not occurred.
AnnaBridge 171:3a7713b1edbc 10928 * | | |1 = Slave select active interrupt event occurred.
AnnaBridge 171:3a7713b1edbc 10929 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10930 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10931 * | | |0 = Slave select inactive interrupt was cleared or not occurred.
AnnaBridge 171:3a7713b1edbc 10932 * | | |1 = Slave select inactive interrupt event occurred.
AnnaBridge 171:3a7713b1edbc 10933 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10934 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
AnnaBridge 171:3a7713b1edbc 10935 * | | |0 = The slave select line status is 0.
AnnaBridge 171:3a7713b1edbc 10936 * | | |1 = The slave select line status is 1.
AnnaBridge 171:3a7713b1edbc 10937 * | | |Note: This bit is only available in Slave mode.
AnnaBridge 171:3a7713b1edbc 10938 * | | |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
AnnaBridge 171:3a7713b1edbc 10939 * |[5] |SLVTOIF |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
AnnaBridge 171:3a7713b1edbc 10940 * | | |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
AnnaBridge 171:3a7713b1edbc 10941 * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
AnnaBridge 171:3a7713b1edbc 10942 * | | |0 = Slave time-out is not active.
AnnaBridge 171:3a7713b1edbc 10943 * | | |1 = Slave time-out is active.
AnnaBridge 171:3a7713b1edbc 10944 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10945 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10946 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
AnnaBridge 171:3a7713b1edbc 10947 * | | |0 = No Slave mode bit count error event.
AnnaBridge 171:3a7713b1edbc 10948 * | | |1 = Slave mode bit count error event occurs.
AnnaBridge 171:3a7713b1edbc 10949 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
AnnaBridge 171:3a7713b1edbc 10950 * | | |This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10951 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10952 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
AnnaBridge 171:3a7713b1edbc 10953 * | | |0 = No Slave TX under run event.
AnnaBridge 171:3a7713b1edbc 10954 * | | |1 = Slave TX under run occurs.
AnnaBridge 171:3a7713b1edbc 10955 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10956 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 10957 * | | |0 = Receive FIFO buffer is not empty.
AnnaBridge 171:3a7713b1edbc 10958 * | | |1 = Receive FIFO buffer is empty.
AnnaBridge 171:3a7713b1edbc 10959 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 10960 * | | |0 = Receive FIFO buffer is not full.
AnnaBridge 171:3a7713b1edbc 10961 * | | |1 = Receive FIFO buffer is full.
AnnaBridge 171:3a7713b1edbc 10962 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10963 * | | |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
AnnaBridge 171:3a7713b1edbc 10964 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
AnnaBridge 171:3a7713b1edbc 10965 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10966 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 10967 * | | |0 = No FIFO is over run.
AnnaBridge 171:3a7713b1edbc 10968 * | | |1 = Receive FIFO over run.
AnnaBridge 171:3a7713b1edbc 10969 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10970 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10971 * | | |0 = No receive FIFO time-out event.
AnnaBridge 171:3a7713b1edbc 10972 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
AnnaBridge 171:3a7713b1edbc 10973 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 10974 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10975 * |[15] |SPIENSTS |SPI Enable Status (Read Only)
AnnaBridge 171:3a7713b1edbc 10976 * | | |0 = The SPI controller is disabled.
AnnaBridge 171:3a7713b1edbc 10977 * | | |1 = The SPI controller is enabled.
AnnaBridge 171:3a7713b1edbc 10978 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
AnnaBridge 171:3a7713b1edbc 10979 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
AnnaBridge 171:3a7713b1edbc 10980 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 10981 * | | |0 = Transmit FIFO buffer is not empty.
AnnaBridge 171:3a7713b1edbc 10982 * | | |1 = Transmit FIFO buffer is empty.
AnnaBridge 171:3a7713b1edbc 10983 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 10984 * | | |0 = Transmit FIFO buffer is not full.
AnnaBridge 171:3a7713b1edbc 10985 * | | |1 = Transmit FIFO buffer is full.
AnnaBridge 171:3a7713b1edbc 10986 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 10987 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
AnnaBridge 171:3a7713b1edbc 10988 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
AnnaBridge 171:3a7713b1edbc 10989 * |[19] |TXUFIF |TX Underflow Interrupt Flag
AnnaBridge 171:3a7713b1edbc 10990 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
AnnaBridge 171:3a7713b1edbc 10991 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 10992 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
AnnaBridge 171:3a7713b1edbc 10993 * | | |Note 1: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 10994 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
AnnaBridge 171:3a7713b1edbc 10995 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
AnnaBridge 171:3a7713b1edbc 10996 * | | |0 = The reset function of TXRST or RXRST is done.
AnnaBridge 171:3a7713b1edbc 10997 * | | |1 = Doing the reset function of TXRST or RXRST.
AnnaBridge 171:3a7713b1edbc 10998 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
AnnaBridge 171:3a7713b1edbc 10999 * | | |User can check the status of this bit to monitor the reset function is doing or done.
AnnaBridge 171:3a7713b1edbc 11000 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
AnnaBridge 171:3a7713b1edbc 11001 * | | |This bit field indicates the valid data count of receive FIFO buffer.
AnnaBridge 171:3a7713b1edbc 11002 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
AnnaBridge 171:3a7713b1edbc 11003 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
AnnaBridge 171:3a7713b1edbc 11004 * @var SPI_T::TX
AnnaBridge 171:3a7713b1edbc 11005 * Offset: 0x20 Data Transmit Register
AnnaBridge 171:3a7713b1edbc 11006 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11007 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11008 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11009 * |[31:0] |TX |Data Transmit Register
AnnaBridge 171:3a7713b1edbc 11010 * | | |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
AnnaBridge 171:3a7713b1edbc 11011 * | | |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
AnnaBridge 171:3a7713b1edbc 11012 * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
AnnaBridge 171:3a7713b1edbc 11013 * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
AnnaBridge 171:3a7713b1edbc 11014 * | | |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
AnnaBridge 171:3a7713b1edbc 11015 * @var SPI_T::RX
AnnaBridge 171:3a7713b1edbc 11016 * Offset: 0x30 Data Receive Register
AnnaBridge 171:3a7713b1edbc 11017 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11018 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11019 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11020 * |[31:0] |RX |Data Receive Register
AnnaBridge 171:3a7713b1edbc 11021 * | | |There are 8-/4-level FIFO buffers in this controller.
AnnaBridge 171:3a7713b1edbc 11022 * | | |The data receive register holds the data received from SPI data input pin.
AnnaBridge 171:3a7713b1edbc 11023 * | | |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
AnnaBridge 171:3a7713b1edbc 11024 * | | |This is a read only register.
AnnaBridge 171:3a7713b1edbc 11025 * @var SPI_T::I2SCTL
AnnaBridge 171:3a7713b1edbc 11026 * Offset: 0x60 I2S Control Register
AnnaBridge 171:3a7713b1edbc 11027 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11028 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11029 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11030 * |[0] |I2SEN |I2S Controller Enable Bit
AnnaBridge 171:3a7713b1edbc 11031 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 11032 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 11033 * | | |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
AnnaBridge 171:3a7713b1edbc 11034 * |[1] |TXEN |Transmit Enable Bit
AnnaBridge 171:3a7713b1edbc 11035 * | | |0 = Data transmit Disabled.
AnnaBridge 171:3a7713b1edbc 11036 * | | |1 = Data transmit Enabled.
AnnaBridge 171:3a7713b1edbc 11037 * |[2] |RXEN |Receive Enable Bit
AnnaBridge 171:3a7713b1edbc 11038 * | | |0 = Data receiving Disabled.
AnnaBridge 171:3a7713b1edbc 11039 * | | |1 = Data receiving Enabled.
AnnaBridge 171:3a7713b1edbc 11040 * |[3] |MUTE |Transmit Mute Enable Bit
AnnaBridge 171:3a7713b1edbc 11041 * | | |0 = Transmit data is shifted from buffer.
AnnaBridge 171:3a7713b1edbc 11042 * | | |1= Transmit channel zero.
AnnaBridge 171:3a7713b1edbc 11043 * |[5:4] |WDWIDTH |Word Width
AnnaBridge 171:3a7713b1edbc 11044 * | | |00 = data is 8-bit.
AnnaBridge 171:3a7713b1edbc 11045 * | | |01 = data is 16-bit.
AnnaBridge 171:3a7713b1edbc 11046 * | | |10 = data is 24-bit.
AnnaBridge 171:3a7713b1edbc 11047 * | | |11 = data is 32-bit.
AnnaBridge 171:3a7713b1edbc 11048 * |[6] |MONO |Monaural Data
AnnaBridge 171:3a7713b1edbc 11049 * | | |0 = Data is stereo format.
AnnaBridge 171:3a7713b1edbc 11050 * | | |1 = Data is monaural format.
AnnaBridge 171:3a7713b1edbc 11051 * |[7] |ORDER |Stereo Data Order In FIFO
AnnaBridge 171:3a7713b1edbc 11052 * | | |0 = Left channel data at high byte.
AnnaBridge 171:3a7713b1edbc 11053 * | | |1 = Left channel data at low byte.
AnnaBridge 171:3a7713b1edbc 11054 * |[8] |SLAVE |Slave Mode
AnnaBridge 171:3a7713b1edbc 11055 * | | |I2S can operate as master or slave.
AnnaBridge 171:3a7713b1edbc 11056 * | | |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
AnnaBridge 171:3a7713b1edbc 11057 * | | |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
AnnaBridge 171:3a7713b1edbc 11058 * | | |0 = Master mode.
AnnaBridge 171:3a7713b1edbc 11059 * | | |1 = Slave mode.
AnnaBridge 171:3a7713b1edbc 11060 * |[15] |MCLKEN |Master Clock Enable Bit
AnnaBridge 171:3a7713b1edbc 11061 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
AnnaBridge 171:3a7713b1edbc 11062 * | | |0 = Master clock Disabled.
AnnaBridge 171:3a7713b1edbc 11063 * | | |1 = Master clock Enabled.
AnnaBridge 171:3a7713b1edbc 11064 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 11065 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
AnnaBridge 171:3a7713b1edbc 11066 * | | |This function is only available in transmit operation.
AnnaBridge 171:3a7713b1edbc 11067 * | | |0 = Right channel zero cross detection Disabled.
AnnaBridge 171:3a7713b1edbc 11068 * | | |1 = Right channel zero cross detection Enabled.
AnnaBridge 171:3a7713b1edbc 11069 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 11070 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
AnnaBridge 171:3a7713b1edbc 11071 * | | |This function is only available in transmit operation.
AnnaBridge 171:3a7713b1edbc 11072 * | | |0 = Left channel zero cross detection Disabled.
AnnaBridge 171:3a7713b1edbc 11073 * | | |1 = Left channel zero cross detection Enabled.
AnnaBridge 171:3a7713b1edbc 11074 * |[23] |RXLCH |Receive Left Channel Enable Bit
AnnaBridge 171:3a7713b1edbc 11075 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
AnnaBridge 171:3a7713b1edbc 11076 * | | |0 = Receive right channel data in Mono mode.
AnnaBridge 171:3a7713b1edbc 11077 * | | |1 = Receive left channel data in Mono mode.
AnnaBridge 171:3a7713b1edbc 11078 * |[24] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 11079 * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
AnnaBridge 171:3a7713b1edbc 11080 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 11081 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 11082 * |[25] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 11083 * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
AnnaBridge 171:3a7713b1edbc 11084 * | | |0 = Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 11085 * | | |1 = Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 11086 * |[29:28] |FORMAT |Data Format Selection
AnnaBridge 171:3a7713b1edbc 11087 * | | |00 = I2S data format.
AnnaBridge 171:3a7713b1edbc 11088 * | | |01 = MSB justified data format.
AnnaBridge 171:3a7713b1edbc 11089 * | | |10 = PCM mode A.
AnnaBridge 171:3a7713b1edbc 11090 * | | |11 = PCM mode B.
AnnaBridge 171:3a7713b1edbc 11091 * @var SPI_T::I2SCLK
AnnaBridge 171:3a7713b1edbc 11092 * Offset: 0x64 I2S Clock Divider Control Register
AnnaBridge 171:3a7713b1edbc 11093 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11094 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11095 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11096 * |[5:0] |MCLKDIV |Master Clock Divider
AnnaBridge 171:3a7713b1edbc 11097 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
AnnaBridge 171:3a7713b1edbc 11098 * | | |The master clock rate, F_MCLK, is determined by the following expressions.
AnnaBridge 171:3a7713b1edbc 11099 * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
AnnaBridge 171:3a7713b1edbc 11100 * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
AnnaBridge 171:3a7713b1edbc 11101 * | | |F_I2SCLK is the frequency of I2S peripheral clock.
AnnaBridge 171:3a7713b1edbc 11102 * | | |In general, the master clock rate is 256 times sampling clock rate.
AnnaBridge 171:3a7713b1edbc 11103 * |[16:8] |BCLKDIV |Bit Clock Divider
AnnaBridge 171:3a7713b1edbc 11104 * | | |The I2S controller will generate bit clock in Master mode.
AnnaBridge 171:3a7713b1edbc 11105 * | | |The bit clock rate, F_BCLK, is determined by the following expression.
AnnaBridge 171:3a7713b1edbc 11106 * | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
AnnaBridge 171:3a7713b1edbc 11107 * @var SPI_T::I2SSTS
AnnaBridge 171:3a7713b1edbc 11108 * Offset: 0x68 I2S Status Register
AnnaBridge 171:3a7713b1edbc 11109 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11110 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11111 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11112 * |[4] |RIGHT |Right Channel (Read Only)
AnnaBridge 171:3a7713b1edbc 11113 * | | |This bit indicates the current transmit data is belong to which channel.
AnnaBridge 171:3a7713b1edbc 11114 * | | |0 = Left channel.
AnnaBridge 171:3a7713b1edbc 11115 * | | |1 = Right channel.
AnnaBridge 171:3a7713b1edbc 11116 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 11117 * | | |0 = Receive FIFO buffer is not empty.
AnnaBridge 171:3a7713b1edbc 11118 * | | |1 = Receive FIFO buffer is empty.
AnnaBridge 171:3a7713b1edbc 11119 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 11120 * | | |0 = Receive FIFO buffer is not full.
AnnaBridge 171:3a7713b1edbc 11121 * | | |1 = Receive FIFO buffer is full.
AnnaBridge 171:3a7713b1edbc 11122 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 11123 * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
AnnaBridge 171:3a7713b1edbc 11124 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
AnnaBridge 171:3a7713b1edbc 11125 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
AnnaBridge 171:3a7713b1edbc 11126 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11127 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 11128 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 11129 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11130 * | | |0 = No receive FIFO time-out event.
AnnaBridge 171:3a7713b1edbc 11131 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
AnnaBridge 171:3a7713b1edbc 11132 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 11133 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 11134 * |[15] |I2SENSTS |I2S Enable Status (Read Only)
AnnaBridge 171:3a7713b1edbc 11135 * | | |0 = The SPI/I2S control logic is disabled.
AnnaBridge 171:3a7713b1edbc 11136 * | | |1 = The SPI/I2S control logic is enabled.
AnnaBridge 171:3a7713b1edbc 11137 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
AnnaBridge 171:3a7713b1edbc 11138 * | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
AnnaBridge 171:3a7713b1edbc 11139 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 11140 * | | |0 = Transmit FIFO buffer is not empty.
AnnaBridge 171:3a7713b1edbc 11141 * | | |1 = Transmit FIFO buffer is empty.
AnnaBridge 171:3a7713b1edbc 11142 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 11143 * | | |0 = Transmit FIFO buffer is not full.
AnnaBridge 171:3a7713b1edbc 11144 * | | |1 = Transmit FIFO buffer is full.
AnnaBridge 171:3a7713b1edbc 11145 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 11146 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
AnnaBridge 171:3a7713b1edbc 11147 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
AnnaBridge 171:3a7713b1edbc 11148 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
AnnaBridge 171:3a7713b1edbc 11149 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11150 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
AnnaBridge 171:3a7713b1edbc 11151 * | | | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
AnnaBridge 171:3a7713b1edbc 11152 * | | |Note: This bit will be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 11153 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11154 * | | |0 = No zero cross event occurred on right channel.
AnnaBridge 171:3a7713b1edbc 11155 * | | |1 = Zero cross event occurred on right channel.
AnnaBridge 171:3a7713b1edbc 11156 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11157 * | | |0 = No zero cross event occurred on left channel.
AnnaBridge 171:3a7713b1edbc 11158 * | | |1 = Zero cross event occurred on left channel.
AnnaBridge 171:3a7713b1edbc 11159 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
AnnaBridge 171:3a7713b1edbc 11160 * | | |0 = The reset function of TXRST or RXRST is done.
AnnaBridge 171:3a7713b1edbc 11161 * | | |1 = Doing the reset function of TXRST or RXRST.
AnnaBridge 171:3a7713b1edbc 11162 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
AnnaBridge 171:3a7713b1edbc 11163 * | | |User can check the status of this bit to monitor the reset function is doing or done.
AnnaBridge 171:3a7713b1edbc 11164 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
AnnaBridge 171:3a7713b1edbc 11165 * | | |This bit field indicates the valid data count of receive FIFO buffer.
AnnaBridge 171:3a7713b1edbc 11166 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
AnnaBridge 171:3a7713b1edbc 11167 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
AnnaBridge 171:3a7713b1edbc 11168 */
AnnaBridge 171:3a7713b1edbc 11169
AnnaBridge 171:3a7713b1edbc 11170 __IO uint32_t CTL; /* Offset: 0x00 Control Register */
AnnaBridge 171:3a7713b1edbc 11171 __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
AnnaBridge 171:3a7713b1edbc 11172 __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
AnnaBridge 171:3a7713b1edbc 11173 __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
AnnaBridge 171:3a7713b1edbc 11174 __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 11175 __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
AnnaBridge 171:3a7713b1edbc 11176 __I uint32_t RESERVE0[2];
AnnaBridge 171:3a7713b1edbc 11177 __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
AnnaBridge 171:3a7713b1edbc 11178 __I uint32_t RESERVE1[3];
AnnaBridge 171:3a7713b1edbc 11179 __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
AnnaBridge 171:3a7713b1edbc 11180 __I uint32_t RESERVE2[11];
AnnaBridge 171:3a7713b1edbc 11181 __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
AnnaBridge 171:3a7713b1edbc 11182 __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
AnnaBridge 171:3a7713b1edbc 11183 __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
AnnaBridge 171:3a7713b1edbc 11184
AnnaBridge 171:3a7713b1edbc 11185 } SPI_T;
AnnaBridge 171:3a7713b1edbc 11186
AnnaBridge 171:3a7713b1edbc 11187
AnnaBridge 171:3a7713b1edbc 11188
AnnaBridge 171:3a7713b1edbc 11189 /**
AnnaBridge 171:3a7713b1edbc 11190 @addtogroup SPI_CONST SPI Bit Field Definition
AnnaBridge 171:3a7713b1edbc 11191 Constant Definitions for SPI Controller
AnnaBridge 171:3a7713b1edbc 11192 @{ */
AnnaBridge 171:3a7713b1edbc 11193
AnnaBridge 171:3a7713b1edbc 11194 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
AnnaBridge 171:3a7713b1edbc 11195 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
AnnaBridge 171:3a7713b1edbc 11196
AnnaBridge 171:3a7713b1edbc 11197 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
AnnaBridge 171:3a7713b1edbc 11198 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
AnnaBridge 171:3a7713b1edbc 11199
AnnaBridge 171:3a7713b1edbc 11200 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
AnnaBridge 171:3a7713b1edbc 11201 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
AnnaBridge 171:3a7713b1edbc 11202
AnnaBridge 171:3a7713b1edbc 11203 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
AnnaBridge 171:3a7713b1edbc 11204 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
AnnaBridge 171:3a7713b1edbc 11205
AnnaBridge 171:3a7713b1edbc 11206 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
AnnaBridge 171:3a7713b1edbc 11207 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
AnnaBridge 171:3a7713b1edbc 11208
AnnaBridge 171:3a7713b1edbc 11209 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
AnnaBridge 171:3a7713b1edbc 11210 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
AnnaBridge 171:3a7713b1edbc 11211
AnnaBridge 171:3a7713b1edbc 11212 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
AnnaBridge 171:3a7713b1edbc 11213 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
AnnaBridge 171:3a7713b1edbc 11214
AnnaBridge 171:3a7713b1edbc 11215 #define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
AnnaBridge 171:3a7713b1edbc 11216 #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
AnnaBridge 171:3a7713b1edbc 11217
AnnaBridge 171:3a7713b1edbc 11218 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
AnnaBridge 171:3a7713b1edbc 11219 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
AnnaBridge 171:3a7713b1edbc 11220
AnnaBridge 171:3a7713b1edbc 11221 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
AnnaBridge 171:3a7713b1edbc 11222 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
AnnaBridge 171:3a7713b1edbc 11223
AnnaBridge 171:3a7713b1edbc 11224 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
AnnaBridge 171:3a7713b1edbc 11225 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
AnnaBridge 171:3a7713b1edbc 11226
AnnaBridge 171:3a7713b1edbc 11227 #define SPI_CTL_QDIODIR_Pos (20) /*!< SPI_T::CTL: QDIODIR Position */
AnnaBridge 171:3a7713b1edbc 11228 #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI_T::CTL: QDIODIR Mask */
AnnaBridge 171:3a7713b1edbc 11229
AnnaBridge 171:3a7713b1edbc 11230 #define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
AnnaBridge 171:3a7713b1edbc 11231 #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
AnnaBridge 171:3a7713b1edbc 11232
AnnaBridge 171:3a7713b1edbc 11233 #define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
AnnaBridge 171:3a7713b1edbc 11234 #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
AnnaBridge 171:3a7713b1edbc 11235
AnnaBridge 171:3a7713b1edbc 11236 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
AnnaBridge 171:3a7713b1edbc 11237 #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
AnnaBridge 171:3a7713b1edbc 11238
AnnaBridge 171:3a7713b1edbc 11239 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
AnnaBridge 171:3a7713b1edbc 11240 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
AnnaBridge 171:3a7713b1edbc 11241
AnnaBridge 171:3a7713b1edbc 11242 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
AnnaBridge 171:3a7713b1edbc 11243 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
AnnaBridge 171:3a7713b1edbc 11244
AnnaBridge 171:3a7713b1edbc 11245 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
AnnaBridge 171:3a7713b1edbc 11246 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
AnnaBridge 171:3a7713b1edbc 11247
AnnaBridge 171:3a7713b1edbc 11248 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
AnnaBridge 171:3a7713b1edbc 11249 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
AnnaBridge 171:3a7713b1edbc 11250
AnnaBridge 171:3a7713b1edbc 11251 #define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
AnnaBridge 171:3a7713b1edbc 11252 #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
AnnaBridge 171:3a7713b1edbc 11253
AnnaBridge 171:3a7713b1edbc 11254 #define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
AnnaBridge 171:3a7713b1edbc 11255 #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
AnnaBridge 171:3a7713b1edbc 11256
AnnaBridge 171:3a7713b1edbc 11257 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
AnnaBridge 171:3a7713b1edbc 11258 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
AnnaBridge 171:3a7713b1edbc 11259
AnnaBridge 171:3a7713b1edbc 11260 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
AnnaBridge 171:3a7713b1edbc 11261 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
AnnaBridge 171:3a7713b1edbc 11262
AnnaBridge 171:3a7713b1edbc 11263 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
AnnaBridge 171:3a7713b1edbc 11264 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
AnnaBridge 171:3a7713b1edbc 11265
AnnaBridge 171:3a7713b1edbc 11266 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
AnnaBridge 171:3a7713b1edbc 11267 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
AnnaBridge 171:3a7713b1edbc 11268
AnnaBridge 171:3a7713b1edbc 11269 #define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
AnnaBridge 171:3a7713b1edbc 11270 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
AnnaBridge 171:3a7713b1edbc 11271
AnnaBridge 171:3a7713b1edbc 11272 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
AnnaBridge 171:3a7713b1edbc 11273 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
AnnaBridge 171:3a7713b1edbc 11274
AnnaBridge 171:3a7713b1edbc 11275 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
AnnaBridge 171:3a7713b1edbc 11276 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
AnnaBridge 171:3a7713b1edbc 11277
AnnaBridge 171:3a7713b1edbc 11278 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
AnnaBridge 171:3a7713b1edbc 11279 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
AnnaBridge 171:3a7713b1edbc 11280
AnnaBridge 171:3a7713b1edbc 11281 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
AnnaBridge 171:3a7713b1edbc 11282 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
AnnaBridge 171:3a7713b1edbc 11283
AnnaBridge 171:3a7713b1edbc 11284 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
AnnaBridge 171:3a7713b1edbc 11285 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
AnnaBridge 171:3a7713b1edbc 11286
AnnaBridge 171:3a7713b1edbc 11287 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
AnnaBridge 171:3a7713b1edbc 11288 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
AnnaBridge 171:3a7713b1edbc 11289
AnnaBridge 171:3a7713b1edbc 11290 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
AnnaBridge 171:3a7713b1edbc 11291 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
AnnaBridge 171:3a7713b1edbc 11292
AnnaBridge 171:3a7713b1edbc 11293 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
AnnaBridge 171:3a7713b1edbc 11294 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
AnnaBridge 171:3a7713b1edbc 11295
AnnaBridge 171:3a7713b1edbc 11296 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
AnnaBridge 171:3a7713b1edbc 11297 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
AnnaBridge 171:3a7713b1edbc 11298
AnnaBridge 171:3a7713b1edbc 11299 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
AnnaBridge 171:3a7713b1edbc 11300 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
AnnaBridge 171:3a7713b1edbc 11301
AnnaBridge 171:3a7713b1edbc 11302 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
AnnaBridge 171:3a7713b1edbc 11303 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
AnnaBridge 171:3a7713b1edbc 11304
AnnaBridge 171:3a7713b1edbc 11305 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
AnnaBridge 171:3a7713b1edbc 11306 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
AnnaBridge 171:3a7713b1edbc 11307
AnnaBridge 171:3a7713b1edbc 11308 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
AnnaBridge 171:3a7713b1edbc 11309 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
AnnaBridge 171:3a7713b1edbc 11310
AnnaBridge 171:3a7713b1edbc 11311 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
AnnaBridge 171:3a7713b1edbc 11312 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
AnnaBridge 171:3a7713b1edbc 11313
AnnaBridge 171:3a7713b1edbc 11314 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
AnnaBridge 171:3a7713b1edbc 11315 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
AnnaBridge 171:3a7713b1edbc 11316
AnnaBridge 171:3a7713b1edbc 11317 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
AnnaBridge 171:3a7713b1edbc 11318 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 11319
AnnaBridge 171:3a7713b1edbc 11320 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
AnnaBridge 171:3a7713b1edbc 11321 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
AnnaBridge 171:3a7713b1edbc 11322
AnnaBridge 171:3a7713b1edbc 11323 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
AnnaBridge 171:3a7713b1edbc 11324 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
AnnaBridge 171:3a7713b1edbc 11325
AnnaBridge 171:3a7713b1edbc 11326 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
AnnaBridge 171:3a7713b1edbc 11327 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
AnnaBridge 171:3a7713b1edbc 11328
AnnaBridge 171:3a7713b1edbc 11329 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
AnnaBridge 171:3a7713b1edbc 11330 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
AnnaBridge 171:3a7713b1edbc 11331
AnnaBridge 171:3a7713b1edbc 11332 #define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
AnnaBridge 171:3a7713b1edbc 11333 #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
AnnaBridge 171:3a7713b1edbc 11334
AnnaBridge 171:3a7713b1edbc 11335 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
AnnaBridge 171:3a7713b1edbc 11336 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
AnnaBridge 171:3a7713b1edbc 11337
AnnaBridge 171:3a7713b1edbc 11338 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
AnnaBridge 171:3a7713b1edbc 11339 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
AnnaBridge 171:3a7713b1edbc 11340
AnnaBridge 171:3a7713b1edbc 11341 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 11342 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 11343
AnnaBridge 171:3a7713b1edbc 11344 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
AnnaBridge 171:3a7713b1edbc 11345 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
AnnaBridge 171:3a7713b1edbc 11346
AnnaBridge 171:3a7713b1edbc 11347 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
AnnaBridge 171:3a7713b1edbc 11348 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
AnnaBridge 171:3a7713b1edbc 11349
AnnaBridge 171:3a7713b1edbc 11350 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
AnnaBridge 171:3a7713b1edbc 11351 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
AnnaBridge 171:3a7713b1edbc 11352
AnnaBridge 171:3a7713b1edbc 11353 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
AnnaBridge 171:3a7713b1edbc 11354 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
AnnaBridge 171:3a7713b1edbc 11355
AnnaBridge 171:3a7713b1edbc 11356 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
AnnaBridge 171:3a7713b1edbc 11357 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
AnnaBridge 171:3a7713b1edbc 11358
AnnaBridge 171:3a7713b1edbc 11359 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 11360 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 11361
AnnaBridge 171:3a7713b1edbc 11362 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
AnnaBridge 171:3a7713b1edbc 11363 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
AnnaBridge 171:3a7713b1edbc 11364
AnnaBridge 171:3a7713b1edbc 11365 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
AnnaBridge 171:3a7713b1edbc 11366 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
AnnaBridge 171:3a7713b1edbc 11367
AnnaBridge 171:3a7713b1edbc 11368 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
AnnaBridge 171:3a7713b1edbc 11369 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
AnnaBridge 171:3a7713b1edbc 11370
AnnaBridge 171:3a7713b1edbc 11371 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
AnnaBridge 171:3a7713b1edbc 11372 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
AnnaBridge 171:3a7713b1edbc 11373
AnnaBridge 171:3a7713b1edbc 11374 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
AnnaBridge 171:3a7713b1edbc 11375 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
AnnaBridge 171:3a7713b1edbc 11376
AnnaBridge 171:3a7713b1edbc 11377 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
AnnaBridge 171:3a7713b1edbc 11378 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
AnnaBridge 171:3a7713b1edbc 11379
AnnaBridge 171:3a7713b1edbc 11380 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
AnnaBridge 171:3a7713b1edbc 11381 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
AnnaBridge 171:3a7713b1edbc 11382
AnnaBridge 171:3a7713b1edbc 11383 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
AnnaBridge 171:3a7713b1edbc 11384 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
AnnaBridge 171:3a7713b1edbc 11385
AnnaBridge 171:3a7713b1edbc 11386 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
AnnaBridge 171:3a7713b1edbc 11387 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
AnnaBridge 171:3a7713b1edbc 11388
AnnaBridge 171:3a7713b1edbc 11389 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
AnnaBridge 171:3a7713b1edbc 11390 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
AnnaBridge 171:3a7713b1edbc 11391
AnnaBridge 171:3a7713b1edbc 11392 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
AnnaBridge 171:3a7713b1edbc 11393 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
AnnaBridge 171:3a7713b1edbc 11394
AnnaBridge 171:3a7713b1edbc 11395 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
AnnaBridge 171:3a7713b1edbc 11396 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
AnnaBridge 171:3a7713b1edbc 11397
AnnaBridge 171:3a7713b1edbc 11398 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
AnnaBridge 171:3a7713b1edbc 11399 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
AnnaBridge 171:3a7713b1edbc 11400
AnnaBridge 171:3a7713b1edbc 11401 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
AnnaBridge 171:3a7713b1edbc 11402 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
AnnaBridge 171:3a7713b1edbc 11403
AnnaBridge 171:3a7713b1edbc 11404 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
AnnaBridge 171:3a7713b1edbc 11405 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
AnnaBridge 171:3a7713b1edbc 11406
AnnaBridge 171:3a7713b1edbc 11407 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
AnnaBridge 171:3a7713b1edbc 11408 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
AnnaBridge 171:3a7713b1edbc 11409
AnnaBridge 171:3a7713b1edbc 11410 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
AnnaBridge 171:3a7713b1edbc 11411 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
AnnaBridge 171:3a7713b1edbc 11412
AnnaBridge 171:3a7713b1edbc 11413 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
AnnaBridge 171:3a7713b1edbc 11414 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
AnnaBridge 171:3a7713b1edbc 11415
AnnaBridge 171:3a7713b1edbc 11416 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
AnnaBridge 171:3a7713b1edbc 11417 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
AnnaBridge 171:3a7713b1edbc 11418
AnnaBridge 171:3a7713b1edbc 11419 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
AnnaBridge 171:3a7713b1edbc 11420 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
AnnaBridge 171:3a7713b1edbc 11421
AnnaBridge 171:3a7713b1edbc 11422 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
AnnaBridge 171:3a7713b1edbc 11423 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
AnnaBridge 171:3a7713b1edbc 11424
AnnaBridge 171:3a7713b1edbc 11425 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
AnnaBridge 171:3a7713b1edbc 11426 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
AnnaBridge 171:3a7713b1edbc 11427
AnnaBridge 171:3a7713b1edbc 11428 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
AnnaBridge 171:3a7713b1edbc 11429 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
AnnaBridge 171:3a7713b1edbc 11430
AnnaBridge 171:3a7713b1edbc 11431 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
AnnaBridge 171:3a7713b1edbc 11432 #define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
AnnaBridge 171:3a7713b1edbc 11433
AnnaBridge 171:3a7713b1edbc 11434 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
AnnaBridge 171:3a7713b1edbc 11435 #define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
AnnaBridge 171:3a7713b1edbc 11436
AnnaBridge 171:3a7713b1edbc 11437 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
AnnaBridge 171:3a7713b1edbc 11438 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
AnnaBridge 171:3a7713b1edbc 11439
AnnaBridge 171:3a7713b1edbc 11440 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 11441 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 11442
AnnaBridge 171:3a7713b1edbc 11443 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
AnnaBridge 171:3a7713b1edbc 11444 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
AnnaBridge 171:3a7713b1edbc 11445
AnnaBridge 171:3a7713b1edbc 11446 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
AnnaBridge 171:3a7713b1edbc 11447 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
AnnaBridge 171:3a7713b1edbc 11448
AnnaBridge 171:3a7713b1edbc 11449 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
AnnaBridge 171:3a7713b1edbc 11450 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
AnnaBridge 171:3a7713b1edbc 11451
AnnaBridge 171:3a7713b1edbc 11452 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
AnnaBridge 171:3a7713b1edbc 11453 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
AnnaBridge 171:3a7713b1edbc 11454
AnnaBridge 171:3a7713b1edbc 11455 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
AnnaBridge 171:3a7713b1edbc 11456 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
AnnaBridge 171:3a7713b1edbc 11457
AnnaBridge 171:3a7713b1edbc 11458 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 11459 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 11460
AnnaBridge 171:3a7713b1edbc 11461 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
AnnaBridge 171:3a7713b1edbc 11462 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
AnnaBridge 171:3a7713b1edbc 11463
AnnaBridge 171:3a7713b1edbc 11464 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
AnnaBridge 171:3a7713b1edbc 11465 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
AnnaBridge 171:3a7713b1edbc 11466
AnnaBridge 171:3a7713b1edbc 11467 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
AnnaBridge 171:3a7713b1edbc 11468 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
AnnaBridge 171:3a7713b1edbc 11469
AnnaBridge 171:3a7713b1edbc 11470 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
AnnaBridge 171:3a7713b1edbc 11471 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
AnnaBridge 171:3a7713b1edbc 11472
AnnaBridge 171:3a7713b1edbc 11473 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
AnnaBridge 171:3a7713b1edbc 11474 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
AnnaBridge 171:3a7713b1edbc 11475
AnnaBridge 171:3a7713b1edbc 11476 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
AnnaBridge 171:3a7713b1edbc 11477 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
AnnaBridge 171:3a7713b1edbc 11478
AnnaBridge 171:3a7713b1edbc 11479 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
AnnaBridge 171:3a7713b1edbc 11480 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
AnnaBridge 171:3a7713b1edbc 11481
AnnaBridge 171:3a7713b1edbc 11482 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
AnnaBridge 171:3a7713b1edbc 11483 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
AnnaBridge 171:3a7713b1edbc 11484
AnnaBridge 171:3a7713b1edbc 11485 /**@}*/ /* SPI_CONST */
AnnaBridge 171:3a7713b1edbc 11486 /**@}*/ /* end of SPI register group */
AnnaBridge 171:3a7713b1edbc 11487
AnnaBridge 171:3a7713b1edbc 11488
AnnaBridge 171:3a7713b1edbc 11489 /*---------------------- System Manger Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 11490 /**
AnnaBridge 171:3a7713b1edbc 11491 @addtogroup SYS System Manger Controller(SYS)
AnnaBridge 171:3a7713b1edbc 11492 Memory Mapped Structure for SYS Controller
AnnaBridge 171:3a7713b1edbc 11493 @{ */
AnnaBridge 171:3a7713b1edbc 11494
AnnaBridge 171:3a7713b1edbc 11495
AnnaBridge 171:3a7713b1edbc 11496 typedef struct
AnnaBridge 171:3a7713b1edbc 11497 {
AnnaBridge 171:3a7713b1edbc 11498
AnnaBridge 171:3a7713b1edbc 11499 /**
AnnaBridge 171:3a7713b1edbc 11500 * @var SYS_T::PDID
AnnaBridge 171:3a7713b1edbc 11501 * Offset: 0x00 Part Device Identification Number Register
AnnaBridge 171:3a7713b1edbc 11502 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11503 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11504 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11505 * |[31:0] |PDID |Part Device Identification Number (Read Only)
AnnaBridge 171:3a7713b1edbc 11506 * | | |This register reflects device part number code.
AnnaBridge 171:3a7713b1edbc 11507 * | | |Software can read this register to identify which device is used.
AnnaBridge 171:3a7713b1edbc 11508 * @var SYS_T::RSTSTS
AnnaBridge 171:3a7713b1edbc 11509 * Offset: 0x04 System Reset Status Register
AnnaBridge 171:3a7713b1edbc 11510 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11511 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11512 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11513 * |[0] |PORF |POR Reset Flag
AnnaBridge 171:3a7713b1edbc 11514 * | | |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11515 * | | |0 = No reset from POR or CHIPRST.
AnnaBridge 171:3a7713b1edbc 11516 * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
AnnaBridge 171:3a7713b1edbc 11517 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11518 * |[1] |PINRF |nRESET Pin Reset Flag
AnnaBridge 171:3a7713b1edbc 11519 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11520 * | | |0 = No reset from nRESET pin.
AnnaBridge 171:3a7713b1edbc 11521 * | | |1 = Pin nRESET had issued the reset signal to reset the system.
AnnaBridge 171:3a7713b1edbc 11522 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11523 * |[2] |WDTRF |WDT Reset Flag
AnnaBridge 171:3a7713b1edbc 11524 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11525 * | | |0 = No reset from watchdog timer or window watchdog timer.
AnnaBridge 171:3a7713b1edbc 11526 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
AnnaBridge 171:3a7713b1edbc 11527 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 11528 * | | |Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11529 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
AnnaBridge 171:3a7713b1edbc 11530 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
AnnaBridge 171:3a7713b1edbc 11531 * |[3] |LVRF |LVR Reset Flag
AnnaBridge 171:3a7713b1edbc 11532 * | | |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11533 * | | |0 = No reset from LVR.
AnnaBridge 171:3a7713b1edbc 11534 * | | |1 = LVR controller had issued the reset signal to reset the system.
AnnaBridge 171:3a7713b1edbc 11535 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11536 * |[4] |BODRF |BOD Reset Flag
AnnaBridge 171:3a7713b1edbc 11537 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11538 * | | |0 = No reset from BOD.
AnnaBridge 171:3a7713b1edbc 11539 * | | |1 = The BOD had issued the reset signal to reset the system.
AnnaBridge 171:3a7713b1edbc 11540 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11541 * |[5] |SYSRF |System Reset Flag
AnnaBridge 171:3a7713b1edbc 11542 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
AnnaBridge 171:3a7713b1edbc 11543 * | | |0 = No reset from Cortex-M4.
AnnaBridge 171:3a7713b1edbc 11544 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
AnnaBridge 171:3a7713b1edbc 11545 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11546 * |[7] |CPURF |CPU Reset Flag
AnnaBridge 171:3a7713b1edbc 11547 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
AnnaBridge 171:3a7713b1edbc 11548 * | | |0 = No reset from CPU.
AnnaBridge 171:3a7713b1edbc 11549 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
AnnaBridge 171:3a7713b1edbc 11550 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11551 * |[8] |CPULKRF |CPU Lockup Reset Flag
AnnaBridge 171:3a7713b1edbc 11552 * | | |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
AnnaBridge 171:3a7713b1edbc 11553 * | | |0 = No reset from CPU lockup happened.
AnnaBridge 171:3a7713b1edbc 11554 * | | |1 = The Cortex-M4 lockup happened and chip is reset.
AnnaBridge 171:3a7713b1edbc 11555 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11556 * @var SYS_T::IPRST0
AnnaBridge 171:3a7713b1edbc 11557 * Offset: 0x08 Peripheral Reset Control Register 0
AnnaBridge 171:3a7713b1edbc 11558 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11559 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11560 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11561 * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11562 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
AnnaBridge 171:3a7713b1edbc 11563 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
AnnaBridge 171:3a7713b1edbc 11564 * | | |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
AnnaBridge 171:3a7713b1edbc 11565 * | | |0 = Chip normal operation.
AnnaBridge 171:3a7713b1edbc 11566 * | | |1 = Chip one shot reset.
AnnaBridge 171:3a7713b1edbc 11567 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11568 * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11569 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
AnnaBridge 171:3a7713b1edbc 11570 * | | |0 = Processor core normal operation.
AnnaBridge 171:3a7713b1edbc 11571 * | | |1 = Processor core one-shot reset.
AnnaBridge 171:3a7713b1edbc 11572 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11573 * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11574 * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
AnnaBridge 171:3a7713b1edbc 11575 * | | |User needs to set this bit to 0 to release from reset state.
AnnaBridge 171:3a7713b1edbc 11576 * | | |0 = PDMA controller normal operation.
AnnaBridge 171:3a7713b1edbc 11577 * | | |1 = PDMA controller reset.
AnnaBridge 171:3a7713b1edbc 11578 * |[3] |EBIRST |EBI Controller Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11579 * | | |Set this bit to 1 will generate a reset signal to the EBI.
AnnaBridge 171:3a7713b1edbc 11580 * | | |User needs to set this bit to 0 to release from the reset state.
AnnaBridge 171:3a7713b1edbc 11581 * | | |0 = EBI controller normal operation.
AnnaBridge 171:3a7713b1edbc 11582 * | | |1 = EBI controller reset.
AnnaBridge 171:3a7713b1edbc 11583 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11584 * |[4] |USBHRST |USBH Controller Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11585 * | | |Set this bit to 1 will generate a reset signal to the USB host controller.
AnnaBridge 171:3a7713b1edbc 11586 * | | |User needs to set this bit to 0 to release from the reset state.
AnnaBridge 171:3a7713b1edbc 11587 * | | |0 = USBH controller normal operation.
AnnaBridge 171:3a7713b1edbc 11588 * | | |1 = USBH controller reset.
AnnaBridge 171:3a7713b1edbc 11589 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11590 * |[7] |CRCRST |CRC Calculation Unit Reset (Write Protect)
AnnaBridge 171:3a7713b1edbc 11591 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation module.
AnnaBridge 171:3a7713b1edbc 11592 * | | |User needs to set this bit to 0 to release from the reset state.
AnnaBridge 171:3a7713b1edbc 11593 * | | |0 = CRC Calculation unit normal operation.
AnnaBridge 171:3a7713b1edbc 11594 * | | |1 = CRC Calculation unit reset.
AnnaBridge 171:3a7713b1edbc 11595 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11596 * @var SYS_T::IPRST1
AnnaBridge 171:3a7713b1edbc 11597 * Offset: 0x0C Peripheral Reset Control Register 1
AnnaBridge 171:3a7713b1edbc 11598 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11599 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11600 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11601 * |[1] |GPIORST |GPIO Controller Reset
AnnaBridge 171:3a7713b1edbc 11602 * | | |0 = GPIO controller normal operation.
AnnaBridge 171:3a7713b1edbc 11603 * | | |1 = GPIO controller reset.
AnnaBridge 171:3a7713b1edbc 11604 * |[2] |TMR0RST |Timer0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11605 * | | |0 = Timer0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11606 * | | |1 = Timer0 controller reset.
AnnaBridge 171:3a7713b1edbc 11607 * |[3] |TMR1RST |Timer1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11608 * | | |0 = Timer1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11609 * | | |1 = Timer1 controller reset.
AnnaBridge 171:3a7713b1edbc 11610 * |[4] |TMR2RST |Timer2 Controller Reset
AnnaBridge 171:3a7713b1edbc 11611 * | | |0 = Timer2 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11612 * | | |1 = Timer2 controller reset.
AnnaBridge 171:3a7713b1edbc 11613 * |[5] |TMR3RST |Timer3 Controller Reset
AnnaBridge 171:3a7713b1edbc 11614 * | | |0 = Timer3 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11615 * | | |1 = Timer3 controller reset.
AnnaBridge 171:3a7713b1edbc 11616 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11617 * | | |0 = Analog Comparator 0/1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11618 * | | |1 = Analog Comparator 0/1 controller reset.
AnnaBridge 171:3a7713b1edbc 11619 * |[8] |I2C0RST |I2C0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11620 * | | |0 = I2C0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11621 * | | |1 = I2C0 controller reset.
AnnaBridge 171:3a7713b1edbc 11622 * |[9] |I2C1RST |I2C1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11623 * | | |0 = I2C1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11624 * | | |1 = I2C1 controller reset.
AnnaBridge 171:3a7713b1edbc 11625 * |[12] |SPI0RST |SPI0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11626 * | | |0 = SPI0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11627 * | | |1 = SPI0 controller reset.
AnnaBridge 171:3a7713b1edbc 11628 * |[13] |SPI1RST |SPI1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11629 * | | |0 = SPI1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11630 * | | |1 = SPI1 controller reset.
AnnaBridge 171:3a7713b1edbc 11631 * |[14] |SPI2RST |SPI2 Controller Reset
AnnaBridge 171:3a7713b1edbc 11632 * | | |0 = SPI2 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11633 * | | |1 = SPI2 controller reset.
AnnaBridge 171:3a7713b1edbc 11634 * |[16] |UART0RST |UART0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11635 * | | |0 = UART0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11636 * | | |1 = UART0 controller reset.
AnnaBridge 171:3a7713b1edbc 11637 * |[17] |UART1RST |UART1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11638 * | | |0 = UART1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11639 * | | |1 = UART1 controller reset.
AnnaBridge 171:3a7713b1edbc 11640 * |[18] |UART2RST |UART2 Controller Reset
AnnaBridge 171:3a7713b1edbc 11641 * | | |0 = UART2 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11642 * | | |1 = UART2 controller reset.
AnnaBridge 171:3a7713b1edbc 11643 * |[19] |UART3RST |UART3 Controller Reset
AnnaBridge 171:3a7713b1edbc 11644 * | | |0 = UART3 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11645 * | | |1 = UART3 controller reset.
AnnaBridge 171:3a7713b1edbc 11646 * |[24] |CAN0RST |CAN0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11647 * | | |0 = CAN0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11648 * | | |1 = CAN0 controller reset.
AnnaBridge 171:3a7713b1edbc 11649 * |[26] |OTGRST |OTG Controller Reset
AnnaBridge 171:3a7713b1edbc 11650 * | | |0 = OTG controller normal operation.
AnnaBridge 171:3a7713b1edbc 11651 * | | |1 = OTG controller reset.
AnnaBridge 171:3a7713b1edbc 11652 * |[27] |USBDRST |USB Device Controller Reset
AnnaBridge 171:3a7713b1edbc 11653 * | | |0 = USB device controller normal operation.
AnnaBridge 171:3a7713b1edbc 11654 * | | |1 = USB device controller reset.
AnnaBridge 171:3a7713b1edbc 11655 * |[28] |EADCRST |EADC Controller Reset
AnnaBridge 171:3a7713b1edbc 11656 * | | |0 = EADC controller normal operation.
AnnaBridge 171:3a7713b1edbc 11657 * | | |1 = EADC controller reset.
AnnaBridge 171:3a7713b1edbc 11658 * @var SYS_T::IPRST2
AnnaBridge 171:3a7713b1edbc 11659 * Offset: 0x10 Peripheral Reset Control Register 2
AnnaBridge 171:3a7713b1edbc 11660 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11661 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11662 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11663 * |[0] |SC0RST |SC0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11664 * | | |0 = SC0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11665 * | | |1 = SC0 controller reset.
AnnaBridge 171:3a7713b1edbc 11666 * |[12] |DACRST |DAC Controller Reset
AnnaBridge 171:3a7713b1edbc 11667 * | | |0 = DAC controller normal operation.
AnnaBridge 171:3a7713b1edbc 11668 * | | |1 = DAC controller reset.
AnnaBridge 171:3a7713b1edbc 11669 * |[16] |PWM0RST |PWM0 Controller Reset
AnnaBridge 171:3a7713b1edbc 11670 * | | |0 = PWM0 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11671 * | | |1 = PWM0 controller reset.
AnnaBridge 171:3a7713b1edbc 11672 * |[17] |PWM1RST |PWM1 Controller Reset
AnnaBridge 171:3a7713b1edbc 11673 * | | |0 = PWM1 controller normal operation.
AnnaBridge 171:3a7713b1edbc 11674 * | | |1 = PWM1 controller reset.
AnnaBridge 171:3a7713b1edbc 11675 * |[25] |TKRST |Touch Key Controller Reset
AnnaBridge 171:3a7713b1edbc 11676 * | | |0 = Touch Key controller normal operation.
AnnaBridge 171:3a7713b1edbc 11677 * | | |1 = Touch Key controller reset.
AnnaBridge 171:3a7713b1edbc 11678 * @var SYS_T::BODCTL
AnnaBridge 171:3a7713b1edbc 11679 * Offset: 0x18 Brown-Out Detector Control Register
AnnaBridge 171:3a7713b1edbc 11680 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11681 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11682 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11683 * |[0] |BODEN |Brown-Out Detector Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 11684 * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
AnnaBridge 171:3a7713b1edbc 11685 * | | |0 = Brown-out Detector function Disabled.
AnnaBridge 171:3a7713b1edbc 11686 * | | |1 = Brown-out Detector function Enabled.
AnnaBridge 171:3a7713b1edbc 11687 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11688 * |[2:1] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 11689 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
AnnaBridge 171:3a7713b1edbc 11690 * | | |00 = Brown-Out Detector Threshold Voltage is 2.2V
AnnaBridge 171:3a7713b1edbc 11691 * | | |01 = Brown-Out Detector Threshold Voltage is 2.7V
AnnaBridge 171:3a7713b1edbc 11692 * | | |10 = Brown-Out Detector Threshold Voltage is 3.7V
AnnaBridge 171:3a7713b1edbc 11693 * | | |11 = Brown-Out Detector Threshold Voltage is 4.5V
AnnaBridge 171:3a7713b1edbc 11694 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11695 * |[3] |BODRSTEN |Brown-Out Reset Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 11696 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
AnnaBridge 171:3a7713b1edbc 11697 * | | |0 = Brown-out "INTERRUPT" function Enabled.
AnnaBridge 171:3a7713b1edbc 11698 * | | |1 = Brown-out "RESET" function Enabled.
AnnaBridge 171:3a7713b1edbc 11699 * | | |Note1:
AnnaBridge 171:3a7713b1edbc 11700 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
AnnaBridge 171:3a7713b1edbc 11701 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
AnnaBridge 171:3a7713b1edbc 11702 * | | |BOD interrupt will keep till to the BODEN set to 0.
AnnaBridge 171:3a7713b1edbc 11703 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
AnnaBridge 171:3a7713b1edbc 11704 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11705 * |[4] |BODIF |Brown-Out Detector Interrupt Flag
AnnaBridge 171:3a7713b1edbc 11706 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
AnnaBridge 171:3a7713b1edbc 11707 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 11708 * | | |Note: Write 1 to clear this bit to 0.
AnnaBridge 171:3a7713b1edbc 11709 * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
AnnaBridge 171:3a7713b1edbc 11710 * | | |0 = BOD operate in normal mode (default).
AnnaBridge 171:3a7713b1edbc 11711 * | | |1 = BOD Low Power mode Enabled.
AnnaBridge 171:3a7713b1edbc 11712 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
AnnaBridge 171:3a7713b1edbc 11713 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11714 * |[6] |BODOUT |Brown-Out Detector Output Status
AnnaBridge 171:3a7713b1edbc 11715 * | | |0 = Brown-out Detector output status is 0.
AnnaBridge 171:3a7713b1edbc 11716 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
AnnaBridge 171:3a7713b1edbc 11717 * | | |1 = Brown-out Detector output status is 1.
AnnaBridge 171:3a7713b1edbc 11718 * | | |It means the detected voltage is lower than BODVL setting.
AnnaBridge 171:3a7713b1edbc 11719 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
AnnaBridge 171:3a7713b1edbc 11720 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 11721 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
AnnaBridge 171:3a7713b1edbc 11722 * | | |LVR function is enabled by default.
AnnaBridge 171:3a7713b1edbc 11723 * | | |0 = Low Voltage Reset function Disabled.
AnnaBridge 171:3a7713b1edbc 11724 * | | |1 = Low Voltage Reset function Enabled
AnnaBridge 171:3a7713b1edbc 11725 * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
AnnaBridge 171:3a7713b1edbc 11726 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11727 * |[10:8] |BODDGSEL |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
AnnaBridge 171:3a7713b1edbc 11728 * | | |000 = BOD output is sampled by RC10K clock.
AnnaBridge 171:3a7713b1edbc 11729 * | | |001 = 4 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11730 * | | |010 = 8 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11731 * | | |011 = 16 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11732 * | | |100 = 32 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11733 * | | |101 = 64 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11734 * | | |110 = 128 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11735 * | | |111 = 256 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11736 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11737 * |[14:12] |LVRDGSEL |LVR Output De-Glitch Time Select (Write Protect)
AnnaBridge 171:3a7713b1edbc 11738 * | | |000 = Without de-glitch function.
AnnaBridge 171:3a7713b1edbc 11739 * | | |001 = 4 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11740 * | | |010 = 8 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11741 * | | |011 = 16 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11742 * | | |100 = 32 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11743 * | | |101 = 64 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11744 * | | |110 = 128 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11745 * | | |111 = 256 system clock (HCLK).
AnnaBridge 171:3a7713b1edbc 11746 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11747 * @var SYS_T::IVSCTL
AnnaBridge 171:3a7713b1edbc 11748 * Offset: 0x1C Internal Voltage Source Control Register
AnnaBridge 171:3a7713b1edbc 11749 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11750 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11751 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11752 * |[0] |VTEMPEN |Temperature Sensor Enable Bit
AnnaBridge 171:3a7713b1edbc 11753 * | | |This bit is used to enable/disable temperature sensor function.
AnnaBridge 171:3a7713b1edbc 11754 * | | |0 = Temperature sensor function Disabled (default).
AnnaBridge 171:3a7713b1edbc 11755 * | | |1 = Temperature sensor function Enabled.
AnnaBridge 171:3a7713b1edbc 11756 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
AnnaBridge 171:3a7713b1edbc 11757 * | | |Please refer to ADC function chapter for details.
AnnaBridge 171:3a7713b1edbc 11758 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
AnnaBridge 171:3a7713b1edbc 11759 * | | |This bit is used to enable/disable VBAT unity gain buffer function.
AnnaBridge 171:3a7713b1edbc 11760 * | | |0 = VBAT unity gain buffer function Disabled (default).
AnnaBridge 171:3a7713b1edbc 11761 * | | |1 = VBAT unity gain buffer function Enabled.
AnnaBridge 171:3a7713b1edbc 11762 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
AnnaBridge 171:3a7713b1edbc 11763 * @var SYS_T::PORCTL
AnnaBridge 171:3a7713b1edbc 11764 * Offset: 0x24 Power-On-Reset Controller Register
AnnaBridge 171:3a7713b1edbc 11765 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11766 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11767 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11768 * |[15:0] |POROFF |Power-On-Reset Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 11769 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
AnnaBridge 171:3a7713b1edbc 11770 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
AnnaBridge 171:3a7713b1edbc 11771 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
AnnaBridge 171:3a7713b1edbc 11772 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
AnnaBridge 171:3a7713b1edbc 11773 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11774 * @var SYS_T::VREFCTL
AnnaBridge 171:3a7713b1edbc 11775 * Offset: 0x28 VREF Control Register
AnnaBridge 171:3a7713b1edbc 11776 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11777 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11778 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11779 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
AnnaBridge 171:3a7713b1edbc 11780 * | | |00011 = VREF is internal 2.65V.
AnnaBridge 171:3a7713b1edbc 11781 * | | |00111 = VREF is internal 2.048V.
AnnaBridge 171:3a7713b1edbc 11782 * | | |01011 = VREF is internal 3.072V.
AnnaBridge 171:3a7713b1edbc 11783 * | | |01111 = VREF is internal 4.096V.
AnnaBridge 171:3a7713b1edbc 11784 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 11785 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11786 * @var SYS_T::USBPHY
AnnaBridge 171:3a7713b1edbc 11787 * Offset: 0x2C USB PHY Control Register
AnnaBridge 171:3a7713b1edbc 11788 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11789 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11790 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11791 * |[1:0] |USBROLE |USB Role Option (Write Protect)
AnnaBridge 171:3a7713b1edbc 11792 * | | |These two bits are used to select the role of USB.
AnnaBridge 171:3a7713b1edbc 11793 * | | |00 = Standard USB Device mode.
AnnaBridge 171:3a7713b1edbc 11794 * | | |01 = Standard USB Host mode.
AnnaBridge 171:3a7713b1edbc 11795 * | | |10 = ID dependent mode.
AnnaBridge 171:3a7713b1edbc 11796 * | | |11 = On-The-Go device mode.
AnnaBridge 171:3a7713b1edbc 11797 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11798 * |[8] |LDO33EN |USB LDO33 Enable Bit (Write Protect)
AnnaBridge 171:3a7713b1edbc 11799 * | | |0 = USB LDO33 Disabled.
AnnaBridge 171:3a7713b1edbc 11800 * | | |1 = USB LDO33 Enabled.
AnnaBridge 171:3a7713b1edbc 11801 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 11802 * @var SYS_T::GPA_MFPL
AnnaBridge 171:3a7713b1edbc 11803 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11804 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11805 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11806 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11807 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11808 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11809 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11810 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11811 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11812 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11813 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11814 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11815 * @var SYS_T::GPA_MFPH
AnnaBridge 171:3a7713b1edbc 11816 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11817 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11818 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11819 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11820 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11821 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11822 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11823 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11824 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11825 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11826 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11827 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11828 * @var SYS_T::GPB_MFPL
AnnaBridge 171:3a7713b1edbc 11829 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11830 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11831 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11832 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11833 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11834 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11835 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11836 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11837 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11838 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11839 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11840 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11841 * @var SYS_T::GPB_MFPH
AnnaBridge 171:3a7713b1edbc 11842 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11843 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11844 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11845 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11846 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11847 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11848 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11849 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11850 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11851 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11852 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11853 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11854 * @var SYS_T::GPC_MFPL
AnnaBridge 171:3a7713b1edbc 11855 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11856 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11857 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11858 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11859 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11860 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11861 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11862 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11863 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11864 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11865 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11866 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11867 * @var SYS_T::GPC_MFPH
AnnaBridge 171:3a7713b1edbc 11868 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11869 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11870 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11871 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11872 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11873 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11874 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11875 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11876 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11877 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11878 * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11879 * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11880 * @var SYS_T::GPD_MFPL
AnnaBridge 171:3a7713b1edbc 11881 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11882 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11883 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11884 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11885 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11886 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11887 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11888 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11889 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11890 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11891 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11892 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11893 * @var SYS_T::GPD_MFPH
AnnaBridge 171:3a7713b1edbc 11894 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11895 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11896 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11897 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11898 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11899 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11900 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11901 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11902 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11903 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11904 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11905 * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11906 * @var SYS_T::GPE_MFPL
AnnaBridge 171:3a7713b1edbc 11907 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11908 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11909 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11910 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11911 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11912 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11913 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11914 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11915 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11916 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11917 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11918 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11919 * @var SYS_T::GPE_MFPH
AnnaBridge 171:3a7713b1edbc 11920 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11921 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11922 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11923 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11924 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11925 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11926 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11927 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11928 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11929 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11930 * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11931 * @var SYS_T::GPF_MFPL
AnnaBridge 171:3a7713b1edbc 11932 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
AnnaBridge 171:3a7713b1edbc 11933 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11934 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11935 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11936 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11937 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11938 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11939 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11940 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11941 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11942 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11943 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
AnnaBridge 171:3a7713b1edbc 11944 * @var SYS_T::SRAM_INTCTL
AnnaBridge 171:3a7713b1edbc 11945 * Offset: 0xC0 System SRAM Interrupt Enable Control Register
AnnaBridge 171:3a7713b1edbc 11946 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11947 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11948 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11949 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 11950 * | | |0 = SRAM parity check error interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 11951 * | | |1 = SRAM parity check error interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 11952 * @var SYS_T::SRAM_STATUS
AnnaBridge 171:3a7713b1edbc 11953 * Offset: 0xC4 System SRAM Parity Error Status Register
AnnaBridge 171:3a7713b1edbc 11954 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11955 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11956 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11957 * |[0] |PERRIF |SRAM Parity Check Error Flag
AnnaBridge 171:3a7713b1edbc 11958 * | | |0 = No System SRAM parity error.
AnnaBridge 171:3a7713b1edbc 11959 * | | |1 = System SRAM parity error occur.
AnnaBridge 171:3a7713b1edbc 11960 * @var SYS_T::SRAM_ERRADDR
AnnaBridge 171:3a7713b1edbc 11961 * Offset: 0xC8 System SRAM Parity Check Error Address Register
AnnaBridge 171:3a7713b1edbc 11962 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11963 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11964 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11965 * |[31:0] |ERRADDR |System SRAM Parity Error Address
AnnaBridge 171:3a7713b1edbc 11966 * | | |This register shows system SRAM parity error byte address.
AnnaBridge 171:3a7713b1edbc 11967 * @var SYS_T::SRAM_BISTCTL
AnnaBridge 171:3a7713b1edbc 11968 * Offset: 0xD0 System SRAM BIST Test Control Register
AnnaBridge 171:3a7713b1edbc 11969 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11970 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11971 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11972 * |[0] |SRBIST0 |1st
AnnaBridge 171:3a7713b1edbc 11973 * | | |SRAM BIST Enable Bit
AnnaBridge 171:3a7713b1edbc 11974 * | | |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
AnnaBridge 171:3a7713b1edbc 11975 * | | |0 = system SRAM BIST Disabled.
AnnaBridge 171:3a7713b1edbc 11976 * | | |1 = system SRAM BIST Enabled.
AnnaBridge 171:3a7713b1edbc 11977 * |[1] |SRBIST1 |2nd
AnnaBridge 171:3a7713b1edbc 11978 * | | |SRAM BIST Enable Bit
AnnaBridge 171:3a7713b1edbc 11979 * | | |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
AnnaBridge 171:3a7713b1edbc 11980 * | | |0 = system SRAM BIST Disabled.
AnnaBridge 171:3a7713b1edbc 11981 * | | |1 = system SRAM BIST Enabled.
AnnaBridge 171:3a7713b1edbc 11982 * |[2] |CRBIST |CACHE BIST Enable Bit
AnnaBridge 171:3a7713b1edbc 11983 * | | |This bit enables BIST test for CACHE RAM
AnnaBridge 171:3a7713b1edbc 11984 * | | |0 = system CACHE BIST Disabled.
AnnaBridge 171:3a7713b1edbc 11985 * | | |1 = system CACHE BIST Enabled.
AnnaBridge 171:3a7713b1edbc 11986 * |[3] |CANBIST |CAN BIST Enable Bit
AnnaBridge 171:3a7713b1edbc 11987 * | | |This bit enables BIST test for CAN RAM
AnnaBridge 171:3a7713b1edbc 11988 * | | |0 = system CAN BIST Disabled.
AnnaBridge 171:3a7713b1edbc 11989 * | | |1 = system CAN BIST Enabled.
AnnaBridge 171:3a7713b1edbc 11990 * |[4] |USBBIST |USB BIST Enable Bit
AnnaBridge 171:3a7713b1edbc 11991 * | | |This bit enables BIST test for USB RAM
AnnaBridge 171:3a7713b1edbc 11992 * | | |0 = system USB BIST Disabled.
AnnaBridge 171:3a7713b1edbc 11993 * | | |1 = system USB BIST Enabled.
AnnaBridge 171:3a7713b1edbc 11994 * @var SYS_T::SRAM_BISTSTS
AnnaBridge 171:3a7713b1edbc 11995 * Offset: 0xD4 System SRAM BIST Test Status Register
AnnaBridge 171:3a7713b1edbc 11996 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11997 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 11998 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 11999 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
AnnaBridge 171:3a7713b1edbc 12000 * | | |0 = 1st system SRAM BIST test pass.
AnnaBridge 171:3a7713b1edbc 12001 * | | |1 = 1st system SRAM BIST test fail.
AnnaBridge 171:3a7713b1edbc 12002 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
AnnaBridge 171:3a7713b1edbc 12003 * | | |0 = 2nd system SRAM BIST test pass.
AnnaBridge 171:3a7713b1edbc 12004 * | | |1 = 2nd system SRAM BIST test fail.
AnnaBridge 171:3a7713b1edbc 12005 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
AnnaBridge 171:3a7713b1edbc 12006 * | | |0 = System CACHE RAM BIST test pass.
AnnaBridge 171:3a7713b1edbc 12007 * | | |1 = System CACHE RAM BIST test fail.
AnnaBridge 171:3a7713b1edbc 12008 * |[3] |CANBEF |CAN SRAM BIST Fail Flag
AnnaBridge 171:3a7713b1edbc 12009 * | | |0 = CAN SRAM BIST test pass.
AnnaBridge 171:3a7713b1edbc 12010 * | | |1 = CAN SRAM BIST test fail.
AnnaBridge 171:3a7713b1edbc 12011 * |[4] |USBBEF |USB SRAM BIST Fail Flag
AnnaBridge 171:3a7713b1edbc 12012 * | | |0 = USB SRAM BIST test pass.
AnnaBridge 171:3a7713b1edbc 12013 * | | |1 = USB SRAM BIST test fail.
AnnaBridge 171:3a7713b1edbc 12014 * |[16] |SRBEND0 |1st SRAM BIST Test Finish
AnnaBridge 171:3a7713b1edbc 12015 * | | |0 = 1st system SRAM BIST active.
AnnaBridge 171:3a7713b1edbc 12016 * | | |1 = 1st system SRAM BIST finish.
AnnaBridge 171:3a7713b1edbc 12017 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
AnnaBridge 171:3a7713b1edbc 12018 * | | |0 = 2nd system SRAM BIST is active.
AnnaBridge 171:3a7713b1edbc 12019 * | | |1 = 2nd system SRAM BIST finish.
AnnaBridge 171:3a7713b1edbc 12020 * |[18] |CRBEND |CACHE SRAM BIST Test Finish
AnnaBridge 171:3a7713b1edbc 12021 * | | |0 = System CACHE RAM BIST is active.
AnnaBridge 171:3a7713b1edbc 12022 * | | |1 = System CACHE RAM BIST test finish.
AnnaBridge 171:3a7713b1edbc 12023 * |[19] |CANBEND |CAN SRAM BIST Test Finish
AnnaBridge 171:3a7713b1edbc 12024 * | | |0 = CAN SRAM BIST is active.
AnnaBridge 171:3a7713b1edbc 12025 * | | |1 = CAN SRAM BIST test finish.
AnnaBridge 171:3a7713b1edbc 12026 * |[20] |USBBEND |USB SRAM BIST Test Finish
AnnaBridge 171:3a7713b1edbc 12027 * | | |0 = USB SRAM BIST is active.
AnnaBridge 171:3a7713b1edbc 12028 * | | |1 = USB SRAM BIST test finish.
AnnaBridge 171:3a7713b1edbc 12029 * @var SYS_T::IRCTCTL
AnnaBridge 171:3a7713b1edbc 12030 * Offset: 0xF0 IRC Trim Control Register
AnnaBridge 171:3a7713b1edbc 12031 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12032 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12033 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12034 * |[1:0] |FREQSEL |Trim Frequency Selection
AnnaBridge 171:3a7713b1edbc 12035 * | | |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
AnnaBridge 171:3a7713b1edbc 12036 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
AnnaBridge 171:3a7713b1edbc 12037 * | | |00 = Disable HIRC auto trim function.
AnnaBridge 171:3a7713b1edbc 12038 * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
AnnaBridge 171:3a7713b1edbc 12039 * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
AnnaBridge 171:3a7713b1edbc 12040 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 12041 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
AnnaBridge 171:3a7713b1edbc 12042 * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12043 * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12044 * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12045 * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12046 * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12047 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
AnnaBridge 171:3a7713b1edbc 12048 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
AnnaBridge 171:3a7713b1edbc 12049 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
AnnaBridge 171:3a7713b1edbc 12050 * | | |Once the HIRC locked, the internal trim value update counter will be reset.
AnnaBridge 171:3a7713b1edbc 12051 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
AnnaBridge 171:3a7713b1edbc 12052 * | | |00 = Trim retry count limitation is 64 loops.
AnnaBridge 171:3a7713b1edbc 12053 * | | |01 = Trim retry count limitation is 128 loops.
AnnaBridge 171:3a7713b1edbc 12054 * | | |10 = Trim retry count limitation is 256 loops.
AnnaBridge 171:3a7713b1edbc 12055 * | | |11 = Trim retry count limitation is 512 loops.
AnnaBridge 171:3a7713b1edbc 12056 * |[8] |CESTOPEN |Clock Error Stop Enable Bit
AnnaBridge 171:3a7713b1edbc 12057 * | | |0 = The trim operation is keep going if clock is inaccuracy.
AnnaBridge 171:3a7713b1edbc 12058 * | | |1 = The trim operation is stopped if clock is inaccuracy.
AnnaBridge 171:3a7713b1edbc 12059 * @var SYS_T::IRCTIEN
AnnaBridge 171:3a7713b1edbc 12060 * Offset: 0xF4 IRC Trim Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 12061 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12062 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12063 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12064 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 12065 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
AnnaBridge 171:3a7713b1edbc 12066 * | | |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
AnnaBridge 171:3a7713b1edbc 12067 * | | |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 12068 * | | |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 12069 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 12070 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
AnnaBridge 171:3a7713b1edbc 12071 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
AnnaBridge 171:3a7713b1edbc 12072 * | | |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 12073 * | | |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
AnnaBridge 171:3a7713b1edbc 12074 * @var SYS_T::IRCTISTS
AnnaBridge 171:3a7713b1edbc 12075 * Offset: 0xF8 IRC Trim Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 12076 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12077 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12078 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12079 * |[0] |FREQLOCK |HIRC Frequency Lock Status
AnnaBridge 171:3a7713b1edbc 12080 * | | |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
AnnaBridge 171:3a7713b1edbc 12081 * | | |This is a status bit and doesn't trigger any interrupt.
AnnaBridge 171:3a7713b1edbc 12082 * |[1] |TFAILIF |Trim Failure Interrupt Status
AnnaBridge 171:3a7713b1edbc 12083 * | | |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
AnnaBridge 171:3a7713b1edbc 12084 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
AnnaBridge 171:3a7713b1edbc 12085 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
AnnaBridge 171:3a7713b1edbc 12086 * | | |Write 1 to clear this to 0.
AnnaBridge 171:3a7713b1edbc 12087 * | | |0 = Trim value update limitation count does not reach.
AnnaBridge 171:3a7713b1edbc 12088 * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
AnnaBridge 171:3a7713b1edbc 12089 * |[2] |CLKERRIF |Clock Error Interrupt Status
AnnaBridge 171:3a7713b1edbc 12090 * | | |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
AnnaBridge 171:3a7713b1edbc 12091 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
AnnaBridge 171:3a7713b1edbc 12092 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
AnnaBridge 171:3a7713b1edbc 12093 * | | |Write 1 to clear this to 0.
AnnaBridge 171:3a7713b1edbc 12094 * | | |0 = Clock frequency is accuracy.
AnnaBridge 171:3a7713b1edbc 12095 * | | |1 = Clock frequency is inaccuracy.
AnnaBridge 171:3a7713b1edbc 12096 * @var SYS_T::REGLCTL
AnnaBridge 171:3a7713b1edbc 12097 * Offset: 0x100 Register Lock Control Register
AnnaBridge 171:3a7713b1edbc 12098 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12099 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12100 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12101 * |[7:0] |REGLCTL |Register Lock Control Code
AnnaBridge 171:3a7713b1edbc 12102 * | | |Write operation:
AnnaBridge 171:3a7713b1edbc 12103 * | | |Some registers have write-protection function.
AnnaBridge 171:3a7713b1edbc 12104 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
AnnaBridge 171:3a7713b1edbc 12105 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
AnnaBridge 171:3a7713b1edbc 12106 * | | |Read operation:
AnnaBridge 171:3a7713b1edbc 12107 * | | |0 = Write-protection Enabled for writing protected registers.
AnnaBridge 171:3a7713b1edbc 12108 * | | |Any write to the protected register is ignored.
AnnaBridge 171:3a7713b1edbc 12109 * | | |1 = Write-protection Disabled for writing protected registers.
AnnaBridge 171:3a7713b1edbc 12110 * | | |The Protected registers are:
AnnaBridge 171:3a7713b1edbc 12111 * | | |SYS_IPRST0: address 0x4000_0008
AnnaBridge 171:3a7713b1edbc 12112 * | | |SYS_BODCTL: address 0x4000_0018
AnnaBridge 171:3a7713b1edbc 12113 * | | |SYS_PORCTL: address 0x4000_0024
AnnaBridge 171:3a7713b1edbc 12114 * | | |SYS_VREFCTL: address 0x4000_0028
AnnaBridge 171:3a7713b1edbc 12115 * | | |SYS_USBPHY: address 0x4000_002C
AnnaBridge 171:3a7713b1edbc 12116 * | | |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
AnnaBridge 171:3a7713b1edbc 12117 * | | |SYS_SRAM_BISTCTL: address 0x4000_00D0
AnnaBridge 171:3a7713b1edbc 12118 * | | |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
AnnaBridge 171:3a7713b1edbc 12119 * | | |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
AnnaBridge 171:3a7713b1edbc 12120 * | | |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
AnnaBridge 171:3a7713b1edbc 12121 * | | |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
AnnaBridge 171:3a7713b1edbc 12122 * | | |CLK_CLKDSTS: address 0x4000_0274
AnnaBridge 171:3a7713b1edbc 12123 * | | |NMIEN: address 0x4000_0300
AnnaBridge 171:3a7713b1edbc 12124 * | | |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
AnnaBridge 171:3a7713b1edbc 12125 * | | |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
AnnaBridge 171:3a7713b1edbc 12126 * | | |FMC_ISPSTS: address 0x4000_C040
AnnaBridge 171:3a7713b1edbc 12127 * | | |WDT_CTL: address 0x4004_0000
AnnaBridge 171:3a7713b1edbc 12128 * | | |FMC_FTCTL: address 0x4000_5018
AnnaBridge 171:3a7713b1edbc 12129 * | | |FMC_ICPCMD: address 0x4000_501C
AnnaBridge 171:3a7713b1edbc 12130 * | | |CLK_PLLCTL: address 0x40000240
AnnaBridge 171:3a7713b1edbc 12131 * | | |PWM_CTL0: address 0x4005_8000
AnnaBridge 171:3a7713b1edbc 12132 * | | |PWM_CTL0: address 0x4005_9000
AnnaBridge 171:3a7713b1edbc 12133 * | | |PWM_DTCTL0_1: address 0x4005_8070
AnnaBridge 171:3a7713b1edbc 12134 * | | |PWM_DTCTL0_1: address 0x4005_9070
AnnaBridge 171:3a7713b1edbc 12135 * | | |PWM_DTCTL2_3: address 0x4005_8074
AnnaBridge 171:3a7713b1edbc 12136 * | | |PWM_DTCTL2_3: address 0x4005_9074
AnnaBridge 171:3a7713b1edbc 12137 * | | |PWM_DTCTL4_5: address 0x4005_8078
AnnaBridge 171:3a7713b1edbc 12138 * | | |PWM_DTCTL4_5: address 0x4005_9078
AnnaBridge 171:3a7713b1edbc 12139 * | | |PWM_BRKCTL0_1: address 0x4005_80C8
AnnaBridge 171:3a7713b1edbc 12140 * | | |PWM_BRKCTL0_1: address 0x4005_90C8
AnnaBridge 171:3a7713b1edbc 12141 * | | |PWM_BRKCTL2_3: address0x4005_80CC
AnnaBridge 171:3a7713b1edbc 12142 * | | |PWM_BRKCTL2_3: address0x4005_90CC
AnnaBridge 171:3a7713b1edbc 12143 * | | |PWM_BRKCTL4_5: address0x4005_80D0
AnnaBridge 171:3a7713b1edbc 12144 * | | |PWM_BRKCTL4_5: address0x4005_90D0
AnnaBridge 171:3a7713b1edbc 12145 * | | |PWM_INTEN1: address0x4005_80E4
AnnaBridge 171:3a7713b1edbc 12146 * | | |PWM_INTEN1: address0x4005_90E4
AnnaBridge 171:3a7713b1edbc 12147 * | | |PWM_INTSTS1: address0x4005_80EC
AnnaBridge 171:3a7713b1edbc 12148 * | | |PWM_INTSTS1: address0x4005_90EC
AnnaBridge 171:3a7713b1edbc 12149 */
AnnaBridge 171:3a7713b1edbc 12150
AnnaBridge 171:3a7713b1edbc 12151 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
AnnaBridge 171:3a7713b1edbc 12152 __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
AnnaBridge 171:3a7713b1edbc 12153 __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
AnnaBridge 171:3a7713b1edbc 12154 __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
AnnaBridge 171:3a7713b1edbc 12155 __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
AnnaBridge 171:3a7713b1edbc 12156 __I uint32_t RESERVE0[1];
AnnaBridge 171:3a7713b1edbc 12157 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
AnnaBridge 171:3a7713b1edbc 12158 __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
AnnaBridge 171:3a7713b1edbc 12159 __I uint32_t RESERVE1[1];
AnnaBridge 171:3a7713b1edbc 12160 __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
AnnaBridge 171:3a7713b1edbc 12161 __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
AnnaBridge 171:3a7713b1edbc 12162 __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
AnnaBridge 171:3a7713b1edbc 12163 __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12164 __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12165 __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12166 __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12167 __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12168 __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12169 __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12170 __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12171 __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12172 __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12173 __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
AnnaBridge 171:3a7713b1edbc 12174 __I uint32_t RESERVE2[25];
AnnaBridge 171:3a7713b1edbc 12175 __IO uint32_t SRAM_INTCTL; /* Offset: 0xC0 System SRAM Interrupt Enable Control Register */
AnnaBridge 171:3a7713b1edbc 12176 __I uint32_t SRAM_STATUS; /* Offset: 0xC4 System SRAM Parity Error Status Register */
AnnaBridge 171:3a7713b1edbc 12177 __I uint32_t SRAM_ERRADDR; /* Offset: 0xC8 System SRAM Parity Check Error Address Register */
AnnaBridge 171:3a7713b1edbc 12178 __I uint32_t RESERVE3[1];
AnnaBridge 171:3a7713b1edbc 12179 __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
AnnaBridge 171:3a7713b1edbc 12180 __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
AnnaBridge 171:3a7713b1edbc 12181 __I uint32_t RESERVE4[6];
AnnaBridge 171:3a7713b1edbc 12182 __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
AnnaBridge 171:3a7713b1edbc 12183 __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 12184 __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 12185 __I uint32_t RESERVE5[1];
AnnaBridge 171:3a7713b1edbc 12186 __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
AnnaBridge 171:3a7713b1edbc 12187
AnnaBridge 171:3a7713b1edbc 12188 } SYS_T;
AnnaBridge 171:3a7713b1edbc 12189
AnnaBridge 171:3a7713b1edbc 12190
AnnaBridge 171:3a7713b1edbc 12191
AnnaBridge 171:3a7713b1edbc 12192 /**
AnnaBridge 171:3a7713b1edbc 12193 @addtogroup SYS_CONST SYS Bit Field Definition
AnnaBridge 171:3a7713b1edbc 12194 Constant Definitions for SYS Controller
AnnaBridge 171:3a7713b1edbc 12195 @{ */
AnnaBridge 171:3a7713b1edbc 12196
AnnaBridge 171:3a7713b1edbc 12197 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
AnnaBridge 171:3a7713b1edbc 12198 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
AnnaBridge 171:3a7713b1edbc 12199
AnnaBridge 171:3a7713b1edbc 12200 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
AnnaBridge 171:3a7713b1edbc 12201 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
AnnaBridge 171:3a7713b1edbc 12202
AnnaBridge 171:3a7713b1edbc 12203 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
AnnaBridge 171:3a7713b1edbc 12204 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
AnnaBridge 171:3a7713b1edbc 12205
AnnaBridge 171:3a7713b1edbc 12206 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
AnnaBridge 171:3a7713b1edbc 12207 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
AnnaBridge 171:3a7713b1edbc 12208
AnnaBridge 171:3a7713b1edbc 12209 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
AnnaBridge 171:3a7713b1edbc 12210 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
AnnaBridge 171:3a7713b1edbc 12211
AnnaBridge 171:3a7713b1edbc 12212 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
AnnaBridge 171:3a7713b1edbc 12213 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
AnnaBridge 171:3a7713b1edbc 12214
AnnaBridge 171:3a7713b1edbc 12215 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
AnnaBridge 171:3a7713b1edbc 12216 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
AnnaBridge 171:3a7713b1edbc 12217
AnnaBridge 171:3a7713b1edbc 12218 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
AnnaBridge 171:3a7713b1edbc 12219 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
AnnaBridge 171:3a7713b1edbc 12220
AnnaBridge 171:3a7713b1edbc 12221 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
AnnaBridge 171:3a7713b1edbc 12222 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
AnnaBridge 171:3a7713b1edbc 12223
AnnaBridge 171:3a7713b1edbc 12224 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
AnnaBridge 171:3a7713b1edbc 12225 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
AnnaBridge 171:3a7713b1edbc 12226
AnnaBridge 171:3a7713b1edbc 12227 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
AnnaBridge 171:3a7713b1edbc 12228 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
AnnaBridge 171:3a7713b1edbc 12229
AnnaBridge 171:3a7713b1edbc 12230 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
AnnaBridge 171:3a7713b1edbc 12231 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
AnnaBridge 171:3a7713b1edbc 12232
AnnaBridge 171:3a7713b1edbc 12233 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
AnnaBridge 171:3a7713b1edbc 12234 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
AnnaBridge 171:3a7713b1edbc 12235
AnnaBridge 171:3a7713b1edbc 12236 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */
AnnaBridge 171:3a7713b1edbc 12237 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
AnnaBridge 171:3a7713b1edbc 12238
AnnaBridge 171:3a7713b1edbc 12239 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
AnnaBridge 171:3a7713b1edbc 12240 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
AnnaBridge 171:3a7713b1edbc 12241
AnnaBridge 171:3a7713b1edbc 12242 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
AnnaBridge 171:3a7713b1edbc 12243 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
AnnaBridge 171:3a7713b1edbc 12244
AnnaBridge 171:3a7713b1edbc 12245 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
AnnaBridge 171:3a7713b1edbc 12246 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
AnnaBridge 171:3a7713b1edbc 12247
AnnaBridge 171:3a7713b1edbc 12248 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
AnnaBridge 171:3a7713b1edbc 12249 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
AnnaBridge 171:3a7713b1edbc 12250
AnnaBridge 171:3a7713b1edbc 12251 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
AnnaBridge 171:3a7713b1edbc 12252 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
AnnaBridge 171:3a7713b1edbc 12253
AnnaBridge 171:3a7713b1edbc 12254 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
AnnaBridge 171:3a7713b1edbc 12255 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
AnnaBridge 171:3a7713b1edbc 12256
AnnaBridge 171:3a7713b1edbc 12257 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
AnnaBridge 171:3a7713b1edbc 12258 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
AnnaBridge 171:3a7713b1edbc 12259
AnnaBridge 171:3a7713b1edbc 12260 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
AnnaBridge 171:3a7713b1edbc 12261 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
AnnaBridge 171:3a7713b1edbc 12262
AnnaBridge 171:3a7713b1edbc 12263 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
AnnaBridge 171:3a7713b1edbc 12264 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
AnnaBridge 171:3a7713b1edbc 12265
AnnaBridge 171:3a7713b1edbc 12266 #define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
AnnaBridge 171:3a7713b1edbc 12267 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
AnnaBridge 171:3a7713b1edbc 12268
AnnaBridge 171:3a7713b1edbc 12269 #define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
AnnaBridge 171:3a7713b1edbc 12270 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
AnnaBridge 171:3a7713b1edbc 12271
AnnaBridge 171:3a7713b1edbc 12272 #define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
AnnaBridge 171:3a7713b1edbc 12273 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
AnnaBridge 171:3a7713b1edbc 12274
AnnaBridge 171:3a7713b1edbc 12275 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
AnnaBridge 171:3a7713b1edbc 12276 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
AnnaBridge 171:3a7713b1edbc 12277
AnnaBridge 171:3a7713b1edbc 12278 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
AnnaBridge 171:3a7713b1edbc 12279 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
AnnaBridge 171:3a7713b1edbc 12280
AnnaBridge 171:3a7713b1edbc 12281 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
AnnaBridge 171:3a7713b1edbc 12282 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
AnnaBridge 171:3a7713b1edbc 12283
AnnaBridge 171:3a7713b1edbc 12284 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
AnnaBridge 171:3a7713b1edbc 12285 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
AnnaBridge 171:3a7713b1edbc 12286
AnnaBridge 171:3a7713b1edbc 12287 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
AnnaBridge 171:3a7713b1edbc 12288 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
AnnaBridge 171:3a7713b1edbc 12289
AnnaBridge 171:3a7713b1edbc 12290 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
AnnaBridge 171:3a7713b1edbc 12291 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
AnnaBridge 171:3a7713b1edbc 12292
AnnaBridge 171:3a7713b1edbc 12293 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
AnnaBridge 171:3a7713b1edbc 12294 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
AnnaBridge 171:3a7713b1edbc 12295
AnnaBridge 171:3a7713b1edbc 12296 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
AnnaBridge 171:3a7713b1edbc 12297 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
AnnaBridge 171:3a7713b1edbc 12298
AnnaBridge 171:3a7713b1edbc 12299 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
AnnaBridge 171:3a7713b1edbc 12300 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
AnnaBridge 171:3a7713b1edbc 12301
AnnaBridge 171:3a7713b1edbc 12302 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
AnnaBridge 171:3a7713b1edbc 12303 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
AnnaBridge 171:3a7713b1edbc 12304
AnnaBridge 171:3a7713b1edbc 12305 #define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */
AnnaBridge 171:3a7713b1edbc 12306 #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */
AnnaBridge 171:3a7713b1edbc 12307
AnnaBridge 171:3a7713b1edbc 12308 #define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */
AnnaBridge 171:3a7713b1edbc 12309 #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */
AnnaBridge 171:3a7713b1edbc 12310
AnnaBridge 171:3a7713b1edbc 12311 #define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */
AnnaBridge 171:3a7713b1edbc 12312 #define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */
AnnaBridge 171:3a7713b1edbc 12313
AnnaBridge 171:3a7713b1edbc 12314 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
AnnaBridge 171:3a7713b1edbc 12315 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
AnnaBridge 171:3a7713b1edbc 12316
AnnaBridge 171:3a7713b1edbc 12317 #define SYS_BODCTL_BODVL_Pos (1) /*!< SYS_T::BODCTL: BODVL Position */
AnnaBridge 171:3a7713b1edbc 12318 #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
AnnaBridge 171:3a7713b1edbc 12319
AnnaBridge 171:3a7713b1edbc 12320 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
AnnaBridge 171:3a7713b1edbc 12321 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
AnnaBridge 171:3a7713b1edbc 12322
AnnaBridge 171:3a7713b1edbc 12323 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
AnnaBridge 171:3a7713b1edbc 12324 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
AnnaBridge 171:3a7713b1edbc 12325
AnnaBridge 171:3a7713b1edbc 12326 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
AnnaBridge 171:3a7713b1edbc 12327 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
AnnaBridge 171:3a7713b1edbc 12328
AnnaBridge 171:3a7713b1edbc 12329 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
AnnaBridge 171:3a7713b1edbc 12330 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
AnnaBridge 171:3a7713b1edbc 12331
AnnaBridge 171:3a7713b1edbc 12332 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
AnnaBridge 171:3a7713b1edbc 12333 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
AnnaBridge 171:3a7713b1edbc 12334
AnnaBridge 171:3a7713b1edbc 12335 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
AnnaBridge 171:3a7713b1edbc 12336 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
AnnaBridge 171:3a7713b1edbc 12337
AnnaBridge 171:3a7713b1edbc 12338 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
AnnaBridge 171:3a7713b1edbc 12339 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
AnnaBridge 171:3a7713b1edbc 12340
AnnaBridge 171:3a7713b1edbc 12341 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
AnnaBridge 171:3a7713b1edbc 12342 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
AnnaBridge 171:3a7713b1edbc 12343
AnnaBridge 171:3a7713b1edbc 12344 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
AnnaBridge 171:3a7713b1edbc 12345 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
AnnaBridge 171:3a7713b1edbc 12346
AnnaBridge 171:3a7713b1edbc 12347 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
AnnaBridge 171:3a7713b1edbc 12348 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
AnnaBridge 171:3a7713b1edbc 12349
AnnaBridge 171:3a7713b1edbc 12350 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
AnnaBridge 171:3a7713b1edbc 12351 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
AnnaBridge 171:3a7713b1edbc 12352
AnnaBridge 171:3a7713b1edbc 12353 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
AnnaBridge 171:3a7713b1edbc 12354 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
AnnaBridge 171:3a7713b1edbc 12355
AnnaBridge 171:3a7713b1edbc 12356 #define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS_T::USBPHY: LDO33EN Position */
AnnaBridge 171:3a7713b1edbc 12357 #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS_T::USBPHY: LDO33EN Mask */
AnnaBridge 171:3a7713b1edbc 12358
AnnaBridge 171:3a7713b1edbc 12359 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
AnnaBridge 171:3a7713b1edbc 12360 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12361
AnnaBridge 171:3a7713b1edbc 12362 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
AnnaBridge 171:3a7713b1edbc 12363 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12364
AnnaBridge 171:3a7713b1edbc 12365 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
AnnaBridge 171:3a7713b1edbc 12366 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12367
AnnaBridge 171:3a7713b1edbc 12368 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
AnnaBridge 171:3a7713b1edbc 12369 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12370
AnnaBridge 171:3a7713b1edbc 12371 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
AnnaBridge 171:3a7713b1edbc 12372 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12373
AnnaBridge 171:3a7713b1edbc 12374 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
AnnaBridge 171:3a7713b1edbc 12375 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12376
AnnaBridge 171:3a7713b1edbc 12377 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
AnnaBridge 171:3a7713b1edbc 12378 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12379
AnnaBridge 171:3a7713b1edbc 12380 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
AnnaBridge 171:3a7713b1edbc 12381 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12382
AnnaBridge 171:3a7713b1edbc 12383 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
AnnaBridge 171:3a7713b1edbc 12384 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
AnnaBridge 171:3a7713b1edbc 12385
AnnaBridge 171:3a7713b1edbc 12386 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
AnnaBridge 171:3a7713b1edbc 12387 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
AnnaBridge 171:3a7713b1edbc 12388
AnnaBridge 171:3a7713b1edbc 12389 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
AnnaBridge 171:3a7713b1edbc 12390 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
AnnaBridge 171:3a7713b1edbc 12391
AnnaBridge 171:3a7713b1edbc 12392 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
AnnaBridge 171:3a7713b1edbc 12393 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
AnnaBridge 171:3a7713b1edbc 12394
AnnaBridge 171:3a7713b1edbc 12395 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
AnnaBridge 171:3a7713b1edbc 12396 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
AnnaBridge 171:3a7713b1edbc 12397
AnnaBridge 171:3a7713b1edbc 12398 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
AnnaBridge 171:3a7713b1edbc 12399 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
AnnaBridge 171:3a7713b1edbc 12400
AnnaBridge 171:3a7713b1edbc 12401 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
AnnaBridge 171:3a7713b1edbc 12402 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
AnnaBridge 171:3a7713b1edbc 12403
AnnaBridge 171:3a7713b1edbc 12404 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
AnnaBridge 171:3a7713b1edbc 12405 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
AnnaBridge 171:3a7713b1edbc 12406
AnnaBridge 171:3a7713b1edbc 12407 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
AnnaBridge 171:3a7713b1edbc 12408 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12409
AnnaBridge 171:3a7713b1edbc 12410 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
AnnaBridge 171:3a7713b1edbc 12411 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12412
AnnaBridge 171:3a7713b1edbc 12413 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
AnnaBridge 171:3a7713b1edbc 12414 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12415
AnnaBridge 171:3a7713b1edbc 12416 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
AnnaBridge 171:3a7713b1edbc 12417 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12418
AnnaBridge 171:3a7713b1edbc 12419 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
AnnaBridge 171:3a7713b1edbc 12420 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12421
AnnaBridge 171:3a7713b1edbc 12422 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
AnnaBridge 171:3a7713b1edbc 12423 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12424
AnnaBridge 171:3a7713b1edbc 12425 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
AnnaBridge 171:3a7713b1edbc 12426 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12427
AnnaBridge 171:3a7713b1edbc 12428 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
AnnaBridge 171:3a7713b1edbc 12429 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12430
AnnaBridge 171:3a7713b1edbc 12431 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
AnnaBridge 171:3a7713b1edbc 12432 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
AnnaBridge 171:3a7713b1edbc 12433
AnnaBridge 171:3a7713b1edbc 12434 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
AnnaBridge 171:3a7713b1edbc 12435 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
AnnaBridge 171:3a7713b1edbc 12436
AnnaBridge 171:3a7713b1edbc 12437 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
AnnaBridge 171:3a7713b1edbc 12438 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
AnnaBridge 171:3a7713b1edbc 12439
AnnaBridge 171:3a7713b1edbc 12440 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
AnnaBridge 171:3a7713b1edbc 12441 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
AnnaBridge 171:3a7713b1edbc 12442
AnnaBridge 171:3a7713b1edbc 12443 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
AnnaBridge 171:3a7713b1edbc 12444 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
AnnaBridge 171:3a7713b1edbc 12445
AnnaBridge 171:3a7713b1edbc 12446 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
AnnaBridge 171:3a7713b1edbc 12447 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
AnnaBridge 171:3a7713b1edbc 12448
AnnaBridge 171:3a7713b1edbc 12449 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
AnnaBridge 171:3a7713b1edbc 12450 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
AnnaBridge 171:3a7713b1edbc 12451
AnnaBridge 171:3a7713b1edbc 12452 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
AnnaBridge 171:3a7713b1edbc 12453 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
AnnaBridge 171:3a7713b1edbc 12454
AnnaBridge 171:3a7713b1edbc 12455 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
AnnaBridge 171:3a7713b1edbc 12456 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12457
AnnaBridge 171:3a7713b1edbc 12458 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
AnnaBridge 171:3a7713b1edbc 12459 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12460
AnnaBridge 171:3a7713b1edbc 12461 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
AnnaBridge 171:3a7713b1edbc 12462 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12463
AnnaBridge 171:3a7713b1edbc 12464 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
AnnaBridge 171:3a7713b1edbc 12465 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12466
AnnaBridge 171:3a7713b1edbc 12467 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
AnnaBridge 171:3a7713b1edbc 12468 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12469
AnnaBridge 171:3a7713b1edbc 12470 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
AnnaBridge 171:3a7713b1edbc 12471 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12472
AnnaBridge 171:3a7713b1edbc 12473 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
AnnaBridge 171:3a7713b1edbc 12474 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12475
AnnaBridge 171:3a7713b1edbc 12476 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
AnnaBridge 171:3a7713b1edbc 12477 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12478
AnnaBridge 171:3a7713b1edbc 12479 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
AnnaBridge 171:3a7713b1edbc 12480 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
AnnaBridge 171:3a7713b1edbc 12481
AnnaBridge 171:3a7713b1edbc 12482 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
AnnaBridge 171:3a7713b1edbc 12483 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
AnnaBridge 171:3a7713b1edbc 12484
AnnaBridge 171:3a7713b1edbc 12485 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
AnnaBridge 171:3a7713b1edbc 12486 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
AnnaBridge 171:3a7713b1edbc 12487
AnnaBridge 171:3a7713b1edbc 12488 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
AnnaBridge 171:3a7713b1edbc 12489 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
AnnaBridge 171:3a7713b1edbc 12490
AnnaBridge 171:3a7713b1edbc 12491 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
AnnaBridge 171:3a7713b1edbc 12492 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
AnnaBridge 171:3a7713b1edbc 12493
AnnaBridge 171:3a7713b1edbc 12494 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
AnnaBridge 171:3a7713b1edbc 12495 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
AnnaBridge 171:3a7713b1edbc 12496
AnnaBridge 171:3a7713b1edbc 12497 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
AnnaBridge 171:3a7713b1edbc 12498 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
AnnaBridge 171:3a7713b1edbc 12499
AnnaBridge 171:3a7713b1edbc 12500 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
AnnaBridge 171:3a7713b1edbc 12501 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
AnnaBridge 171:3a7713b1edbc 12502
AnnaBridge 171:3a7713b1edbc 12503 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
AnnaBridge 171:3a7713b1edbc 12504 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12505
AnnaBridge 171:3a7713b1edbc 12506 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
AnnaBridge 171:3a7713b1edbc 12507 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12508
AnnaBridge 171:3a7713b1edbc 12509 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
AnnaBridge 171:3a7713b1edbc 12510 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12511
AnnaBridge 171:3a7713b1edbc 12512 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
AnnaBridge 171:3a7713b1edbc 12513 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12514
AnnaBridge 171:3a7713b1edbc 12515 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
AnnaBridge 171:3a7713b1edbc 12516 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12517
AnnaBridge 171:3a7713b1edbc 12518 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
AnnaBridge 171:3a7713b1edbc 12519 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12520
AnnaBridge 171:3a7713b1edbc 12521 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
AnnaBridge 171:3a7713b1edbc 12522 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12523
AnnaBridge 171:3a7713b1edbc 12524 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
AnnaBridge 171:3a7713b1edbc 12525 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12526
AnnaBridge 171:3a7713b1edbc 12527 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
AnnaBridge 171:3a7713b1edbc 12528 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
AnnaBridge 171:3a7713b1edbc 12529
AnnaBridge 171:3a7713b1edbc 12530 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
AnnaBridge 171:3a7713b1edbc 12531 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
AnnaBridge 171:3a7713b1edbc 12532
AnnaBridge 171:3a7713b1edbc 12533 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
AnnaBridge 171:3a7713b1edbc 12534 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
AnnaBridge 171:3a7713b1edbc 12535
AnnaBridge 171:3a7713b1edbc 12536 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
AnnaBridge 171:3a7713b1edbc 12537 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
AnnaBridge 171:3a7713b1edbc 12538
AnnaBridge 171:3a7713b1edbc 12539 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
AnnaBridge 171:3a7713b1edbc 12540 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
AnnaBridge 171:3a7713b1edbc 12541
AnnaBridge 171:3a7713b1edbc 12542 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
AnnaBridge 171:3a7713b1edbc 12543 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
AnnaBridge 171:3a7713b1edbc 12544
AnnaBridge 171:3a7713b1edbc 12545 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
AnnaBridge 171:3a7713b1edbc 12546 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
AnnaBridge 171:3a7713b1edbc 12547
AnnaBridge 171:3a7713b1edbc 12548 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
AnnaBridge 171:3a7713b1edbc 12549 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
AnnaBridge 171:3a7713b1edbc 12550
AnnaBridge 171:3a7713b1edbc 12551 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
AnnaBridge 171:3a7713b1edbc 12552 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12553
AnnaBridge 171:3a7713b1edbc 12554 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
AnnaBridge 171:3a7713b1edbc 12555 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12556
AnnaBridge 171:3a7713b1edbc 12557 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
AnnaBridge 171:3a7713b1edbc 12558 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12559
AnnaBridge 171:3a7713b1edbc 12560 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
AnnaBridge 171:3a7713b1edbc 12561 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12562
AnnaBridge 171:3a7713b1edbc 12563 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
AnnaBridge 171:3a7713b1edbc 12564 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12565
AnnaBridge 171:3a7713b1edbc 12566 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
AnnaBridge 171:3a7713b1edbc 12567 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12568
AnnaBridge 171:3a7713b1edbc 12569 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
AnnaBridge 171:3a7713b1edbc 12570 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12571
AnnaBridge 171:3a7713b1edbc 12572 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
AnnaBridge 171:3a7713b1edbc 12573 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12574
AnnaBridge 171:3a7713b1edbc 12575 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
AnnaBridge 171:3a7713b1edbc 12576 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
AnnaBridge 171:3a7713b1edbc 12577
AnnaBridge 171:3a7713b1edbc 12578 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
AnnaBridge 171:3a7713b1edbc 12579 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
AnnaBridge 171:3a7713b1edbc 12580
AnnaBridge 171:3a7713b1edbc 12581 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
AnnaBridge 171:3a7713b1edbc 12582 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
AnnaBridge 171:3a7713b1edbc 12583
AnnaBridge 171:3a7713b1edbc 12584 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
AnnaBridge 171:3a7713b1edbc 12585 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
AnnaBridge 171:3a7713b1edbc 12586
AnnaBridge 171:3a7713b1edbc 12587 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
AnnaBridge 171:3a7713b1edbc 12588 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
AnnaBridge 171:3a7713b1edbc 12589
AnnaBridge 171:3a7713b1edbc 12590 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
AnnaBridge 171:3a7713b1edbc 12591 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
AnnaBridge 171:3a7713b1edbc 12592
AnnaBridge 171:3a7713b1edbc 12593 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
AnnaBridge 171:3a7713b1edbc 12594 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
AnnaBridge 171:3a7713b1edbc 12595
AnnaBridge 171:3a7713b1edbc 12596 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
AnnaBridge 171:3a7713b1edbc 12597 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
AnnaBridge 171:3a7713b1edbc 12598
AnnaBridge 171:3a7713b1edbc 12599 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
AnnaBridge 171:3a7713b1edbc 12600 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
AnnaBridge 171:3a7713b1edbc 12601
AnnaBridge 171:3a7713b1edbc 12602 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
AnnaBridge 171:3a7713b1edbc 12603 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
AnnaBridge 171:3a7713b1edbc 12604
AnnaBridge 171:3a7713b1edbc 12605 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
AnnaBridge 171:3a7713b1edbc 12606 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
AnnaBridge 171:3a7713b1edbc 12607
AnnaBridge 171:3a7713b1edbc 12608 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
AnnaBridge 171:3a7713b1edbc 12609 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
AnnaBridge 171:3a7713b1edbc 12610
AnnaBridge 171:3a7713b1edbc 12611 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
AnnaBridge 171:3a7713b1edbc 12612 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
AnnaBridge 171:3a7713b1edbc 12613
AnnaBridge 171:3a7713b1edbc 12614 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
AnnaBridge 171:3a7713b1edbc 12615 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
AnnaBridge 171:3a7713b1edbc 12616
AnnaBridge 171:3a7713b1edbc 12617 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
AnnaBridge 171:3a7713b1edbc 12618 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
AnnaBridge 171:3a7713b1edbc 12619
AnnaBridge 171:3a7713b1edbc 12620 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
AnnaBridge 171:3a7713b1edbc 12621 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
AnnaBridge 171:3a7713b1edbc 12622
AnnaBridge 171:3a7713b1edbc 12623 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
AnnaBridge 171:3a7713b1edbc 12624 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
AnnaBridge 171:3a7713b1edbc 12625
AnnaBridge 171:3a7713b1edbc 12626 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
AnnaBridge 171:3a7713b1edbc 12627 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
AnnaBridge 171:3a7713b1edbc 12628
AnnaBridge 171:3a7713b1edbc 12629 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
AnnaBridge 171:3a7713b1edbc 12630 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
AnnaBridge 171:3a7713b1edbc 12631
AnnaBridge 171:3a7713b1edbc 12632 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
AnnaBridge 171:3a7713b1edbc 12633 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
AnnaBridge 171:3a7713b1edbc 12634
AnnaBridge 171:3a7713b1edbc 12635 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
AnnaBridge 171:3a7713b1edbc 12636 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
AnnaBridge 171:3a7713b1edbc 12637
AnnaBridge 171:3a7713b1edbc 12638 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
AnnaBridge 171:3a7713b1edbc 12639 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
AnnaBridge 171:3a7713b1edbc 12640
AnnaBridge 171:3a7713b1edbc 12641 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
AnnaBridge 171:3a7713b1edbc 12642 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
AnnaBridge 171:3a7713b1edbc 12643
AnnaBridge 171:3a7713b1edbc 12644 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position */
AnnaBridge 171:3a7713b1edbc 12645 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
AnnaBridge 171:3a7713b1edbc 12646
AnnaBridge 171:3a7713b1edbc 12647 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position */
AnnaBridge 171:3a7713b1edbc 12648 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
AnnaBridge 171:3a7713b1edbc 12649
AnnaBridge 171:3a7713b1edbc 12650 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
AnnaBridge 171:3a7713b1edbc 12651 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
AnnaBridge 171:3a7713b1edbc 12652
AnnaBridge 171:3a7713b1edbc 12653 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
AnnaBridge 171:3a7713b1edbc 12654 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
AnnaBridge 171:3a7713b1edbc 12655
AnnaBridge 171:3a7713b1edbc 12656 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
AnnaBridge 171:3a7713b1edbc 12657 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
AnnaBridge 171:3a7713b1edbc 12658
AnnaBridge 171:3a7713b1edbc 12659 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
AnnaBridge 171:3a7713b1edbc 12660 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
AnnaBridge 171:3a7713b1edbc 12661
AnnaBridge 171:3a7713b1edbc 12662 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
AnnaBridge 171:3a7713b1edbc 12663 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
AnnaBridge 171:3a7713b1edbc 12664
AnnaBridge 171:3a7713b1edbc 12665 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
AnnaBridge 171:3a7713b1edbc 12666 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
AnnaBridge 171:3a7713b1edbc 12667
AnnaBridge 171:3a7713b1edbc 12668 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
AnnaBridge 171:3a7713b1edbc 12669 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
AnnaBridge 171:3a7713b1edbc 12670
AnnaBridge 171:3a7713b1edbc 12671 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
AnnaBridge 171:3a7713b1edbc 12672 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
AnnaBridge 171:3a7713b1edbc 12673
AnnaBridge 171:3a7713b1edbc 12674 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
AnnaBridge 171:3a7713b1edbc 12675 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
AnnaBridge 171:3a7713b1edbc 12676
AnnaBridge 171:3a7713b1edbc 12677 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
AnnaBridge 171:3a7713b1edbc 12678 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
AnnaBridge 171:3a7713b1edbc 12679
AnnaBridge 171:3a7713b1edbc 12680 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
AnnaBridge 171:3a7713b1edbc 12681 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
AnnaBridge 171:3a7713b1edbc 12682
AnnaBridge 171:3a7713b1edbc 12683 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
AnnaBridge 171:3a7713b1edbc 12684 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
AnnaBridge 171:3a7713b1edbc 12685
AnnaBridge 171:3a7713b1edbc 12686 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
AnnaBridge 171:3a7713b1edbc 12687 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
AnnaBridge 171:3a7713b1edbc 12688
AnnaBridge 171:3a7713b1edbc 12689 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
AnnaBridge 171:3a7713b1edbc 12690 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
AnnaBridge 171:3a7713b1edbc 12691
AnnaBridge 171:3a7713b1edbc 12692 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
AnnaBridge 171:3a7713b1edbc 12693 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
AnnaBridge 171:3a7713b1edbc 12694
AnnaBridge 171:3a7713b1edbc 12695 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
AnnaBridge 171:3a7713b1edbc 12696 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
AnnaBridge 171:3a7713b1edbc 12697
AnnaBridge 171:3a7713b1edbc 12698 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
AnnaBridge 171:3a7713b1edbc 12699 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
AnnaBridge 171:3a7713b1edbc 12700
AnnaBridge 171:3a7713b1edbc 12701 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
AnnaBridge 171:3a7713b1edbc 12702 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
AnnaBridge 171:3a7713b1edbc 12703
AnnaBridge 171:3a7713b1edbc 12704 /**@}*/ /* SYS_CONST */
AnnaBridge 171:3a7713b1edbc 12705
AnnaBridge 171:3a7713b1edbc 12706
AnnaBridge 171:3a7713b1edbc 12707 typedef struct
AnnaBridge 171:3a7713b1edbc 12708 {
AnnaBridge 171:3a7713b1edbc 12709
AnnaBridge 171:3a7713b1edbc 12710 /**
AnnaBridge 171:3a7713b1edbc 12711 * @var SYS_INT_T::NMIEN
AnnaBridge 171:3a7713b1edbc 12712 * Offset: 0x00 NMI Source Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 12713 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12714 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12715 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12716 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12717 * | | |0 = BOD NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12718 * | | |1 = BOD NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12719 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12720 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12721 * | | |0 = IRC TRIM NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12722 * | | |1 = IRC TRIM NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12723 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12724 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12725 * | | |0 = Power-down mode wake-up NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12726 * | | |1 = Power-down mode wake-up NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12727 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12728 * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12729 * | | |0 = SRAM parity check error NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12730 * | | |1 = SRAM parity check error NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12731 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12732 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12733 * | | |0 = Clock fail detected interrupt NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12734 * | | |1 = Clock fail detected interrupt NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12735 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12736 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12737 * | | |0 = RTC NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12738 * | | |1 = RTC NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12739 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12740 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12741 * | | |0 = Backup register tamper detected interrupt.NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12742 * | | |1 = Backup register tamper detected interrupt.NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12743 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12744 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12745 * | | |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12746 * | | |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12747 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12748 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12749 * | | |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12750 * | | |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12751 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12752 * |[10] |EINT2 |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12753 * | | |0 = External interrupt from PC.0 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12754 * | | |1 = External interrupt from PC.0 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12755 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12756 * |[11] |EINT3 |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12757 * | | |0 = External interrupt from PD.0 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12758 * | | |1 = External interrupt from PD.0 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12759 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12760 * |[12] |EINT4 |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12761 * | | |0 = External interrupt from PE.0 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12762 * | | |1 = External interrupt from PE.0 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12763 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12764 * |[13] |EINT5 |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12765 * | | |0 = External interrupt from PF.0 pin NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12766 * | | |1 = External interrupt from PF.0 pin NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12767 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12768 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12769 * | | |0 = UART0 NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12770 * | | |1 = UART0 NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12771 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12772 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
AnnaBridge 171:3a7713b1edbc 12773 * | | |0 = UART1 NMI source Disabled.
AnnaBridge 171:3a7713b1edbc 12774 * | | |1 = UART1 NMI source Enabled.
AnnaBridge 171:3a7713b1edbc 12775 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 12776 * @var SYS_INT_T::NMISTS
AnnaBridge 171:3a7713b1edbc 12777 * Offset: 0x04 NMI source interrupt Status Register
AnnaBridge 171:3a7713b1edbc 12778 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12779 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12780 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12781 * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12782 * | | |0 = BOD interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12783 * | | |1 = BOD interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12784 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12785 * | | |0 = HIRC TRIM interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12786 * | | |1 = HIRC TRIM interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12787 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12788 * | | |0 = Power-down mode wake-up interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12789 * | | |1 = Power-down mode wake-up interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12790 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12791 * | | |0 = SRAM parity check error interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12792 * | | |1 = SRAM parity check error interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12793 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12794 * | | |0 = Clock fail detected interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12795 * | | |1 = Clock fail detected interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12796 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12797 * | | |0 = RTC interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12798 * | | |1 = RTC interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12799 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12800 * | | |0 = Backup register tamper detected interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12801 * | | |1 = Backup register tamper detected interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12802 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12803 * | | |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12804 * | | |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12805 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12806 * | | |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12807 * | | |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12808 * |[10] |EINT2 |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12809 * | | |0 = External Interrupt from PC.0 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12810 * | | |1 = External Interrupt from PC.0 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12811 * |[11] |EINT3 |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12812 * | | |0 = External Interrupt from PD.0 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12813 * | | |1 = External Interrupt from PD.0 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12814 * |[12] |EINT4 |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12815 * | | |0 = External Interrupt from PE.0 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12816 * | | |1 = External Interrupt from PE.0 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12817 * |[13] |EINT5 |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12818 * | | |0 = External Interrupt from PF.0 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12819 * | | |1 = External Interrupt from PF.0 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12820 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12821 * | | |0 = UART1 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12822 * | | |1 = UART1 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12823 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 12824 * | | |0 = UART1 interrupt is deasserted.
AnnaBridge 171:3a7713b1edbc 12825 * | | |1 = UART1 interrupt is asserted.
AnnaBridge 171:3a7713b1edbc 12826 */
AnnaBridge 171:3a7713b1edbc 12827
AnnaBridge 171:3a7713b1edbc 12828 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 12829 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 12830
AnnaBridge 171:3a7713b1edbc 12831 } SYS_INT_T;
AnnaBridge 171:3a7713b1edbc 12832
AnnaBridge 171:3a7713b1edbc 12833
AnnaBridge 171:3a7713b1edbc 12834
AnnaBridge 171:3a7713b1edbc 12835 /**
AnnaBridge 171:3a7713b1edbc 12836 @addtogroup INT_CONST INT Bit Field Definition
AnnaBridge 171:3a7713b1edbc 12837 Constant Definitions for SYS Controller
AnnaBridge 171:3a7713b1edbc 12838 @{ */
AnnaBridge 171:3a7713b1edbc 12839
AnnaBridge 171:3a7713b1edbc 12840 #define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */
AnnaBridge 171:3a7713b1edbc 12841 #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */
AnnaBridge 171:3a7713b1edbc 12842
AnnaBridge 171:3a7713b1edbc 12843 #define SYS_NMIEN_IRC_INT_Pos (1) /*!< SYS_INT_T::NMIEN: IRC_INT Position */
AnnaBridge 171:3a7713b1edbc 12844 #define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) /*!< SYS_INT_T::NMIEN: IRC_INT Mask */
AnnaBridge 171:3a7713b1edbc 12845
AnnaBridge 171:3a7713b1edbc 12846 #define SYS_NMIEN_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWU_INT Position */
AnnaBridge 171:3a7713b1edbc 12847 #define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask */
AnnaBridge 171:3a7713b1edbc 12848
AnnaBridge 171:3a7713b1edbc 12849 #define SYS_NMIEN_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAM_PERR Position */
AnnaBridge 171:3a7713b1edbc 12850 #define SYS_NMIEN_SRAM_PERR_Msk (0x1ul << SYS_NMIEN_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask */
AnnaBridge 171:3a7713b1edbc 12851
AnnaBridge 171:3a7713b1edbc 12852 #define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */
AnnaBridge 171:3a7713b1edbc 12853 #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */
AnnaBridge 171:3a7713b1edbc 12854
AnnaBridge 171:3a7713b1edbc 12855 #define SYS_NMIEN_RTC_INT_Pos (6) /*!< SYS_INT_T::NMIEN: RTC_INT Position */
AnnaBridge 171:3a7713b1edbc 12856 #define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) /*!< SYS_INT_T::NMIEN: RTC_INT Mask */
AnnaBridge 171:3a7713b1edbc 12857
AnnaBridge 171:3a7713b1edbc 12858 #define SYS_NMIEN_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPER_INT Position */
AnnaBridge 171:3a7713b1edbc 12859 #define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask */
AnnaBridge 171:3a7713b1edbc 12860
AnnaBridge 171:3a7713b1edbc 12861 #define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */
AnnaBridge 171:3a7713b1edbc 12862 #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */
AnnaBridge 171:3a7713b1edbc 12863
AnnaBridge 171:3a7713b1edbc 12864 #define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */
AnnaBridge 171:3a7713b1edbc 12865 #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */
AnnaBridge 171:3a7713b1edbc 12866
AnnaBridge 171:3a7713b1edbc 12867 #define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */
AnnaBridge 171:3a7713b1edbc 12868 #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */
AnnaBridge 171:3a7713b1edbc 12869
AnnaBridge 171:3a7713b1edbc 12870 #define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */
AnnaBridge 171:3a7713b1edbc 12871 #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */
AnnaBridge 171:3a7713b1edbc 12872
AnnaBridge 171:3a7713b1edbc 12873 #define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */
AnnaBridge 171:3a7713b1edbc 12874 #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */
AnnaBridge 171:3a7713b1edbc 12875
AnnaBridge 171:3a7713b1edbc 12876 #define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */
AnnaBridge 171:3a7713b1edbc 12877 #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */
AnnaBridge 171:3a7713b1edbc 12878
AnnaBridge 171:3a7713b1edbc 12879 #define SYS_NMIEN_UART0_INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0_INT Position */
AnnaBridge 171:3a7713b1edbc 12880 #define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0_INT Mask */
AnnaBridge 171:3a7713b1edbc 12881
AnnaBridge 171:3a7713b1edbc 12882 #define SYS_NMIEN_UART1_INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1_INT Position */
AnnaBridge 171:3a7713b1edbc 12883 #define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1_INT Mask */
AnnaBridge 171:3a7713b1edbc 12884
AnnaBridge 171:3a7713b1edbc 12885 #define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */
AnnaBridge 171:3a7713b1edbc 12886 #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */
AnnaBridge 171:3a7713b1edbc 12887
AnnaBridge 171:3a7713b1edbc 12888 #define SYS_NMISTS_IRC_INT_Pos (1) /*!< SYS_INT_T::NMISTS: IRC_INT Position */
AnnaBridge 171:3a7713b1edbc 12889 #define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) /*!< SYS_INT_T::NMISTS: IRC_INT Mask */
AnnaBridge 171:3a7713b1edbc 12890
AnnaBridge 171:3a7713b1edbc 12891 #define SYS_NMISTS_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWU_INT Position */
AnnaBridge 171:3a7713b1edbc 12892 #define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask */
AnnaBridge 171:3a7713b1edbc 12893
AnnaBridge 171:3a7713b1edbc 12894 #define SYS_NMISTS_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAM_PERR Position */
AnnaBridge 171:3a7713b1edbc 12895 #define SYS_NMISTS_SRAM_PERR_Msk (0x1ul << SYS_NMISTS_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask */
AnnaBridge 171:3a7713b1edbc 12896
AnnaBridge 171:3a7713b1edbc 12897 #define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */
AnnaBridge 171:3a7713b1edbc 12898 #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */
AnnaBridge 171:3a7713b1edbc 12899
AnnaBridge 171:3a7713b1edbc 12900 #define SYS_NMISTS_RTC_INT_Pos (6) /*!< SYS_INT_T::NMISTS: RTC_INT Position */
AnnaBridge 171:3a7713b1edbc 12901 #define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) /*!< SYS_INT_T::NMISTS: RTC_INT Mask */
AnnaBridge 171:3a7713b1edbc 12902
AnnaBridge 171:3a7713b1edbc 12903 #define SYS_NMISTS_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPER_INT Position */
AnnaBridge 171:3a7713b1edbc 12904 #define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask */
AnnaBridge 171:3a7713b1edbc 12905
AnnaBridge 171:3a7713b1edbc 12906 #define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */
AnnaBridge 171:3a7713b1edbc 12907 #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */
AnnaBridge 171:3a7713b1edbc 12908
AnnaBridge 171:3a7713b1edbc 12909 #define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */
AnnaBridge 171:3a7713b1edbc 12910 #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */
AnnaBridge 171:3a7713b1edbc 12911
AnnaBridge 171:3a7713b1edbc 12912 #define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */
AnnaBridge 171:3a7713b1edbc 12913 #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */
AnnaBridge 171:3a7713b1edbc 12914
AnnaBridge 171:3a7713b1edbc 12915 #define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */
AnnaBridge 171:3a7713b1edbc 12916 #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */
AnnaBridge 171:3a7713b1edbc 12917
AnnaBridge 171:3a7713b1edbc 12918 #define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */
AnnaBridge 171:3a7713b1edbc 12919 #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */
AnnaBridge 171:3a7713b1edbc 12920
AnnaBridge 171:3a7713b1edbc 12921 #define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */
AnnaBridge 171:3a7713b1edbc 12922 #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */
AnnaBridge 171:3a7713b1edbc 12923
AnnaBridge 171:3a7713b1edbc 12924 #define SYS_NMISTS_UART0_INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */
AnnaBridge 171:3a7713b1edbc 12925 #define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */
AnnaBridge 171:3a7713b1edbc 12926
AnnaBridge 171:3a7713b1edbc 12927 #define SYS_NMISTS_UART1_INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */
AnnaBridge 171:3a7713b1edbc 12928 #define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */
AnnaBridge 171:3a7713b1edbc 12929
AnnaBridge 171:3a7713b1edbc 12930 /**@}*/ /* INT_CONST */
AnnaBridge 171:3a7713b1edbc 12931 /**@}*/ /* end of SYS register group */
AnnaBridge 171:3a7713b1edbc 12932
AnnaBridge 171:3a7713b1edbc 12933
AnnaBridge 171:3a7713b1edbc 12934 /*---------------------- Touch Key Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 12935 /**
AnnaBridge 171:3a7713b1edbc 12936 @addtogroup TK Touch Key Controller(TK)
AnnaBridge 171:3a7713b1edbc 12937 Memory Mapped Structure for TK Controller
AnnaBridge 171:3a7713b1edbc 12938 @{ */
AnnaBridge 171:3a7713b1edbc 12939
AnnaBridge 171:3a7713b1edbc 12940
AnnaBridge 171:3a7713b1edbc 12941 typedef struct
AnnaBridge 171:3a7713b1edbc 12942 {
AnnaBridge 171:3a7713b1edbc 12943
AnnaBridge 171:3a7713b1edbc 12944
AnnaBridge 171:3a7713b1edbc 12945 /**
AnnaBridge 171:3a7713b1edbc 12946 * @var TK_T::CTL
AnnaBridge 171:3a7713b1edbc 12947 * Offset: 0x00 Touch Key Scan Control Register
AnnaBridge 171:3a7713b1edbc 12948 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12949 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 12950 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 12951 * |[0] |TKSEN0 |TK0 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12952 * | | |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
AnnaBridge 171:3a7713b1edbc 12953 * | | |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 12954 * | | |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
AnnaBridge 171:3a7713b1edbc 12955 * |[1] |TKSEN1 |TK1 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12956 * | | |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
AnnaBridge 171:3a7713b1edbc 12957 * | | |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 12958 * | | |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
AnnaBridge 171:3a7713b1edbc 12959 * |[2] |TKSEN2 |TK2 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12960 * | | |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
AnnaBridge 171:3a7713b1edbc 12961 * | | |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 12962 * | | |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
AnnaBridge 171:3a7713b1edbc 12963 * |[3] |TKSEN3 |TK3 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12964 * | | |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 12965 * | | |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
AnnaBridge 171:3a7713b1edbc 12966 * | | |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
AnnaBridge 171:3a7713b1edbc 12967 * |[4] |TKSEN4 |TK4 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12968 * | | |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
AnnaBridge 171:3a7713b1edbc 12969 * | | |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 12970 * | | |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
AnnaBridge 171:3a7713b1edbc 12971 * |[5] |TKSEN5 |TK5 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12972 * | | |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
AnnaBridge 171:3a7713b1edbc 12973 * | | |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 12974 * | | |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
AnnaBridge 171:3a7713b1edbc 12975 * |[6] |TKSEN6 |TK6 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12976 * | | |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
AnnaBridge 171:3a7713b1edbc 12977 * | | |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 12978 * | | |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
AnnaBridge 171:3a7713b1edbc 12979 * |[7] |TKSEN7 |TK7 Scan Enable
AnnaBridge 171:3a7713b1edbc 12980 * | | |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
AnnaBridge 171:3a7713b1edbc 12981 * | | |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 12982 * | | |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
AnnaBridge 171:3a7713b1edbc 12983 * |[8] |TKSEN8 |TK8 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12984 * | | |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
AnnaBridge 171:3a7713b1edbc 12985 * | | |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 12986 * | | |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
AnnaBridge 171:3a7713b1edbc 12987 * |[9] |TKSEN9 |TK9 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12988 * | | |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
AnnaBridge 171:3a7713b1edbc 12989 * | | |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 12990 * | | |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
AnnaBridge 171:3a7713b1edbc 12991 * |[10] |TKSEN10 |TK10 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 12992 * | | |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
AnnaBridge 171:3a7713b1edbc 12993 * | | |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 12994 * | | |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
AnnaBridge 171:3a7713b1edbc 12995 * |[11] |TKSEN11 |TK11 Scan Enable
AnnaBridge 171:3a7713b1edbc 12996 * | | |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
AnnaBridge 171:3a7713b1edbc 12997 * | | |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 12998 * | | |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
AnnaBridge 171:3a7713b1edbc 12999 * |[12] |TKSEN12 |TK12 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13000 * | | |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
AnnaBridge 171:3a7713b1edbc 13001 * | | |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13002 * | | |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
AnnaBridge 171:3a7713b1edbc 13003 * |[13] |TKSEN13 |TK13 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13004 * | | |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
AnnaBridge 171:3a7713b1edbc 13005 * | | |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 13006 * | | |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
AnnaBridge 171:3a7713b1edbc 13007 * |[14] |TKSEN14 |TK14 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13008 * | | |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
AnnaBridge 171:3a7713b1edbc 13009 * | | |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 13010 * | | |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
AnnaBridge 171:3a7713b1edbc 13011 * |[15] |TKSEN15 |TK15 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13012 * | | |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
AnnaBridge 171:3a7713b1edbc 13013 * | | |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 13014 * | | |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
AnnaBridge 171:3a7713b1edbc 13015 * |[16] |TKSEN16 |TK16 Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13016 * | | |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
AnnaBridge 171:3a7713b1edbc 13017 * | | |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13018 * | | |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
AnnaBridge 171:3a7713b1edbc 13019 * |[22:20] |AVCCHSEL |AVCCH Voltage Select
AnnaBridge 171:3a7713b1edbc 13020 * | | |000 = 1/16 VDD.
AnnaBridge 171:3a7713b1edbc 13021 * | | |001 = 1/8 VDD.
AnnaBridge 171:3a7713b1edbc 13022 * | | |010 = 3/16 VDD.
AnnaBridge 171:3a7713b1edbc 13023 * | | |011 = 1/4 VDD.
AnnaBridge 171:3a7713b1edbc 13024 * | | |100 = 5/16 VDD.
AnnaBridge 171:3a7713b1edbc 13025 * | | |101 = 3/8 VDD.
AnnaBridge 171:3a7713b1edbc 13026 * | | |110 = 7/16 VDD.
AnnaBridge 171:3a7713b1edbc 13027 * | | |111 = 1/2 VDD.
AnnaBridge 171:3a7713b1edbc 13028 * |[24] |SCAN |Scan
AnnaBridge 171:3a7713b1edbc 13029 * | | |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
AnnaBridge 171:3a7713b1edbc 13030 * | | |This bit will be self-cleared after key scan started.
AnnaBridge 171:3a7713b1edbc 13031 * |[25] |TMRTRGEN |Timer Trigger Enable Bit
AnnaBridge 171:3a7713b1edbc 13032 * | | |0 = Disable timer to trigger key scan.
AnnaBridge 171:3a7713b1edbc 13033 * | | |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
AnnaBridge 171:3a7713b1edbc 13034 * |[31] |TKEN |Touch Key Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13035 * | | |0 = Disable Touch Key Function.
AnnaBridge 171:3a7713b1edbc 13036 * | | |1 = Enable Touch Key Function.
AnnaBridge 171:3a7713b1edbc 13037 * @var TK_T::REFCTL
AnnaBridge 171:3a7713b1edbc 13038 * Offset: 0x04 Touch Key Reference Control Register
AnnaBridge 171:3a7713b1edbc 13039 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13040 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13041 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13042 * |[0] |TKREN0 |TK0 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13043 * | | |0 = TK0 is not reference.
AnnaBridge 171:3a7713b1edbc 13044 * | | |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
AnnaBridge 171:3a7713b1edbc 13045 * |[1] |TKREN1 |TK1 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13046 * | | |0 = TK1 is not reference.
AnnaBridge 171:3a7713b1edbc 13047 * | | |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 13048 * |[2] |TKREN2 |TK2 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13049 * | | |0 = TK2 is not reference.
AnnaBridge 171:3a7713b1edbc 13050 * | | |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 13051 * |[3] |TKREN3 |TK3 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13052 * | | |0 = TK3 is not reference.
AnnaBridge 171:3a7713b1edbc 13053 * | | |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 13054 * |[4] |TKREN4 |TK4 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13055 * | | |0 = TK4 is not reference.
AnnaBridge 171:3a7713b1edbc 13056 * | | |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13057 * |[5] |TKREN5 |TK5 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13058 * | | |0 = TK5 is not reference.
AnnaBridge 171:3a7713b1edbc 13059 * | | |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 13060 * |[6] |TKREN6 |TK6 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13061 * | | |0 = TK6 is not reference.
AnnaBridge 171:3a7713b1edbc 13062 * | | |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 13063 * |[7] |TKREN7 |TK7 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13064 * | | |0 = TK7 is not reference.
AnnaBridge 171:3a7713b1edbc 13065 * | | |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 13066 * |[8] |TKREN8 |TK8 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13067 * | | |0 = TK8 is not reference.
AnnaBridge 171:3a7713b1edbc 13068 * | | |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13069 * |[9] |TKREN9 |TK9 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13070 * | | |0 = TK9 is not reference.
AnnaBridge 171:3a7713b1edbc 13071 * | | |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 13072 * |[10] |TKREN10 |TK10 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13073 * | | |0 = TK10 is not reference.
AnnaBridge 171:3a7713b1edbc 13074 * | | |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 13075 * |[11] |TKREN11 |TK11 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13076 * | | |0 = TK11 is not reference.
AnnaBridge 171:3a7713b1edbc 13077 * | | |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 13078 * |[12] |TKREN12 |TK12 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13079 * | | |0 = TK12 is not reference.
AnnaBridge 171:3a7713b1edbc 13080 * | | |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13081 * |[13] |TKREN13 |TK13 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13082 * | | |0 = TK13 is not reference.
AnnaBridge 171:3a7713b1edbc 13083 * | | |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
AnnaBridge 171:3a7713b1edbc 13084 * |[14] |TKREN14 |TK14 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13085 * | | |0 = TK14 is not reference.
AnnaBridge 171:3a7713b1edbc 13086 * | | |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
AnnaBridge 171:3a7713b1edbc 13087 * |[15] |TKREN15 |TK15 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13088 * | | |0 = TK15 is not reference.
AnnaBridge 171:3a7713b1edbc 13089 * | | |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
AnnaBridge 171:3a7713b1edbc 13090 * |[16] |TKREN16 |TK16 Reference Enable Bit
AnnaBridge 171:3a7713b1edbc 13091 * | | |0 = TK16 is not reference.
AnnaBridge 171:3a7713b1edbc 13092 * | | |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
AnnaBridge 171:3a7713b1edbc 13093 * | | |Note: This bit is forced to "1" automatically if none is set as reference.
AnnaBridge 171:3a7713b1edbc 13094 * |[23] |SCANALL |All Key Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 13095 * | | |This function is used for low power key scanning operation.
AnnaBridge 171:3a7713b1edbc 13096 * | | |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
AnnaBridge 171:3a7713b1edbc 13097 * | | |0 = Disable All Keys Scan function.
AnnaBridge 171:3a7713b1edbc 13098 * | | |1 = Enable All Keys Scan function.
AnnaBridge 171:3a7713b1edbc 13099 * |[25:24] |SENTCTL |Touch Key Sensing Time Control
AnnaBridge 171:3a7713b1edbc 13100 * | | |00 = 128 x SENPTCTL.
AnnaBridge 171:3a7713b1edbc 13101 * | | |01 = 255 x SENPTCTL.
AnnaBridge 171:3a7713b1edbc 13102 * | | |10 = 511 x SENPTCTL.
AnnaBridge 171:3a7713b1edbc 13103 * | | |11 = 1023 x SENPTCTL.
AnnaBridge 171:3a7713b1edbc 13104 * |[29:28] |SENPTCTL |Touch Key Sensing Pulse Width Time Control
AnnaBridge 171:3a7713b1edbc 13105 * | | |00 = 1us.
AnnaBridge 171:3a7713b1edbc 13106 * | | |01 = 2us.
AnnaBridge 171:3a7713b1edbc 13107 * | | |10 = 4us.
AnnaBridge 171:3a7713b1edbc 13108 * | | |11 = 8us.
AnnaBridge 171:3a7713b1edbc 13109 * @var TK_T::CCBDAT0
AnnaBridge 171:3a7713b1edbc 13110 * Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0
AnnaBridge 171:3a7713b1edbc 13111 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13112 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13113 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13114 * |[7:0] |CCBDAT0 |TK0 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13115 * | | |This is register is used for TK0 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13116 * |[15:8] |CCBDAT1 |TK1 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13117 * | | |This is register is used for TK1 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13118 * |[23:16] |CCBDAT2 |TK2 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13119 * | | |This is register is used for TK2 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13120 * |[31:24] |CCBDAT3 |TK3 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13121 * | | |This is register is used for TK3 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13122 * @var TK_T::CCBDAT1
AnnaBridge 171:3a7713b1edbc 13123 * Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1
AnnaBridge 171:3a7713b1edbc 13124 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13125 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13126 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13127 * |[7:0] |CCBDAT4 |TK4 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13128 * | | |This is register is used for TK4 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13129 * |[15:8] |CCBDAT5 |TK5 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13130 * | | |This is register is used for TK5 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13131 * |[23:16] |CCBDAT6 |TK6 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13132 * | | |This is register is used for TK6 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13133 * |[31:24] |CCBDAT7 |TK7 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13134 * | | |This is register is used for TK7 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13135 * @var TK_T::CCBDAT2
AnnaBridge 171:3a7713b1edbc 13136 * Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2
AnnaBridge 171:3a7713b1edbc 13137 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13138 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13139 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13140 * |[7:0] |CCBDAT8 |TK8 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13141 * | | |This is register is used for TK8 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13142 * |[15:8] |CCBDAT9 |TK9 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13143 * | | |This is register is used for TK9 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13144 * |[23:16] |CCBDAT10 |TK10 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13145 * | | |This is register is used for TK10 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13146 * |[31:24] |CCBDAT11 |TK11 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13147 * | | |This is register is used for TK11 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13148 * @var TK_T::CCBDAT3
AnnaBridge 171:3a7713b1edbc 13149 * Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3
AnnaBridge 171:3a7713b1edbc 13150 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13151 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13152 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13153 * |[7:0] |CCBDAT12 |TK12 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13154 * | | |This is register is used for TK12 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13155 * |[15:8] |CCBDAT13 |TK13 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13156 * | | |This is register is used for TK13 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13157 * |[23:16] |CCBDAT14 |TK14 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13158 * | | |This is register is used for TK14 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13159 * |[31:24] |CCBDAT15 |TK15 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13160 * | | |This is register is used for TK15 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13161 * @var TK_T::CCBDAT4
AnnaBridge 171:3a7713b1edbc 13162 * Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4
AnnaBridge 171:3a7713b1edbc 13163 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13164 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13165 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13166 * |[7:0] |CCBDAT16 |TK16 Complement CB Data
AnnaBridge 171:3a7713b1edbc 13167 * | | |This is register is used for TK16 sensitivity adjustment.
AnnaBridge 171:3a7713b1edbc 13168 * |[31:24] |REFCBDAT |Reference CB Data
AnnaBridge 171:3a7713b1edbc 13169 * @var TK_T::IDLESEL
AnnaBridge 171:3a7713b1edbc 13170 * Offset: 0x1C Touch Key Idle State Control Register
AnnaBridge 171:3a7713b1edbc 13171 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13172 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13173 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13174 * |[31:0] |IDLSn |TKn Idle State Control
AnnaBridge 171:3a7713b1edbc 13175 * | | |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
AnnaBridge 171:3a7713b1edbc 13176 * | | |00 = TKn connected to GND.
AnnaBridge 171:3a7713b1edbc 13177 * | | |01 = TKn connected to AVCCH.
AnnaBridge 171:3a7713b1edbc 13178 * | | |10 = TKn connected to VDD.
AnnaBridge 171:3a7713b1edbc 13179 * | | |11 = TKn connected to VDD.
AnnaBridge 171:3a7713b1edbc 13180 * | | |n = 0 to 15.
AnnaBridge 171:3a7713b1edbc 13181 * @var TK_T::POLSEL
AnnaBridge 171:3a7713b1edbc 13182 * Offset: 0x20 Touch Key Polarity Select Register
AnnaBridge 171:3a7713b1edbc 13183 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13184 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13185 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13186 * |[31:0] |POLSELn |TKn Polarity Select
AnnaBridge 171:3a7713b1edbc 13187 * | | |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
AnnaBridge 171:3a7713b1edbc 13188 * | | |00 = TKn connected to Gnd.
AnnaBridge 171:3a7713b1edbc 13189 * | | |01 = TKn connected to AVCCH.
AnnaBridge 171:3a7713b1edbc 13190 * | | |10 = TKn connected to VDD.
AnnaBridge 171:3a7713b1edbc 13191 * | | |11 = TKn connected to VDD.
AnnaBridge 171:3a7713b1edbc 13192 * @var TK_T::POLCTL
AnnaBridge 171:3a7713b1edbc 13193 * Offset: 0x24 Touch Key Polarity Control Register
AnnaBridge 171:3a7713b1edbc 13194 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13195 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13196 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13197 * |[1:0] |IDLS16 |TK16 Idle State Control
AnnaBridge 171:3a7713b1edbc 13198 * | | |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
AnnaBridge 171:3a7713b1edbc 13199 * | | |00 = TK16 connected to Gnd.
AnnaBridge 171:3a7713b1edbc 13200 * | | |01 = TK16 connected to AVCCH.
AnnaBridge 171:3a7713b1edbc 13201 * | | |10 = TK16 connected to VDD.
AnnaBridge 171:3a7713b1edbc 13202 * | | |11 = TK16 connected to VDD.
AnnaBridge 171:3a7713b1edbc 13203 * |[3:2] |POLSEL16 |TK16 Polarity Control
AnnaBridge 171:3a7713b1edbc 13204 * | | |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
AnnaBridge 171:3a7713b1edbc 13205 * | | |00 = TK16 connected to Gnd.
AnnaBridge 171:3a7713b1edbc 13206 * | | |01 = TK16 connected to AVCCH.
AnnaBridge 171:3a7713b1edbc 13207 * | | |10 = TK16 connected to VDD.
AnnaBridge 171:3a7713b1edbc 13208 * | | |11 = TK16 connected to VDD.
AnnaBridge 171:3a7713b1edbc 13209 * |[5:4] |CBPOLSEL |Capacitor Bank Polarity Select
AnnaBridge 171:3a7713b1edbc 13210 * | | |00 = Gnd.
AnnaBridge 171:3a7713b1edbc 13211 * | | |01 = AVCCH.
AnnaBridge 171:3a7713b1edbc 13212 * | | |10 = VDD.
AnnaBridge 171:3a7713b1edbc 13213 * | | |11 = VDD.
AnnaBridge 171:3a7713b1edbc 13214 * |[8] |POLEN0 |TK0 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13215 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13216 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13217 * |[9] |POLEN1 |TK1 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13218 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13219 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13220 * |[10] |POLEN2 |TK2 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13221 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13222 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13223 * |[11] |POLEN3 |TK3 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13224 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13225 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13226 * |[12] |POLEN4 |TK4 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13227 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13228 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13229 * |[13] |POLEN5 |TK5 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13230 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13231 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13232 * |[14] |POLEN6 |TK6 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13233 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13234 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13235 * |[15] |POLEN7 |TK7 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13236 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13237 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13238 * |[16] |POLEN8 |TK8 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13239 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13240 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13241 * |[17] |POLEN9 |TK9 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13242 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13243 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13244 * |[18] |POLEN10 |TK10 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13245 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13246 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13247 * |[19] |POLEN11 |TK11 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13248 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13249 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13250 * |[20] |POLEN12 |TK12 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13251 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13252 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13253 * |[21] |POLEN13 |TK13 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13254 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13255 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13256 * |[22] |POLEN14 |TK14 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13257 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13258 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13259 * |[23] |POLEN15 |TK15 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13260 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13261 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13262 * |[24] |POLEN16 |TK16 Polarity Function Enable Control
AnnaBridge 171:3a7713b1edbc 13263 * | | |0 = Disabled.
AnnaBridge 171:3a7713b1edbc 13264 * | | |1 = Enabled.
AnnaBridge 171:3a7713b1edbc 13265 * |[31] |SPOTINIT |Touch Key Sensing Initial Potential Control
AnnaBridge 171:3a7713b1edbc 13266 * | | |0 = Key pad is connected to Gnd before sensing.
AnnaBridge 171:3a7713b1edbc 13267 * | | |1 = Key pad is connected to AVCCH before sensing.
AnnaBridge 171:3a7713b1edbc 13268 * @var TK_T::STATUS
AnnaBridge 171:3a7713b1edbc 13269 * Offset: 0x28 Touch Key Status Register
AnnaBridge 171:3a7713b1edbc 13270 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13271 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13272 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13273 * |[0] |BUSY |Touch Key Busy (Read Only)
AnnaBridge 171:3a7713b1edbc 13274 * | | |0 = Key scan is complete or stopped.
AnnaBridge 171:3a7713b1edbc 13275 * | | |1 = Key scan is proceeding.
AnnaBridge 171:3a7713b1edbc 13276 * |[1] |SCIF |Touch Key Scan Complete Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13277 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13278 * | | |0 = Key scan is proceeding and data is not ready for read.
AnnaBridge 171:3a7713b1edbc 13279 * | | |1 = Key scan is complete and data is ready for read in TKDATx registers.
AnnaBridge 171:3a7713b1edbc 13280 * | | |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
AnnaBridge 171:3a7713b1edbc 13281 * | | |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
AnnaBridge 171:3a7713b1edbc 13282 * |[8] |TKIF0 |TK0 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13283 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13284 * | | |0 = No threshold control event with TK0.
AnnaBridge 171:3a7713b1edbc 13285 * | | |1 = Threshold control event occurs with TK0.
AnnaBridge 171:3a7713b1edbc 13286 * |[9] |TKIF1 |TK1 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13287 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13288 * | | |0 = No threshold control event with TK1.
AnnaBridge 171:3a7713b1edbc 13289 * | | |1 = Threshold control event occurs with TK1.
AnnaBridge 171:3a7713b1edbc 13290 * |[10] |TKIF2 |TK2 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13291 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13292 * | | |0 = No threshold control event with TK2.
AnnaBridge 171:3a7713b1edbc 13293 * | | |1 = Threshold control event occurs with TK2.
AnnaBridge 171:3a7713b1edbc 13294 * |[11] |TKIF3 |TK3 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13295 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13296 * | | |0 = No threshold control event with TK3.
AnnaBridge 171:3a7713b1edbc 13297 * | | |1 = Threshold control event occurs with TK3.
AnnaBridge 171:3a7713b1edbc 13298 * |[12] |TKIF4 |TK4 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13299 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13300 * | | |0 = No threshold control event with TK4.
AnnaBridge 171:3a7713b1edbc 13301 * | | |1 = Threshold control event occurs with TK4.
AnnaBridge 171:3a7713b1edbc 13302 * |[13] |TKIF5 |TK5 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13303 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13304 * | | |0 = No threshold control event with TK5.
AnnaBridge 171:3a7713b1edbc 13305 * | | |1 = Threshold control event occurs with TK5.
AnnaBridge 171:3a7713b1edbc 13306 * |[14] |TKIF6 |TK6 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13307 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13308 * | | |0 = No threshold control event with TK6.
AnnaBridge 171:3a7713b1edbc 13309 * | | |1 = Threshold control event occurs with TK6.
AnnaBridge 171:3a7713b1edbc 13310 * |[15] |TKIF7 |TK7 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13311 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13312 * | | |0 = No threshold control event with TK7.
AnnaBridge 171:3a7713b1edbc 13313 * | | |1 = Threshold control event occurs with TK7.
AnnaBridge 171:3a7713b1edbc 13314 * |[16] |TKIF8 |TK8 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13315 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13316 * | | |0 = No threshold control event with TK8.
AnnaBridge 171:3a7713b1edbc 13317 * | | |1 = Threshold control event occurs with TK8.
AnnaBridge 171:3a7713b1edbc 13318 * |[17] |TKIF9 |TK9 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13319 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13320 * | | |0 = No threshold control event with TK9.
AnnaBridge 171:3a7713b1edbc 13321 * | | |1 = Threshold control event occurs with TK9.
AnnaBridge 171:3a7713b1edbc 13322 * |[18] |TKIF10 |TK10 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13323 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13324 * | | |0 = No threshold control event with TK10.
AnnaBridge 171:3a7713b1edbc 13325 * | | |1 = Threshold control event occurs with TK10.
AnnaBridge 171:3a7713b1edbc 13326 * |[19] |TKIF11 |TK11 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13327 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13328 * | | |0 = No threshold control event with TK11.
AnnaBridge 171:3a7713b1edbc 13329 * | | |1 = Threshold control event occurs with TK11.
AnnaBridge 171:3a7713b1edbc 13330 * |[20] |TKIF12 |TK12 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13331 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13332 * | | |0 = No threshold control event with TK12.
AnnaBridge 171:3a7713b1edbc 13333 * | | |1 = Threshold control event occurs with TK12.
AnnaBridge 171:3a7713b1edbc 13334 * |[21] |TKIF13 |TK13 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13335 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13336 * | | |0 = No threshold control event with TK13.
AnnaBridge 171:3a7713b1edbc 13337 * | | |1 = Threshold control event occurs with TK13.
AnnaBridge 171:3a7713b1edbc 13338 * |[22] |TKIF14 |TK14 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13339 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13340 * | | |0 = No threshold control event with TK14.
AnnaBridge 171:3a7713b1edbc 13341 * | | |1 = Threshold control event occurs with TK14.
AnnaBridge 171:3a7713b1edbc 13342 * |[23] |TKIF15 |TK15 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13343 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13344 * | | |0 = No threshold control event with TK15.
AnnaBridge 171:3a7713b1edbc 13345 * | | |1 = Threshold control event occurs with TK15.
AnnaBridge 171:3a7713b1edbc 13346 * |[24] |TKIF16 |TK16 Interrupt Flag
AnnaBridge 171:3a7713b1edbc 13347 * | | |This bit will be cleared by writing a "1" to this bit.
AnnaBridge 171:3a7713b1edbc 13348 * | | |0 = No threshold control event with TK16.
AnnaBridge 171:3a7713b1edbc 13349 * | | |1 = Threshold control event occurs with TK16.
AnnaBridge 171:3a7713b1edbc 13350 * @var TK_T::DAT0
AnnaBridge 171:3a7713b1edbc 13351 * Offset: 0x2C Touch Key Data Register 0
AnnaBridge 171:3a7713b1edbc 13352 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13353 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13354 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13355 * |[7:0] |TKDAT0 |TK0 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13356 * | | |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
AnnaBridge 171:3a7713b1edbc 13357 * |[15:8] |TKDAT1 |TK1 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13358 * | | |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
AnnaBridge 171:3a7713b1edbc 13359 * |[23:16] |TKDAT2 |TK2 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13360 * | | |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
AnnaBridge 171:3a7713b1edbc 13361 * |[31:24] |TKDAT3 |TK3 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13362 * | | |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
AnnaBridge 171:3a7713b1edbc 13363 * @var TK_T::DAT1
AnnaBridge 171:3a7713b1edbc 13364 * Offset: 0x30 Touch Key Data Register 1
AnnaBridge 171:3a7713b1edbc 13365 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13366 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13367 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13368 * |[7:0] |TKDAT4 |TK0 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13369 * | | |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
AnnaBridge 171:3a7713b1edbc 13370 * |[15:8] |TKDAT5 |TK5 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13371 * | | |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
AnnaBridge 171:3a7713b1edbc 13372 * |[23:16] |TKDAT6 |TK6 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13373 * | | |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
AnnaBridge 171:3a7713b1edbc 13374 * |[31:24] |TKDAT7 |TK7 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13375 * | | |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
AnnaBridge 171:3a7713b1edbc 13376 * @var TK_T::DAT2
AnnaBridge 171:3a7713b1edbc 13377 * Offset: 0x34 Touch Key Data Register 2
AnnaBridge 171:3a7713b1edbc 13378 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13379 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13380 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13381 * |[7:0] |TKDAT8 |TK8 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13382 * | | |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
AnnaBridge 171:3a7713b1edbc 13383 * |[15:8] |TKDAT9 |TK9 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13384 * | | |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
AnnaBridge 171:3a7713b1edbc 13385 * |[23:16] |TKDAT10 |TK10 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13386 * | | |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
AnnaBridge 171:3a7713b1edbc 13387 * |[31:24] |TKDAT11 |TK11 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13388 * | | |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
AnnaBridge 171:3a7713b1edbc 13389 * @var TK_T::DAT3
AnnaBridge 171:3a7713b1edbc 13390 * Offset: 0x38 Touch Key Data Register 3
AnnaBridge 171:3a7713b1edbc 13391 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13392 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13393 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13394 * |[7:0] |TKDAT12 |TK12 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13395 * | | |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
AnnaBridge 171:3a7713b1edbc 13396 * |[15:8] |TKDAT13 |TK13 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13397 * | | |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
AnnaBridge 171:3a7713b1edbc 13398 * |[23:16] |TKDAT14 |TK14 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13399 * | | |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
AnnaBridge 171:3a7713b1edbc 13400 * |[31:24] |TKDAT15 |TK15 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13401 * | | |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
AnnaBridge 171:3a7713b1edbc 13402 * @var TK_T::DAT4
AnnaBridge 171:3a7713b1edbc 13403 * Offset: 0x3C Touch Key Data Register 4
AnnaBridge 171:3a7713b1edbc 13404 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13405 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13406 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13407 * |[7:0] |TKDAT16 |TK16 Sensing Result Data (Read Only)
AnnaBridge 171:3a7713b1edbc 13408 * | | |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
AnnaBridge 171:3a7713b1edbc 13409 * @var TK_T::INTEN
AnnaBridge 171:3a7713b1edbc 13410 * Offset: 0x40 Touch Key Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 13411 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13412 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13413 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13414 * |[0] |SCTHIEN |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 13415 * | | |0 = Key scan complete with threshold control interrupt is disable.
AnnaBridge 171:3a7713b1edbc 13416 * | | |1 = Key scan complete with threshold control interrupt is enable.
AnnaBridge 171:3a7713b1edbc 13417 * |[1] |SCINTEN |Touch Key Scan Complete Interrupt Enable
AnnaBridge 171:3a7713b1edbc 13418 * | | |Bit
AnnaBridge 171:3a7713b1edbc 13419 * | | |0 = Key scan complete without threshold control interrupt is disable.
AnnaBridge 171:3a7713b1edbc 13420 * | | |1 = Key scan complete without threshold control interrupt is enable.
AnnaBridge 171:3a7713b1edbc 13421 * |[31] |THIMOD |Touch Key Threshold Interrupt Mode Select
AnnaBridge 171:3a7713b1edbc 13422 * | | |0 = Edge trigger mode.
AnnaBridge 171:3a7713b1edbc 13423 * | | |1 = Level trigger mode.
AnnaBridge 171:3a7713b1edbc 13424 * @var TK_T::TH0_1
AnnaBridge 171:3a7713b1edbc 13425 * Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13426 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13427 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13428 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13429 * |[7:0] |LTH0 |Low Threshold Of TK0
AnnaBridge 171:3a7713b1edbc 13430 * | | |Low level for TK0 threshold control.
AnnaBridge 171:3a7713b1edbc 13431 * |[15:8] |HTH0 |High Threshold Of TK0
AnnaBridge 171:3a7713b1edbc 13432 * | | |High level for TK0 threshold control.
AnnaBridge 171:3a7713b1edbc 13433 * |[23:16] |LTH1 |Low Threshold Of TK1
AnnaBridge 171:3a7713b1edbc 13434 * | | |Low level for TK1 threshold control.
AnnaBridge 171:3a7713b1edbc 13435 * |[31:24] |HTH1 |High Threshold Of TK1
AnnaBridge 171:3a7713b1edbc 13436 * | | |High level for TK1 threshold control.
AnnaBridge 171:3a7713b1edbc 13437 * @var TK_T::TH2_3
AnnaBridge 171:3a7713b1edbc 13438 * Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13439 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13440 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13441 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13442 * |[7:0] |LTH2 |Low Threshold Of TK2
AnnaBridge 171:3a7713b1edbc 13443 * | | |Low level for TK2 threshold control.
AnnaBridge 171:3a7713b1edbc 13444 * |[15:8] |HTH2 |High Threshold Of TK2
AnnaBridge 171:3a7713b1edbc 13445 * | | |High level for TK2 threshold control.
AnnaBridge 171:3a7713b1edbc 13446 * |[23:16] |LTH3 |Low Threshold Of TK3
AnnaBridge 171:3a7713b1edbc 13447 * | | |Low level for TK3 threshold control.
AnnaBridge 171:3a7713b1edbc 13448 * |[31:24] |HTH3 |High Threshold Of TK3
AnnaBridge 171:3a7713b1edbc 13449 * | | |High level for TK3 threshold control.
AnnaBridge 171:3a7713b1edbc 13450 * @var TK_T::TH4_5
AnnaBridge 171:3a7713b1edbc 13451 * Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13452 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13453 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13454 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13455 * |[7:0] |LTH4 |Low Threshold Of TK4
AnnaBridge 171:3a7713b1edbc 13456 * | | |Low level for TK4 threshold control.
AnnaBridge 171:3a7713b1edbc 13457 * |[15:8] |HTH4 |High Threshold Of TK4
AnnaBridge 171:3a7713b1edbc 13458 * | | |High level for TK4 threshold control.
AnnaBridge 171:3a7713b1edbc 13459 * |[23:16] |LTH5 |Low Threshold Of TK5
AnnaBridge 171:3a7713b1edbc 13460 * | | |Low level for TK5 threshold control.
AnnaBridge 171:3a7713b1edbc 13461 * |[31:24] |HTH5 |High Threshold Of TK5
AnnaBridge 171:3a7713b1edbc 13462 * | | |High level for TK5 threshold control.
AnnaBridge 171:3a7713b1edbc 13463 * @var TK_T::TH6_7
AnnaBridge 171:3a7713b1edbc 13464 * Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13465 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13466 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13467 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13468 * |[7:0] |LTH6 |Low Threshold Of TK6
AnnaBridge 171:3a7713b1edbc 13469 * | | |Low level for TK6 threshold control.
AnnaBridge 171:3a7713b1edbc 13470 * |[15:8] |HTH6 |High Threshold Of TK6
AnnaBridge 171:3a7713b1edbc 13471 * | | |High level for TK6 threshold control.
AnnaBridge 171:3a7713b1edbc 13472 * |[23:16] |LTH7 |Low Threshold Of TK7
AnnaBridge 171:3a7713b1edbc 13473 * | | |Low level for TK7 threshold control.
AnnaBridge 171:3a7713b1edbc 13474 * |[31:24] |HTH7 |High Threshold Of TK7
AnnaBridge 171:3a7713b1edbc 13475 * | | |High level for TK7 threshold control.
AnnaBridge 171:3a7713b1edbc 13476 * @var TK_T::TH8_9
AnnaBridge 171:3a7713b1edbc 13477 * Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13478 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13479 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13480 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13481 * |[7:0] |LTH8 |Low Threshold Of TK8
AnnaBridge 171:3a7713b1edbc 13482 * | | |Low level for TK8 threshold control.
AnnaBridge 171:3a7713b1edbc 13483 * |[15:8] |HTH8 |High Threshold Of TK8
AnnaBridge 171:3a7713b1edbc 13484 * | | |High level for TK8 threshold control.
AnnaBridge 171:3a7713b1edbc 13485 * |[23:16] |LTH9 |Low Threshold Of TK9
AnnaBridge 171:3a7713b1edbc 13486 * | | |Low level for TK9 threshold control.
AnnaBridge 171:3a7713b1edbc 13487 * |[31:24] |HTH9 |High Threshold Of TK9
AnnaBridge 171:3a7713b1edbc 13488 * | | |High level for TK9 threshold control.
AnnaBridge 171:3a7713b1edbc 13489 * @var TK_T::TH10_11
AnnaBridge 171:3a7713b1edbc 13490 * Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13491 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13492 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13493 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13494 * |[7:0] |LTH10 |Low Threshold Of TK10
AnnaBridge 171:3a7713b1edbc 13495 * | | |Low level for TK10 threshold control.
AnnaBridge 171:3a7713b1edbc 13496 * |[15:8] |HTH10 |High Threshold Of TK10
AnnaBridge 171:3a7713b1edbc 13497 * | | |High level for TK10 threshold control.
AnnaBridge 171:3a7713b1edbc 13498 * |[23:16] |LTH11 |Low Threshold Of TK11
AnnaBridge 171:3a7713b1edbc 13499 * | | |Low level for TK11 threshold control.
AnnaBridge 171:3a7713b1edbc 13500 * |[31:24] |HTH11 |High Threshold Of TK11
AnnaBridge 171:3a7713b1edbc 13501 * | | |High level for TK11 threshold control.
AnnaBridge 171:3a7713b1edbc 13502 * @var TK_T::TH12_13
AnnaBridge 171:3a7713b1edbc 13503 * Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13504 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13505 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13506 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13507 * |[7:0] |LTH12 |Low Threshold Of TK12
AnnaBridge 171:3a7713b1edbc 13508 * | | |Low level for TK12 threshold control.
AnnaBridge 171:3a7713b1edbc 13509 * |[15:8] |HTH12 |High Threshold Of TK12
AnnaBridge 171:3a7713b1edbc 13510 * | | |High level for TK12 threshold control.
AnnaBridge 171:3a7713b1edbc 13511 * |[23:16] |LTH13 |Low Threshold Of TK13
AnnaBridge 171:3a7713b1edbc 13512 * | | |Low level for TK13 threshold control.
AnnaBridge 171:3a7713b1edbc 13513 * |[31:24] |HTH13 |High Threshold Of TK13
AnnaBridge 171:3a7713b1edbc 13514 * | | |High level for TK13 threshold control.
AnnaBridge 171:3a7713b1edbc 13515 * @var TK_T::TH14_15
AnnaBridge 171:3a7713b1edbc 13516 * Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13517 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13518 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13519 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13520 * |[7:0] |LTH14 |Low Threshold Of TK14
AnnaBridge 171:3a7713b1edbc 13521 * | | |Low level for TK14 threshold control.
AnnaBridge 171:3a7713b1edbc 13522 * |[15:8] |HTH14 |High Threshold Of TK14
AnnaBridge 171:3a7713b1edbc 13523 * | | |High level for TK14 threshold control.
AnnaBridge 171:3a7713b1edbc 13524 * |[23:16] |LTH15 |Low Threshold Of TK15
AnnaBridge 171:3a7713b1edbc 13525 * | | |Low level for TK15 threshold control.
AnnaBridge 171:3a7713b1edbc 13526 * |[31:24] |HTH15 |High Threshold Of TK15
AnnaBridge 171:3a7713b1edbc 13527 * | | |High level for TK15 threshold control.
AnnaBridge 171:3a7713b1edbc 13528 * @var TK_T::TH16
AnnaBridge 171:3a7713b1edbc 13529 * Offset: 0x64 Touch Key TK16 Threshold Control Register
AnnaBridge 171:3a7713b1edbc 13530 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13531 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 13532 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 13533 * |[7:0] |LTH16 |Low Threshold Of TK16
AnnaBridge 171:3a7713b1edbc 13534 * | | |Low level for TK16 threshold control.
AnnaBridge 171:3a7713b1edbc 13535 * |[15:8] |HTH16 |High Threshold Of TK16
AnnaBridge 171:3a7713b1edbc 13536 * | | |High level for TK16 threshold control.
AnnaBridge 171:3a7713b1edbc 13537 */
AnnaBridge 171:3a7713b1edbc 13538
AnnaBridge 171:3a7713b1edbc 13539 __IO uint32_t CTL; /* Offset: 0x00 Touch Key Scan Control Register */
AnnaBridge 171:3a7713b1edbc 13540 __IO uint32_t REFCTL; /* Offset: 0x04 Touch Key Reference Control Register */
AnnaBridge 171:3a7713b1edbc 13541 __IO uint32_t CCBDAT0; /* Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0 */
AnnaBridge 171:3a7713b1edbc 13542 __IO uint32_t CCBDAT1; /* Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1 */
AnnaBridge 171:3a7713b1edbc 13543 __IO uint32_t CCBDAT2; /* Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2 */
AnnaBridge 171:3a7713b1edbc 13544 __IO uint32_t CCBDAT3; /* Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3 */
AnnaBridge 171:3a7713b1edbc 13545 __IO uint32_t CCBDAT4; /* Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4 */
AnnaBridge 171:3a7713b1edbc 13546 __IO uint32_t IDLESEL; /* Offset: 0x1C Touch Key Idle State Control Register */
AnnaBridge 171:3a7713b1edbc 13547 __IO uint32_t POLSEL; /* Offset: 0x20 Touch Key Polarity Select Register */
AnnaBridge 171:3a7713b1edbc 13548 __IO uint32_t POLCTL; /* Offset: 0x24 Touch Key Polarity Control Register */
AnnaBridge 171:3a7713b1edbc 13549 __IO uint32_t STATUS; /* Offset: 0x28 Touch Key Status Register */
AnnaBridge 171:3a7713b1edbc 13550 __I uint32_t DAT0; /* Offset: 0x2C Touch Key Data Register 0 */
AnnaBridge 171:3a7713b1edbc 13551 __I uint32_t DAT1; /* Offset: 0x30 Touch Key Data Register 1 */
AnnaBridge 171:3a7713b1edbc 13552 __I uint32_t DAT2; /* Offset: 0x34 Touch Key Data Register 2 */
AnnaBridge 171:3a7713b1edbc 13553 __I uint32_t DAT3; /* Offset: 0x38 Touch Key Data Register 3 */
AnnaBridge 171:3a7713b1edbc 13554 __I uint32_t DAT4; /* Offset: 0x3C Touch Key Data Register 4 */
AnnaBridge 171:3a7713b1edbc 13555 __IO uint32_t INTEN; /* Offset: 0x40 Touch Key Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 13556 __IO uint32_t TH0_1; /* Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13557 __IO uint32_t TH2_3; /* Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13558 __IO uint32_t TH4_5; /* Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13559 __IO uint32_t TH6_7; /* Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13560 __IO uint32_t TH8_9; /* Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13561 __IO uint32_t TH10_11; /* Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13562 __IO uint32_t TH12_13; /* Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13563 __IO uint32_t TH14_15; /* Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13564 __IO uint32_t TH16; /* Offset: 0x64 Touch Key TK16 Threshold Control Register */
AnnaBridge 171:3a7713b1edbc 13565
AnnaBridge 171:3a7713b1edbc 13566 } TK_T;
AnnaBridge 171:3a7713b1edbc 13567
AnnaBridge 171:3a7713b1edbc 13568
AnnaBridge 171:3a7713b1edbc 13569
AnnaBridge 171:3a7713b1edbc 13570 /**
AnnaBridge 171:3a7713b1edbc 13571 @addtogroup TK_CONST TK Bit Field Definition
AnnaBridge 171:3a7713b1edbc 13572 Constant Definitions for TK Controller
AnnaBridge 171:3a7713b1edbc 13573 @{ */
AnnaBridge 171:3a7713b1edbc 13574
AnnaBridge 171:3a7713b1edbc 13575
AnnaBridge 171:3a7713b1edbc 13576 #define TK_CTL_TKSEN0_Pos (0) /*!< TK_T::CTL: TKSEN0 Position */
AnnaBridge 171:3a7713b1edbc 13577 #define TK_CTL_TKSEN0_Msk (0x1ul << TK_CTL_TKSEN0_Pos) /*!< TK_T::CTL: TKSEN0 Mask */
AnnaBridge 171:3a7713b1edbc 13578
AnnaBridge 171:3a7713b1edbc 13579 #define TK_CTL_TKSEN1_Pos (1) /*!< TK_T::CTL: TKSEN1 Position */
AnnaBridge 171:3a7713b1edbc 13580 #define TK_CTL_TKSEN1_Msk (0x1ul << TK_CTL_TKSEN1_Pos) /*!< TK_T::CTL: TKSEN1 Mask */
AnnaBridge 171:3a7713b1edbc 13581
AnnaBridge 171:3a7713b1edbc 13582 #define TK_CTL_TKSEN2_Pos (2) /*!< TK_T::CTL: TKSEN2 Position */
AnnaBridge 171:3a7713b1edbc 13583 #define TK_CTL_TKSEN2_Msk (0x1ul << TK_CTL_TKSEN2_Pos) /*!< TK_T::CTL: TKSEN2 Mask */
AnnaBridge 171:3a7713b1edbc 13584
AnnaBridge 171:3a7713b1edbc 13585 #define TK_CTL_TKSEN3_Pos (3) /*!< TK_T::CTL: TKSEN3 Position */
AnnaBridge 171:3a7713b1edbc 13586 #define TK_CTL_TKSEN3_Msk (0x1ul << TK_CTL_TKSEN3_Pos) /*!< TK_T::CTL: TKSEN3 Mask */
AnnaBridge 171:3a7713b1edbc 13587
AnnaBridge 171:3a7713b1edbc 13588 #define TK_CTL_TKSEN4_Pos (4) /*!< TK_T::CTL: TKSEN4 Position */
AnnaBridge 171:3a7713b1edbc 13589 #define TK_CTL_TKSEN4_Msk (0x1ul << TK_CTL_TKSEN4_Pos) /*!< TK_T::CTL: TKSEN4 Mask */
AnnaBridge 171:3a7713b1edbc 13590
AnnaBridge 171:3a7713b1edbc 13591 #define TK_CTL_TKSEN5_Pos (5) /*!< TK_T::CTL: TKSEN5 Position */
AnnaBridge 171:3a7713b1edbc 13592 #define TK_CTL_TKSEN5_Msk (0x1ul << TK_CTL_TKSEN5_Pos) /*!< TK_T::CTL: TKSEN5 Mask */
AnnaBridge 171:3a7713b1edbc 13593
AnnaBridge 171:3a7713b1edbc 13594 #define TK_CTL_TKSEN6_Pos (6) /*!< TK_T::CTL: TKSEN6 Position */
AnnaBridge 171:3a7713b1edbc 13595 #define TK_CTL_TKSEN6_Msk (0x1ul << TK_CTL_TKSEN6_Pos) /*!< TK_T::CTL: TKSEN6 Mask */
AnnaBridge 171:3a7713b1edbc 13596
AnnaBridge 171:3a7713b1edbc 13597 #define TK_CTL_TKSEN7_Pos (7) /*!< TK_T::CTL: TKSEN7 Position */
AnnaBridge 171:3a7713b1edbc 13598 #define TK_CTL_TKSEN7_Msk (0x1ul << TK_CTL_TKSEN7_Pos) /*!< TK_T::CTL: TKSEN7 Mask */
AnnaBridge 171:3a7713b1edbc 13599
AnnaBridge 171:3a7713b1edbc 13600 #define TK_CTL_TKSEN8_Pos (8) /*!< TK_T::CTL: TKSEN8 Position */
AnnaBridge 171:3a7713b1edbc 13601 #define TK_CTL_TKSEN8_Msk (0x1ul << TK_CTL_TKSEN8_Pos) /*!< TK_T::CTL: TKSEN8 Mask */
AnnaBridge 171:3a7713b1edbc 13602
AnnaBridge 171:3a7713b1edbc 13603 #define TK_CTL_TKSEN9_Pos (9) /*!< TK_T::CTL: TKSEN9 Position */
AnnaBridge 171:3a7713b1edbc 13604 #define TK_CTL_TKSEN9_Msk (0x1ul << TK_CTL_TKSEN9_Pos) /*!< TK_T::CTL: TKSEN9 Mask */
AnnaBridge 171:3a7713b1edbc 13605
AnnaBridge 171:3a7713b1edbc 13606 #define TK_CTL_TKSEN10_Pos (10) /*!< TK_T::CTL: TKSEN10 Position */
AnnaBridge 171:3a7713b1edbc 13607 #define TK_CTL_TKSEN10_Msk (0x1ul << TK_CTL_TKSEN10_Pos) /*!< TK_T::CTL: TKSEN10 Mask */
AnnaBridge 171:3a7713b1edbc 13608
AnnaBridge 171:3a7713b1edbc 13609 #define TK_CTL_TKSEN11_Pos (11) /*!< TK_T::CTL: TKSEN11 Position */
AnnaBridge 171:3a7713b1edbc 13610 #define TK_CTL_TKSEN11_Msk (0x1ul << TK_CTL_TKSEN11_Pos) /*!< TK_T::CTL: TKSEN11 Mask */
AnnaBridge 171:3a7713b1edbc 13611
AnnaBridge 171:3a7713b1edbc 13612 #define TK_CTL_TKSEN12_Pos (12) /*!< TK_T::CTL: TKSEN12 Position */
AnnaBridge 171:3a7713b1edbc 13613 #define TK_CTL_TKSEN12_Msk (0x1ul << TK_CTL_TKSEN12_Pos) /*!< TK_T::CTL: TKSEN12 Mask */
AnnaBridge 171:3a7713b1edbc 13614
AnnaBridge 171:3a7713b1edbc 13615 #define TK_CTL_TKSEN13_Pos (13) /*!< TK_T::CTL: TKSEN13 Position */
AnnaBridge 171:3a7713b1edbc 13616 #define TK_CTL_TKSEN13_Msk (0x1ul << TK_CTL_TKSEN13_Pos) /*!< TK_T::CTL: TKSEN13 Mask */
AnnaBridge 171:3a7713b1edbc 13617
AnnaBridge 171:3a7713b1edbc 13618 #define TK_CTL_TKSEN14_Pos (14) /*!< TK_T::CTL: TKSEN14 Position */
AnnaBridge 171:3a7713b1edbc 13619 #define TK_CTL_TKSEN14_Msk (0x1ul << TK_CTL_TKSEN14_Pos) /*!< TK_T::CTL: TKSEN14 Mask */
AnnaBridge 171:3a7713b1edbc 13620
AnnaBridge 171:3a7713b1edbc 13621 #define TK_CTL_TKSEN15_Pos (15) /*!< TK_T::CTL: TKSEN15 Position */
AnnaBridge 171:3a7713b1edbc 13622 #define TK_CTL_TKSEN15_Msk (0x1ul << TK_CTL_TKSEN15_Pos) /*!< TK_T::CTL: TKSEN15 Mask */
AnnaBridge 171:3a7713b1edbc 13623
AnnaBridge 171:3a7713b1edbc 13624 #define TK_CTL_TKSEN16_Pos (16) /*!< TK_T::CTL: TKSEN16 Position */
AnnaBridge 171:3a7713b1edbc 13625 #define TK_CTL_TKSEN16_Msk (0x1ul << TK_CTL_TKSEN16_Pos) /*!< TK_T::CTL: TKSEN16 Mask */
AnnaBridge 171:3a7713b1edbc 13626
AnnaBridge 171:3a7713b1edbc 13627 #define TK_CTL_AVCCHSEL_Pos (20) /*!< TK_T::CTL: AVCCHSEL Position */
AnnaBridge 171:3a7713b1edbc 13628 #define TK_CTL_AVCCHSEL_Msk (0x7ul << TK_CTL_AVCCHSEL_Pos) /*!< TK_T::CTL: AVCCHSEL Mask */
AnnaBridge 171:3a7713b1edbc 13629
AnnaBridge 171:3a7713b1edbc 13630 #define TK_CTL_SCAN_Pos (24) /*!< TK_T::CTL: SCAN Position */
AnnaBridge 171:3a7713b1edbc 13631 #define TK_CTL_SCAN_Msk (0x1ul << TK_CTL_SCAN_Pos) /*!< TK_T::CTL: SCAN Mask */
AnnaBridge 171:3a7713b1edbc 13632
AnnaBridge 171:3a7713b1edbc 13633 #define TK_CTL_TMRTRGEN_Pos (25) /*!< TK_T::CTL: TMRTRGEN Position */
AnnaBridge 171:3a7713b1edbc 13634 #define TK_CTL_TMRTRGEN_Msk (0x1ul << TK_CTL_TMRTRGEN_Pos) /*!< TK_T::CTL: TMRTRGEN Mask */
AnnaBridge 171:3a7713b1edbc 13635
AnnaBridge 171:3a7713b1edbc 13636 #define TK_CTL_TKEN_Pos (31) /*!< TK_T::CTL: TKEN Position */
AnnaBridge 171:3a7713b1edbc 13637 #define TK_CTL_TKEN_Msk (0x1ul << TK_CTL_TKEN_Pos) /*!< TK_T::CTL: TKEN Mask */
AnnaBridge 171:3a7713b1edbc 13638
AnnaBridge 171:3a7713b1edbc 13639 #define TK_REFCTL_TKREN0_Pos (0) /*!< TK_T::REFCTL: TKREN0 Position */
AnnaBridge 171:3a7713b1edbc 13640 #define TK_REFCTL_TKREN0_Msk (0x1ul << TK_REFCTL_TKREN0_Pos) /*!< TK_T::REFCTL: TKREN0 Mask */
AnnaBridge 171:3a7713b1edbc 13641
AnnaBridge 171:3a7713b1edbc 13642 #define TK_REFCTL_TKREN1_Pos (1) /*!< TK_T::REFCTL: TKREN1 Position */
AnnaBridge 171:3a7713b1edbc 13643 #define TK_REFCTL_TKREN1_Msk (0x1ul << TK_REFCTL_TKREN1_Pos) /*!< TK_T::REFCTL: TKREN1 Mask */
AnnaBridge 171:3a7713b1edbc 13644
AnnaBridge 171:3a7713b1edbc 13645 #define TK_REFCTL_TKREN2_Pos (2) /*!< TK_T::REFCTL: TKREN2 Position */
AnnaBridge 171:3a7713b1edbc 13646 #define TK_REFCTL_TKREN2_Msk (0x1ul << TK_REFCTL_TKREN2_Pos) /*!< TK_T::REFCTL: TKREN2 Mask */
AnnaBridge 171:3a7713b1edbc 13647
AnnaBridge 171:3a7713b1edbc 13648 #define TK_REFCTL_TKREN3_Pos (3) /*!< TK_T::REFCTL: TKREN3 Position */
AnnaBridge 171:3a7713b1edbc 13649 #define TK_REFCTL_TKREN3_Msk (0x1ul << TK_REFCTL_TKREN3_Pos) /*!< TK_T::REFCTL: TKREN3 Mask */
AnnaBridge 171:3a7713b1edbc 13650
AnnaBridge 171:3a7713b1edbc 13651 #define TK_REFCTL_TKREN4_Pos (4) /*!< TK_T::REFCTL: TKREN4 Position */
AnnaBridge 171:3a7713b1edbc 13652 #define TK_REFCTL_TKREN4_Msk (0x1ul << TK_REFCTL_TKREN4_Pos) /*!< TK_T::REFCTL: TKREN4 Mask */
AnnaBridge 171:3a7713b1edbc 13653
AnnaBridge 171:3a7713b1edbc 13654 #define TK_REFCTL_TKREN5_Pos (5) /*!< TK_T::REFCTL: TKREN5 Position */
AnnaBridge 171:3a7713b1edbc 13655 #define TK_REFCTL_TKREN5_Msk (0x1ul << TK_REFCTL_TKREN5_Pos) /*!< TK_T::REFCTL: TKREN5 Mask */
AnnaBridge 171:3a7713b1edbc 13656
AnnaBridge 171:3a7713b1edbc 13657 #define TK_REFCTL_TKREN6_Pos (6) /*!< TK_T::REFCTL: TKREN6 Position */
AnnaBridge 171:3a7713b1edbc 13658 #define TK_REFCTL_TKREN6_Msk (0x1ul << TK_REFCTL_TKREN6_Pos) /*!< TK_T::REFCTL: TKREN6 Mask */
AnnaBridge 171:3a7713b1edbc 13659
AnnaBridge 171:3a7713b1edbc 13660 #define TK_REFCTL_TKREN7_Pos (7) /*!< TK_T::REFCTL: TKREN7 Position */
AnnaBridge 171:3a7713b1edbc 13661 #define TK_REFCTL_TKREN7_Msk (0x1ul << TK_REFCTL_TKREN7_Pos) /*!< TK_T::REFCTL: TKREN7 Mask */
AnnaBridge 171:3a7713b1edbc 13662
AnnaBridge 171:3a7713b1edbc 13663 #define TK_REFCTL_TKREN8_Pos (8) /*!< TK_T::REFCTL: TKREN8 Position */
AnnaBridge 171:3a7713b1edbc 13664 #define TK_REFCTL_TKREN8_Msk (0x1ul << TK_REFCTL_TKREN8_Pos) /*!< TK_T::REFCTL: TKREN8 Mask */
AnnaBridge 171:3a7713b1edbc 13665
AnnaBridge 171:3a7713b1edbc 13666 #define TK_REFCTL_TKREN9_Pos (9) /*!< TK_T::REFCTL: TKREN9 Position */
AnnaBridge 171:3a7713b1edbc 13667 #define TK_REFCTL_TKREN9_Msk (0x1ul << TK_REFCTL_TKREN9_Pos) /*!< TK_T::REFCTL: TKREN9 Mask */
AnnaBridge 171:3a7713b1edbc 13668
AnnaBridge 171:3a7713b1edbc 13669 #define TK_REFCTL_TKREN10_Pos (10) /*!< TK_T::REFCTL: TKREN10 Position */
AnnaBridge 171:3a7713b1edbc 13670 #define TK_REFCTL_TKREN10_Msk (0x1ul << TK_REFCTL_TKREN10_Pos) /*!< TK_T::REFCTL: TKREN10 Mask */
AnnaBridge 171:3a7713b1edbc 13671
AnnaBridge 171:3a7713b1edbc 13672 #define TK_REFCTL_TKREN11_Pos (11) /*!< TK_T::REFCTL: TKREN11 Position */
AnnaBridge 171:3a7713b1edbc 13673 #define TK_REFCTL_TKREN11_Msk (0x1ul << TK_REFCTL_TKREN11_Pos) /*!< TK_T::REFCTL: TKREN11 Mask */
AnnaBridge 171:3a7713b1edbc 13674
AnnaBridge 171:3a7713b1edbc 13675 #define TK_REFCTL_TKREN12_Pos (12) /*!< TK_T::REFCTL: TKREN12 Position */
AnnaBridge 171:3a7713b1edbc 13676 #define TK_REFCTL_TKREN12_Msk (0x1ul << TK_REFCTL_TKREN12_Pos) /*!< TK_T::REFCTL: TKREN12 Mask */
AnnaBridge 171:3a7713b1edbc 13677
AnnaBridge 171:3a7713b1edbc 13678 #define TK_REFCTL_TKREN13_Pos (13) /*!< TK_T::REFCTL: TKREN13 Position */
AnnaBridge 171:3a7713b1edbc 13679 #define TK_REFCTL_TKREN13_Msk (0x1ul << TK_REFCTL_TKREN13_Pos) /*!< TK_T::REFCTL: TKREN13 Mask */
AnnaBridge 171:3a7713b1edbc 13680
AnnaBridge 171:3a7713b1edbc 13681 #define TK_REFCTL_TKREN14_Pos (14) /*!< TK_T::REFCTL: TKREN14 Position */
AnnaBridge 171:3a7713b1edbc 13682 #define TK_REFCTL_TKREN14_Msk (0x1ul << TK_REFCTL_TKREN14_Pos) /*!< TK_T::REFCTL: TKREN14 Mask */
AnnaBridge 171:3a7713b1edbc 13683
AnnaBridge 171:3a7713b1edbc 13684 #define TK_REFCTL_TKREN15_Pos (15) /*!< TK_T::REFCTL: TKREN15 Position */
AnnaBridge 171:3a7713b1edbc 13685 #define TK_REFCTL_TKREN15_Msk (0x1ul << TK_REFCTL_TKREN15_Pos) /*!< TK_T::REFCTL: TKREN15 Mask */
AnnaBridge 171:3a7713b1edbc 13686
AnnaBridge 171:3a7713b1edbc 13687 #define TK_REFCTL_TKREN16_Pos (16) /*!< TK_T::REFCTL: TKREN16 Position */
AnnaBridge 171:3a7713b1edbc 13688 #define TK_REFCTL_TKREN16_Msk (0x1ul << TK_REFCTL_TKREN16_Pos) /*!< TK_T::REFCTL: TKREN16 Mask */
AnnaBridge 171:3a7713b1edbc 13689
AnnaBridge 171:3a7713b1edbc 13690 #define TK_REFCTL_SCANALL_Pos (23) /*!< TK_T::REFCTL: SCANALL Position */
AnnaBridge 171:3a7713b1edbc 13691 #define TK_REFCTL_SCANALL_Msk (0x1ul << TK_REFCTL_SCANALL_Pos) /*!< TK_T::REFCTL: SCANALL Mask */
AnnaBridge 171:3a7713b1edbc 13692
AnnaBridge 171:3a7713b1edbc 13693 #define TK_REFCTL_SENTCTL_Pos (24) /*!< TK_T::REFCTL: SENTCTL Position */
AnnaBridge 171:3a7713b1edbc 13694 #define TK_REFCTL_SENTCTL_Msk (0x3ul << TK_REFCTL_SENTCTL_Pos) /*!< TK_T::REFCTL: SENTCTL Mask */
AnnaBridge 171:3a7713b1edbc 13695
AnnaBridge 171:3a7713b1edbc 13696 #define TK_REFCTL_SENPTCTL_Pos (28) /*!< TK_T::REFCTL: SENPTCTL Position */
AnnaBridge 171:3a7713b1edbc 13697 #define TK_REFCTL_SENPTCTL_Msk (0x3ul << TK_REFCTL_SENPTCTL_Pos) /*!< TK_T::REFCTL: SENPTCTL Mask */
AnnaBridge 171:3a7713b1edbc 13698
AnnaBridge 171:3a7713b1edbc 13699 #define TK_CCBDAT0_CCBDAT0_Pos (0) /*!< TK_T::CCBDAT0: CCBDAT0 Position */
AnnaBridge 171:3a7713b1edbc 13700 #define TK_CCBDAT0_CCBDAT0_Msk (0xfful << TK_CCBDAT0_CCBDAT0_Pos) /*!< TK_T::CCBDAT0: CCBDAT0 Mask */
AnnaBridge 171:3a7713b1edbc 13701
AnnaBridge 171:3a7713b1edbc 13702 #define TK_CCBDAT0_CCBDAT1_Pos (8) /*!< TK_T::CCBDAT0: CCBDAT1 Position */
AnnaBridge 171:3a7713b1edbc 13703 #define TK_CCBDAT0_CCBDAT1_Msk (0xfful << TK_CCBDAT0_CCBDAT1_Pos) /*!< TK_T::CCBDAT0: CCBDAT1 Mask */
AnnaBridge 171:3a7713b1edbc 13704
AnnaBridge 171:3a7713b1edbc 13705 #define TK_CCBDAT0_CCBDAT2_Pos (16) /*!< TK_T::CCBDAT0: CCBDAT2 Position */
AnnaBridge 171:3a7713b1edbc 13706 #define TK_CCBDAT0_CCBDAT2_Msk (0xfful << TK_CCBDAT0_CCBDAT2_Pos) /*!< TK_T::CCBDAT0: CCBDAT2 Mask */
AnnaBridge 171:3a7713b1edbc 13707
AnnaBridge 171:3a7713b1edbc 13708 #define TK_CCBDAT0_CCBDAT3_Pos (24) /*!< TK_T::CCBDAT0: CCBDAT3 Position */
AnnaBridge 171:3a7713b1edbc 13709 #define TK_CCBDAT0_CCBDAT3_Msk (0xfful << TK_CCBDAT0_CCBDAT3_Pos) /*!< TK_T::CCBDAT0: CCBDAT3 Mask */
AnnaBridge 171:3a7713b1edbc 13710
AnnaBridge 171:3a7713b1edbc 13711 #define TK_CCBDAT1_CCBDAT4_Pos (0) /*!< TK_T::CCBDAT1: CCBDAT4 Position */
AnnaBridge 171:3a7713b1edbc 13712 #define TK_CCBDAT1_CCBDAT4_Msk (0xfful << TK_CCBDAT1_CCBDAT4_Pos) /*!< TK_T::CCBDAT1: CCBDAT4 Mask */
AnnaBridge 171:3a7713b1edbc 13713
AnnaBridge 171:3a7713b1edbc 13714 #define TK_CCBDAT1_CCBDAT5_Pos (8) /*!< TK_T::CCBDAT1: CCBDAT5 Position */
AnnaBridge 171:3a7713b1edbc 13715 #define TK_CCBDAT1_CCBDAT5_Msk (0xfful << TK_CCBDAT1_CCBDAT5_Pos) /*!< TK_T::CCBDAT1: CCBDAT5 Mask */
AnnaBridge 171:3a7713b1edbc 13716
AnnaBridge 171:3a7713b1edbc 13717 #define TK_CCBDAT1_CCBDAT6_Pos (16) /*!< TK_T::CCBDAT1: CCBDAT6 Position */
AnnaBridge 171:3a7713b1edbc 13718 #define TK_CCBDAT1_CCBDAT6_Msk (0xfful << TK_CCBDAT1_CCBDAT6_Pos) /*!< TK_T::CCBDAT1: CCBDAT6 Mask */
AnnaBridge 171:3a7713b1edbc 13719
AnnaBridge 171:3a7713b1edbc 13720 #define TK_CCBDAT1_CCBDAT7_Pos (24) /*!< TK_T::CCBDAT1: CCBDAT7 Position */
AnnaBridge 171:3a7713b1edbc 13721 #define TK_CCBDAT1_CCBDAT7_Msk (0xfful << TK_CCBDAT1_CCBDAT7_Pos) /*!< TK_T::CCBDAT1: CCBDAT7 Mask */
AnnaBridge 171:3a7713b1edbc 13722
AnnaBridge 171:3a7713b1edbc 13723 #define TK_CCBDAT2_CCBDAT8_Pos (0) /*!< TK_T::CCBDAT2: CCBDAT8 Position */
AnnaBridge 171:3a7713b1edbc 13724 #define TK_CCBDAT2_CCBDAT8_Msk (0xfful << TK_CCBDAT2_CCBDAT8_Pos) /*!< TK_T::CCBDAT2: CCBDAT8 Mask */
AnnaBridge 171:3a7713b1edbc 13725
AnnaBridge 171:3a7713b1edbc 13726 #define TK_CCBDAT2_CCBDAT9_Pos (8) /*!< TK_T::CCBDAT2: CCBDAT9 Position */
AnnaBridge 171:3a7713b1edbc 13727 #define TK_CCBDAT2_CCBDAT9_Msk (0xfful << TK_CCBDAT2_CCBDAT9_Pos) /*!< TK_T::CCBDAT2: CCBDAT9 Mask */
AnnaBridge 171:3a7713b1edbc 13728
AnnaBridge 171:3a7713b1edbc 13729 #define TK_CCBDAT2_CCBDAT10_Pos (16) /*!< TK_T::CCBDAT2: CCBDAT10 Position */
AnnaBridge 171:3a7713b1edbc 13730 #define TK_CCBDAT2_CCBDAT10_Msk (0xfful << TK_CCBDAT2_CCBDAT10_Pos) /*!< TK_T::CCBDAT2: CCBDAT10 Mask */
AnnaBridge 171:3a7713b1edbc 13731
AnnaBridge 171:3a7713b1edbc 13732 #define TK_CCBDAT2_CCBDAT11_Pos (24) /*!< TK_T::CCBDAT2: CCBDAT11 Position */
AnnaBridge 171:3a7713b1edbc 13733 #define TK_CCBDAT2_CCBDAT11_Msk (0xfful << TK_CCBDAT2_CCBDAT11_Pos) /*!< TK_T::CCBDAT2: CCBDAT11 Mask */
AnnaBridge 171:3a7713b1edbc 13734
AnnaBridge 171:3a7713b1edbc 13735 #define TK_CCBDAT3_CCBDAT12_Pos (0) /*!< TK_T::CCBDAT3: CCBDAT12 Position */
AnnaBridge 171:3a7713b1edbc 13736 #define TK_CCBDAT3_CCBDAT12_Msk (0xfful << TK_CCBDAT3_CCBDAT12_Pos) /*!< TK_T::CCBDAT3: CCBDAT12 Mask */
AnnaBridge 171:3a7713b1edbc 13737
AnnaBridge 171:3a7713b1edbc 13738 #define TK_CCBDAT3_CCBDAT13_Pos (8) /*!< TK_T::CCBDAT3: CCBDAT13 Position */
AnnaBridge 171:3a7713b1edbc 13739 #define TK_CCBDAT3_CCBDAT13_Msk (0xfful << TK_CCBDAT3_CCBDAT13_Pos) /*!< TK_T::CCBDAT3: CCBDAT13 Mask */
AnnaBridge 171:3a7713b1edbc 13740
AnnaBridge 171:3a7713b1edbc 13741 #define TK_CCBDAT3_CCBDAT14_Pos (16) /*!< TK_T::CCBDAT3: CCBDAT14 Position */
AnnaBridge 171:3a7713b1edbc 13742 #define TK_CCBDAT3_CCBDAT14_Msk (0xfful << TK_CCBDAT3_CCBDAT14_Pos) /*!< TK_T::CCBDAT3: CCBDAT14 Mask */
AnnaBridge 171:3a7713b1edbc 13743
AnnaBridge 171:3a7713b1edbc 13744 #define TK_CCBDAT3_CCBDAT15_Pos (24) /*!< TK_T::CCBDAT3: CCBDAT15 Position */
AnnaBridge 171:3a7713b1edbc 13745 #define TK_CCBDAT3_CCBDAT15_Msk (0xfful << TK_CCBDAT3_CCBDAT15_Pos) /*!< TK_T::CCBDAT3: CCBDAT15 Mask */
AnnaBridge 171:3a7713b1edbc 13746
AnnaBridge 171:3a7713b1edbc 13747 #define TK_CCBDAT4_CCBDAT16_Pos (0) /*!< TK_T::CCBDAT4: CCBDAT16 Position */
AnnaBridge 171:3a7713b1edbc 13748 #define TK_CCBDAT4_CCBDAT16_Msk (0xfful << TK_CCBDAT4_CCBDAT16_Pos) /*!< TK_T::CCBDAT4: CCBDAT16 Mask */
AnnaBridge 171:3a7713b1edbc 13749
AnnaBridge 171:3a7713b1edbc 13750 #define TK_CCBDAT4_REFCBDAT_Pos (24) /*!< TK_T::CCBDAT4: REFCBDAT Position */
AnnaBridge 171:3a7713b1edbc 13751 #define TK_CCBDAT4_REFCBDAT_Msk (0xfful << TK_CCBDAT4_REFCBDAT_Pos) /*!< TK_T::CCBDAT4: REFCBDAT Mask */
AnnaBridge 171:3a7713b1edbc 13752
AnnaBridge 171:3a7713b1edbc 13753 #define TK_IDLESEL_IDLS_Pos (0) /*!< TK_T::IDLESEL: IDLS Position */
AnnaBridge 171:3a7713b1edbc 13754 #define TK_IDLESEL_IDLS_Msk (0xfffffffful << TK_IDLESEL_IDLS_Pos) /*!< TK_T::IDLESEL: IDLS Mask */
AnnaBridge 171:3a7713b1edbc 13755
AnnaBridge 171:3a7713b1edbc 13756 #define TK_IDLESEL_IDLSn_Pos (0) /*!< TK_T::IDLESEL: IDLSn Position */
AnnaBridge 171:3a7713b1edbc 13757 #define TK_IDLESEL_IDLSn_Msk (0x3ul << TK_IDLESEL_IDLSn_Pos) /*!< TK_T::IDLESEL: IDLSn Mask */
AnnaBridge 171:3a7713b1edbc 13758
AnnaBridge 171:3a7713b1edbc 13759 #define TK_POLSEL_POLSEL_Pos (0) /*!< TK_T::POLSEL: POLSEL Position */
AnnaBridge 171:3a7713b1edbc 13760 #define TK_POLSEL_POLSEL_Msk (0xfffffffful << TK_POLSEL_POLSEL_Pos) /*!< TK_T::POLSEL: POLSEL Mask */
AnnaBridge 171:3a7713b1edbc 13761
AnnaBridge 171:3a7713b1edbc 13762 #define TK_POLSEL_POLSELn_Pos (0) /*!< TK_T::POLSEL: POLSELn Position */
AnnaBridge 171:3a7713b1edbc 13763 #define TK_POLSEL_POLSELn_Msk (0x3ul << TK_POLSEL_POLSELn_Pos) /*!< TK_T::POLSEL: POLSELn Mask */
AnnaBridge 171:3a7713b1edbc 13764
AnnaBridge 171:3a7713b1edbc 13765 #define TK_POLCTL_IDLS16_Pos (0) /*!< TK_T::POLCTL: IDLS16 Position */
AnnaBridge 171:3a7713b1edbc 13766 #define TK_POLCTL_IDLS16_Msk (0x3ul << TK_POLCTL_IDLS16_Pos) /*!< TK_T::POLCTL: IDLS16 Mask */
AnnaBridge 171:3a7713b1edbc 13767
AnnaBridge 171:3a7713b1edbc 13768 #define TK_POLCTL_POLSEL16_Pos (2) /*!< TK_T::POLCTL: POLSEL16 Position */
AnnaBridge 171:3a7713b1edbc 13769 #define TK_POLCTL_POLSEL16_Msk (0x3ul << TK_POLCTL_POLSEL16_Pos) /*!< TK_T::POLCTL: POLSEL16 Mask */
AnnaBridge 171:3a7713b1edbc 13770
AnnaBridge 171:3a7713b1edbc 13771 #define TK_POLCTL_CBPOLSEL_Pos (4) /*!< TK_T::POLCTL: CBPOLSEL Position */
AnnaBridge 171:3a7713b1edbc 13772 #define TK_POLCTL_CBPOLSEL_Msk (0x3ul << TK_POLCTL_CBPOLSEL_Pos) /*!< TK_T::POLCTL: CBPOLSEL Mask */
AnnaBridge 171:3a7713b1edbc 13773
AnnaBridge 171:3a7713b1edbc 13774 #define TK_POLCTL_POLEN0_Pos (8) /*!< TK_T::POLCTL: POLEN0 Position */
AnnaBridge 171:3a7713b1edbc 13775 #define TK_POLCTL_POLEN0_Msk (0x1ul << TK_POLCTL_POLEN0_Pos) /*!< TK_T::POLCTL: POLEN0 Mask */
AnnaBridge 171:3a7713b1edbc 13776
AnnaBridge 171:3a7713b1edbc 13777 #define TK_POLCTL_POLEN1_Pos (9) /*!< TK_T::POLCTL: POLEN1 Position */
AnnaBridge 171:3a7713b1edbc 13778 #define TK_POLCTL_POLEN1_Msk (0x1ul << TK_POLCTL_POLEN1_Pos) /*!< TK_T::POLCTL: POLEN1 Mask */
AnnaBridge 171:3a7713b1edbc 13779
AnnaBridge 171:3a7713b1edbc 13780 #define TK_POLCTL_POLEN2_Pos (10) /*!< TK_T::POLCTL: POLEN2 Position */
AnnaBridge 171:3a7713b1edbc 13781 #define TK_POLCTL_POLEN2_Msk (0x1ul << TK_POLCTL_POLEN2_Pos) /*!< TK_T::POLCTL: POLEN2 Mask */
AnnaBridge 171:3a7713b1edbc 13782
AnnaBridge 171:3a7713b1edbc 13783 #define TK_POLCTL_POLEN3_Pos (11) /*!< TK_T::POLCTL: POLEN3 Position */
AnnaBridge 171:3a7713b1edbc 13784 #define TK_POLCTL_POLEN3_Msk (0x1ul << TK_POLCTL_POLEN3_Pos) /*!< TK_T::POLCTL: POLEN3 Mask */
AnnaBridge 171:3a7713b1edbc 13785
AnnaBridge 171:3a7713b1edbc 13786 #define TK_POLCTL_POLEN4_Pos (12) /*!< TK_T::POLCTL: POLEN4 Position */
AnnaBridge 171:3a7713b1edbc 13787 #define TK_POLCTL_POLEN4_Msk (0x1ul << TK_POLCTL_POLEN4_Pos) /*!< TK_T::POLCTL: POLEN4 Mask */
AnnaBridge 171:3a7713b1edbc 13788
AnnaBridge 171:3a7713b1edbc 13789 #define TK_POLCTL_POLEN5_Pos (13) /*!< TK_T::POLCTL: POLEN5 Position */
AnnaBridge 171:3a7713b1edbc 13790 #define TK_POLCTL_POLEN5_Msk (0x1ul << TK_POLCTL_POLEN5_Pos) /*!< TK_T::POLCTL: POLEN5 Mask */
AnnaBridge 171:3a7713b1edbc 13791
AnnaBridge 171:3a7713b1edbc 13792 #define TK_POLCTL_POLEN6_Pos (14) /*!< TK_T::POLCTL: POLEN6 Position */
AnnaBridge 171:3a7713b1edbc 13793 #define TK_POLCTL_POLEN6_Msk (0x1ul << TK_POLCTL_POLEN6_Pos) /*!< TK_T::POLCTL: POLEN6 Mask */
AnnaBridge 171:3a7713b1edbc 13794
AnnaBridge 171:3a7713b1edbc 13795 #define TK_POLCTL_POLEN7_Pos (15) /*!< TK_T::POLCTL: POLEN7 Position */
AnnaBridge 171:3a7713b1edbc 13796 #define TK_POLCTL_POLEN7_Msk (0x1ul << TK_POLCTL_POLEN7_Pos) /*!< TK_T::POLCTL: POLEN7 Mask */
AnnaBridge 171:3a7713b1edbc 13797
AnnaBridge 171:3a7713b1edbc 13798 #define TK_POLCTL_POLEN8_Pos (16) /*!< TK_T::POLCTL: POLEN8 Position */
AnnaBridge 171:3a7713b1edbc 13799 #define TK_POLCTL_POLEN8_Msk (0x1ul << TK_POLCTL_POLEN8_Pos) /*!< TK_T::POLCTL: POLEN8 Mask */
AnnaBridge 171:3a7713b1edbc 13800
AnnaBridge 171:3a7713b1edbc 13801 #define TK_POLCTL_POLEN9_Pos (17) /*!< TK_T::POLCTL: POLEN9 Position */
AnnaBridge 171:3a7713b1edbc 13802 #define TK_POLCTL_POLEN9_Msk (0x1ul << TK_POLCTL_POLEN9_Pos) /*!< TK_T::POLCTL: POLEN9 Mask */
AnnaBridge 171:3a7713b1edbc 13803
AnnaBridge 171:3a7713b1edbc 13804 #define TK_POLCTL_POLEN10_Pos (18) /*!< TK_T::POLCTL: POLEN10 Position */
AnnaBridge 171:3a7713b1edbc 13805 #define TK_POLCTL_POLEN10_Msk (0x1ul << TK_POLCTL_POLEN10_Pos) /*!< TK_T::POLCTL: POLEN10 Mask */
AnnaBridge 171:3a7713b1edbc 13806
AnnaBridge 171:3a7713b1edbc 13807 #define TK_POLCTL_POLEN11_Pos (19) /*!< TK_T::POLCTL: POLEN11 Position */
AnnaBridge 171:3a7713b1edbc 13808 #define TK_POLCTL_POLEN11_Msk (0x1ul << TK_POLCTL_POLEN11_Pos) /*!< TK_T::POLCTL: POLEN11 Mask */
AnnaBridge 171:3a7713b1edbc 13809
AnnaBridge 171:3a7713b1edbc 13810 #define TK_POLCTL_POLEN12_Pos (20) /*!< TK_T::POLCTL: POLEN12 Position */
AnnaBridge 171:3a7713b1edbc 13811 #define TK_POLCTL_POLEN12_Msk (0x1ul << TK_POLCTL_POLEN12_Pos) /*!< TK_T::POLCTL: POLEN12 Mask */
AnnaBridge 171:3a7713b1edbc 13812
AnnaBridge 171:3a7713b1edbc 13813 #define TK_POLCTL_POLEN13_Pos (21) /*!< TK_T::POLCTL: POLEN13 Position */
AnnaBridge 171:3a7713b1edbc 13814 #define TK_POLCTL_POLEN13_Msk (0x1ul << TK_POLCTL_POLEN13_Pos) /*!< TK_T::POLCTL: POLEN13 Mask */
AnnaBridge 171:3a7713b1edbc 13815
AnnaBridge 171:3a7713b1edbc 13816 #define TK_POLCTL_POLEN14_Pos (22) /*!< TK_T::POLCTL: POLEN14 Position */
AnnaBridge 171:3a7713b1edbc 13817 #define TK_POLCTL_POLEN14_Msk (0x1ul << TK_POLCTL_POLEN14_Pos) /*!< TK_T::POLCTL: POLEN14 Mask */
AnnaBridge 171:3a7713b1edbc 13818
AnnaBridge 171:3a7713b1edbc 13819 #define TK_POLCTL_POLEN15_Pos (23) /*!< TK_T::POLCTL: POLEN15 Position */
AnnaBridge 171:3a7713b1edbc 13820 #define TK_POLCTL_POLEN15_Msk (0x1ul << TK_POLCTL_POLEN15_Pos) /*!< TK_T::POLCTL: POLEN15 Mask */
AnnaBridge 171:3a7713b1edbc 13821
AnnaBridge 171:3a7713b1edbc 13822 #define TK_POLCTL_POLEN16_Pos (24) /*!< TK_T::POLCTL: POLEN16 Position */
AnnaBridge 171:3a7713b1edbc 13823 #define TK_POLCTL_POLEN16_Msk (0x1ul << TK_POLCTL_POLEN16_Pos) /*!< TK_T::POLCTL: POLEN16 Mask */
AnnaBridge 171:3a7713b1edbc 13824
AnnaBridge 171:3a7713b1edbc 13825 #define TK_POLCTL_SPOTINIT_Pos (31) /*!< TK_T::POLCTL: SPOTINIT Position */
AnnaBridge 171:3a7713b1edbc 13826 #define TK_POLCTL_SPOTINIT_Msk (0x1ul << TK_POLCTL_SPOTINIT_Pos) /*!< TK_T::POLCTL: SPOTINIT Mask */
AnnaBridge 171:3a7713b1edbc 13827
AnnaBridge 171:3a7713b1edbc 13828 #define TK_STATUS_BUSY_Pos (0) /*!< TK_T::STATUS: BUSY Position */
AnnaBridge 171:3a7713b1edbc 13829 #define TK_STATUS_BUSY_Msk (0x1ul << TK_STATUS_BUSY_Pos) /*!< TK_T::STATUS: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 13830
AnnaBridge 171:3a7713b1edbc 13831 #define TK_STATUS_SCIF_Pos (1) /*!< TK_T::STATUS: SCIF Position */
AnnaBridge 171:3a7713b1edbc 13832 #define TK_STATUS_SCIF_Msk (0x1ul << TK_STATUS_SCIF_Pos) /*!< TK_T::STATUS: SCIF Mask */
AnnaBridge 171:3a7713b1edbc 13833
AnnaBridge 171:3a7713b1edbc 13834 #define TK_STATUS_TKIF0_Pos (8) /*!< TK_T::STATUS: TKIF0 Position */
AnnaBridge 171:3a7713b1edbc 13835 #define TK_STATUS_TKIF0_Msk (0x1ul << TK_STATUS_TKIF0_Pos) /*!< TK_T::STATUS: TKIF0 Mask */
AnnaBridge 171:3a7713b1edbc 13836
AnnaBridge 171:3a7713b1edbc 13837 #define TK_STATUS_TKIF1_Pos (9) /*!< TK_T::STATUS: TKIF1 Position */
AnnaBridge 171:3a7713b1edbc 13838 #define TK_STATUS_TKIF1_Msk (0x1ul << TK_STATUS_TKIF1_Pos) /*!< TK_T::STATUS: TKIF1 Mask */
AnnaBridge 171:3a7713b1edbc 13839
AnnaBridge 171:3a7713b1edbc 13840 #define TK_STATUS_TKIF2_Pos (10) /*!< TK_T::STATUS: TKIF2 Position */
AnnaBridge 171:3a7713b1edbc 13841 #define TK_STATUS_TKIF2_Msk (0x1ul << TK_STATUS_TKIF2_Pos) /*!< TK_T::STATUS: TKIF2 Mask */
AnnaBridge 171:3a7713b1edbc 13842
AnnaBridge 171:3a7713b1edbc 13843 #define TK_STATUS_TKIF3_Pos (11) /*!< TK_T::STATUS: TKIF3 Position */
AnnaBridge 171:3a7713b1edbc 13844 #define TK_STATUS_TKIF3_Msk (0x1ul << TK_STATUS_TKIF3_Pos) /*!< TK_T::STATUS: TKIF3 Mask */
AnnaBridge 171:3a7713b1edbc 13845
AnnaBridge 171:3a7713b1edbc 13846 #define TK_STATUS_TKIF4_Pos (12) /*!< TK_T::STATUS: TKIF4 Position */
AnnaBridge 171:3a7713b1edbc 13847 #define TK_STATUS_TKIF4_Msk (0x1ul << TK_STATUS_TKIF4_Pos) /*!< TK_T::STATUS: TKIF4 Mask */
AnnaBridge 171:3a7713b1edbc 13848
AnnaBridge 171:3a7713b1edbc 13849 #define TK_STATUS_TKIF5_Pos (13) /*!< TK_T::STATUS: TKIF5 Position */
AnnaBridge 171:3a7713b1edbc 13850 #define TK_STATUS_TKIF5_Msk (0x1ul << TK_STATUS_TKIF5_Pos) /*!< TK_T::STATUS: TKIF5 Mask */
AnnaBridge 171:3a7713b1edbc 13851
AnnaBridge 171:3a7713b1edbc 13852 #define TK_STATUS_TKIF6_Pos (14) /*!< TK_T::STATUS: TKIF6 Position */
AnnaBridge 171:3a7713b1edbc 13853 #define TK_STATUS_TKIF6_Msk (0x1ul << TK_STATUS_TKIF6_Pos) /*!< TK_T::STATUS: TKIF6 Mask */
AnnaBridge 171:3a7713b1edbc 13854
AnnaBridge 171:3a7713b1edbc 13855 #define TK_STATUS_TKIF7_Pos (15) /*!< TK_T::STATUS: TKIF7 Position */
AnnaBridge 171:3a7713b1edbc 13856 #define TK_STATUS_TKIF7_Msk (0x1ul << TK_STATUS_TKIF7_Pos) /*!< TK_T::STATUS: TKIF7 Mask */
AnnaBridge 171:3a7713b1edbc 13857
AnnaBridge 171:3a7713b1edbc 13858 #define TK_STATUS_TKIF8_Pos (16) /*!< TK_T::STATUS: TKIF8 Position */
AnnaBridge 171:3a7713b1edbc 13859 #define TK_STATUS_TKIF8_Msk (0x1ul << TK_STATUS_TKIF8_Pos) /*!< TK_T::STATUS: TKIF8 Mask */
AnnaBridge 171:3a7713b1edbc 13860
AnnaBridge 171:3a7713b1edbc 13861 #define TK_STATUS_TKIF9_Pos (17) /*!< TK_T::STATUS: TKIF9 Position */
AnnaBridge 171:3a7713b1edbc 13862 #define TK_STATUS_TKIF9_Msk (0x1ul << TK_STATUS_TKIF9_Pos) /*!< TK_T::STATUS: TKIF9 Mask */
AnnaBridge 171:3a7713b1edbc 13863
AnnaBridge 171:3a7713b1edbc 13864 #define TK_STATUS_TKIF10_Pos (18) /*!< TK_T::STATUS: TKIF10 Position */
AnnaBridge 171:3a7713b1edbc 13865 #define TK_STATUS_TKIF10_Msk (0x1ul << TK_STATUS_TKIF10_Pos) /*!< TK_T::STATUS: TKIF10 Mask */
AnnaBridge 171:3a7713b1edbc 13866
AnnaBridge 171:3a7713b1edbc 13867 #define TK_STATUS_TKIF11_Pos (19) /*!< TK_T::STATUS: TKIF11 Position */
AnnaBridge 171:3a7713b1edbc 13868 #define TK_STATUS_TKIF11_Msk (0x1ul << TK_STATUS_TKIF11_Pos) /*!< TK_T::STATUS: TKIF11 Mask */
AnnaBridge 171:3a7713b1edbc 13869
AnnaBridge 171:3a7713b1edbc 13870 #define TK_STATUS_TKIF12_Pos (20) /*!< TK_T::STATUS: TKIF12 Position */
AnnaBridge 171:3a7713b1edbc 13871 #define TK_STATUS_TKIF12_Msk (0x1ul << TK_STATUS_TKIF12_Pos) /*!< TK_T::STATUS: TKIF12 Mask */
AnnaBridge 171:3a7713b1edbc 13872
AnnaBridge 171:3a7713b1edbc 13873 #define TK_STATUS_TKIF13_Pos (21) /*!< TK_T::STATUS: TKIF13 Position */
AnnaBridge 171:3a7713b1edbc 13874 #define TK_STATUS_TKIF13_Msk (0x1ul << TK_STATUS_TKIF13_Pos) /*!< TK_T::STATUS: TKIF13 Mask */
AnnaBridge 171:3a7713b1edbc 13875
AnnaBridge 171:3a7713b1edbc 13876 #define TK_STATUS_TKIF14_Pos (22) /*!< TK_T::STATUS: TKIF14 Position */
AnnaBridge 171:3a7713b1edbc 13877 #define TK_STATUS_TKIF14_Msk (0x1ul << TK_STATUS_TKIF14_Pos) /*!< TK_T::STATUS: TKIF14 Mask */
AnnaBridge 171:3a7713b1edbc 13878
AnnaBridge 171:3a7713b1edbc 13879 #define TK_STATUS_TKIF15_Pos (23) /*!< TK_T::STATUS: TKIF15 Position */
AnnaBridge 171:3a7713b1edbc 13880 #define TK_STATUS_TKIF15_Msk (0x1ul << TK_STATUS_TKIF15_Pos) /*!< TK_T::STATUS: TKIF15 Mask */
AnnaBridge 171:3a7713b1edbc 13881
AnnaBridge 171:3a7713b1edbc 13882 #define TK_STATUS_TKIF16_Pos (24) /*!< TK_T::STATUS: TKIF16 Position */
AnnaBridge 171:3a7713b1edbc 13883 #define TK_STATUS_TKIF16_Msk (0x1ul << TK_STATUS_TKIF16_Pos) /*!< TK_T::STATUS: TKIF16 Mask */
AnnaBridge 171:3a7713b1edbc 13884
AnnaBridge 171:3a7713b1edbc 13885 #define TK_DAT0_TKDAT0_Pos (0) /*!< TK_T::DAT0: TKDAT0 Position */
AnnaBridge 171:3a7713b1edbc 13886 #define TK_DAT0_TKDAT0_Msk (0xfful << TK_DAT0_TKDAT0_Pos) /*!< TK_T::DAT0: TKDAT0 Mask */
AnnaBridge 171:3a7713b1edbc 13887
AnnaBridge 171:3a7713b1edbc 13888 #define TK_DAT0_TKDAT1_Pos (8) /*!< TK_T::DAT0: TKDAT1 Position */
AnnaBridge 171:3a7713b1edbc 13889 #define TK_DAT0_TKDAT1_Msk (0xfful << TK_DAT0_TKDAT1_Pos) /*!< TK_T::DAT0: TKDAT1 Mask */
AnnaBridge 171:3a7713b1edbc 13890
AnnaBridge 171:3a7713b1edbc 13891 #define TK_DAT0_TKDAT2_Pos (16) /*!< TK_T::DAT0: TKDAT2 Position */
AnnaBridge 171:3a7713b1edbc 13892 #define TK_DAT0_TKDAT2_Msk (0xfful << TK_DAT0_TKDAT2_Pos) /*!< TK_T::DAT0: TKDAT2 Mask */
AnnaBridge 171:3a7713b1edbc 13893
AnnaBridge 171:3a7713b1edbc 13894 #define TK_DAT0_TKDAT3_Pos (24) /*!< TK_T::DAT0: TKDAT3 Position */
AnnaBridge 171:3a7713b1edbc 13895 #define TK_DAT0_TKDAT3_Msk (0xfful << TK_DAT0_TKDAT3_Pos) /*!< TK_T::DAT0: TKDAT3 Mask */
AnnaBridge 171:3a7713b1edbc 13896
AnnaBridge 171:3a7713b1edbc 13897 #define TK_DAT1_TKDAT4_Pos (0) /*!< TK_T::DAT1: TKDAT4 Position */
AnnaBridge 171:3a7713b1edbc 13898 #define TK_DAT1_TKDAT4_Msk (0xfful << TK_DAT1_TKDAT4_Pos) /*!< TK_T::DAT1: TKDAT4 Mask */
AnnaBridge 171:3a7713b1edbc 13899
AnnaBridge 171:3a7713b1edbc 13900 #define TK_DAT1_TKDAT5_Pos (8) /*!< TK_T::DAT1: TKDAT5 Position */
AnnaBridge 171:3a7713b1edbc 13901 #define TK_DAT1_TKDAT5_Msk (0xfful << TK_DAT1_TKDAT5_Pos) /*!< TK_T::DAT1: TKDAT5 Mask */
AnnaBridge 171:3a7713b1edbc 13902
AnnaBridge 171:3a7713b1edbc 13903 #define TK_DAT1_TKDAT6_Pos (16) /*!< TK_T::DAT1: TKDAT6 Position */
AnnaBridge 171:3a7713b1edbc 13904 #define TK_DAT1_TKDAT6_Msk (0xfful << TK_DAT1_TKDAT6_Pos) /*!< TK_T::DAT1: TKDAT6 Mask */
AnnaBridge 171:3a7713b1edbc 13905
AnnaBridge 171:3a7713b1edbc 13906 #define TK_DAT1_TKDAT7_Pos (24) /*!< TK_T::DAT1: TKDAT7 Position */
AnnaBridge 171:3a7713b1edbc 13907 #define TK_DAT1_TKDAT7_Msk (0xfful << TK_DAT1_TKDAT7_Pos) /*!< TK_T::DAT1: TKDAT7 Mask */
AnnaBridge 171:3a7713b1edbc 13908
AnnaBridge 171:3a7713b1edbc 13909 #define TK_DAT2_TKDAT8_Pos (0) /*!< TK_T::DAT2: TKDAT8 Position */
AnnaBridge 171:3a7713b1edbc 13910 #define TK_DAT2_TKDAT8_Msk (0xfful << TK_DAT2_TKDAT8_Pos) /*!< TK_T::DAT2: TKDAT8 Mask */
AnnaBridge 171:3a7713b1edbc 13911
AnnaBridge 171:3a7713b1edbc 13912 #define TK_DAT2_TKDAT9_Pos (8) /*!< TK_T::DAT2: TKDAT9 Position */
AnnaBridge 171:3a7713b1edbc 13913 #define TK_DAT2_TKDAT9_Msk (0xfful << TK_DAT2_TKDAT9_Pos) /*!< TK_T::DAT2: TKDAT9 Mask */
AnnaBridge 171:3a7713b1edbc 13914
AnnaBridge 171:3a7713b1edbc 13915 #define TK_DAT2_TKDAT10_Pos (16) /*!< TK_T::DAT2: TKDAT10 Position */
AnnaBridge 171:3a7713b1edbc 13916 #define TK_DAT2_TKDAT10_Msk (0xfful << TK_DAT2_TKDAT10_Pos) /*!< TK_T::DAT2: TKDAT10 Mask */
AnnaBridge 171:3a7713b1edbc 13917
AnnaBridge 171:3a7713b1edbc 13918 #define TK_DAT2_TKDAT11_Pos (24) /*!< TK_T::DAT2: TKDAT11 Position */
AnnaBridge 171:3a7713b1edbc 13919 #define TK_DAT2_TKDAT11_Msk (0xfful << TK_DAT2_TKDAT11_Pos) /*!< TK_T::DAT2: TKDAT11 Mask */
AnnaBridge 171:3a7713b1edbc 13920
AnnaBridge 171:3a7713b1edbc 13921 #define TK_DAT3_TKDAT12_Pos (0) /*!< TK_T::DAT3: TKDAT12 Position */
AnnaBridge 171:3a7713b1edbc 13922 #define TK_DAT3_TKDAT12_Msk (0xfful << TK_DAT3_TKDAT12_Pos) /*!< TK_T::DAT3: TKDAT12 Mask */
AnnaBridge 171:3a7713b1edbc 13923
AnnaBridge 171:3a7713b1edbc 13924 #define TK_DAT3_TKDAT13_Pos (8) /*!< TK_T::DAT3: TKDAT13 Position */
AnnaBridge 171:3a7713b1edbc 13925 #define TK_DAT3_TKDAT13_Msk (0xfful << TK_DAT3_TKDAT13_Pos) /*!< TK_T::DAT3: TKDAT13 Mask */
AnnaBridge 171:3a7713b1edbc 13926
AnnaBridge 171:3a7713b1edbc 13927 #define TK_DAT3_TKDAT14_Pos (16) /*!< TK_T::DAT3: TKDAT14 Position */
AnnaBridge 171:3a7713b1edbc 13928 #define TK_DAT3_TKDAT14_Msk (0xfful << TK_DAT3_TKDAT14_Pos) /*!< TK_T::DAT3: TKDAT14 Mask */
AnnaBridge 171:3a7713b1edbc 13929
AnnaBridge 171:3a7713b1edbc 13930 #define TK_DAT3_TKDAT15_Pos (24) /*!< TK_T::DAT3: TKDAT15 Position */
AnnaBridge 171:3a7713b1edbc 13931 #define TK_DAT3_TKDAT15_Msk (0xfful << TK_DAT3_TKDAT15_Pos) /*!< TK_T::DAT3: TKDAT15 Mask */
AnnaBridge 171:3a7713b1edbc 13932
AnnaBridge 171:3a7713b1edbc 13933 #define TK_DAT4_TKDAT16_Pos (0) /*!< TK_T::DAT4: TKDAT16 Position */
AnnaBridge 171:3a7713b1edbc 13934 #define TK_DAT4_TKDAT16_Msk (0xfful << TK_DAT4_TKDAT16_Pos) /*!< TK_T::DAT4: TKDAT16 Mask */
AnnaBridge 171:3a7713b1edbc 13935
AnnaBridge 171:3a7713b1edbc 13936 #define TK_INTEN_SCTHIEN_Pos (0) /*!< TK_T::INTEN: SCTHIEN Position */
AnnaBridge 171:3a7713b1edbc 13937 #define TK_INTEN_SCTHIEN_Msk (0x1ul << TK_INTEN_SCTHIEN_Pos) /*!< TK_T::INTEN: SCTHIEN Mask */
AnnaBridge 171:3a7713b1edbc 13938
AnnaBridge 171:3a7713b1edbc 13939 #define TK_INTEN_SCINTEN_Pos (1) /*!< TK_T::INTEN: SCINTEN Position */
AnnaBridge 171:3a7713b1edbc 13940 #define TK_INTEN_SCINTEN_Msk (0x1ul << TK_INTEN_SCINTEN_Pos) /*!< TK_T::INTEN: SCINTEN Mask */
AnnaBridge 171:3a7713b1edbc 13941
AnnaBridge 171:3a7713b1edbc 13942 #define TK_INTEN_THIMOD_Pos (31) /*!< TK_T::INTEN: THIMOD Position */
AnnaBridge 171:3a7713b1edbc 13943 #define TK_INTEN_THIMOD_Msk (0x1ul << TK_INTEN_THIMOD_Pos) /*!< TK_T::INTEN: THIMOD Mask */
AnnaBridge 171:3a7713b1edbc 13944
AnnaBridge 171:3a7713b1edbc 13945 #define TK_TH0_1_LTH0_Pos (0) /*!< TK_T::TH0_1: LTH0 Position */
AnnaBridge 171:3a7713b1edbc 13946 #define TK_TH0_1_LTH0_Msk (0xfful << TK_TH0_1_LTH0_Pos) /*!< TK_T::TH0_1: LTH0 Mask */
AnnaBridge 171:3a7713b1edbc 13947
AnnaBridge 171:3a7713b1edbc 13948 #define TK_TH0_1_HTH0_Pos (8) /*!< TK_T::TH0_1: HTH0 Position */
AnnaBridge 171:3a7713b1edbc 13949 #define TK_TH0_1_HTH0_Msk (0xfful << TK_TH0_1_HTH0_Pos) /*!< TK_T::TH0_1: HTH0 Mask */
AnnaBridge 171:3a7713b1edbc 13950
AnnaBridge 171:3a7713b1edbc 13951 #define TK_TH0_1_LTH1_Pos (16) /*!< TK_T::TH0_1: LTH1 Position */
AnnaBridge 171:3a7713b1edbc 13952 #define TK_TH0_1_LTH1_Msk (0xfful << TK_TH0_1_LTH1_Pos) /*!< TK_T::TH0_1: LTH1 Mask */
AnnaBridge 171:3a7713b1edbc 13953
AnnaBridge 171:3a7713b1edbc 13954 #define TK_TH0_1_HTH1_Pos (24) /*!< TK_T::TH0_1: HTH1 Position */
AnnaBridge 171:3a7713b1edbc 13955 #define TK_TH0_1_HTH1_Msk (0xfful << TK_TH0_1_HTH1_Pos) /*!< TK_T::TH0_1: HTH1 Mask */
AnnaBridge 171:3a7713b1edbc 13956
AnnaBridge 171:3a7713b1edbc 13957 #define TK_TH2_3_LTH2_Pos (0) /*!< TK_T::TH2_3: LTH2 Position */
AnnaBridge 171:3a7713b1edbc 13958 #define TK_TH2_3_LTH2_Msk (0xfful << TK_TH2_3_LTH2_Pos) /*!< TK_T::TH2_3: LTH2 Mask */
AnnaBridge 171:3a7713b1edbc 13959
AnnaBridge 171:3a7713b1edbc 13960 #define TK_TH2_3_HTH2_Pos (8) /*!< TK_T::TH2_3: HTH2 Position */
AnnaBridge 171:3a7713b1edbc 13961 #define TK_TH2_3_HTH2_Msk (0xfful << TK_TH2_3_HTH2_Pos) /*!< TK_T::TH2_3: HTH2 Mask */
AnnaBridge 171:3a7713b1edbc 13962
AnnaBridge 171:3a7713b1edbc 13963 #define TK_TH2_3_LTH3_Pos (16) /*!< TK_T::TH2_3: LTH3 Position */
AnnaBridge 171:3a7713b1edbc 13964 #define TK_TH2_3_LTH3_Msk (0xfful << TK_TH2_3_LTH3_Pos) /*!< TK_T::TH2_3: LTH3 Mask */
AnnaBridge 171:3a7713b1edbc 13965
AnnaBridge 171:3a7713b1edbc 13966 #define TK_TH2_3_HTH3_Pos (24) /*!< TK_T::TH2_3: HTH3 Position */
AnnaBridge 171:3a7713b1edbc 13967 #define TK_TH2_3_HTH3_Msk (0xfful << TK_TH2_3_HTH3_Pos) /*!< TK_T::TH2_3: HTH3 Mask */
AnnaBridge 171:3a7713b1edbc 13968
AnnaBridge 171:3a7713b1edbc 13969 #define TK_TH4_5_LTH4_Pos (0) /*!< TK_T::TH4_5: LTH4 Position */
AnnaBridge 171:3a7713b1edbc 13970 #define TK_TH4_5_LTH4_Msk (0xfful << TK_TH4_5_LTH4_Pos) /*!< TK_T::TH4_5: LTH4 Mask */
AnnaBridge 171:3a7713b1edbc 13971
AnnaBridge 171:3a7713b1edbc 13972 #define TK_TH4_5_HTH4_Pos (8) /*!< TK_T::TH4_5: HTH4 Position */
AnnaBridge 171:3a7713b1edbc 13973 #define TK_TH4_5_HTH4_Msk (0xfful << TK_TH4_5_HTH4_Pos) /*!< TK_T::TH4_5: HTH4 Mask */
AnnaBridge 171:3a7713b1edbc 13974
AnnaBridge 171:3a7713b1edbc 13975 #define TK_TH4_5_LTH5_Pos (16) /*!< TK_T::TH4_5: LTH5 Position */
AnnaBridge 171:3a7713b1edbc 13976 #define TK_TH4_5_LTH5_Msk (0xfful << TK_TH4_5_LTH5_Pos) /*!< TK_T::TH4_5: LTH5 Mask */
AnnaBridge 171:3a7713b1edbc 13977
AnnaBridge 171:3a7713b1edbc 13978 #define TK_TH4_5_HTH5_Pos (24) /*!< TK_T::TH4_5: HTH5 Position */
AnnaBridge 171:3a7713b1edbc 13979 #define TK_TH4_5_HTH5_Msk (0xfful << TK_TH4_5_HTH5_Pos) /*!< TK_T::TH4_5: HTH5 Mask */
AnnaBridge 171:3a7713b1edbc 13980
AnnaBridge 171:3a7713b1edbc 13981 #define TK_TH6_7_LTH6_Pos (0) /*!< TK_T::TH6_7: LTH6 Position */
AnnaBridge 171:3a7713b1edbc 13982 #define TK_TH6_7_LTH6_Msk (0xfful << TK_TH6_7_LTH6_Pos) /*!< TK_T::TH6_7: LTH6 Mask */
AnnaBridge 171:3a7713b1edbc 13983
AnnaBridge 171:3a7713b1edbc 13984 #define TK_TH6_7_HTH6_Pos (8) /*!< TK_T::TH6_7: HTH6 Position */
AnnaBridge 171:3a7713b1edbc 13985 #define TK_TH6_7_HTH6_Msk (0xfful << TK_TH6_7_HTH6_Pos) /*!< TK_T::TH6_7: HTH6 Mask */
AnnaBridge 171:3a7713b1edbc 13986
AnnaBridge 171:3a7713b1edbc 13987 #define TK_TH6_7_LTH7_Pos (16) /*!< TK_T::TH6_7: LTH7 Position */
AnnaBridge 171:3a7713b1edbc 13988 #define TK_TH6_7_LTH7_Msk (0xfful << TK_TH6_7_LTH7_Pos) /*!< TK_T::TH6_7: LTH7 Mask */
AnnaBridge 171:3a7713b1edbc 13989
AnnaBridge 171:3a7713b1edbc 13990 #define TK_TH6_7_HTH7_Pos (24) /*!< TK_T::TH6_7: HTH7 Position */
AnnaBridge 171:3a7713b1edbc 13991 #define TK_TH6_7_HTH7_Msk (0xfful << TK_TH6_7_HTH7_Pos) /*!< TK_T::TH6_7: HTH7 Mask */
AnnaBridge 171:3a7713b1edbc 13992
AnnaBridge 171:3a7713b1edbc 13993 #define TK_TH8_9_LTH8_Pos (0) /*!< TK_T::TH8_9: LTH8 Position */
AnnaBridge 171:3a7713b1edbc 13994 #define TK_TH8_9_LTH8_Msk (0xfful << TK_TH8_9_LTH8_Pos) /*!< TK_T::TH8_9: LTH8 Mask */
AnnaBridge 171:3a7713b1edbc 13995
AnnaBridge 171:3a7713b1edbc 13996 #define TK_TH8_9_HTH8_Pos (8) /*!< TK_T::TH8_9: HTH8 Position */
AnnaBridge 171:3a7713b1edbc 13997 #define TK_TH8_9_HTH8_Msk (0xfful << TK_TH8_9_HTH8_Pos) /*!< TK_T::TH8_9: HTH8 Mask */
AnnaBridge 171:3a7713b1edbc 13998
AnnaBridge 171:3a7713b1edbc 13999 #define TK_TH8_9_LTH9_Pos (16) /*!< TK_T::TH8_9: LTH9 Position */
AnnaBridge 171:3a7713b1edbc 14000 #define TK_TH8_9_LTH9_Msk (0xfful << TK_TH8_9_LTH9_Pos) /*!< TK_T::TH8_9: LTH9 Mask */
AnnaBridge 171:3a7713b1edbc 14001
AnnaBridge 171:3a7713b1edbc 14002 #define TK_TH8_9_HTH9_Pos (24) /*!< TK_T::TH8_9: HTH9 Position */
AnnaBridge 171:3a7713b1edbc 14003 #define TK_TH8_9_HTH9_Msk (0xfful << TK_TH8_9_HTH9_Pos) /*!< TK_T::TH8_9: HTH9 Mask */
AnnaBridge 171:3a7713b1edbc 14004
AnnaBridge 171:3a7713b1edbc 14005 #define TK_TH10_11_LTH10_Pos (0) /*!< TK_T::TH10_11: LTH10 Position */
AnnaBridge 171:3a7713b1edbc 14006 #define TK_TH10_11_LTH10_Msk (0xfful << TK_TH10_11_LTH10_Pos) /*!< TK_T::TH10_11: LTH10 Mask */
AnnaBridge 171:3a7713b1edbc 14007
AnnaBridge 171:3a7713b1edbc 14008 #define TK_TH10_11_HTH10_Pos (8) /*!< TK_T::TH10_11: HTH10 Position */
AnnaBridge 171:3a7713b1edbc 14009 #define TK_TH10_11_HTH10_Msk (0xfful << TK_TH10_11_HTH10_Pos) /*!< TK_T::TH10_11: HTH10 Mask */
AnnaBridge 171:3a7713b1edbc 14010
AnnaBridge 171:3a7713b1edbc 14011 #define TK_TH10_11_LTH11_Pos (16) /*!< TK_T::TH10_11: LTH11 Position */
AnnaBridge 171:3a7713b1edbc 14012 #define TK_TH10_11_LTH11_Msk (0xfful << TK_TH10_11_LTH11_Pos) /*!< TK_T::TH10_11: LTH11 Mask */
AnnaBridge 171:3a7713b1edbc 14013
AnnaBridge 171:3a7713b1edbc 14014 #define TK_TH10_11_HTH11_Pos (24) /*!< TK_T::TH10_11: HTH11 Position */
AnnaBridge 171:3a7713b1edbc 14015 #define TK_TH10_11_HTH11_Msk (0xfful << TK_TH10_11_HTH11_Pos) /*!< TK_T::TH10_11: HTH11 Mask */
AnnaBridge 171:3a7713b1edbc 14016
AnnaBridge 171:3a7713b1edbc 14017 #define TK_TH12_13_LTH12_Pos (0) /*!< TK_T::TH12_13: LTH12 Position */
AnnaBridge 171:3a7713b1edbc 14018 #define TK_TH12_13_LTH12_Msk (0xfful << TK_TH12_13_LTH12_Pos) /*!< TK_T::TH12_13: LTH12 Mask */
AnnaBridge 171:3a7713b1edbc 14019
AnnaBridge 171:3a7713b1edbc 14020 #define TK_TH12_13_HTH12_Pos (8) /*!< TK_T::TH12_13: HTH12 Position */
AnnaBridge 171:3a7713b1edbc 14021 #define TK_TH12_13_HTH12_Msk (0xfful << TK_TH12_13_HTH12_Pos) /*!< TK_T::TH12_13: HTH12 Mask */
AnnaBridge 171:3a7713b1edbc 14022
AnnaBridge 171:3a7713b1edbc 14023 #define TK_TH12_13_LTH13_Pos (16) /*!< TK_T::TH12_13: LTH13 Position */
AnnaBridge 171:3a7713b1edbc 14024 #define TK_TH12_13_LTH13_Msk (0xfful << TK_TH12_13_LTH13_Pos) /*!< TK_T::TH12_13: LTH13 Mask */
AnnaBridge 171:3a7713b1edbc 14025
AnnaBridge 171:3a7713b1edbc 14026 #define TK_TH12_13_HTH13_Pos (24) /*!< TK_T::TH12_13: HTH13 Position */
AnnaBridge 171:3a7713b1edbc 14027 #define TK_TH12_13_HTH13_Msk (0xfful << TK_TH12_13_HTH13_Pos) /*!< TK_T::TH12_13: HTH13 Mask */
AnnaBridge 171:3a7713b1edbc 14028
AnnaBridge 171:3a7713b1edbc 14029 #define TK_TH14_15_LTH14_Pos (0) /*!< TK_T::TH14_15: LTH14 Position */
AnnaBridge 171:3a7713b1edbc 14030 #define TK_TH14_15_LTH14_Msk (0xfful << TK_TH14_15_LTH14_Pos) /*!< TK_T::TH14_15: LTH14 Mask */
AnnaBridge 171:3a7713b1edbc 14031
AnnaBridge 171:3a7713b1edbc 14032 #define TK_TH14_15_HTH14_Pos (8) /*!< TK_T::TH14_15: HTH14 Position */
AnnaBridge 171:3a7713b1edbc 14033 #define TK_TH14_15_HTH14_Msk (0xfful << TK_TH14_15_HTH14_Pos) /*!< TK_T::TH14_15: HTH14 Mask */
AnnaBridge 171:3a7713b1edbc 14034
AnnaBridge 171:3a7713b1edbc 14035 #define TK_TH14_15_LTH15_Pos (16) /*!< TK_T::TH14_15: LTH15 Position */
AnnaBridge 171:3a7713b1edbc 14036 #define TK_TH14_15_LTH15_Msk (0xfful << TK_TH14_15_LTH15_Pos) /*!< TK_T::TH14_15: LTH15 Mask */
AnnaBridge 171:3a7713b1edbc 14037
AnnaBridge 171:3a7713b1edbc 14038 #define TK_TH14_15_HTH15_Pos (24) /*!< TK_T::TH14_15: HTH15 Position */
AnnaBridge 171:3a7713b1edbc 14039 #define TK_TH14_15_HTH15_Msk (0xfful << TK_TH14_15_HTH15_Pos) /*!< TK_T::TH14_15: HTH15 Mask */
AnnaBridge 171:3a7713b1edbc 14040
AnnaBridge 171:3a7713b1edbc 14041 #define TK_TH16_LTH16_Pos (0) /*!< TK_T::TH16: LTH16 Position */
AnnaBridge 171:3a7713b1edbc 14042 #define TK_TH16_LTH16_Msk (0xfful << TK_TH16_LTH16_Pos) /*!< TK_T::TH16: LTH16 Mask */
AnnaBridge 171:3a7713b1edbc 14043
AnnaBridge 171:3a7713b1edbc 14044 #define TK_TH16_HTH16_Pos (8) /*!< TK_T::TH16: HTH16 Position */
AnnaBridge 171:3a7713b1edbc 14045 #define TK_TH16_HTH16_Msk (0xfful << TK_TH16_HTH16_Pos) /*!< TK_T::TH16: HTH16 Mask */
AnnaBridge 171:3a7713b1edbc 14046
AnnaBridge 171:3a7713b1edbc 14047 /**@}*/ /* TK_CONST */
AnnaBridge 171:3a7713b1edbc 14048 /**@}*/ /* end of TK register group */
AnnaBridge 171:3a7713b1edbc 14049
AnnaBridge 171:3a7713b1edbc 14050
AnnaBridge 171:3a7713b1edbc 14051 /*---------------------- Timer Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 14052 /**
AnnaBridge 171:3a7713b1edbc 14053 @addtogroup TMR Timer Controller(TMR)
AnnaBridge 171:3a7713b1edbc 14054 Memory Mapped Structure for TMR Controller
AnnaBridge 171:3a7713b1edbc 14055 @{ */
AnnaBridge 171:3a7713b1edbc 14056
AnnaBridge 171:3a7713b1edbc 14057
AnnaBridge 171:3a7713b1edbc 14058 typedef struct
AnnaBridge 171:3a7713b1edbc 14059 {
AnnaBridge 171:3a7713b1edbc 14060
AnnaBridge 171:3a7713b1edbc 14061
AnnaBridge 171:3a7713b1edbc 14062
AnnaBridge 171:3a7713b1edbc 14063
AnnaBridge 171:3a7713b1edbc 14064 /**
AnnaBridge 171:3a7713b1edbc 14065 * @var TIMER_T::CTL
AnnaBridge 171:3a7713b1edbc 14066 * Offset: 0x00 Timer Control and Status Register
AnnaBridge 171:3a7713b1edbc 14067 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14068 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14069 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14070 * |[7:0] |PSC |Prescale Counter
AnnaBridge 171:3a7713b1edbc 14071 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
AnnaBridge 171:3a7713b1edbc 14072 * | | |If this field is 0 (PSC = 0), then there is no scaling.
AnnaBridge 171:3a7713b1edbc 14073 * |[17] |WKTKEN |Wake-Up Touch-Key Scan Enable Bit
AnnaBridge 171:3a7713b1edbc 14074 * | | |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
AnnaBridge 171:3a7713b1edbc 14075 * | | |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
AnnaBridge 171:3a7713b1edbc 14076 * | | |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
AnnaBridge 171:3a7713b1edbc 14077 * | | |Note: This bit is only available in TIMER0_CTL.
AnnaBridge 171:3a7713b1edbc 14078 * |[18] |TRGSSEL |Trigger Source Select Bit
AnnaBridge 171:3a7713b1edbc 14079 * | | |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
AnnaBridge 171:3a7713b1edbc 14080 * | | |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
AnnaBridge 171:3a7713b1edbc 14081 * | | |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
AnnaBridge 171:3a7713b1edbc 14082 * |[19] |TRGPWM |Trigger PWM Enable Bit
AnnaBridge 171:3a7713b1edbc 14083 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
AnnaBridge 171:3a7713b1edbc 14084 * | | |0 = Timer interrupt trigger PWM Disabled.
AnnaBridge 171:3a7713b1edbc 14085 * | | |1 = Timer interrupt trigger PWM Enabled.
AnnaBridge 171:3a7713b1edbc 14086 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
AnnaBridge 171:3a7713b1edbc 14087 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
AnnaBridge 171:3a7713b1edbc 14088 * |[20] |TRGDAC |Trigger DAC Enable Bit
AnnaBridge 171:3a7713b1edbc 14089 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
AnnaBridge 171:3a7713b1edbc 14090 * | | |0 = Timer interrupt trigger DAC Disabled.
AnnaBridge 171:3a7713b1edbc 14091 * | | |1 = Timer interrupt trigger DAC Enabled.
AnnaBridge 171:3a7713b1edbc 14092 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
AnnaBridge 171:3a7713b1edbc 14093 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
AnnaBridge 171:3a7713b1edbc 14094 * |[21] |TRGEADC |Trigger EADC Enable Bit
AnnaBridge 171:3a7713b1edbc 14095 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
AnnaBridge 171:3a7713b1edbc 14096 * | | |0 = Timer interrupt trigger EADC Disabled.
AnnaBridge 171:3a7713b1edbc 14097 * | | |1 = Timer interrupt trigger EADC Enabled.
AnnaBridge 171:3a7713b1edbc 14098 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
AnnaBridge 171:3a7713b1edbc 14099 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
AnnaBridge 171:3a7713b1edbc 14100 * |[22] |TGLPINSEL |Toggle-Output Pin Select
AnnaBridge 171:3a7713b1edbc 14101 * | | |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
AnnaBridge 171:3a7713b1edbc 14102 * | | |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
AnnaBridge 171:3a7713b1edbc 14103 * |[23] |WKEN |Wake-Up Function Enable Bit
AnnaBridge 171:3a7713b1edbc 14104 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
AnnaBridge 171:3a7713b1edbc 14105 * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 14106 * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 14107 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 14108 * | | |This bit is for external counting pin function enabled.
AnnaBridge 171:3a7713b1edbc 14109 * | | |0 = Event counter mode Disabled.
AnnaBridge 171:3a7713b1edbc 14110 * | | |1 = Event counter mode Enabled.
AnnaBridge 171:3a7713b1edbc 14111 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
AnnaBridge 171:3a7713b1edbc 14112 * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
AnnaBridge 171:3a7713b1edbc 14113 * | | |This bit indicates the 24-bit up counter status.
AnnaBridge 171:3a7713b1edbc 14114 * | | |0 = 24-bit up counter is not active.
AnnaBridge 171:3a7713b1edbc 14115 * | | |1 = 24-bit up counter is active.
AnnaBridge 171:3a7713b1edbc 14116 * |[26] |RSTCNT |Timer Counter Reset Bit
AnnaBridge 171:3a7713b1edbc 14117 * | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
AnnaBridge 171:3a7713b1edbc 14118 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 14119 * | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
AnnaBridge 171:3a7713b1edbc 14120 * |[28:27] |OPMODE |Timer Counting Mode Select
AnnaBridge 171:3a7713b1edbc 14121 * | | |00 = The Timer controller is operated in One-shot mode.
AnnaBridge 171:3a7713b1edbc 14122 * | | |01 = The Timer controller is operated in Periodic mode.
AnnaBridge 171:3a7713b1edbc 14123 * | | |10 = The Timer controller is operated in Toggle-output mode.
AnnaBridge 171:3a7713b1edbc 14124 * | | |11 = The Timer controller is operated in Continuous Counting mode.
AnnaBridge 171:3a7713b1edbc 14125 * |[29] |INTEN |Timer Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14126 * | | |0 = Timer Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14127 * | | |1 = Timer Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14128 * | | |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
AnnaBridge 171:3a7713b1edbc 14129 * |[30] |CNTEN |Timer Counting Enable Bit
AnnaBridge 171:3a7713b1edbc 14130 * | | |0 = Stops/Suspends counting.
AnnaBridge 171:3a7713b1edbc 14131 * | | |1 = Starts counting.
AnnaBridge 171:3a7713b1edbc 14132 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
AnnaBridge 171:3a7713b1edbc 14133 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
AnnaBridge 171:3a7713b1edbc 14134 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable
AnnaBridge 171:3a7713b1edbc 14135 * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
AnnaBridge 171:3a7713b1edbc 14136 * | | |TIMER counter will be held while CPU is held by ICE.
AnnaBridge 171:3a7713b1edbc 14137 * | | |1 = ICE debug mode acknowledgement Disabled.
AnnaBridge 171:3a7713b1edbc 14138 * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
AnnaBridge 171:3a7713b1edbc 14139 * @var TIMER_T::CMP
AnnaBridge 171:3a7713b1edbc 14140 * Offset: 0x04 Timer Compare Register
AnnaBridge 171:3a7713b1edbc 14141 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14142 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14143 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14144 * |[23:0] |CMPDAT |Timer Compared Value
AnnaBridge 171:3a7713b1edbc 14145 * | | |CMPDAT is a 24-bit compared value register.
AnnaBridge 171:3a7713b1edbc 14146 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
AnnaBridge 171:3a7713b1edbc 14147 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
AnnaBridge 171:3a7713b1edbc 14148 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
AnnaBridge 171:3a7713b1edbc 14149 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
AnnaBridge 171:3a7713b1edbc 14150 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
AnnaBridge 171:3a7713b1edbc 14151 * @var TIMER_T::INTSTS
AnnaBridge 171:3a7713b1edbc 14152 * Offset: 0x08 Timer Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 14153 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14154 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14155 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14156 * |[0] |TIF |Timer Interrupt Flag
AnnaBridge 171:3a7713b1edbc 14157 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
AnnaBridge 171:3a7713b1edbc 14158 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 14159 * | | |1 = CNT value matches the CMPDAT value.
AnnaBridge 171:3a7713b1edbc 14160 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14161 * |[1] |TWKF |Timer Wake-Up Flag
AnnaBridge 171:3a7713b1edbc 14162 * | | |This bit indicates the interrupt wake-up flag status of timer.
AnnaBridge 171:3a7713b1edbc 14163 * | | |0 = Timer does not cause CPU wake-up.
AnnaBridge 171:3a7713b1edbc 14164 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 14165 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14166 * @var TIMER_T::CNT
AnnaBridge 171:3a7713b1edbc 14167 * Offset: 0x0C Timer Data Register
AnnaBridge 171:3a7713b1edbc 14168 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14169 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14170 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14171 * |[23:0] |CNT |Timer Data Register
AnnaBridge 171:3a7713b1edbc 14172 * | | |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
AnnaBridge 171:3a7713b1edbc 14173 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
AnnaBridge 171:3a7713b1edbc 14174 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
AnnaBridge 171:3a7713b1edbc 14175 * @var TIMER_T::CAP
AnnaBridge 171:3a7713b1edbc 14176 * Offset: 0x10 Timer Capture Data Register
AnnaBridge 171:3a7713b1edbc 14177 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14178 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14179 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14180 * |[23:0] |CAPDAT |Timer Capture Data Register
AnnaBridge 171:3a7713b1edbc 14181 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
AnnaBridge 171:3a7713b1edbc 14182 * @var TIMER_T::EXTCTL
AnnaBridge 171:3a7713b1edbc 14183 * Offset: 0x14 Timer External Control Register
AnnaBridge 171:3a7713b1edbc 14184 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14185 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14186 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14187 * |[0] |CNTPHASE |Timer External Count Phase
AnnaBridge 171:3a7713b1edbc 14188 * | | |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
AnnaBridge 171:3a7713b1edbc 14189 * | | |0 = A Falling edge of external counting pin will be counted.
AnnaBridge 171:3a7713b1edbc 14190 * | | |1 = A Rising edge of external counting pin will be counted.
AnnaBridge 171:3a7713b1edbc 14191 * |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
AnnaBridge 171:3a7713b1edbc 14192 * | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
AnnaBridge 171:3a7713b1edbc 14193 * | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
AnnaBridge 171:3a7713b1edbc 14194 * | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
AnnaBridge 171:3a7713b1edbc 14195 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 14196 * |[3] |CAPEN |Timer External Capture Pin Enable
AnnaBridge 171:3a7713b1edbc 14197 * | | |This bit enables the Tx_EXT pin.
AnnaBridge 171:3a7713b1edbc 14198 * | | |0 =Tx_EXT (x= 0~3) pin Disabled.
AnnaBridge 171:3a7713b1edbc 14199 * | | |1 =Tx_EXT (x= 0~3) pin Enabled.
AnnaBridge 171:3a7713b1edbc 14200 * |[4] |CAPFUNCS |Capture Function Selection
AnnaBridge 171:3a7713b1edbc 14201 * | | |0 = External Capture Mode Enabled.
AnnaBridge 171:3a7713b1edbc 14202 * | | |1 = External Reset Mode Enabled.
AnnaBridge 171:3a7713b1edbc 14203 * | | |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
AnnaBridge 171:3a7713b1edbc 14204 * | | |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
AnnaBridge 171:3a7713b1edbc 14205 * |[5] |CAPIEN |Timer External Capture Interrupt Enable
AnnaBridge 171:3a7713b1edbc 14206 * | | |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14207 * | | |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14208 * | | |Note: CAPIEN is used to enable timer external interrupt.
AnnaBridge 171:3a7713b1edbc 14209 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
AnnaBridge 171:3a7713b1edbc 14210 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
AnnaBridge 171:3a7713b1edbc 14211 * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
AnnaBridge 171:3a7713b1edbc 14212 * | | |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
AnnaBridge 171:3a7713b1edbc 14213 * | | |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
AnnaBridge 171:3a7713b1edbc 14214 * | | |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
AnnaBridge 171:3a7713b1edbc 14215 * |[7] |CNTDBEN |Timer Counter Pin De-Bounce Enable
AnnaBridge 171:3a7713b1edbc 14216 * | | |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
AnnaBridge 171:3a7713b1edbc 14217 * | | |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
AnnaBridge 171:3a7713b1edbc 14218 * | | |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
AnnaBridge 171:3a7713b1edbc 14219 * @var TIMER_T::EINTSTS
AnnaBridge 171:3a7713b1edbc 14220 * Offset: 0x18 Timer External Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 14221 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14222 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14223 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14224 * |[0] |CAPIF |Timer External Capture Interrupt Flag
AnnaBridge 171:3a7713b1edbc 14225 * | | |This bit indicates the timer external capture interrupt flag status.
AnnaBridge 171:3a7713b1edbc 14226 * | | |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
AnnaBridge 171:3a7713b1edbc 14227 * | | |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
AnnaBridge 171:3a7713b1edbc 14228 * | | |Note1: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14229 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
AnnaBridge 171:3a7713b1edbc 14230 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
AnnaBridge 171:3a7713b1edbc 14231 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
AnnaBridge 171:3a7713b1edbc 14232 */
AnnaBridge 171:3a7713b1edbc 14233
AnnaBridge 171:3a7713b1edbc 14234 __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
AnnaBridge 171:3a7713b1edbc 14235 __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 14236 __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 14237 __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
AnnaBridge 171:3a7713b1edbc 14238 __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
AnnaBridge 171:3a7713b1edbc 14239 __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
AnnaBridge 171:3a7713b1edbc 14240 __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 14241
AnnaBridge 171:3a7713b1edbc 14242 } TIMER_T;
AnnaBridge 171:3a7713b1edbc 14243
AnnaBridge 171:3a7713b1edbc 14244
AnnaBridge 171:3a7713b1edbc 14245
AnnaBridge 171:3a7713b1edbc 14246 /**
AnnaBridge 171:3a7713b1edbc 14247 @addtogroup TMR_CONST TMR Bit Field Definition
AnnaBridge 171:3a7713b1edbc 14248 Constant Definitions for TMR Controller
AnnaBridge 171:3a7713b1edbc 14249 @{ */
AnnaBridge 171:3a7713b1edbc 14250
AnnaBridge 171:3a7713b1edbc 14251 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
AnnaBridge 171:3a7713b1edbc 14252 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
AnnaBridge 171:3a7713b1edbc 14253
AnnaBridge 171:3a7713b1edbc 14254 #define TIMER_CTL_WKTKEN_Pos (17) /*!< TIMER_T::CTL: WKTKEN Position */
AnnaBridge 171:3a7713b1edbc 14255 #define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) /*!< TIMER_T::CTL: WKTKEN Mask */
AnnaBridge 171:3a7713b1edbc 14256
AnnaBridge 171:3a7713b1edbc 14257 #define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
AnnaBridge 171:3a7713b1edbc 14258 #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
AnnaBridge 171:3a7713b1edbc 14259
AnnaBridge 171:3a7713b1edbc 14260 #define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
AnnaBridge 171:3a7713b1edbc 14261 #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
AnnaBridge 171:3a7713b1edbc 14262
AnnaBridge 171:3a7713b1edbc 14263 #define TIMER_CTL_TRGDAC_Pos (20) /*!< TIMER_T::CTL: TRGDAC Position */
AnnaBridge 171:3a7713b1edbc 14264 #define TIMER_CTL_TRGDAC_Msk (0x1ul << TIMER_CTL_TRGDAC_Pos) /*!< TIMER_T::CTL: TRGDAC Mask */
AnnaBridge 171:3a7713b1edbc 14265
AnnaBridge 171:3a7713b1edbc 14266 #define TIMER_CTL_TRGEADC_Pos (21) /*!< TIMER_T::CTL: TRGEADC Position */
AnnaBridge 171:3a7713b1edbc 14267 #define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) /*!< TIMER_T::CTL: TRGEADC Mask */
AnnaBridge 171:3a7713b1edbc 14268
AnnaBridge 171:3a7713b1edbc 14269 #define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
AnnaBridge 171:3a7713b1edbc 14270 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
AnnaBridge 171:3a7713b1edbc 14271
AnnaBridge 171:3a7713b1edbc 14272 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
AnnaBridge 171:3a7713b1edbc 14273 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 14274
AnnaBridge 171:3a7713b1edbc 14275 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
AnnaBridge 171:3a7713b1edbc 14276 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
AnnaBridge 171:3a7713b1edbc 14277
AnnaBridge 171:3a7713b1edbc 14278 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
AnnaBridge 171:3a7713b1edbc 14279 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
AnnaBridge 171:3a7713b1edbc 14280
AnnaBridge 171:3a7713b1edbc 14281 #define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
AnnaBridge 171:3a7713b1edbc 14282 #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
AnnaBridge 171:3a7713b1edbc 14283
AnnaBridge 171:3a7713b1edbc 14284 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
AnnaBridge 171:3a7713b1edbc 14285 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
AnnaBridge 171:3a7713b1edbc 14286
AnnaBridge 171:3a7713b1edbc 14287 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
AnnaBridge 171:3a7713b1edbc 14288 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 14289
AnnaBridge 171:3a7713b1edbc 14290 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
AnnaBridge 171:3a7713b1edbc 14291 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
AnnaBridge 171:3a7713b1edbc 14292
AnnaBridge 171:3a7713b1edbc 14293 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
AnnaBridge 171:3a7713b1edbc 14294 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
AnnaBridge 171:3a7713b1edbc 14295
AnnaBridge 171:3a7713b1edbc 14296 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
AnnaBridge 171:3a7713b1edbc 14297 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
AnnaBridge 171:3a7713b1edbc 14298
AnnaBridge 171:3a7713b1edbc 14299 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
AnnaBridge 171:3a7713b1edbc 14300 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
AnnaBridge 171:3a7713b1edbc 14301
AnnaBridge 171:3a7713b1edbc 14302 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
AnnaBridge 171:3a7713b1edbc 14303 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
AnnaBridge 171:3a7713b1edbc 14304
AnnaBridge 171:3a7713b1edbc 14305 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
AnnaBridge 171:3a7713b1edbc 14306 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
AnnaBridge 171:3a7713b1edbc 14307
AnnaBridge 171:3a7713b1edbc 14308 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
AnnaBridge 171:3a7713b1edbc 14309 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
AnnaBridge 171:3a7713b1edbc 14310
AnnaBridge 171:3a7713b1edbc 14311 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
AnnaBridge 171:3a7713b1edbc 14312 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
AnnaBridge 171:3a7713b1edbc 14313
AnnaBridge 171:3a7713b1edbc 14314 #define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
AnnaBridge 171:3a7713b1edbc 14315 #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
AnnaBridge 171:3a7713b1edbc 14316
AnnaBridge 171:3a7713b1edbc 14317 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
AnnaBridge 171:3a7713b1edbc 14318 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
AnnaBridge 171:3a7713b1edbc 14319
AnnaBridge 171:3a7713b1edbc 14320 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
AnnaBridge 171:3a7713b1edbc 14321 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
AnnaBridge 171:3a7713b1edbc 14322
AnnaBridge 171:3a7713b1edbc 14323 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
AnnaBridge 171:3a7713b1edbc 14324 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
AnnaBridge 171:3a7713b1edbc 14325
AnnaBridge 171:3a7713b1edbc 14326 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
AnnaBridge 171:3a7713b1edbc 14327 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
AnnaBridge 171:3a7713b1edbc 14328
AnnaBridge 171:3a7713b1edbc 14329 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
AnnaBridge 171:3a7713b1edbc 14330 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
AnnaBridge 171:3a7713b1edbc 14331
AnnaBridge 171:3a7713b1edbc 14332 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
AnnaBridge 171:3a7713b1edbc 14333 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
AnnaBridge 171:3a7713b1edbc 14334
AnnaBridge 171:3a7713b1edbc 14335 /**@}*/ /* TIMER_CONST */
AnnaBridge 171:3a7713b1edbc 14336 /**@}*/ /* end of TIMER register group */
AnnaBridge 171:3a7713b1edbc 14337
AnnaBridge 171:3a7713b1edbc 14338
AnnaBridge 171:3a7713b1edbc 14339 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 14340 /**
AnnaBridge 171:3a7713b1edbc 14341 @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
AnnaBridge 171:3a7713b1edbc 14342 Memory Mapped Structure for UART Controller
AnnaBridge 171:3a7713b1edbc 14343 @{ */
AnnaBridge 171:3a7713b1edbc 14344
AnnaBridge 171:3a7713b1edbc 14345
AnnaBridge 171:3a7713b1edbc 14346 typedef struct
AnnaBridge 171:3a7713b1edbc 14347 {
AnnaBridge 171:3a7713b1edbc 14348
AnnaBridge 171:3a7713b1edbc 14349
AnnaBridge 171:3a7713b1edbc 14350
AnnaBridge 171:3a7713b1edbc 14351
AnnaBridge 171:3a7713b1edbc 14352 /**
AnnaBridge 171:3a7713b1edbc 14353 * @var UART_T::DAT
AnnaBridge 171:3a7713b1edbc 14354 * Offset: 0x00 UART Receive/Transmit Buffer Register
AnnaBridge 171:3a7713b1edbc 14355 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14356 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14357 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14358 * |[7:0] |DAT |Receiving/Transmit Buffer
AnnaBridge 171:3a7713b1edbc 14359 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 14360 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
AnnaBridge 171:3a7713b1edbc 14361 * | | |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
AnnaBridge 171:3a7713b1edbc 14362 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 14363 * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
AnnaBridge 171:3a7713b1edbc 14364 * @var UART_T::INTEN
AnnaBridge 171:3a7713b1edbc 14365 * Offset: 0x04 UART Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 14366 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14367 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14368 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14369 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14370 * | | |0 = Receive data available interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14371 * | | |1 = Receive data available interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14372 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14373 * | | |0 = Transmit holding register empty interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14374 * | | |1 = Transmit holding register empty interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14375 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14376 * | | |0 = Receive Line Status interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14377 * | | |1 = Receive Line Status interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14378 * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14379 * | | |0 = Modem status interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14380 * | | |1 = Modem status interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14381 * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14382 * | | |0 = RX time-out interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14383 * | | |1 = RX time-out interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14384 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14385 * | | |0 = Buffer error interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14386 * | | |1 = Buffer error interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14387 * |[8] |LINIEN |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
AnnaBridge 171:3a7713b1edbc 14388 * | | |0 = LIN bus interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14389 * | | |1 = LIN bus interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14390 * | | |Note: This bit is used for LIN function mode.
AnnaBridge 171:3a7713b1edbc 14391 * |[9] |WKCTSIEN |nCTS Wake-Up Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14392 * | | |0 = nCTS wake-up system function Disabled.
AnnaBridge 171:3a7713b1edbc 14393 * | | |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
AnnaBridge 171:3a7713b1edbc 14394 * |[10] |WKDATIEN |Incoming Data Wake-Up Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14395 * | | |0 = Incoming data wake-up system function Disabled.
AnnaBridge 171:3a7713b1edbc 14396 * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
AnnaBridge 171:3a7713b1edbc 14397 * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
AnnaBridge 171:3a7713b1edbc 14398 * |[11] |TOCNTEN |Time-Out Counter Enable Bit
AnnaBridge 171:3a7713b1edbc 14399 * | | |0 = Time-out counter Disabled.
AnnaBridge 171:3a7713b1edbc 14400 * | | |1 = Time-out counter Enabled.
AnnaBridge 171:3a7713b1edbc 14401 * |[12] |ATORTSEN |nRTS Auto-Flow Control Enable Bit
AnnaBridge 171:3a7713b1edbc 14402 * | | |0 = nRTS auto-flow control Disabled.
AnnaBridge 171:3a7713b1edbc 14403 * | | |1 = nRTS auto-flow control Enabled.
AnnaBridge 171:3a7713b1edbc 14404 * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
AnnaBridge 171:3a7713b1edbc 14405 * |[13] |ATOCTSEN |nCTS Auto-Flow Control Enable Bit
AnnaBridge 171:3a7713b1edbc 14406 * | | |0 = nCTS auto-flow control Disabled.
AnnaBridge 171:3a7713b1edbc 14407 * | | |1 = nCTS auto-flow control Enabled.
AnnaBridge 171:3a7713b1edbc 14408 * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
AnnaBridge 171:3a7713b1edbc 14409 * |[14] |TXPDMAEN |TX DMA Enable Bit
AnnaBridge 171:3a7713b1edbc 14410 * | | |This bit can enable or disable TX DMA service.
AnnaBridge 171:3a7713b1edbc 14411 * | | |0 = TX DMA Disabled.
AnnaBridge 171:3a7713b1edbc 14412 * | | |1 = TX DMA Enabled.
AnnaBridge 171:3a7713b1edbc 14413 * |[15] |RXPDMAEN |RX DMA Enable Bit
AnnaBridge 171:3a7713b1edbc 14414 * | | |This bit can enable or disable RX DMA service.
AnnaBridge 171:3a7713b1edbc 14415 * | | |0 = RX DMA Disabled.
AnnaBridge 171:3a7713b1edbc 14416 * | | |1 = RX DMA Enabled.
AnnaBridge 171:3a7713b1edbc 14417 * |[18] |ABRIEN |Auto-Baud Rate Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 14418 * | | |0 = Auto-baud rate interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 14419 * | | |1 = Auto-baud rate interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 14420 * @var UART_T::FIFO
AnnaBridge 171:3a7713b1edbc 14421 * Offset: 0x08 UART FIFO Control Register
AnnaBridge 171:3a7713b1edbc 14422 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14423 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14424 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14425 * |[1] |RXRST |RX Field Software Reset
AnnaBridge 171:3a7713b1edbc 14426 * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
AnnaBridge 171:3a7713b1edbc 14427 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 14428 * | | |1 = Reset the RX internal state machine and pointers.
AnnaBridge 171:3a7713b1edbc 14429 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
AnnaBridge 171:3a7713b1edbc 14430 * |[2] |TXRST |TX Field Software Reset
AnnaBridge 171:3a7713b1edbc 14431 * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
AnnaBridge 171:3a7713b1edbc 14432 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 14433 * | | |1 = Reset the TX internal state machine and pointers.
AnnaBridge 171:3a7713b1edbc 14434 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
AnnaBridge 171:3a7713b1edbc 14435 * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
AnnaBridge 171:3a7713b1edbc 14436 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
AnnaBridge 171:3a7713b1edbc 14437 * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
AnnaBridge 171:3a7713b1edbc 14438 * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
AnnaBridge 171:3a7713b1edbc 14439 * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
AnnaBridge 171:3a7713b1edbc 14440 * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
AnnaBridge 171:3a7713b1edbc 14441 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 14442 * |[8] |RXOFF |Receiver Disable
AnnaBridge 171:3a7713b1edbc 14443 * | | |The receiver is disabled or not (set 1 to disable receiver)
AnnaBridge 171:3a7713b1edbc 14444 * | | |0 = Receiver Enabled.
AnnaBridge 171:3a7713b1edbc 14445 * | | |1 = Receiver Disabled.
AnnaBridge 171:3a7713b1edbc 14446 * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.
AnnaBridge 171:3a7713b1edbc 14447 * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
AnnaBridge 171:3a7713b1edbc 14448 * |[19:16] |RTSTRGLV |nRTS Trigger Level For Auto-Flow Control Use
AnnaBridge 171:3a7713b1edbc 14449 * | | |0000 = nRTS Trigger Level is 1 bytes.
AnnaBridge 171:3a7713b1edbc 14450 * | | |0001 = nRTS Trigger Level is 4bytes.
AnnaBridge 171:3a7713b1edbc 14451 * | | |0010 = nRTS Trigger Level is 8 bytes.
AnnaBridge 171:3a7713b1edbc 14452 * | | |0011 = nRTS Trigger Level is 14 bytes.
AnnaBridge 171:3a7713b1edbc 14453 * | | |Others = Reserved.
AnnaBridge 171:3a7713b1edbc 14454 * | | |Note: This field is used for auto nRTS flow control.
AnnaBridge 171:3a7713b1edbc 14455 * @var UART_T::LINE
AnnaBridge 171:3a7713b1edbc 14456 * Offset: 0x0C UART Line Control Register
AnnaBridge 171:3a7713b1edbc 14457 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14458 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14459 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14460 * |[1:0] |WLS |Word Length Selection
AnnaBridge 171:3a7713b1edbc 14461 * | | |This field sets UART word length.
AnnaBridge 171:3a7713b1edbc 14462 * | | |00 = 5 bits.
AnnaBridge 171:3a7713b1edbc 14463 * | | |01 = 6 bits.
AnnaBridge 171:3a7713b1edbc 14464 * | | |10 = 7 bits.
AnnaBridge 171:3a7713b1edbc 14465 * | | |11 = 8 bits.
AnnaBridge 171:3a7713b1edbc 14466 * |[2] |NSB |Number Of "STOP Bit"
AnnaBridge 171:3a7713b1edbc 14467 * | | |0 = One "STOP bit" is generated in the transmitted data.
AnnaBridge 171:3a7713b1edbc 14468 * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
AnnaBridge 171:3a7713b1edbc 14469 * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
AnnaBridge 171:3a7713b1edbc 14470 * |[3] |PBE |Parity Bit Enable Bit
AnnaBridge 171:3a7713b1edbc 14471 * | | |0 = No parity bit generated Disabled.
AnnaBridge 171:3a7713b1edbc 14472 * | | |1 = Parity bit generated Enabled.
AnnaBridge 171:3a7713b1edbc 14473 * | | |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
AnnaBridge 171:3a7713b1edbc 14474 * |[4] |EPE |Even Parity Enable Bit
AnnaBridge 171:3a7713b1edbc 14475 * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
AnnaBridge 171:3a7713b1edbc 14476 * | | |1 = Even number of logic 1's is transmitted and checked in each word.
AnnaBridge 171:3a7713b1edbc 14477 * | | |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
AnnaBridge 171:3a7713b1edbc 14478 * |[5] |SPE |Stick Parity Enable Bit
AnnaBridge 171:3a7713b1edbc 14479 * | | |0 = Stick parity Disabled.
AnnaBridge 171:3a7713b1edbc 14480 * | | |1 = Stick parity Enabled.
AnnaBridge 171:3a7713b1edbc 14481 * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
AnnaBridge 171:3a7713b1edbc 14482 * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
AnnaBridge 171:3a7713b1edbc 14483 * |[6] |BCB |Break Control Bit
AnnaBridge 171:3a7713b1edbc 14484 * | | |0 = Break Control Disabled.
AnnaBridge 171:3a7713b1edbc 14485 * | | |1 = Break Control Enabled.
AnnaBridge 171:3a7713b1edbc 14486 * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
AnnaBridge 171:3a7713b1edbc 14487 * | | |This bit acts only on TX line and has no effect on the transmitter logic.
AnnaBridge 171:3a7713b1edbc 14488 * @var UART_T::MODEM
AnnaBridge 171:3a7713b1edbc 14489 * Offset: 0x10 UART Modem Control Register
AnnaBridge 171:3a7713b1edbc 14490 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14491 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14492 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14493 * |[1] |RTS |nRTS (Request-To-Send) Signal Control
AnnaBridge 171:3a7713b1edbc 14494 * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
AnnaBridge 171:3a7713b1edbc 14495 * | | |0 = nRTS signal is active.
AnnaBridge 171:3a7713b1edbc 14496 * | | |1 = nRTS signal is inactive.
AnnaBridge 171:3a7713b1edbc 14497 * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
AnnaBridge 171:3a7713b1edbc 14498 * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
AnnaBridge 171:3a7713b1edbc 14499 * |[9] |RTSACTLV |nRTS Pin Active Level
AnnaBridge 171:3a7713b1edbc 14500 * | | |This bit defines the active level state of nRTS pin output.
AnnaBridge 171:3a7713b1edbc 14501 * | | |0 =n RTS pin output is high level active.
AnnaBridge 171:3a7713b1edbc 14502 * | | |1 = nRTS pin output is low level active. (Default)
AnnaBridge 171:3a7713b1edbc 14503 * | | |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
AnnaBridge 171:3a7713b1edbc 14504 * | | |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
AnnaBridge 171:3a7713b1edbc 14505 * |[13] |RTSSTS |nRTS Pin Status (Read Only)
AnnaBridge 171:3a7713b1edbc 14506 * | | |This bit mirror from nRTS pin output of voltage logic status.
AnnaBridge 171:3a7713b1edbc 14507 * | | |0 = nRTS pin output is low level voltage logic state.
AnnaBridge 171:3a7713b1edbc 14508 * | | |1 = nRTS pin output is high level voltage logic state.
AnnaBridge 171:3a7713b1edbc 14509 * @var UART_T::MODEMSTS
AnnaBridge 171:3a7713b1edbc 14510 * Offset: 0x14 UART Modem Status Register
AnnaBridge 171:3a7713b1edbc 14511 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14512 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14513 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14514 * |[0] |CTSDETF |Detect nCTS State Change Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14515 * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
AnnaBridge 171:3a7713b1edbc 14516 * | | |0 = nCTS input has not change state.
AnnaBridge 171:3a7713b1edbc 14517 * | | |1 = nCTS input has change state.
AnnaBridge 171:3a7713b1edbc 14518 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 14519 * |[4] |CTSSTS |nCTS Pin Status (Read Only)
AnnaBridge 171:3a7713b1edbc 14520 * | | |This bit mirror from nCTS pin input of voltage logic status.
AnnaBridge 171:3a7713b1edbc 14521 * | | |0 = nCTS pin input is low level voltage logic state.
AnnaBridge 171:3a7713b1edbc 14522 * | | |1 = nCTS pin input is high level voltage logic state.
AnnaBridge 171:3a7713b1edbc 14523 * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
AnnaBridge 171:3a7713b1edbc 14524 * |[8] |CTSACTLV |nCTS Pin Active Level
AnnaBridge 171:3a7713b1edbc 14525 * | | |This bit defines the active level state of nCTS pin input.
AnnaBridge 171:3a7713b1edbc 14526 * | | |0 = nCTS pin input is high level active.
AnnaBridge 171:3a7713b1edbc 14527 * | | |1 = nCTS pin input is low level active. (Default)
AnnaBridge 171:3a7713b1edbc 14528 * @var UART_T::FIFOSTS
AnnaBridge 171:3a7713b1edbc 14529 * Offset: 0x18 UART FIFO Status Register
AnnaBridge 171:3a7713b1edbc 14530 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14531 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14532 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14533 * |[0] |RXOVIF |RX Overflow Error Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14534 * | | |This bit is set when RX FIFO overflow.
AnnaBridge 171:3a7713b1edbc 14535 * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
AnnaBridge 171:3a7713b1edbc 14536 * | | |0 = RX FIFO is not overflow.
AnnaBridge 171:3a7713b1edbc 14537 * | | |1 = RX FIFO is overflow.
AnnaBridge 171:3a7713b1edbc 14538 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 14539 * |[1] |ABRDIF |Auto-Baud Rate Detect Interrupt (Read Only)
AnnaBridge 171:3a7713b1edbc 14540 * | | |0 = Auto-baud rate detect function is not finished.
AnnaBridge 171:3a7713b1edbc 14541 * | | |1 = Auto-baud rate detect function is finished.
AnnaBridge 171:3a7713b1edbc 14542 * | | |This bit is set to logic "1" when auto-baud rate detect function is finished.
AnnaBridge 171:3a7713b1edbc 14543 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 14544 * |[2] |ABRDTOIF |Auto-Baud Rate Time-Out Interrupt (Read Only)
AnnaBridge 171:3a7713b1edbc 14545 * | | |0 = Auto-baud rate counter is underflow.
AnnaBridge 171:3a7713b1edbc 14546 * | | |1 = Auto-baud rate counter is overflow.
AnnaBridge 171:3a7713b1edbc 14547 * | | |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
AnnaBridge 171:3a7713b1edbc 14548 * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 14549 * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14550 * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
AnnaBridge 171:3a7713b1edbc 14551 * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
AnnaBridge 171:3a7713b1edbc 14552 * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
AnnaBridge 171:3a7713b1edbc 14553 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14554 * |[4] |PEF |Parity Error Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14555 * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
AnnaBridge 171:3a7713b1edbc 14556 * | | |0 = No parity error is generated.
AnnaBridge 171:3a7713b1edbc 14557 * | | |1 = Parity error is generated.
AnnaBridge 171:3a7713b1edbc 14558 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14559 * |[5] |FEF |Framing Error Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14560 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
AnnaBridge 171:3a7713b1edbc 14561 * | | |0 = No framing error is generated.
AnnaBridge 171:3a7713b1edbc 14562 * | | |1 = Framing error is generated.
AnnaBridge 171:3a7713b1edbc 14563 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14564 * |[6] |BIF |Break Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14565 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
AnnaBridge 171:3a7713b1edbc 14566 * | | |0 = No Break interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14567 * | | |1 = Break interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14568 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14569 * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
AnnaBridge 171:3a7713b1edbc 14570 * | | |This field indicates the RX FIFO Buffer Pointer.
AnnaBridge 171:3a7713b1edbc 14571 * | | |When UART receives one byte from external device, RXPTR increases one.
AnnaBridge 171:3a7713b1edbc 14572 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
AnnaBridge 171:3a7713b1edbc 14573 * | | |The Maximum value shown in RXPTR is 15.
AnnaBridge 171:3a7713b1edbc 14574 * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
AnnaBridge 171:3a7713b1edbc 14575 * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
AnnaBridge 171:3a7713b1edbc 14576 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
AnnaBridge 171:3a7713b1edbc 14577 * | | |This bit initiate RX FIFO empty or not.
AnnaBridge 171:3a7713b1edbc 14578 * | | |0 = RX FIFO is not empty.
AnnaBridge 171:3a7713b1edbc 14579 * | | |1 = RX FIFO is empty.
AnnaBridge 171:3a7713b1edbc 14580 * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
AnnaBridge 171:3a7713b1edbc 14581 * | | |It will be cleared when UART receives any new data.
AnnaBridge 171:3a7713b1edbc 14582 * |[15] |RXFULL |Receiver FIFO Full (Read Only)
AnnaBridge 171:3a7713b1edbc 14583 * | | |This bit initiates RX FIFO full or not.
AnnaBridge 171:3a7713b1edbc 14584 * | | |0 = RX FIFO is not full.
AnnaBridge 171:3a7713b1edbc 14585 * | | |1 = RX FIFO is full.
AnnaBridge 171:3a7713b1edbc 14586 * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
AnnaBridge 171:3a7713b1edbc 14587 * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
AnnaBridge 171:3a7713b1edbc 14588 * | | |This field indicates the TX FIFO Buffer Pointer.
AnnaBridge 171:3a7713b1edbc 14589 * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
AnnaBridge 171:3a7713b1edbc 14590 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
AnnaBridge 171:3a7713b1edbc 14591 * | | |The Maximum value shown in TXPTR is 15.
AnnaBridge 171:3a7713b1edbc 14592 * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
AnnaBridge 171:3a7713b1edbc 14593 * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
AnnaBridge 171:3a7713b1edbc 14594 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
AnnaBridge 171:3a7713b1edbc 14595 * | | |This bit indicates TX FIFO empty or not.
AnnaBridge 171:3a7713b1edbc 14596 * | | |0 = TX FIFO is not empty.
AnnaBridge 171:3a7713b1edbc 14597 * | | |1 = TX FIFO is empty.
AnnaBridge 171:3a7713b1edbc 14598 * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
AnnaBridge 171:3a7713b1edbc 14599 * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
AnnaBridge 171:3a7713b1edbc 14600 * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
AnnaBridge 171:3a7713b1edbc 14601 * | | |This bit indicates TX FIFO full or not.
AnnaBridge 171:3a7713b1edbc 14602 * | | |0 = TX FIFO is not full.
AnnaBridge 171:3a7713b1edbc 14603 * | | |1 = TX FIFO is full.
AnnaBridge 171:3a7713b1edbc 14604 * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
AnnaBridge 171:3a7713b1edbc 14605 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14606 * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
AnnaBridge 171:3a7713b1edbc 14607 * | | |0 = TX FIFO is not overflow.
AnnaBridge 171:3a7713b1edbc 14608 * | | |1 = TX FIFO is overflow.
AnnaBridge 171:3a7713b1edbc 14609 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
AnnaBridge 171:3a7713b1edbc 14610 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14611 * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
AnnaBridge 171:3a7713b1edbc 14612 * | | |0 = TX FIFO is not empty.
AnnaBridge 171:3a7713b1edbc 14613 * | | |1 = TX FIFO is empty.
AnnaBridge 171:3a7713b1edbc 14614 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
AnnaBridge 171:3a7713b1edbc 14615 * @var UART_T::INTSTS
AnnaBridge 171:3a7713b1edbc 14616 * Offset: 0x1C UART Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 14617 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14618 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14619 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14620 * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14621 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
AnnaBridge 171:3a7713b1edbc 14622 * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14623 * | | |0 = No RDA interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14624 * | | |1 = RDA interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14625 * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
AnnaBridge 171:3a7713b1edbc 14626 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14627 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
AnnaBridge 171:3a7713b1edbc 14628 * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14629 * | | |0 = No THRE interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14630 * | | |1 = THRE interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14631 * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
AnnaBridge 171:3a7713b1edbc 14632 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14633 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
AnnaBridge 171:3a7713b1edbc 14634 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14635 * | | |0 = No RLS interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14636 * | | |1 = RLS interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14637 * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
AnnaBridge 171:3a7713b1edbc 14638 * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
AnnaBridge 171:3a7713b1edbc 14639 * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
AnnaBridge 171:3a7713b1edbc 14640 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
AnnaBridge 171:3a7713b1edbc 14641 * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14642 * | | |0 = No Modem interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14643 * | | |1 = Modem interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14644 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
AnnaBridge 171:3a7713b1edbc 14645 * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14646 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
AnnaBridge 171:3a7713b1edbc 14647 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14648 * | | |0 = No Time-out interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14649 * | | |1 = Time-out interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14650 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
AnnaBridge 171:3a7713b1edbc 14651 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14652 * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
AnnaBridge 171:3a7713b1edbc 14653 * | | |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
AnnaBridge 171:3a7713b1edbc 14654 * | | |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14655 * | | |0 = No buffer error interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14656 * | | |1 = Buffer error interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14657 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 14658 * | | |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
AnnaBridge 171:3a7713b1edbc 14659 * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14660 * | | |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
AnnaBridge 171:3a7713b1edbc 14661 * | | |0 = No DATWKIF and CTSWKIF are generated.
AnnaBridge 171:3a7713b1edbc 14662 * | | |1 = DATWKIF or CTSWKIF.
AnnaBridge 171:3a7713b1edbc 14663 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 14664 * | | |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
AnnaBridge 171:3a7713b1edbc 14665 * |[7] |LINIF |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
AnnaBridge 171:3a7713b1edbc 14666 * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
AnnaBridge 171:3a7713b1edbc 14667 * | | |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14668 * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
AnnaBridge 171:3a7713b1edbc 14669 * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
AnnaBridge 171:3a7713b1edbc 14670 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 14671 * | | |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
AnnaBridge 171:3a7713b1edbc 14672 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14673 * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14674 * | | |0 = No RDA interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14675 * | | |1 = RDA interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14676 * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14677 * | | |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14678 * | | |0 = No DATE interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14679 * | | |1 = DATE interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14680 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14681 * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14682 * | | |0 = No RLS interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14683 * | | |1 = RLS interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14684 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14685 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
AnnaBridge 171:3a7713b1edbc 14686 * | | |0 = No Modem interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14687 * | | |1 = Modem interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14688 * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14689 * | | |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14690 * | | |0 = No Tout interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14691 * | | |1 = Tout interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14692 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14693 * | | |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14694 * | | |0 = No buffer error interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14695 * | | |1 = Buffer error interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14696 * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
AnnaBridge 171:3a7713b1edbc 14697 * | | |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14698 * | | |0 = No LIN Bus interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14699 * | | |1 = The LIN Bus interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14700 * |[16] |CTSWKIF |nCTS Wake-Up Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14701 * | | |0 = Chip stays in power-down state.
AnnaBridge 171:3a7713b1edbc 14702 * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
AnnaBridge 171:3a7713b1edbc 14703 * | | |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14704 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14705 * |[17] |DATWKIF |Data Wake-Up Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14706 * | | |This bit is set if chip wake-up from power-down state by data wake-up.
AnnaBridge 171:3a7713b1edbc 14707 * | | |0 = Chip stays in power-down state.
AnnaBridge 171:3a7713b1edbc 14708 * | | |1 = Chip wake-up from power-down state by data wake-up.
AnnaBridge 171:3a7713b1edbc 14709 * | | |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
AnnaBridge 171:3a7713b1edbc 14710 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
AnnaBridge 171:3a7713b1edbc 14711 * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14712 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
AnnaBridge 171:3a7713b1edbc 14713 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14714 * | | |0 = No RLS interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14715 * | | |1 = RLS interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14716 * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
AnnaBridge 171:3a7713b1edbc 14717 * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
AnnaBridge 171:3a7713b1edbc 14718 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
AnnaBridge 171:3a7713b1edbc 14719 * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14720 * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
AnnaBridge 171:3a7713b1edbc 14721 * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14722 * | | |0 = No Modem interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14723 * | | |1 = Modem interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14724 * | | |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
AnnaBridge 171:3a7713b1edbc 14725 * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14726 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
AnnaBridge 171:3a7713b1edbc 14727 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14728 * | | |0 = No Time-out interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14729 * | | |1 = Time-out interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14730 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
AnnaBridge 171:3a7713b1edbc 14731 * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14732 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
AnnaBridge 171:3a7713b1edbc 14733 * | | |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
AnnaBridge 171:3a7713b1edbc 14734 * | | |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14735 * | | |0 = No buffer error interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14736 * | | |1 = Buffer error interrupt flag is generated.
AnnaBridge 171:3a7713b1edbc 14737 * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
AnnaBridge 171:3a7713b1edbc 14738 * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14739 * | | |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14740 * | | |0 = No RLS interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14741 * | | |1 = RLS interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14742 * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14743 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14744 * | | |0 = No Modem interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14745 * | | |1 = Modem interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14746 * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14747 * | | |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
AnnaBridge 171:3a7713b1edbc 14748 * | | |0 = No Tout interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14749 * | | |1 = Tout interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14750 * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
AnnaBridge 171:3a7713b1edbc 14751 * | | |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
AnnaBridge 171:3a7713b1edbc 14752 * | | |0 = No buffer error interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14753 * | | |1 = Buffer error interrupt is generated in DMA mode.
AnnaBridge 171:3a7713b1edbc 14754 * @var UART_T::TOUT
AnnaBridge 171:3a7713b1edbc 14755 * Offset: 0x20 UART Time-out Register
AnnaBridge 171:3a7713b1edbc 14756 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14757 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14758 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14759 * |[7:0] |TOIC |Time-Out Interrupt Comparator
AnnaBridge 171:3a7713b1edbc 14760 * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
AnnaBridge 171:3a7713b1edbc 14761 * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
AnnaBridge 171:3a7713b1edbc 14762 * | | |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
AnnaBridge 171:3a7713b1edbc 14763 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
AnnaBridge 171:3a7713b1edbc 14764 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
AnnaBridge 171:3a7713b1edbc 14765 * |[15:8] |DLY |TX Delay Time Value
AnnaBridge 171:3a7713b1edbc 14766 * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.
AnnaBridge 171:3a7713b1edbc 14767 * | | |The unit is bit time.
AnnaBridge 171:3a7713b1edbc 14768 * @var UART_T::BAUD
AnnaBridge 171:3a7713b1edbc 14769 * Offset: 0x24 UART Baud Rate Divisor Register
AnnaBridge 171:3a7713b1edbc 14770 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14771 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14772 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14773 * |[15:0] |BRD |Baud Rate Divider
AnnaBridge 171:3a7713b1edbc 14774 * | | |The field indicates the baud rate divider.
AnnaBridge 171:3a7713b1edbc 14775 * | | |This filed is used in baud rate calculation.
AnnaBridge 171:3a7713b1edbc 14776 * | | |The detail description is shown in Table 6.21-2.
AnnaBridge 171:3a7713b1edbc 14777 * |[27:24] |EDIVM1 |Extra Divider For BAUD Rate Mode 1
AnnaBridge 171:3a7713b1edbc 14778 * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
AnnaBridge 171:3a7713b1edbc 14779 * | | |The detail description is shown in Table 6.21-2.
AnnaBridge 171:3a7713b1edbc 14780 * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
AnnaBridge 171:3a7713b1edbc 14781 * | | |This bit is baud rate mode selection bit 0.
AnnaBridge 171:3a7713b1edbc 14782 * | | |UART provides three baud rate calculation modes.
AnnaBridge 171:3a7713b1edbc 14783 * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
AnnaBridge 171:3a7713b1edbc 14784 * | | |The detail description is shown in Table 6.21-2.
AnnaBridge 171:3a7713b1edbc 14785 * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
AnnaBridge 171:3a7713b1edbc 14786 * | | |This bit is baud rate mode selection bit 1.
AnnaBridge 171:3a7713b1edbc 14787 * | | |UART provides three baud rate calculation modes.
AnnaBridge 171:3a7713b1edbc 14788 * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
AnnaBridge 171:3a7713b1edbc 14789 * | | |The detail description is shown in Table 6.21-2.
AnnaBridge 171:3a7713b1edbc 14790 * | | |Note: In IrDA mode must be operated in mode 0.
AnnaBridge 171:3a7713b1edbc 14791 * @var UART_T::IRDA
AnnaBridge 171:3a7713b1edbc 14792 * Offset: 0x28 UART IrDA Control Register
AnnaBridge 171:3a7713b1edbc 14793 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14794 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14795 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14796 * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
AnnaBridge 171:3a7713b1edbc 14797 * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
AnnaBridge 171:3a7713b1edbc 14798 * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
AnnaBridge 171:3a7713b1edbc 14799 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
AnnaBridge 171:3a7713b1edbc 14800 * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
AnnaBridge 171:3a7713b1edbc 14801 * | | |0 = None inverse transmitting signal. (Default)
AnnaBridge 171:3a7713b1edbc 14802 * | | |1 = Inverse transmitting output signal.
AnnaBridge 171:3a7713b1edbc 14803 * |[6] |RXINV |IrDA Inverse Receive Input Signal
AnnaBridge 171:3a7713b1edbc 14804 * | | |0 = None inverse receiving input signal.
AnnaBridge 171:3a7713b1edbc 14805 * | | |1 = Inverse receiving input signal. (Default)
AnnaBridge 171:3a7713b1edbc 14806 * @var UART_T::ALTCTL
AnnaBridge 171:3a7713b1edbc 14807 * Offset: 0x2C UART Alternate Control/Status Register
AnnaBridge 171:3a7713b1edbc 14808 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14809 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14810 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14811 * |[3:0] |BRKFL |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
AnnaBridge 171:3a7713b1edbc 14812 * | | |This field indicates a 4-bit LIN TX break field count.
AnnaBridge 171:3a7713b1edbc 14813 * | | |Note1: This break field length is BRKFL + 1
AnnaBridge 171:3a7713b1edbc 14814 * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
AnnaBridge 171:3a7713b1edbc 14815 * |[6] |LINRXEN |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
AnnaBridge 171:3a7713b1edbc 14816 * | | |0 = LIN RX mode Disabled.
AnnaBridge 171:3a7713b1edbc 14817 * | | |1 = LIN RX mode Enabled.
AnnaBridge 171:3a7713b1edbc 14818 * |[7] |LINTXEN |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
AnnaBridge 171:3a7713b1edbc 14819 * | | |0 = LIN TX Break mode Disabled.
AnnaBridge 171:3a7713b1edbc 14820 * | | |1 = LIN TX Break mode Enabled.
AnnaBridge 171:3a7713b1edbc 14821 * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 14822 * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
AnnaBridge 171:3a7713b1edbc 14823 * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
AnnaBridge 171:3a7713b1edbc 14824 * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
AnnaBridge 171:3a7713b1edbc 14825 * | | |Note: It cannot be active with RS-485_AAD operation mode.
AnnaBridge 171:3a7713b1edbc 14826 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
AnnaBridge 171:3a7713b1edbc 14827 * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
AnnaBridge 171:3a7713b1edbc 14828 * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
AnnaBridge 171:3a7713b1edbc 14829 * | | |Note: It cannot be active with RS-485_NMM operation mode.
AnnaBridge 171:3a7713b1edbc 14830 * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
AnnaBridge 171:3a7713b1edbc 14831 * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
AnnaBridge 171:3a7713b1edbc 14832 * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
AnnaBridge 171:3a7713b1edbc 14833 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
AnnaBridge 171:3a7713b1edbc 14834 * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 14835 * | | |This bit is used to enable RS-485 Address Detection mode.
AnnaBridge 171:3a7713b1edbc 14836 * | | |0 = Address detection mode Disabled.
AnnaBridge 171:3a7713b1edbc 14837 * | | |1 = Address detection mode Enabled.
AnnaBridge 171:3a7713b1edbc 14838 * | | |Note: This bit is used for RS-485 any operation mode.
AnnaBridge 171:3a7713b1edbc 14839 * |[17] |ABRIF |Auto-Baud Rate Interrupt Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14840 * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14841 * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
AnnaBridge 171:3a7713b1edbc 14842 * |[18] |ABRDEN |Auto-Baud Rate Detect Enable Bit
AnnaBridge 171:3a7713b1edbc 14843 * | | |0 = Auto-baud rate detect function Disabled.
AnnaBridge 171:3a7713b1edbc 14844 * | | |1 = Auto-baud rate detect function Enabled.
AnnaBridge 171:3a7713b1edbc 14845 * | | |This bit is cleared automatically after auto-baud detection is finished.
AnnaBridge 171:3a7713b1edbc 14846 * |[20:19] |ABRDBITS |Auto-Baud Rate Detect Bit Length
AnnaBridge 171:3a7713b1edbc 14847 * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
AnnaBridge 171:3a7713b1edbc 14848 * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
AnnaBridge 171:3a7713b1edbc 14849 * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
AnnaBridge 171:3a7713b1edbc 14850 * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
AnnaBridge 171:3a7713b1edbc 14851 * | | |Note : The calculation of bit number includes the START bit.
AnnaBridge 171:3a7713b1edbc 14852 * |[31:24] |ADDRMV |Address Match Value
AnnaBridge 171:3a7713b1edbc 14853 * | | |This field contains the RS-485 address match values.
AnnaBridge 171:3a7713b1edbc 14854 * | | |Note: This field is used for RS-485 auto address detection mode.
AnnaBridge 171:3a7713b1edbc 14855 * @var UART_T::FUNCSEL
AnnaBridge 171:3a7713b1edbc 14856 * Offset: 0x30 UART Function Select Register
AnnaBridge 171:3a7713b1edbc 14857 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14858 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14859 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14860 * |[1:0] |FUNCSEL |Function Select
AnnaBridge 171:3a7713b1edbc 14861 * | | |00 = UART function.
AnnaBridge 171:3a7713b1edbc 14862 * | | |01 = LIN function (Only Available in UART0/UART1 Channel).
AnnaBridge 171:3a7713b1edbc 14863 * | | |10 = IrDA function.
AnnaBridge 171:3a7713b1edbc 14864 * | | |11 = RS-485 function.
AnnaBridge 171:3a7713b1edbc 14865 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
AnnaBridge 171:3a7713b1edbc 14866 * @var UART_T::LINCTL
AnnaBridge 171:3a7713b1edbc 14867 * Offset: 0x34 UART LIN Control Register
AnnaBridge 171:3a7713b1edbc 14868 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14869 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14870 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14871 * |[0] |SLVEN |LIN Slave Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 14872 * | | |0 = LIN slave mode Disabled.
AnnaBridge 171:3a7713b1edbc 14873 * | | |1 = LIN slave mode Enabled.
AnnaBridge 171:3a7713b1edbc 14874 * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 14875 * | | |0 = LIN slave header detection Disabled.
AnnaBridge 171:3a7713b1edbc 14876 * | | |1 = LIN slave header detection Enabled.
AnnaBridge 171:3a7713b1edbc 14877 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
AnnaBridge 171:3a7713b1edbc 14878 * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
AnnaBridge 171:3a7713b1edbc 14879 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14880 * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 14881 * | | |0 = LIN automatic resynchronization Disabled.
AnnaBridge 171:3a7713b1edbc 14882 * | | |1 = LIN automatic resynchronization Enabled.
AnnaBridge 171:3a7713b1edbc 14883 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
AnnaBridge 171:3a7713b1edbc 14884 * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
AnnaBridge 171:3a7713b1edbc 14885 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
AnnaBridge 171:3a7713b1edbc 14886 * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
AnnaBridge 171:3a7713b1edbc 14887 * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
AnnaBridge 171:3a7713b1edbc 14888 * | | |1 = UART_BAUD is updated at the next received character.
AnnaBridge 171:3a7713b1edbc 14889 * | | |User must set the bit before checksum reception.
AnnaBridge 171:3a7713b1edbc 14890 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
AnnaBridge 171:3a7713b1edbc 14891 * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
AnnaBridge 171:3a7713b1edbc 14892 * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
AnnaBridge 171:3a7713b1edbc 14893 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
AnnaBridge 171:3a7713b1edbc 14894 * |[4] |MUTE |LIN Mute Mode Enable Bit
AnnaBridge 171:3a7713b1edbc 14895 * | | |0 = LIN mute mode Disabled.
AnnaBridge 171:3a7713b1edbc 14896 * | | |1 = LIN mute mode Enabled.
AnnaBridge 171:3a7713b1edbc 14897 * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
AnnaBridge 171:3a7713b1edbc 14898 * |[8] |SENDH |LIN TX Send Header Enable Bit
AnnaBridge 171:3a7713b1edbc 14899 * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
AnnaBridge 171:3a7713b1edbc 14900 * | | |0 = Send LIN TX header Disabled.
AnnaBridge 171:3a7713b1edbc 14901 * | | |1 = Send LIN TX header Enabled.
AnnaBridge 171:3a7713b1edbc 14902 * | | |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
AnnaBridge 171:3a7713b1edbc 14903 * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
AnnaBridge 171:3a7713b1edbc 14904 * |[9] |IDPEN |LIN ID Parity Enable Bit
AnnaBridge 171:3a7713b1edbc 14905 * | | |0 = LIN frame ID parity Disabled.
AnnaBridge 171:3a7713b1edbc 14906 * | | |1 = LIN frame ID parity Enabled.
AnnaBridge 171:3a7713b1edbc 14907 * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
AnnaBridge 171:3a7713b1edbc 14908 * | | |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
AnnaBridge 171:3a7713b1edbc 14909 * |[10] |BRKDETEN |LIN Break Detection Enable Bit
AnnaBridge 171:3a7713b1edbc 14910 * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
AnnaBridge 171:3a7713b1edbc 14911 * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14912 * | | |0 = LIN break detection Disabled .
AnnaBridge 171:3a7713b1edbc 14913 * | | |1 = LIN break detection Enabled.
AnnaBridge 171:3a7713b1edbc 14914 * |[11] |RXOFF |LIN Receiver Disable Bit
AnnaBridge 171:3a7713b1edbc 14915 * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0),
AnnaBridge 171:3a7713b1edbc 14916 * | | |all received byte data will be accepted and stored in the RX-FIFO,
AnnaBridge 171:3a7713b1edbc 14917 * | | |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
AnnaBridge 171:3a7713b1edbc 14918 * | | |0 = LIN receiver Enabled.
AnnaBridge 171:3a7713b1edbc 14919 * | | |1 = LIN receiver Disabled.
AnnaBridge 171:3a7713b1edbc 14920 * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
AnnaBridge 171:3a7713b1edbc 14921 * |[12] |BITERREN |Bit Error Detect Enable Bit
AnnaBridge 171:3a7713b1edbc 14922 * | | |0 = Bit error detection function Disabled.
AnnaBridge 171:3a7713b1edbc 14923 * | | |1 = Bit error detection Enabled.
AnnaBridge 171:3a7713b1edbc 14924 * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
AnnaBridge 171:3a7713b1edbc 14925 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14926 * |[19:16] |BRKFL |LIN Break Field Length
AnnaBridge 171:3a7713b1edbc 14927 * | | |This field indicates a 4-bit LIN TX break field count.
AnnaBridge 171:3a7713b1edbc 14928 * | | |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
AnnaBridge 171:3a7713b1edbc 14929 * | | |Note2: This break field length is BRKFL + 1.
AnnaBridge 171:3a7713b1edbc 14930 * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
AnnaBridge 171:3a7713b1edbc 14931 * |[21:20] |BSL |LIN Break/Sync Delimiter Length
AnnaBridge 171:3a7713b1edbc 14932 * | | |00 = The LIN break/sync delimiter length is 1-bit time.
AnnaBridge 171:3a7713b1edbc 14933 * | | |01 = The LIN break/sync delimiter length is 2-bit time.
AnnaBridge 171:3a7713b1edbc 14934 * | | |10 = The LIN break/sync delimiter length is 3-bit time.
AnnaBridge 171:3a7713b1edbc 14935 * | | |11 = The LIN break/sync delimiter length is 4-bit time.
AnnaBridge 171:3a7713b1edbc 14936 * | | |Note: This bit used for LIN master to sending header field.
AnnaBridge 171:3a7713b1edbc 14937 * |[23:22] |HSEL |LIN Header Select
AnnaBridge 171:3a7713b1edbc 14938 * | | |00 = The LIN header includes "break field".
AnnaBridge 171:3a7713b1edbc 14939 * | | |01 = The LIN header includes "break field" and "sync field".
AnnaBridge 171:3a7713b1edbc 14940 * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field".
AnnaBridge 171:3a7713b1edbc 14941 * | | |11 = Reserved.
AnnaBridge 171:3a7713b1edbc 14942 * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
AnnaBridge 171:3a7713b1edbc 14943 * |[31:24] |PID |LIN PID Bits
AnnaBridge 171:3a7713b1edbc 14944 * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
AnnaBridge 171:3a7713b1edbc 14945 * | | |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
AnnaBridge 171:3a7713b1edbc 14946 * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
AnnaBridge 171:3a7713b1edbc 14947 * | | |Note2: This field can be used for LIN master mode or slave mode.
AnnaBridge 171:3a7713b1edbc 14948 * @var UART_T::LINSTS
AnnaBridge 171:3a7713b1edbc 14949 * Offset: 0x38 UART LIN Status Register
AnnaBridge 171:3a7713b1edbc 14950 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14951 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 14952 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 14953 * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14954 * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14955 * | | |0 = LIN header not detected.
AnnaBridge 171:3a7713b1edbc 14956 * | | |1 = LIN header detected (break + sync + frame ID).
AnnaBridge 171:3a7713b1edbc 14957 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14958 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
AnnaBridge 171:3a7713b1edbc 14959 * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
AnnaBridge 171:3a7713b1edbc 14960 * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14961 * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14962 * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
AnnaBridge 171:3a7713b1edbc 14963 * | | |0 = LIN header error not detected.
AnnaBridge 171:3a7713b1edbc 14964 * | | |1 = LIN header error detected.
AnnaBridge 171:3a7713b1edbc 14965 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14966 * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
AnnaBridge 171:3a7713b1edbc 14967 * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
AnnaBridge 171:3a7713b1edbc 14968 * | | |This bit is set by hardware when receipted frame ID parity is not correct.
AnnaBridge 171:3a7713b1edbc 14969 * | | |0 = No active.
AnnaBridge 171:3a7713b1edbc 14970 * | | |1 = Receipted frame ID parity is not correct.
AnnaBridge 171:3a7713b1edbc 14971 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14972 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
AnnaBridge 171:3a7713b1edbc 14973 * |[3] |SLVSYNCF |LIN Slave Sync Field (Read Only)
AnnaBridge 171:3a7713b1edbc 14974 * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
AnnaBridge 171:3a7713b1edbc 14975 * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
AnnaBridge 171:3a7713b1edbc 14976 * | | |0 = The current character is not at LIN sync state.
AnnaBridge 171:3a7713b1edbc 14977 * | | |1 = The current character is at LIN sync state.
AnnaBridge 171:3a7713b1edbc 14978 * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
AnnaBridge 171:3a7713b1edbc 14979 * | | |Note2: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14980 * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
AnnaBridge 171:3a7713b1edbc 14981 * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14982 * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
AnnaBridge 171:3a7713b1edbc 14983 * | | |0 = LIN break not detected.
AnnaBridge 171:3a7713b1edbc 14984 * | | |1 = LIN break detected.
AnnaBridge 171:3a7713b1edbc 14985 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14986 * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
AnnaBridge 171:3a7713b1edbc 14987 * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
AnnaBridge 171:3a7713b1edbc 14988 * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
AnnaBridge 171:3a7713b1edbc 14989 * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
AnnaBridge 171:3a7713b1edbc 14990 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 14991 * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
AnnaBridge 171:3a7713b1edbc 14992 */
AnnaBridge 171:3a7713b1edbc 14993
AnnaBridge 171:3a7713b1edbc 14994 __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
AnnaBridge 171:3a7713b1edbc 14995 __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 14996 __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 14997 __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
AnnaBridge 171:3a7713b1edbc 14998 __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
AnnaBridge 171:3a7713b1edbc 14999 __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
AnnaBridge 171:3a7713b1edbc 15000 __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 15001 __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 15002 __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
AnnaBridge 171:3a7713b1edbc 15003 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
AnnaBridge 171:3a7713b1edbc 15004 __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
AnnaBridge 171:3a7713b1edbc 15005 __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
AnnaBridge 171:3a7713b1edbc 15006 __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
AnnaBridge 171:3a7713b1edbc 15007 __IO uint32_t LINCTL; /* Offset: 0x34 UART LIN Control Register */
AnnaBridge 171:3a7713b1edbc 15008 __IO uint32_t LINSTS; /* Offset: 0x38 UART LIN Status Register */
AnnaBridge 171:3a7713b1edbc 15009
AnnaBridge 171:3a7713b1edbc 15010 } UART_T;
AnnaBridge 171:3a7713b1edbc 15011
AnnaBridge 171:3a7713b1edbc 15012
AnnaBridge 171:3a7713b1edbc 15013
AnnaBridge 171:3a7713b1edbc 15014 /**
AnnaBridge 171:3a7713b1edbc 15015 @addtogroup UART_CONST UART Bit Field Definition
AnnaBridge 171:3a7713b1edbc 15016 Constant Definitions for UART Controller
AnnaBridge 171:3a7713b1edbc 15017 @{ */
AnnaBridge 171:3a7713b1edbc 15018
AnnaBridge 171:3a7713b1edbc 15019 #define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
AnnaBridge 171:3a7713b1edbc 15020 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
AnnaBridge 171:3a7713b1edbc 15021
AnnaBridge 171:3a7713b1edbc 15022 #define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
AnnaBridge 171:3a7713b1edbc 15023 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
AnnaBridge 171:3a7713b1edbc 15024
AnnaBridge 171:3a7713b1edbc 15025 #define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
AnnaBridge 171:3a7713b1edbc 15026 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
AnnaBridge 171:3a7713b1edbc 15027
AnnaBridge 171:3a7713b1edbc 15028 #define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
AnnaBridge 171:3a7713b1edbc 15029 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
AnnaBridge 171:3a7713b1edbc 15030
AnnaBridge 171:3a7713b1edbc 15031 #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
AnnaBridge 171:3a7713b1edbc 15032 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
AnnaBridge 171:3a7713b1edbc 15033
AnnaBridge 171:3a7713b1edbc 15034 #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
AnnaBridge 171:3a7713b1edbc 15035 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
AnnaBridge 171:3a7713b1edbc 15036
AnnaBridge 171:3a7713b1edbc 15037 #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
AnnaBridge 171:3a7713b1edbc 15038 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
AnnaBridge 171:3a7713b1edbc 15039
AnnaBridge 171:3a7713b1edbc 15040 #define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
AnnaBridge 171:3a7713b1edbc 15041 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
AnnaBridge 171:3a7713b1edbc 15042
AnnaBridge 171:3a7713b1edbc 15043 #define UART_INTEN_WKCTSIEN_Pos (9) /*!< UART_T::INTEN: WKCTSIEN Position */
AnnaBridge 171:3a7713b1edbc 15044 #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART_T::INTEN: WKCTSIEN Mask */
AnnaBridge 171:3a7713b1edbc 15045
AnnaBridge 171:3a7713b1edbc 15046 #define UART_INTEN_WKDATIEN_Pos (10) /*!< UART_T::INTEN: WKDATIEN Position */
AnnaBridge 171:3a7713b1edbc 15047 #define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) /*!< UART_T::INTEN: WKDATIEN Mask */
AnnaBridge 171:3a7713b1edbc 15048
AnnaBridge 171:3a7713b1edbc 15049 #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
AnnaBridge 171:3a7713b1edbc 15050 #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
AnnaBridge 171:3a7713b1edbc 15051
AnnaBridge 171:3a7713b1edbc 15052 #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
AnnaBridge 171:3a7713b1edbc 15053 #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
AnnaBridge 171:3a7713b1edbc 15054
AnnaBridge 171:3a7713b1edbc 15055 #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
AnnaBridge 171:3a7713b1edbc 15056 #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
AnnaBridge 171:3a7713b1edbc 15057
AnnaBridge 171:3a7713b1edbc 15058 #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
AnnaBridge 171:3a7713b1edbc 15059 #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
AnnaBridge 171:3a7713b1edbc 15060
AnnaBridge 171:3a7713b1edbc 15061 #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
AnnaBridge 171:3a7713b1edbc 15062 #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
AnnaBridge 171:3a7713b1edbc 15063
AnnaBridge 171:3a7713b1edbc 15064 #define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
AnnaBridge 171:3a7713b1edbc 15065 #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
AnnaBridge 171:3a7713b1edbc 15066
AnnaBridge 171:3a7713b1edbc 15067 #define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
AnnaBridge 171:3a7713b1edbc 15068 #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
AnnaBridge 171:3a7713b1edbc 15069
AnnaBridge 171:3a7713b1edbc 15070 #define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
AnnaBridge 171:3a7713b1edbc 15071 #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
AnnaBridge 171:3a7713b1edbc 15072
AnnaBridge 171:3a7713b1edbc 15073 #define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
AnnaBridge 171:3a7713b1edbc 15074 #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
AnnaBridge 171:3a7713b1edbc 15075
AnnaBridge 171:3a7713b1edbc 15076 #define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
AnnaBridge 171:3a7713b1edbc 15077 #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
AnnaBridge 171:3a7713b1edbc 15078
AnnaBridge 171:3a7713b1edbc 15079 #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
AnnaBridge 171:3a7713b1edbc 15080 #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
AnnaBridge 171:3a7713b1edbc 15081
AnnaBridge 171:3a7713b1edbc 15082 #define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
AnnaBridge 171:3a7713b1edbc 15083 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
AnnaBridge 171:3a7713b1edbc 15084
AnnaBridge 171:3a7713b1edbc 15085 #define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
AnnaBridge 171:3a7713b1edbc 15086 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
AnnaBridge 171:3a7713b1edbc 15087
AnnaBridge 171:3a7713b1edbc 15088 #define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
AnnaBridge 171:3a7713b1edbc 15089 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
AnnaBridge 171:3a7713b1edbc 15090
AnnaBridge 171:3a7713b1edbc 15091 #define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
AnnaBridge 171:3a7713b1edbc 15092 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
AnnaBridge 171:3a7713b1edbc 15093
AnnaBridge 171:3a7713b1edbc 15094 #define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
AnnaBridge 171:3a7713b1edbc 15095 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
AnnaBridge 171:3a7713b1edbc 15096
AnnaBridge 171:3a7713b1edbc 15097 #define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
AnnaBridge 171:3a7713b1edbc 15098 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
AnnaBridge 171:3a7713b1edbc 15099
AnnaBridge 171:3a7713b1edbc 15100 #define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
AnnaBridge 171:3a7713b1edbc 15101 #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
AnnaBridge 171:3a7713b1edbc 15102
AnnaBridge 171:3a7713b1edbc 15103 #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
AnnaBridge 171:3a7713b1edbc 15104 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
AnnaBridge 171:3a7713b1edbc 15105
AnnaBridge 171:3a7713b1edbc 15106 #define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
AnnaBridge 171:3a7713b1edbc 15107 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
AnnaBridge 171:3a7713b1edbc 15108
AnnaBridge 171:3a7713b1edbc 15109 #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
AnnaBridge 171:3a7713b1edbc 15110 #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
AnnaBridge 171:3a7713b1edbc 15111
AnnaBridge 171:3a7713b1edbc 15112 #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
AnnaBridge 171:3a7713b1edbc 15113 #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
AnnaBridge 171:3a7713b1edbc 15114
AnnaBridge 171:3a7713b1edbc 15115 #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
AnnaBridge 171:3a7713b1edbc 15116 #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
AnnaBridge 171:3a7713b1edbc 15117
AnnaBridge 171:3a7713b1edbc 15118 #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
AnnaBridge 171:3a7713b1edbc 15119 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
AnnaBridge 171:3a7713b1edbc 15120
AnnaBridge 171:3a7713b1edbc 15121 #define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
AnnaBridge 171:3a7713b1edbc 15122 #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
AnnaBridge 171:3a7713b1edbc 15123
AnnaBridge 171:3a7713b1edbc 15124 #define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
AnnaBridge 171:3a7713b1edbc 15125 #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
AnnaBridge 171:3a7713b1edbc 15126
AnnaBridge 171:3a7713b1edbc 15127 #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
AnnaBridge 171:3a7713b1edbc 15128 #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
AnnaBridge 171:3a7713b1edbc 15129
AnnaBridge 171:3a7713b1edbc 15130 #define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
AnnaBridge 171:3a7713b1edbc 15131 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
AnnaBridge 171:3a7713b1edbc 15132
AnnaBridge 171:3a7713b1edbc 15133 #define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
AnnaBridge 171:3a7713b1edbc 15134 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
AnnaBridge 171:3a7713b1edbc 15135
AnnaBridge 171:3a7713b1edbc 15136 #define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
AnnaBridge 171:3a7713b1edbc 15137 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
AnnaBridge 171:3a7713b1edbc 15138
AnnaBridge 171:3a7713b1edbc 15139 #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
AnnaBridge 171:3a7713b1edbc 15140 #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
AnnaBridge 171:3a7713b1edbc 15141
AnnaBridge 171:3a7713b1edbc 15142 #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 15143 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 15144
AnnaBridge 171:3a7713b1edbc 15145 #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
AnnaBridge 171:3a7713b1edbc 15146 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
AnnaBridge 171:3a7713b1edbc 15147
AnnaBridge 171:3a7713b1edbc 15148 #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
AnnaBridge 171:3a7713b1edbc 15149 #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
AnnaBridge 171:3a7713b1edbc 15150
AnnaBridge 171:3a7713b1edbc 15151 #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
AnnaBridge 171:3a7713b1edbc 15152 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
AnnaBridge 171:3a7713b1edbc 15153
AnnaBridge 171:3a7713b1edbc 15154 #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
AnnaBridge 171:3a7713b1edbc 15155 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
AnnaBridge 171:3a7713b1edbc 15156
AnnaBridge 171:3a7713b1edbc 15157 #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
AnnaBridge 171:3a7713b1edbc 15158 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
AnnaBridge 171:3a7713b1edbc 15159
AnnaBridge 171:3a7713b1edbc 15160 #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
AnnaBridge 171:3a7713b1edbc 15161 #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
AnnaBridge 171:3a7713b1edbc 15162
AnnaBridge 171:3a7713b1edbc 15163 #define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
AnnaBridge 171:3a7713b1edbc 15164 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
AnnaBridge 171:3a7713b1edbc 15165
AnnaBridge 171:3a7713b1edbc 15166 #define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
AnnaBridge 171:3a7713b1edbc 15167 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
AnnaBridge 171:3a7713b1edbc 15168
AnnaBridge 171:3a7713b1edbc 15169 #define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
AnnaBridge 171:3a7713b1edbc 15170 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
AnnaBridge 171:3a7713b1edbc 15171
AnnaBridge 171:3a7713b1edbc 15172 #define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
AnnaBridge 171:3a7713b1edbc 15173 #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
AnnaBridge 171:3a7713b1edbc 15174
AnnaBridge 171:3a7713b1edbc 15175 #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
AnnaBridge 171:3a7713b1edbc 15176 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
AnnaBridge 171:3a7713b1edbc 15177
AnnaBridge 171:3a7713b1edbc 15178 #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
AnnaBridge 171:3a7713b1edbc 15179 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
AnnaBridge 171:3a7713b1edbc 15180
AnnaBridge 171:3a7713b1edbc 15181 #define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
AnnaBridge 171:3a7713b1edbc 15182 #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
AnnaBridge 171:3a7713b1edbc 15183
AnnaBridge 171:3a7713b1edbc 15184 #define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
AnnaBridge 171:3a7713b1edbc 15185 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
AnnaBridge 171:3a7713b1edbc 15186
AnnaBridge 171:3a7713b1edbc 15187 #define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
AnnaBridge 171:3a7713b1edbc 15188 #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
AnnaBridge 171:3a7713b1edbc 15189
AnnaBridge 171:3a7713b1edbc 15190 #define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
AnnaBridge 171:3a7713b1edbc 15191 #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
AnnaBridge 171:3a7713b1edbc 15192
AnnaBridge 171:3a7713b1edbc 15193 #define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
AnnaBridge 171:3a7713b1edbc 15194 #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
AnnaBridge 171:3a7713b1edbc 15195
AnnaBridge 171:3a7713b1edbc 15196 #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
AnnaBridge 171:3a7713b1edbc 15197 #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
AnnaBridge 171:3a7713b1edbc 15198
AnnaBridge 171:3a7713b1edbc 15199 #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
AnnaBridge 171:3a7713b1edbc 15200 #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
AnnaBridge 171:3a7713b1edbc 15201
AnnaBridge 171:3a7713b1edbc 15202 #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
AnnaBridge 171:3a7713b1edbc 15203 #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
AnnaBridge 171:3a7713b1edbc 15204
AnnaBridge 171:3a7713b1edbc 15205 #define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
AnnaBridge 171:3a7713b1edbc 15206 #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
AnnaBridge 171:3a7713b1edbc 15207
AnnaBridge 171:3a7713b1edbc 15208 #define UART_INTSTS_CTSWKIF_Pos (16) /*!< UART_T::INTSTS: CTSWKIF Position */
AnnaBridge 171:3a7713b1edbc 15209 #define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) /*!< UART_T::INTSTS: CTSWKIF Mask */
AnnaBridge 171:3a7713b1edbc 15210
AnnaBridge 171:3a7713b1edbc 15211 #define UART_INTSTS_DATWKIF_Pos (17) /*!< UART_T::INTSTS: DATWKIF Position */
AnnaBridge 171:3a7713b1edbc 15212 #define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) /*!< UART_T::INTSTS: DATWKIF Mask */
AnnaBridge 171:3a7713b1edbc 15213
AnnaBridge 171:3a7713b1edbc 15214 #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
AnnaBridge 171:3a7713b1edbc 15215 #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
AnnaBridge 171:3a7713b1edbc 15216
AnnaBridge 171:3a7713b1edbc 15217 #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
AnnaBridge 171:3a7713b1edbc 15218 #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
AnnaBridge 171:3a7713b1edbc 15219
AnnaBridge 171:3a7713b1edbc 15220 #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
AnnaBridge 171:3a7713b1edbc 15221 #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
AnnaBridge 171:3a7713b1edbc 15222
AnnaBridge 171:3a7713b1edbc 15223 #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
AnnaBridge 171:3a7713b1edbc 15224 #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
AnnaBridge 171:3a7713b1edbc 15225
AnnaBridge 171:3a7713b1edbc 15226 #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
AnnaBridge 171:3a7713b1edbc 15227 #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
AnnaBridge 171:3a7713b1edbc 15228
AnnaBridge 171:3a7713b1edbc 15229 #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
AnnaBridge 171:3a7713b1edbc 15230 #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
AnnaBridge 171:3a7713b1edbc 15231
AnnaBridge 171:3a7713b1edbc 15232 #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
AnnaBridge 171:3a7713b1edbc 15233 #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
AnnaBridge 171:3a7713b1edbc 15234
AnnaBridge 171:3a7713b1edbc 15235 #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
AnnaBridge 171:3a7713b1edbc 15236 #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
AnnaBridge 171:3a7713b1edbc 15237
AnnaBridge 171:3a7713b1edbc 15238 #define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
AnnaBridge 171:3a7713b1edbc 15239 #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
AnnaBridge 171:3a7713b1edbc 15240
AnnaBridge 171:3a7713b1edbc 15241 #define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
AnnaBridge 171:3a7713b1edbc 15242 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
AnnaBridge 171:3a7713b1edbc 15243
AnnaBridge 171:3a7713b1edbc 15244 #define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
AnnaBridge 171:3a7713b1edbc 15245 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
AnnaBridge 171:3a7713b1edbc 15246
AnnaBridge 171:3a7713b1edbc 15247 #define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
AnnaBridge 171:3a7713b1edbc 15248 #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
AnnaBridge 171:3a7713b1edbc 15249
AnnaBridge 171:3a7713b1edbc 15250 #define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
AnnaBridge 171:3a7713b1edbc 15251 #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
AnnaBridge 171:3a7713b1edbc 15252
AnnaBridge 171:3a7713b1edbc 15253 #define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
AnnaBridge 171:3a7713b1edbc 15254 #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
AnnaBridge 171:3a7713b1edbc 15255
AnnaBridge 171:3a7713b1edbc 15256 #define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
AnnaBridge 171:3a7713b1edbc 15257 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
AnnaBridge 171:3a7713b1edbc 15258
AnnaBridge 171:3a7713b1edbc 15259 #define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
AnnaBridge 171:3a7713b1edbc 15260 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
AnnaBridge 171:3a7713b1edbc 15261
AnnaBridge 171:3a7713b1edbc 15262 #define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
AnnaBridge 171:3a7713b1edbc 15263 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
AnnaBridge 171:3a7713b1edbc 15264
AnnaBridge 171:3a7713b1edbc 15265 #define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
AnnaBridge 171:3a7713b1edbc 15266 #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
AnnaBridge 171:3a7713b1edbc 15267
AnnaBridge 171:3a7713b1edbc 15268 #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
AnnaBridge 171:3a7713b1edbc 15269 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
AnnaBridge 171:3a7713b1edbc 15270
AnnaBridge 171:3a7713b1edbc 15271 #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
AnnaBridge 171:3a7713b1edbc 15272 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
AnnaBridge 171:3a7713b1edbc 15273
AnnaBridge 171:3a7713b1edbc 15274 #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
AnnaBridge 171:3a7713b1edbc 15275 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
AnnaBridge 171:3a7713b1edbc 15276
AnnaBridge 171:3a7713b1edbc 15277 #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
AnnaBridge 171:3a7713b1edbc 15278 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
AnnaBridge 171:3a7713b1edbc 15279
AnnaBridge 171:3a7713b1edbc 15280 #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
AnnaBridge 171:3a7713b1edbc 15281 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
AnnaBridge 171:3a7713b1edbc 15282
AnnaBridge 171:3a7713b1edbc 15283 #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
AnnaBridge 171:3a7713b1edbc 15284 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
AnnaBridge 171:3a7713b1edbc 15285
AnnaBridge 171:3a7713b1edbc 15286 #define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
AnnaBridge 171:3a7713b1edbc 15287 #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
AnnaBridge 171:3a7713b1edbc 15288
AnnaBridge 171:3a7713b1edbc 15289 #define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
AnnaBridge 171:3a7713b1edbc 15290 #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
AnnaBridge 171:3a7713b1edbc 15291
AnnaBridge 171:3a7713b1edbc 15292 #define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
AnnaBridge 171:3a7713b1edbc 15293 #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
AnnaBridge 171:3a7713b1edbc 15294
AnnaBridge 171:3a7713b1edbc 15295 #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
AnnaBridge 171:3a7713b1edbc 15296 #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
AnnaBridge 171:3a7713b1edbc 15297
AnnaBridge 171:3a7713b1edbc 15298 #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
AnnaBridge 171:3a7713b1edbc 15299 #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
AnnaBridge 171:3a7713b1edbc 15300
AnnaBridge 171:3a7713b1edbc 15301 #define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
AnnaBridge 171:3a7713b1edbc 15302 #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
AnnaBridge 171:3a7713b1edbc 15303
AnnaBridge 171:3a7713b1edbc 15304 #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
AnnaBridge 171:3a7713b1edbc 15305 #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
AnnaBridge 171:3a7713b1edbc 15306
AnnaBridge 171:3a7713b1edbc 15307 #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
AnnaBridge 171:3a7713b1edbc 15308 #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
AnnaBridge 171:3a7713b1edbc 15309
AnnaBridge 171:3a7713b1edbc 15310 #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
AnnaBridge 171:3a7713b1edbc 15311 #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
AnnaBridge 171:3a7713b1edbc 15312
AnnaBridge 171:3a7713b1edbc 15313 #define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
AnnaBridge 171:3a7713b1edbc 15314 #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
AnnaBridge 171:3a7713b1edbc 15315
AnnaBridge 171:3a7713b1edbc 15316 #define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
AnnaBridge 171:3a7713b1edbc 15317 #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
AnnaBridge 171:3a7713b1edbc 15318
AnnaBridge 171:3a7713b1edbc 15319 #define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
AnnaBridge 171:3a7713b1edbc 15320 #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
AnnaBridge 171:3a7713b1edbc 15321
AnnaBridge 171:3a7713b1edbc 15322 #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
AnnaBridge 171:3a7713b1edbc 15323 #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
AnnaBridge 171:3a7713b1edbc 15324
AnnaBridge 171:3a7713b1edbc 15325 #define UART_LINCTL_RXOFF_Pos (11) /*!< UART_T::LINCTL: RXOFF Position */
AnnaBridge 171:3a7713b1edbc 15326 #define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART_T::LINCTL: RXOFF Mask */
AnnaBridge 171:3a7713b1edbc 15327
AnnaBridge 171:3a7713b1edbc 15328 #define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
AnnaBridge 171:3a7713b1edbc 15329 #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
AnnaBridge 171:3a7713b1edbc 15330
AnnaBridge 171:3a7713b1edbc 15331 #define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
AnnaBridge 171:3a7713b1edbc 15332 #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
AnnaBridge 171:3a7713b1edbc 15333
AnnaBridge 171:3a7713b1edbc 15334 #define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
AnnaBridge 171:3a7713b1edbc 15335 #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
AnnaBridge 171:3a7713b1edbc 15336
AnnaBridge 171:3a7713b1edbc 15337 #define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
AnnaBridge 171:3a7713b1edbc 15338 #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
AnnaBridge 171:3a7713b1edbc 15339
AnnaBridge 171:3a7713b1edbc 15340 #define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
AnnaBridge 171:3a7713b1edbc 15341 #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
AnnaBridge 171:3a7713b1edbc 15342
AnnaBridge 171:3a7713b1edbc 15343 #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
AnnaBridge 171:3a7713b1edbc 15344 #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
AnnaBridge 171:3a7713b1edbc 15345
AnnaBridge 171:3a7713b1edbc 15346 #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
AnnaBridge 171:3a7713b1edbc 15347 #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
AnnaBridge 171:3a7713b1edbc 15348
AnnaBridge 171:3a7713b1edbc 15349 #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
AnnaBridge 171:3a7713b1edbc 15350 #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
AnnaBridge 171:3a7713b1edbc 15351
AnnaBridge 171:3a7713b1edbc 15352 #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
AnnaBridge 171:3a7713b1edbc 15353 #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
AnnaBridge 171:3a7713b1edbc 15354
AnnaBridge 171:3a7713b1edbc 15355 #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
AnnaBridge 171:3a7713b1edbc 15356 #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
AnnaBridge 171:3a7713b1edbc 15357
AnnaBridge 171:3a7713b1edbc 15358 #define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
AnnaBridge 171:3a7713b1edbc 15359 #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
AnnaBridge 171:3a7713b1edbc 15360
AnnaBridge 171:3a7713b1edbc 15361
AnnaBridge 171:3a7713b1edbc 15362 /**@}*/ /* UART_CONST */
AnnaBridge 171:3a7713b1edbc 15363 /**@}*/ /* end of UART register group */
AnnaBridge 171:3a7713b1edbc 15364
AnnaBridge 171:3a7713b1edbc 15365
AnnaBridge 171:3a7713b1edbc 15366 /*---------------------- Universal Serial Bus Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 15367 /**
AnnaBridge 171:3a7713b1edbc 15368 @addtogroup USB Universal Serial Bus Controller(USB)
AnnaBridge 171:3a7713b1edbc 15369 Memory Mapped Structure for USB Controller
AnnaBridge 171:3a7713b1edbc 15370 @{ */
AnnaBridge 171:3a7713b1edbc 15371
AnnaBridge 171:3a7713b1edbc 15372 /**
AnnaBridge 171:3a7713b1edbc 15373 * @brief USBD endpoints register
AnnaBridge 171:3a7713b1edbc 15374 */
AnnaBridge 171:3a7713b1edbc 15375
AnnaBridge 171:3a7713b1edbc 15376 typedef struct
AnnaBridge 171:3a7713b1edbc 15377 {
AnnaBridge 171:3a7713b1edbc 15378
AnnaBridge 171:3a7713b1edbc 15379
AnnaBridge 171:3a7713b1edbc 15380 /**
AnnaBridge 171:3a7713b1edbc 15381 * @var USBD_EP_T::BUFSEG
AnnaBridge 171:3a7713b1edbc 15382 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register
AnnaBridge 171:3a7713b1edbc 15383 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15384 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15385 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15386 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
AnnaBridge 171:3a7713b1edbc 15387 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
AnnaBridge 171:3a7713b1edbc 15388 * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000}
AnnaBridge 171:3a7713b1edbc 15389 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
AnnaBridge 171:3a7713b1edbc 15390 * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
AnnaBridge 171:3a7713b1edbc 15391 * @var USBD_EP_T::MXPLD
AnnaBridge 171:3a7713b1edbc 15392 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register
AnnaBridge 171:3a7713b1edbc 15393 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15394 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15395 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15396 * |[8:0] |MXPLD |Maximal Payload
AnnaBridge 171:3a7713b1edbc 15397 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
AnnaBridge 171:3a7713b1edbc 15398 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
AnnaBridge 171:3a7713b1edbc 15399 * | | |(1) When the register is written by CPU,
AnnaBridge 171:3a7713b1edbc 15400 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
AnnaBridge 171:3a7713b1edbc 15401 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
AnnaBridge 171:3a7713b1edbc 15402 * | | |(2) When the register is read by CPU,
AnnaBridge 171:3a7713b1edbc 15403 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
AnnaBridge 171:3a7713b1edbc 15404 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
AnnaBridge 171:3a7713b1edbc 15405 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
AnnaBridge 171:3a7713b1edbc 15406 * @var USBD_EP_T::CFG
AnnaBridge 171:3a7713b1edbc 15407 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register
AnnaBridge 171:3a7713b1edbc 15408 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15409 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15410 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15411 * |[3:0] |EPNUM |Endpoint Number
AnnaBridge 171:3a7713b1edbc 15412 * | | |These bits are used to define the endpoint number of the current endpoint.
AnnaBridge 171:3a7713b1edbc 15413 * |[4] |ISOCH |Isochronous Endpoint
AnnaBridge 171:3a7713b1edbc 15414 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
AnnaBridge 171:3a7713b1edbc 15415 * | | |0 = No Isochronous endpoint.
AnnaBridge 171:3a7713b1edbc 15416 * | | |1 = Isochronous endpoint.
AnnaBridge 171:3a7713b1edbc 15417 * |[6:5] |STATE |Endpoint STATE
AnnaBridge 171:3a7713b1edbc 15418 * | | |00 = Endpoint is Disabled.
AnnaBridge 171:3a7713b1edbc 15419 * | | |01 = Out endpoint.
AnnaBridge 171:3a7713b1edbc 15420 * | | |10 = IN endpoint.
AnnaBridge 171:3a7713b1edbc 15421 * | | |11 = Undefined.
AnnaBridge 171:3a7713b1edbc 15422 * |[7] |DSQSYNC |Data Sequence Synchronization
AnnaBridge 171:3a7713b1edbc 15423 * | | |0 = DATA0 PID.
AnnaBridge 171:3a7713b1edbc 15424 * | | |1 = DATA1 PID.
AnnaBridge 171:3a7713b1edbc 15425 * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
AnnaBridge 171:3a7713b1edbc 15426 * | | |Hardware will toggle automatically in IN token base on the bit.
AnnaBridge 171:3a7713b1edbc 15427 * |[9] |CSTALL |Clear STALL Response
AnnaBridge 171:3a7713b1edbc 15428 * | | |0 = Disable the device to clear the STALL handshake in setup stage.
AnnaBridge 171:3a7713b1edbc 15429 * | | |1 = Clear the device to response STALL handshake in setup stage.
AnnaBridge 171:3a7713b1edbc 15430 * @var USBD_EP_T::CFGP
AnnaBridge 171:3a7713b1edbc 15431 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
AnnaBridge 171:3a7713b1edbc 15432 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15433 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15434 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15435 * |[0] |CLRRDY |Clear Ready
AnnaBridge 171:3a7713b1edbc 15436 * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
AnnaBridge 171:3a7713b1edbc 15437 * | | |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
AnnaBridge 171:3a7713b1edbc 15438 * | | |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
AnnaBridge 171:3a7713b1edbc 15439 * | | |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
AnnaBridge 171:3a7713b1edbc 15440 * | | |This bit is write 1 only and is always 0 when it is read back.
AnnaBridge 171:3a7713b1edbc 15441 * |[1] |SSTALL |Set STALL
AnnaBridge 171:3a7713b1edbc 15442 * | | |0 = Disable the device to response STALL.
AnnaBridge 171:3a7713b1edbc 15443 * | | |1 = Set the device to respond STALL automatically.
AnnaBridge 171:3a7713b1edbc 15444 */
AnnaBridge 171:3a7713b1edbc 15445
AnnaBridge 171:3a7713b1edbc 15446 __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
AnnaBridge 171:3a7713b1edbc 15447 __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
AnnaBridge 171:3a7713b1edbc 15448 __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
AnnaBridge 171:3a7713b1edbc 15449 __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
AnnaBridge 171:3a7713b1edbc 15450
AnnaBridge 171:3a7713b1edbc 15451 } USBD_EP_T;
AnnaBridge 171:3a7713b1edbc 15452
AnnaBridge 171:3a7713b1edbc 15453
AnnaBridge 171:3a7713b1edbc 15454
AnnaBridge 171:3a7713b1edbc 15455
AnnaBridge 171:3a7713b1edbc 15456
AnnaBridge 171:3a7713b1edbc 15457 typedef struct
AnnaBridge 171:3a7713b1edbc 15458 {
AnnaBridge 171:3a7713b1edbc 15459
AnnaBridge 171:3a7713b1edbc 15460
AnnaBridge 171:3a7713b1edbc 15461 /**
AnnaBridge 171:3a7713b1edbc 15462 * @var USBD_T::INTEN
AnnaBridge 171:3a7713b1edbc 15463 * Offset: 0x00 USB Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 15464 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15465 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15466 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15467 * |[0] |BUSIEN |Bus Event Interrupt Enable
AnnaBridge 171:3a7713b1edbc 15468 * | | |0 = BUS event interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 15469 * | | |1 = BUS event interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 15470 * |[1] |USBIEN |USB Event Interrupt Enable
AnnaBridge 171:3a7713b1edbc 15471 * | | |0 = USB event interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 15472 * | | |1 = USB event interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 15473 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable
AnnaBridge 171:3a7713b1edbc 15474 * | | |0 = Floating detection Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 15475 * | | |1 = Floating detection Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 15476 * |[3] |NEVWKIEN |USB No-Event-Wake-Up Interrupt Enable
AnnaBridge 171:3a7713b1edbc 15477 * | | |0 = No-Event-Wake-up Interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 15478 * | | |1 = No-Event-Wake-up Interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 15479 * |[8] |WKEN |Wake-Up Function Enable
AnnaBridge 171:3a7713b1edbc 15480 * | | |0 = USB wake-up function Disabled.
AnnaBridge 171:3a7713b1edbc 15481 * | | |1 = USB wake-up function Enabled.
AnnaBridge 171:3a7713b1edbc 15482 * |[15] |INNAKEN |Active NAK Function And Its Status In IN Token
AnnaBridge 171:3a7713b1edbc 15483 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be
AnnaBridge 171:3a7713b1edbc 15484 * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
AnnaBridge 171:3a7713b1edbc 15485 * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
AnnaBridge 171:3a7713b1edbc 15486 * | | | will be asserted, when the device responds NAK after receiving IN token.
AnnaBridge 171:3a7713b1edbc 15487 * @var USBD_T::INTSTS
AnnaBridge 171:3a7713b1edbc 15488 * Offset: 0x04 USB Interrupt Event Status Register
AnnaBridge 171:3a7713b1edbc 15489 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15490 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15491 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15492 * |[0] |BUSIF |BUS Interrupt Status
AnnaBridge 171:3a7713b1edbc 15493 * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
AnnaBridge 171:3a7713b1edbc 15494 * | | |0 = No BUS event occurred.
AnnaBridge 171:3a7713b1edbc 15495 * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
AnnaBridge 171:3a7713b1edbc 15496 * |[1] |USBIF |USB Event Interrupt Status
AnnaBridge 171:3a7713b1edbc 15497 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
AnnaBridge 171:3a7713b1edbc 15498 * | | |0 = No USB event occurred.
AnnaBridge 171:3a7713b1edbc 15499 * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
AnnaBridge 171:3a7713b1edbc 15500 * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
AnnaBridge 171:3a7713b1edbc 15501 * |[2] |VBDETIF |VBUS Detection Interrupt Status
AnnaBridge 171:3a7713b1edbc 15502 * | | |0 = There is not attached/detached event in the USB.
AnnaBridge 171:3a7713b1edbc 15503 * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
AnnaBridge 171:3a7713b1edbc 15504 * |[3] |NEVWKIF |USB No-Event-Wake-Up Interrupt Status
AnnaBridge 171:3a7713b1edbc 15505 * | | |0 = No Wake-up event occurred.
AnnaBridge 171:3a7713b1edbc 15506 * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
AnnaBridge 171:3a7713b1edbc 15507 * |[16] |EPEVT0 |Endpoint 0's USB Event Status
AnnaBridge 171:3a7713b1edbc 15508 * | | |0 = No event occurred on endpoint 0.
AnnaBridge 171:3a7713b1edbc 15509 * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15510 * |[17] |EPEVT1 |Endpoint 1's USB Event Status
AnnaBridge 171:3a7713b1edbc 15511 * | | |0 = No event occurred on endpoint 1.
AnnaBridge 171:3a7713b1edbc 15512 * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15513 * |[18] |EPEVT2 |Endpoint 2's USB Event Status
AnnaBridge 171:3a7713b1edbc 15514 * | | |0 = No event occurred on endpoint 2.
AnnaBridge 171:3a7713b1edbc 15515 * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15516 * |[19] |EPEVT3 |Endpoint 3's USB Event Status
AnnaBridge 171:3a7713b1edbc 15517 * | | |0 = No event occurred on endpoint 3.
AnnaBridge 171:3a7713b1edbc 15518 * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15519 * |[20] |EPEVT4 |Endpoint 4's USB Event Status
AnnaBridge 171:3a7713b1edbc 15520 * | | |0 = No event occurred on endpoint 4.
AnnaBridge 171:3a7713b1edbc 15521 * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15522 * |[21] |EPEVT5 |Endpoint 5's USB Event Status
AnnaBridge 171:3a7713b1edbc 15523 * | | |0 = No event occurred on endpoint 5.
AnnaBridge 171:3a7713b1edbc 15524 * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15525 * |[22] |EPEVT6 |Endpoint 6's USB Event Status
AnnaBridge 171:3a7713b1edbc 15526 * | | |0 = No event occurred on endpoint 6.
AnnaBridge 171:3a7713b1edbc 15527 * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15528 * |[23] |EPEVT7 |Endpoint 7's USB Event Status
AnnaBridge 171:3a7713b1edbc 15529 * | | |0 = No event occurred on endpoint 7.
AnnaBridge 171:3a7713b1edbc 15530 * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
AnnaBridge 171:3a7713b1edbc 15531 * |[31] |SETUP |Setup Event Status
AnnaBridge 171:3a7713b1edbc 15532 * | | |0 = No Setup event.
AnnaBridge 171:3a7713b1edbc 15533 * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
AnnaBridge 171:3a7713b1edbc 15534 * @var USBD_T::FADDR
AnnaBridge 171:3a7713b1edbc 15535 * Offset: 0x08 USB Device Function Address Register
AnnaBridge 171:3a7713b1edbc 15536 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15537 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15538 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15539 * |[6:0] |FADDR |USB Device Function Address
AnnaBridge 171:3a7713b1edbc 15540 * @var USBD_T::EPSTS
AnnaBridge 171:3a7713b1edbc 15541 * Offset: 0x0C USB Endpoint Status Register
AnnaBridge 171:3a7713b1edbc 15542 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15543 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15544 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15545 * |[7] |OV |Overrun
AnnaBridge 171:3a7713b1edbc 15546 * | | |It indicates that the received data is over the maximum payload number or not.
AnnaBridge 171:3a7713b1edbc 15547 * | | |0 = No overrun.
AnnaBridge 171:3a7713b1edbc 15548 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
AnnaBridge 171:3a7713b1edbc 15549 * |[10:8] |EPSTS0 |Endpoint 0 Bus Status
AnnaBridge 171:3a7713b1edbc 15550 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15551 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15552 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15553 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15554 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15555 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15556 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15557 * |[13:11] |EPSTS1 |Endpoint 1 Bus Status
AnnaBridge 171:3a7713b1edbc 15558 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15559 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15560 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15561 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15562 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15563 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15564 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15565 * |[16:14] |EPSTS2 |Endpoint 2 Bus Status
AnnaBridge 171:3a7713b1edbc 15566 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15567 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15568 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15569 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15570 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15571 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15572 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15573 * |[19:17] |EPSTS3 |Endpoint 3 Bus Status
AnnaBridge 171:3a7713b1edbc 15574 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15575 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15576 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15577 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15578 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15579 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15580 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15581 * |[22:20] |EPSTS4 |Endpoint 4 Bus Status
AnnaBridge 171:3a7713b1edbc 15582 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15583 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15584 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15585 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15586 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15587 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15588 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15589 * |[25:23] |EPSTS5 |Endpoint 5 Bus Status
AnnaBridge 171:3a7713b1edbc 15590 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15591 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15592 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15593 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15594 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15595 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15596 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15597 * |[28:26] |EPSTS6 |Endpoint 6 Bus Status
AnnaBridge 171:3a7713b1edbc 15598 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15599 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15600 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15601 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15602 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15603 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15604 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15605 * |[31:29] |EPSTS7 |Endpoint 7 Bus Status
AnnaBridge 171:3a7713b1edbc 15606 * | | |These bits are used to indicate the current status of this endpoint
AnnaBridge 171:3a7713b1edbc 15607 * | | |000 = In ACK.
AnnaBridge 171:3a7713b1edbc 15608 * | | |001 = In NAK.
AnnaBridge 171:3a7713b1edbc 15609 * | | |010 = Out Packet Data0 ACK.
AnnaBridge 171:3a7713b1edbc 15610 * | | |110 = Out Packet Data1 ACK.
AnnaBridge 171:3a7713b1edbc 15611 * | | |011 = Setup ACK.
AnnaBridge 171:3a7713b1edbc 15612 * | | |111 = Isochronous transfer end.
AnnaBridge 171:3a7713b1edbc 15613 * @var USBD_T::ATTR
AnnaBridge 171:3a7713b1edbc 15614 * Offset: 0x10 USB Bus Status and Attribution Register
AnnaBridge 171:3a7713b1edbc 15615 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15616 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15617 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15618 * |[0] |USBRST |USB Reset Status
AnnaBridge 171:3a7713b1edbc 15619 * | | |0 = Bus no reset.
AnnaBridge 171:3a7713b1edbc 15620 * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
AnnaBridge 171:3a7713b1edbc 15621 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 15622 * |[1] |SUSPEND |Suspend Status
AnnaBridge 171:3a7713b1edbc 15623 * | | |0 = Bus no suspend.
AnnaBridge 171:3a7713b1edbc 15624 * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
AnnaBridge 171:3a7713b1edbc 15625 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 15626 * |[2] |RESUME |Resume Status
AnnaBridge 171:3a7713b1edbc 15627 * | | |0 = No bus resume.
AnnaBridge 171:3a7713b1edbc 15628 * | | |1 = Resume from suspend.
AnnaBridge 171:3a7713b1edbc 15629 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 15630 * |[3] |TOUT |Time-Out Status
AnnaBridge 171:3a7713b1edbc 15631 * | | |0 = No time-out.
AnnaBridge 171:3a7713b1edbc 15632 * | | |1 = No Bus response more than 18 bits time.
AnnaBridge 171:3a7713b1edbc 15633 * | | |Note: This bit is read only.
AnnaBridge 171:3a7713b1edbc 15634 * |[4] |PHYEN |PHY Transceiver Function Enable
AnnaBridge 171:3a7713b1edbc 15635 * | | |0 = PHY transceiver function Disabled.
AnnaBridge 171:3a7713b1edbc 15636 * | | |1 = PHY transceiver function Enabled.
AnnaBridge 171:3a7713b1edbc 15637 * |[5] |RWAKEUP |Remote Wake-Up
AnnaBridge 171:3a7713b1edbc 15638 * | | |0 = Release the USB bus from K state.
AnnaBridge 171:3a7713b1edbc 15639 * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
AnnaBridge 171:3a7713b1edbc 15640 * |[7] |USBEN |USB Controller Enable
AnnaBridge 171:3a7713b1edbc 15641 * | | |0 = USB Controller Disabled.
AnnaBridge 171:3a7713b1edbc 15642 * | | |1 = USB Controller Enabled.
AnnaBridge 171:3a7713b1edbc 15643 * |[8] |DPPUEN |Pull-Up Resistor On USB_D+ Enable
AnnaBridge 171:3a7713b1edbc 15644 * | | |0 = Pull-up resistor in USB_D+ pin Disabled.
AnnaBridge 171:3a7713b1edbc 15645 * | | |1 = Pull-up resistor in USB_D+ pin Enabled.
AnnaBridge 171:3a7713b1edbc 15646 * |[9] |PWRDN |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
AnnaBridge 171:3a7713b1edbc 15647 * | | |0 = Power down related circuits of PHY transceiver.
AnnaBridge 171:3a7713b1edbc 15648 * | | |1 = Turn on related circuits of PHY transceiver.
AnnaBridge 171:3a7713b1edbc 15649 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
AnnaBridge 171:3a7713b1edbc 15650 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
AnnaBridge 171:3a7713b1edbc 15651 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
AnnaBridge 171:3a7713b1edbc 15652 * @var USBD_T::VBUSDET
AnnaBridge 171:3a7713b1edbc 15653 * Offset: 0x14 USB Device VBUS Detection Register
AnnaBridge 171:3a7713b1edbc 15654 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15655 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15656 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15657 * |[0] |FLDET |Device VBUS Detected
AnnaBridge 171:3a7713b1edbc 15658 * | | |0 = Controller is not attached into the USB host.
AnnaBridge 171:3a7713b1edbc 15659 * | | |1 =Controller is attached into the BUS.
AnnaBridge 171:3a7713b1edbc 15660 * @var USBD_T::STBUFSEG
AnnaBridge 171:3a7713b1edbc 15661 * Offset: 0x18 Setup Token Buffer Segmentation Register
AnnaBridge 171:3a7713b1edbc 15662 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15663 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15664 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15665 * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation
AnnaBridge 171:3a7713b1edbc 15666 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
AnnaBridge 171:3a7713b1edbc 15667 * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
AnnaBridge 171:3a7713b1edbc 15668 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
AnnaBridge 171:3a7713b1edbc 15669 * | | |Note: It is used for SETUP token only.
AnnaBridge 171:3a7713b1edbc 15670 * @var USBD_T::SE0
AnnaBridge 171:3a7713b1edbc 15671 * Offset: 0x90 USB Drive SE0 Control Register
AnnaBridge 171:3a7713b1edbc 15672 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15673 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15674 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15675 * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus
AnnaBridge 171:3a7713b1edbc 15676 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
AnnaBridge 171:3a7713b1edbc 15677 * | | |0 = None.
AnnaBridge 171:3a7713b1edbc 15678 * | | |1 = Force USB PHY transceiver to drive SE0.
AnnaBridge 171:3a7713b1edbc 15679 * @var USBD_T::EP
AnnaBridge 171:3a7713b1edbc 15680 * Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register
AnnaBridge 171:3a7713b1edbc 15681 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15682 */
AnnaBridge 171:3a7713b1edbc 15683
AnnaBridge 171:3a7713b1edbc 15684 __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 15685 __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
AnnaBridge 171:3a7713b1edbc 15686 __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
AnnaBridge 171:3a7713b1edbc 15687 __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
AnnaBridge 171:3a7713b1edbc 15688 __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
AnnaBridge 171:3a7713b1edbc 15689 __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
AnnaBridge 171:3a7713b1edbc 15690 __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
AnnaBridge 171:3a7713b1edbc 15691 __I uint32_t RESERVE0[29];
AnnaBridge 171:3a7713b1edbc 15692 __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
AnnaBridge 171:3a7713b1edbc 15693 __I uint32_t RESERVE1[283];
AnnaBridge 171:3a7713b1edbc 15694 USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
AnnaBridge 171:3a7713b1edbc 15695
AnnaBridge 171:3a7713b1edbc 15696 } USBD_T;
AnnaBridge 171:3a7713b1edbc 15697
AnnaBridge 171:3a7713b1edbc 15698
AnnaBridge 171:3a7713b1edbc 15699
AnnaBridge 171:3a7713b1edbc 15700 /**
AnnaBridge 171:3a7713b1edbc 15701 @addtogroup USB_CONST USB Bit Field Definition
AnnaBridge 171:3a7713b1edbc 15702 Constant Definitions for USB Controller
AnnaBridge 171:3a7713b1edbc 15703 @{ */
AnnaBridge 171:3a7713b1edbc 15704
AnnaBridge 171:3a7713b1edbc 15705 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
AnnaBridge 171:3a7713b1edbc 15706 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
AnnaBridge 171:3a7713b1edbc 15707
AnnaBridge 171:3a7713b1edbc 15708 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
AnnaBridge 171:3a7713b1edbc 15709 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
AnnaBridge 171:3a7713b1edbc 15710
AnnaBridge 171:3a7713b1edbc 15711 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
AnnaBridge 171:3a7713b1edbc 15712 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
AnnaBridge 171:3a7713b1edbc 15713
AnnaBridge 171:3a7713b1edbc 15714 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
AnnaBridge 171:3a7713b1edbc 15715 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
AnnaBridge 171:3a7713b1edbc 15716
AnnaBridge 171:3a7713b1edbc 15717 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
AnnaBridge 171:3a7713b1edbc 15718 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 15719
AnnaBridge 171:3a7713b1edbc 15720 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
AnnaBridge 171:3a7713b1edbc 15721 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
AnnaBridge 171:3a7713b1edbc 15722
AnnaBridge 171:3a7713b1edbc 15723 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
AnnaBridge 171:3a7713b1edbc 15724 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
AnnaBridge 171:3a7713b1edbc 15725
AnnaBridge 171:3a7713b1edbc 15726 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
AnnaBridge 171:3a7713b1edbc 15727 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
AnnaBridge 171:3a7713b1edbc 15728
AnnaBridge 171:3a7713b1edbc 15729 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
AnnaBridge 171:3a7713b1edbc 15730 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
AnnaBridge 171:3a7713b1edbc 15731
AnnaBridge 171:3a7713b1edbc 15732 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
AnnaBridge 171:3a7713b1edbc 15733 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
AnnaBridge 171:3a7713b1edbc 15734
AnnaBridge 171:3a7713b1edbc 15735 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
AnnaBridge 171:3a7713b1edbc 15736 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
AnnaBridge 171:3a7713b1edbc 15737
AnnaBridge 171:3a7713b1edbc 15738 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
AnnaBridge 171:3a7713b1edbc 15739 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
AnnaBridge 171:3a7713b1edbc 15740
AnnaBridge 171:3a7713b1edbc 15741 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
AnnaBridge 171:3a7713b1edbc 15742 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
AnnaBridge 171:3a7713b1edbc 15743
AnnaBridge 171:3a7713b1edbc 15744 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
AnnaBridge 171:3a7713b1edbc 15745 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
AnnaBridge 171:3a7713b1edbc 15746
AnnaBridge 171:3a7713b1edbc 15747 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
AnnaBridge 171:3a7713b1edbc 15748 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
AnnaBridge 171:3a7713b1edbc 15749
AnnaBridge 171:3a7713b1edbc 15750 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
AnnaBridge 171:3a7713b1edbc 15751 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
AnnaBridge 171:3a7713b1edbc 15752
AnnaBridge 171:3a7713b1edbc 15753 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
AnnaBridge 171:3a7713b1edbc 15754 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
AnnaBridge 171:3a7713b1edbc 15755
AnnaBridge 171:3a7713b1edbc 15756 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
AnnaBridge 171:3a7713b1edbc 15757 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
AnnaBridge 171:3a7713b1edbc 15758
AnnaBridge 171:3a7713b1edbc 15759 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
AnnaBridge 171:3a7713b1edbc 15760 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
AnnaBridge 171:3a7713b1edbc 15761
AnnaBridge 171:3a7713b1edbc 15762 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
AnnaBridge 171:3a7713b1edbc 15763 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
AnnaBridge 171:3a7713b1edbc 15764
AnnaBridge 171:3a7713b1edbc 15765 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
AnnaBridge 171:3a7713b1edbc 15766 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
AnnaBridge 171:3a7713b1edbc 15767
AnnaBridge 171:3a7713b1edbc 15768 #define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
AnnaBridge 171:3a7713b1edbc 15769 #define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
AnnaBridge 171:3a7713b1edbc 15770
AnnaBridge 171:3a7713b1edbc 15771 #define USBD_EPSTS_EPSTS1_Pos (11) /*!< USBD_T::EPSTS: EPSTS1 Position */
AnnaBridge 171:3a7713b1edbc 15772 #define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
AnnaBridge 171:3a7713b1edbc 15773
AnnaBridge 171:3a7713b1edbc 15774 #define USBD_EPSTS_EPSTS2_Pos (14) /*!< USBD_T::EPSTS: EPSTS2 Position */
AnnaBridge 171:3a7713b1edbc 15775 #define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
AnnaBridge 171:3a7713b1edbc 15776
AnnaBridge 171:3a7713b1edbc 15777 #define USBD_EPSTS_EPSTS3_Pos (17) /*!< USBD_T::EPSTS: EPSTS3 Position */
AnnaBridge 171:3a7713b1edbc 15778 #define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
AnnaBridge 171:3a7713b1edbc 15779
AnnaBridge 171:3a7713b1edbc 15780 #define USBD_EPSTS_EPSTS4_Pos (20) /*!< USBD_T::EPSTS: EPSTS4 Position */
AnnaBridge 171:3a7713b1edbc 15781 #define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
AnnaBridge 171:3a7713b1edbc 15782
AnnaBridge 171:3a7713b1edbc 15783 #define USBD_EPSTS_EPSTS5_Pos (23) /*!< USBD_T::EPSTS: EPSTS5 Position */
AnnaBridge 171:3a7713b1edbc 15784 #define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
AnnaBridge 171:3a7713b1edbc 15785
AnnaBridge 171:3a7713b1edbc 15786 #define USBD_EPSTS_EPSTS6_Pos (26) /*!< USBD_T::EPSTS: EPSTS6 Position */
AnnaBridge 171:3a7713b1edbc 15787 #define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) /*!< USBD_T::EPSTS: EPSTS6 Mask */
AnnaBridge 171:3a7713b1edbc 15788
AnnaBridge 171:3a7713b1edbc 15789 #define USBD_EPSTS_EPSTS7_Pos (29) /*!< USBD_T::EPSTS: EPSTS7 Position */
AnnaBridge 171:3a7713b1edbc 15790 #define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) /*!< USBD_T::EPSTS: EPSTS7 Mask */
AnnaBridge 171:3a7713b1edbc 15791
AnnaBridge 171:3a7713b1edbc 15792 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
AnnaBridge 171:3a7713b1edbc 15793 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
AnnaBridge 171:3a7713b1edbc 15794
AnnaBridge 171:3a7713b1edbc 15795 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
AnnaBridge 171:3a7713b1edbc 15796 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
AnnaBridge 171:3a7713b1edbc 15797
AnnaBridge 171:3a7713b1edbc 15798 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
AnnaBridge 171:3a7713b1edbc 15799 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
AnnaBridge 171:3a7713b1edbc 15800
AnnaBridge 171:3a7713b1edbc 15801 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
AnnaBridge 171:3a7713b1edbc 15802 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
AnnaBridge 171:3a7713b1edbc 15803
AnnaBridge 171:3a7713b1edbc 15804 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
AnnaBridge 171:3a7713b1edbc 15805 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
AnnaBridge 171:3a7713b1edbc 15806
AnnaBridge 171:3a7713b1edbc 15807 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
AnnaBridge 171:3a7713b1edbc 15808 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
AnnaBridge 171:3a7713b1edbc 15809
AnnaBridge 171:3a7713b1edbc 15810 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
AnnaBridge 171:3a7713b1edbc 15811 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
AnnaBridge 171:3a7713b1edbc 15812
AnnaBridge 171:3a7713b1edbc 15813 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
AnnaBridge 171:3a7713b1edbc 15814 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
AnnaBridge 171:3a7713b1edbc 15815
AnnaBridge 171:3a7713b1edbc 15816 #define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
AnnaBridge 171:3a7713b1edbc 15817 #define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
AnnaBridge 171:3a7713b1edbc 15818
AnnaBridge 171:3a7713b1edbc 15819 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
AnnaBridge 171:3a7713b1edbc 15820 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
AnnaBridge 171:3a7713b1edbc 15821
AnnaBridge 171:3a7713b1edbc 15822 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
AnnaBridge 171:3a7713b1edbc 15823 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
AnnaBridge 171:3a7713b1edbc 15824
AnnaBridge 171:3a7713b1edbc 15825 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
AnnaBridge 171:3a7713b1edbc 15826 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
AnnaBridge 171:3a7713b1edbc 15827
AnnaBridge 171:3a7713b1edbc 15828 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
AnnaBridge 171:3a7713b1edbc 15829 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
AnnaBridge 171:3a7713b1edbc 15830
AnnaBridge 171:3a7713b1edbc 15831 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
AnnaBridge 171:3a7713b1edbc 15832 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
AnnaBridge 171:3a7713b1edbc 15833
AnnaBridge 171:3a7713b1edbc 15834 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
AnnaBridge 171:3a7713b1edbc 15835 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
AnnaBridge 171:3a7713b1edbc 15836
AnnaBridge 171:3a7713b1edbc 15837 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
AnnaBridge 171:3a7713b1edbc 15838 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
AnnaBridge 171:3a7713b1edbc 15839
AnnaBridge 171:3a7713b1edbc 15840 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
AnnaBridge 171:3a7713b1edbc 15841 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
AnnaBridge 171:3a7713b1edbc 15842
AnnaBridge 171:3a7713b1edbc 15843 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
AnnaBridge 171:3a7713b1edbc 15844 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
AnnaBridge 171:3a7713b1edbc 15845
AnnaBridge 171:3a7713b1edbc 15846 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
AnnaBridge 171:3a7713b1edbc 15847 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
AnnaBridge 171:3a7713b1edbc 15848
AnnaBridge 171:3a7713b1edbc 15849 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
AnnaBridge 171:3a7713b1edbc 15850 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
AnnaBridge 171:3a7713b1edbc 15851
AnnaBridge 171:3a7713b1edbc 15852 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
AnnaBridge 171:3a7713b1edbc 15853 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
AnnaBridge 171:3a7713b1edbc 15854
AnnaBridge 171:3a7713b1edbc 15855 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
AnnaBridge 171:3a7713b1edbc 15856 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
AnnaBridge 171:3a7713b1edbc 15857
AnnaBridge 171:3a7713b1edbc 15858 /**@}*/ /* USB_CONST */
AnnaBridge 171:3a7713b1edbc 15859 /**@}*/ /* end of USB register group */
AnnaBridge 171:3a7713b1edbc 15860
AnnaBridge 171:3a7713b1edbc 15861
AnnaBridge 171:3a7713b1edbc 15862 /*---------------------- USB Host Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 15863 /**
AnnaBridge 171:3a7713b1edbc 15864 @addtogroup USBH USB Host Controller(USBH)
AnnaBridge 171:3a7713b1edbc 15865 Memory Mapped Structure for USBH Controller
AnnaBridge 171:3a7713b1edbc 15866 @{ */
AnnaBridge 171:3a7713b1edbc 15867
AnnaBridge 171:3a7713b1edbc 15868
AnnaBridge 171:3a7713b1edbc 15869 typedef struct
AnnaBridge 171:3a7713b1edbc 15870 {
AnnaBridge 171:3a7713b1edbc 15871
AnnaBridge 171:3a7713b1edbc 15872
AnnaBridge 171:3a7713b1edbc 15873
AnnaBridge 171:3a7713b1edbc 15874
AnnaBridge 171:3a7713b1edbc 15875 /**
AnnaBridge 171:3a7713b1edbc 15876 * @var USBH_T::HcRevision
AnnaBridge 171:3a7713b1edbc 15877 * Offset: 0x00 Host Controller Revision Register
AnnaBridge 171:3a7713b1edbc 15878 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15879 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15880 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15881 * |[7:0] |REV |Revision Number
AnnaBridge 171:3a7713b1edbc 15882 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
AnnaBridge 171:3a7713b1edbc 15883 * | | |Host Controller supports 1.1 specification.
AnnaBridge 171:3a7713b1edbc 15884 * | | |(X.Y = XYh).
AnnaBridge 171:3a7713b1edbc 15885 * @var USBH_T::HcControl
AnnaBridge 171:3a7713b1edbc 15886 * Offset: 0x04 Host Controller Control Register
AnnaBridge 171:3a7713b1edbc 15887 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15888 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15889 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15890 * |[1:0] |CBSR |Control Bulk Service Ratio
AnnaBridge 171:3a7713b1edbc 15891 * | | |This specifies the service ratio between Control and Bulk EDs.
AnnaBridge 171:3a7713b1edbc 15892 * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
AnnaBridge 171:3a7713b1edbc 15893 * | | |The internal count will be retained when crossing the frame boundary.
AnnaBridge 171:3a7713b1edbc 15894 * | | |In case of reset, HCD is responsible for restoring this.
AnnaBridge 171:3a7713b1edbc 15895 * | | |Value.
AnnaBridge 171:3a7713b1edbc 15896 * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
AnnaBridge 171:3a7713b1edbc 15897 * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
AnnaBridge 171:3a7713b1edbc 15898 * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
AnnaBridge 171:3a7713b1edbc 15899 * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
AnnaBridge 171:3a7713b1edbc 15900 * |[2] |PLE |Periodic List Enable Bit
AnnaBridge 171:3a7713b1edbc 15901 * | | |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
AnnaBridge 171:3a7713b1edbc 15902 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
AnnaBridge 171:3a7713b1edbc 15903 * | | |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
AnnaBridge 171:3a7713b1edbc 15904 * | | |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
AnnaBridge 171:3a7713b1edbc 15905 * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
AnnaBridge 171:3a7713b1edbc 15906 * |[3] |IE |Isochronous List Enable Bit
AnnaBridge 171:3a7713b1edbc 15907 * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
AnnaBridge 171:3a7713b1edbc 15908 * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
AnnaBridge 171:3a7713b1edbc 15909 * | | |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
AnnaBridge 171:3a7713b1edbc 15910 * | | |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
AnnaBridge 171:3a7713b1edbc 15911 * |[4] |CLE |Control List Enable Bit
AnnaBridge 171:3a7713b1edbc 15912 * | | |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
AnnaBridge 171:3a7713b1edbc 15913 * | | |1 = Enable processing of the Control list in the next frame.
AnnaBridge 171:3a7713b1edbc 15914 * |[5] |BLE |Bulk List Enable Bit
AnnaBridge 171:3a7713b1edbc 15915 * | | |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
AnnaBridge 171:3a7713b1edbc 15916 * | | |1 = Enable processing of the Bulk list in the next frame.
AnnaBridge 171:3a7713b1edbc 15917 * |[7:6] |HCFS |Host Controller Functional State
AnnaBridge 171:3a7713b1edbc 15918 * | | |This field sets the Host Controller state.
AnnaBridge 171:3a7713b1edbc 15919 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
AnnaBridge 171:3a7713b1edbc 15920 * | | |States are:
AnnaBridge 171:3a7713b1edbc 15921 * | | |00 = USBSUSPEND.
AnnaBridge 171:3a7713b1edbc 15922 * | | |01 = USBRESUME.
AnnaBridge 171:3a7713b1edbc 15923 * | | |10 = USBOPERATIONAL.
AnnaBridge 171:3a7713b1edbc 15924 * | | |11 = USBRESET.
AnnaBridge 171:3a7713b1edbc 15925 * @var USBH_T::HcCommandStatus
AnnaBridge 171:3a7713b1edbc 15926 * Offset: 0x08 Host Controller CMD Status Register
AnnaBridge 171:3a7713b1edbc 15927 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15928 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15929 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15930 * |[0] |HCR |Host Controller Reset
AnnaBridge 171:3a7713b1edbc 15931 * | | |This bit is set to initiate the software reset of Host Controller.
AnnaBridge 171:3a7713b1edbc 15932 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
AnnaBridge 171:3a7713b1edbc 15933 * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
AnnaBridge 171:3a7713b1edbc 15934 * | | |0 = Host Controller is not in software reset state.
AnnaBridge 171:3a7713b1edbc 15935 * | | |1 = Host Controller is in software reset state.
AnnaBridge 171:3a7713b1edbc 15936 * |[1] |CLF |Control List Filled
AnnaBridge 171:3a7713b1edbc 15937 * | | |Set high to indicate there is an active TD on the Control List.
AnnaBridge 171:3a7713b1edbc 15938 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
AnnaBridge 171:3a7713b1edbc 15939 * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
AnnaBridge 171:3a7713b1edbc 15940 * | | |1 = An active TD added or found on the Control list.
AnnaBridge 171:3a7713b1edbc 15941 * |[2] |BLF |Bulk List Filled
AnnaBridge 171:3a7713b1edbc 15942 * | | |Set high to indicate there is an active TD on the Bulk list.
AnnaBridge 171:3a7713b1edbc 15943 * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
AnnaBridge 171:3a7713b1edbc 15944 * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
AnnaBridge 171:3a7713b1edbc 15945 * | | |1 = An active TD added or found on the Bulk list.
AnnaBridge 171:3a7713b1edbc 15946 * |[17:16] |SOC |Schedule Overrun Count
AnnaBridge 171:3a7713b1edbc 15947 * | | |These bits are incremented on each scheduling overrun error.
AnnaBridge 171:3a7713b1edbc 15948 * | | |It is initialized to 00b and wraps around at 11b.
AnnaBridge 171:3a7713b1edbc 15949 * | | |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
AnnaBridge 171:3a7713b1edbc 15950 * @var USBH_T::HcInterruptStatus
AnnaBridge 171:3a7713b1edbc 15951 * Offset: 0x0C Host Controller Interrupt Status Register
AnnaBridge 171:3a7713b1edbc 15952 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15953 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15954 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15955 * |[0] |SO |Scheduling Overrun
AnnaBridge 171:3a7713b1edbc 15956 * | | |Set when the List Processor determines a Schedule Overrun has occurred.
AnnaBridge 171:3a7713b1edbc 15957 * | | |0 = Schedule Overrun didn't occur.
AnnaBridge 171:3a7713b1edbc 15958 * | | |1 = Schedule Overrun has occurred.
AnnaBridge 171:3a7713b1edbc 15959 * |[1] |WDH |Write Back Done Head
AnnaBridge 171:3a7713b1edbc 15960 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
AnnaBridge 171:3a7713b1edbc 15961 * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
AnnaBridge 171:3a7713b1edbc 15962 * | | |0 =.Host Controller didn't update HccaDoneHead.
AnnaBridge 171:3a7713b1edbc 15963 * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
AnnaBridge 171:3a7713b1edbc 15964 * |[2] |SF |Start Of Frame
AnnaBridge 171:3a7713b1edbc 15965 * | | |Set when the Frame Management functional block signals a 'Start of Frame' event.
AnnaBridge 171:3a7713b1edbc 15966 * | | |Host Control generates a SOF token at the same time.
AnnaBridge 171:3a7713b1edbc 15967 * | | |0 =.Not the start of a frame.
AnnaBridge 171:3a7713b1edbc 15968 * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
AnnaBridge 171:3a7713b1edbc 15969 * |[3] |RD |Resume Detected
AnnaBridge 171:3a7713b1edbc 15970 * | | |Set when Host Controller detects resume signaling on a downstream port.
AnnaBridge 171:3a7713b1edbc 15971 * | | |0 = No resume signaling detected on a downstream port.
AnnaBridge 171:3a7713b1edbc 15972 * | | |1 = Resume signaling detected on a downstream port.
AnnaBridge 171:3a7713b1edbc 15973 * |[5] |FNO |Frame Number Overflow
AnnaBridge 171:3a7713b1edbc 15974 * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
AnnaBridge 171:3a7713b1edbc 15975 * | | |0 = The bit 15 of Frame Number didn't change.
AnnaBridge 171:3a7713b1edbc 15976 * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
AnnaBridge 171:3a7713b1edbc 15977 * |[6] |RHSC |Root Hub Status Change
AnnaBridge 171:3a7713b1edbc 15978 * | | |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
AnnaBridge 171:3a7713b1edbc 15979 * | | |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
AnnaBridge 171:3a7713b1edbc 15980 * | | |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
AnnaBridge 171:3a7713b1edbc 15981 * @var USBH_T::HcInterruptEnable
AnnaBridge 171:3a7713b1edbc 15982 * Offset: 0x10 Host Controller Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 15983 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15984 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 15985 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 15986 * |[0] |SO |Scheduling Overrun Enable Bit
AnnaBridge 171:3a7713b1edbc 15987 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 15988 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 15989 * | | |1 = Enable interrupt generation due to SO (HcIntSts[0]).
AnnaBridge 171:3a7713b1edbc 15990 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 15991 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
AnnaBridge 171:3a7713b1edbc 15992 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
AnnaBridge 171:3a7713b1edbc 15993 * |[1] |WDH |Write Back Done Head Enable Bit
AnnaBridge 171:3a7713b1edbc 15994 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 15995 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 15996 * | | |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
AnnaBridge 171:3a7713b1edbc 15997 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 15998 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
AnnaBridge 171:3a7713b1edbc 15999 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
AnnaBridge 171:3a7713b1edbc 16000 * |[2] |SF |Start Of Frame Enable Bit
AnnaBridge 171:3a7713b1edbc 16001 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16002 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16003 * | | |1 = Enable interrupt generation due to SF (HcIntSts[2]).
AnnaBridge 171:3a7713b1edbc 16004 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16005 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
AnnaBridge 171:3a7713b1edbc 16006 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
AnnaBridge 171:3a7713b1edbc 16007 * |[3] |RD |Resume Detected Enable Bit
AnnaBridge 171:3a7713b1edbc 16008 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16009 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16010 * | | |1 = Enable interrupt generation due to RD (HcIntSts[3]).
AnnaBridge 171:3a7713b1edbc 16011 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16012 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
AnnaBridge 171:3a7713b1edbc 16013 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
AnnaBridge 171:3a7713b1edbc 16014 * |[5] |FNO |Frame Number Overflow Enable Bit
AnnaBridge 171:3a7713b1edbc 16015 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16016 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16017 * | | |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
AnnaBridge 171:3a7713b1edbc 16018 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16019 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
AnnaBridge 171:3a7713b1edbc 16020 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
AnnaBridge 171:3a7713b1edbc 16021 * |[6] |RHSC |Root Hub Status Change Enable Bit
AnnaBridge 171:3a7713b1edbc 16022 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16023 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16024 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
AnnaBridge 171:3a7713b1edbc 16025 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16026 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
AnnaBridge 171:3a7713b1edbc 16027 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
AnnaBridge 171:3a7713b1edbc 16028 * |[31] |MIE |Master Interrupt Enable Bit
AnnaBridge 171:3a7713b1edbc 16029 * | | |This bit is a global interrupt enable.
AnnaBridge 171:3a7713b1edbc 16030 * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
AnnaBridge 171:3a7713b1edbc 16031 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16032 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16033 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16034 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16035 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16036 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16037 * @var USBH_T::HcInterruptDisable
AnnaBridge 171:3a7713b1edbc 16038 * Offset: 0x14 Host Controller Interrupt Disable Register
AnnaBridge 171:3a7713b1edbc 16039 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16040 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16041 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16042 * |[0] |SO |Scheduling Overrun Disable Bit
AnnaBridge 171:3a7713b1edbc 16043 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16044 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16045 * | | |1 = Disable interrupt generation due to SO (HcIntSts[0]).
AnnaBridge 171:3a7713b1edbc 16046 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16047 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
AnnaBridge 171:3a7713b1edbc 16048 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
AnnaBridge 171:3a7713b1edbc 16049 * |[1] |WDH |Write Back Done Head Disable Bit
AnnaBridge 171:3a7713b1edbc 16050 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16051 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16052 * | | |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
AnnaBridge 171:3a7713b1edbc 16053 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16054 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
AnnaBridge 171:3a7713b1edbc 16055 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
AnnaBridge 171:3a7713b1edbc 16056 * |[2] |SF |Start Of Frame Disable Bit
AnnaBridge 171:3a7713b1edbc 16057 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16058 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16059 * | | |1 = Disable interrupt generation due to SF (HcIntSts[2]).
AnnaBridge 171:3a7713b1edbc 16060 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16061 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
AnnaBridge 171:3a7713b1edbc 16062 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
AnnaBridge 171:3a7713b1edbc 16063 * |[3] |RD |Resume Detected Disable Bit
AnnaBridge 171:3a7713b1edbc 16064 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16065 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16066 * | | |1 = Disable interrupt generation due to RD (HcIntSts[3]).
AnnaBridge 171:3a7713b1edbc 16067 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16068 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
AnnaBridge 171:3a7713b1edbc 16069 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
AnnaBridge 171:3a7713b1edbc 16070 * |[5] |FNO |Frame Number Overflow Disable Bit
AnnaBridge 171:3a7713b1edbc 16071 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16072 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16073 * | | |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
AnnaBridge 171:3a7713b1edbc 16074 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16075 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
AnnaBridge 171:3a7713b1edbc 16076 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
AnnaBridge 171:3a7713b1edbc 16077 * |[6] |RHSC |Root Hub Status Change Disable Bit
AnnaBridge 171:3a7713b1edbc 16078 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16079 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16080 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
AnnaBridge 171:3a7713b1edbc 16081 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16082 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
AnnaBridge 171:3a7713b1edbc 16083 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
AnnaBridge 171:3a7713b1edbc 16084 * |[31] |MIE |Master Interrupt Disable Bit
AnnaBridge 171:3a7713b1edbc 16085 * | | |Global interrupt disable. Writing '1' to disable all interrupts.
AnnaBridge 171:3a7713b1edbc 16086 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16087 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16088 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16089 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16090 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16091 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
AnnaBridge 171:3a7713b1edbc 16092 * @var USBH_T::HcHCCA
AnnaBridge 171:3a7713b1edbc 16093 * Offset: 0x18 Host Controller Communication Area Register
AnnaBridge 171:3a7713b1edbc 16094 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16095 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16096 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16097 * |[31:8] |HCCA |Host Controller Communication Area
AnnaBridge 171:3a7713b1edbc 16098 * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
AnnaBridge 171:3a7713b1edbc 16099 * @var USBH_T::HcPeriodCurrentED
AnnaBridge 171:3a7713b1edbc 16100 * Offset: 0x1C Host Controller Period Current ED Register
AnnaBridge 171:3a7713b1edbc 16101 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16102 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16103 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16104 * |[31:4] |PCED |Periodic Current ED
AnnaBridge 171:3a7713b1edbc 16105 * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
AnnaBridge 171:3a7713b1edbc 16106 * @var USBH_T::HcControlHeadED
AnnaBridge 171:3a7713b1edbc 16107 * Offset: 0x20 Host Controller Control Head ED Register
AnnaBridge 171:3a7713b1edbc 16108 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16109 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16110 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16111 * |[31:4] |CHED |Control Head ED
AnnaBridge 171:3a7713b1edbc 16112 * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
AnnaBridge 171:3a7713b1edbc 16113 * @var USBH_T::HcControlCurrentED
AnnaBridge 171:3a7713b1edbc 16114 * Offset: 0x24 Host Controller Control Current ED Register
AnnaBridge 171:3a7713b1edbc 16115 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16116 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16117 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16118 * |[31:4] |CCED |Control Current Head ED
AnnaBridge 171:3a7713b1edbc 16119 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
AnnaBridge 171:3a7713b1edbc 16120 * @var USBH_T::HcBulkHeadED
AnnaBridge 171:3a7713b1edbc 16121 * Offset: 0x28 Host Controller Bulk Head ED Register
AnnaBridge 171:3a7713b1edbc 16122 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16123 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16124 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16125 * |[31:4] |BHED |Bulk Head ED
AnnaBridge 171:3a7713b1edbc 16126 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
AnnaBridge 171:3a7713b1edbc 16127 * @var USBH_T::HcBulkCurrentED
AnnaBridge 171:3a7713b1edbc 16128 * Offset: 0x2C Host Controller Bulk Current ED Register
AnnaBridge 171:3a7713b1edbc 16129 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16130 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16131 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16132 * |[31:4] |BCED |Bulk Current Head ED
AnnaBridge 171:3a7713b1edbc 16133 * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
AnnaBridge 171:3a7713b1edbc 16134 * @var USBH_T::HcDoneHead
AnnaBridge 171:3a7713b1edbc 16135 * Offset: 0x30 Host Controller Done Head Register
AnnaBridge 171:3a7713b1edbc 16136 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16137 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16138 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16139 * |[31:4] |DH |Done Head
AnnaBridge 171:3a7713b1edbc 16140 * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
AnnaBridge 171:3a7713b1edbc 16141 * @var USBH_T::HcFmInterval
AnnaBridge 171:3a7713b1edbc 16142 * Offset: 0x34 Host Controller Frame Interval Register
AnnaBridge 171:3a7713b1edbc 16143 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16144 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16145 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16146 * |[13:0] |FI |Frame Interval
AnnaBridge 171:3a7713b1edbc 16147 * | | |This field specifies the length of a frame as (bit times - 1).
AnnaBridge 171:3a7713b1edbc 16148 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
AnnaBridge 171:3a7713b1edbc 16149 * |[30:16] |FSMPS |FS Largest Data Packet
AnnaBridge 171:3a7713b1edbc 16150 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
AnnaBridge 171:3a7713b1edbc 16151 * |[31] |FIT |Frame Interval Toggle
AnnaBridge 171:3a7713b1edbc 16152 * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
AnnaBridge 171:3a7713b1edbc 16153 * | | |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
AnnaBridge 171:3a7713b1edbc 16154 * | | |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
AnnaBridge 171:3a7713b1edbc 16155 * @var USBH_T::HcFmRemaining
AnnaBridge 171:3a7713b1edbc 16156 * Offset: 0x38 Host Controller Frame Remaining Register
AnnaBridge 171:3a7713b1edbc 16157 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16158 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16159 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16160 * |[13:0] |FR |Frame Remaining
AnnaBridge 171:3a7713b1edbc 16161 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
AnnaBridge 171:3a7713b1edbc 16162 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
AnnaBridge 171:3a7713b1edbc 16163 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
AnnaBridge 171:3a7713b1edbc 16164 * |[31] |FRT |Frame Remaining Toggle
AnnaBridge 171:3a7713b1edbc 16165 * | | |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
AnnaBridge 171:3a7713b1edbc 16166 * @var USBH_T::HcFmNumber
AnnaBridge 171:3a7713b1edbc 16167 * Offset: 0x3C Host Controller Frame Number Register
AnnaBridge 171:3a7713b1edbc 16168 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16169 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16170 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16171 * |[15:0] |FN |Frame Number
AnnaBridge 171:3a7713b1edbc 16172 * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
AnnaBridge 171:3a7713b1edbc 16173 * | | |The count rolls over from 'FFFFh' to '0h.'.
AnnaBridge 171:3a7713b1edbc 16174 * @var USBH_T::HcPeriodicStart
AnnaBridge 171:3a7713b1edbc 16175 * Offset: 0x40 Host Controller Periodic Start Register
AnnaBridge 171:3a7713b1edbc 16176 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16177 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16178 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16179 * |[13:0] |PS |Periodic Start
AnnaBridge 171:3a7713b1edbc 16180 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
AnnaBridge 171:3a7713b1edbc 16181 * @var USBH_T::HcLSThreshold
AnnaBridge 171:3a7713b1edbc 16182 * Offset: 0x44 Host Controller Low-speed Threshold Register
AnnaBridge 171:3a7713b1edbc 16183 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16184 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16185 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16186 * |[11:0] |LST |Low-Speed Threshold
AnnaBridge 171:3a7713b1edbc 16187 * | | |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
AnnaBridge 171:3a7713b1edbc 16188 * | | |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
AnnaBridge 171:3a7713b1edbc 16189 * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
AnnaBridge 171:3a7713b1edbc 16190 * @var USBH_T::HcRhDescriptorA
AnnaBridge 171:3a7713b1edbc 16191 * Offset: 0x48 Host Controller Root Hub Descriptor A Register
AnnaBridge 171:3a7713b1edbc 16192 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16193 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16194 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16195 * |[7:0] |NDP |Number Downstream Ports
AnnaBridge 171:3a7713b1edbc 16196 * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
AnnaBridge 171:3a7713b1edbc 16197 * |[8] |PSM |Power Switching Mode
AnnaBridge 171:3a7713b1edbc 16198 * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
AnnaBridge 171:3a7713b1edbc 16199 * | | |0 = Global Switching.
AnnaBridge 171:3a7713b1edbc 16200 * | | |1 = Individual Switching.
AnnaBridge 171:3a7713b1edbc 16201 * |[11] |OCPM |Over Current Protection Mode
AnnaBridge 171:3a7713b1edbc 16202 * | | |This bit describes how the over current status for the Root Hub ports reported.
AnnaBridge 171:3a7713b1edbc 16203 * | | |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
AnnaBridge 171:3a7713b1edbc 16204 * | | |0 = Global Over current.
AnnaBridge 171:3a7713b1edbc 16205 * | | |1 = Individual Over current.
AnnaBridge 171:3a7713b1edbc 16206 * |[12] |NOCP |No Over Current Protection
AnnaBridge 171:3a7713b1edbc 16207 * | | |This bit describes how the over current status for the Root Hub ports reported.
AnnaBridge 171:3a7713b1edbc 16208 * | | |0 = Over current status is reported.
AnnaBridge 171:3a7713b1edbc 16209 * | | |1 = Over current status is not reported.
AnnaBridge 171:3a7713b1edbc 16210 * @var USBH_T::HcRhDescriptorB
AnnaBridge 171:3a7713b1edbc 16211 * Offset: 0x4C Host Controller Root Hub Descriptor B Register
AnnaBridge 171:3a7713b1edbc 16212 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16213 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16214 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16215 * |[31:16] |PPCM |Port Power Control Mask
AnnaBridge 171:3a7713b1edbc 16216 * | | |Global power switching.
AnnaBridge 171:3a7713b1edbc 16217 * | | |This field is only valid if PowerSwitchingMode is set (individual port switching).
AnnaBridge 171:3a7713b1edbc 16218 * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
AnnaBridge 171:3a7713b1edbc 16219 * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
AnnaBridge 171:3a7713b1edbc 16220 * | | |0 = Port power controlled by global power switching.
AnnaBridge 171:3a7713b1edbc 16221 * | | |1 = Port power controlled by port power switching.
AnnaBridge 171:3a7713b1edbc 16222 * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
AnnaBridge 171:3a7713b1edbc 16223 * @var USBH_T::HcRhStatus
AnnaBridge 171:3a7713b1edbc 16224 * Offset: 0x50 Host Controller Root Hub Status Register
AnnaBridge 171:3a7713b1edbc 16225 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16226 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16227 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16228 * |[0] |LPS |Clear Global Power
AnnaBridge 171:3a7713b1edbc 16229 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
AnnaBridge 171:3a7713b1edbc 16230 * | | |This bit always read as zero.
AnnaBridge 171:3a7713b1edbc 16231 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16232 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16233 * | | |1 = Clear global power.
AnnaBridge 171:3a7713b1edbc 16234 * |[1] |OCI |Over Current Indicator
AnnaBridge 171:3a7713b1edbc 16235 * | | |This bit reflects the state of the over current status pin.
AnnaBridge 171:3a7713b1edbc 16236 * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
AnnaBridge 171:3a7713b1edbc 16237 * | | |0 = No over current condition.
AnnaBridge 171:3a7713b1edbc 16238 * | | |1 = Over current condition.
AnnaBridge 171:3a7713b1edbc 16239 * |[15] |DRWE |Device Remote Wakeup Enable Bit
AnnaBridge 171:3a7713b1edbc 16240 * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
AnnaBridge 171:3a7713b1edbc 16241 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16242 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16243 * | | |1 = Enable Connect Status Change as a remote wake-up event.
AnnaBridge 171:3a7713b1edbc 16244 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16245 * | | |0 = Connect Status Change as a remote wake-up event disabled.
AnnaBridge 171:3a7713b1edbc 16246 * | | |1 = Connect Status Change as a remote wake-up event enabled.
AnnaBridge 171:3a7713b1edbc 16247 * |[16] |LPSC |Set Global Power
AnnaBridge 171:3a7713b1edbc 16248 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
AnnaBridge 171:3a7713b1edbc 16249 * | | |This bit always read as zero.
AnnaBridge 171:3a7713b1edbc 16250 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16251 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16252 * | | |1 = Set global power.
AnnaBridge 171:3a7713b1edbc 16253 * |[17] |OCIC |Over Current Indicator Change
AnnaBridge 171:3a7713b1edbc 16254 * | | |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
AnnaBridge 171:3a7713b1edbc 16255 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16256 * | | |0 = OCI (HcRhSts[1]) didn't change.
AnnaBridge 171:3a7713b1edbc 16257 * | | |1 = OCI (HcRhSts[1]) change.
AnnaBridge 171:3a7713b1edbc 16258 * |[31] |CRWE |Clear Remote Wake-up Enable Bit
AnnaBridge 171:3a7713b1edbc 16259 * | | |This bit is use to clear DRWE (HcRhSts[15]).
AnnaBridge 171:3a7713b1edbc 16260 * | | |This bit always read as zero.
AnnaBridge 171:3a7713b1edbc 16261 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16262 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16263 * | | |1 = Clear DRWE (HcRhSts[15]).
AnnaBridge 171:3a7713b1edbc 16264 * @var USBH_T::HcRhPortStatus
AnnaBridge 171:3a7713b1edbc 16265 * Offset: 0x54 Host Controller Root Hub Port Status [1]
AnnaBridge 171:3a7713b1edbc 16266 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16267 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16268 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16269 * |[0] |CCS |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
AnnaBridge 171:3a7713b1edbc 16270 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16271 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16272 * | | |1 = Clear port enable.
AnnaBridge 171:3a7713b1edbc 16273 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16274 * | | |0 = No device connected.
AnnaBridge 171:3a7713b1edbc 16275 * | | |1 = Device connected.
AnnaBridge 171:3a7713b1edbc 16276 * |[1] |PES |Port Enable Status
AnnaBridge 171:3a7713b1edbc 16277 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16278 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16279 * | | |1 = Set port enable.
AnnaBridge 171:3a7713b1edbc 16280 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16281 * | | |0 = Port Disabled.
AnnaBridge 171:3a7713b1edbc 16282 * | | |1 = Port Enabled.
AnnaBridge 171:3a7713b1edbc 16283 * |[2] |PSS |Port Suspend Status
AnnaBridge 171:3a7713b1edbc 16284 * | | |This bit indicates the port is suspended
AnnaBridge 171:3a7713b1edbc 16285 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16286 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16287 * | | |1 = Set port suspend.
AnnaBridge 171:3a7713b1edbc 16288 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16289 * | | |0 = Port is not suspended.
AnnaBridge 171:3a7713b1edbc 16290 * | | |1 = Port is selectively suspended.
AnnaBridge 171:3a7713b1edbc 16291 * |[3] |POCI |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
AnnaBridge 171:3a7713b1edbc 16292 * | | |This bit reflects the state of the over current status pin dedicated to this port.
AnnaBridge 171:3a7713b1edbc 16293 * | | |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
AnnaBridge 171:3a7713b1edbc 16294 * | | |This bit is also used to initiate the selective result sequence for the port.
AnnaBridge 171:3a7713b1edbc 16295 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16296 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16297 * | | |1 = Clear port suspend.
AnnaBridge 171:3a7713b1edbc 16298 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16299 * | | |0 = No over current condition.
AnnaBridge 171:3a7713b1edbc 16300 * | | |1 = Over current condition.
AnnaBridge 171:3a7713b1edbc 16301 * |[4] |PRS |Port Reset Status
AnnaBridge 171:3a7713b1edbc 16302 * | | |This bit reflects the reset state of the port.
AnnaBridge 171:3a7713b1edbc 16303 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16304 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16305 * | | |1 = Set port reset.
AnnaBridge 171:3a7713b1edbc 16306 * | | |Read Operation
AnnaBridge 171:3a7713b1edbc 16307 * | | |0 = Port reset signal is not active.
AnnaBridge 171:3a7713b1edbc 16308 * | | |1 = Port reset signal is active.
AnnaBridge 171:3a7713b1edbc 16309 * |[8] |PPS |Port Power Status
AnnaBridge 171:3a7713b1edbc 16310 * | | |This bit reflects the power state of the port regardless of the power switching mode.
AnnaBridge 171:3a7713b1edbc 16311 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16312 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16313 * | | |1 = Port Power Enabled.
AnnaBridge 171:3a7713b1edbc 16314 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16315 * | | |0 = Port power is Disabled.
AnnaBridge 171:3a7713b1edbc 16316 * | | |1 = Port power is Enabled.
AnnaBridge 171:3a7713b1edbc 16317 * |[9] |LSDA |Low Speed Device Attached (Read) Or Clear Port Power (Write)
AnnaBridge 171:3a7713b1edbc 16318 * | | |This bit defines the speed (and bud idle) of the attached device.
AnnaBridge 171:3a7713b1edbc 16319 * | | |It is only valid when CCS (HcRhPrt1[0]) is set.
AnnaBridge 171:3a7713b1edbc 16320 * | | |This bit is also used to clear port power.
AnnaBridge 171:3a7713b1edbc 16321 * | | |Write Operation:
AnnaBridge 171:3a7713b1edbc 16322 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16323 * | | |1 = Clear PPS (HcRhPrt1[8]).
AnnaBridge 171:3a7713b1edbc 16324 * | | |Read Operation:
AnnaBridge 171:3a7713b1edbc 16325 * | | |0 = Full Speed device.
AnnaBridge 171:3a7713b1edbc 16326 * | | |1 = Low-speed device.
AnnaBridge 171:3a7713b1edbc 16327 * |[16] |CSC |Connect Status Change
AnnaBridge 171:3a7713b1edbc 16328 * | | |This bit indicates connect or disconnect event has been detected (CCS
AnnaBridge 171:3a7713b1edbc 16329 * | | |(HcRhPrt1[0]) changed).
AnnaBridge 171:3a7713b1edbc 16330 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16331 * | | |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
AnnaBridge 171:3a7713b1edbc 16332 * | | |1 = Hardware detection of connect/disconnect event (CCS
AnnaBridge 171:3a7713b1edbc 16333 * | | |(HcRhPrt1[0]) changed).
AnnaBridge 171:3a7713b1edbc 16334 * |[17] |PESC |Port Enable Status Change
AnnaBridge 171:3a7713b1edbc 16335 * | | |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
AnnaBridge 171:3a7713b1edbc 16336 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16337 * | | |0 = PES (HcRhPrt1[1]) didn't change.
AnnaBridge 171:3a7713b1edbc 16338 * | | |1 = PES (HcRhPrt1[1]) changed.
AnnaBridge 171:3a7713b1edbc 16339 * |[18] |PSSC |Port Suspend Status Change
AnnaBridge 171:3a7713b1edbc 16340 * | | |This bit indicates the completion of the selective resume sequence for the port.
AnnaBridge 171:3a7713b1edbc 16341 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16342 * | | |0 = Port resume is not completed.
AnnaBridge 171:3a7713b1edbc 16343 * | | |1 = Port resume completed.
AnnaBridge 171:3a7713b1edbc 16344 * |[19] |OCIC |Port Over Current Indicator Change
AnnaBridge 171:3a7713b1edbc 16345 * | | |This bit is set when POCI (HcRhPrt1[3]) changes.
AnnaBridge 171:3a7713b1edbc 16346 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16347 * | | |0 = POCI (HcRhPrt1[3]) didn't change.
AnnaBridge 171:3a7713b1edbc 16348 * | | |1 = POCI (HcRhPrt1[3]) changes.
AnnaBridge 171:3a7713b1edbc 16349 * |[20] |PRSC |Port Reset Status Change
AnnaBridge 171:3a7713b1edbc 16350 * | | |This bit indicates that the port reset signal has completed.
AnnaBridge 171:3a7713b1edbc 16351 * | | |Write 1 to clear this bit to zero.
AnnaBridge 171:3a7713b1edbc 16352 * | | |0 = Port reset is not complete.
AnnaBridge 171:3a7713b1edbc 16353 * | | |1 = Port reset is complete.
AnnaBridge 171:3a7713b1edbc 16354 * @var USBH_T::HcPhyControl
AnnaBridge 171:3a7713b1edbc 16355 * Offset: 0x200 USB Host Controller PHY Control Register
AnnaBridge 171:3a7713b1edbc 16356 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16357 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16358 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16359 * |[27] |STBYEN |USB Transceiver Standby Enable Bit
AnnaBridge 171:3a7713b1edbc 16360 * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
AnnaBridge 171:3a7713b1edbc 16361 * | | |0 = The USB transceiver would never enter the standby mode.
AnnaBridge 171:3a7713b1edbc 16362 * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
AnnaBridge 171:3a7713b1edbc 16363 * @var USBH_T::HcMiscControl
AnnaBridge 171:3a7713b1edbc 16364 * Offset: 0x204 USB Host Controller Miscellaneous Control Register
AnnaBridge 171:3a7713b1edbc 16365 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16366 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16367 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16368 * |[1] |ABORT |AHB Bus ERROR Response
AnnaBridge 171:3a7713b1edbc 16369 * | | |This bit indicates there is an ERROR response received in AHB bus.
AnnaBridge 171:3a7713b1edbc 16370 * | | |0 = No ERROR response received.
AnnaBridge 171:3a7713b1edbc 16371 * | | |1 = ERROR response received.
AnnaBridge 171:3a7713b1edbc 16372 * |[3] |OCAL |Over Current Active Low
AnnaBridge 171:3a7713b1edbc 16373 * | | |This bit controls the polarity of over current flag from external power IC.
AnnaBridge 171:3a7713b1edbc 16374 * | | |0 = Over current flag is high active.
AnnaBridge 171:3a7713b1edbc 16375 * | | |1 = Over current flag is low active.
AnnaBridge 171:3a7713b1edbc 16376 * |[16] |DPRT1 |Disable Port 1
AnnaBridge 171:3a7713b1edbc 16377 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
AnnaBridge 171:3a7713b1edbc 16378 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
AnnaBridge 171:3a7713b1edbc 16379 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
AnnaBridge 171:3a7713b1edbc 16380 * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
AnnaBridge 171:3a7713b1edbc 16381 * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
AnnaBridge 171:3a7713b1edbc 16382 */
AnnaBridge 171:3a7713b1edbc 16383
AnnaBridge 171:3a7713b1edbc 16384 __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
AnnaBridge 171:3a7713b1edbc 16385 __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
AnnaBridge 171:3a7713b1edbc 16386 __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
AnnaBridge 171:3a7713b1edbc 16387 __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 16388 __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 16389 __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
AnnaBridge 171:3a7713b1edbc 16390 __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
AnnaBridge 171:3a7713b1edbc 16391 __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
AnnaBridge 171:3a7713b1edbc 16392 __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
AnnaBridge 171:3a7713b1edbc 16393 __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
AnnaBridge 171:3a7713b1edbc 16394 __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
AnnaBridge 171:3a7713b1edbc 16395 __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
AnnaBridge 171:3a7713b1edbc 16396 __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
AnnaBridge 171:3a7713b1edbc 16397 __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
AnnaBridge 171:3a7713b1edbc 16398 __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
AnnaBridge 171:3a7713b1edbc 16399 __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
AnnaBridge 171:3a7713b1edbc 16400 __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
AnnaBridge 171:3a7713b1edbc 16401 __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
AnnaBridge 171:3a7713b1edbc 16402 __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
AnnaBridge 171:3a7713b1edbc 16403 __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
AnnaBridge 171:3a7713b1edbc 16404 __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
AnnaBridge 171:3a7713b1edbc 16405 __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
AnnaBridge 171:3a7713b1edbc 16406 __I uint32_t RESERVE0[105];
AnnaBridge 171:3a7713b1edbc 16407 __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
AnnaBridge 171:3a7713b1edbc 16408 __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
AnnaBridge 171:3a7713b1edbc 16409
AnnaBridge 171:3a7713b1edbc 16410 } USBH_T;
AnnaBridge 171:3a7713b1edbc 16411
AnnaBridge 171:3a7713b1edbc 16412
AnnaBridge 171:3a7713b1edbc 16413
AnnaBridge 171:3a7713b1edbc 16414
AnnaBridge 171:3a7713b1edbc 16415 /**
AnnaBridge 171:3a7713b1edbc 16416 @addtogroup USBH_CONST USBH Bit Field Definition
AnnaBridge 171:3a7713b1edbc 16417 Constant Definitions for USBH Controller
AnnaBridge 171:3a7713b1edbc 16418 @{ */
AnnaBridge 171:3a7713b1edbc 16419
AnnaBridge 171:3a7713b1edbc 16420 #define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
AnnaBridge 171:3a7713b1edbc 16421 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
AnnaBridge 171:3a7713b1edbc 16422
AnnaBridge 171:3a7713b1edbc 16423 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
AnnaBridge 171:3a7713b1edbc 16424 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
AnnaBridge 171:3a7713b1edbc 16425
AnnaBridge 171:3a7713b1edbc 16426 #define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: CBSR Position */
AnnaBridge 171:3a7713b1edbc 16427 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: CBSR Mask */
AnnaBridge 171:3a7713b1edbc 16428
AnnaBridge 171:3a7713b1edbc 16429 #define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
AnnaBridge 171:3a7713b1edbc 16430 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
AnnaBridge 171:3a7713b1edbc 16431
AnnaBridge 171:3a7713b1edbc 16432 #define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
AnnaBridge 171:3a7713b1edbc 16433 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
AnnaBridge 171:3a7713b1edbc 16434
AnnaBridge 171:3a7713b1edbc 16435 #define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
AnnaBridge 171:3a7713b1edbc 16436 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
AnnaBridge 171:3a7713b1edbc 16437
AnnaBridge 171:3a7713b1edbc 16438 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
AnnaBridge 171:3a7713b1edbc 16439 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
AnnaBridge 171:3a7713b1edbc 16440
AnnaBridge 171:3a7713b1edbc 16441 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
AnnaBridge 171:3a7713b1edbc 16442 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
AnnaBridge 171:3a7713b1edbc 16443
AnnaBridge 171:3a7713b1edbc 16444 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
AnnaBridge 171:3a7713b1edbc 16445 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
AnnaBridge 171:3a7713b1edbc 16446
AnnaBridge 171:3a7713b1edbc 16447 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
AnnaBridge 171:3a7713b1edbc 16448 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
AnnaBridge 171:3a7713b1edbc 16449
AnnaBridge 171:3a7713b1edbc 16450 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
AnnaBridge 171:3a7713b1edbc 16451 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
AnnaBridge 171:3a7713b1edbc 16452
AnnaBridge 171:3a7713b1edbc 16453 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
AnnaBridge 171:3a7713b1edbc 16454 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
AnnaBridge 171:3a7713b1edbc 16455
AnnaBridge 171:3a7713b1edbc 16456 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position */
AnnaBridge 171:3a7713b1edbc 16457 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
AnnaBridge 171:3a7713b1edbc 16458
AnnaBridge 171:3a7713b1edbc 16459 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
AnnaBridge 171:3a7713b1edbc 16460 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
AnnaBridge 171:3a7713b1edbc 16461
AnnaBridge 171:3a7713b1edbc 16462 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
AnnaBridge 171:3a7713b1edbc 16463 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
AnnaBridge 171:3a7713b1edbc 16464
AnnaBridge 171:3a7713b1edbc 16465 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position */
AnnaBridge 171:3a7713b1edbc 16466 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
AnnaBridge 171:3a7713b1edbc 16467
AnnaBridge 171:3a7713b1edbc 16468 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position */
AnnaBridge 171:3a7713b1edbc 16469 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
AnnaBridge 171:3a7713b1edbc 16470
AnnaBridge 171:3a7713b1edbc 16471 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
AnnaBridge 171:3a7713b1edbc 16472 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
AnnaBridge 171:3a7713b1edbc 16473
AnnaBridge 171:3a7713b1edbc 16474 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position */
AnnaBridge 171:3a7713b1edbc 16475 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
AnnaBridge 171:3a7713b1edbc 16476
AnnaBridge 171:3a7713b1edbc 16477 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
AnnaBridge 171:3a7713b1edbc 16478 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
AnnaBridge 171:3a7713b1edbc 16479
AnnaBridge 171:3a7713b1edbc 16480 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
AnnaBridge 171:3a7713b1edbc 16481 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
AnnaBridge 171:3a7713b1edbc 16482
AnnaBridge 171:3a7713b1edbc 16483 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position */
AnnaBridge 171:3a7713b1edbc 16484 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
AnnaBridge 171:3a7713b1edbc 16485
AnnaBridge 171:3a7713b1edbc 16486 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position */
AnnaBridge 171:3a7713b1edbc 16487 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
AnnaBridge 171:3a7713b1edbc 16488
AnnaBridge 171:3a7713b1edbc 16489 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position */
AnnaBridge 171:3a7713b1edbc 16490 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
AnnaBridge 171:3a7713b1edbc 16491
AnnaBridge 171:3a7713b1edbc 16492 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position */
AnnaBridge 171:3a7713b1edbc 16493 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
AnnaBridge 171:3a7713b1edbc 16494
AnnaBridge 171:3a7713b1edbc 16495 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position */
AnnaBridge 171:3a7713b1edbc 16496 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
AnnaBridge 171:3a7713b1edbc 16497
AnnaBridge 171:3a7713b1edbc 16498 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position */
AnnaBridge 171:3a7713b1edbc 16499 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
AnnaBridge 171:3a7713b1edbc 16500
AnnaBridge 171:3a7713b1edbc 16501 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position */
AnnaBridge 171:3a7713b1edbc 16502 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
AnnaBridge 171:3a7713b1edbc 16503
AnnaBridge 171:3a7713b1edbc 16504 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position */
AnnaBridge 171:3a7713b1edbc 16505 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
AnnaBridge 171:3a7713b1edbc 16506
AnnaBridge 171:3a7713b1edbc 16507 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position */
AnnaBridge 171:3a7713b1edbc 16508 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
AnnaBridge 171:3a7713b1edbc 16509
AnnaBridge 171:3a7713b1edbc 16510 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position */
AnnaBridge 171:3a7713b1edbc 16511 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
AnnaBridge 171:3a7713b1edbc 16512
AnnaBridge 171:3a7713b1edbc 16513 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
AnnaBridge 171:3a7713b1edbc 16514 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
AnnaBridge 171:3a7713b1edbc 16515
AnnaBridge 171:3a7713b1edbc 16516 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position */
AnnaBridge 171:3a7713b1edbc 16517 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
AnnaBridge 171:3a7713b1edbc 16518
AnnaBridge 171:3a7713b1edbc 16519 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
AnnaBridge 171:3a7713b1edbc 16520 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
AnnaBridge 171:3a7713b1edbc 16521
AnnaBridge 171:3a7713b1edbc 16522 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position */
AnnaBridge 171:3a7713b1edbc 16523 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
AnnaBridge 171:3a7713b1edbc 16524
AnnaBridge 171:3a7713b1edbc 16525 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
AnnaBridge 171:3a7713b1edbc 16526 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
AnnaBridge 171:3a7713b1edbc 16527
AnnaBridge 171:3a7713b1edbc 16528 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
AnnaBridge 171:3a7713b1edbc 16529 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
AnnaBridge 171:3a7713b1edbc 16530
AnnaBridge 171:3a7713b1edbc 16531 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
AnnaBridge 171:3a7713b1edbc 16532 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
AnnaBridge 171:3a7713b1edbc 16533
AnnaBridge 171:3a7713b1edbc 16534 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
AnnaBridge 171:3a7713b1edbc 16535 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
AnnaBridge 171:3a7713b1edbc 16536
AnnaBridge 171:3a7713b1edbc 16537 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
AnnaBridge 171:3a7713b1edbc 16538 #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
AnnaBridge 171:3a7713b1edbc 16539
AnnaBridge 171:3a7713b1edbc 16540 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
AnnaBridge 171:3a7713b1edbc 16541 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
AnnaBridge 171:3a7713b1edbc 16542
AnnaBridge 171:3a7713b1edbc 16543 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
AnnaBridge 171:3a7713b1edbc 16544 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
AnnaBridge 171:3a7713b1edbc 16545
AnnaBridge 171:3a7713b1edbc 16546 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
AnnaBridge 171:3a7713b1edbc 16547 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
AnnaBridge 171:3a7713b1edbc 16548
AnnaBridge 171:3a7713b1edbc 16549 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
AnnaBridge 171:3a7713b1edbc 16550 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
AnnaBridge 171:3a7713b1edbc 16551
AnnaBridge 171:3a7713b1edbc 16552 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
AnnaBridge 171:3a7713b1edbc 16553 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
AnnaBridge 171:3a7713b1edbc 16554
AnnaBridge 171:3a7713b1edbc 16555 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
AnnaBridge 171:3a7713b1edbc 16556 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
AnnaBridge 171:3a7713b1edbc 16557
AnnaBridge 171:3a7713b1edbc 16558 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
AnnaBridge 171:3a7713b1edbc 16559 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
AnnaBridge 171:3a7713b1edbc 16560
AnnaBridge 171:3a7713b1edbc 16561 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
AnnaBridge 171:3a7713b1edbc 16562 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
AnnaBridge 171:3a7713b1edbc 16563
AnnaBridge 171:3a7713b1edbc 16564 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
AnnaBridge 171:3a7713b1edbc 16565 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
AnnaBridge 171:3a7713b1edbc 16566
AnnaBridge 171:3a7713b1edbc 16567 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
AnnaBridge 171:3a7713b1edbc 16568 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
AnnaBridge 171:3a7713b1edbc 16569
AnnaBridge 171:3a7713b1edbc 16570 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
AnnaBridge 171:3a7713b1edbc 16571 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
AnnaBridge 171:3a7713b1edbc 16572
AnnaBridge 171:3a7713b1edbc 16573 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
AnnaBridge 171:3a7713b1edbc 16574 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
AnnaBridge 171:3a7713b1edbc 16575
AnnaBridge 171:3a7713b1edbc 16576 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
AnnaBridge 171:3a7713b1edbc 16577 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
AnnaBridge 171:3a7713b1edbc 16578
AnnaBridge 171:3a7713b1edbc 16579 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
AnnaBridge 171:3a7713b1edbc 16580 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
AnnaBridge 171:3a7713b1edbc 16581
AnnaBridge 171:3a7713b1edbc 16582 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
AnnaBridge 171:3a7713b1edbc 16583 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
AnnaBridge 171:3a7713b1edbc 16584
AnnaBridge 171:3a7713b1edbc 16585 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
AnnaBridge 171:3a7713b1edbc 16586 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
AnnaBridge 171:3a7713b1edbc 16587
AnnaBridge 171:3a7713b1edbc 16588 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
AnnaBridge 171:3a7713b1edbc 16589 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
AnnaBridge 171:3a7713b1edbc 16590
AnnaBridge 171:3a7713b1edbc 16591 #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
AnnaBridge 171:3a7713b1edbc 16592 #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
AnnaBridge 171:3a7713b1edbc 16593
AnnaBridge 171:3a7713b1edbc 16594 #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
AnnaBridge 171:3a7713b1edbc 16595 #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
AnnaBridge 171:3a7713b1edbc 16596
AnnaBridge 171:3a7713b1edbc 16597 #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
AnnaBridge 171:3a7713b1edbc 16598 #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
AnnaBridge 171:3a7713b1edbc 16599
AnnaBridge 171:3a7713b1edbc 16600 #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
AnnaBridge 171:3a7713b1edbc 16601 #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
AnnaBridge 171:3a7713b1edbc 16602
AnnaBridge 171:3a7713b1edbc 16603 #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
AnnaBridge 171:3a7713b1edbc 16604 #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
AnnaBridge 171:3a7713b1edbc 16605
AnnaBridge 171:3a7713b1edbc 16606 #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
AnnaBridge 171:3a7713b1edbc 16607 #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
AnnaBridge 171:3a7713b1edbc 16608
AnnaBridge 171:3a7713b1edbc 16609 #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
AnnaBridge 171:3a7713b1edbc 16610 #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
AnnaBridge 171:3a7713b1edbc 16611
AnnaBridge 171:3a7713b1edbc 16612 #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
AnnaBridge 171:3a7713b1edbc 16613 #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
AnnaBridge 171:3a7713b1edbc 16614
AnnaBridge 171:3a7713b1edbc 16615 #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
AnnaBridge 171:3a7713b1edbc 16616 #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
AnnaBridge 171:3a7713b1edbc 16617
AnnaBridge 171:3a7713b1edbc 16618 #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
AnnaBridge 171:3a7713b1edbc 16619 #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
AnnaBridge 171:3a7713b1edbc 16620
AnnaBridge 171:3a7713b1edbc 16621 #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
AnnaBridge 171:3a7713b1edbc 16622 #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
AnnaBridge 171:3a7713b1edbc 16623
AnnaBridge 171:3a7713b1edbc 16624 #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
AnnaBridge 171:3a7713b1edbc 16625 #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
AnnaBridge 171:3a7713b1edbc 16626
AnnaBridge 171:3a7713b1edbc 16627 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
AnnaBridge 171:3a7713b1edbc 16628 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
AnnaBridge 171:3a7713b1edbc 16629
AnnaBridge 171:3a7713b1edbc 16630 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
AnnaBridge 171:3a7713b1edbc 16631 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
AnnaBridge 171:3a7713b1edbc 16632
AnnaBridge 171:3a7713b1edbc 16633 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
AnnaBridge 171:3a7713b1edbc 16634 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
AnnaBridge 171:3a7713b1edbc 16635
AnnaBridge 171:3a7713b1edbc 16636 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
AnnaBridge 171:3a7713b1edbc 16637 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
AnnaBridge 171:3a7713b1edbc 16638
AnnaBridge 171:3a7713b1edbc 16639 /**@}*/ /* USBH_CONST */
AnnaBridge 171:3a7713b1edbc 16640 /**@}*/ /* end of USBH register group */
AnnaBridge 171:3a7713b1edbc 16641
AnnaBridge 171:3a7713b1edbc 16642
AnnaBridge 171:3a7713b1edbc 16643 /*---------------------- Watch Dog Timer Controller -------------------------*/
AnnaBridge 171:3a7713b1edbc 16644 /**
AnnaBridge 171:3a7713b1edbc 16645 @addtogroup WDT Watch Dog Timer Controller(WDT)
AnnaBridge 171:3a7713b1edbc 16646 Memory Mapped Structure for WDT Controller
AnnaBridge 171:3a7713b1edbc 16647 @{ */
AnnaBridge 171:3a7713b1edbc 16648
AnnaBridge 171:3a7713b1edbc 16649
AnnaBridge 171:3a7713b1edbc 16650 typedef struct
AnnaBridge 171:3a7713b1edbc 16651 {
AnnaBridge 171:3a7713b1edbc 16652
AnnaBridge 171:3a7713b1edbc 16653
AnnaBridge 171:3a7713b1edbc 16654
AnnaBridge 171:3a7713b1edbc 16655
AnnaBridge 171:3a7713b1edbc 16656 /**
AnnaBridge 171:3a7713b1edbc 16657 * @var WDT_T::CTL
AnnaBridge 171:3a7713b1edbc 16658 * Offset: 0x00 WDT Control Register
AnnaBridge 171:3a7713b1edbc 16659 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16660 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16661 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16662 * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
AnnaBridge 171:3a7713b1edbc 16663 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16664 * | | |1 = Reset the internal 18-bit WDT up counter value.
AnnaBridge 171:3a7713b1edbc 16665 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16666 * | | |Note2: This bit will be automatically cleared by hardware.
AnnaBridge 171:3a7713b1edbc 16667 * |[1] |RSTEN |WDT Time-Out Reset Enable Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 16668 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
AnnaBridge 171:3a7713b1edbc 16669 * | | |0 = WDT time-out reset function Disabled.
AnnaBridge 171:3a7713b1edbc 16670 * | | |1 = WDT time-out reset function Enabled.
AnnaBridge 171:3a7713b1edbc 16671 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16672 * |[2] |RSTF |WDT Time-Out Reset Flag
AnnaBridge 171:3a7713b1edbc 16673 * | | |This bit indicates the system has been reset by WDT time-out reset or not.
AnnaBridge 171:3a7713b1edbc 16674 * | | |0 = WDT time-out reset did not occur.
AnnaBridge 171:3a7713b1edbc 16675 * | | |1 = WDT time-out reset occurred.
AnnaBridge 171:3a7713b1edbc 16676 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 16677 * |[3] |IF |WDT Time-Out Interrupt Flag
AnnaBridge 171:3a7713b1edbc 16678 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
AnnaBridge 171:3a7713b1edbc 16679 * | | |0 = WDT time-out interrupt did not occur.
AnnaBridge 171:3a7713b1edbc 16680 * | | |1 = WDT time-out interrupt occurred.
AnnaBridge 171:3a7713b1edbc 16681 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 16682 * |[4] |WKEN |WDT Time-Out Wake-Up Function Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 16683 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
AnnaBridge 171:3a7713b1edbc 16684 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 16685 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 16686 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16687 * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
AnnaBridge 171:3a7713b1edbc 16688 * |[5] |WKF |WDT Time-Out Wake-Up Flag
AnnaBridge 171:3a7713b1edbc 16689 * | | |This bit indicates the interrupt wake-up flag status of WDT
AnnaBridge 171:3a7713b1edbc 16690 * | | |0 = WDT does not cause chip wake-up.
AnnaBridge 171:3a7713b1edbc 16691 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
AnnaBridge 171:3a7713b1edbc 16692 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16693 * | | |Note2: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 16694 * |[6] |INTEN |WDT Time-Out Interrupt Enable Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 16695 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
AnnaBridge 171:3a7713b1edbc 16696 * | | |0 = WDT time-out interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 16697 * | | |1 = WDT time-out interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 16698 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16699 * |[7] |WDTEN |WDT Enable Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 16700 * | | |0 = WDT Disabled (This action will reset the internal up counter value).
AnnaBridge 171:3a7713b1edbc 16701 * | | |1 = WDT Enabled.
AnnaBridge 171:3a7713b1edbc 16702 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16703 * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
AnnaBridge 171:3a7713b1edbc 16704 * |[10:8] |TOUTSEL |WDT Time-Out Interval Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 16705 * | | |These three bits select the time-out interval period for the WDT.
AnnaBridge 171:3a7713b1edbc 16706 * | | |000 = (2^4)*TWDT.
AnnaBridge 171:3a7713b1edbc 16707 * | | |001 = (2^6)*TWDT.
AnnaBridge 171:3a7713b1edbc 16708 * | | |010 = (2^8)*TWDT.
AnnaBridge 171:3a7713b1edbc 16709 * | | |011 = (2^10)*TWDT.
AnnaBridge 171:3a7713b1edbc 16710 * | | |100 = (2^12)*TWDT.
AnnaBridge 171:3a7713b1edbc 16711 * | | |101 = (2^14)*TWDT.
AnnaBridge 171:3a7713b1edbc 16712 * | | |110 = (2^16)*TWDT.
AnnaBridge 171:3a7713b1edbc 16713 * | | |111 = (2^18)*TWDT.
AnnaBridge 171:3a7713b1edbc 16714 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16715 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
AnnaBridge 171:3a7713b1edbc 16716 * | | |0 = ICE debug mode acknowledgement affects WDT counting.
AnnaBridge 171:3a7713b1edbc 16717 * | | |WDT up counter will be held while CPU is held by ICE.
AnnaBridge 171:3a7713b1edbc 16718 * | | |1 = ICE debug mode acknowledgement Disabled.
AnnaBridge 171:3a7713b1edbc 16719 * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
AnnaBridge 171:3a7713b1edbc 16720 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16721 * @var WDT_T::ALTCTL
AnnaBridge 171:3a7713b1edbc 16722 * Offset: 0x04 WDT Alternative Control Register
AnnaBridge 171:3a7713b1edbc 16723 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16724 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16725 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16726 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
AnnaBridge 171:3a7713b1edbc 16727 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
AnnaBridge 171:3a7713b1edbc 16728 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
AnnaBridge 171:3a7713b1edbc 16729 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
AnnaBridge 171:3a7713b1edbc 16730 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
AnnaBridge 171:3a7713b1edbc 16731 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
AnnaBridge 171:3a7713b1edbc 16732 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
AnnaBridge 171:3a7713b1edbc 16733 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
AnnaBridge 171:3a7713b1edbc 16734 * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
AnnaBridge 171:3a7713b1edbc 16735 */
AnnaBridge 171:3a7713b1edbc 16736
AnnaBridge 171:3a7713b1edbc 16737 __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
AnnaBridge 171:3a7713b1edbc 16738 __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
AnnaBridge 171:3a7713b1edbc 16739
AnnaBridge 171:3a7713b1edbc 16740 } WDT_T;
AnnaBridge 171:3a7713b1edbc 16741
AnnaBridge 171:3a7713b1edbc 16742
AnnaBridge 171:3a7713b1edbc 16743
AnnaBridge 171:3a7713b1edbc 16744 /**
AnnaBridge 171:3a7713b1edbc 16745 @addtogroup WDT_CONST WDT Bit Field Definition
AnnaBridge 171:3a7713b1edbc 16746 Constant Definitions for WDT Controller
AnnaBridge 171:3a7713b1edbc 16747 @{ */
AnnaBridge 171:3a7713b1edbc 16748
AnnaBridge 171:3a7713b1edbc 16749 #define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
AnnaBridge 171:3a7713b1edbc 16750 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
AnnaBridge 171:3a7713b1edbc 16751
AnnaBridge 171:3a7713b1edbc 16752 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
AnnaBridge 171:3a7713b1edbc 16753 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
AnnaBridge 171:3a7713b1edbc 16754
AnnaBridge 171:3a7713b1edbc 16755 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
AnnaBridge 171:3a7713b1edbc 16756 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
AnnaBridge 171:3a7713b1edbc 16757
AnnaBridge 171:3a7713b1edbc 16758 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
AnnaBridge 171:3a7713b1edbc 16759 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
AnnaBridge 171:3a7713b1edbc 16760
AnnaBridge 171:3a7713b1edbc 16761 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
AnnaBridge 171:3a7713b1edbc 16762 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
AnnaBridge 171:3a7713b1edbc 16763
AnnaBridge 171:3a7713b1edbc 16764 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
AnnaBridge 171:3a7713b1edbc 16765 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
AnnaBridge 171:3a7713b1edbc 16766
AnnaBridge 171:3a7713b1edbc 16767 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
AnnaBridge 171:3a7713b1edbc 16768 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 16769
AnnaBridge 171:3a7713b1edbc 16770 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
AnnaBridge 171:3a7713b1edbc 16771 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
AnnaBridge 171:3a7713b1edbc 16772
AnnaBridge 171:3a7713b1edbc 16773 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
AnnaBridge 171:3a7713b1edbc 16774 #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
AnnaBridge 171:3a7713b1edbc 16775
AnnaBridge 171:3a7713b1edbc 16776 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
AnnaBridge 171:3a7713b1edbc 16777 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
AnnaBridge 171:3a7713b1edbc 16778
AnnaBridge 171:3a7713b1edbc 16779 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
AnnaBridge 171:3a7713b1edbc 16780 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
AnnaBridge 171:3a7713b1edbc 16781
AnnaBridge 171:3a7713b1edbc 16782 /**@}*/ /* WDT_CONST */
AnnaBridge 171:3a7713b1edbc 16783 /**@}*/ /* end of WDT register group */
AnnaBridge 171:3a7713b1edbc 16784
AnnaBridge 171:3a7713b1edbc 16785
AnnaBridge 171:3a7713b1edbc 16786 /*---------------------- Window Watchdog Timer -------------------------*/
AnnaBridge 171:3a7713b1edbc 16787 /**
AnnaBridge 171:3a7713b1edbc 16788 @addtogroup WWDT Window Watchdog Timer(WWDT)
AnnaBridge 171:3a7713b1edbc 16789 Memory Mapped Structure for WWDT Controller
AnnaBridge 171:3a7713b1edbc 16790 @{ */
AnnaBridge 171:3a7713b1edbc 16791
AnnaBridge 171:3a7713b1edbc 16792
AnnaBridge 171:3a7713b1edbc 16793 typedef struct
AnnaBridge 171:3a7713b1edbc 16794 {
AnnaBridge 171:3a7713b1edbc 16795
AnnaBridge 171:3a7713b1edbc 16796
AnnaBridge 171:3a7713b1edbc 16797
AnnaBridge 171:3a7713b1edbc 16798
AnnaBridge 171:3a7713b1edbc 16799 /**
AnnaBridge 171:3a7713b1edbc 16800 * @var WWDT_T::RLDCNT
AnnaBridge 171:3a7713b1edbc 16801 * Offset: 0x00 WWDT Reload Counter Register
AnnaBridge 171:3a7713b1edbc 16802 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16803 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16804 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16805 * |[31:0] |WWDT_RLDCNT|WWDT Reload Counter Register
AnnaBridge 171:3a7713b1edbc 16806 * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
AnnaBridge 171:3a7713b1edbc 16807 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
AnnaBridge 171:3a7713b1edbc 16808 * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
AnnaBridge 171:3a7713b1edbc 16809 * @var WWDT_T::CTL
AnnaBridge 171:3a7713b1edbc 16810 * Offset: 0x04 WWDT Control Register
AnnaBridge 171:3a7713b1edbc 16811 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16812 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16813 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16814 * |[0] |WWDTEN |WWDT Enable Control Bit
AnnaBridge 171:3a7713b1edbc 16815 * | | |Set this bit to enable WWDT counter counting.
AnnaBridge 171:3a7713b1edbc 16816 * | | |0 = WWDT counter is stopped.
AnnaBridge 171:3a7713b1edbc 16817 * | | |1 = WWDT counter is starting counting.
AnnaBridge 171:3a7713b1edbc 16818 * |[1] |INTEN |WWDT Interrupt Enable Control Bit
AnnaBridge 171:3a7713b1edbc 16819 * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
AnnaBridge 171:3a7713b1edbc 16820 * | | |0 = WWDT counter compare match interrupt Disabled.
AnnaBridge 171:3a7713b1edbc 16821 * | | |1 = WWDT counter compare match interrupt Enabled.
AnnaBridge 171:3a7713b1edbc 16822 * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
AnnaBridge 171:3a7713b1edbc 16823 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16824 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16825 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16826 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16827 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16828 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16829 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16830 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16831 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16832 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16833 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16834 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16835 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16836 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16837 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16838 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
AnnaBridge 171:3a7713b1edbc 16839 * |[21:16] |CMPDAT |WWDT Window Compare Register
AnnaBridge 171:3a7713b1edbc 16840 * | | |Set this register to adjust the valid reload window.
AnnaBridge 171:3a7713b1edbc 16841 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
AnnaBridge 171:3a7713b1edbc 16842 * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
AnnaBridge 171:3a7713b1edbc 16843 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
AnnaBridge 171:3a7713b1edbc 16844 * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
AnnaBridge 171:3a7713b1edbc 16845 * | | |WWDT down counter will be held while CPU is held by ICE.
AnnaBridge 171:3a7713b1edbc 16846 * | | |1 = ICE debug mode acknowledgement Disabled.
AnnaBridge 171:3a7713b1edbc 16847 * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
AnnaBridge 171:3a7713b1edbc 16848 * @var WWDT_T::STATUS
AnnaBridge 171:3a7713b1edbc 16849 * Offset: 0x08 WWDT Status Register
AnnaBridge 171:3a7713b1edbc 16850 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16851 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16852 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16853 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
AnnaBridge 171:3a7713b1edbc 16854 * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
AnnaBridge 171:3a7713b1edbc 16855 * | | |0 = No effect.
AnnaBridge 171:3a7713b1edbc 16856 * | | |1 = WWDT counter value matches CMPDAT.
AnnaBridge 171:3a7713b1edbc 16857 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 16858 * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
AnnaBridge 171:3a7713b1edbc 16859 * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
AnnaBridge 171:3a7713b1edbc 16860 * | | |0 = WWDT time-out reset did not occur.
AnnaBridge 171:3a7713b1edbc 16861 * | | |1 = WWDT time-out reset occurred.
AnnaBridge 171:3a7713b1edbc 16862 * | | |Note: This bit is cleared by writing 1 to it.
AnnaBridge 171:3a7713b1edbc 16863 * @var WWDT_T::CNT
AnnaBridge 171:3a7713b1edbc 16864 * Offset: 0x0C WWDT Counter Value Register
AnnaBridge 171:3a7713b1edbc 16865 * ---------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 16866 * |Bits |Field |Descriptions
AnnaBridge 171:3a7713b1edbc 16867 * | :----: | :----: | :---- |
AnnaBridge 171:3a7713b1edbc 16868 * |[5:0] |CNTDAT |WWDT Counter Value
AnnaBridge 171:3a7713b1edbc 16869 * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
AnnaBridge 171:3a7713b1edbc 16870 */
AnnaBridge 171:3a7713b1edbc 16871
AnnaBridge 171:3a7713b1edbc 16872 __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
AnnaBridge 171:3a7713b1edbc 16873 __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
AnnaBridge 171:3a7713b1edbc 16874 __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
AnnaBridge 171:3a7713b1edbc 16875 __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
AnnaBridge 171:3a7713b1edbc 16876
AnnaBridge 171:3a7713b1edbc 16877 } WWDT_T;
AnnaBridge 171:3a7713b1edbc 16878
AnnaBridge 171:3a7713b1edbc 16879
AnnaBridge 171:3a7713b1edbc 16880
AnnaBridge 171:3a7713b1edbc 16881 /**
AnnaBridge 171:3a7713b1edbc 16882 @addtogroup WWDT_CONST WWDT Bit Field Definition
AnnaBridge 171:3a7713b1edbc 16883 Constant Definitions for WWDT Controller
AnnaBridge 171:3a7713b1edbc 16884 @{ */
AnnaBridge 171:3a7713b1edbc 16885
AnnaBridge 171:3a7713b1edbc 16886 #define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position */
AnnaBridge 171:3a7713b1edbc 16887 #define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask */
AnnaBridge 171:3a7713b1edbc 16888
AnnaBridge 171:3a7713b1edbc 16889 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
AnnaBridge 171:3a7713b1edbc 16890 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
AnnaBridge 171:3a7713b1edbc 16891
AnnaBridge 171:3a7713b1edbc 16892 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
AnnaBridge 171:3a7713b1edbc 16893 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 16894
AnnaBridge 171:3a7713b1edbc 16895 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
AnnaBridge 171:3a7713b1edbc 16896 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
AnnaBridge 171:3a7713b1edbc 16897
AnnaBridge 171:3a7713b1edbc 16898 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
AnnaBridge 171:3a7713b1edbc 16899 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
AnnaBridge 171:3a7713b1edbc 16900
AnnaBridge 171:3a7713b1edbc 16901 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
AnnaBridge 171:3a7713b1edbc 16902 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
AnnaBridge 171:3a7713b1edbc 16903
AnnaBridge 171:3a7713b1edbc 16904 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
AnnaBridge 171:3a7713b1edbc 16905 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
AnnaBridge 171:3a7713b1edbc 16906
AnnaBridge 171:3a7713b1edbc 16907 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
AnnaBridge 171:3a7713b1edbc 16908 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
AnnaBridge 171:3a7713b1edbc 16909
AnnaBridge 171:3a7713b1edbc 16910 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
AnnaBridge 171:3a7713b1edbc 16911 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
AnnaBridge 171:3a7713b1edbc 16912
AnnaBridge 171:3a7713b1edbc 16913 /**@}*/ /* WWDT_CONST */
AnnaBridge 171:3a7713b1edbc 16914 /**@}*/ /* end of WWDT register group */
AnnaBridge 171:3a7713b1edbc 16915
AnnaBridge 171:3a7713b1edbc 16916
AnnaBridge 171:3a7713b1edbc 16917 /**@}*/ /* end of REGISTER group */
AnnaBridge 171:3a7713b1edbc 16918
AnnaBridge 171:3a7713b1edbc 16919
AnnaBridge 171:3a7713b1edbc 16920 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 16921 /* Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 16922 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 16923 /** @addtogroup MemoryMap Memory Mapping
AnnaBridge 171:3a7713b1edbc 16924 @{
AnnaBridge 171:3a7713b1edbc 16925 */
AnnaBridge 171:3a7713b1edbc 16926
AnnaBridge 171:3a7713b1edbc 16927 /* Peripheral and SRAM base address */
AnnaBridge 171:3a7713b1edbc 16928 #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
AnnaBridge 171:3a7713b1edbc 16929 #define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
AnnaBridge 171:3a7713b1edbc 16930
AnnaBridge 171:3a7713b1edbc 16931
AnnaBridge 171:3a7713b1edbc 16932 /* Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 16933 #define AHBPERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 16934 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
AnnaBridge 171:3a7713b1edbc 16935
AnnaBridge 171:3a7713b1edbc 16936 /*!< AHB peripherals */
AnnaBridge 171:3a7713b1edbc 16937 #define GCR_BASE (AHBPERIPH_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 16938 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
AnnaBridge 171:3a7713b1edbc 16939 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
AnnaBridge 171:3a7713b1edbc 16940 #define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 16941 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 16942 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
AnnaBridge 171:3a7713b1edbc 16943 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
AnnaBridge 171:3a7713b1edbc 16944 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
AnnaBridge 171:3a7713b1edbc 16945 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
AnnaBridge 171:3a7713b1edbc 16946 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
AnnaBridge 171:3a7713b1edbc 16947 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
AnnaBridge 171:3a7713b1edbc 16948 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
AnnaBridge 171:3a7713b1edbc 16949 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 16950 #define USBH_BASE (AHBPERIPH_BASE + 0x09000)
AnnaBridge 171:3a7713b1edbc 16951 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 16952 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 16953 #define CRC_BASE (AHBPERIPH_BASE + 0x31000)
AnnaBridge 171:3a7713b1edbc 16954
AnnaBridge 171:3a7713b1edbc 16955 /*!< APB0 peripherals */
AnnaBridge 171:3a7713b1edbc 16956 #define WDT_BASE (APBPERIPH_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 16957 #define WWDT_BASE (APBPERIPH_BASE + 0x00100)
AnnaBridge 171:3a7713b1edbc 16958 #define TMR01_BASE (APBPERIPH_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 16959 #define PWM0_BASE (APBPERIPH_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 16960 #define SPI0_BASE (APBPERIPH_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 16961 #define SPI2_BASE (APBPERIPH_BASE + 0x22000)
AnnaBridge 171:3a7713b1edbc 16962 #define UART0_BASE (APBPERIPH_BASE + 0x30000)
AnnaBridge 171:3a7713b1edbc 16963 #define UART2_BASE (APBPERIPH_BASE + 0x32000)
AnnaBridge 171:3a7713b1edbc 16964 #define I2C0_BASE (APBPERIPH_BASE + 0x40000)
AnnaBridge 171:3a7713b1edbc 16965 #define SC0_BASE (APBPERIPH_BASE + 0x50000)
AnnaBridge 171:3a7713b1edbc 16966 #define CAN0_BASE (APBPERIPH_BASE + 0x60000)
AnnaBridge 171:3a7713b1edbc 16967 #define USBD_BASE (APBPERIPH_BASE + 0x80000)
AnnaBridge 171:3a7713b1edbc 16968 #define TK_BASE (APBPERIPH_BASE + 0xA2000)
AnnaBridge 171:3a7713b1edbc 16969
AnnaBridge 171:3a7713b1edbc 16970 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 16971 #define RTC_BASE (APBPERIPH_BASE + 0x01000)
AnnaBridge 171:3a7713b1edbc 16972 #define EADC0_BASE (APBPERIPH_BASE + 0x03000)
AnnaBridge 171:3a7713b1edbc 16973 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
AnnaBridge 171:3a7713b1edbc 16974 #define DAC_BASE (APBPERIPH_BASE + 0x07000)
AnnaBridge 171:3a7713b1edbc 16975 #define OTG_BASE (APBPERIPH_BASE + 0x0D000)
AnnaBridge 171:3a7713b1edbc 16976 #define TMR23_BASE (APBPERIPH_BASE + 0x11000)
AnnaBridge 171:3a7713b1edbc 16977 #define PWM1_BASE (APBPERIPH_BASE + 0x19000)
AnnaBridge 171:3a7713b1edbc 16978 #define SPI1_BASE (APBPERIPH_BASE + 0x21000)
AnnaBridge 171:3a7713b1edbc 16979 #define UART1_BASE (APBPERIPH_BASE + 0x31000)
AnnaBridge 171:3a7713b1edbc 16980 #define UART3_BASE (APBPERIPH_BASE + 0x33000)
AnnaBridge 171:3a7713b1edbc 16981 #define I2C1_BASE (APBPERIPH_BASE + 0x41000)
AnnaBridge 171:3a7713b1edbc 16982 /*@}*/ /* end of group MemoryMap */
AnnaBridge 171:3a7713b1edbc 16983
AnnaBridge 171:3a7713b1edbc 16984
AnnaBridge 171:3a7713b1edbc 16985 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 16986 /* Peripheral declaration */
AnnaBridge 171:3a7713b1edbc 16987 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 16988 /** @addtogroup PeripheralDecl Peripheral Declaration
AnnaBridge 171:3a7713b1edbc 16989 @{
AnnaBridge 171:3a7713b1edbc 16990 */
AnnaBridge 171:3a7713b1edbc 16991
AnnaBridge 171:3a7713b1edbc 16992
AnnaBridge 171:3a7713b1edbc 16993 #define SYS ((SYS_T *) GCR_BASE)
AnnaBridge 171:3a7713b1edbc 16994 #define SYSINT ((SYS_INT_T *) INT_BASE)
AnnaBridge 171:3a7713b1edbc 16995 #define CLK ((CLK_T *) CLK_BASE)
AnnaBridge 171:3a7713b1edbc 16996 #define PA ((GPIO_T *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 16997 #define PB ((GPIO_T *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 16998 #define PC ((GPIO_T *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 16999 #define PD ((GPIO_T *) GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 17000 #define PE ((GPIO_T *) GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 17001 #define PF ((GPIO_T *) GPIOF_BASE)
AnnaBridge 171:3a7713b1edbc 17002 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
AnnaBridge 171:3a7713b1edbc 17003 #define PDMA ((PDMA_T *) PDMA_BASE)
AnnaBridge 171:3a7713b1edbc 17004 #define USBH ((USBH_T *) USBH_BASE)
AnnaBridge 171:3a7713b1edbc 17005 #define FMC ((FMC_T *) FMC_BASE)
AnnaBridge 171:3a7713b1edbc 17006 #define EBI ((EBI_T *) EBI_BASE)
AnnaBridge 171:3a7713b1edbc 17007 #define CRC ((CRC_T *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 17008
AnnaBridge 171:3a7713b1edbc 17009 #define WDT ((WDT_T *) WDT_BASE)
AnnaBridge 171:3a7713b1edbc 17010 #define WWDT ((WWDT_T *) WWDT_BASE)
AnnaBridge 171:3a7713b1edbc 17011 #define RTC ((RTC_T *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 17012 #define EADC ((EADC_T *) EADC0_BASE)
AnnaBridge 171:3a7713b1edbc 17013 #define ACMP01 ((ACMP_T *) ACMP01_BASE)
AnnaBridge 171:3a7713b1edbc 17014
AnnaBridge 171:3a7713b1edbc 17015 #define USBD ((USBD_T *) USBD_BASE)
AnnaBridge 171:3a7713b1edbc 17016 #define OTG ((OTG_T *) OTG_BASE)
AnnaBridge 171:3a7713b1edbc 17017 #define TIMER0 ((TIMER_T *) TMR01_BASE)
AnnaBridge 171:3a7713b1edbc 17018 #define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
AnnaBridge 171:3a7713b1edbc 17019 #define TIMER2 ((TIMER_T *) TMR23_BASE)
AnnaBridge 171:3a7713b1edbc 17020 #define TIMER3 ((TIMER_T *) (TMR23_BASE+ 0x20))
AnnaBridge 171:3a7713b1edbc 17021 #define PWM0 ((PWM_T *) PWM0_BASE)
AnnaBridge 171:3a7713b1edbc 17022 #define PWM1 ((PWM_T *) PWM1_BASE)
AnnaBridge 171:3a7713b1edbc 17023 #define DAC ((DAC_T *) DAC_BASE)
AnnaBridge 171:3a7713b1edbc 17024 #define SPI0 ((SPI_T *) SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 17025 #define SPI1 ((SPI_T *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 17026 #define SPI2 ((SPI_T *) SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 17027 #define UART0 ((UART_T *) UART0_BASE)
AnnaBridge 171:3a7713b1edbc 17028 #define UART1 ((UART_T *) UART1_BASE)
AnnaBridge 171:3a7713b1edbc 17029 #define UART2 ((UART_T *) UART2_BASE)
AnnaBridge 171:3a7713b1edbc 17030 #define UART3 ((UART_T *) UART3_BASE)
AnnaBridge 171:3a7713b1edbc 17031 #define I2C0 ((I2C_T *) I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 17032 #define I2C1 ((I2C_T *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 17033 #define SC0 ((SC_T *) SC0_BASE)
AnnaBridge 171:3a7713b1edbc 17034 #define CAN0 ((CAN_T *) CAN0_BASE)
AnnaBridge 171:3a7713b1edbc 17035 #define TK ((TK_T *) TK_BASE)
AnnaBridge 171:3a7713b1edbc 17036
AnnaBridge 171:3a7713b1edbc 17037 /* One Bit Mask Definitions */
AnnaBridge 171:3a7713b1edbc 17038 #define BIT0 0x00000001
AnnaBridge 171:3a7713b1edbc 17039 #define BIT1 0x00000002
AnnaBridge 171:3a7713b1edbc 17040 #define BIT2 0x00000004
AnnaBridge 171:3a7713b1edbc 17041 #define BIT3 0x00000008
AnnaBridge 171:3a7713b1edbc 17042 #define BIT4 0x00000010
AnnaBridge 171:3a7713b1edbc 17043 #define BIT5 0x00000020
AnnaBridge 171:3a7713b1edbc 17044 #define BIT6 0x00000040
AnnaBridge 171:3a7713b1edbc 17045 #define BIT7 0x00000080
AnnaBridge 171:3a7713b1edbc 17046 #define BIT8 0x00000100
AnnaBridge 171:3a7713b1edbc 17047 #define BIT9 0x00000200
AnnaBridge 171:3a7713b1edbc 17048 #define BIT10 0x00000400
AnnaBridge 171:3a7713b1edbc 17049 #define BIT11 0x00000800
AnnaBridge 171:3a7713b1edbc 17050 #define BIT12 0x00001000
AnnaBridge 171:3a7713b1edbc 17051 #define BIT13 0x00002000
AnnaBridge 171:3a7713b1edbc 17052 #define BIT14 0x00004000
AnnaBridge 171:3a7713b1edbc 17053 #define BIT15 0x00008000
AnnaBridge 171:3a7713b1edbc 17054 #define BIT16 0x00010000
AnnaBridge 171:3a7713b1edbc 17055 #define BIT17 0x00020000
AnnaBridge 171:3a7713b1edbc 17056 #define BIT18 0x00040000
AnnaBridge 171:3a7713b1edbc 17057 #define BIT19 0x00080000
AnnaBridge 171:3a7713b1edbc 17058 #define BIT20 0x00100000
AnnaBridge 171:3a7713b1edbc 17059 #define BIT21 0x00200000
AnnaBridge 171:3a7713b1edbc 17060 #define BIT22 0x00400000
AnnaBridge 171:3a7713b1edbc 17061 #define BIT23 0x00800000
AnnaBridge 171:3a7713b1edbc 17062 #define BIT24 0x01000000
AnnaBridge 171:3a7713b1edbc 17063 #define BIT25 0x02000000
AnnaBridge 171:3a7713b1edbc 17064 #define BIT26 0x04000000
AnnaBridge 171:3a7713b1edbc 17065 #define BIT27 0x08000000
AnnaBridge 171:3a7713b1edbc 17066 #define BIT28 0x10000000
AnnaBridge 171:3a7713b1edbc 17067 #define BIT29 0x20000000
AnnaBridge 171:3a7713b1edbc 17068 #define BIT30 0x40000000
AnnaBridge 171:3a7713b1edbc 17069 #define BIT31 0x80000000
AnnaBridge 171:3a7713b1edbc 17070
AnnaBridge 171:3a7713b1edbc 17071 /* Byte Mask Definitions */
AnnaBridge 171:3a7713b1edbc 17072 #define BYTE0_Msk (0x000000FF)
AnnaBridge 171:3a7713b1edbc 17073 #define BYTE1_Msk (0x0000FF00)
AnnaBridge 171:3a7713b1edbc 17074 #define BYTE2_Msk (0x00FF0000)
AnnaBridge 171:3a7713b1edbc 17075 #define BYTE3_Msk (0xFF000000)
AnnaBridge 171:3a7713b1edbc 17076
AnnaBridge 171:3a7713b1edbc 17077 #define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
AnnaBridge 171:3a7713b1edbc 17078 #define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
AnnaBridge 171:3a7713b1edbc 17079 #define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
AnnaBridge 171:3a7713b1edbc 17080 #define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
AnnaBridge 171:3a7713b1edbc 17081
AnnaBridge 171:3a7713b1edbc 17082 #ifndef TRUE
AnnaBridge 171:3a7713b1edbc 17083 # define TRUE 1
AnnaBridge 171:3a7713b1edbc 17084 #endif
AnnaBridge 171:3a7713b1edbc 17085 #ifndef FALSE
AnnaBridge 171:3a7713b1edbc 17086 # define FALSE 0
AnnaBridge 171:3a7713b1edbc 17087 #endif
AnnaBridge 171:3a7713b1edbc 17088
AnnaBridge 171:3a7713b1edbc 17089 #ifndef NULL
AnnaBridge 171:3a7713b1edbc 17090 #define NULL 0
AnnaBridge 171:3a7713b1edbc 17091 #endif
AnnaBridge 171:3a7713b1edbc 17092
AnnaBridge 171:3a7713b1edbc 17093 #include "m451_sys.h"
AnnaBridge 171:3a7713b1edbc 17094 #include "m451_clk.h"
AnnaBridge 171:3a7713b1edbc 17095 #include "m451_gpio.h"
AnnaBridge 171:3a7713b1edbc 17096 #include "m451_i2c.h"
AnnaBridge 171:3a7713b1edbc 17097 #include "m451_crc.h"
AnnaBridge 171:3a7713b1edbc 17098 #include "m451_ebi.h"
AnnaBridge 171:3a7713b1edbc 17099 #include "m451_rtc.h"
AnnaBridge 171:3a7713b1edbc 17100 #include "m451_timer.h"
AnnaBridge 171:3a7713b1edbc 17101 #include "m451_wdt.h"
AnnaBridge 171:3a7713b1edbc 17102 #include "m451_wwdt.h"
AnnaBridge 171:3a7713b1edbc 17103 #include "m451_spi.h"
AnnaBridge 171:3a7713b1edbc 17104 #include "m451_sc.h"
AnnaBridge 171:3a7713b1edbc 17105 #include "m451_scuart.h"
AnnaBridge 171:3a7713b1edbc 17106 #include "m451_acmp.h"
AnnaBridge 171:3a7713b1edbc 17107 #include "m451_eadc.h"
AnnaBridge 171:3a7713b1edbc 17108 #include "m451_dac.h"
AnnaBridge 171:3a7713b1edbc 17109 #include "m451_can.h"
AnnaBridge 171:3a7713b1edbc 17110 #include "m451_usbd.h"
AnnaBridge 171:3a7713b1edbc 17111 #include "m451_fmc.h"
AnnaBridge 171:3a7713b1edbc 17112 #include "m451_uart.h"
AnnaBridge 171:3a7713b1edbc 17113 #include "m451_pwm.h"
AnnaBridge 171:3a7713b1edbc 17114 #include "m451_pdma.h"
AnnaBridge 171:3a7713b1edbc 17115 #include "m451_tk.h"
AnnaBridge 171:3a7713b1edbc 17116 #include "m451_otg.h"
AnnaBridge 171:3a7713b1edbc 17117
AnnaBridge 171:3a7713b1edbc 17118 typedef volatile unsigned char vu8;
AnnaBridge 171:3a7713b1edbc 17119 typedef volatile unsigned long vu32;
AnnaBridge 171:3a7713b1edbc 17120 typedef volatile unsigned short vu16;
AnnaBridge 171:3a7713b1edbc 17121 #define M8(adr) (*((vu8 *) (adr)))
AnnaBridge 171:3a7713b1edbc 17122 #define M16(adr) (*((vu16 *) (adr)))
AnnaBridge 171:3a7713b1edbc 17123 #define M32(adr) (*((vu32 *) (adr)))
AnnaBridge 171:3a7713b1edbc 17124
AnnaBridge 171:3a7713b1edbc 17125 #define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17126 #define inpw(port) (*((volatile unsigned int *)(port)))
AnnaBridge 171:3a7713b1edbc 17127 #define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17128 #define inpb(port) (*((volatile unsigned char *)(port)))
AnnaBridge 171:3a7713b1edbc 17129 #define outps(port,value) (*((volatile unsigned short *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17130 #define inps(port) (*((volatile unsigned short *)(port)))
AnnaBridge 171:3a7713b1edbc 17131
AnnaBridge 171:3a7713b1edbc 17132 #define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17133 #define inp32(port) (*((volatile unsigned int *)(port)))
AnnaBridge 171:3a7713b1edbc 17134 #define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17135 #define inp8(port) (*((volatile unsigned char *)(port)))
AnnaBridge 171:3a7713b1edbc 17136 #define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
AnnaBridge 171:3a7713b1edbc 17137 #define inp16(port) (*((volatile unsigned short *)(port)))
AnnaBridge 171:3a7713b1edbc 17138
AnnaBridge 171:3a7713b1edbc 17139 /*@}*/ /* end of group PeripheralDecl */
AnnaBridge 171:3a7713b1edbc 17140
AnnaBridge 171:3a7713b1edbc 17141 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 17142 }
AnnaBridge 171:3a7713b1edbc 17143 #endif
AnnaBridge 171:3a7713b1edbc 17144
AnnaBridge 171:3a7713b1edbc 17145 #endif /* __M451SERIES_H__ */
AnnaBridge 171:3a7713b1edbc 17146
AnnaBridge 171:3a7713b1edbc 17147 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
AnnaBridge 171:3a7713b1edbc 17148
AnnaBridge 171:3a7713b1edbc 17149
AnnaBridge 171:3a7713b1edbc 17150