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TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/m451_pwm.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file pwm.h
AnnaBridge 171:3a7713b1edbc 3 * @version V1.00
AnnaBridge 171:3a7713b1edbc 4 * $Revision: 26 $
AnnaBridge 171:3a7713b1edbc 5 * $Date: 15/08/11 10:26a $
AnnaBridge 171:3a7713b1edbc 6 * @brief M451 series PWM driver header file
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * @note
AnnaBridge 171:3a7713b1edbc 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 171:3a7713b1edbc 10 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 11 #ifndef __PWM_H__
AnnaBridge 171:3a7713b1edbc 12 #define __PWM_H__
AnnaBridge 171:3a7713b1edbc 13
AnnaBridge 171:3a7713b1edbc 14 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 15 extern "C"
AnnaBridge 171:3a7713b1edbc 16 {
AnnaBridge 171:3a7713b1edbc 17 #endif
AnnaBridge 171:3a7713b1edbc 18
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 /** @addtogroup Standard_Driver Standard Driver
AnnaBridge 171:3a7713b1edbc 21 @{
AnnaBridge 171:3a7713b1edbc 22 */
AnnaBridge 171:3a7713b1edbc 23
AnnaBridge 171:3a7713b1edbc 24 /** @addtogroup PWM_Driver PWM Driver
AnnaBridge 171:3a7713b1edbc 25 @{
AnnaBridge 171:3a7713b1edbc 26 */
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 /** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
AnnaBridge 171:3a7713b1edbc 29 @{
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31 #define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
AnnaBridge 171:3a7713b1edbc 32 #define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 33 #define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 34 #define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 35 #define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 36 #define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 37 #define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 40 /* Counter Type Constant Definitions */
AnnaBridge 171:3a7713b1edbc 41 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 42 #define PWM_UP_COUNTER (0UL) /*!< Up counter type */
AnnaBridge 171:3a7713b1edbc 43 #define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
AnnaBridge 171:3a7713b1edbc 44 #define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 /* Aligned Type Constant Definitions */
AnnaBridge 171:3a7713b1edbc 48 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 49 #define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
AnnaBridge 171:3a7713b1edbc 50 #define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 53 /* Output Level Constant Definitions */
AnnaBridge 171:3a7713b1edbc 54 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 55 #define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
AnnaBridge 171:3a7713b1edbc 56 #define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
AnnaBridge 171:3a7713b1edbc 57 #define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
AnnaBridge 171:3a7713b1edbc 58 #define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 61 /* Trigger Source Select Constant Definitions */
AnnaBridge 171:3a7713b1edbc 62 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 63 #define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */
AnnaBridge 171:3a7713b1edbc 64 #define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */
AnnaBridge 171:3a7713b1edbc 65 #define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */
AnnaBridge 171:3a7713b1edbc 66 #define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
AnnaBridge 171:3a7713b1edbc 67 #define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
AnnaBridge 171:3a7713b1edbc 68 #define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */
AnnaBridge 171:3a7713b1edbc 69 #define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */
AnnaBridge 171:3a7713b1edbc 70 #define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
AnnaBridge 171:3a7713b1edbc 71 #define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
AnnaBridge 171:3a7713b1edbc 72 #define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
AnnaBridge 171:3a7713b1edbc 73 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
AnnaBridge 171:3a7713b1edbc 74 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
AnnaBridge 171:3a7713b1edbc 75 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
AnnaBridge 171:3a7713b1edbc 76 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
AnnaBridge 171:3a7713b1edbc 77 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
AnnaBridge 171:3a7713b1edbc 78 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 #define PWM_TRIGGER_DAC_ZERO_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 81 #define PWM_TRIGGER_DAC_PERIOD_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
AnnaBridge 171:3a7713b1edbc 82 #define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000UL) /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
AnnaBridge 171:3a7713b1edbc 83 #define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000UL) /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 86 /* Fail brake Control Constant Definitions */
AnnaBridge 171:3a7713b1edbc 87 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 88 #define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 89 #define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 90 #define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 91 #define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 92 #define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 93 #define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 94 #define PWM_FB_EDGE_SYS_RAM (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 95 #define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 #define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 98 #define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 99 #define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 100 #define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 101 #define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 102 #define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 103 #define PWM_FB_LEVEL_SYS_RAM (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 104 #define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
AnnaBridge 171:3a7713b1edbc 107 #define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 110 /* Capture Control Constant Definitions */
AnnaBridge 171:3a7713b1edbc 111 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 112 #define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
AnnaBridge 171:3a7713b1edbc 113 #define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
AnnaBridge 171:3a7713b1edbc 116 #define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
AnnaBridge 171:3a7713b1edbc 117 #define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 120 /* Duty Interrupt Type Constant Definitions */
AnnaBridge 171:3a7713b1edbc 121 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 122 #define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
AnnaBridge 171:3a7713b1edbc 123 #define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 126 /* Interrupt Flag Accumulator Constant Definitions */
AnnaBridge 171:3a7713b1edbc 127 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 128 #define PWM_IFA_EVEN_ZERO_POINT (0UL) /*!< PWM counter equal to zero in even channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 129 #define PWM_IFA_EVEN_PERIOD_POINT (1UL) /*!< PWM counter equal to period in even channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 130 #define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value in even channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 131 #define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value in even channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 132 #define PWM_IFA_ODD_ZERO_POINT (4UL) /*!< PWM counter equal to zero in odd channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 133 #define PWM_IFA_ODD_PERIOD_POINT (5UL) /*!< PWM counter equal to period in odd channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 134 #define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT (6UL) /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 135 #define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT (7UL) /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 138 /* Load Mode Constant Definitions */
AnnaBridge 171:3a7713b1edbc 139 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 140 #define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
AnnaBridge 171:3a7713b1edbc 141 #define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */
AnnaBridge 171:3a7713b1edbc 142 #define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 145 /* Synchronize Control Constant Definitions */
AnnaBridge 171:3a7713b1edbc 146 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 147 #define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
AnnaBridge 171:3a7713b1edbc 148 #define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 149 #define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 150 #define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
AnnaBridge 171:3a7713b1edbc 151 #define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
AnnaBridge 171:3a7713b1edbc 152 #define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 155 /* Noise Filter Clock Divide Select Constant Definitions */
AnnaBridge 171:3a7713b1edbc 156 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 157 #define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 158 #define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 159 #define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 160 #define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 161 #define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 162 #define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 163 #define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 164 #define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 167 /* Clock Source Select Constant Definitions */
AnnaBridge 171:3a7713b1edbc 168 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 169 #define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
AnnaBridge 171:3a7713b1edbc 170 #define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
AnnaBridge 171:3a7713b1edbc 171 #define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
AnnaBridge 171:3a7713b1edbc 172 #define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
AnnaBridge 171:3a7713b1edbc 173 #define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
AnnaBridge 171:3a7713b1edbc 180 @{
AnnaBridge 171:3a7713b1edbc 181 */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /**
AnnaBridge 171:3a7713b1edbc 184 * @brief This macro enable complementary mode
AnnaBridge 171:3a7713b1edbc 185 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 186 * @return None
AnnaBridge 171:3a7713b1edbc 187 * @details This macro is used to enable complementary mode of PWM module.
AnnaBridge 171:3a7713b1edbc 188 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODEn_Msk)
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @brief This macro disable complementary mode, and enable independent mode.
AnnaBridge 171:3a7713b1edbc 194 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 195 * @return None
AnnaBridge 171:3a7713b1edbc 196 * @details This macro is used to disable complementary mode of PWM module.
AnnaBridge 171:3a7713b1edbc 197 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199 #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODEn_Msk)
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /**
AnnaBridge 171:3a7713b1edbc 202 * @brief This macro enable group mode
AnnaBridge 171:3a7713b1edbc 203 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 204 * @return None
AnnaBridge 171:3a7713b1edbc 205 * @details This macro is used to enable group mode of PWM module.
AnnaBridge 171:3a7713b1edbc 206 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 207 */
AnnaBridge 171:3a7713b1edbc 208 #define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /**
AnnaBridge 171:3a7713b1edbc 211 * @brief This macro disable group mode
AnnaBridge 171:3a7713b1edbc 212 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 213 * @return None
AnnaBridge 171:3a7713b1edbc 214 * @details This macro is used to disable group mode of PWM module.
AnnaBridge 171:3a7713b1edbc 215 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217 #define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /**
AnnaBridge 171:3a7713b1edbc 220 * @brief Enable timer synchronous mode of specified channel(s)
AnnaBridge 171:3a7713b1edbc 221 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 222 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 223 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 224 * @return None
AnnaBridge 171:3a7713b1edbc 225 * @details This macro is used to enable timer synchronous mode of specified channel(s).
AnnaBridge 171:3a7713b1edbc 226 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228 #define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) ((pwm)->SSCTL |= (u32ChannelMask))
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /**
AnnaBridge 171:3a7713b1edbc 231 * @brief Disable timer synchronous mode of specified channel(s)
AnnaBridge 171:3a7713b1edbc 232 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 233 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 234 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 235 * @return None
AnnaBridge 171:3a7713b1edbc 236 * @details This macro is used to disable timer synchronous mode of specified channel(s).
AnnaBridge 171:3a7713b1edbc 237 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 #define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
AnnaBridge 171:3a7713b1edbc 240 do{ \
AnnaBridge 171:3a7713b1edbc 241 int i;\
AnnaBridge 171:3a7713b1edbc 242 for(i = 0; i < 6; i++) { \
AnnaBridge 171:3a7713b1edbc 243 if((u32ChannelMask) & (1 << i)) \
AnnaBridge 171:3a7713b1edbc 244 (pwm)->SSCTL &= ~(1UL << i); \
AnnaBridge 171:3a7713b1edbc 245 } \
AnnaBridge 171:3a7713b1edbc 246 }while(0)
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 * @brief This macro enable output inverter of specified channel(s)
AnnaBridge 171:3a7713b1edbc 250 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 251 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 252 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 253 * @return None
AnnaBridge 171:3a7713b1edbc 254 * @details This macro is used to enable output inverter of specified channel(s).
AnnaBridge 171:3a7713b1edbc 255 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257 #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @brief This macro get captured rising data
AnnaBridge 171:3a7713b1edbc 261 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 262 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 263 * @return None
AnnaBridge 171:3a7713b1edbc 264 * @details This macro is used to get captured rising data of specified channel.
AnnaBridge 171:3a7713b1edbc 265 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267 #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /**
AnnaBridge 171:3a7713b1edbc 270 * @brief This macro get captured falling data
AnnaBridge 171:3a7713b1edbc 271 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 272 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 273 * @return None
AnnaBridge 171:3a7713b1edbc 274 * @details This macro is used to get captured falling data of specified channel.
AnnaBridge 171:3a7713b1edbc 275 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277 #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /**
AnnaBridge 171:3a7713b1edbc 280 * @brief This macro mask output logic to high or low
AnnaBridge 171:3a7713b1edbc 281 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 282 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 283 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 284 * @param[in] u32LevelMask Output logic to high or low
AnnaBridge 171:3a7713b1edbc 285 * @return None
AnnaBridge 171:3a7713b1edbc 286 * @details This macro is used to mask output logic to high or low of specified channel(s).
AnnaBridge 171:3a7713b1edbc 287 * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
AnnaBridge 171:3a7713b1edbc 288 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290 #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
AnnaBridge 171:3a7713b1edbc 291 { \
AnnaBridge 171:3a7713b1edbc 292 (pwm)->MSKEN = (u32ChannelMask); \
AnnaBridge 171:3a7713b1edbc 293 (pwm)->MSK = (u32LevelMask); \
AnnaBridge 171:3a7713b1edbc 294 }
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /**
AnnaBridge 171:3a7713b1edbc 297 * @brief This macro set the prescaler of the selected channel
AnnaBridge 171:3a7713b1edbc 298 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 299 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 300 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
AnnaBridge 171:3a7713b1edbc 301 * @return None
AnnaBridge 171:3a7713b1edbc 302 * @details This macro is used to set the prescaler of specified channel.
AnnaBridge 171:3a7713b1edbc 303 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
AnnaBridge 171:3a7713b1edbc 304 * channel 1 will also be affected.
AnnaBridge 171:3a7713b1edbc 305 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler))
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /**
AnnaBridge 171:3a7713b1edbc 310 * @brief This macro set the comparator of the selected channel
AnnaBridge 171:3a7713b1edbc 311 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 312 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 313 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
AnnaBridge 171:3a7713b1edbc 314 * @return None
AnnaBridge 171:3a7713b1edbc 315 * @details This macro is used to set the comparator of specified channel.
AnnaBridge 171:3a7713b1edbc 316 * @note This new setting will take effect on next PWM period.
AnnaBridge 171:3a7713b1edbc 317 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 318 */
AnnaBridge 171:3a7713b1edbc 319 #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /**
AnnaBridge 171:3a7713b1edbc 322 * @brief This macro set the free trigger comparator of the selected channel
AnnaBridge 171:3a7713b1edbc 323 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 324 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 325 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
AnnaBridge 171:3a7713b1edbc 326 * @return None
AnnaBridge 171:3a7713b1edbc 327 * @details This macro is used to set the free trigger comparator of specified channel.
AnnaBridge 171:3a7713b1edbc 328 * @note This new setting will take effect on next PWM period.
AnnaBridge 171:3a7713b1edbc 329 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 330 */
AnnaBridge 171:3a7713b1edbc 331 #define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR))
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 /**
AnnaBridge 171:3a7713b1edbc 334 * @brief This macro set the period of the selected channel
AnnaBridge 171:3a7713b1edbc 335 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 336 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 337 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
AnnaBridge 171:3a7713b1edbc 338 * @return None
AnnaBridge 171:3a7713b1edbc 339 * @details This macro is used to set the period of specified channel.
AnnaBridge 171:3a7713b1edbc 340 * @note This new setting will take effect on next PWM period.
AnnaBridge 171:3a7713b1edbc 341 * @note PWM counter will stop if period length set to 0.
AnnaBridge 171:3a7713b1edbc 342 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 343 */
AnnaBridge 171:3a7713b1edbc 344 #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 /**
AnnaBridge 171:3a7713b1edbc 347 * @brief This macro set the PWM aligned type
AnnaBridge 171:3a7713b1edbc 348 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 349 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 350 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 351 * @param[in] u32AlignedType PWM aligned type, valid values are:
AnnaBridge 171:3a7713b1edbc 352 * - \ref PWM_EDGE_ALIGNED
AnnaBridge 171:3a7713b1edbc 353 * - \ref PWM_CENTER_ALIGNED
AnnaBridge 171:3a7713b1edbc 354 * @return None
AnnaBridge 171:3a7713b1edbc 355 * @details This macro is used to set the PWM aligned type of specified channel(s).
AnnaBridge 171:3a7713b1edbc 356 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
AnnaBridge 171:3a7713b1edbc 359 do{ \
AnnaBridge 171:3a7713b1edbc 360 int i; \
AnnaBridge 171:3a7713b1edbc 361 for(i = 0; i < 6; i++) { \
AnnaBridge 171:3a7713b1edbc 362 if((u32ChannelMask) & (1 << i)) \
AnnaBridge 171:3a7713b1edbc 363 (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (2 * i))) | ((u32AlignedType) << ( 2 * i))); \
AnnaBridge 171:3a7713b1edbc 364 } \
AnnaBridge 171:3a7713b1edbc 365 }while(0)
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /**
AnnaBridge 171:3a7713b1edbc 368 * @brief Set load window of window loading mode for specified channel(s)
AnnaBridge 171:3a7713b1edbc 369 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 370 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 371 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 372 * @return None
AnnaBridge 171:3a7713b1edbc 373 * @details This macro is used to set load window of window loading mode for specified channel(s).
AnnaBridge 171:3a7713b1edbc 374 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 #define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /**
AnnaBridge 171:3a7713b1edbc 379 * @brief Trigger synchronous event from specified channel(s)
AnnaBridge 171:3a7713b1edbc 380 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 381 * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
AnnaBridge 171:3a7713b1edbc 382 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
AnnaBridge 171:3a7713b1edbc 383 * @return None
AnnaBridge 171:3a7713b1edbc 384 * @details This macro is used to trigger synchronous event from specified channel(s).
AnnaBridge 171:3a7713b1edbc 385 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 #define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /**
AnnaBridge 171:3a7713b1edbc 390 * @brief Clear counter of specified channel(s)
AnnaBridge 171:3a7713b1edbc 391 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 392 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 393 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 394 * @return None
AnnaBridge 171:3a7713b1edbc 395 * @details This macro is used to clear counter of specified channel(s).
AnnaBridge 171:3a7713b1edbc 396 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /**
AnnaBridge 171:3a7713b1edbc 401 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
AnnaBridge 171:3a7713b1edbc 402 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 403 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 404 * Bit 0 represents channel 0, bit 1 represents channel 1...
AnnaBridge 171:3a7713b1edbc 405 * @param[in] u32ZeroLevel output level at zero point, valid values are:
AnnaBridge 171:3a7713b1edbc 406 * - \ref PWM_OUTPUT_NOTHING
AnnaBridge 171:3a7713b1edbc 407 * - \ref PWM_OUTPUT_LOW
AnnaBridge 171:3a7713b1edbc 408 * - \ref PWM_OUTPUT_HIGH
AnnaBridge 171:3a7713b1edbc 409 * - \ref PWM_OUTPUT_TOGGLE
AnnaBridge 171:3a7713b1edbc 410 * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
AnnaBridge 171:3a7713b1edbc 411 * - \ref PWM_OUTPUT_NOTHING
AnnaBridge 171:3a7713b1edbc 412 * - \ref PWM_OUTPUT_LOW
AnnaBridge 171:3a7713b1edbc 413 * - \ref PWM_OUTPUT_HIGH
AnnaBridge 171:3a7713b1edbc 414 * - \ref PWM_OUTPUT_TOGGLE
AnnaBridge 171:3a7713b1edbc 415 * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
AnnaBridge 171:3a7713b1edbc 416 * - \ref PWM_OUTPUT_NOTHING
AnnaBridge 171:3a7713b1edbc 417 * - \ref PWM_OUTPUT_LOW
AnnaBridge 171:3a7713b1edbc 418 * - \ref PWM_OUTPUT_HIGH
AnnaBridge 171:3a7713b1edbc 419 * - \ref PWM_OUTPUT_TOGGLE
AnnaBridge 171:3a7713b1edbc 420 * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
AnnaBridge 171:3a7713b1edbc 421 * - \ref PWM_OUTPUT_NOTHING
AnnaBridge 171:3a7713b1edbc 422 * - \ref PWM_OUTPUT_LOW
AnnaBridge 171:3a7713b1edbc 423 * - \ref PWM_OUTPUT_HIGH
AnnaBridge 171:3a7713b1edbc 424 * - \ref PWM_OUTPUT_TOGGLE
AnnaBridge 171:3a7713b1edbc 425 * @return None
AnnaBridge 171:3a7713b1edbc 426 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
AnnaBridge 171:3a7713b1edbc 427 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429 #define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
AnnaBridge 171:3a7713b1edbc 430 do{ \
AnnaBridge 171:3a7713b1edbc 431 int i; \
AnnaBridge 171:3a7713b1edbc 432 for(i = 0; i < 6; i++) { \
AnnaBridge 171:3a7713b1edbc 433 if((u32ChannelMask) & (1 << i)) { \
AnnaBridge 171:3a7713b1edbc 434 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
AnnaBridge 171:3a7713b1edbc 435 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
AnnaBridge 171:3a7713b1edbc 436 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
AnnaBridge 171:3a7713b1edbc 437 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
AnnaBridge 171:3a7713b1edbc 438 } \
AnnaBridge 171:3a7713b1edbc 439 } \
AnnaBridge 171:3a7713b1edbc 440 }while(0)
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /**
AnnaBridge 171:3a7713b1edbc 443 * @brief Trigger brake event from specified channel(s)
AnnaBridge 171:3a7713b1edbc 444 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 445 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
AnnaBridge 171:3a7713b1edbc 446 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
AnnaBridge 171:3a7713b1edbc 447 * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
AnnaBridge 171:3a7713b1edbc 448 * - \ref PWM_FB_EDGE
AnnaBridge 171:3a7713b1edbc 449 * - \ref PWM_FB_LEVEL
AnnaBridge 171:3a7713b1edbc 450 * @return None
AnnaBridge 171:3a7713b1edbc 451 * @details This macro is used to trigger brake event from specified channel(s).
AnnaBridge 171:3a7713b1edbc 452 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 453 */
AnnaBridge 171:3a7713b1edbc 454 #define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /**
AnnaBridge 171:3a7713b1edbc 457 * @brief Set Dead zone clock source
AnnaBridge 171:3a7713b1edbc 458 * @param[in] pwm The pointer of the specified PWM module
AnnaBridge 171:3a7713b1edbc 459 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
AnnaBridge 171:3a7713b1edbc 460 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
AnnaBridge 171:3a7713b1edbc 461 * @return None
AnnaBridge 171:3a7713b1edbc 462 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
AnnaBridge 171:3a7713b1edbc 463 * @note The write-protection function should be disabled before using this function.
AnnaBridge 171:3a7713b1edbc 464 * @note This function is only supported in M45xD/M45xC.
AnnaBridge 171:3a7713b1edbc 465 * \hideinitializer
AnnaBridge 171:3a7713b1edbc 466 */
AnnaBridge 171:3a7713b1edbc 467 #define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
AnnaBridge 171:3a7713b1edbc 468 (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
AnnaBridge 171:3a7713b1edbc 469 ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 472 /* Define PWM functions prototype */
AnnaBridge 171:3a7713b1edbc 473 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 474 uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
AnnaBridge 171:3a7713b1edbc 475 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
AnnaBridge 171:3a7713b1edbc 476 uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
AnnaBridge 171:3a7713b1edbc 477 uint32_t u32ChannelNum,
AnnaBridge 171:3a7713b1edbc 478 uint32_t u32Frequency,
AnnaBridge 171:3a7713b1edbc 479 uint32_t u32DutyCycle,
AnnaBridge 171:3a7713b1edbc 480 uint32_t u32Frequency2);
AnnaBridge 171:3a7713b1edbc 481 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 482 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 483 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 484 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
AnnaBridge 171:3a7713b1edbc 485 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 486 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
AnnaBridge 171:3a7713b1edbc 487 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 488 void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
AnnaBridge 171:3a7713b1edbc 489 void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 490 void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
AnnaBridge 171:3a7713b1edbc 491 uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 492 void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
AnnaBridge 171:3a7713b1edbc 493 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 494 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 495 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 496 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 497 void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
AnnaBridge 171:3a7713b1edbc 498 void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 499 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
AnnaBridge 171:3a7713b1edbc 500 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 501 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
AnnaBridge 171:3a7713b1edbc 502 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
AnnaBridge 171:3a7713b1edbc 503 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
AnnaBridge 171:3a7713b1edbc 504 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 505 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
AnnaBridge 171:3a7713b1edbc 506 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 507 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 508 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 509 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
AnnaBridge 171:3a7713b1edbc 510 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
AnnaBridge 171:3a7713b1edbc 511 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
AnnaBridge 171:3a7713b1edbc 512 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
AnnaBridge 171:3a7713b1edbc 513 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
AnnaBridge 171:3a7713b1edbc 514 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 515 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 516 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 517 void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 518 void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 519 void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 520 uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 521 void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
AnnaBridge 171:3a7713b1edbc 522 void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 523 void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 524 void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 525 void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 526 uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 527 void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 528 uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 529 void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
AnnaBridge 171:3a7713b1edbc 530 void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
AnnaBridge 171:3a7713b1edbc 531 void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
AnnaBridge 171:3a7713b1edbc 532 void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 533 void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
AnnaBridge 171:3a7713b1edbc 534 void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
AnnaBridge 171:3a7713b1edbc 535 void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
AnnaBridge 171:3a7713b1edbc 536 void PWM_EnableSyncPinInverse(PWM_T *pwm);
AnnaBridge 171:3a7713b1edbc 537 void PWM_DisableSyncPinInverse(PWM_T *pwm);
AnnaBridge 171:3a7713b1edbc 538 void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
AnnaBridge 171:3a7713b1edbc 539 void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
AnnaBridge 171:3a7713b1edbc 540 void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
AnnaBridge 171:3a7713b1edbc 541 void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
AnnaBridge 171:3a7713b1edbc 542 void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
AnnaBridge 171:3a7713b1edbc 543 void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
AnnaBridge 171:3a7713b1edbc 544 uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 545 void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 /*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 /*@}*/ /* end of group PWM_Driver */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /*@}*/ /* end of group Standard_Driver */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 555 }
AnnaBridge 171:3a7713b1edbc 556 #endif
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #endif //__PWM_H__
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/