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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_ll_tim.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_ll_tim.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of TIM LL module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_LL_TIM_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_LL_TIM_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	45	#include "stm32l4xx.h"
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	165:d1b4690b3f8b	48	* @{
AnnaBridge	165:d1b4690b3f8b	49	*/
AnnaBridge	165:d1b4690b3f8b	50
AnnaBridge	165:d1b4690b3f8b	51	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
AnnaBridge	165:d1b4690b3f8b	52
AnnaBridge	165:d1b4690b3f8b	53	/** @defgroup TIM_LL TIM
AnnaBridge	165:d1b4690b3f8b	54	* @{
AnnaBridge	165:d1b4690b3f8b	55	*/
AnnaBridge	165:d1b4690b3f8b	56
AnnaBridge	165:d1b4690b3f8b	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	165:d1b4690b3f8b	60	* @{
AnnaBridge	165:d1b4690b3f8b	61	*/
AnnaBridge	165:d1b4690b3f8b	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	165:d1b4690b3f8b	63	{
AnnaBridge	165:d1b4690b3f8b	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	165:d1b4690b3f8b	65	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	165:d1b4690b3f8b	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	165:d1b4690b3f8b	67	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	165:d1b4690b3f8b	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	165:d1b4690b3f8b	69	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	165:d1b4690b3f8b	70	0x04U, /* 6: TIMx_CH4 */
AnnaBridge	165:d1b4690b3f8b	71	0x3CU, /* 7: TIMx_CH5 */
AnnaBridge	165:d1b4690b3f8b	72	0x3CU /* 8: TIMx_CH6 */
AnnaBridge	165:d1b4690b3f8b	73	};
AnnaBridge	165:d1b4690b3f8b	74
AnnaBridge	165:d1b4690b3f8b	75	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	165:d1b4690b3f8b	76	{
AnnaBridge	165:d1b4690b3f8b	77	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	165:d1b4690b3f8b	78	0U, /* 1: - NA */
AnnaBridge	165:d1b4690b3f8b	79	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	165:d1b4690b3f8b	80	0U, /* 3: - NA */
AnnaBridge	165:d1b4690b3f8b	81	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	165:d1b4690b3f8b	82	0U, /* 5: - NA */
AnnaBridge	165:d1b4690b3f8b	83	8U, /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	165:d1b4690b3f8b	84	0U, /* 7: OC5M, OC5FE, OC5PE */
AnnaBridge	165:d1b4690b3f8b	85	8U /* 8: OC6M, OC6FE, OC6PE */
AnnaBridge	165:d1b4690b3f8b	86	};
AnnaBridge	165:d1b4690b3f8b	87
AnnaBridge	165:d1b4690b3f8b	88	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	165:d1b4690b3f8b	89	{
AnnaBridge	165:d1b4690b3f8b	90	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	165:d1b4690b3f8b	91	0U, /* 1: - NA */
AnnaBridge	165:d1b4690b3f8b	92	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	165:d1b4690b3f8b	93	0U, /* 3: - NA */
AnnaBridge	165:d1b4690b3f8b	94	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	165:d1b4690b3f8b	95	0U, /* 5: - NA */
AnnaBridge	165:d1b4690b3f8b	96	8U, /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	165:d1b4690b3f8b	97	0U, /* 7: - NA */
AnnaBridge	165:d1b4690b3f8b	98	0U /* 8: - NA */
AnnaBridge	165:d1b4690b3f8b	99	};
AnnaBridge	165:d1b4690b3f8b	100
AnnaBridge	165:d1b4690b3f8b	101	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	165:d1b4690b3f8b	102	{
AnnaBridge	165:d1b4690b3f8b	103	0U, /* 0: CC1P */
AnnaBridge	165:d1b4690b3f8b	104	2U, /* 1: CC1NP */
AnnaBridge	165:d1b4690b3f8b	105	4U, /* 2: CC2P */
AnnaBridge	165:d1b4690b3f8b	106	6U, /* 3: CC2NP */
AnnaBridge	165:d1b4690b3f8b	107	8U, /* 4: CC3P */
AnnaBridge	165:d1b4690b3f8b	108	10U, /* 5: CC3NP */
AnnaBridge	165:d1b4690b3f8b	109	12U, /* 6: CC4P */
AnnaBridge	165:d1b4690b3f8b	110	16U, /* 7: CC5P */
AnnaBridge	165:d1b4690b3f8b	111	20U /* 8: CC6P */
AnnaBridge	165:d1b4690b3f8b	112	};
AnnaBridge	165:d1b4690b3f8b	113
AnnaBridge	165:d1b4690b3f8b	114	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	165:d1b4690b3f8b	115	{
AnnaBridge	165:d1b4690b3f8b	116	0U, /* 0: OIS1 */
AnnaBridge	165:d1b4690b3f8b	117	1U, /* 1: OIS1N */
AnnaBridge	165:d1b4690b3f8b	118	2U, /* 2: OIS2 */
AnnaBridge	165:d1b4690b3f8b	119	3U, /* 3: OIS2N */
AnnaBridge	165:d1b4690b3f8b	120	4U, /* 4: OIS3 */
AnnaBridge	165:d1b4690b3f8b	121	5U, /* 5: OIS3N */
AnnaBridge	165:d1b4690b3f8b	122	6U, /* 6: OIS4 */
AnnaBridge	165:d1b4690b3f8b	123	8U, /* 7: OIS5 */
AnnaBridge	165:d1b4690b3f8b	124	10U /* 8: OIS6 */
AnnaBridge	165:d1b4690b3f8b	125	};
AnnaBridge	165:d1b4690b3f8b	126	/**
AnnaBridge	165:d1b4690b3f8b	127	* @}
AnnaBridge	165:d1b4690b3f8b	128	*/
AnnaBridge	165:d1b4690b3f8b	129
AnnaBridge	165:d1b4690b3f8b	130
AnnaBridge	165:d1b4690b3f8b	131	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	132	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	165:d1b4690b3f8b	133	* @{
AnnaBridge	165:d1b4690b3f8b	134	*/
AnnaBridge	165:d1b4690b3f8b	135
AnnaBridge	165:d1b4690b3f8b	136	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	165:d1b4690b3f8b	137	#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source)
AnnaBridge	165:d1b4690b3f8b	138
AnnaBridge	165:d1b4690b3f8b	139	/* Generic bit definitions for TIMx_OR2 register */
AnnaBridge	165:d1b4690b3f8b	140	#define TIMx_OR2_BKINE TIM1_OR2_BKINE /!< BRK BKIN input enable /
AnnaBridge	165:d1b4690b3f8b	141	#define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /!< BRK COMP1 enable /
AnnaBridge	165:d1b4690b3f8b	142	#define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /!< BRK COMP2 enable /
AnnaBridge	165:d1b4690b3f8b	143	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	144	#define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /!< BRK DFSDM1_BREAK[0] enable /
AnnaBridge	165:d1b4690b3f8b	145	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	146	#define TIMx_OR2_BKINP TIM1_OR2_BKINP /!< BRK BKIN input polarity /
AnnaBridge	165:d1b4690b3f8b	147	#define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /!< BRK COMP1 input polarity /
AnnaBridge	165:d1b4690b3f8b	148	#define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /!< BRK COMP2 input polarity /
AnnaBridge	165:d1b4690b3f8b	149	#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /!< TIMx ETR source selection /
AnnaBridge	165:d1b4690b3f8b	150
AnnaBridge	165:d1b4690b3f8b	151	/* Generic bit definitions for TIMx_OR3 register */
AnnaBridge	165:d1b4690b3f8b	152	#define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /!< BRK2 BKIN2 input enable /
AnnaBridge	165:d1b4690b3f8b	153	#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /!< BRK2 COMP1 enable /
AnnaBridge	165:d1b4690b3f8b	154	#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /!< BRK2 COMP2 enable /
AnnaBridge	165:d1b4690b3f8b	155	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	156	#define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /!< BRK2 DFSDM1_BREAK[1] enable /
AnnaBridge	165:d1b4690b3f8b	157	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	158	#define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /!< BRK2 BKIN2 input polarity /
AnnaBridge	165:d1b4690b3f8b	159	#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /!< BRK2 COMP1 input polarity /
AnnaBridge	165:d1b4690b3f8b	160	#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /!< BRK2 COMP2 input polarity /
AnnaBridge	165:d1b4690b3f8b	161
AnnaBridge	165:d1b4690b3f8b	162	/* Remap mask definitions */
AnnaBridge	165:d1b4690b3f8b	163	#define TIMx_OR1_RMP_SHIFT 16U
AnnaBridge	165:d1b4690b3f8b	164	#define TIMx_OR1_RMP_MASK 0x0000FFFFU
AnnaBridge	165:d1b4690b3f8b	165	#if defined(ADC3)
AnnaBridge	165:d1b4690b3f8b	166	#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	167	#else
AnnaBridge	165:d1b4690b3f8b	168	#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	169	#endif /* ADC3 */
AnnaBridge	165:d1b4690b3f8b	170	#define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP \| TIM2_OR1_ETR1_RMP \| TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	171	#define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	172	#if defined(ADC2) && defined(ADC3)
AnnaBridge	165:d1b4690b3f8b	173	#define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	174	#else
AnnaBridge	165:d1b4690b3f8b	175	#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	176	#endif /* ADC2 & ADC3 */
AnnaBridge	165:d1b4690b3f8b	177	#define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	178	#define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	179	#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	165:d1b4690b3f8b	180
AnnaBridge	165:d1b4690b3f8b	181	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	165:d1b4690b3f8b	182	#define DT_DELAY_1 ((uint8_t)0x7F)
AnnaBridge	165:d1b4690b3f8b	183	#define DT_DELAY_2 ((uint8_t)0x3F)
AnnaBridge	165:d1b4690b3f8b	184	#define DT_DELAY_3 ((uint8_t)0x1F)
AnnaBridge	165:d1b4690b3f8b	185	#define DT_DELAY_4 ((uint8_t)0x1F)
AnnaBridge	165:d1b4690b3f8b	186
AnnaBridge	165:d1b4690b3f8b	187	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	165:d1b4690b3f8b	188	#define DT_RANGE_1 ((uint8_t)0x00)
AnnaBridge	165:d1b4690b3f8b	189	#define DT_RANGE_2 ((uint8_t)0x80)
AnnaBridge	165:d1b4690b3f8b	190	#define DT_RANGE_3 ((uint8_t)0xC0)
AnnaBridge	165:d1b4690b3f8b	191	#define DT_RANGE_4 ((uint8_t)0xE0)
AnnaBridge	165:d1b4690b3f8b	192
AnnaBridge	165:d1b4690b3f8b	193	/** Legacy definitions for compatibility purpose
AnnaBridge	165:d1b4690b3f8b	194	@cond 0
AnnaBridge	165:d1b4690b3f8b	195	*/
AnnaBridge	165:d1b4690b3f8b	196	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	197	#define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
AnnaBridge	165:d1b4690b3f8b	198	#define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
AnnaBridge	165:d1b4690b3f8b	199	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	200	/**
AnnaBridge	165:d1b4690b3f8b	201	@endcond
AnnaBridge	165:d1b4690b3f8b	202	*/
AnnaBridge	165:d1b4690b3f8b	203
AnnaBridge	165:d1b4690b3f8b	204	/**
AnnaBridge	165:d1b4690b3f8b	205	* @}
AnnaBridge	165:d1b4690b3f8b	206	*/
AnnaBridge	165:d1b4690b3f8b	207
AnnaBridge	165:d1b4690b3f8b	208	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	209	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	165:d1b4690b3f8b	210	* @{
AnnaBridge	165:d1b4690b3f8b	211	*/
AnnaBridge	165:d1b4690b3f8b	212	/** @brief Convert channel id into channel index.
AnnaBridge	165:d1b4690b3f8b	213	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	214	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	215	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	216	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	217	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	218	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	219	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	220	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	221	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	222	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	223	* @retval none
AnnaBridge	165:d1b4690b3f8b	224	*/
AnnaBridge	165:d1b4690b3f8b	225	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	165:d1b4690b3f8b	226	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	165:d1b4690b3f8b	227	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	165:d1b4690b3f8b	228	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	165:d1b4690b3f8b	229	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	165:d1b4690b3f8b	230	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	165:d1b4690b3f8b	231	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
AnnaBridge	165:d1b4690b3f8b	232	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
AnnaBridge	165:d1b4690b3f8b	233	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
AnnaBridge	165:d1b4690b3f8b	234
AnnaBridge	165:d1b4690b3f8b	235	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	165:d1b4690b3f8b	236	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	165:d1b4690b3f8b	237	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	238	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:d1b4690b3f8b	239	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:d1b4690b3f8b	240	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:d1b4690b3f8b	241	* @retval none
AnnaBridge	165:d1b4690b3f8b	242	*/
AnnaBridge	165:d1b4690b3f8b	243	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	165:d1b4690b3f8b	244	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	165:d1b4690b3f8b	245	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	165:d1b4690b3f8b	246	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	165:d1b4690b3f8b	247	/**
AnnaBridge	165:d1b4690b3f8b	248	* @}
AnnaBridge	165:d1b4690b3f8b	249	*/
AnnaBridge	165:d1b4690b3f8b	250
AnnaBridge	165:d1b4690b3f8b	251
AnnaBridge	165:d1b4690b3f8b	252	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	253	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	254	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	165:d1b4690b3f8b	255	* @{
AnnaBridge	165:d1b4690b3f8b	256	*/
AnnaBridge	165:d1b4690b3f8b	257
AnnaBridge	165:d1b4690b3f8b	258	/**
AnnaBridge	165:d1b4690b3f8b	259	* @brief TIM Time Base configuration structure definition.
AnnaBridge	165:d1b4690b3f8b	260	*/
AnnaBridge	165:d1b4690b3f8b	261	typedef struct
AnnaBridge	165:d1b4690b3f8b	262	{
AnnaBridge	165:d1b4690b3f8b	263	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	165:d1b4690b3f8b	264	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:d1b4690b3f8b	265
AnnaBridge	165:d1b4690b3f8b	266	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	165:d1b4690b3f8b	267
AnnaBridge	165:d1b4690b3f8b	268	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	165:d1b4690b3f8b	269	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	165:d1b4690b3f8b	270
AnnaBridge	165:d1b4690b3f8b	271	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	165:d1b4690b3f8b	272
AnnaBridge	165:d1b4690b3f8b	273	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	165:d1b4690b3f8b	274	Auto-Reload Register at the next update event.
AnnaBridge	165:d1b4690b3f8b	275	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:d1b4690b3f8b	276	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	277
AnnaBridge	165:d1b4690b3f8b	278	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	165:d1b4690b3f8b	279
AnnaBridge	165:d1b4690b3f8b	280	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	165:d1b4690b3f8b	281	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	165:d1b4690b3f8b	282
AnnaBridge	165:d1b4690b3f8b	283	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	165:d1b4690b3f8b	284
AnnaBridge	165:d1b4690b3f8b	285	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	165:d1b4690b3f8b	286	reaches zero, an update event is generated and counting restarts
AnnaBridge	165:d1b4690b3f8b	287	from the RCR value (N).
AnnaBridge	165:d1b4690b3f8b	288	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	165:d1b4690b3f8b	289	- the number of PWM periods in edge-aligned mode
AnnaBridge	165:d1b4690b3f8b	290	- the number of half PWM period in center-aligned mode
AnnaBridge	165:d1b4690b3f8b	291	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	165:d1b4690b3f8b	292
AnnaBridge	165:d1b4690b3f8b	293	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	165:d1b4690b3f8b	294	} LL_TIM_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	295
AnnaBridge	165:d1b4690b3f8b	296	/**
AnnaBridge	165:d1b4690b3f8b	297	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	165:d1b4690b3f8b	298	*/
AnnaBridge	165:d1b4690b3f8b	299	typedef struct
AnnaBridge	165:d1b4690b3f8b	300	{
AnnaBridge	165:d1b4690b3f8b	301	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	165:d1b4690b3f8b	302	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	165:d1b4690b3f8b	303
AnnaBridge	165:d1b4690b3f8b	304	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	165:d1b4690b3f8b	305
AnnaBridge	165:d1b4690b3f8b	306	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	165:d1b4690b3f8b	307	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	165:d1b4690b3f8b	308
AnnaBridge	165:d1b4690b3f8b	309	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	165:d1b4690b3f8b	310
AnnaBridge	165:d1b4690b3f8b	311	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	165:d1b4690b3f8b	312	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	165:d1b4690b3f8b	313
AnnaBridge	165:d1b4690b3f8b	314	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	165:d1b4690b3f8b	315
AnnaBridge	165:d1b4690b3f8b	316	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	165:d1b4690b3f8b	317	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:d1b4690b3f8b	318
AnnaBridge	165:d1b4690b3f8b	319	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	165:d1b4690b3f8b	320
AnnaBridge	165:d1b4690b3f8b	321	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	165:d1b4690b3f8b	322	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	165:d1b4690b3f8b	323
AnnaBridge	165:d1b4690b3f8b	324	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	325
AnnaBridge	165:d1b4690b3f8b	326	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	165:d1b4690b3f8b	327	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	165:d1b4690b3f8b	328
AnnaBridge	165:d1b4690b3f8b	329	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	330
AnnaBridge	165:d1b4690b3f8b	331
AnnaBridge	165:d1b4690b3f8b	332	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	165:d1b4690b3f8b	333	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	165:d1b4690b3f8b	334
AnnaBridge	165:d1b4690b3f8b	335	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	165:d1b4690b3f8b	336
AnnaBridge	165:d1b4690b3f8b	337	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	165:d1b4690b3f8b	338	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	165:d1b4690b3f8b	339
AnnaBridge	165:d1b4690b3f8b	340	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	165:d1b4690b3f8b	341	} LL_TIM_OC_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	342
AnnaBridge	165:d1b4690b3f8b	343	/**
AnnaBridge	165:d1b4690b3f8b	344	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	165:d1b4690b3f8b	345	*/
AnnaBridge	165:d1b4690b3f8b	346
AnnaBridge	165:d1b4690b3f8b	347	typedef struct
AnnaBridge	165:d1b4690b3f8b	348	{
AnnaBridge	165:d1b4690b3f8b	349
AnnaBridge	165:d1b4690b3f8b	350	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	165:d1b4690b3f8b	351	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:d1b4690b3f8b	352
AnnaBridge	165:d1b4690b3f8b	353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	354
AnnaBridge	165:d1b4690b3f8b	355	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	165:d1b4690b3f8b	356	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:d1b4690b3f8b	357
AnnaBridge	165:d1b4690b3f8b	358	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:d1b4690b3f8b	359
AnnaBridge	165:d1b4690b3f8b	360	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	165:d1b4690b3f8b	361	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:d1b4690b3f8b	362
AnnaBridge	165:d1b4690b3f8b	363	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:d1b4690b3f8b	364
AnnaBridge	165:d1b4690b3f8b	365	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	165:d1b4690b3f8b	366	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:d1b4690b3f8b	367
AnnaBridge	165:d1b4690b3f8b	368	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:d1b4690b3f8b	369	} LL_TIM_IC_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	370
AnnaBridge	165:d1b4690b3f8b	371
AnnaBridge	165:d1b4690b3f8b	372	/**
AnnaBridge	165:d1b4690b3f8b	373	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	165:d1b4690b3f8b	374	*/
AnnaBridge	165:d1b4690b3f8b	375	typedef struct
AnnaBridge	165:d1b4690b3f8b	376	{
AnnaBridge	165:d1b4690b3f8b	377	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	165:d1b4690b3f8b	378	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	165:d1b4690b3f8b	379
AnnaBridge	165:d1b4690b3f8b	380	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	165:d1b4690b3f8b	381
AnnaBridge	165:d1b4690b3f8b	382	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	165:d1b4690b3f8b	383	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:d1b4690b3f8b	384
AnnaBridge	165:d1b4690b3f8b	385	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	386
AnnaBridge	165:d1b4690b3f8b	387	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	165:d1b4690b3f8b	388	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:d1b4690b3f8b	389
AnnaBridge	165:d1b4690b3f8b	390	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:d1b4690b3f8b	391
AnnaBridge	165:d1b4690b3f8b	392	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	165:d1b4690b3f8b	393	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:d1b4690b3f8b	394
AnnaBridge	165:d1b4690b3f8b	395	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:d1b4690b3f8b	396
AnnaBridge	165:d1b4690b3f8b	397	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	165:d1b4690b3f8b	398	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:d1b4690b3f8b	399
AnnaBridge	165:d1b4690b3f8b	400	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:d1b4690b3f8b	401
AnnaBridge	165:d1b4690b3f8b	402	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	165:d1b4690b3f8b	403	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:d1b4690b3f8b	404
AnnaBridge	165:d1b4690b3f8b	405	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	406
AnnaBridge	165:d1b4690b3f8b	407	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	165:d1b4690b3f8b	408	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:d1b4690b3f8b	409
AnnaBridge	165:d1b4690b3f8b	410	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:d1b4690b3f8b	411
AnnaBridge	165:d1b4690b3f8b	412	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	165:d1b4690b3f8b	413	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:d1b4690b3f8b	414
AnnaBridge	165:d1b4690b3f8b	415	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:d1b4690b3f8b	416
AnnaBridge	165:d1b4690b3f8b	417	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	165:d1b4690b3f8b	418	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:d1b4690b3f8b	419
AnnaBridge	165:d1b4690b3f8b	420	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:d1b4690b3f8b	421
AnnaBridge	165:d1b4690b3f8b	422	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	423
AnnaBridge	165:d1b4690b3f8b	424	/**
AnnaBridge	165:d1b4690b3f8b	425	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	165:d1b4690b3f8b	426	*/
AnnaBridge	165:d1b4690b3f8b	427	typedef struct
AnnaBridge	165:d1b4690b3f8b	428	{
AnnaBridge	165:d1b4690b3f8b	429
AnnaBridge	165:d1b4690b3f8b	430	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	165:d1b4690b3f8b	431	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:d1b4690b3f8b	432
AnnaBridge	165:d1b4690b3f8b	433	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:d1b4690b3f8b	434
AnnaBridge	165:d1b4690b3f8b	435	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	165:d1b4690b3f8b	436	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	165:d1b4690b3f8b	437	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	165:d1b4690b3f8b	438	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:d1b4690b3f8b	439
AnnaBridge	165:d1b4690b3f8b	440	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:d1b4690b3f8b	441
AnnaBridge	165:d1b4690b3f8b	442	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	165:d1b4690b3f8b	443	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:d1b4690b3f8b	444
AnnaBridge	165:d1b4690b3f8b	445	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:d1b4690b3f8b	446
AnnaBridge	165:d1b4690b3f8b	447	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	165:d1b4690b3f8b	448	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	165:d1b4690b3f8b	449	a change occurs on the Hall inputs.
AnnaBridge	165:d1b4690b3f8b	450	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	165:d1b4690b3f8b	451
AnnaBridge	165:d1b4690b3f8b	452	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	165:d1b4690b3f8b	453	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	454
AnnaBridge	165:d1b4690b3f8b	455	/**
AnnaBridge	165:d1b4690b3f8b	456	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	165:d1b4690b3f8b	457	*/
AnnaBridge	165:d1b4690b3f8b	458	typedef struct
AnnaBridge	165:d1b4690b3f8b	459	{
AnnaBridge	165:d1b4690b3f8b	460	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	165:d1b4690b3f8b	461	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	165:d1b4690b3f8b	462
AnnaBridge	165:d1b4690b3f8b	463	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	165:d1b4690b3f8b	464
AnnaBridge	165:d1b4690b3f8b	465	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	466
AnnaBridge	165:d1b4690b3f8b	467	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	165:d1b4690b3f8b	468	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	165:d1b4690b3f8b	469
AnnaBridge	165:d1b4690b3f8b	470	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	165:d1b4690b3f8b	471
AnnaBridge	165:d1b4690b3f8b	472	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	473
AnnaBridge	165:d1b4690b3f8b	474	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	165:d1b4690b3f8b	475	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	165:d1b4690b3f8b	476
AnnaBridge	165:d1b4690b3f8b	477	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	165:d1b4690b3f8b	478	has been written, their content is frozen until the next reset.*/
AnnaBridge	165:d1b4690b3f8b	479
AnnaBridge	165:d1b4690b3f8b	480	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	165:d1b4690b3f8b	481	switching-on of the outputs.
AnnaBridge	165:d1b4690b3f8b	482	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	165:d1b4690b3f8b	483
AnnaBridge	165:d1b4690b3f8b	484	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	165:d1b4690b3f8b	485
AnnaBridge	165:d1b4690b3f8b	486	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	487
AnnaBridge	165:d1b4690b3f8b	488	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	165:d1b4690b3f8b	489	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	165:d1b4690b3f8b	490
AnnaBridge	165:d1b4690b3f8b	491	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	165:d1b4690b3f8b	492
AnnaBridge	165:d1b4690b3f8b	493	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	494
AnnaBridge	165:d1b4690b3f8b	495	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	165:d1b4690b3f8b	496	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	165:d1b4690b3f8b	497
AnnaBridge	165:d1b4690b3f8b	498	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	165:d1b4690b3f8b	499
AnnaBridge	165:d1b4690b3f8b	500	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	501
AnnaBridge	165:d1b4690b3f8b	502	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
AnnaBridge	165:d1b4690b3f8b	503	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
AnnaBridge	165:d1b4690b3f8b	504
AnnaBridge	165:d1b4690b3f8b	505	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	165:d1b4690b3f8b	506
AnnaBridge	165:d1b4690b3f8b	507	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	508
AnnaBridge	165:d1b4690b3f8b	509	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
AnnaBridge	165:d1b4690b3f8b	510	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
AnnaBridge	165:d1b4690b3f8b	511
AnnaBridge	165:d1b4690b3f8b	512	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
AnnaBridge	165:d1b4690b3f8b	513
AnnaBridge	165:d1b4690b3f8b	514	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	515
AnnaBridge	165:d1b4690b3f8b	516	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
AnnaBridge	165:d1b4690b3f8b	517	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
AnnaBridge	165:d1b4690b3f8b	518
AnnaBridge	165:d1b4690b3f8b	519	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	165:d1b4690b3f8b	520
AnnaBridge	165:d1b4690b3f8b	521	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	522
AnnaBridge	165:d1b4690b3f8b	523	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
AnnaBridge	165:d1b4690b3f8b	524	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
AnnaBridge	165:d1b4690b3f8b	525
AnnaBridge	165:d1b4690b3f8b	526	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	165:d1b4690b3f8b	527
AnnaBridge	165:d1b4690b3f8b	528	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	529
AnnaBridge	165:d1b4690b3f8b	530	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	165:d1b4690b3f8b	531	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	165:d1b4690b3f8b	532
AnnaBridge	165:d1b4690b3f8b	533	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	165:d1b4690b3f8b	534
AnnaBridge	165:d1b4690b3f8b	535	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:d1b4690b3f8b	536	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	537
AnnaBridge	165:d1b4690b3f8b	538	/**
AnnaBridge	165:d1b4690b3f8b	539	* @}
AnnaBridge	165:d1b4690b3f8b	540	*/
AnnaBridge	165:d1b4690b3f8b	541	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	542
AnnaBridge	165:d1b4690b3f8b	543	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	544	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	165:d1b4690b3f8b	545	* @{
AnnaBridge	165:d1b4690b3f8b	546	*/
AnnaBridge	165:d1b4690b3f8b	547
AnnaBridge	165:d1b4690b3f8b	548	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:d1b4690b3f8b	549	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	165:d1b4690b3f8b	550	* @{
AnnaBridge	165:d1b4690b3f8b	551	*/
AnnaBridge	165:d1b4690b3f8b	552	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	165:d1b4690b3f8b	553	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	554	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	555	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	556	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	557	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	558	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
AnnaBridge	165:d1b4690b3f8b	559	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	165:d1b4690b3f8b	560	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	165:d1b4690b3f8b	561	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	165:d1b4690b3f8b	562	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
AnnaBridge	165:d1b4690b3f8b	563	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	165:d1b4690b3f8b	564	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	165:d1b4690b3f8b	565	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	165:d1b4690b3f8b	566	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	165:d1b4690b3f8b	567	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
AnnaBridge	165:d1b4690b3f8b	568	/**
AnnaBridge	165:d1b4690b3f8b	569	* @}
AnnaBridge	165:d1b4690b3f8b	570	*/
AnnaBridge	165:d1b4690b3f8b	571
AnnaBridge	165:d1b4690b3f8b	572	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	573	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	165:d1b4690b3f8b	574	* @{
AnnaBridge	165:d1b4690b3f8b	575	*/
AnnaBridge	165:d1b4690b3f8b	576	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	165:d1b4690b3f8b	577	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	165:d1b4690b3f8b	578	/**
AnnaBridge	165:d1b4690b3f8b	579	* @}
AnnaBridge	165:d1b4690b3f8b	580	*/
AnnaBridge	165:d1b4690b3f8b	581
AnnaBridge	165:d1b4690b3f8b	582	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
AnnaBridge	165:d1b4690b3f8b	583	* @{
AnnaBridge	165:d1b4690b3f8b	584	*/
AnnaBridge	165:d1b4690b3f8b	585	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
AnnaBridge	165:d1b4690b3f8b	586	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
AnnaBridge	165:d1b4690b3f8b	587	/**
AnnaBridge	165:d1b4690b3f8b	588	* @}
AnnaBridge	165:d1b4690b3f8b	589	*/
AnnaBridge	165:d1b4690b3f8b	590
AnnaBridge	165:d1b4690b3f8b	591	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	165:d1b4690b3f8b	592	* @{
AnnaBridge	165:d1b4690b3f8b	593	*/
AnnaBridge	165:d1b4690b3f8b	594	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	165:d1b4690b3f8b	595	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	165:d1b4690b3f8b	596	/**
AnnaBridge	165:d1b4690b3f8b	597	* @}
AnnaBridge	165:d1b4690b3f8b	598	*/
AnnaBridge	165:d1b4690b3f8b	599	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	600
AnnaBridge	165:d1b4690b3f8b	601	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	165:d1b4690b3f8b	602	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	165:d1b4690b3f8b	603	* @{
AnnaBridge	165:d1b4690b3f8b	604	*/
AnnaBridge	165:d1b4690b3f8b	605	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	165:d1b4690b3f8b	606	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	165:d1b4690b3f8b	607	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	165:d1b4690b3f8b	608	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	165:d1b4690b3f8b	609	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	165:d1b4690b3f8b	610	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	165:d1b4690b3f8b	611	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	165:d1b4690b3f8b	612	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	165:d1b4690b3f8b	613	/**
AnnaBridge	165:d1b4690b3f8b	614	* @}
AnnaBridge	165:d1b4690b3f8b	615	*/
AnnaBridge	165:d1b4690b3f8b	616
AnnaBridge	165:d1b4690b3f8b	617	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	165:d1b4690b3f8b	618	* @{
AnnaBridge	165:d1b4690b3f8b	619	*/
AnnaBridge	165:d1b4690b3f8b	620	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	165:d1b4690b3f8b	621	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	165:d1b4690b3f8b	622	/**
AnnaBridge	165:d1b4690b3f8b	623	* @}
AnnaBridge	165:d1b4690b3f8b	624	*/
AnnaBridge	165:d1b4690b3f8b	625
AnnaBridge	165:d1b4690b3f8b	626	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	165:d1b4690b3f8b	627	* @{
AnnaBridge	165:d1b4690b3f8b	628	*/
AnnaBridge	165:d1b4690b3f8b	629	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	165:d1b4690b3f8b	630	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	165:d1b4690b3f8b	631	/**
AnnaBridge	165:d1b4690b3f8b	632	* @}
AnnaBridge	165:d1b4690b3f8b	633	*/
AnnaBridge	165:d1b4690b3f8b	634
AnnaBridge	165:d1b4690b3f8b	635	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	165:d1b4690b3f8b	636	* @{
AnnaBridge	165:d1b4690b3f8b	637	*/
AnnaBridge	165:d1b4690b3f8b	638	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	165:d1b4690b3f8b	639	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	165:d1b4690b3f8b	640	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	165:d1b4690b3f8b	641	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	165:d1b4690b3f8b	642	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	165:d1b4690b3f8b	643	/**
AnnaBridge	165:d1b4690b3f8b	644	* @}
AnnaBridge	165:d1b4690b3f8b	645	*/
AnnaBridge	165:d1b4690b3f8b	646
AnnaBridge	165:d1b4690b3f8b	647	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	165:d1b4690b3f8b	648	* @{
AnnaBridge	165:d1b4690b3f8b	649	*/
AnnaBridge	165:d1b4690b3f8b	650	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	165:d1b4690b3f8b	651	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	165:d1b4690b3f8b	652	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	165:d1b4690b3f8b	653	/**
AnnaBridge	165:d1b4690b3f8b	654	* @}
AnnaBridge	165:d1b4690b3f8b	655	*/
AnnaBridge	165:d1b4690b3f8b	656
AnnaBridge	165:d1b4690b3f8b	657	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	165:d1b4690b3f8b	658	* @{
AnnaBridge	165:d1b4690b3f8b	659	*/
AnnaBridge	165:d1b4690b3f8b	660	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	165:d1b4690b3f8b	661	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	165:d1b4690b3f8b	662	/**
AnnaBridge	165:d1b4690b3f8b	663	* @}
AnnaBridge	165:d1b4690b3f8b	664	*/
AnnaBridge	165:d1b4690b3f8b	665
AnnaBridge	165:d1b4690b3f8b	666	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	165:d1b4690b3f8b	667	* @{
AnnaBridge	165:d1b4690b3f8b	668	*/
AnnaBridge	165:d1b4690b3f8b	669	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	165:d1b4690b3f8b	670	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	165:d1b4690b3f8b	671	/**
AnnaBridge	165:d1b4690b3f8b	672	* @}
AnnaBridge	165:d1b4690b3f8b	673	*/
AnnaBridge	165:d1b4690b3f8b	674
AnnaBridge	165:d1b4690b3f8b	675	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	165:d1b4690b3f8b	676	* @{
AnnaBridge	165:d1b4690b3f8b	677	*/
AnnaBridge	165:d1b4690b3f8b	678	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	165:d1b4690b3f8b	679	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	165:d1b4690b3f8b	680	/**
AnnaBridge	165:d1b4690b3f8b	681	* @}
AnnaBridge	165:d1b4690b3f8b	682	*/
AnnaBridge	165:d1b4690b3f8b	683
AnnaBridge	165:d1b4690b3f8b	684	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	165:d1b4690b3f8b	685	* @{
AnnaBridge	165:d1b4690b3f8b	686	*/
AnnaBridge	165:d1b4690b3f8b	687	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	165:d1b4690b3f8b	688	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	165:d1b4690b3f8b	689	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	165:d1b4690b3f8b	690	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	165:d1b4690b3f8b	691	/**
AnnaBridge	165:d1b4690b3f8b	692	* @}
AnnaBridge	165:d1b4690b3f8b	693	*/
AnnaBridge	165:d1b4690b3f8b	694
AnnaBridge	165:d1b4690b3f8b	695	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	165:d1b4690b3f8b	696	* @{
AnnaBridge	165:d1b4690b3f8b	697	*/
AnnaBridge	165:d1b4690b3f8b	698	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	165:d1b4690b3f8b	699	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	165:d1b4690b3f8b	700	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	165:d1b4690b3f8b	701	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	165:d1b4690b3f8b	702	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	165:d1b4690b3f8b	703	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	165:d1b4690b3f8b	704	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	165:d1b4690b3f8b	705	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
AnnaBridge	165:d1b4690b3f8b	706	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
AnnaBridge	165:d1b4690b3f8b	707	/**
AnnaBridge	165:d1b4690b3f8b	708	* @}
AnnaBridge	165:d1b4690b3f8b	709	*/
AnnaBridge	165:d1b4690b3f8b	710
AnnaBridge	165:d1b4690b3f8b	711	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	712	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	165:d1b4690b3f8b	713	* @{
AnnaBridge	165:d1b4690b3f8b	714	*/
AnnaBridge	165:d1b4690b3f8b	715	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	165:d1b4690b3f8b	716	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	165:d1b4690b3f8b	717	/**
AnnaBridge	165:d1b4690b3f8b	718	* @}
AnnaBridge	165:d1b4690b3f8b	719	*/
AnnaBridge	165:d1b4690b3f8b	720	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	721
AnnaBridge	165:d1b4690b3f8b	722	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	165:d1b4690b3f8b	723	* @{
AnnaBridge	165:d1b4690b3f8b	724	*/
AnnaBridge	165:d1b4690b3f8b	725	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	165:d1b4690b3f8b	726	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	165:d1b4690b3f8b	727	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	165:d1b4690b3f8b	728	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	165:d1b4690b3f8b	729	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	165:d1b4690b3f8b	730	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	165:d1b4690b3f8b	731	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	165:d1b4690b3f8b	732	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	165:d1b4690b3f8b	733	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
AnnaBridge	165:d1b4690b3f8b	734	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
AnnaBridge	165:d1b4690b3f8b	735	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
AnnaBridge	165:d1b4690b3f8b	736	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
AnnaBridge	165:d1b4690b3f8b	737	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
AnnaBridge	165:d1b4690b3f8b	738	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
AnnaBridge	165:d1b4690b3f8b	739	/**
AnnaBridge	165:d1b4690b3f8b	740	* @}
AnnaBridge	165:d1b4690b3f8b	741	*/
AnnaBridge	165:d1b4690b3f8b	742
AnnaBridge	165:d1b4690b3f8b	743	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	165:d1b4690b3f8b	744	* @{
AnnaBridge	165:d1b4690b3f8b	745	*/
AnnaBridge	165:d1b4690b3f8b	746	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	165:d1b4690b3f8b	747	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	165:d1b4690b3f8b	748	/**
AnnaBridge	165:d1b4690b3f8b	749	* @}
AnnaBridge	165:d1b4690b3f8b	750	*/
AnnaBridge	165:d1b4690b3f8b	751
AnnaBridge	165:d1b4690b3f8b	752	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	165:d1b4690b3f8b	753	* @{
AnnaBridge	165:d1b4690b3f8b	754	*/
AnnaBridge	165:d1b4690b3f8b	755	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	165:d1b4690b3f8b	756	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	165:d1b4690b3f8b	757	/**
AnnaBridge	165:d1b4690b3f8b	758	* @}
AnnaBridge	165:d1b4690b3f8b	759	*/
AnnaBridge	165:d1b4690b3f8b	760
AnnaBridge	165:d1b4690b3f8b	761	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
AnnaBridge	165:d1b4690b3f8b	762	* @{
AnnaBridge	165:d1b4690b3f8b	763	*/
AnnaBridge	165:d1b4690b3f8b	764	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
AnnaBridge	165:d1b4690b3f8b	765	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
AnnaBridge	165:d1b4690b3f8b	766	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
AnnaBridge	165:d1b4690b3f8b	767	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
AnnaBridge	165:d1b4690b3f8b	768	/**
AnnaBridge	165:d1b4690b3f8b	769	* @}
AnnaBridge	165:d1b4690b3f8b	770	*/
AnnaBridge	165:d1b4690b3f8b	771
AnnaBridge	165:d1b4690b3f8b	772	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	165:d1b4690b3f8b	773	* @{
AnnaBridge	165:d1b4690b3f8b	774	*/
AnnaBridge	165:d1b4690b3f8b	775	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	165:d1b4690b3f8b	776	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	165:d1b4690b3f8b	777	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	165:d1b4690b3f8b	778	/**
AnnaBridge	165:d1b4690b3f8b	779	* @}
AnnaBridge	165:d1b4690b3f8b	780	*/
AnnaBridge	165:d1b4690b3f8b	781
AnnaBridge	165:d1b4690b3f8b	782	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	165:d1b4690b3f8b	783	* @{
AnnaBridge	165:d1b4690b3f8b	784	*/
AnnaBridge	165:d1b4690b3f8b	785	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	165:d1b4690b3f8b	786	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	165:d1b4690b3f8b	787	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	165:d1b4690b3f8b	788	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	165:d1b4690b3f8b	789	/**
AnnaBridge	165:d1b4690b3f8b	790	* @}
AnnaBridge	165:d1b4690b3f8b	791	*/
AnnaBridge	165:d1b4690b3f8b	792
AnnaBridge	165:d1b4690b3f8b	793	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	165:d1b4690b3f8b	794	* @{
AnnaBridge	165:d1b4690b3f8b	795	*/
AnnaBridge	165:d1b4690b3f8b	796	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	165:d1b4690b3f8b	797	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:d1b4690b3f8b	798	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:d1b4690b3f8b	799	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:d1b4690b3f8b	800	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:d1b4690b3f8b	801	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:d1b4690b3f8b	802	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:d1b4690b3f8b	803	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:d1b4690b3f8b	804	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	165:d1b4690b3f8b	805	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:d1b4690b3f8b	806	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:d1b4690b3f8b	807	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:d1b4690b3f8b	808	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:d1b4690b3f8b	809	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:d1b4690b3f8b	810	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:d1b4690b3f8b	811	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:d1b4690b3f8b	812	/**
AnnaBridge	165:d1b4690b3f8b	813	* @}
AnnaBridge	165:d1b4690b3f8b	814	*/
AnnaBridge	165:d1b4690b3f8b	815
AnnaBridge	165:d1b4690b3f8b	816	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	165:d1b4690b3f8b	817	* @{
AnnaBridge	165:d1b4690b3f8b	818	*/
AnnaBridge	165:d1b4690b3f8b	819	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	165:d1b4690b3f8b	820	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	165:d1b4690b3f8b	821	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	165:d1b4690b3f8b	822	/**
AnnaBridge	165:d1b4690b3f8b	823	* @}
AnnaBridge	165:d1b4690b3f8b	824	*/
AnnaBridge	165:d1b4690b3f8b	825
AnnaBridge	165:d1b4690b3f8b	826	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	165:d1b4690b3f8b	827	* @{
AnnaBridge	165:d1b4690b3f8b	828	*/
AnnaBridge	165:d1b4690b3f8b	829	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	165:d1b4690b3f8b	830	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
AnnaBridge	165:d1b4690b3f8b	831	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	165:d1b4690b3f8b	832	/**
AnnaBridge	165:d1b4690b3f8b	833	* @}
AnnaBridge	165:d1b4690b3f8b	834	*/
AnnaBridge	165:d1b4690b3f8b	835
AnnaBridge	165:d1b4690b3f8b	836	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	165:d1b4690b3f8b	837	* @{
AnnaBridge	165:d1b4690b3f8b	838	*/
AnnaBridge	165:d1b4690b3f8b	839	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	165:d1b4690b3f8b	840	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	165:d1b4690b3f8b	841	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
AnnaBridge	165:d1b4690b3f8b	842	/**
AnnaBridge	165:d1b4690b3f8b	843	* @}
AnnaBridge	165:d1b4690b3f8b	844	*/
AnnaBridge	165:d1b4690b3f8b	845
AnnaBridge	165:d1b4690b3f8b	846	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	165:d1b4690b3f8b	847	* @{
AnnaBridge	165:d1b4690b3f8b	848	*/
AnnaBridge	165:d1b4690b3f8b	849	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	850	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	851	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	852	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	853	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	854	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	855	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	856	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	165:d1b4690b3f8b	857	/**
AnnaBridge	165:d1b4690b3f8b	858	* @}
AnnaBridge	165:d1b4690b3f8b	859	*/
AnnaBridge	165:d1b4690b3f8b	860
AnnaBridge	165:d1b4690b3f8b	861	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
AnnaBridge	165:d1b4690b3f8b	862	* @{
AnnaBridge	165:d1b4690b3f8b	863	*/
AnnaBridge	165:d1b4690b3f8b	864	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	865	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	866	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	867	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	868	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	869	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	870	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	871	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	872	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	873	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	874	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	875	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	876	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	877	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	878	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	879	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	165:d1b4690b3f8b	880	/**
AnnaBridge	165:d1b4690b3f8b	881	* @}
AnnaBridge	165:d1b4690b3f8b	882	*/
AnnaBridge	165:d1b4690b3f8b	883
AnnaBridge	165:d1b4690b3f8b	884	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	165:d1b4690b3f8b	885	* @{
AnnaBridge	165:d1b4690b3f8b	886	*/
AnnaBridge	165:d1b4690b3f8b	887	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	165:d1b4690b3f8b	888	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	165:d1b4690b3f8b	889	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	165:d1b4690b3f8b	890	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	165:d1b4690b3f8b	891	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
AnnaBridge	165:d1b4690b3f8b	892	/**
AnnaBridge	165:d1b4690b3f8b	893	* @}
AnnaBridge	165:d1b4690b3f8b	894	*/
AnnaBridge	165:d1b4690b3f8b	895
AnnaBridge	165:d1b4690b3f8b	896	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	165:d1b4690b3f8b	897	* @{
AnnaBridge	165:d1b4690b3f8b	898	*/
AnnaBridge	165:d1b4690b3f8b	899	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	900	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	901	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	902	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	903	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	904	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	905	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	906	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	165:d1b4690b3f8b	907	/**
AnnaBridge	165:d1b4690b3f8b	908	* @}
AnnaBridge	165:d1b4690b3f8b	909	*/
AnnaBridge	165:d1b4690b3f8b	910
AnnaBridge	165:d1b4690b3f8b	911	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	165:d1b4690b3f8b	912	* @{
AnnaBridge	165:d1b4690b3f8b	913	*/
AnnaBridge	165:d1b4690b3f8b	914	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	165:d1b4690b3f8b	915	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	165:d1b4690b3f8b	916	/**
AnnaBridge	165:d1b4690b3f8b	917	* @}
AnnaBridge	165:d1b4690b3f8b	918	*/
AnnaBridge	165:d1b4690b3f8b	919
AnnaBridge	165:d1b4690b3f8b	920	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	165:d1b4690b3f8b	921	* @{
AnnaBridge	165:d1b4690b3f8b	922	*/
AnnaBridge	165:d1b4690b3f8b	923	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	165:d1b4690b3f8b	924	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	165:d1b4690b3f8b	925	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	165:d1b4690b3f8b	926	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	165:d1b4690b3f8b	927	/**
AnnaBridge	165:d1b4690b3f8b	928	* @}
AnnaBridge	165:d1b4690b3f8b	929	*/
AnnaBridge	165:d1b4690b3f8b	930
AnnaBridge	165:d1b4690b3f8b	931	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	165:d1b4690b3f8b	932	* @{
AnnaBridge	165:d1b4690b3f8b	933	*/
AnnaBridge	165:d1b4690b3f8b	934	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	165:d1b4690b3f8b	935	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:d1b4690b3f8b	936	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:d1b4690b3f8b	937	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:d1b4690b3f8b	938	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:d1b4690b3f8b	939	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:d1b4690b3f8b	940	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:d1b4690b3f8b	941	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:d1b4690b3f8b	942	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:d1b4690b3f8b	943	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:d1b4690b3f8b	944	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:d1b4690b3f8b	945	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:d1b4690b3f8b	946	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:d1b4690b3f8b	947	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:d1b4690b3f8b	948	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:d1b4690b3f8b	949	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:d1b4690b3f8b	950	/**
AnnaBridge	165:d1b4690b3f8b	951	* @}
AnnaBridge	165:d1b4690b3f8b	952	*/
AnnaBridge	165:d1b4690b3f8b	953
AnnaBridge	165:d1b4690b3f8b	954	/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
AnnaBridge	165:d1b4690b3f8b	955	* @{
AnnaBridge	165:d1b4690b3f8b	956	*/
AnnaBridge	165:d1b4690b3f8b	957	#define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /!< ETR legacy mode /
AnnaBridge	165:d1b4690b3f8b	958	#define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /!< COMP1 output connected to ETR input /
AnnaBridge	165:d1b4690b3f8b	959	#define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /!< COMP2 output connected to ETR input /
AnnaBridge	165:d1b4690b3f8b	960	/**
AnnaBridge	165:d1b4690b3f8b	961	* @}
AnnaBridge	165:d1b4690b3f8b	962	*/
AnnaBridge	165:d1b4690b3f8b	963
AnnaBridge	165:d1b4690b3f8b	964	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	165:d1b4690b3f8b	965	* @{
AnnaBridge	165:d1b4690b3f8b	966	*/
AnnaBridge	165:d1b4690b3f8b	967	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	165:d1b4690b3f8b	968	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	165:d1b4690b3f8b	969	/**
AnnaBridge	165:d1b4690b3f8b	970	* @}
AnnaBridge	165:d1b4690b3f8b	971	*/
AnnaBridge	165:d1b4690b3f8b	972
AnnaBridge	165:d1b4690b3f8b	973	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
AnnaBridge	165:d1b4690b3f8b	974	* @{
AnnaBridge	165:d1b4690b3f8b	975	*/
AnnaBridge	165:d1b4690b3f8b	976	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	165:d1b4690b3f8b	977	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:d1b4690b3f8b	978	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:d1b4690b3f8b	979	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:d1b4690b3f8b	980	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:d1b4690b3f8b	981	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:d1b4690b3f8b	982	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:d1b4690b3f8b	983	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:d1b4690b3f8b	984	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	165:d1b4690b3f8b	985	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:d1b4690b3f8b	986	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:d1b4690b3f8b	987	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:d1b4690b3f8b	988	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:d1b4690b3f8b	989	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:d1b4690b3f8b	990	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:d1b4690b3f8b	991	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:d1b4690b3f8b	992	/**
AnnaBridge	165:d1b4690b3f8b	993	* @}
AnnaBridge	165:d1b4690b3f8b	994	*/
AnnaBridge	165:d1b4690b3f8b	995
AnnaBridge	165:d1b4690b3f8b	996	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
AnnaBridge	165:d1b4690b3f8b	997	* @{
AnnaBridge	165:d1b4690b3f8b	998	*/
AnnaBridge	165:d1b4690b3f8b	999	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
AnnaBridge	165:d1b4690b3f8b	1000	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
AnnaBridge	165:d1b4690b3f8b	1001	/**
AnnaBridge	165:d1b4690b3f8b	1002	* @}
AnnaBridge	165:d1b4690b3f8b	1003	*/
AnnaBridge	165:d1b4690b3f8b	1004
AnnaBridge	165:d1b4690b3f8b	1005	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
AnnaBridge	165:d1b4690b3f8b	1006	* @{
AnnaBridge	165:d1b4690b3f8b	1007	*/
AnnaBridge	165:d1b4690b3f8b	1008	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	165:d1b4690b3f8b	1009	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:d1b4690b3f8b	1010	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:d1b4690b3f8b	1011	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:d1b4690b3f8b	1012	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:d1b4690b3f8b	1013	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:d1b4690b3f8b	1014	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:d1b4690b3f8b	1015	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:d1b4690b3f8b	1016	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	165:d1b4690b3f8b	1017	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:d1b4690b3f8b	1018	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:d1b4690b3f8b	1019	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:d1b4690b3f8b	1020	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:d1b4690b3f8b	1021	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:d1b4690b3f8b	1022	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:d1b4690b3f8b	1023	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:d1b4690b3f8b	1024	/**
AnnaBridge	165:d1b4690b3f8b	1025	* @}
AnnaBridge	165:d1b4690b3f8b	1026	*/
AnnaBridge	165:d1b4690b3f8b	1027
AnnaBridge	165:d1b4690b3f8b	1028	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	165:d1b4690b3f8b	1029	* @{
AnnaBridge	165:d1b4690b3f8b	1030	*/
AnnaBridge	165:d1b4690b3f8b	1031	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	165:d1b4690b3f8b	1032	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	165:d1b4690b3f8b	1033	/**
AnnaBridge	165:d1b4690b3f8b	1034	* @}
AnnaBridge	165:d1b4690b3f8b	1035	*/
AnnaBridge	165:d1b4690b3f8b	1036
AnnaBridge	165:d1b4690b3f8b	1037	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	165:d1b4690b3f8b	1038	* @{
AnnaBridge	165:d1b4690b3f8b	1039	*/
AnnaBridge	165:d1b4690b3f8b	1040	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	165:d1b4690b3f8b	1041	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	165:d1b4690b3f8b	1042	/**
AnnaBridge	165:d1b4690b3f8b	1043	* @}
AnnaBridge	165:d1b4690b3f8b	1044	*/
AnnaBridge	165:d1b4690b3f8b	1045
AnnaBridge	165:d1b4690b3f8b	1046	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
AnnaBridge	165:d1b4690b3f8b	1047	* @{
AnnaBridge	165:d1b4690b3f8b	1048	*/
AnnaBridge	165:d1b4690b3f8b	1049	#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /!< TIMx_BKIN input /
AnnaBridge	165:d1b4690b3f8b	1050	#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /!< TIMx_BKIN2 input /
AnnaBridge	165:d1b4690b3f8b	1051	/**
AnnaBridge	165:d1b4690b3f8b	1052	* @}
AnnaBridge	165:d1b4690b3f8b	1053	*/
AnnaBridge	165:d1b4690b3f8b	1054
AnnaBridge	165:d1b4690b3f8b	1055	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
AnnaBridge	165:d1b4690b3f8b	1056	* @{
AnnaBridge	165:d1b4690b3f8b	1057	*/
AnnaBridge	165:d1b4690b3f8b	1058	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /!< BKIN input from AF controller /
AnnaBridge	165:d1b4690b3f8b	1059	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /!< internal signal: COMP1 output /
AnnaBridge	165:d1b4690b3f8b	1060	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /!< internal signal: COMP2 output /
AnnaBridge	165:d1b4690b3f8b	1061	#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /!< internal signal: DFSDM1 break output /
AnnaBridge	165:d1b4690b3f8b	1062	/**
AnnaBridge	165:d1b4690b3f8b	1063	* @}
AnnaBridge	165:d1b4690b3f8b	1064	*/
AnnaBridge	165:d1b4690b3f8b	1065
AnnaBridge	165:d1b4690b3f8b	1066	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
AnnaBridge	165:d1b4690b3f8b	1067	* @{
AnnaBridge	165:d1b4690b3f8b	1068	*/
AnnaBridge	165:d1b4690b3f8b	1069	#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /!< BRK BKIN input is active low /
AnnaBridge	165:d1b4690b3f8b	1070	#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /!< BRK BKIN input is active high /
AnnaBridge	165:d1b4690b3f8b	1071	/**
AnnaBridge	165:d1b4690b3f8b	1072	* @}
AnnaBridge	165:d1b4690b3f8b	1073	*/
AnnaBridge	165:d1b4690b3f8b	1074
AnnaBridge	165:d1b4690b3f8b	1075	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	165:d1b4690b3f8b	1076	* @{
AnnaBridge	165:d1b4690b3f8b	1077	*/
AnnaBridge	165:d1b4690b3f8b	1078	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1079	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1080	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1081	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1082	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1083	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1084	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1085	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1086	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1087	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1088	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1089	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1090	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1091	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1092	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1093	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1094	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1095	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1096	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1097	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1098	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1099	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR1 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1100	#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_OR2 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1101	#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_OR3 register is the DMA base address for DMA burst /
AnnaBridge	165:d1b4690b3f8b	1102	/**
AnnaBridge	165:d1b4690b3f8b	1103	* @}
AnnaBridge	165:d1b4690b3f8b	1104	*/
AnnaBridge	165:d1b4690b3f8b	1105
AnnaBridge	165:d1b4690b3f8b	1106	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	165:d1b4690b3f8b	1107	* @{
AnnaBridge	165:d1b4690b3f8b	1108	*/
AnnaBridge	165:d1b4690b3f8b	1109	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1110	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1111	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1112	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1113	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1114	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1115	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1116	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1117	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1118	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1119	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1120	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1121	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1122	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1123	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1124	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1125	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1126	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	165:d1b4690b3f8b	1127	/**
AnnaBridge	165:d1b4690b3f8b	1128	* @}
AnnaBridge	165:d1b4690b3f8b	1129	*/
AnnaBridge	165:d1b4690b3f8b	1130
AnnaBridge	165:d1b4690b3f8b	1131	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
AnnaBridge	165:d1b4690b3f8b	1132	* @{
AnnaBridge	165:d1b4690b3f8b	1133	*/
AnnaBridge	165:d1b4690b3f8b	1134	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
AnnaBridge	165:d1b4690b3f8b	1135	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
AnnaBridge	165:d1b4690b3f8b	1136	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
AnnaBridge	165:d1b4690b3f8b	1137	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
AnnaBridge	165:d1b4690b3f8b	1138	/**
AnnaBridge	165:d1b4690b3f8b	1139	* @}
AnnaBridge	165:d1b4690b3f8b	1140	*/
AnnaBridge	165:d1b4690b3f8b	1141
AnnaBridge	165:d1b4690b3f8b	1142	#if defined(ADC3)
AnnaBridge	165:d1b4690b3f8b	1143	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
AnnaBridge	165:d1b4690b3f8b	1144	* @{
AnnaBridge	165:d1b4690b3f8b	1145	*/
AnnaBridge	165:d1b4690b3f8b	1146	#define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /!< TIM1_ETR is not connected to ADC3 analog watchdog x/
AnnaBridge	165:d1b4690b3f8b	1147	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 1 /
AnnaBridge	165:d1b4690b3f8b	1148	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	165:d1b4690b3f8b	1149	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	165:d1b4690b3f8b	1150	/**
AnnaBridge	165:d1b4690b3f8b	1151	* @}
AnnaBridge	165:d1b4690b3f8b	1152	*/
AnnaBridge	165:d1b4690b3f8b	1153	#endif /* ADC3 */
AnnaBridge	165:d1b4690b3f8b	1154
AnnaBridge	165:d1b4690b3f8b	1155	/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1156	* @{
AnnaBridge	165:d1b4690b3f8b	1157	*/
AnnaBridge	165:d1b4690b3f8b	1158	#define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /!< TIM1 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1159	#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to COMP1 output /
AnnaBridge	165:d1b4690b3f8b	1160	/**
AnnaBridge	165:d1b4690b3f8b	1161	* @}
AnnaBridge	165:d1b4690b3f8b	1162	*/
AnnaBridge	165:d1b4690b3f8b	1163
AnnaBridge	165:d1b4690b3f8b	1164	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
AnnaBridge	165:d1b4690b3f8b	1165	* @{
AnnaBridge	165:d1b4690b3f8b	1166	*/
AnnaBridge	165:d1b4690b3f8b	1167	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1168	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
AnnaBridge	165:d1b4690b3f8b	1169	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
AnnaBridge	165:d1b4690b3f8b	1170	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	165:d1b4690b3f8b	1171	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	165:d1b4690b3f8b	1172	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	1173	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	165:d1b4690b3f8b	1174	#define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
AnnaBridge	165:d1b4690b3f8b	1175	#define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
AnnaBridge	165:d1b4690b3f8b	1176	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L442xx \|\| STM32L433xx \|\| STM32L443xx \|\| */
AnnaBridge	165:d1b4690b3f8b	1177	/* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
AnnaBridge	165:d1b4690b3f8b	1178	#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /!< TIM2_ETR is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1179	#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to LSE /
AnnaBridge	165:d1b4690b3f8b	1180	/**
AnnaBridge	165:d1b4690b3f8b	1181	* @}
AnnaBridge	165:d1b4690b3f8b	1182	*/
AnnaBridge	165:d1b4690b3f8b	1183
AnnaBridge	165:d1b4690b3f8b	1184	/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
AnnaBridge	165:d1b4690b3f8b	1185	* @{
AnnaBridge	165:d1b4690b3f8b	1186	*/
AnnaBridge	165:d1b4690b3f8b	1187	#define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /!< TIM2 input capture 4 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1188	#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP1_OUT /
AnnaBridge	165:d1b4690b3f8b	1189	#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP2_OUT /
AnnaBridge	165:d1b4690b3f8b	1190	#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT /
AnnaBridge	165:d1b4690b3f8b	1191	/**
AnnaBridge	165:d1b4690b3f8b	1192	* @}
AnnaBridge	165:d1b4690b3f8b	1193	*/
AnnaBridge	165:d1b4690b3f8b	1194
AnnaBridge	165:d1b4690b3f8b	1195	#if defined(TIM3)
AnnaBridge	165:d1b4690b3f8b	1196	/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1197	* @{
AnnaBridge	165:d1b4690b3f8b	1198	*/
AnnaBridge	165:d1b4690b3f8b	1199	#define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /!< TIM3 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1200	#define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP1_OUT /
AnnaBridge	165:d1b4690b3f8b	1201	#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP2_OUT /
AnnaBridge	165:d1b4690b3f8b	1202	#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT /
AnnaBridge	165:d1b4690b3f8b	1203	/**
AnnaBridge	165:d1b4690b3f8b	1204	* @}
AnnaBridge	165:d1b4690b3f8b	1205	*/
AnnaBridge	165:d1b4690b3f8b	1206	#endif /* TIM3 */
AnnaBridge	165:d1b4690b3f8b	1207
AnnaBridge	165:d1b4690b3f8b	1208	#if defined(TIM8)
AnnaBridge	165:d1b4690b3f8b	1209	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
AnnaBridge	165:d1b4690b3f8b	1210	* @{
AnnaBridge	165:d1b4690b3f8b	1211	*/
AnnaBridge	165:d1b4690b3f8b	1212	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
AnnaBridge	165:d1b4690b3f8b	1213	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
AnnaBridge	165:d1b4690b3f8b	1214	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
AnnaBridge	165:d1b4690b3f8b	1215	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
AnnaBridge	165:d1b4690b3f8b	1216	/**
AnnaBridge	165:d1b4690b3f8b	1217	* @}
AnnaBridge	165:d1b4690b3f8b	1218	*/
AnnaBridge	165:d1b4690b3f8b	1219
AnnaBridge	165:d1b4690b3f8b	1220	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
AnnaBridge	165:d1b4690b3f8b	1221	* @{
AnnaBridge	165:d1b4690b3f8b	1222	*/
AnnaBridge	165:d1b4690b3f8b	1223	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
AnnaBridge	165:d1b4690b3f8b	1224	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
AnnaBridge	165:d1b4690b3f8b	1225	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	165:d1b4690b3f8b	1226	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	165:d1b4690b3f8b	1227	/**
AnnaBridge	165:d1b4690b3f8b	1228	* @}
AnnaBridge	165:d1b4690b3f8b	1229	*/
AnnaBridge	165:d1b4690b3f8b	1230
AnnaBridge	165:d1b4690b3f8b	1231	/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1232	* @{
AnnaBridge	165:d1b4690b3f8b	1233	*/
AnnaBridge	165:d1b4690b3f8b	1234	#define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /!< TIM8 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1235	#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to COMP2 output /
AnnaBridge	165:d1b4690b3f8b	1236	/**
AnnaBridge	165:d1b4690b3f8b	1237	* @}
AnnaBridge	165:d1b4690b3f8b	1238	*/
AnnaBridge	165:d1b4690b3f8b	1239	#endif /* TIM8 */
AnnaBridge	165:d1b4690b3f8b	1240
AnnaBridge	165:d1b4690b3f8b	1241	/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1242	* @{
AnnaBridge	165:d1b4690b3f8b	1243	*/
AnnaBridge	165:d1b4690b3f8b	1244	#define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /!< TIM15 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1245	#define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to LSE /
AnnaBridge	165:d1b4690b3f8b	1246	/**
AnnaBridge	165:d1b4690b3f8b	1247	* @}
AnnaBridge	165:d1b4690b3f8b	1248	*/
AnnaBridge	165:d1b4690b3f8b	1249
AnnaBridge	165:d1b4690b3f8b	1250	/** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
AnnaBridge	165:d1b4690b3f8b	1251	* @{
AnnaBridge	165:d1b4690b3f8b	1252	*/
AnnaBridge	165:d1b4690b3f8b	1253	#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /!< No redirection/
AnnaBridge	165:d1b4690b3f8b	1254	#define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 \| TIM15_OR1_RMP_MASK) /!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
AnnaBridge	165:d1b4690b3f8b	1255	#define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 \| TIM15_OR1_RMP_MASK) /!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y/
AnnaBridge	165:d1b4690b3f8b	1256	#define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE \| TIM15_OR1_RMP_MASK) /!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
AnnaBridge	165:d1b4690b3f8b	1257	/**
AnnaBridge	165:d1b4690b3f8b	1258	* @}
AnnaBridge	165:d1b4690b3f8b	1259	*/
AnnaBridge	165:d1b4690b3f8b	1260
AnnaBridge	165:d1b4690b3f8b	1261	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1262	* @{
AnnaBridge	165:d1b4690b3f8b	1263	*/
AnnaBridge	165:d1b4690b3f8b	1264	#define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /!< TIM16 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1265	#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSI /
AnnaBridge	165:d1b4690b3f8b	1266	#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSE /
AnnaBridge	165:d1b4690b3f8b	1267	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup interrupt /
AnnaBridge	165:d1b4690b3f8b	1268	#if defined TIM16_OR1_TI1_RMP_2
AnnaBridge	165:d1b4690b3f8b	1269	#define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MSI /
AnnaBridge	165:d1b4690b3f8b	1270	#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to HSE/32 /
AnnaBridge	165:d1b4690b3f8b	1271	#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MCO /
AnnaBridge	165:d1b4690b3f8b	1272	#endif
AnnaBridge	165:d1b4690b3f8b	1273	/**
AnnaBridge	165:d1b4690b3f8b	1274	* @}
AnnaBridge	165:d1b4690b3f8b	1275	*/
AnnaBridge	165:d1b4690b3f8b	1276
AnnaBridge	165:d1b4690b3f8b	1277	#if defined(TIM17)
AnnaBridge	165:d1b4690b3f8b	1278	/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
AnnaBridge	165:d1b4690b3f8b	1279	* @{
AnnaBridge	165:d1b4690b3f8b	1280	*/
AnnaBridge	165:d1b4690b3f8b	1281	#define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /!< TIM17 input capture 1 is connected to GPIO /
AnnaBridge	165:d1b4690b3f8b	1282	#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MSI /
AnnaBridge	165:d1b4690b3f8b	1283	#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to HSE/32 /
AnnaBridge	165:d1b4690b3f8b	1284	#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MCO /
AnnaBridge	165:d1b4690b3f8b	1285	/**
AnnaBridge	165:d1b4690b3f8b	1286	* @}
AnnaBridge	165:d1b4690b3f8b	1287	*/
AnnaBridge	165:d1b4690b3f8b	1288	#endif /* TIM17 */
AnnaBridge	165:d1b4690b3f8b	1289
AnnaBridge	165:d1b4690b3f8b	1290	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	165:d1b4690b3f8b	1291	* @{
AnnaBridge	165:d1b4690b3f8b	1292	*/
AnnaBridge	165:d1b4690b3f8b	1293	#define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /!< OCREF_CLR_INT is not connected /
AnnaBridge	165:d1b4690b3f8b	1294	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	165:d1b4690b3f8b	1295	/**
AnnaBridge	165:d1b4690b3f8b	1296	* @}
AnnaBridge	165:d1b4690b3f8b	1297	*/
AnnaBridge	165:d1b4690b3f8b	1298
AnnaBridge	165:d1b4690b3f8b	1299	/** Legacy definitions for compatibility purpose
AnnaBridge	165:d1b4690b3f8b	1300	@cond 0
AnnaBridge	165:d1b4690b3f8b	1301	*/
AnnaBridge	165:d1b4690b3f8b	1302	#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	165:d1b4690b3f8b	1303	/**
AnnaBridge	165:d1b4690b3f8b	1304	@endcond
AnnaBridge	165:d1b4690b3f8b	1305	*/
AnnaBridge	165:d1b4690b3f8b	1306	/**
AnnaBridge	165:d1b4690b3f8b	1307	* @}
AnnaBridge	165:d1b4690b3f8b	1308	*/
AnnaBridge	165:d1b4690b3f8b	1309
AnnaBridge	165:d1b4690b3f8b	1310	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1311	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	165:d1b4690b3f8b	1312	* @{
AnnaBridge	165:d1b4690b3f8b	1313	*/
AnnaBridge	165:d1b4690b3f8b	1314
AnnaBridge	165:d1b4690b3f8b	1315	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:d1b4690b3f8b	1316	* @{
AnnaBridge	165:d1b4690b3f8b	1317	*/
AnnaBridge	165:d1b4690b3f8b	1318	/**
AnnaBridge	165:d1b4690b3f8b	1319	* @brief Write a value in TIM register.
AnnaBridge	165:d1b4690b3f8b	1320	* @param __INSTANCE__ TIM Instance
AnnaBridge	165:d1b4690b3f8b	1321	* @param __REG__ Register to be written
AnnaBridge	165:d1b4690b3f8b	1322	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:d1b4690b3f8b	1323	* @retval None
AnnaBridge	165:d1b4690b3f8b	1324	*/
AnnaBridge	165:d1b4690b3f8b	1325	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	165:d1b4690b3f8b	1326
AnnaBridge	165:d1b4690b3f8b	1327	/**
AnnaBridge	165:d1b4690b3f8b	1328	* @brief Read a value in TIM register.
AnnaBridge	165:d1b4690b3f8b	1329	* @param __INSTANCE__ TIM Instance
AnnaBridge	165:d1b4690b3f8b	1330	* @param __REG__ Register to be read
AnnaBridge	165:d1b4690b3f8b	1331	* @retval Register value
AnnaBridge	165:d1b4690b3f8b	1332	*/
AnnaBridge	165:d1b4690b3f8b	1333	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	165:d1b4690b3f8b	1334	/**
AnnaBridge	165:d1b4690b3f8b	1335	* @}
AnnaBridge	165:d1b4690b3f8b	1336	*/
AnnaBridge	165:d1b4690b3f8b	1337
AnnaBridge	165:d1b4690b3f8b	1338	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	165:d1b4690b3f8b	1339	* @{
AnnaBridge	165:d1b4690b3f8b	1340	*/
AnnaBridge	165:d1b4690b3f8b	1341
AnnaBridge	165:d1b4690b3f8b	1342	/**
AnnaBridge	165:d1b4690b3f8b	1343	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
AnnaBridge	165:d1b4690b3f8b	1344	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
AnnaBridge	165:d1b4690b3f8b	1345	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
AnnaBridge	165:d1b4690b3f8b	1346	* to TIMx_CNT register bit 31)
AnnaBridge	165:d1b4690b3f8b	1347	* @param __CNT__ Counter value
AnnaBridge	165:d1b4690b3f8b	1348	* @retval UIF status bit
AnnaBridge	165:d1b4690b3f8b	1349	*/
AnnaBridge	165:d1b4690b3f8b	1350	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
AnnaBridge	165:d1b4690b3f8b	1351	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
AnnaBridge	165:d1b4690b3f8b	1352
AnnaBridge	165:d1b4690b3f8b	1353	/**
AnnaBridge	165:d1b4690b3f8b	1354	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	165:d1b4690b3f8b	1355	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	165:d1b4690b3f8b	1356	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1357	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1358	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:d1b4690b3f8b	1359	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:d1b4690b3f8b	1360	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:d1b4690b3f8b	1361	* @param __DT__ deadtime duration (in ns)
AnnaBridge	165:d1b4690b3f8b	1362	* @retval DTG[0:7]
AnnaBridge	165:d1b4690b3f8b	1363	*/
AnnaBridge	165:d1b4690b3f8b	1364	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	165:d1b4690b3f8b	1365	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	165:d1b4690b3f8b	1366	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
AnnaBridge	165:d1b4690b3f8b	1367	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
AnnaBridge	165:d1b4690b3f8b	1368	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
AnnaBridge	165:d1b4690b3f8b	1369	0U)
AnnaBridge	165:d1b4690b3f8b	1370
AnnaBridge	165:d1b4690b3f8b	1371	/**
AnnaBridge	165:d1b4690b3f8b	1372	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	165:d1b4690b3f8b	1373	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	165:d1b4690b3f8b	1374	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1375	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1376	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	1377	*/
AnnaBridge	165:d1b4690b3f8b	1378	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	165:d1b4690b3f8b	1379	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	165:d1b4690b3f8b	1380
AnnaBridge	165:d1b4690b3f8b	1381	/**
AnnaBridge	165:d1b4690b3f8b	1382	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	165:d1b4690b3f8b	1383	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	165:d1b4690b3f8b	1384	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1385	* @param __PSC__ prescaler
AnnaBridge	165:d1b4690b3f8b	1386	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1387	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	1388	*/
AnnaBridge	165:d1b4690b3f8b	1389	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	165:d1b4690b3f8b	1390	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	165:d1b4690b3f8b	1391
AnnaBridge	165:d1b4690b3f8b	1392	/**
AnnaBridge	165:d1b4690b3f8b	1393	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	165:d1b4690b3f8b	1394	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	165:d1b4690b3f8b	1395	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1396	* @param __PSC__ prescaler
AnnaBridge	165:d1b4690b3f8b	1397	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	165:d1b4690b3f8b	1398	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	1399	*/
AnnaBridge	165:d1b4690b3f8b	1400	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	165:d1b4690b3f8b	1401	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	165:d1b4690b3f8b	1402	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	165:d1b4690b3f8b	1403
AnnaBridge	165:d1b4690b3f8b	1404	/**
AnnaBridge	165:d1b4690b3f8b	1405	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	165:d1b4690b3f8b	1406	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	165:d1b4690b3f8b	1407	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1408	* @param __PSC__ prescaler
AnnaBridge	165:d1b4690b3f8b	1409	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	165:d1b4690b3f8b	1410	* @param __PULSE__ pulse duration (in us)
AnnaBridge	165:d1b4690b3f8b	1411	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	1412	*/
AnnaBridge	165:d1b4690b3f8b	1413	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	165:d1b4690b3f8b	1414	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	165:d1b4690b3f8b	1415	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	165:d1b4690b3f8b	1416
AnnaBridge	165:d1b4690b3f8b	1417	/**
AnnaBridge	165:d1b4690b3f8b	1418	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	165:d1b4690b3f8b	1419	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	165:d1b4690b3f8b	1420	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1421	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:d1b4690b3f8b	1422	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:d1b4690b3f8b	1423	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:d1b4690b3f8b	1424	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:d1b4690b3f8b	1425	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	165:d1b4690b3f8b	1426	*/
AnnaBridge	165:d1b4690b3f8b	1427	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	165:d1b4690b3f8b	1428	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	165:d1b4690b3f8b	1429
AnnaBridge	165:d1b4690b3f8b	1430
AnnaBridge	165:d1b4690b3f8b	1431	/**
AnnaBridge	165:d1b4690b3f8b	1432	* @}
AnnaBridge	165:d1b4690b3f8b	1433	*/
AnnaBridge	165:d1b4690b3f8b	1434
AnnaBridge	165:d1b4690b3f8b	1435
AnnaBridge	165:d1b4690b3f8b	1436	/**
AnnaBridge	165:d1b4690b3f8b	1437	* @}
AnnaBridge	165:d1b4690b3f8b	1438	*/
AnnaBridge	165:d1b4690b3f8b	1439
AnnaBridge	165:d1b4690b3f8b	1440	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1441	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	165:d1b4690b3f8b	1442	* @{
AnnaBridge	165:d1b4690b3f8b	1443	*/
AnnaBridge	165:d1b4690b3f8b	1444
AnnaBridge	165:d1b4690b3f8b	1445	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	165:d1b4690b3f8b	1446	* @{
AnnaBridge	165:d1b4690b3f8b	1447	*/
AnnaBridge	165:d1b4690b3f8b	1448	/**
AnnaBridge	165:d1b4690b3f8b	1449	* @brief Enable timer counter.
AnnaBridge	165:d1b4690b3f8b	1450	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	165:d1b4690b3f8b	1451	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1452	* @retval None
AnnaBridge	165:d1b4690b3f8b	1453	*/
AnnaBridge	165:d1b4690b3f8b	1454	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1455	{
AnnaBridge	165:d1b4690b3f8b	1456	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	165:d1b4690b3f8b	1457	}
AnnaBridge	165:d1b4690b3f8b	1458
AnnaBridge	165:d1b4690b3f8b	1459	/**
AnnaBridge	165:d1b4690b3f8b	1460	* @brief Disable timer counter.
AnnaBridge	165:d1b4690b3f8b	1461	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	165:d1b4690b3f8b	1462	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1463	* @retval None
AnnaBridge	165:d1b4690b3f8b	1464	*/
AnnaBridge	165:d1b4690b3f8b	1465	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1466	{
AnnaBridge	165:d1b4690b3f8b	1467	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	165:d1b4690b3f8b	1468	}
AnnaBridge	165:d1b4690b3f8b	1469
AnnaBridge	165:d1b4690b3f8b	1470	/**
AnnaBridge	165:d1b4690b3f8b	1471	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	165:d1b4690b3f8b	1472	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	165:d1b4690b3f8b	1473	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1474	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	1475	*/
AnnaBridge	165:d1b4690b3f8b	1476	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1477	{
AnnaBridge	165:d1b4690b3f8b	1478	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	165:d1b4690b3f8b	1479	}
AnnaBridge	165:d1b4690b3f8b	1480
AnnaBridge	165:d1b4690b3f8b	1481	/**
AnnaBridge	165:d1b4690b3f8b	1482	* @brief Enable update event generation.
AnnaBridge	165:d1b4690b3f8b	1483	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	165:d1b4690b3f8b	1484	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1485	* @retval None
AnnaBridge	165:d1b4690b3f8b	1486	*/
AnnaBridge	165:d1b4690b3f8b	1487	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1488	{
AnnaBridge	165:d1b4690b3f8b	1489	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	165:d1b4690b3f8b	1490	}
AnnaBridge	165:d1b4690b3f8b	1491
AnnaBridge	165:d1b4690b3f8b	1492	/**
AnnaBridge	165:d1b4690b3f8b	1493	* @brief Disable update event generation.
AnnaBridge	165:d1b4690b3f8b	1494	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	165:d1b4690b3f8b	1495	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1496	* @retval None
AnnaBridge	165:d1b4690b3f8b	1497	*/
AnnaBridge	165:d1b4690b3f8b	1498	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1499	{
AnnaBridge	165:d1b4690b3f8b	1500	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	165:d1b4690b3f8b	1501	}
AnnaBridge	165:d1b4690b3f8b	1502
AnnaBridge	165:d1b4690b3f8b	1503	/**
AnnaBridge	165:d1b4690b3f8b	1504	* @brief Indicates whether update event generation is enabled.
AnnaBridge	165:d1b4690b3f8b	1505	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	165:d1b4690b3f8b	1506	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1507	* @retval Inverted state of bit (0 or 1).
AnnaBridge	165:d1b4690b3f8b	1508	*/
AnnaBridge	165:d1b4690b3f8b	1509	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1510	{
AnnaBridge	165:d1b4690b3f8b	1511	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
AnnaBridge	165:d1b4690b3f8b	1512	}
AnnaBridge	165:d1b4690b3f8b	1513
AnnaBridge	165:d1b4690b3f8b	1514	/**
AnnaBridge	165:d1b4690b3f8b	1515	* @brief Set update event source
AnnaBridge	165:d1b4690b3f8b	1516	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	165:d1b4690b3f8b	1517	* generate an update interrupt or DMA request if enabled:
AnnaBridge	165:d1b4690b3f8b	1518	* - Counter overflow/underflow
AnnaBridge	165:d1b4690b3f8b	1519	* - Setting the UG bit
AnnaBridge	165:d1b4690b3f8b	1520	* - Update generation through the slave mode controller
AnnaBridge	165:d1b4690b3f8b	1521	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	165:d1b4690b3f8b	1522	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	165:d1b4690b3f8b	1523	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	165:d1b4690b3f8b	1524	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1525	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1526	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	165:d1b4690b3f8b	1527	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	165:d1b4690b3f8b	1528	* @retval None
AnnaBridge	165:d1b4690b3f8b	1529	*/
AnnaBridge	165:d1b4690b3f8b	1530	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	165:d1b4690b3f8b	1531	{
AnnaBridge	165:d1b4690b3f8b	1532	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	165:d1b4690b3f8b	1533	}
AnnaBridge	165:d1b4690b3f8b	1534
AnnaBridge	165:d1b4690b3f8b	1535	/**
AnnaBridge	165:d1b4690b3f8b	1536	* @brief Get actual event update source
AnnaBridge	165:d1b4690b3f8b	1537	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	165:d1b4690b3f8b	1538	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1539	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1540	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	165:d1b4690b3f8b	1541	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	165:d1b4690b3f8b	1542	*/
AnnaBridge	165:d1b4690b3f8b	1543	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1544	{
AnnaBridge	165:d1b4690b3f8b	1545	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	165:d1b4690b3f8b	1546	}
AnnaBridge	165:d1b4690b3f8b	1547
AnnaBridge	165:d1b4690b3f8b	1548	/**
AnnaBridge	165:d1b4690b3f8b	1549	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	165:d1b4690b3f8b	1550	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	165:d1b4690b3f8b	1551	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1552	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1553	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	165:d1b4690b3f8b	1554	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	165:d1b4690b3f8b	1555	* @retval None
AnnaBridge	165:d1b4690b3f8b	1556	*/
AnnaBridge	165:d1b4690b3f8b	1557	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	165:d1b4690b3f8b	1558	{
AnnaBridge	165:d1b4690b3f8b	1559	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	165:d1b4690b3f8b	1560	}
AnnaBridge	165:d1b4690b3f8b	1561
AnnaBridge	165:d1b4690b3f8b	1562	/**
AnnaBridge	165:d1b4690b3f8b	1563	* @brief Get actual one pulse mode.
AnnaBridge	165:d1b4690b3f8b	1564	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	165:d1b4690b3f8b	1565	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1566	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1567	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	165:d1b4690b3f8b	1568	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	165:d1b4690b3f8b	1569	*/
AnnaBridge	165:d1b4690b3f8b	1570	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1571	{
AnnaBridge	165:d1b4690b3f8b	1572	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	165:d1b4690b3f8b	1573	}
AnnaBridge	165:d1b4690b3f8b	1574
AnnaBridge	165:d1b4690b3f8b	1575	/**
AnnaBridge	165:d1b4690b3f8b	1576	* @brief Set the timer counter counting mode.
AnnaBridge	165:d1b4690b3f8b	1577	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	165:d1b4690b3f8b	1578	* check whether or not the counter mode selection feature is supported
AnnaBridge	165:d1b4690b3f8b	1579	* by a timer instance.
AnnaBridge	165:d1b4690b3f8b	1580	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
AnnaBridge	165:d1b4690b3f8b	1581	* requires a timer reset to avoid unexpected direction
AnnaBridge	165:d1b4690b3f8b	1582	* due to DIR bit readonly in center aligned mode.
AnnaBridge	165:d1b4690b3f8b	1583	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	165:d1b4690b3f8b	1584	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	165:d1b4690b3f8b	1585	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1586	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1587	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	165:d1b4690b3f8b	1588	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	165:d1b4690b3f8b	1589	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	165:d1b4690b3f8b	1590	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	165:d1b4690b3f8b	1591	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	165:d1b4690b3f8b	1592	* @retval None
AnnaBridge	165:d1b4690b3f8b	1593	*/
AnnaBridge	165:d1b4690b3f8b	1594	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	165:d1b4690b3f8b	1595	{
AnnaBridge	165:d1b4690b3f8b	1596	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	165:d1b4690b3f8b	1597	}
AnnaBridge	165:d1b4690b3f8b	1598
AnnaBridge	165:d1b4690b3f8b	1599	/**
AnnaBridge	165:d1b4690b3f8b	1600	* @brief Get actual counter mode.
AnnaBridge	165:d1b4690b3f8b	1601	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	165:d1b4690b3f8b	1602	* check whether or not the counter mode selection feature is supported
AnnaBridge	165:d1b4690b3f8b	1603	* by a timer instance.
AnnaBridge	165:d1b4690b3f8b	1604	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	165:d1b4690b3f8b	1605	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	165:d1b4690b3f8b	1606	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1607	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1608	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	165:d1b4690b3f8b	1609	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	165:d1b4690b3f8b	1610	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	165:d1b4690b3f8b	1611	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	165:d1b4690b3f8b	1612	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	165:d1b4690b3f8b	1613	*/
AnnaBridge	165:d1b4690b3f8b	1614	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1615	{
AnnaBridge	165:d1b4690b3f8b	1616	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	165:d1b4690b3f8b	1617	}
AnnaBridge	165:d1b4690b3f8b	1618
AnnaBridge	165:d1b4690b3f8b	1619	/**
AnnaBridge	165:d1b4690b3f8b	1620	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	165:d1b4690b3f8b	1621	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	165:d1b4690b3f8b	1622	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1623	* @retval None
AnnaBridge	165:d1b4690b3f8b	1624	*/
AnnaBridge	165:d1b4690b3f8b	1625	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1626	{
AnnaBridge	165:d1b4690b3f8b	1627	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	165:d1b4690b3f8b	1628	}
AnnaBridge	165:d1b4690b3f8b	1629
AnnaBridge	165:d1b4690b3f8b	1630	/**
AnnaBridge	165:d1b4690b3f8b	1631	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	165:d1b4690b3f8b	1632	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	165:d1b4690b3f8b	1633	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1634	* @retval None
AnnaBridge	165:d1b4690b3f8b	1635	*/
AnnaBridge	165:d1b4690b3f8b	1636	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1637	{
AnnaBridge	165:d1b4690b3f8b	1638	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	165:d1b4690b3f8b	1639	}
AnnaBridge	165:d1b4690b3f8b	1640
AnnaBridge	165:d1b4690b3f8b	1641	/**
AnnaBridge	165:d1b4690b3f8b	1642	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	165:d1b4690b3f8b	1643	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	165:d1b4690b3f8b	1644	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1645	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	1646	*/
AnnaBridge	165:d1b4690b3f8b	1647	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1648	{
AnnaBridge	165:d1b4690b3f8b	1649	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	165:d1b4690b3f8b	1650	}
AnnaBridge	165:d1b4690b3f8b	1651
AnnaBridge	165:d1b4690b3f8b	1652	/**
AnnaBridge	165:d1b4690b3f8b	1653	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	165:d1b4690b3f8b	1654	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1655	* whether or not the clock division feature is supported by the timer
AnnaBridge	165:d1b4690b3f8b	1656	* instance.
AnnaBridge	165:d1b4690b3f8b	1657	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	165:d1b4690b3f8b	1658	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1659	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1660	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:d1b4690b3f8b	1661	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:d1b4690b3f8b	1662	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:d1b4690b3f8b	1663	* @retval None
AnnaBridge	165:d1b4690b3f8b	1664	*/
AnnaBridge	165:d1b4690b3f8b	1665	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	165:d1b4690b3f8b	1666	{
AnnaBridge	165:d1b4690b3f8b	1667	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	165:d1b4690b3f8b	1668	}
AnnaBridge	165:d1b4690b3f8b	1669
AnnaBridge	165:d1b4690b3f8b	1670	/**
AnnaBridge	165:d1b4690b3f8b	1671	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	165:d1b4690b3f8b	1672	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1673	* whether or not the clock division feature is supported by the timer
AnnaBridge	165:d1b4690b3f8b	1674	* instance.
AnnaBridge	165:d1b4690b3f8b	1675	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	165:d1b4690b3f8b	1676	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1677	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1678	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:d1b4690b3f8b	1679	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:d1b4690b3f8b	1680	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:d1b4690b3f8b	1681	*/
AnnaBridge	165:d1b4690b3f8b	1682	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1683	{
AnnaBridge	165:d1b4690b3f8b	1684	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	165:d1b4690b3f8b	1685	}
AnnaBridge	165:d1b4690b3f8b	1686
AnnaBridge	165:d1b4690b3f8b	1687	/**
AnnaBridge	165:d1b4690b3f8b	1688	* @brief Set the counter value.
AnnaBridge	165:d1b4690b3f8b	1689	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1690	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	1691	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	165:d1b4690b3f8b	1692	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1693	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	165:d1b4690b3f8b	1694	* @retval None
AnnaBridge	165:d1b4690b3f8b	1695	*/
AnnaBridge	165:d1b4690b3f8b	1696	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	165:d1b4690b3f8b	1697	{
AnnaBridge	165:d1b4690b3f8b	1698	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	165:d1b4690b3f8b	1699	}
AnnaBridge	165:d1b4690b3f8b	1700
AnnaBridge	165:d1b4690b3f8b	1701	/**
AnnaBridge	165:d1b4690b3f8b	1702	* @brief Get the counter value.
AnnaBridge	165:d1b4690b3f8b	1703	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1704	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	1705	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	165:d1b4690b3f8b	1706	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1707	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	165:d1b4690b3f8b	1708	*/
AnnaBridge	165:d1b4690b3f8b	1709	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1710	{
AnnaBridge	165:d1b4690b3f8b	1711	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	165:d1b4690b3f8b	1712	}
AnnaBridge	165:d1b4690b3f8b	1713
AnnaBridge	165:d1b4690b3f8b	1714	/**
AnnaBridge	165:d1b4690b3f8b	1715	* @brief Get the current direction of the counter
AnnaBridge	165:d1b4690b3f8b	1716	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	165:d1b4690b3f8b	1717	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1718	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1719	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	165:d1b4690b3f8b	1720	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	165:d1b4690b3f8b	1721	*/
AnnaBridge	165:d1b4690b3f8b	1722	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1723	{
AnnaBridge	165:d1b4690b3f8b	1724	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	165:d1b4690b3f8b	1725	}
AnnaBridge	165:d1b4690b3f8b	1726
AnnaBridge	165:d1b4690b3f8b	1727	/**
AnnaBridge	165:d1b4690b3f8b	1728	* @brief Set the prescaler value.
AnnaBridge	165:d1b4690b3f8b	1729	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	165:d1b4690b3f8b	1730	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	165:d1b4690b3f8b	1731	* prescaler ratio is taken into account at the next update event.
AnnaBridge	165:d1b4690b3f8b	1732	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	165:d1b4690b3f8b	1733	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	165:d1b4690b3f8b	1734	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1735	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	1736	* @retval None
AnnaBridge	165:d1b4690b3f8b	1737	*/
AnnaBridge	165:d1b4690b3f8b	1738	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	165:d1b4690b3f8b	1739	{
AnnaBridge	165:d1b4690b3f8b	1740	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	165:d1b4690b3f8b	1741	}
AnnaBridge	165:d1b4690b3f8b	1742
AnnaBridge	165:d1b4690b3f8b	1743	/**
AnnaBridge	165:d1b4690b3f8b	1744	* @brief Get the prescaler value.
AnnaBridge	165:d1b4690b3f8b	1745	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	165:d1b4690b3f8b	1746	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1747	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	1748	*/
AnnaBridge	165:d1b4690b3f8b	1749	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1750	{
AnnaBridge	165:d1b4690b3f8b	1751	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	165:d1b4690b3f8b	1752	}
AnnaBridge	165:d1b4690b3f8b	1753
AnnaBridge	165:d1b4690b3f8b	1754	/**
AnnaBridge	165:d1b4690b3f8b	1755	* @brief Set the auto-reload value.
AnnaBridge	165:d1b4690b3f8b	1756	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	165:d1b4690b3f8b	1757	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1758	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	1759	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	165:d1b4690b3f8b	1760	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	165:d1b4690b3f8b	1761	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1762	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	1763	* @retval None
AnnaBridge	165:d1b4690b3f8b	1764	*/
AnnaBridge	165:d1b4690b3f8b	1765	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	165:d1b4690b3f8b	1766	{
AnnaBridge	165:d1b4690b3f8b	1767	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	165:d1b4690b3f8b	1768	}
AnnaBridge	165:d1b4690b3f8b	1769
AnnaBridge	165:d1b4690b3f8b	1770	/**
AnnaBridge	165:d1b4690b3f8b	1771	* @brief Get the auto-reload value.
AnnaBridge	165:d1b4690b3f8b	1772	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	165:d1b4690b3f8b	1773	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1774	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	1775	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1776	* @retval Auto-reload value
AnnaBridge	165:d1b4690b3f8b	1777	*/
AnnaBridge	165:d1b4690b3f8b	1778	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1779	{
AnnaBridge	165:d1b4690b3f8b	1780	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	165:d1b4690b3f8b	1781	}
AnnaBridge	165:d1b4690b3f8b	1782
AnnaBridge	165:d1b4690b3f8b	1783	/**
AnnaBridge	165:d1b4690b3f8b	1784	* @brief Set the repetition counter value.
AnnaBridge	165:d1b4690b3f8b	1785	* @note For advanced timer instances RepetitionCounter can be up to 65535.
AnnaBridge	165:d1b4690b3f8b	1786	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1787	* whether or not a timer instance supports a repetition counter.
AnnaBridge	165:d1b4690b3f8b	1788	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	165:d1b4690b3f8b	1789	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1790	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	165:d1b4690b3f8b	1791	* @retval None
AnnaBridge	165:d1b4690b3f8b	1792	*/
AnnaBridge	165:d1b4690b3f8b	1793	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	165:d1b4690b3f8b	1794	{
AnnaBridge	165:d1b4690b3f8b	1795	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	165:d1b4690b3f8b	1796	}
AnnaBridge	165:d1b4690b3f8b	1797
AnnaBridge	165:d1b4690b3f8b	1798	/**
AnnaBridge	165:d1b4690b3f8b	1799	* @brief Get the repetition counter value.
AnnaBridge	165:d1b4690b3f8b	1800	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1801	* whether or not a timer instance supports a repetition counter.
AnnaBridge	165:d1b4690b3f8b	1802	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	165:d1b4690b3f8b	1803	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1804	* @retval Repetition counter value
AnnaBridge	165:d1b4690b3f8b	1805	*/
AnnaBridge	165:d1b4690b3f8b	1806	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1807	{
AnnaBridge	165:d1b4690b3f8b	1808	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	165:d1b4690b3f8b	1809	}
AnnaBridge	165:d1b4690b3f8b	1810
AnnaBridge	165:d1b4690b3f8b	1811	/**
AnnaBridge	165:d1b4690b3f8b	1812	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
AnnaBridge	165:d1b4690b3f8b	1813	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
AnnaBridge	165:d1b4690b3f8b	1814	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
AnnaBridge	165:d1b4690b3f8b	1815	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1816	* @retval None
AnnaBridge	165:d1b4690b3f8b	1817	*/
AnnaBridge	165:d1b4690b3f8b	1818	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1819	{
AnnaBridge	165:d1b4690b3f8b	1820	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	165:d1b4690b3f8b	1821	}
AnnaBridge	165:d1b4690b3f8b	1822
AnnaBridge	165:d1b4690b3f8b	1823	/**
AnnaBridge	165:d1b4690b3f8b	1824	* @brief Disable update interrupt flag (UIF) remapping.
AnnaBridge	165:d1b4690b3f8b	1825	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
AnnaBridge	165:d1b4690b3f8b	1826	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1827	* @retval None
AnnaBridge	165:d1b4690b3f8b	1828	*/
AnnaBridge	165:d1b4690b3f8b	1829	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1830	{
AnnaBridge	165:d1b4690b3f8b	1831	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	165:d1b4690b3f8b	1832	}
AnnaBridge	165:d1b4690b3f8b	1833
AnnaBridge	165:d1b4690b3f8b	1834	/**
AnnaBridge	165:d1b4690b3f8b	1835	* @}
AnnaBridge	165:d1b4690b3f8b	1836	*/
AnnaBridge	165:d1b4690b3f8b	1837
AnnaBridge	165:d1b4690b3f8b	1838	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	165:d1b4690b3f8b	1839	* @{
AnnaBridge	165:d1b4690b3f8b	1840	*/
AnnaBridge	165:d1b4690b3f8b	1841	/**
AnnaBridge	165:d1b4690b3f8b	1842	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	165:d1b4690b3f8b	1843	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	165:d1b4690b3f8b	1844	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	165:d1b4690b3f8b	1845	* @note Only on channels that have a complementary output.
AnnaBridge	165:d1b4690b3f8b	1846	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1847	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:d1b4690b3f8b	1848	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	165:d1b4690b3f8b	1849	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1850	* @retval None
AnnaBridge	165:d1b4690b3f8b	1851	*/
AnnaBridge	165:d1b4690b3f8b	1852	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1853	{
AnnaBridge	165:d1b4690b3f8b	1854	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	165:d1b4690b3f8b	1855	}
AnnaBridge	165:d1b4690b3f8b	1856
AnnaBridge	165:d1b4690b3f8b	1857	/**
AnnaBridge	165:d1b4690b3f8b	1858	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	165:d1b4690b3f8b	1859	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1860	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:d1b4690b3f8b	1861	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	165:d1b4690b3f8b	1862	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1863	* @retval None
AnnaBridge	165:d1b4690b3f8b	1864	*/
AnnaBridge	165:d1b4690b3f8b	1865	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1866	{
AnnaBridge	165:d1b4690b3f8b	1867	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	165:d1b4690b3f8b	1868	}
AnnaBridge	165:d1b4690b3f8b	1869
AnnaBridge	165:d1b4690b3f8b	1870	/**
AnnaBridge	165:d1b4690b3f8b	1871	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	165:d1b4690b3f8b	1872	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	1873	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:d1b4690b3f8b	1874	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	165:d1b4690b3f8b	1875	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1876	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1877	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	165:d1b4690b3f8b	1878	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	165:d1b4690b3f8b	1879	* @retval None
AnnaBridge	165:d1b4690b3f8b	1880	*/
AnnaBridge	165:d1b4690b3f8b	1881	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	165:d1b4690b3f8b	1882	{
AnnaBridge	165:d1b4690b3f8b	1883	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	165:d1b4690b3f8b	1884	}
AnnaBridge	165:d1b4690b3f8b	1885
AnnaBridge	165:d1b4690b3f8b	1886	/**
AnnaBridge	165:d1b4690b3f8b	1887	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	165:d1b4690b3f8b	1888	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	165:d1b4690b3f8b	1889	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1890	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1891	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	165:d1b4690b3f8b	1892	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	165:d1b4690b3f8b	1893	* @retval None
AnnaBridge	165:d1b4690b3f8b	1894	*/
AnnaBridge	165:d1b4690b3f8b	1895	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	165:d1b4690b3f8b	1896	{
AnnaBridge	165:d1b4690b3f8b	1897	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	165:d1b4690b3f8b	1898	}
AnnaBridge	165:d1b4690b3f8b	1899
AnnaBridge	165:d1b4690b3f8b	1900	/**
AnnaBridge	165:d1b4690b3f8b	1901	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	165:d1b4690b3f8b	1902	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	165:d1b4690b3f8b	1903	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1904	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1905	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	165:d1b4690b3f8b	1906	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	165:d1b4690b3f8b	1907	*/
AnnaBridge	165:d1b4690b3f8b	1908	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	1909	{
AnnaBridge	165:d1b4690b3f8b	1910	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	165:d1b4690b3f8b	1911	}
AnnaBridge	165:d1b4690b3f8b	1912
AnnaBridge	165:d1b4690b3f8b	1913	/**
AnnaBridge	165:d1b4690b3f8b	1914	* @brief Set the lock level to freeze the
AnnaBridge	165:d1b4690b3f8b	1915	* configuration of several capture/compare parameters.
AnnaBridge	165:d1b4690b3f8b	1916	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	1917	* the lock mechanism is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	1918	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	165:d1b4690b3f8b	1919	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1920	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1921	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	165:d1b4690b3f8b	1922	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	165:d1b4690b3f8b	1923	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	165:d1b4690b3f8b	1924	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	165:d1b4690b3f8b	1925	* @retval None
AnnaBridge	165:d1b4690b3f8b	1926	*/
AnnaBridge	165:d1b4690b3f8b	1927	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	165:d1b4690b3f8b	1928	{
AnnaBridge	165:d1b4690b3f8b	1929	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	165:d1b4690b3f8b	1930	}
AnnaBridge	165:d1b4690b3f8b	1931
AnnaBridge	165:d1b4690b3f8b	1932	/**
AnnaBridge	165:d1b4690b3f8b	1933	* @brief Enable capture/compare channels.
AnnaBridge	165:d1b4690b3f8b	1934	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1935	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1936	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1937	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1938	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1939	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1940	* CCER CC4E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1941	* CCER CC5E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:d1b4690b3f8b	1942	* CCER CC6E LL_TIM_CC_EnableChannel
AnnaBridge	165:d1b4690b3f8b	1943	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1944	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	1945	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	1946	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	1947	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	1948	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	1949	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	1950	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	1951	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	1952	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	1953	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	1954	* @retval None
AnnaBridge	165:d1b4690b3f8b	1955	*/
AnnaBridge	165:d1b4690b3f8b	1956	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:d1b4690b3f8b	1957	{
AnnaBridge	165:d1b4690b3f8b	1958	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	165:d1b4690b3f8b	1959	}
AnnaBridge	165:d1b4690b3f8b	1960
AnnaBridge	165:d1b4690b3f8b	1961	/**
AnnaBridge	165:d1b4690b3f8b	1962	* @brief Disable capture/compare channels.
AnnaBridge	165:d1b4690b3f8b	1963	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1964	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1965	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1966	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1967	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1968	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1969	* CCER CC4E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1970	* CCER CC5E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:d1b4690b3f8b	1971	* CCER CC6E LL_TIM_CC_DisableChannel
AnnaBridge	165:d1b4690b3f8b	1972	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	1973	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	1974	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	1975	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	1976	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	1977	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	1978	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	1979	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	1980	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	1981	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	1982	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	1983	* @retval None
AnnaBridge	165:d1b4690b3f8b	1984	*/
AnnaBridge	165:d1b4690b3f8b	1985	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:d1b4690b3f8b	1986	{
AnnaBridge	165:d1b4690b3f8b	1987	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	165:d1b4690b3f8b	1988	}
AnnaBridge	165:d1b4690b3f8b	1989
AnnaBridge	165:d1b4690b3f8b	1990	/**
AnnaBridge	165:d1b4690b3f8b	1991	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	165:d1b4690b3f8b	1992	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1993	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1994	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1995	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1996	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1997	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1998	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	1999	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:d1b4690b3f8b	2000	* CCER CC6E LL_TIM_CC_IsEnabledChannel
AnnaBridge	165:d1b4690b3f8b	2001	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2002	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	2003	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2004	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	2005	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2006	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	2007	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2008	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	2009	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2010	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2011	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2012	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2013	*/
AnnaBridge	165:d1b4690b3f8b	2014	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:d1b4690b3f8b	2015	{
AnnaBridge	165:d1b4690b3f8b	2016	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	165:d1b4690b3f8b	2017	}
AnnaBridge	165:d1b4690b3f8b	2018
AnnaBridge	165:d1b4690b3f8b	2019	/**
AnnaBridge	165:d1b4690b3f8b	2020	* @}
AnnaBridge	165:d1b4690b3f8b	2021	*/
AnnaBridge	165:d1b4690b3f8b	2022
AnnaBridge	165:d1b4690b3f8b	2023	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	165:d1b4690b3f8b	2024	* @{
AnnaBridge	165:d1b4690b3f8b	2025	*/
AnnaBridge	165:d1b4690b3f8b	2026	/**
AnnaBridge	165:d1b4690b3f8b	2027	* @brief Configure an output channel.
AnnaBridge	165:d1b4690b3f8b	2028	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2029	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2030	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2031	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2032	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2033	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2034	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2035	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2036	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2037	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2038	* CCER CC5P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2039	* CCER CC6P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2040	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2041	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2042	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2043	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2044	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:d1b4690b3f8b	2045	* CR2 OIS6 LL_TIM_OC_ConfigOutput
AnnaBridge	165:d1b4690b3f8b	2046	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2047	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2048	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2049	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2050	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2051	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2052	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2053	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2054	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	165:d1b4690b3f8b	2055	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	2056	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:d1b4690b3f8b	2057	* @retval None
AnnaBridge	165:d1b4690b3f8b	2058	*/
AnnaBridge	165:d1b4690b3f8b	2059	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	165:d1b4690b3f8b	2060	{
AnnaBridge	165:d1b4690b3f8b	2061	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2062	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2063	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2064	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:d1b4690b3f8b	2065	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2066	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	165:d1b4690b3f8b	2067	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2068	}
AnnaBridge	165:d1b4690b3f8b	2069
AnnaBridge	165:d1b4690b3f8b	2070	/**
AnnaBridge	165:d1b4690b3f8b	2071	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	165:d1b4690b3f8b	2072	* OCx and OCxN (when relevant) are derived.
AnnaBridge	165:d1b4690b3f8b	2073	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	165:d1b4690b3f8b	2074	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	165:d1b4690b3f8b	2075	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	165:d1b4690b3f8b	2076	* CCMR2 OC4M LL_TIM_OC_SetMode\n
AnnaBridge	165:d1b4690b3f8b	2077	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	165:d1b4690b3f8b	2078	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	165:d1b4690b3f8b	2079	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2080	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2081	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2082	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2083	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2084	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2085	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2086	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2087	* @param Mode This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2088	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	165:d1b4690b3f8b	2089	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	165:d1b4690b3f8b	2090	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	165:d1b4690b3f8b	2091	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	165:d1b4690b3f8b	2092	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	165:d1b4690b3f8b	2093	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	165:d1b4690b3f8b	2094	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	165:d1b4690b3f8b	2095	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	165:d1b4690b3f8b	2096	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	165:d1b4690b3f8b	2097	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	165:d1b4690b3f8b	2098	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	165:d1b4690b3f8b	2099	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	165:d1b4690b3f8b	2100	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	165:d1b4690b3f8b	2101	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	165:d1b4690b3f8b	2102	* @retval None
AnnaBridge	165:d1b4690b3f8b	2103	*/
AnnaBridge	165:d1b4690b3f8b	2104	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	165:d1b4690b3f8b	2105	{
AnnaBridge	165:d1b4690b3f8b	2106	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2107	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2108	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2109	}
AnnaBridge	165:d1b4690b3f8b	2110
AnnaBridge	165:d1b4690b3f8b	2111	/**
AnnaBridge	165:d1b4690b3f8b	2112	* @brief Get the output compare mode of an output channel.
AnnaBridge	165:d1b4690b3f8b	2113	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	165:d1b4690b3f8b	2114	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	165:d1b4690b3f8b	2115	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	165:d1b4690b3f8b	2116	* CCMR2 OC4M LL_TIM_OC_GetMode\n
AnnaBridge	165:d1b4690b3f8b	2117	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	165:d1b4690b3f8b	2118	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	165:d1b4690b3f8b	2119	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2120	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2121	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2122	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2123	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2124	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2125	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2126	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2127	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2128	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	165:d1b4690b3f8b	2129	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	165:d1b4690b3f8b	2130	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	165:d1b4690b3f8b	2131	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	165:d1b4690b3f8b	2132	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	165:d1b4690b3f8b	2133	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	165:d1b4690b3f8b	2134	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	165:d1b4690b3f8b	2135	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	165:d1b4690b3f8b	2136	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	165:d1b4690b3f8b	2137	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	165:d1b4690b3f8b	2138	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	165:d1b4690b3f8b	2139	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	165:d1b4690b3f8b	2140	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	165:d1b4690b3f8b	2141	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	165:d1b4690b3f8b	2142	*/
AnnaBridge	165:d1b4690b3f8b	2143	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2144	{
AnnaBridge	165:d1b4690b3f8b	2145	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2146	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2147	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2148	}
AnnaBridge	165:d1b4690b3f8b	2149
AnnaBridge	165:d1b4690b3f8b	2150	/**
AnnaBridge	165:d1b4690b3f8b	2151	* @brief Set the polarity of an output channel.
AnnaBridge	165:d1b4690b3f8b	2152	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2153	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2154	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2155	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2156	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2157	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2158	* CCER CC4P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2159	* CCER CC5P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2160	* CCER CC6P LL_TIM_OC_SetPolarity
AnnaBridge	165:d1b4690b3f8b	2161	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2162	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2163	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2164	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	2165	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2166	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	2167	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2168	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	2169	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2170	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2171	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2172	* @param Polarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2173	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	165:d1b4690b3f8b	2174	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	2175	* @retval None
AnnaBridge	165:d1b4690b3f8b	2176	*/
AnnaBridge	165:d1b4690b3f8b	2177	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	165:d1b4690b3f8b	2178	{
AnnaBridge	165:d1b4690b3f8b	2179	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2180	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2181	}
AnnaBridge	165:d1b4690b3f8b	2182
AnnaBridge	165:d1b4690b3f8b	2183	/**
AnnaBridge	165:d1b4690b3f8b	2184	* @brief Get the polarity of an output channel.
AnnaBridge	165:d1b4690b3f8b	2185	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2186	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2187	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2188	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2189	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2190	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2191	* CCER CC4P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2192	* CCER CC5P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2193	* CCER CC6P LL_TIM_OC_GetPolarity
AnnaBridge	165:d1b4690b3f8b	2194	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2195	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2196	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2197	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	2198	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2199	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	2200	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2201	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	2202	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2203	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2204	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2205	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2206	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	165:d1b4690b3f8b	2207	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	2208	*/
AnnaBridge	165:d1b4690b3f8b	2209	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2210	{
AnnaBridge	165:d1b4690b3f8b	2211	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2212	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2213	}
AnnaBridge	165:d1b4690b3f8b	2214
AnnaBridge	165:d1b4690b3f8b	2215	/**
AnnaBridge	165:d1b4690b3f8b	2216	* @brief Set the IDLE state of an output channel
AnnaBridge	165:d1b4690b3f8b	2217	* @note This function is significant only for the timer instances
AnnaBridge	165:d1b4690b3f8b	2218	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	165:d1b4690b3f8b	2219	* can be used to check whether or not a timer instance provides
AnnaBridge	165:d1b4690b3f8b	2220	* a break input.
AnnaBridge	165:d1b4690b3f8b	2221	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2222	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2223	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2224	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2225	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2226	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2227	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2228	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2229	* CR2 OIS6 LL_TIM_OC_SetIdleState
AnnaBridge	165:d1b4690b3f8b	2230	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2231	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2232	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2233	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	2234	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2235	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	2236	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2237	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	2238	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2239	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2240	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2241	* @param IdleState This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2242	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	165:d1b4690b3f8b	2243	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:d1b4690b3f8b	2244	* @retval None
AnnaBridge	165:d1b4690b3f8b	2245	*/
AnnaBridge	165:d1b4690b3f8b	2246	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	165:d1b4690b3f8b	2247	{
AnnaBridge	165:d1b4690b3f8b	2248	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2249	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2250	}
AnnaBridge	165:d1b4690b3f8b	2251
AnnaBridge	165:d1b4690b3f8b	2252	/**
AnnaBridge	165:d1b4690b3f8b	2253	* @brief Get the IDLE state of an output channel
AnnaBridge	165:d1b4690b3f8b	2254	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2255	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2256	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2257	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2258	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2259	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2260	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2261	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:d1b4690b3f8b	2262	* CR2 OIS6 LL_TIM_OC_GetIdleState
AnnaBridge	165:d1b4690b3f8b	2263	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2264	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2265	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2266	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:d1b4690b3f8b	2267	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2268	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:d1b4690b3f8b	2269	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2270	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:d1b4690b3f8b	2271	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2272	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2273	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2274	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2275	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	165:d1b4690b3f8b	2276	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:d1b4690b3f8b	2277	*/
AnnaBridge	165:d1b4690b3f8b	2278	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2279	{
AnnaBridge	165:d1b4690b3f8b	2280	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2281	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2282	}
AnnaBridge	165:d1b4690b3f8b	2283
AnnaBridge	165:d1b4690b3f8b	2284	/**
AnnaBridge	165:d1b4690b3f8b	2285	* @brief Enable fast mode for the output channel.
AnnaBridge	165:d1b4690b3f8b	2286	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	165:d1b4690b3f8b	2287	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:d1b4690b3f8b	2288	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:d1b4690b3f8b	2289	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:d1b4690b3f8b	2290	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:d1b4690b3f8b	2291	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:d1b4690b3f8b	2292	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	165:d1b4690b3f8b	2293	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2294	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2295	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2296	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2297	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2298	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2299	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2300	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2301	* @retval None
AnnaBridge	165:d1b4690b3f8b	2302	*/
AnnaBridge	165:d1b4690b3f8b	2303	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2304	{
AnnaBridge	165:d1b4690b3f8b	2305	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2306	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2307	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2308
AnnaBridge	165:d1b4690b3f8b	2309	}
AnnaBridge	165:d1b4690b3f8b	2310
AnnaBridge	165:d1b4690b3f8b	2311	/**
AnnaBridge	165:d1b4690b3f8b	2312	* @brief Disable fast mode for the output channel.
AnnaBridge	165:d1b4690b3f8b	2313	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:d1b4690b3f8b	2314	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:d1b4690b3f8b	2315	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:d1b4690b3f8b	2316	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:d1b4690b3f8b	2317	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:d1b4690b3f8b	2318	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	165:d1b4690b3f8b	2319	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2320	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2321	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2322	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2323	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2324	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2325	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2326	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2327	* @retval None
AnnaBridge	165:d1b4690b3f8b	2328	*/
AnnaBridge	165:d1b4690b3f8b	2329	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2330	{
AnnaBridge	165:d1b4690b3f8b	2331	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2332	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2333	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2334
AnnaBridge	165:d1b4690b3f8b	2335	}
AnnaBridge	165:d1b4690b3f8b	2336
AnnaBridge	165:d1b4690b3f8b	2337	/**
AnnaBridge	165:d1b4690b3f8b	2338	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	165:d1b4690b3f8b	2339	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:d1b4690b3f8b	2340	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:d1b4690b3f8b	2341	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:d1b4690b3f8b	2342	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:d1b4690b3f8b	2343	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:d1b4690b3f8b	2344	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
AnnaBridge	165:d1b4690b3f8b	2345	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2346	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2347	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2348	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2349	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2350	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2351	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2352	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2353	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2354	*/
AnnaBridge	165:d1b4690b3f8b	2355	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2356	{
AnnaBridge	165:d1b4690b3f8b	2357	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2358	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2359	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:d1b4690b3f8b	2360	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:d1b4690b3f8b	2361	}
AnnaBridge	165:d1b4690b3f8b	2362
AnnaBridge	165:d1b4690b3f8b	2363	/**
AnnaBridge	165:d1b4690b3f8b	2364	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	165:d1b4690b3f8b	2365	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:d1b4690b3f8b	2366	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:d1b4690b3f8b	2367	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:d1b4690b3f8b	2368	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:d1b4690b3f8b	2369	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:d1b4690b3f8b	2370	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	165:d1b4690b3f8b	2371	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2372	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2373	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2374	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2375	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2376	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2377	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2378	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2379	* @retval None
AnnaBridge	165:d1b4690b3f8b	2380	*/
AnnaBridge	165:d1b4690b3f8b	2381	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2382	{
AnnaBridge	165:d1b4690b3f8b	2383	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2384	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2385	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2386	}
AnnaBridge	165:d1b4690b3f8b	2387
AnnaBridge	165:d1b4690b3f8b	2388	/**
AnnaBridge	165:d1b4690b3f8b	2389	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	165:d1b4690b3f8b	2390	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:d1b4690b3f8b	2391	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:d1b4690b3f8b	2392	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:d1b4690b3f8b	2393	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:d1b4690b3f8b	2394	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:d1b4690b3f8b	2395	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	165:d1b4690b3f8b	2396	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2397	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2398	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2399	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2400	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2401	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2402	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2403	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2404	* @retval None
AnnaBridge	165:d1b4690b3f8b	2405	*/
AnnaBridge	165:d1b4690b3f8b	2406	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2407	{
AnnaBridge	165:d1b4690b3f8b	2408	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2409	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2410	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2411	}
AnnaBridge	165:d1b4690b3f8b	2412
AnnaBridge	165:d1b4690b3f8b	2413	/**
AnnaBridge	165:d1b4690b3f8b	2414	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	165:d1b4690b3f8b	2415	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:d1b4690b3f8b	2416	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:d1b4690b3f8b	2417	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:d1b4690b3f8b	2418	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:d1b4690b3f8b	2419	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:d1b4690b3f8b	2420	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	165:d1b4690b3f8b	2421	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2422	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2423	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2424	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2425	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2426	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2427	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2428	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2429	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2430	*/
AnnaBridge	165:d1b4690b3f8b	2431	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2432	{
AnnaBridge	165:d1b4690b3f8b	2433	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2434	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2435	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:d1b4690b3f8b	2436	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:d1b4690b3f8b	2437	}
AnnaBridge	165:d1b4690b3f8b	2438
AnnaBridge	165:d1b4690b3f8b	2439	/**
AnnaBridge	165:d1b4690b3f8b	2440	* @brief Enable clearing the output channel on an external event.
AnnaBridge	165:d1b4690b3f8b	2441	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	165:d1b4690b3f8b	2442	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	2443	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:d1b4690b3f8b	2444	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:d1b4690b3f8b	2445	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:d1b4690b3f8b	2446	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:d1b4690b3f8b	2447	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:d1b4690b3f8b	2448	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:d1b4690b3f8b	2449	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	165:d1b4690b3f8b	2450	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2451	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2452	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2453	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2454	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2455	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2456	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2457	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2458	* @retval None
AnnaBridge	165:d1b4690b3f8b	2459	*/
AnnaBridge	165:d1b4690b3f8b	2460	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2461	{
AnnaBridge	165:d1b4690b3f8b	2462	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2463	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2464	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2465	}
AnnaBridge	165:d1b4690b3f8b	2466
AnnaBridge	165:d1b4690b3f8b	2467	/**
AnnaBridge	165:d1b4690b3f8b	2468	* @brief Disable clearing the output channel on an external event.
AnnaBridge	165:d1b4690b3f8b	2469	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	2470	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:d1b4690b3f8b	2471	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:d1b4690b3f8b	2472	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:d1b4690b3f8b	2473	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:d1b4690b3f8b	2474	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:d1b4690b3f8b	2475	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:d1b4690b3f8b	2476	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	165:d1b4690b3f8b	2477	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2478	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2479	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2480	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2481	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2482	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2483	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2484	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2485	* @retval None
AnnaBridge	165:d1b4690b3f8b	2486	*/
AnnaBridge	165:d1b4690b3f8b	2487	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2488	{
AnnaBridge	165:d1b4690b3f8b	2489	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2490	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2491	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2492	}
AnnaBridge	165:d1b4690b3f8b	2493
AnnaBridge	165:d1b4690b3f8b	2494	/**
AnnaBridge	165:d1b4690b3f8b	2495	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	165:d1b4690b3f8b	2496	* @note This function enables clearing the output channel on an external event.
AnnaBridge	165:d1b4690b3f8b	2497	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	165:d1b4690b3f8b	2498	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	2499	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:d1b4690b3f8b	2500	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:d1b4690b3f8b	2501	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:d1b4690b3f8b	2502	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:d1b4690b3f8b	2503	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:d1b4690b3f8b	2504	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:d1b4690b3f8b	2505	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	165:d1b4690b3f8b	2506	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2507	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2508	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2509	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2510	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2511	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2512	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	165:d1b4690b3f8b	2513	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	165:d1b4690b3f8b	2514	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2515	*/
AnnaBridge	165:d1b4690b3f8b	2516	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2517	{
AnnaBridge	165:d1b4690b3f8b	2518	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2519	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2520	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:d1b4690b3f8b	2521	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:d1b4690b3f8b	2522	}
AnnaBridge	165:d1b4690b3f8b	2523
AnnaBridge	165:d1b4690b3f8b	2524	/**
AnnaBridge	165:d1b4690b3f8b	2525	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
AnnaBridge	165:d1b4690b3f8b	2526	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2527	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2528	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	165:d1b4690b3f8b	2529	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	165:d1b4690b3f8b	2530	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2531	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	165:d1b4690b3f8b	2532	* @retval None
AnnaBridge	165:d1b4690b3f8b	2533	*/
AnnaBridge	165:d1b4690b3f8b	2534	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	165:d1b4690b3f8b	2535	{
AnnaBridge	165:d1b4690b3f8b	2536	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	165:d1b4690b3f8b	2537	}
AnnaBridge	165:d1b4690b3f8b	2538
AnnaBridge	165:d1b4690b3f8b	2539	/**
AnnaBridge	165:d1b4690b3f8b	2540	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	165:d1b4690b3f8b	2541	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2542	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2543	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2544	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2545	* output channel 1 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2546	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	165:d1b4690b3f8b	2547	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2548	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2549	* @retval None
AnnaBridge	165:d1b4690b3f8b	2550	*/
AnnaBridge	165:d1b4690b3f8b	2551	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2552	{
AnnaBridge	165:d1b4690b3f8b	2553	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2554	}
AnnaBridge	165:d1b4690b3f8b	2555
AnnaBridge	165:d1b4690b3f8b	2556	/**
AnnaBridge	165:d1b4690b3f8b	2557	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	165:d1b4690b3f8b	2558	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2559	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2560	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2561	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2562	* output channel 2 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2563	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	165:d1b4690b3f8b	2564	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2565	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2566	* @retval None
AnnaBridge	165:d1b4690b3f8b	2567	*/
AnnaBridge	165:d1b4690b3f8b	2568	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2569	{
AnnaBridge	165:d1b4690b3f8b	2570	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2571	}
AnnaBridge	165:d1b4690b3f8b	2572
AnnaBridge	165:d1b4690b3f8b	2573	/**
AnnaBridge	165:d1b4690b3f8b	2574	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	165:d1b4690b3f8b	2575	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2576	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2577	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2578	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2579	* output channel is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2580	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	165:d1b4690b3f8b	2581	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2582	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2583	* @retval None
AnnaBridge	165:d1b4690b3f8b	2584	*/
AnnaBridge	165:d1b4690b3f8b	2585	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2586	{
AnnaBridge	165:d1b4690b3f8b	2587	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2588	}
AnnaBridge	165:d1b4690b3f8b	2589
AnnaBridge	165:d1b4690b3f8b	2590	/**
AnnaBridge	165:d1b4690b3f8b	2591	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	165:d1b4690b3f8b	2592	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2593	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2594	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2595	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2596	* output channel 4 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2597	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	165:d1b4690b3f8b	2598	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2599	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2600	* @retval None
AnnaBridge	165:d1b4690b3f8b	2601	*/
AnnaBridge	165:d1b4690b3f8b	2602	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2603	{
AnnaBridge	165:d1b4690b3f8b	2604	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2605	}
AnnaBridge	165:d1b4690b3f8b	2606
AnnaBridge	165:d1b4690b3f8b	2607	/**
AnnaBridge	165:d1b4690b3f8b	2608	* @brief Set compare value for output channel 5 (TIMx_CCR5).
AnnaBridge	165:d1b4690b3f8b	2609	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2610	* output channel 5 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2611	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	165:d1b4690b3f8b	2612	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2613	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2614	* @retval None
AnnaBridge	165:d1b4690b3f8b	2615	*/
AnnaBridge	165:d1b4690b3f8b	2616	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2617	{
AnnaBridge	165:d1b4690b3f8b	2618	WRITE_REG(TIMx->CCR5, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2619	}
AnnaBridge	165:d1b4690b3f8b	2620
AnnaBridge	165:d1b4690b3f8b	2621	/**
AnnaBridge	165:d1b4690b3f8b	2622	* @brief Set compare value for output channel 6 (TIMx_CCR6).
AnnaBridge	165:d1b4690b3f8b	2623	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2624	* output channel 6 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2625	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	165:d1b4690b3f8b	2626	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2627	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:d1b4690b3f8b	2628	* @retval None
AnnaBridge	165:d1b4690b3f8b	2629	*/
AnnaBridge	165:d1b4690b3f8b	2630	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:d1b4690b3f8b	2631	{
AnnaBridge	165:d1b4690b3f8b	2632	WRITE_REG(TIMx->CCR6, CompareValue);
AnnaBridge	165:d1b4690b3f8b	2633	}
AnnaBridge	165:d1b4690b3f8b	2634
AnnaBridge	165:d1b4690b3f8b	2635	/**
AnnaBridge	165:d1b4690b3f8b	2636	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	165:d1b4690b3f8b	2637	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2638	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2639	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2640	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2641	* output channel 1 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2642	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	165:d1b4690b3f8b	2643	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2644	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2645	*/
AnnaBridge	165:d1b4690b3f8b	2646	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2647	{
AnnaBridge	165:d1b4690b3f8b	2648	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	165:d1b4690b3f8b	2649	}
AnnaBridge	165:d1b4690b3f8b	2650
AnnaBridge	165:d1b4690b3f8b	2651	/**
AnnaBridge	165:d1b4690b3f8b	2652	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	165:d1b4690b3f8b	2653	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2654	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2655	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2656	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2657	* output channel 2 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2658	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	165:d1b4690b3f8b	2659	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2660	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2661	*/
AnnaBridge	165:d1b4690b3f8b	2662	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2663	{
AnnaBridge	165:d1b4690b3f8b	2664	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	165:d1b4690b3f8b	2665	}
AnnaBridge	165:d1b4690b3f8b	2666
AnnaBridge	165:d1b4690b3f8b	2667	/**
AnnaBridge	165:d1b4690b3f8b	2668	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	165:d1b4690b3f8b	2669	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2670	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2671	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2672	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2673	* output channel 3 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2674	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	165:d1b4690b3f8b	2675	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2676	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2677	*/
AnnaBridge	165:d1b4690b3f8b	2678	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2679	{
AnnaBridge	165:d1b4690b3f8b	2680	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	165:d1b4690b3f8b	2681	}
AnnaBridge	165:d1b4690b3f8b	2682
AnnaBridge	165:d1b4690b3f8b	2683	/**
AnnaBridge	165:d1b4690b3f8b	2684	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	165:d1b4690b3f8b	2685	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	2686	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2687	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	2688	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2689	* output channel 4 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2690	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	165:d1b4690b3f8b	2691	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2692	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2693	*/
AnnaBridge	165:d1b4690b3f8b	2694	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2695	{
AnnaBridge	165:d1b4690b3f8b	2696	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	165:d1b4690b3f8b	2697	}
AnnaBridge	165:d1b4690b3f8b	2698
AnnaBridge	165:d1b4690b3f8b	2699	/**
AnnaBridge	165:d1b4690b3f8b	2700	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
AnnaBridge	165:d1b4690b3f8b	2701	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2702	* output channel 5 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2703	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	165:d1b4690b3f8b	2704	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2705	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2706	*/
AnnaBridge	165:d1b4690b3f8b	2707	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2708	{
AnnaBridge	165:d1b4690b3f8b	2709	return (uint32_t)(READ_REG(TIMx->CCR5));
AnnaBridge	165:d1b4690b3f8b	2710	}
AnnaBridge	165:d1b4690b3f8b	2711
AnnaBridge	165:d1b4690b3f8b	2712	/**
AnnaBridge	165:d1b4690b3f8b	2713	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
AnnaBridge	165:d1b4690b3f8b	2714	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	2715	* output channel 6 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	2716	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	165:d1b4690b3f8b	2717	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2718	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	2719	*/
AnnaBridge	165:d1b4690b3f8b	2720	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	2721	{
AnnaBridge	165:d1b4690b3f8b	2722	return (uint32_t)(READ_REG(TIMx->CCR6));
AnnaBridge	165:d1b4690b3f8b	2723	}
AnnaBridge	165:d1b4690b3f8b	2724
AnnaBridge	165:d1b4690b3f8b	2725	/**
AnnaBridge	165:d1b4690b3f8b	2726	* @brief Select on which reference signal the OC5REF is combined to.
AnnaBridge	165:d1b4690b3f8b	2727	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	2728	* whether or not a timer instance supports the combined 3-phase PWM mode.
AnnaBridge	165:d1b4690b3f8b	2729	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	165:d1b4690b3f8b	2730	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	165:d1b4690b3f8b	2731	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	165:d1b4690b3f8b	2732	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2733	* @param GroupCH5 This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2734	* @arg @ref LL_TIM_GROUPCH5_NONE
AnnaBridge	165:d1b4690b3f8b	2735	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
AnnaBridge	165:d1b4690b3f8b	2736	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
AnnaBridge	165:d1b4690b3f8b	2737	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
AnnaBridge	165:d1b4690b3f8b	2738	* @retval None
AnnaBridge	165:d1b4690b3f8b	2739	*/
AnnaBridge	165:d1b4690b3f8b	2740	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
AnnaBridge	165:d1b4690b3f8b	2741	{
AnnaBridge	165:d1b4690b3f8b	2742	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
AnnaBridge	165:d1b4690b3f8b	2743	}
AnnaBridge	165:d1b4690b3f8b	2744
AnnaBridge	165:d1b4690b3f8b	2745	/**
AnnaBridge	165:d1b4690b3f8b	2746	* @}
AnnaBridge	165:d1b4690b3f8b	2747	*/
AnnaBridge	165:d1b4690b3f8b	2748
AnnaBridge	165:d1b4690b3f8b	2749	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	165:d1b4690b3f8b	2750	* @{
AnnaBridge	165:d1b4690b3f8b	2751	*/
AnnaBridge	165:d1b4690b3f8b	2752	/**
AnnaBridge	165:d1b4690b3f8b	2753	* @brief Configure input channel.
AnnaBridge	165:d1b4690b3f8b	2754	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2755	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2756	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2757	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2758	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2759	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2760	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2761	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2762	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2763	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2764	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2765	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2766	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2767	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2768	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2769	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2770	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2771	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2772	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	165:d1b4690b3f8b	2773	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	165:d1b4690b3f8b	2774	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2775	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2776	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2777	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2778	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2779	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2780	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	165:d1b4690b3f8b	2781	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:d1b4690b3f8b	2782	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:d1b4690b3f8b	2783	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	2784	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	165:d1b4690b3f8b	2785	* @retval None
AnnaBridge	165:d1b4690b3f8b	2786	*/
AnnaBridge	165:d1b4690b3f8b	2787	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	165:d1b4690b3f8b	2788	{
AnnaBridge	165:d1b4690b3f8b	2789	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2790	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2791	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	165:d1b4690b3f8b	2792	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2793	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:d1b4690b3f8b	2794	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2795	}
AnnaBridge	165:d1b4690b3f8b	2796
AnnaBridge	165:d1b4690b3f8b	2797	/**
AnnaBridge	165:d1b4690b3f8b	2798	* @brief Set the active input.
AnnaBridge	165:d1b4690b3f8b	2799	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2800	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2801	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2802	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	165:d1b4690b3f8b	2803	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2804	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2805	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2806	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2807	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2808	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2809	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2810	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	165:d1b4690b3f8b	2811	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	165:d1b4690b3f8b	2812	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:d1b4690b3f8b	2813	* @retval None
AnnaBridge	165:d1b4690b3f8b	2814	*/
AnnaBridge	165:d1b4690b3f8b	2815	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	165:d1b4690b3f8b	2816	{
AnnaBridge	165:d1b4690b3f8b	2817	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2818	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2819	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2820	}
AnnaBridge	165:d1b4690b3f8b	2821
AnnaBridge	165:d1b4690b3f8b	2822	/**
AnnaBridge	165:d1b4690b3f8b	2823	* @brief Get the current active input.
AnnaBridge	165:d1b4690b3f8b	2824	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2825	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2826	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:d1b4690b3f8b	2827	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	165:d1b4690b3f8b	2828	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2829	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2830	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2831	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2832	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2833	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2834	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2835	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	165:d1b4690b3f8b	2836	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	165:d1b4690b3f8b	2837	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:d1b4690b3f8b	2838	*/
AnnaBridge	165:d1b4690b3f8b	2839	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2840	{
AnnaBridge	165:d1b4690b3f8b	2841	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2842	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2843	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:d1b4690b3f8b	2844	}
AnnaBridge	165:d1b4690b3f8b	2845
AnnaBridge	165:d1b4690b3f8b	2846	/**
AnnaBridge	165:d1b4690b3f8b	2847	* @brief Set the prescaler of input channel.
AnnaBridge	165:d1b4690b3f8b	2848	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2849	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2850	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2851	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	165:d1b4690b3f8b	2852	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2853	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2854	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2855	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2856	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2857	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2858	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2859	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:d1b4690b3f8b	2860	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:d1b4690b3f8b	2861	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:d1b4690b3f8b	2862	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:d1b4690b3f8b	2863	* @retval None
AnnaBridge	165:d1b4690b3f8b	2864	*/
AnnaBridge	165:d1b4690b3f8b	2865	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	165:d1b4690b3f8b	2866	{
AnnaBridge	165:d1b4690b3f8b	2867	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2868	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2869	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2870	}
AnnaBridge	165:d1b4690b3f8b	2871
AnnaBridge	165:d1b4690b3f8b	2872	/**
AnnaBridge	165:d1b4690b3f8b	2873	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	165:d1b4690b3f8b	2874	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2875	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2876	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:d1b4690b3f8b	2877	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	165:d1b4690b3f8b	2878	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2879	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2880	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2881	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2882	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2883	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2884	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2885	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:d1b4690b3f8b	2886	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:d1b4690b3f8b	2887	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:d1b4690b3f8b	2888	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:d1b4690b3f8b	2889	*/
AnnaBridge	165:d1b4690b3f8b	2890	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2891	{
AnnaBridge	165:d1b4690b3f8b	2892	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2893	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2894	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:d1b4690b3f8b	2895	}
AnnaBridge	165:d1b4690b3f8b	2896
AnnaBridge	165:d1b4690b3f8b	2897	/**
AnnaBridge	165:d1b4690b3f8b	2898	* @brief Set the input filter duration.
AnnaBridge	165:d1b4690b3f8b	2899	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	165:d1b4690b3f8b	2900	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	165:d1b4690b3f8b	2901	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	165:d1b4690b3f8b	2902	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	165:d1b4690b3f8b	2903	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2904	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2905	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2906	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2907	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2908	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2909	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2910	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	165:d1b4690b3f8b	2911	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	165:d1b4690b3f8b	2912	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	165:d1b4690b3f8b	2913	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	165:d1b4690b3f8b	2914	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	165:d1b4690b3f8b	2915	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	165:d1b4690b3f8b	2916	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	165:d1b4690b3f8b	2917	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	165:d1b4690b3f8b	2918	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	165:d1b4690b3f8b	2919	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	165:d1b4690b3f8b	2920	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	165:d1b4690b3f8b	2921	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	165:d1b4690b3f8b	2922	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	165:d1b4690b3f8b	2923	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	165:d1b4690b3f8b	2924	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	165:d1b4690b3f8b	2925	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	2926	* @retval None
AnnaBridge	165:d1b4690b3f8b	2927	*/
AnnaBridge	165:d1b4690b3f8b	2928	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	165:d1b4690b3f8b	2929	{
AnnaBridge	165:d1b4690b3f8b	2930	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2931	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2932	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2933	}
AnnaBridge	165:d1b4690b3f8b	2934
AnnaBridge	165:d1b4690b3f8b	2935	/**
AnnaBridge	165:d1b4690b3f8b	2936	* @brief Get the input filter duration.
AnnaBridge	165:d1b4690b3f8b	2937	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	165:d1b4690b3f8b	2938	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	165:d1b4690b3f8b	2939	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	165:d1b4690b3f8b	2940	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	165:d1b4690b3f8b	2941	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2942	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2943	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2944	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2945	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2946	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2947	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2948	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	165:d1b4690b3f8b	2949	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	165:d1b4690b3f8b	2950	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	165:d1b4690b3f8b	2951	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	165:d1b4690b3f8b	2952	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	165:d1b4690b3f8b	2953	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	165:d1b4690b3f8b	2954	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	165:d1b4690b3f8b	2955	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	165:d1b4690b3f8b	2956	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	165:d1b4690b3f8b	2957	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	165:d1b4690b3f8b	2958	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	165:d1b4690b3f8b	2959	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	165:d1b4690b3f8b	2960	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	165:d1b4690b3f8b	2961	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	165:d1b4690b3f8b	2962	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	165:d1b4690b3f8b	2963	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	2964	*/
AnnaBridge	165:d1b4690b3f8b	2965	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	2966	{
AnnaBridge	165:d1b4690b3f8b	2967	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2968	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:d1b4690b3f8b	2969	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:d1b4690b3f8b	2970	}
AnnaBridge	165:d1b4690b3f8b	2971
AnnaBridge	165:d1b4690b3f8b	2972	/**
AnnaBridge	165:d1b4690b3f8b	2973	* @brief Set the input channel polarity.
AnnaBridge	165:d1b4690b3f8b	2974	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2975	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2976	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2977	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2978	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2979	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2980	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:d1b4690b3f8b	2981	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	165:d1b4690b3f8b	2982	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	2983	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2984	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	2985	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	2986	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	2987	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	2988	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2989	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	165:d1b4690b3f8b	2990	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	165:d1b4690b3f8b	2991	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	165:d1b4690b3f8b	2992	* @retval None
AnnaBridge	165:d1b4690b3f8b	2993	*/
AnnaBridge	165:d1b4690b3f8b	2994	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	165:d1b4690b3f8b	2995	{
AnnaBridge	165:d1b4690b3f8b	2996	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	2997	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:d1b4690b3f8b	2998	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	2999	}
AnnaBridge	165:d1b4690b3f8b	3000
AnnaBridge	165:d1b4690b3f8b	3001	/**
AnnaBridge	165:d1b4690b3f8b	3002	* @brief Get the current input channel polarity.
AnnaBridge	165:d1b4690b3f8b	3003	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3004	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3005	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3006	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3007	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3008	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3009	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:d1b4690b3f8b	3010	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	165:d1b4690b3f8b	3011	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3012	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3013	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:d1b4690b3f8b	3014	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:d1b4690b3f8b	3015	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:d1b4690b3f8b	3016	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:d1b4690b3f8b	3017	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3018	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	165:d1b4690b3f8b	3019	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	165:d1b4690b3f8b	3020	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	165:d1b4690b3f8b	3021	*/
AnnaBridge	165:d1b4690b3f8b	3022	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:d1b4690b3f8b	3023	{
AnnaBridge	165:d1b4690b3f8b	3024	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:d1b4690b3f8b	3025	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	165:d1b4690b3f8b	3026	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:d1b4690b3f8b	3027	}
AnnaBridge	165:d1b4690b3f8b	3028
AnnaBridge	165:d1b4690b3f8b	3029	/**
AnnaBridge	165:d1b4690b3f8b	3030	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	165:d1b4690b3f8b	3031	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3032	* a timer instance provides an XOR input.
AnnaBridge	165:d1b4690b3f8b	3033	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	165:d1b4690b3f8b	3034	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3035	* @retval None
AnnaBridge	165:d1b4690b3f8b	3036	*/
AnnaBridge	165:d1b4690b3f8b	3037	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3038	{
AnnaBridge	165:d1b4690b3f8b	3039	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	165:d1b4690b3f8b	3040	}
AnnaBridge	165:d1b4690b3f8b	3041
AnnaBridge	165:d1b4690b3f8b	3042	/**
AnnaBridge	165:d1b4690b3f8b	3043	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	165:d1b4690b3f8b	3044	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3045	* a timer instance provides an XOR input.
AnnaBridge	165:d1b4690b3f8b	3046	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	165:d1b4690b3f8b	3047	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3048	* @retval None
AnnaBridge	165:d1b4690b3f8b	3049	*/
AnnaBridge	165:d1b4690b3f8b	3050	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3051	{
AnnaBridge	165:d1b4690b3f8b	3052	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	165:d1b4690b3f8b	3053	}
AnnaBridge	165:d1b4690b3f8b	3054
AnnaBridge	165:d1b4690b3f8b	3055	/**
AnnaBridge	165:d1b4690b3f8b	3056	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	165:d1b4690b3f8b	3057	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3058	* a timer instance provides an XOR input.
AnnaBridge	165:d1b4690b3f8b	3059	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	165:d1b4690b3f8b	3060	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3061	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3062	*/
AnnaBridge	165:d1b4690b3f8b	3063	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3064	{
AnnaBridge	165:d1b4690b3f8b	3065	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	165:d1b4690b3f8b	3066	}
AnnaBridge	165:d1b4690b3f8b	3067
AnnaBridge	165:d1b4690b3f8b	3068	/**
AnnaBridge	165:d1b4690b3f8b	3069	* @brief Get captured value for input channel 1.
AnnaBridge	165:d1b4690b3f8b	3070	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	3071	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3072	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	3073	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3074	* input channel 1 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	3075	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	165:d1b4690b3f8b	3076	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3077	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	3078	*/
AnnaBridge	165:d1b4690b3f8b	3079	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3080	{
AnnaBridge	165:d1b4690b3f8b	3081	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	165:d1b4690b3f8b	3082	}
AnnaBridge	165:d1b4690b3f8b	3083
AnnaBridge	165:d1b4690b3f8b	3084	/**
AnnaBridge	165:d1b4690b3f8b	3085	* @brief Get captured value for input channel 2.
AnnaBridge	165:d1b4690b3f8b	3086	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	3087	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3088	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	3089	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3090	* input channel 2 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	3091	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	165:d1b4690b3f8b	3092	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3093	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	3094	*/
AnnaBridge	165:d1b4690b3f8b	3095	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3096	{
AnnaBridge	165:d1b4690b3f8b	3097	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	165:d1b4690b3f8b	3098	}
AnnaBridge	165:d1b4690b3f8b	3099
AnnaBridge	165:d1b4690b3f8b	3100	/**
AnnaBridge	165:d1b4690b3f8b	3101	* @brief Get captured value for input channel 3.
AnnaBridge	165:d1b4690b3f8b	3102	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	3103	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3104	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	3105	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3106	* input channel 3 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	3107	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	165:d1b4690b3f8b	3108	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3109	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	3110	*/
AnnaBridge	165:d1b4690b3f8b	3111	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3112	{
AnnaBridge	165:d1b4690b3f8b	3113	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	165:d1b4690b3f8b	3114	}
AnnaBridge	165:d1b4690b3f8b	3115
AnnaBridge	165:d1b4690b3f8b	3116	/**
AnnaBridge	165:d1b4690b3f8b	3117	* @brief Get captured value for input channel 4.
AnnaBridge	165:d1b4690b3f8b	3118	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	165:d1b4690b3f8b	3119	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3120	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	165:d1b4690b3f8b	3121	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3122	* input channel 4 is supported by a timer instance.
AnnaBridge	165:d1b4690b3f8b	3123	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	165:d1b4690b3f8b	3124	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3125	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:d1b4690b3f8b	3126	*/
AnnaBridge	165:d1b4690b3f8b	3127	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3128	{
AnnaBridge	165:d1b4690b3f8b	3129	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	165:d1b4690b3f8b	3130	}
AnnaBridge	165:d1b4690b3f8b	3131
AnnaBridge	165:d1b4690b3f8b	3132	/**
AnnaBridge	165:d1b4690b3f8b	3133	* @}
AnnaBridge	165:d1b4690b3f8b	3134	*/
AnnaBridge	165:d1b4690b3f8b	3135
AnnaBridge	165:d1b4690b3f8b	3136	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	165:d1b4690b3f8b	3137	* @{
AnnaBridge	165:d1b4690b3f8b	3138	*/
AnnaBridge	165:d1b4690b3f8b	3139	/**
AnnaBridge	165:d1b4690b3f8b	3140	* @brief Enable external clock mode 2.
AnnaBridge	165:d1b4690b3f8b	3141	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	165:d1b4690b3f8b	3142	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3143	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:d1b4690b3f8b	3144	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	165:d1b4690b3f8b	3145	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3146	* @retval None
AnnaBridge	165:d1b4690b3f8b	3147	*/
AnnaBridge	165:d1b4690b3f8b	3148	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3149	{
AnnaBridge	165:d1b4690b3f8b	3150	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	165:d1b4690b3f8b	3151	}
AnnaBridge	165:d1b4690b3f8b	3152
AnnaBridge	165:d1b4690b3f8b	3153	/**
AnnaBridge	165:d1b4690b3f8b	3154	* @brief Disable external clock mode 2.
AnnaBridge	165:d1b4690b3f8b	3155	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3156	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:d1b4690b3f8b	3157	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	165:d1b4690b3f8b	3158	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3159	* @retval None
AnnaBridge	165:d1b4690b3f8b	3160	*/
AnnaBridge	165:d1b4690b3f8b	3161	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3162	{
AnnaBridge	165:d1b4690b3f8b	3163	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	165:d1b4690b3f8b	3164	}
AnnaBridge	165:d1b4690b3f8b	3165
AnnaBridge	165:d1b4690b3f8b	3166	/**
AnnaBridge	165:d1b4690b3f8b	3167	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	165:d1b4690b3f8b	3168	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3169	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:d1b4690b3f8b	3170	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	165:d1b4690b3f8b	3171	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3172	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3173	*/
AnnaBridge	165:d1b4690b3f8b	3174	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3175	{
AnnaBridge	165:d1b4690b3f8b	3176	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	165:d1b4690b3f8b	3177	}
AnnaBridge	165:d1b4690b3f8b	3178
AnnaBridge	165:d1b4690b3f8b	3179	/**
AnnaBridge	165:d1b4690b3f8b	3180	* @brief Set the clock source of the counter clock.
AnnaBridge	165:d1b4690b3f8b	3181	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	165:d1b4690b3f8b	3182	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	165:d1b4690b3f8b	3183	* function. This timer input must be configured by calling
AnnaBridge	165:d1b4690b3f8b	3184	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	165:d1b4690b3f8b	3185	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3186	* whether or not a timer instance supports external clock mode1.
AnnaBridge	165:d1b4690b3f8b	3187	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3188	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:d1b4690b3f8b	3189	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	165:d1b4690b3f8b	3190	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	165:d1b4690b3f8b	3191	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3192	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3193	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	165:d1b4690b3f8b	3194	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	165:d1b4690b3f8b	3195	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	165:d1b4690b3f8b	3196	* @retval None
AnnaBridge	165:d1b4690b3f8b	3197	*/
AnnaBridge	165:d1b4690b3f8b	3198	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	165:d1b4690b3f8b	3199	{
AnnaBridge	165:d1b4690b3f8b	3200	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	165:d1b4690b3f8b	3201	}
AnnaBridge	165:d1b4690b3f8b	3202
AnnaBridge	165:d1b4690b3f8b	3203	/**
AnnaBridge	165:d1b4690b3f8b	3204	* @brief Set the encoder interface mode.
AnnaBridge	165:d1b4690b3f8b	3205	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3206	* whether or not a timer instance supports the encoder mode.
AnnaBridge	165:d1b4690b3f8b	3207	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	165:d1b4690b3f8b	3208	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3209	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3210	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	165:d1b4690b3f8b	3211	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	165:d1b4690b3f8b	3212	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	165:d1b4690b3f8b	3213	* @retval None
AnnaBridge	165:d1b4690b3f8b	3214	*/
AnnaBridge	165:d1b4690b3f8b	3215	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	165:d1b4690b3f8b	3216	{
AnnaBridge	165:d1b4690b3f8b	3217	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	165:d1b4690b3f8b	3218	}
AnnaBridge	165:d1b4690b3f8b	3219
AnnaBridge	165:d1b4690b3f8b	3220	/**
AnnaBridge	165:d1b4690b3f8b	3221	* @}
AnnaBridge	165:d1b4690b3f8b	3222	*/
AnnaBridge	165:d1b4690b3f8b	3223
AnnaBridge	165:d1b4690b3f8b	3224	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	165:d1b4690b3f8b	3225	* @{
AnnaBridge	165:d1b4690b3f8b	3226	*/
AnnaBridge	165:d1b4690b3f8b	3227	/**
AnnaBridge	165:d1b4690b3f8b	3228	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	165:d1b4690b3f8b	3229	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3230	* whether or not a timer instance can operate as a master timer.
AnnaBridge	165:d1b4690b3f8b	3231	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	165:d1b4690b3f8b	3232	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3233	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3234	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	165:d1b4690b3f8b	3235	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	165:d1b4690b3f8b	3236	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	165:d1b4690b3f8b	3237	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	165:d1b4690b3f8b	3238	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	165:d1b4690b3f8b	3239	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	165:d1b4690b3f8b	3240	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	165:d1b4690b3f8b	3241	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	165:d1b4690b3f8b	3242	* @retval None
AnnaBridge	165:d1b4690b3f8b	3243	*/
AnnaBridge	165:d1b4690b3f8b	3244	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	165:d1b4690b3f8b	3245	{
AnnaBridge	165:d1b4690b3f8b	3246	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	165:d1b4690b3f8b	3247	}
AnnaBridge	165:d1b4690b3f8b	3248
AnnaBridge	165:d1b4690b3f8b	3249	/**
AnnaBridge	165:d1b4690b3f8b	3250	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
AnnaBridge	165:d1b4690b3f8b	3251	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:d1b4690b3f8b	3252	* whether or not a timer instance can be used for ADC synchronization.
AnnaBridge	165:d1b4690b3f8b	3253	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
AnnaBridge	165:d1b4690b3f8b	3254	* @param TIMx Timer Instance
AnnaBridge	165:d1b4690b3f8b	3255	* @param ADCSynchronization This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3256	* @arg @ref LL_TIM_TRGO2_RESET
AnnaBridge	165:d1b4690b3f8b	3257	* @arg @ref LL_TIM_TRGO2_ENABLE
AnnaBridge	165:d1b4690b3f8b	3258	* @arg @ref LL_TIM_TRGO2_UPDATE
AnnaBridge	165:d1b4690b3f8b	3259	* @arg @ref LL_TIM_TRGO2_CC1F
AnnaBridge	165:d1b4690b3f8b	3260	* @arg @ref LL_TIM_TRGO2_OC1
AnnaBridge	165:d1b4690b3f8b	3261	* @arg @ref LL_TIM_TRGO2_OC2
AnnaBridge	165:d1b4690b3f8b	3262	* @arg @ref LL_TIM_TRGO2_OC3
AnnaBridge	165:d1b4690b3f8b	3263	* @arg @ref LL_TIM_TRGO2_OC4
AnnaBridge	165:d1b4690b3f8b	3264	* @arg @ref LL_TIM_TRGO2_OC5
AnnaBridge	165:d1b4690b3f8b	3265	* @arg @ref LL_TIM_TRGO2_OC6
AnnaBridge	165:d1b4690b3f8b	3266	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
AnnaBridge	165:d1b4690b3f8b	3267	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
AnnaBridge	165:d1b4690b3f8b	3268	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
AnnaBridge	165:d1b4690b3f8b	3269	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
AnnaBridge	165:d1b4690b3f8b	3270	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
AnnaBridge	165:d1b4690b3f8b	3271	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
AnnaBridge	165:d1b4690b3f8b	3272	* @retval None
AnnaBridge	165:d1b4690b3f8b	3273	*/
AnnaBridge	165:d1b4690b3f8b	3274	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
AnnaBridge	165:d1b4690b3f8b	3275	{
AnnaBridge	165:d1b4690b3f8b	3276	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
AnnaBridge	165:d1b4690b3f8b	3277	}
AnnaBridge	165:d1b4690b3f8b	3278
AnnaBridge	165:d1b4690b3f8b	3279	/**
AnnaBridge	165:d1b4690b3f8b	3280	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	165:d1b4690b3f8b	3281	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3282	* a timer instance can operate as a slave timer.
AnnaBridge	165:d1b4690b3f8b	3283	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	165:d1b4690b3f8b	3284	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3285	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3286	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	165:d1b4690b3f8b	3287	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	165:d1b4690b3f8b	3288	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	165:d1b4690b3f8b	3289	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	165:d1b4690b3f8b	3290	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
AnnaBridge	165:d1b4690b3f8b	3291	* @retval None
AnnaBridge	165:d1b4690b3f8b	3292	*/
AnnaBridge	165:d1b4690b3f8b	3293	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	165:d1b4690b3f8b	3294	{
AnnaBridge	165:d1b4690b3f8b	3295	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	165:d1b4690b3f8b	3296	}
AnnaBridge	165:d1b4690b3f8b	3297
AnnaBridge	165:d1b4690b3f8b	3298	/**
AnnaBridge	165:d1b4690b3f8b	3299	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	165:d1b4690b3f8b	3300	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3301	* a timer instance can operate as a slave timer.
AnnaBridge	165:d1b4690b3f8b	3302	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	165:d1b4690b3f8b	3303	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3304	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3305	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	165:d1b4690b3f8b	3306	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	165:d1b4690b3f8b	3307	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	165:d1b4690b3f8b	3308	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	165:d1b4690b3f8b	3309	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	165:d1b4690b3f8b	3310	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	165:d1b4690b3f8b	3311	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	165:d1b4690b3f8b	3312	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	165:d1b4690b3f8b	3313	* @retval None
AnnaBridge	165:d1b4690b3f8b	3314	*/
AnnaBridge	165:d1b4690b3f8b	3315	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	165:d1b4690b3f8b	3316	{
AnnaBridge	165:d1b4690b3f8b	3317	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	165:d1b4690b3f8b	3318	}
AnnaBridge	165:d1b4690b3f8b	3319
AnnaBridge	165:d1b4690b3f8b	3320	/**
AnnaBridge	165:d1b4690b3f8b	3321	* @brief Enable the Master/Slave mode.
AnnaBridge	165:d1b4690b3f8b	3322	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3323	* a timer instance can operate as a slave timer.
AnnaBridge	165:d1b4690b3f8b	3324	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	165:d1b4690b3f8b	3325	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3326	* @retval None
AnnaBridge	165:d1b4690b3f8b	3327	*/
AnnaBridge	165:d1b4690b3f8b	3328	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3329	{
AnnaBridge	165:d1b4690b3f8b	3330	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	165:d1b4690b3f8b	3331	}
AnnaBridge	165:d1b4690b3f8b	3332
AnnaBridge	165:d1b4690b3f8b	3333	/**
AnnaBridge	165:d1b4690b3f8b	3334	* @brief Disable the Master/Slave mode.
AnnaBridge	165:d1b4690b3f8b	3335	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3336	* a timer instance can operate as a slave timer.
AnnaBridge	165:d1b4690b3f8b	3337	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	165:d1b4690b3f8b	3338	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3339	* @retval None
AnnaBridge	165:d1b4690b3f8b	3340	*/
AnnaBridge	165:d1b4690b3f8b	3341	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3342	{
AnnaBridge	165:d1b4690b3f8b	3343	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	165:d1b4690b3f8b	3344	}
AnnaBridge	165:d1b4690b3f8b	3345
AnnaBridge	165:d1b4690b3f8b	3346	/**
AnnaBridge	165:d1b4690b3f8b	3347	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	165:d1b4690b3f8b	3348	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3349	* a timer instance can operate as a slave timer.
AnnaBridge	165:d1b4690b3f8b	3350	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	165:d1b4690b3f8b	3351	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3352	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3353	*/
AnnaBridge	165:d1b4690b3f8b	3354	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3355	{
AnnaBridge	165:d1b4690b3f8b	3356	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	165:d1b4690b3f8b	3357	}
AnnaBridge	165:d1b4690b3f8b	3358
AnnaBridge	165:d1b4690b3f8b	3359	/**
AnnaBridge	165:d1b4690b3f8b	3360	* @brief Configure the external trigger (ETR) input.
AnnaBridge	165:d1b4690b3f8b	3361	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3362	* a timer instance provides an external trigger input.
AnnaBridge	165:d1b4690b3f8b	3363	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	165:d1b4690b3f8b	3364	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	165:d1b4690b3f8b	3365	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	165:d1b4690b3f8b	3366	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3367	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3368	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	165:d1b4690b3f8b	3369	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	165:d1b4690b3f8b	3370	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3371	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	165:d1b4690b3f8b	3372	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	165:d1b4690b3f8b	3373	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	165:d1b4690b3f8b	3374	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	165:d1b4690b3f8b	3375	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3376	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	165:d1b4690b3f8b	3377	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	165:d1b4690b3f8b	3378	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	165:d1b4690b3f8b	3379	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	165:d1b4690b3f8b	3380	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	165:d1b4690b3f8b	3381	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	165:d1b4690b3f8b	3382	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	165:d1b4690b3f8b	3383	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	165:d1b4690b3f8b	3384	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	165:d1b4690b3f8b	3385	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	165:d1b4690b3f8b	3386	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	165:d1b4690b3f8b	3387	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	165:d1b4690b3f8b	3388	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	165:d1b4690b3f8b	3389	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	165:d1b4690b3f8b	3390	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	165:d1b4690b3f8b	3391	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	3392	* @retval None
AnnaBridge	165:d1b4690b3f8b	3393	*/
AnnaBridge	165:d1b4690b3f8b	3394	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	165:d1b4690b3f8b	3395	uint32_t ETRFilter)
AnnaBridge	165:d1b4690b3f8b	3396	{
AnnaBridge	165:d1b4690b3f8b	3397	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	165:d1b4690b3f8b	3398	}
AnnaBridge	165:d1b4690b3f8b	3399
AnnaBridge	165:d1b4690b3f8b	3400	/**
AnnaBridge	165:d1b4690b3f8b	3401	* @brief Select the external trigger (ETR) input source.
AnnaBridge	165:d1b4690b3f8b	3402	* @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	165:d1b4690b3f8b	3403	* not a timer instance supports ETR source selection.
AnnaBridge	165:d1b4690b3f8b	3404	* @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
AnnaBridge	165:d1b4690b3f8b	3405	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3406	* @param ETRSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3407	* @arg @ref LL_TIM_ETRSOURCE_LEGACY
AnnaBridge	165:d1b4690b3f8b	3408	* @arg @ref LL_TIM_ETRSOURCE_COMP1
AnnaBridge	165:d1b4690b3f8b	3409	* @arg @ref LL_TIM_ETRSOURCE_COMP2
AnnaBridge	165:d1b4690b3f8b	3410	* @retval None
AnnaBridge	165:d1b4690b3f8b	3411	*/
AnnaBridge	165:d1b4690b3f8b	3412	__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
AnnaBridge	165:d1b4690b3f8b	3413	{
AnnaBridge	165:d1b4690b3f8b	3414
AnnaBridge	165:d1b4690b3f8b	3415	MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
AnnaBridge	165:d1b4690b3f8b	3416	}
AnnaBridge	165:d1b4690b3f8b	3417
AnnaBridge	165:d1b4690b3f8b	3418	/**
AnnaBridge	165:d1b4690b3f8b	3419	* @}
AnnaBridge	165:d1b4690b3f8b	3420	*/
AnnaBridge	165:d1b4690b3f8b	3421
AnnaBridge	165:d1b4690b3f8b	3422	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	165:d1b4690b3f8b	3423	* @{
AnnaBridge	165:d1b4690b3f8b	3424	*/
AnnaBridge	165:d1b4690b3f8b	3425	/**
AnnaBridge	165:d1b4690b3f8b	3426	* @brief Enable the break function.
AnnaBridge	165:d1b4690b3f8b	3427	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3428	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3429	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	165:d1b4690b3f8b	3430	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3431	* @retval None
AnnaBridge	165:d1b4690b3f8b	3432	*/
AnnaBridge	165:d1b4690b3f8b	3433	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3434	{
AnnaBridge	165:d1b4690b3f8b	3435	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	165:d1b4690b3f8b	3436	}
AnnaBridge	165:d1b4690b3f8b	3437
AnnaBridge	165:d1b4690b3f8b	3438	/**
AnnaBridge	165:d1b4690b3f8b	3439	* @brief Disable the break function.
AnnaBridge	165:d1b4690b3f8b	3440	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	165:d1b4690b3f8b	3441	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3442	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3443	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3444	* @retval None
AnnaBridge	165:d1b4690b3f8b	3445	*/
AnnaBridge	165:d1b4690b3f8b	3446	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3447	{
AnnaBridge	165:d1b4690b3f8b	3448	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	165:d1b4690b3f8b	3449	}
AnnaBridge	165:d1b4690b3f8b	3450
AnnaBridge	165:d1b4690b3f8b	3451	/**
AnnaBridge	165:d1b4690b3f8b	3452	* @brief Configure the break input.
AnnaBridge	165:d1b4690b3f8b	3453	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3454	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3455	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
AnnaBridge	165:d1b4690b3f8b	3456	* BDTR BKF LL_TIM_ConfigBRK
AnnaBridge	165:d1b4690b3f8b	3457	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3458	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3459	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	3460	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	165:d1b4690b3f8b	3461	* @param BreakFilter This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3462	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
AnnaBridge	165:d1b4690b3f8b	3463	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
AnnaBridge	165:d1b4690b3f8b	3464	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
AnnaBridge	165:d1b4690b3f8b	3465	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
AnnaBridge	165:d1b4690b3f8b	3466	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
AnnaBridge	165:d1b4690b3f8b	3467	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
AnnaBridge	165:d1b4690b3f8b	3468	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
AnnaBridge	165:d1b4690b3f8b	3469	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
AnnaBridge	165:d1b4690b3f8b	3470	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
AnnaBridge	165:d1b4690b3f8b	3471	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
AnnaBridge	165:d1b4690b3f8b	3472	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
AnnaBridge	165:d1b4690b3f8b	3473	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
AnnaBridge	165:d1b4690b3f8b	3474	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
AnnaBridge	165:d1b4690b3f8b	3475	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
AnnaBridge	165:d1b4690b3f8b	3476	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
AnnaBridge	165:d1b4690b3f8b	3477	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	3478	* @retval None
AnnaBridge	165:d1b4690b3f8b	3479	*/
AnnaBridge	165:d1b4690b3f8b	3480	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
AnnaBridge	165:d1b4690b3f8b	3481	{
AnnaBridge	165:d1b4690b3f8b	3482	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
AnnaBridge	165:d1b4690b3f8b	3483	}
AnnaBridge	165:d1b4690b3f8b	3484
AnnaBridge	165:d1b4690b3f8b	3485	/**
AnnaBridge	165:d1b4690b3f8b	3486	* @brief Enable the break 2 function.
AnnaBridge	165:d1b4690b3f8b	3487	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3488	* a timer instance provides a second break input.
AnnaBridge	165:d1b4690b3f8b	3489	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
AnnaBridge	165:d1b4690b3f8b	3490	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3491	* @retval None
AnnaBridge	165:d1b4690b3f8b	3492	*/
AnnaBridge	165:d1b4690b3f8b	3493	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3494	{
AnnaBridge	165:d1b4690b3f8b	3495	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	165:d1b4690b3f8b	3496	}
AnnaBridge	165:d1b4690b3f8b	3497
AnnaBridge	165:d1b4690b3f8b	3498	/**
AnnaBridge	165:d1b4690b3f8b	3499	* @brief Disable the break 2 function.
AnnaBridge	165:d1b4690b3f8b	3500	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3501	* a timer instance provides a second break input.
AnnaBridge	165:d1b4690b3f8b	3502	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
AnnaBridge	165:d1b4690b3f8b	3503	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3504	* @retval None
AnnaBridge	165:d1b4690b3f8b	3505	*/
AnnaBridge	165:d1b4690b3f8b	3506	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3507	{
AnnaBridge	165:d1b4690b3f8b	3508	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	165:d1b4690b3f8b	3509	}
AnnaBridge	165:d1b4690b3f8b	3510
AnnaBridge	165:d1b4690b3f8b	3511	/**
AnnaBridge	165:d1b4690b3f8b	3512	* @brief Configure the break 2 input.
AnnaBridge	165:d1b4690b3f8b	3513	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3514	* a timer instance provides a second break input.
AnnaBridge	165:d1b4690b3f8b	3515	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
AnnaBridge	165:d1b4690b3f8b	3516	* BDTR BK2F LL_TIM_ConfigBRK2
AnnaBridge	165:d1b4690b3f8b	3517	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3518	* @param Break2Polarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3519	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	3520	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
AnnaBridge	165:d1b4690b3f8b	3521	* @param Break2Filter This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3522	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
AnnaBridge	165:d1b4690b3f8b	3523	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
AnnaBridge	165:d1b4690b3f8b	3524	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
AnnaBridge	165:d1b4690b3f8b	3525	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
AnnaBridge	165:d1b4690b3f8b	3526	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
AnnaBridge	165:d1b4690b3f8b	3527	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
AnnaBridge	165:d1b4690b3f8b	3528	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
AnnaBridge	165:d1b4690b3f8b	3529	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
AnnaBridge	165:d1b4690b3f8b	3530	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
AnnaBridge	165:d1b4690b3f8b	3531	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
AnnaBridge	165:d1b4690b3f8b	3532	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
AnnaBridge	165:d1b4690b3f8b	3533	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
AnnaBridge	165:d1b4690b3f8b	3534	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
AnnaBridge	165:d1b4690b3f8b	3535	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
AnnaBridge	165:d1b4690b3f8b	3536	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
AnnaBridge	165:d1b4690b3f8b	3537	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
AnnaBridge	165:d1b4690b3f8b	3538	* @retval None
AnnaBridge	165:d1b4690b3f8b	3539	*/
AnnaBridge	165:d1b4690b3f8b	3540	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
AnnaBridge	165:d1b4690b3f8b	3541	{
AnnaBridge	165:d1b4690b3f8b	3542	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
AnnaBridge	165:d1b4690b3f8b	3543	}
AnnaBridge	165:d1b4690b3f8b	3544
AnnaBridge	165:d1b4690b3f8b	3545	/**
AnnaBridge	165:d1b4690b3f8b	3546	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	165:d1b4690b3f8b	3547	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3548	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3549	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	165:d1b4690b3f8b	3550	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	165:d1b4690b3f8b	3551	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3552	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3553	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	165:d1b4690b3f8b	3554	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	165:d1b4690b3f8b	3555	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3556	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	165:d1b4690b3f8b	3557	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	165:d1b4690b3f8b	3558	* @retval None
AnnaBridge	165:d1b4690b3f8b	3559	*/
AnnaBridge	165:d1b4690b3f8b	3560	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	165:d1b4690b3f8b	3561	{
AnnaBridge	165:d1b4690b3f8b	3562	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	165:d1b4690b3f8b	3563	}
AnnaBridge	165:d1b4690b3f8b	3564
AnnaBridge	165:d1b4690b3f8b	3565	/**
AnnaBridge	165:d1b4690b3f8b	3566	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	165:d1b4690b3f8b	3567	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3568	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3569	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	165:d1b4690b3f8b	3570	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3571	* @retval None
AnnaBridge	165:d1b4690b3f8b	3572	*/
AnnaBridge	165:d1b4690b3f8b	3573	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3574	{
AnnaBridge	165:d1b4690b3f8b	3575	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	165:d1b4690b3f8b	3576	}
AnnaBridge	165:d1b4690b3f8b	3577
AnnaBridge	165:d1b4690b3f8b	3578	/**
AnnaBridge	165:d1b4690b3f8b	3579	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	165:d1b4690b3f8b	3580	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3581	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3582	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	165:d1b4690b3f8b	3583	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3584	* @retval None
AnnaBridge	165:d1b4690b3f8b	3585	*/
AnnaBridge	165:d1b4690b3f8b	3586	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3587	{
AnnaBridge	165:d1b4690b3f8b	3588	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	165:d1b4690b3f8b	3589	}
AnnaBridge	165:d1b4690b3f8b	3590
AnnaBridge	165:d1b4690b3f8b	3591	/**
AnnaBridge	165:d1b4690b3f8b	3592	* @brief Indicate whether automatic output is enabled.
AnnaBridge	165:d1b4690b3f8b	3593	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3594	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3595	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	165:d1b4690b3f8b	3596	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3597	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3598	*/
AnnaBridge	165:d1b4690b3f8b	3599	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3600	{
AnnaBridge	165:d1b4690b3f8b	3601	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	165:d1b4690b3f8b	3602	}
AnnaBridge	165:d1b4690b3f8b	3603
AnnaBridge	165:d1b4690b3f8b	3604	/**
AnnaBridge	165:d1b4690b3f8b	3605	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	165:d1b4690b3f8b	3606	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	165:d1b4690b3f8b	3607	* software and is reset in case of break or break2 event
AnnaBridge	165:d1b4690b3f8b	3608	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3609	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3610	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	165:d1b4690b3f8b	3611	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3612	* @retval None
AnnaBridge	165:d1b4690b3f8b	3613	*/
AnnaBridge	165:d1b4690b3f8b	3614	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3615	{
AnnaBridge	165:d1b4690b3f8b	3616	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	165:d1b4690b3f8b	3617	}
AnnaBridge	165:d1b4690b3f8b	3618
AnnaBridge	165:d1b4690b3f8b	3619	/**
AnnaBridge	165:d1b4690b3f8b	3620	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	165:d1b4690b3f8b	3621	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	165:d1b4690b3f8b	3622	* software and is reset in case of break or break2 event.
AnnaBridge	165:d1b4690b3f8b	3623	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3624	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3625	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	165:d1b4690b3f8b	3626	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3627	* @retval None
AnnaBridge	165:d1b4690b3f8b	3628	*/
AnnaBridge	165:d1b4690b3f8b	3629	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3630	{
AnnaBridge	165:d1b4690b3f8b	3631	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	165:d1b4690b3f8b	3632	}
AnnaBridge	165:d1b4690b3f8b	3633
AnnaBridge	165:d1b4690b3f8b	3634	/**
AnnaBridge	165:d1b4690b3f8b	3635	* @brief Indicates whether outputs are enabled.
AnnaBridge	165:d1b4690b3f8b	3636	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3637	* a timer instance provides a break input.
AnnaBridge	165:d1b4690b3f8b	3638	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	165:d1b4690b3f8b	3639	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3640	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3641	*/
AnnaBridge	165:d1b4690b3f8b	3642	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	3643	{
AnnaBridge	165:d1b4690b3f8b	3644	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	165:d1b4690b3f8b	3645	}
AnnaBridge	165:d1b4690b3f8b	3646
AnnaBridge	165:d1b4690b3f8b	3647	/**
AnnaBridge	165:d1b4690b3f8b	3648	* @brief Enable the signals connected to the designated timer break input.
AnnaBridge	165:d1b4690b3f8b	3649	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	3650	* or not a timer instance allows for break input selection.
AnnaBridge	165:d1b4690b3f8b	3651	* @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3652	* OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3653	* OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3654	* OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3655	* OR3 BK2INE LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3656	* OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3657	* OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3658	* OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
AnnaBridge	165:d1b4690b3f8b	3659	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3660	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3661	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	165:d1b4690b3f8b	3662	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	165:d1b4690b3f8b	3663	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3664	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	165:d1b4690b3f8b	3665	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	165:d1b4690b3f8b	3666	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	165:d1b4690b3f8b	3667	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	165:d1b4690b3f8b	3668	* @retval None
AnnaBridge	165:d1b4690b3f8b	3669	*/
AnnaBridge	165:d1b4690b3f8b	3670	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3671	{
AnnaBridge	165:d1b4690b3f8b	3672	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	165:d1b4690b3f8b	3673	SET_BIT(*pReg , Source);
AnnaBridge	165:d1b4690b3f8b	3674	}
AnnaBridge	165:d1b4690b3f8b	3675
AnnaBridge	165:d1b4690b3f8b	3676	/**
AnnaBridge	165:d1b4690b3f8b	3677	* @brief Disable the signals connected to the designated timer break input.
AnnaBridge	165:d1b4690b3f8b	3678	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	3679	* or not a timer instance allows for break input selection.
AnnaBridge	165:d1b4690b3f8b	3680	* @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3681	* OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3682	* OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3683	* OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3684	* OR3 BK2INE LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3685	* OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3686	* OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	165:d1b4690b3f8b	3687	* OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
AnnaBridge	165:d1b4690b3f8b	3688	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3689	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3690	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	165:d1b4690b3f8b	3691	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	165:d1b4690b3f8b	3692	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3693	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	165:d1b4690b3f8b	3694	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	165:d1b4690b3f8b	3695	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	165:d1b4690b3f8b	3696	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	165:d1b4690b3f8b	3697	* @retval None
AnnaBridge	165:d1b4690b3f8b	3698	*/
AnnaBridge	165:d1b4690b3f8b	3699	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3700	{
AnnaBridge	165:d1b4690b3f8b	3701	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	165:d1b4690b3f8b	3702	CLEAR_BIT(*pReg, Source);
AnnaBridge	165:d1b4690b3f8b	3703	}
AnnaBridge	165:d1b4690b3f8b	3704
AnnaBridge	165:d1b4690b3f8b	3705	/**
AnnaBridge	165:d1b4690b3f8b	3706	* @brief Set the polarity of the break signal for the timer break input.
AnnaBridge	165:d1b4690b3f8b	3707	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:d1b4690b3f8b	3708	* or not a timer instance allows for break input selection.
AnnaBridge	165:d1b4690b3f8b	3709	* @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	165:d1b4690b3f8b	3710	* OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	165:d1b4690b3f8b	3711	* OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	165:d1b4690b3f8b	3712	* OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	165:d1b4690b3f8b	3713	* OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	165:d1b4690b3f8b	3714	* OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
AnnaBridge	165:d1b4690b3f8b	3715	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3716	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3717	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	165:d1b4690b3f8b	3718	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	165:d1b4690b3f8b	3719	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3720	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	165:d1b4690b3f8b	3721	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	165:d1b4690b3f8b	3722	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	165:d1b4690b3f8b	3723	* @param Polarity This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3724	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
AnnaBridge	165:d1b4690b3f8b	3725	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
AnnaBridge	165:d1b4690b3f8b	3726	* @retval None
AnnaBridge	165:d1b4690b3f8b	3727	*/
AnnaBridge	165:d1b4690b3f8b	3728	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
AnnaBridge	165:d1b4690b3f8b	3729	uint32_t Polarity)
AnnaBridge	165:d1b4690b3f8b	3730	{
AnnaBridge	165:d1b4690b3f8b	3731	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	165:d1b4690b3f8b	3732	MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
AnnaBridge	165:d1b4690b3f8b	3733	}
AnnaBridge	165:d1b4690b3f8b	3734	/**
AnnaBridge	165:d1b4690b3f8b	3735	* @}
AnnaBridge	165:d1b4690b3f8b	3736	*/
AnnaBridge	165:d1b4690b3f8b	3737
AnnaBridge	165:d1b4690b3f8b	3738	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	165:d1b4690b3f8b	3739	* @{
AnnaBridge	165:d1b4690b3f8b	3740	*/
AnnaBridge	165:d1b4690b3f8b	3741	/**
AnnaBridge	165:d1b4690b3f8b	3742	* @brief Configures the timer DMA burst feature.
AnnaBridge	165:d1b4690b3f8b	3743	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	165:d1b4690b3f8b	3744	* not a timer instance supports the DMA burst mode.
AnnaBridge	165:d1b4690b3f8b	3745	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	165:d1b4690b3f8b	3746	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	165:d1b4690b3f8b	3747	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3748	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3749	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	165:d1b4690b3f8b	3750	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	165:d1b4690b3f8b	3751	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	165:d1b4690b3f8b	3752	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	165:d1b4690b3f8b	3753	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	165:d1b4690b3f8b	3754	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	165:d1b4690b3f8b	3755	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	165:d1b4690b3f8b	3756	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	165:d1b4690b3f8b	3757	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	165:d1b4690b3f8b	3758	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	165:d1b4690b3f8b	3759	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	165:d1b4690b3f8b	3760	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	165:d1b4690b3f8b	3761	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	165:d1b4690b3f8b	3762	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	165:d1b4690b3f8b	3763	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	165:d1b4690b3f8b	3764	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	165:d1b4690b3f8b	3765	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	165:d1b4690b3f8b	3766	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	165:d1b4690b3f8b	3767	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
AnnaBridge	165:d1b4690b3f8b	3768	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
AnnaBridge	165:d1b4690b3f8b	3769	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
AnnaBridge	165:d1b4690b3f8b	3770	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
AnnaBridge	165:d1b4690b3f8b	3771	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
AnnaBridge	165:d1b4690b3f8b	3772	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
AnnaBridge	165:d1b4690b3f8b	3773	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3774	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	165:d1b4690b3f8b	3775	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3776	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3777	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3778	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3779	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3780	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3781	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3782	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3783	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3784	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3785	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3786	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3787	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3788	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3789	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3790	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3791	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	165:d1b4690b3f8b	3792	* @retval None
AnnaBridge	165:d1b4690b3f8b	3793	*/
AnnaBridge	165:d1b4690b3f8b	3794	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	165:d1b4690b3f8b	3795	{
AnnaBridge	165:d1b4690b3f8b	3796	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	165:d1b4690b3f8b	3797	}
AnnaBridge	165:d1b4690b3f8b	3798
AnnaBridge	165:d1b4690b3f8b	3799	/**
AnnaBridge	165:d1b4690b3f8b	3800	* @}
AnnaBridge	165:d1b4690b3f8b	3801	*/
AnnaBridge	165:d1b4690b3f8b	3802
AnnaBridge	165:d1b4690b3f8b	3803	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	165:d1b4690b3f8b	3804	* @{
AnnaBridge	165:d1b4690b3f8b	3805	*/
AnnaBridge	165:d1b4690b3f8b	3806	/**
AnnaBridge	165:d1b4690b3f8b	3807	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	165:d1b4690b3f8b	3808	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:d1b4690b3f8b	3809	* a some timer inputs can be remapped.
AnnaBridge	165:d1b4690b3f8b	3810	@if STM32L486xx
AnnaBridge	165:d1b4690b3f8b	3811	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3812	* TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3813	* TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3814	* TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3815	* TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3816	* TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3817	* TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3818	* TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3819	* TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3820	* TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3821	* TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3822	* TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3823	* TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3824	* TIM17_OR1 TI1_RMP LL_TIM_SetRemap
AnnaBridge	165:d1b4690b3f8b	3825	@endif
AnnaBridge	165:d1b4690b3f8b	3826	@if STM32L443xx
AnnaBridge	165:d1b4690b3f8b	3827	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3828	* TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3829	* TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3830	* TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3831	* TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3832	* TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3833	* TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3834	* TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3835	* TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	165:d1b4690b3f8b	3836	@endif
AnnaBridge	165:d1b4690b3f8b	3837	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	3838	* @param Remap Remap param depends on the TIMx. Description available only
AnnaBridge	165:d1b4690b3f8b	3839	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	165:d1b4690b3f8b	3840	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	165:d1b4690b3f8b	3841	*
AnnaBridge	165:d1b4690b3f8b	3842	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	165:d1b4690b3f8b	3843	*
AnnaBridge	165:d1b4690b3f8b	3844	@if STM32L486xx
AnnaBridge	165:d1b4690b3f8b	3845	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	165:d1b4690b3f8b	3846	*
AnnaBridge	165:d1b4690b3f8b	3847	* . . ADC1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3848	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
AnnaBridge	165:d1b4690b3f8b	3849	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
AnnaBridge	165:d1b4690b3f8b	3850	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
AnnaBridge	165:d1b4690b3f8b	3851	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
AnnaBridge	165:d1b4690b3f8b	3852	*
AnnaBridge	165:d1b4690b3f8b	3853	* . . ADC3_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3854	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
AnnaBridge	165:d1b4690b3f8b	3855	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
AnnaBridge	165:d1b4690b3f8b	3856	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
AnnaBridge	165:d1b4690b3f8b	3857	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
AnnaBridge	165:d1b4690b3f8b	3858	*
AnnaBridge	165:d1b4690b3f8b	3859	* . . TI1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3860	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3861	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
AnnaBridge	165:d1b4690b3f8b	3862	*
AnnaBridge	165:d1b4690b3f8b	3863	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
AnnaBridge	165:d1b4690b3f8b	3864	*
AnnaBridge	165:d1b4690b3f8b	3865	* ITR1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3866	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
AnnaBridge	165:d1b4690b3f8b	3867	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
AnnaBridge	165:d1b4690b3f8b	3868	*
AnnaBridge	165:d1b4690b3f8b	3869	* . . ETR1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3870	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3871	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3872	*
AnnaBridge	165:d1b4690b3f8b	3873	* . . TI4_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3874	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3875	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
AnnaBridge	165:d1b4690b3f8b	3876	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
AnnaBridge	165:d1b4690b3f8b	3877	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
AnnaBridge	165:d1b4690b3f8b	3878	*
AnnaBridge	165:d1b4690b3f8b	3879	* TIM3: one of the following values
AnnaBridge	165:d1b4690b3f8b	3880	*
AnnaBridge	165:d1b4690b3f8b	3881	* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3882	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
AnnaBridge	165:d1b4690b3f8b	3883	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
AnnaBridge	165:d1b4690b3f8b	3884	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
AnnaBridge	165:d1b4690b3f8b	3885	*
AnnaBridge	165:d1b4690b3f8b	3886	* TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	165:d1b4690b3f8b	3887	*
AnnaBridge	165:d1b4690b3f8b	3888	* . . ADC1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3889	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
AnnaBridge	165:d1b4690b3f8b	3890	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
AnnaBridge	165:d1b4690b3f8b	3891	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
AnnaBridge	165:d1b4690b3f8b	3892	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
AnnaBridge	165:d1b4690b3f8b	3893	*
AnnaBridge	165:d1b4690b3f8b	3894	* . . ADC3_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3895	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
AnnaBridge	165:d1b4690b3f8b	3896	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
AnnaBridge	165:d1b4690b3f8b	3897	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
AnnaBridge	165:d1b4690b3f8b	3898	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
AnnaBridge	165:d1b4690b3f8b	3899	*
AnnaBridge	165:d1b4690b3f8b	3900	* . . TI1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3901	* @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3902	* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
AnnaBridge	165:d1b4690b3f8b	3903	*
AnnaBridge	165:d1b4690b3f8b	3904	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
AnnaBridge	165:d1b4690b3f8b	3905	*
AnnaBridge	165:d1b4690b3f8b	3906	* . . TI1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3907	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3908	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3909	*
AnnaBridge	165:d1b4690b3f8b	3910	* . . ENCODER_MODE can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3911	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
AnnaBridge	165:d1b4690b3f8b	3912	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
AnnaBridge	165:d1b4690b3f8b	3913	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
AnnaBridge	165:d1b4690b3f8b	3914	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
AnnaBridge	165:d1b4690b3f8b	3915	*
AnnaBridge	165:d1b4690b3f8b	3916	* TIM16: one of the following values
AnnaBridge	165:d1b4690b3f8b	3917	*
AnnaBridge	165:d1b4690b3f8b	3918	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3919	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
AnnaBridge	165:d1b4690b3f8b	3920	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3921	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
AnnaBridge	165:d1b4690b3f8b	3922	* @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
AnnaBridge	165:d1b4690b3f8b	3923	* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
AnnaBridge	165:d1b4690b3f8b	3924	* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
AnnaBridge	165:d1b4690b3f8b	3925	*
AnnaBridge	165:d1b4690b3f8b	3926	* TIM17: one of the following values
AnnaBridge	165:d1b4690b3f8b	3927	*
AnnaBridge	165:d1b4690b3f8b	3928	* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3929	* @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
AnnaBridge	165:d1b4690b3f8b	3930	* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
AnnaBridge	165:d1b4690b3f8b	3931	* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
AnnaBridge	165:d1b4690b3f8b	3932	@endif
AnnaBridge	165:d1b4690b3f8b	3933	@if STM32L443xx
AnnaBridge	165:d1b4690b3f8b	3934	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	165:d1b4690b3f8b	3935	*
AnnaBridge	165:d1b4690b3f8b	3936	* . . ADC1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3937	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
AnnaBridge	165:d1b4690b3f8b	3938	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
AnnaBridge	165:d1b4690b3f8b	3939	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
AnnaBridge	165:d1b4690b3f8b	3940	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
AnnaBridge	165:d1b4690b3f8b	3941	*
AnnaBridge	165:d1b4690b3f8b	3942	* . . TI1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3943	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3944	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
AnnaBridge	165:d1b4690b3f8b	3945	*
AnnaBridge	165:d1b4690b3f8b	3946	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
AnnaBridge	165:d1b4690b3f8b	3947	*
AnnaBridge	165:d1b4690b3f8b	3948	* ITR1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3949	* @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
AnnaBridge	165:d1b4690b3f8b	3950	* @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
AnnaBridge	165:d1b4690b3f8b	3951	*
AnnaBridge	165:d1b4690b3f8b	3952	* . . ETR1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3953	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3954	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3955	*
AnnaBridge	165:d1b4690b3f8b	3956	* . . TI4_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3957	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3958	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
AnnaBridge	165:d1b4690b3f8b	3959	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
AnnaBridge	165:d1b4690b3f8b	3960	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
AnnaBridge	165:d1b4690b3f8b	3961	*
AnnaBridge	165:d1b4690b3f8b	3962	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
AnnaBridge	165:d1b4690b3f8b	3963	*
AnnaBridge	165:d1b4690b3f8b	3964	* . . TI1_RMP can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3965	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3966	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3967	*
AnnaBridge	165:d1b4690b3f8b	3968	* . . ENCODER_MODE can be one of the following values
AnnaBridge	165:d1b4690b3f8b	3969	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
AnnaBridge	165:d1b4690b3f8b	3970	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
AnnaBridge	165:d1b4690b3f8b	3971	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
AnnaBridge	165:d1b4690b3f8b	3972	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
AnnaBridge	165:d1b4690b3f8b	3973	*
AnnaBridge	165:d1b4690b3f8b	3974	* TIM16: one of the following values
AnnaBridge	165:d1b4690b3f8b	3975	*
AnnaBridge	165:d1b4690b3f8b	3976	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
AnnaBridge	165:d1b4690b3f8b	3977	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
AnnaBridge	165:d1b4690b3f8b	3978	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
AnnaBridge	165:d1b4690b3f8b	3979	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
AnnaBridge	165:d1b4690b3f8b	3980	* @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
AnnaBridge	165:d1b4690b3f8b	3981	* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
AnnaBridge	165:d1b4690b3f8b	3982	* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
AnnaBridge	165:d1b4690b3f8b	3983	@endif
AnnaBridge	165:d1b4690b3f8b	3984	* @retval None
AnnaBridge	165:d1b4690b3f8b	3985	*/
AnnaBridge	165:d1b4690b3f8b	3986	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	165:d1b4690b3f8b	3987	{
AnnaBridge	165:d1b4690b3f8b	3988	MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
AnnaBridge	165:d1b4690b3f8b	3989	}
AnnaBridge	165:d1b4690b3f8b	3990
AnnaBridge	165:d1b4690b3f8b	3991	/**
AnnaBridge	165:d1b4690b3f8b	3992	* @}
AnnaBridge	165:d1b4690b3f8b	3993	*/
AnnaBridge	165:d1b4690b3f8b	3994
AnnaBridge	165:d1b4690b3f8b	3995	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	165:d1b4690b3f8b	3996	* @{
AnnaBridge	165:d1b4690b3f8b	3997	*/
AnnaBridge	165:d1b4690b3f8b	3998	/**
AnnaBridge	165:d1b4690b3f8b	3999	* @brief Set the OCREF clear input source
AnnaBridge	165:d1b4690b3f8b	4000	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	165:d1b4690b3f8b	4001	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	165:d1b4690b3f8b	4002	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	165:d1b4690b3f8b	4003	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4004	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4005	* @arg @ref LL_TIM_OCREF_CLR_INT_NC
AnnaBridge	165:d1b4690b3f8b	4006	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	165:d1b4690b3f8b	4007	* @retval None
AnnaBridge	165:d1b4690b3f8b	4008	*/
AnnaBridge	165:d1b4690b3f8b	4009	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	165:d1b4690b3f8b	4010	{
AnnaBridge	165:d1b4690b3f8b	4011	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	165:d1b4690b3f8b	4012	}
AnnaBridge	165:d1b4690b3f8b	4013	/**
AnnaBridge	165:d1b4690b3f8b	4014	* @}
AnnaBridge	165:d1b4690b3f8b	4015	*/
AnnaBridge	165:d1b4690b3f8b	4016
AnnaBridge	165:d1b4690b3f8b	4017	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	165:d1b4690b3f8b	4018	* @{
AnnaBridge	165:d1b4690b3f8b	4019	*/
AnnaBridge	165:d1b4690b3f8b	4020	/**
AnnaBridge	165:d1b4690b3f8b	4021	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	165:d1b4690b3f8b	4022	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	165:d1b4690b3f8b	4023	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4024	* @retval None
AnnaBridge	165:d1b4690b3f8b	4025	*/
AnnaBridge	165:d1b4690b3f8b	4026	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4027	{
AnnaBridge	165:d1b4690b3f8b	4028	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	165:d1b4690b3f8b	4029	}
AnnaBridge	165:d1b4690b3f8b	4030
AnnaBridge	165:d1b4690b3f8b	4031	/**
AnnaBridge	165:d1b4690b3f8b	4032	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4033	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	165:d1b4690b3f8b	4034	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4035	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4036	*/
AnnaBridge	165:d1b4690b3f8b	4037	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4038	{
AnnaBridge	165:d1b4690b3f8b	4039	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	165:d1b4690b3f8b	4040	}
AnnaBridge	165:d1b4690b3f8b	4041
AnnaBridge	165:d1b4690b3f8b	4042	/**
AnnaBridge	165:d1b4690b3f8b	4043	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	165:d1b4690b3f8b	4044	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	165:d1b4690b3f8b	4045	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4046	* @retval None
AnnaBridge	165:d1b4690b3f8b	4047	*/
AnnaBridge	165:d1b4690b3f8b	4048	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4049	{
AnnaBridge	165:d1b4690b3f8b	4050	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	165:d1b4690b3f8b	4051	}
AnnaBridge	165:d1b4690b3f8b	4052
AnnaBridge	165:d1b4690b3f8b	4053	/**
AnnaBridge	165:d1b4690b3f8b	4054	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4055	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	165:d1b4690b3f8b	4056	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4057	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4058	*/
AnnaBridge	165:d1b4690b3f8b	4059	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4060	{
AnnaBridge	165:d1b4690b3f8b	4061	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	165:d1b4690b3f8b	4062	}
AnnaBridge	165:d1b4690b3f8b	4063
AnnaBridge	165:d1b4690b3f8b	4064	/**
AnnaBridge	165:d1b4690b3f8b	4065	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	165:d1b4690b3f8b	4066	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	165:d1b4690b3f8b	4067	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4068	* @retval None
AnnaBridge	165:d1b4690b3f8b	4069	*/
AnnaBridge	165:d1b4690b3f8b	4070	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4071	{
AnnaBridge	165:d1b4690b3f8b	4072	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	165:d1b4690b3f8b	4073	}
AnnaBridge	165:d1b4690b3f8b	4074
AnnaBridge	165:d1b4690b3f8b	4075	/**
AnnaBridge	165:d1b4690b3f8b	4076	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4077	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	165:d1b4690b3f8b	4078	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4079	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4080	*/
AnnaBridge	165:d1b4690b3f8b	4081	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4082	{
AnnaBridge	165:d1b4690b3f8b	4083	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	165:d1b4690b3f8b	4084	}
AnnaBridge	165:d1b4690b3f8b	4085
AnnaBridge	165:d1b4690b3f8b	4086	/**
AnnaBridge	165:d1b4690b3f8b	4087	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	165:d1b4690b3f8b	4088	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	165:d1b4690b3f8b	4089	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4090	* @retval None
AnnaBridge	165:d1b4690b3f8b	4091	*/
AnnaBridge	165:d1b4690b3f8b	4092	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4093	{
AnnaBridge	165:d1b4690b3f8b	4094	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	165:d1b4690b3f8b	4095	}
AnnaBridge	165:d1b4690b3f8b	4096
AnnaBridge	165:d1b4690b3f8b	4097	/**
AnnaBridge	165:d1b4690b3f8b	4098	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4099	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	165:d1b4690b3f8b	4100	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4101	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4102	*/
AnnaBridge	165:d1b4690b3f8b	4103	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4104	{
AnnaBridge	165:d1b4690b3f8b	4105	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	165:d1b4690b3f8b	4106	}
AnnaBridge	165:d1b4690b3f8b	4107
AnnaBridge	165:d1b4690b3f8b	4108	/**
AnnaBridge	165:d1b4690b3f8b	4109	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	165:d1b4690b3f8b	4110	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	165:d1b4690b3f8b	4111	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4112	* @retval None
AnnaBridge	165:d1b4690b3f8b	4113	*/
AnnaBridge	165:d1b4690b3f8b	4114	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4115	{
AnnaBridge	165:d1b4690b3f8b	4116	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	165:d1b4690b3f8b	4117	}
AnnaBridge	165:d1b4690b3f8b	4118
AnnaBridge	165:d1b4690b3f8b	4119	/**
AnnaBridge	165:d1b4690b3f8b	4120	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4121	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	165:d1b4690b3f8b	4122	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4123	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4124	*/
AnnaBridge	165:d1b4690b3f8b	4125	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4126	{
AnnaBridge	165:d1b4690b3f8b	4127	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	165:d1b4690b3f8b	4128	}
AnnaBridge	165:d1b4690b3f8b	4129
AnnaBridge	165:d1b4690b3f8b	4130	/**
AnnaBridge	165:d1b4690b3f8b	4131	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
AnnaBridge	165:d1b4690b3f8b	4132	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
AnnaBridge	165:d1b4690b3f8b	4133	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4134	* @retval None
AnnaBridge	165:d1b4690b3f8b	4135	*/
AnnaBridge	165:d1b4690b3f8b	4136	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4137	{
AnnaBridge	165:d1b4690b3f8b	4138	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
AnnaBridge	165:d1b4690b3f8b	4139	}
AnnaBridge	165:d1b4690b3f8b	4140
AnnaBridge	165:d1b4690b3f8b	4141	/**
AnnaBridge	165:d1b4690b3f8b	4142	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4143	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
AnnaBridge	165:d1b4690b3f8b	4144	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4145	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4146	*/
AnnaBridge	165:d1b4690b3f8b	4147	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4148	{
AnnaBridge	165:d1b4690b3f8b	4149	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
AnnaBridge	165:d1b4690b3f8b	4150	}
AnnaBridge	165:d1b4690b3f8b	4151
AnnaBridge	165:d1b4690b3f8b	4152	/**
AnnaBridge	165:d1b4690b3f8b	4153	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
AnnaBridge	165:d1b4690b3f8b	4154	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
AnnaBridge	165:d1b4690b3f8b	4155	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4156	* @retval None
AnnaBridge	165:d1b4690b3f8b	4157	*/
AnnaBridge	165:d1b4690b3f8b	4158	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4159	{
AnnaBridge	165:d1b4690b3f8b	4160	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
AnnaBridge	165:d1b4690b3f8b	4161	}
AnnaBridge	165:d1b4690b3f8b	4162
AnnaBridge	165:d1b4690b3f8b	4163	/**
AnnaBridge	165:d1b4690b3f8b	4164	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4165	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
AnnaBridge	165:d1b4690b3f8b	4166	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4167	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4168	*/
AnnaBridge	165:d1b4690b3f8b	4169	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4170	{
AnnaBridge	165:d1b4690b3f8b	4171	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
AnnaBridge	165:d1b4690b3f8b	4172	}
AnnaBridge	165:d1b4690b3f8b	4173
AnnaBridge	165:d1b4690b3f8b	4174	/**
AnnaBridge	165:d1b4690b3f8b	4175	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	165:d1b4690b3f8b	4176	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	165:d1b4690b3f8b	4177	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4178	* @retval None
AnnaBridge	165:d1b4690b3f8b	4179	*/
AnnaBridge	165:d1b4690b3f8b	4180	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4181	{
AnnaBridge	165:d1b4690b3f8b	4182	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	165:d1b4690b3f8b	4183	}
AnnaBridge	165:d1b4690b3f8b	4184
AnnaBridge	165:d1b4690b3f8b	4185	/**
AnnaBridge	165:d1b4690b3f8b	4186	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4187	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	165:d1b4690b3f8b	4188	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4189	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4190	*/
AnnaBridge	165:d1b4690b3f8b	4191	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4192	{
AnnaBridge	165:d1b4690b3f8b	4193	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	165:d1b4690b3f8b	4194	}
AnnaBridge	165:d1b4690b3f8b	4195
AnnaBridge	165:d1b4690b3f8b	4196	/**
AnnaBridge	165:d1b4690b3f8b	4197	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	165:d1b4690b3f8b	4198	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	165:d1b4690b3f8b	4199	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4200	* @retval None
AnnaBridge	165:d1b4690b3f8b	4201	*/
AnnaBridge	165:d1b4690b3f8b	4202	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4203	{
AnnaBridge	165:d1b4690b3f8b	4204	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	165:d1b4690b3f8b	4205	}
AnnaBridge	165:d1b4690b3f8b	4206
AnnaBridge	165:d1b4690b3f8b	4207	/**
AnnaBridge	165:d1b4690b3f8b	4208	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4209	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	165:d1b4690b3f8b	4210	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4211	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4212	*/
AnnaBridge	165:d1b4690b3f8b	4213	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4214	{
AnnaBridge	165:d1b4690b3f8b	4215	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	165:d1b4690b3f8b	4216	}
AnnaBridge	165:d1b4690b3f8b	4217
AnnaBridge	165:d1b4690b3f8b	4218	/**
AnnaBridge	165:d1b4690b3f8b	4219	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	165:d1b4690b3f8b	4220	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	165:d1b4690b3f8b	4221	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4222	* @retval None
AnnaBridge	165:d1b4690b3f8b	4223	*/
AnnaBridge	165:d1b4690b3f8b	4224	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4225	{
AnnaBridge	165:d1b4690b3f8b	4226	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	165:d1b4690b3f8b	4227	}
AnnaBridge	165:d1b4690b3f8b	4228
AnnaBridge	165:d1b4690b3f8b	4229	/**
AnnaBridge	165:d1b4690b3f8b	4230	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4231	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	165:d1b4690b3f8b	4232	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4233	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4234	*/
AnnaBridge	165:d1b4690b3f8b	4235	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4236	{
AnnaBridge	165:d1b4690b3f8b	4237	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	165:d1b4690b3f8b	4238	}
AnnaBridge	165:d1b4690b3f8b	4239
AnnaBridge	165:d1b4690b3f8b	4240	/**
AnnaBridge	165:d1b4690b3f8b	4241	* @brief Clear the break 2 interrupt flag (B2IF).
AnnaBridge	165:d1b4690b3f8b	4242	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
AnnaBridge	165:d1b4690b3f8b	4243	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4244	* @retval None
AnnaBridge	165:d1b4690b3f8b	4245	*/
AnnaBridge	165:d1b4690b3f8b	4246	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4247	{
AnnaBridge	165:d1b4690b3f8b	4248	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
AnnaBridge	165:d1b4690b3f8b	4249	}
AnnaBridge	165:d1b4690b3f8b	4250
AnnaBridge	165:d1b4690b3f8b	4251	/**
AnnaBridge	165:d1b4690b3f8b	4252	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4253	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
AnnaBridge	165:d1b4690b3f8b	4254	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4255	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4256	*/
AnnaBridge	165:d1b4690b3f8b	4257	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4258	{
AnnaBridge	165:d1b4690b3f8b	4259	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
AnnaBridge	165:d1b4690b3f8b	4260	}
AnnaBridge	165:d1b4690b3f8b	4261
AnnaBridge	165:d1b4690b3f8b	4262	/**
AnnaBridge	165:d1b4690b3f8b	4263	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	165:d1b4690b3f8b	4264	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	165:d1b4690b3f8b	4265	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4266	* @retval None
AnnaBridge	165:d1b4690b3f8b	4267	*/
AnnaBridge	165:d1b4690b3f8b	4268	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4269	{
AnnaBridge	165:d1b4690b3f8b	4270	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	165:d1b4690b3f8b	4271	}
AnnaBridge	165:d1b4690b3f8b	4272
AnnaBridge	165:d1b4690b3f8b	4273	/**
AnnaBridge	165:d1b4690b3f8b	4274	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4275	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	165:d1b4690b3f8b	4276	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4277	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4278	*/
AnnaBridge	165:d1b4690b3f8b	4279	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4280	{
AnnaBridge	165:d1b4690b3f8b	4281	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	165:d1b4690b3f8b	4282	}
AnnaBridge	165:d1b4690b3f8b	4283
AnnaBridge	165:d1b4690b3f8b	4284	/**
AnnaBridge	165:d1b4690b3f8b	4285	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	165:d1b4690b3f8b	4286	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	165:d1b4690b3f8b	4287	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4288	* @retval None
AnnaBridge	165:d1b4690b3f8b	4289	*/
AnnaBridge	165:d1b4690b3f8b	4290	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4291	{
AnnaBridge	165:d1b4690b3f8b	4292	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	165:d1b4690b3f8b	4293	}
AnnaBridge	165:d1b4690b3f8b	4294
AnnaBridge	165:d1b4690b3f8b	4295	/**
AnnaBridge	165:d1b4690b3f8b	4296	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4297	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	165:d1b4690b3f8b	4298	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4299	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4300	*/
AnnaBridge	165:d1b4690b3f8b	4301	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4302	{
AnnaBridge	165:d1b4690b3f8b	4303	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	165:d1b4690b3f8b	4304	}
AnnaBridge	165:d1b4690b3f8b	4305
AnnaBridge	165:d1b4690b3f8b	4306	/**
AnnaBridge	165:d1b4690b3f8b	4307	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	165:d1b4690b3f8b	4308	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	165:d1b4690b3f8b	4309	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4310	* @retval None
AnnaBridge	165:d1b4690b3f8b	4311	*/
AnnaBridge	165:d1b4690b3f8b	4312	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4313	{
AnnaBridge	165:d1b4690b3f8b	4314	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	165:d1b4690b3f8b	4315	}
AnnaBridge	165:d1b4690b3f8b	4316
AnnaBridge	165:d1b4690b3f8b	4317	/**
AnnaBridge	165:d1b4690b3f8b	4318	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4319	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	165:d1b4690b3f8b	4320	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4321	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4322	*/
AnnaBridge	165:d1b4690b3f8b	4323	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4324	{
AnnaBridge	165:d1b4690b3f8b	4325	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	165:d1b4690b3f8b	4326	}
AnnaBridge	165:d1b4690b3f8b	4327
AnnaBridge	165:d1b4690b3f8b	4328	/**
AnnaBridge	165:d1b4690b3f8b	4329	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	165:d1b4690b3f8b	4330	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	165:d1b4690b3f8b	4331	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4332	* @retval None
AnnaBridge	165:d1b4690b3f8b	4333	*/
AnnaBridge	165:d1b4690b3f8b	4334	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4335	{
AnnaBridge	165:d1b4690b3f8b	4336	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	165:d1b4690b3f8b	4337	}
AnnaBridge	165:d1b4690b3f8b	4338
AnnaBridge	165:d1b4690b3f8b	4339	/**
AnnaBridge	165:d1b4690b3f8b	4340	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4341	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	165:d1b4690b3f8b	4342	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4343	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4344	*/
AnnaBridge	165:d1b4690b3f8b	4345	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4346	{
AnnaBridge	165:d1b4690b3f8b	4347	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	165:d1b4690b3f8b	4348	}
AnnaBridge	165:d1b4690b3f8b	4349
AnnaBridge	165:d1b4690b3f8b	4350	/**
AnnaBridge	165:d1b4690b3f8b	4351	* @brief Clear the system break interrupt flag (SBIF).
AnnaBridge	165:d1b4690b3f8b	4352	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
AnnaBridge	165:d1b4690b3f8b	4353	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4354	* @retval None
AnnaBridge	165:d1b4690b3f8b	4355	*/
AnnaBridge	165:d1b4690b3f8b	4356	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4357	{
AnnaBridge	165:d1b4690b3f8b	4358	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
AnnaBridge	165:d1b4690b3f8b	4359	}
AnnaBridge	165:d1b4690b3f8b	4360
AnnaBridge	165:d1b4690b3f8b	4361	/**
AnnaBridge	165:d1b4690b3f8b	4362	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
AnnaBridge	165:d1b4690b3f8b	4363	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
AnnaBridge	165:d1b4690b3f8b	4364	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4365	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4366	*/
AnnaBridge	165:d1b4690b3f8b	4367	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4368	{
AnnaBridge	165:d1b4690b3f8b	4369	return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
AnnaBridge	165:d1b4690b3f8b	4370	}
AnnaBridge	165:d1b4690b3f8b	4371
AnnaBridge	165:d1b4690b3f8b	4372	/**
AnnaBridge	165:d1b4690b3f8b	4373	* @}
AnnaBridge	165:d1b4690b3f8b	4374	*/
AnnaBridge	165:d1b4690b3f8b	4375
AnnaBridge	165:d1b4690b3f8b	4376	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	165:d1b4690b3f8b	4377	* @{
AnnaBridge	165:d1b4690b3f8b	4378	*/
AnnaBridge	165:d1b4690b3f8b	4379	/**
AnnaBridge	165:d1b4690b3f8b	4380	* @brief Enable update interrupt (UIE).
AnnaBridge	165:d1b4690b3f8b	4381	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	165:d1b4690b3f8b	4382	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4383	* @retval None
AnnaBridge	165:d1b4690b3f8b	4384	*/
AnnaBridge	165:d1b4690b3f8b	4385	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4386	{
AnnaBridge	165:d1b4690b3f8b	4387	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	165:d1b4690b3f8b	4388	}
AnnaBridge	165:d1b4690b3f8b	4389
AnnaBridge	165:d1b4690b3f8b	4390	/**
AnnaBridge	165:d1b4690b3f8b	4391	* @brief Disable update interrupt (UIE).
AnnaBridge	165:d1b4690b3f8b	4392	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	165:d1b4690b3f8b	4393	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4394	* @retval None
AnnaBridge	165:d1b4690b3f8b	4395	*/
AnnaBridge	165:d1b4690b3f8b	4396	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4397	{
AnnaBridge	165:d1b4690b3f8b	4398	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	165:d1b4690b3f8b	4399	}
AnnaBridge	165:d1b4690b3f8b	4400
AnnaBridge	165:d1b4690b3f8b	4401	/**
AnnaBridge	165:d1b4690b3f8b	4402	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4403	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	165:d1b4690b3f8b	4404	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4405	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4406	*/
AnnaBridge	165:d1b4690b3f8b	4407	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4408	{
AnnaBridge	165:d1b4690b3f8b	4409	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	165:d1b4690b3f8b	4410	}
AnnaBridge	165:d1b4690b3f8b	4411
AnnaBridge	165:d1b4690b3f8b	4412	/**
AnnaBridge	165:d1b4690b3f8b	4413	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	165:d1b4690b3f8b	4414	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	165:d1b4690b3f8b	4415	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4416	* @retval None
AnnaBridge	165:d1b4690b3f8b	4417	*/
AnnaBridge	165:d1b4690b3f8b	4418	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4419	{
AnnaBridge	165:d1b4690b3f8b	4420	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	165:d1b4690b3f8b	4421	}
AnnaBridge	165:d1b4690b3f8b	4422
AnnaBridge	165:d1b4690b3f8b	4423	/**
AnnaBridge	165:d1b4690b3f8b	4424	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	165:d1b4690b3f8b	4425	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	165:d1b4690b3f8b	4426	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4427	* @retval None
AnnaBridge	165:d1b4690b3f8b	4428	*/
AnnaBridge	165:d1b4690b3f8b	4429	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4430	{
AnnaBridge	165:d1b4690b3f8b	4431	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	165:d1b4690b3f8b	4432	}
AnnaBridge	165:d1b4690b3f8b	4433
AnnaBridge	165:d1b4690b3f8b	4434	/**
AnnaBridge	165:d1b4690b3f8b	4435	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4436	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	165:d1b4690b3f8b	4437	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4438	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4439	*/
AnnaBridge	165:d1b4690b3f8b	4440	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4441	{
AnnaBridge	165:d1b4690b3f8b	4442	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	165:d1b4690b3f8b	4443	}
AnnaBridge	165:d1b4690b3f8b	4444
AnnaBridge	165:d1b4690b3f8b	4445	/**
AnnaBridge	165:d1b4690b3f8b	4446	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	165:d1b4690b3f8b	4447	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	165:d1b4690b3f8b	4448	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4449	* @retval None
AnnaBridge	165:d1b4690b3f8b	4450	*/
AnnaBridge	165:d1b4690b3f8b	4451	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4452	{
AnnaBridge	165:d1b4690b3f8b	4453	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	165:d1b4690b3f8b	4454	}
AnnaBridge	165:d1b4690b3f8b	4455
AnnaBridge	165:d1b4690b3f8b	4456	/**
AnnaBridge	165:d1b4690b3f8b	4457	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	165:d1b4690b3f8b	4458	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	165:d1b4690b3f8b	4459	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4460	* @retval None
AnnaBridge	165:d1b4690b3f8b	4461	*/
AnnaBridge	165:d1b4690b3f8b	4462	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4463	{
AnnaBridge	165:d1b4690b3f8b	4464	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	165:d1b4690b3f8b	4465	}
AnnaBridge	165:d1b4690b3f8b	4466
AnnaBridge	165:d1b4690b3f8b	4467	/**
AnnaBridge	165:d1b4690b3f8b	4468	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4469	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	165:d1b4690b3f8b	4470	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4471	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4472	*/
AnnaBridge	165:d1b4690b3f8b	4473	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4474	{
AnnaBridge	165:d1b4690b3f8b	4475	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	165:d1b4690b3f8b	4476	}
AnnaBridge	165:d1b4690b3f8b	4477
AnnaBridge	165:d1b4690b3f8b	4478	/**
AnnaBridge	165:d1b4690b3f8b	4479	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	165:d1b4690b3f8b	4480	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	165:d1b4690b3f8b	4481	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4482	* @retval None
AnnaBridge	165:d1b4690b3f8b	4483	*/
AnnaBridge	165:d1b4690b3f8b	4484	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4485	{
AnnaBridge	165:d1b4690b3f8b	4486	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	165:d1b4690b3f8b	4487	}
AnnaBridge	165:d1b4690b3f8b	4488
AnnaBridge	165:d1b4690b3f8b	4489	/**
AnnaBridge	165:d1b4690b3f8b	4490	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	165:d1b4690b3f8b	4491	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	165:d1b4690b3f8b	4492	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4493	* @retval None
AnnaBridge	165:d1b4690b3f8b	4494	*/
AnnaBridge	165:d1b4690b3f8b	4495	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4496	{
AnnaBridge	165:d1b4690b3f8b	4497	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	165:d1b4690b3f8b	4498	}
AnnaBridge	165:d1b4690b3f8b	4499
AnnaBridge	165:d1b4690b3f8b	4500	/**
AnnaBridge	165:d1b4690b3f8b	4501	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4502	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	165:d1b4690b3f8b	4503	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4504	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4505	*/
AnnaBridge	165:d1b4690b3f8b	4506	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4507	{
AnnaBridge	165:d1b4690b3f8b	4508	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	165:d1b4690b3f8b	4509	}
AnnaBridge	165:d1b4690b3f8b	4510
AnnaBridge	165:d1b4690b3f8b	4511	/**
AnnaBridge	165:d1b4690b3f8b	4512	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	165:d1b4690b3f8b	4513	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	165:d1b4690b3f8b	4514	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4515	* @retval None
AnnaBridge	165:d1b4690b3f8b	4516	*/
AnnaBridge	165:d1b4690b3f8b	4517	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4518	{
AnnaBridge	165:d1b4690b3f8b	4519	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	165:d1b4690b3f8b	4520	}
AnnaBridge	165:d1b4690b3f8b	4521
AnnaBridge	165:d1b4690b3f8b	4522	/**
AnnaBridge	165:d1b4690b3f8b	4523	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	165:d1b4690b3f8b	4524	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	165:d1b4690b3f8b	4525	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4526	* @retval None
AnnaBridge	165:d1b4690b3f8b	4527	*/
AnnaBridge	165:d1b4690b3f8b	4528	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4529	{
AnnaBridge	165:d1b4690b3f8b	4530	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	165:d1b4690b3f8b	4531	}
AnnaBridge	165:d1b4690b3f8b	4532
AnnaBridge	165:d1b4690b3f8b	4533	/**
AnnaBridge	165:d1b4690b3f8b	4534	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4535	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	165:d1b4690b3f8b	4536	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4537	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4538	*/
AnnaBridge	165:d1b4690b3f8b	4539	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4540	{
AnnaBridge	165:d1b4690b3f8b	4541	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	165:d1b4690b3f8b	4542	}
AnnaBridge	165:d1b4690b3f8b	4543
AnnaBridge	165:d1b4690b3f8b	4544	/**
AnnaBridge	165:d1b4690b3f8b	4545	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	165:d1b4690b3f8b	4546	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	165:d1b4690b3f8b	4547	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4548	* @retval None
AnnaBridge	165:d1b4690b3f8b	4549	*/
AnnaBridge	165:d1b4690b3f8b	4550	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4551	{
AnnaBridge	165:d1b4690b3f8b	4552	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	165:d1b4690b3f8b	4553	}
AnnaBridge	165:d1b4690b3f8b	4554
AnnaBridge	165:d1b4690b3f8b	4555	/**
AnnaBridge	165:d1b4690b3f8b	4556	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	165:d1b4690b3f8b	4557	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	165:d1b4690b3f8b	4558	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4559	* @retval None
AnnaBridge	165:d1b4690b3f8b	4560	*/
AnnaBridge	165:d1b4690b3f8b	4561	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4562	{
AnnaBridge	165:d1b4690b3f8b	4563	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	165:d1b4690b3f8b	4564	}
AnnaBridge	165:d1b4690b3f8b	4565
AnnaBridge	165:d1b4690b3f8b	4566	/**
AnnaBridge	165:d1b4690b3f8b	4567	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4568	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	165:d1b4690b3f8b	4569	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4570	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4571	*/
AnnaBridge	165:d1b4690b3f8b	4572	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4573	{
AnnaBridge	165:d1b4690b3f8b	4574	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	165:d1b4690b3f8b	4575	}
AnnaBridge	165:d1b4690b3f8b	4576
AnnaBridge	165:d1b4690b3f8b	4577	/**
AnnaBridge	165:d1b4690b3f8b	4578	* @brief Enable trigger interrupt (TIE).
AnnaBridge	165:d1b4690b3f8b	4579	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	165:d1b4690b3f8b	4580	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4581	* @retval None
AnnaBridge	165:d1b4690b3f8b	4582	*/
AnnaBridge	165:d1b4690b3f8b	4583	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4584	{
AnnaBridge	165:d1b4690b3f8b	4585	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	165:d1b4690b3f8b	4586	}
AnnaBridge	165:d1b4690b3f8b	4587
AnnaBridge	165:d1b4690b3f8b	4588	/**
AnnaBridge	165:d1b4690b3f8b	4589	* @brief Disable trigger interrupt (TIE).
AnnaBridge	165:d1b4690b3f8b	4590	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	165:d1b4690b3f8b	4591	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4592	* @retval None
AnnaBridge	165:d1b4690b3f8b	4593	*/
AnnaBridge	165:d1b4690b3f8b	4594	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4595	{
AnnaBridge	165:d1b4690b3f8b	4596	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	165:d1b4690b3f8b	4597	}
AnnaBridge	165:d1b4690b3f8b	4598
AnnaBridge	165:d1b4690b3f8b	4599	/**
AnnaBridge	165:d1b4690b3f8b	4600	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4601	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	165:d1b4690b3f8b	4602	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4603	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4604	*/
AnnaBridge	165:d1b4690b3f8b	4605	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4606	{
AnnaBridge	165:d1b4690b3f8b	4607	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	165:d1b4690b3f8b	4608	}
AnnaBridge	165:d1b4690b3f8b	4609
AnnaBridge	165:d1b4690b3f8b	4610	/**
AnnaBridge	165:d1b4690b3f8b	4611	* @brief Enable break interrupt (BIE).
AnnaBridge	165:d1b4690b3f8b	4612	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	165:d1b4690b3f8b	4613	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4614	* @retval None
AnnaBridge	165:d1b4690b3f8b	4615	*/
AnnaBridge	165:d1b4690b3f8b	4616	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4617	{
AnnaBridge	165:d1b4690b3f8b	4618	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	165:d1b4690b3f8b	4619	}
AnnaBridge	165:d1b4690b3f8b	4620
AnnaBridge	165:d1b4690b3f8b	4621	/**
AnnaBridge	165:d1b4690b3f8b	4622	* @brief Disable break interrupt (BIE).
AnnaBridge	165:d1b4690b3f8b	4623	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	165:d1b4690b3f8b	4624	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4625	* @retval None
AnnaBridge	165:d1b4690b3f8b	4626	*/
AnnaBridge	165:d1b4690b3f8b	4627	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4628	{
AnnaBridge	165:d1b4690b3f8b	4629	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	165:d1b4690b3f8b	4630	}
AnnaBridge	165:d1b4690b3f8b	4631
AnnaBridge	165:d1b4690b3f8b	4632	/**
AnnaBridge	165:d1b4690b3f8b	4633	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4634	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	165:d1b4690b3f8b	4635	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4636	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4637	*/
AnnaBridge	165:d1b4690b3f8b	4638	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4639	{
AnnaBridge	165:d1b4690b3f8b	4640	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	165:d1b4690b3f8b	4641	}
AnnaBridge	165:d1b4690b3f8b	4642
AnnaBridge	165:d1b4690b3f8b	4643	/**
AnnaBridge	165:d1b4690b3f8b	4644	* @}
AnnaBridge	165:d1b4690b3f8b	4645	*/
AnnaBridge	165:d1b4690b3f8b	4646
AnnaBridge	165:d1b4690b3f8b	4647	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	165:d1b4690b3f8b	4648	* @{
AnnaBridge	165:d1b4690b3f8b	4649	*/
AnnaBridge	165:d1b4690b3f8b	4650	/**
AnnaBridge	165:d1b4690b3f8b	4651	* @brief Enable update DMA request (UDE).
AnnaBridge	165:d1b4690b3f8b	4652	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	165:d1b4690b3f8b	4653	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4654	* @retval None
AnnaBridge	165:d1b4690b3f8b	4655	*/
AnnaBridge	165:d1b4690b3f8b	4656	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4657	{
AnnaBridge	165:d1b4690b3f8b	4658	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	165:d1b4690b3f8b	4659	}
AnnaBridge	165:d1b4690b3f8b	4660
AnnaBridge	165:d1b4690b3f8b	4661	/**
AnnaBridge	165:d1b4690b3f8b	4662	* @brief Disable update DMA request (UDE).
AnnaBridge	165:d1b4690b3f8b	4663	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	165:d1b4690b3f8b	4664	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4665	* @retval None
AnnaBridge	165:d1b4690b3f8b	4666	*/
AnnaBridge	165:d1b4690b3f8b	4667	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4668	{
AnnaBridge	165:d1b4690b3f8b	4669	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	165:d1b4690b3f8b	4670	}
AnnaBridge	165:d1b4690b3f8b	4671
AnnaBridge	165:d1b4690b3f8b	4672	/**
AnnaBridge	165:d1b4690b3f8b	4673	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4674	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	165:d1b4690b3f8b	4675	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4676	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4677	*/
AnnaBridge	165:d1b4690b3f8b	4678	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4679	{
AnnaBridge	165:d1b4690b3f8b	4680	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	165:d1b4690b3f8b	4681	}
AnnaBridge	165:d1b4690b3f8b	4682
AnnaBridge	165:d1b4690b3f8b	4683	/**
AnnaBridge	165:d1b4690b3f8b	4684	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	165:d1b4690b3f8b	4685	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	165:d1b4690b3f8b	4686	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4687	* @retval None
AnnaBridge	165:d1b4690b3f8b	4688	*/
AnnaBridge	165:d1b4690b3f8b	4689	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4690	{
AnnaBridge	165:d1b4690b3f8b	4691	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	165:d1b4690b3f8b	4692	}
AnnaBridge	165:d1b4690b3f8b	4693
AnnaBridge	165:d1b4690b3f8b	4694	/**
AnnaBridge	165:d1b4690b3f8b	4695	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	165:d1b4690b3f8b	4696	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	165:d1b4690b3f8b	4697	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4698	* @retval None
AnnaBridge	165:d1b4690b3f8b	4699	*/
AnnaBridge	165:d1b4690b3f8b	4700	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4701	{
AnnaBridge	165:d1b4690b3f8b	4702	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	165:d1b4690b3f8b	4703	}
AnnaBridge	165:d1b4690b3f8b	4704
AnnaBridge	165:d1b4690b3f8b	4705	/**
AnnaBridge	165:d1b4690b3f8b	4706	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4707	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	165:d1b4690b3f8b	4708	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4709	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4710	*/
AnnaBridge	165:d1b4690b3f8b	4711	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4712	{
AnnaBridge	165:d1b4690b3f8b	4713	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	165:d1b4690b3f8b	4714	}
AnnaBridge	165:d1b4690b3f8b	4715
AnnaBridge	165:d1b4690b3f8b	4716	/**
AnnaBridge	165:d1b4690b3f8b	4717	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	165:d1b4690b3f8b	4718	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	165:d1b4690b3f8b	4719	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4720	* @retval None
AnnaBridge	165:d1b4690b3f8b	4721	*/
AnnaBridge	165:d1b4690b3f8b	4722	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4723	{
AnnaBridge	165:d1b4690b3f8b	4724	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	165:d1b4690b3f8b	4725	}
AnnaBridge	165:d1b4690b3f8b	4726
AnnaBridge	165:d1b4690b3f8b	4727	/**
AnnaBridge	165:d1b4690b3f8b	4728	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	165:d1b4690b3f8b	4729	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	165:d1b4690b3f8b	4730	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4731	* @retval None
AnnaBridge	165:d1b4690b3f8b	4732	*/
AnnaBridge	165:d1b4690b3f8b	4733	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4734	{
AnnaBridge	165:d1b4690b3f8b	4735	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	165:d1b4690b3f8b	4736	}
AnnaBridge	165:d1b4690b3f8b	4737
AnnaBridge	165:d1b4690b3f8b	4738	/**
AnnaBridge	165:d1b4690b3f8b	4739	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4740	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	165:d1b4690b3f8b	4741	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4742	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4743	*/
AnnaBridge	165:d1b4690b3f8b	4744	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4745	{
AnnaBridge	165:d1b4690b3f8b	4746	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	165:d1b4690b3f8b	4747	}
AnnaBridge	165:d1b4690b3f8b	4748
AnnaBridge	165:d1b4690b3f8b	4749	/**
AnnaBridge	165:d1b4690b3f8b	4750	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	165:d1b4690b3f8b	4751	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	165:d1b4690b3f8b	4752	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4753	* @retval None
AnnaBridge	165:d1b4690b3f8b	4754	*/
AnnaBridge	165:d1b4690b3f8b	4755	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4756	{
AnnaBridge	165:d1b4690b3f8b	4757	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	165:d1b4690b3f8b	4758	}
AnnaBridge	165:d1b4690b3f8b	4759
AnnaBridge	165:d1b4690b3f8b	4760	/**
AnnaBridge	165:d1b4690b3f8b	4761	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	165:d1b4690b3f8b	4762	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	165:d1b4690b3f8b	4763	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4764	* @retval None
AnnaBridge	165:d1b4690b3f8b	4765	*/
AnnaBridge	165:d1b4690b3f8b	4766	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4767	{
AnnaBridge	165:d1b4690b3f8b	4768	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	165:d1b4690b3f8b	4769	}
AnnaBridge	165:d1b4690b3f8b	4770
AnnaBridge	165:d1b4690b3f8b	4771	/**
AnnaBridge	165:d1b4690b3f8b	4772	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4773	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	165:d1b4690b3f8b	4774	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4775	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4776	*/
AnnaBridge	165:d1b4690b3f8b	4777	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4778	{
AnnaBridge	165:d1b4690b3f8b	4779	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	165:d1b4690b3f8b	4780	}
AnnaBridge	165:d1b4690b3f8b	4781
AnnaBridge	165:d1b4690b3f8b	4782	/**
AnnaBridge	165:d1b4690b3f8b	4783	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	165:d1b4690b3f8b	4784	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	165:d1b4690b3f8b	4785	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4786	* @retval None
AnnaBridge	165:d1b4690b3f8b	4787	*/
AnnaBridge	165:d1b4690b3f8b	4788	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4789	{
AnnaBridge	165:d1b4690b3f8b	4790	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	165:d1b4690b3f8b	4791	}
AnnaBridge	165:d1b4690b3f8b	4792
AnnaBridge	165:d1b4690b3f8b	4793	/**
AnnaBridge	165:d1b4690b3f8b	4794	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	165:d1b4690b3f8b	4795	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	165:d1b4690b3f8b	4796	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4797	* @retval None
AnnaBridge	165:d1b4690b3f8b	4798	*/
AnnaBridge	165:d1b4690b3f8b	4799	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4800	{
AnnaBridge	165:d1b4690b3f8b	4801	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	165:d1b4690b3f8b	4802	}
AnnaBridge	165:d1b4690b3f8b	4803
AnnaBridge	165:d1b4690b3f8b	4804	/**
AnnaBridge	165:d1b4690b3f8b	4805	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4806	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	165:d1b4690b3f8b	4807	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4808	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4809	*/
AnnaBridge	165:d1b4690b3f8b	4810	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4811	{
AnnaBridge	165:d1b4690b3f8b	4812	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	165:d1b4690b3f8b	4813	}
AnnaBridge	165:d1b4690b3f8b	4814
AnnaBridge	165:d1b4690b3f8b	4815	/**
AnnaBridge	165:d1b4690b3f8b	4816	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	165:d1b4690b3f8b	4817	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	165:d1b4690b3f8b	4818	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4819	* @retval None
AnnaBridge	165:d1b4690b3f8b	4820	*/
AnnaBridge	165:d1b4690b3f8b	4821	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4822	{
AnnaBridge	165:d1b4690b3f8b	4823	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	165:d1b4690b3f8b	4824	}
AnnaBridge	165:d1b4690b3f8b	4825
AnnaBridge	165:d1b4690b3f8b	4826	/**
AnnaBridge	165:d1b4690b3f8b	4827	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	165:d1b4690b3f8b	4828	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	165:d1b4690b3f8b	4829	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4830	* @retval None
AnnaBridge	165:d1b4690b3f8b	4831	*/
AnnaBridge	165:d1b4690b3f8b	4832	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4833	{
AnnaBridge	165:d1b4690b3f8b	4834	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	165:d1b4690b3f8b	4835	}
AnnaBridge	165:d1b4690b3f8b	4836
AnnaBridge	165:d1b4690b3f8b	4837	/**
AnnaBridge	165:d1b4690b3f8b	4838	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4839	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	165:d1b4690b3f8b	4840	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4841	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4842	*/
AnnaBridge	165:d1b4690b3f8b	4843	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4844	{
AnnaBridge	165:d1b4690b3f8b	4845	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	165:d1b4690b3f8b	4846	}
AnnaBridge	165:d1b4690b3f8b	4847
AnnaBridge	165:d1b4690b3f8b	4848	/**
AnnaBridge	165:d1b4690b3f8b	4849	* @brief Enable trigger interrupt (TDE).
AnnaBridge	165:d1b4690b3f8b	4850	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	165:d1b4690b3f8b	4851	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4852	* @retval None
AnnaBridge	165:d1b4690b3f8b	4853	*/
AnnaBridge	165:d1b4690b3f8b	4854	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4855	{
AnnaBridge	165:d1b4690b3f8b	4856	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	165:d1b4690b3f8b	4857	}
AnnaBridge	165:d1b4690b3f8b	4858
AnnaBridge	165:d1b4690b3f8b	4859	/**
AnnaBridge	165:d1b4690b3f8b	4860	* @brief Disable trigger interrupt (TDE).
AnnaBridge	165:d1b4690b3f8b	4861	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	165:d1b4690b3f8b	4862	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4863	* @retval None
AnnaBridge	165:d1b4690b3f8b	4864	*/
AnnaBridge	165:d1b4690b3f8b	4865	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4866	{
AnnaBridge	165:d1b4690b3f8b	4867	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	165:d1b4690b3f8b	4868	}
AnnaBridge	165:d1b4690b3f8b	4869
AnnaBridge	165:d1b4690b3f8b	4870	/**
AnnaBridge	165:d1b4690b3f8b	4871	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	165:d1b4690b3f8b	4872	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	165:d1b4690b3f8b	4873	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4874	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4875	*/
AnnaBridge	165:d1b4690b3f8b	4876	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4877	{
AnnaBridge	165:d1b4690b3f8b	4878	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	165:d1b4690b3f8b	4879	}
AnnaBridge	165:d1b4690b3f8b	4880
AnnaBridge	165:d1b4690b3f8b	4881	/**
AnnaBridge	165:d1b4690b3f8b	4882	* @}
AnnaBridge	165:d1b4690b3f8b	4883	*/
AnnaBridge	165:d1b4690b3f8b	4884
AnnaBridge	165:d1b4690b3f8b	4885	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	165:d1b4690b3f8b	4886	* @{
AnnaBridge	165:d1b4690b3f8b	4887	*/
AnnaBridge	165:d1b4690b3f8b	4888	/**
AnnaBridge	165:d1b4690b3f8b	4889	* @brief Generate an update event.
AnnaBridge	165:d1b4690b3f8b	4890	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	165:d1b4690b3f8b	4891	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4892	* @retval None
AnnaBridge	165:d1b4690b3f8b	4893	*/
AnnaBridge	165:d1b4690b3f8b	4894	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4895	{
AnnaBridge	165:d1b4690b3f8b	4896	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	165:d1b4690b3f8b	4897	}
AnnaBridge	165:d1b4690b3f8b	4898
AnnaBridge	165:d1b4690b3f8b	4899	/**
AnnaBridge	165:d1b4690b3f8b	4900	* @brief Generate Capture/Compare 1 event.
AnnaBridge	165:d1b4690b3f8b	4901	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	165:d1b4690b3f8b	4902	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4903	* @retval None
AnnaBridge	165:d1b4690b3f8b	4904	*/
AnnaBridge	165:d1b4690b3f8b	4905	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4906	{
AnnaBridge	165:d1b4690b3f8b	4907	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	165:d1b4690b3f8b	4908	}
AnnaBridge	165:d1b4690b3f8b	4909
AnnaBridge	165:d1b4690b3f8b	4910	/**
AnnaBridge	165:d1b4690b3f8b	4911	* @brief Generate Capture/Compare 2 event.
AnnaBridge	165:d1b4690b3f8b	4912	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	165:d1b4690b3f8b	4913	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4914	* @retval None
AnnaBridge	165:d1b4690b3f8b	4915	*/
AnnaBridge	165:d1b4690b3f8b	4916	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4917	{
AnnaBridge	165:d1b4690b3f8b	4918	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	165:d1b4690b3f8b	4919	}
AnnaBridge	165:d1b4690b3f8b	4920
AnnaBridge	165:d1b4690b3f8b	4921	/**
AnnaBridge	165:d1b4690b3f8b	4922	* @brief Generate Capture/Compare 3 event.
AnnaBridge	165:d1b4690b3f8b	4923	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	165:d1b4690b3f8b	4924	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4925	* @retval None
AnnaBridge	165:d1b4690b3f8b	4926	*/
AnnaBridge	165:d1b4690b3f8b	4927	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4928	{
AnnaBridge	165:d1b4690b3f8b	4929	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	165:d1b4690b3f8b	4930	}
AnnaBridge	165:d1b4690b3f8b	4931
AnnaBridge	165:d1b4690b3f8b	4932	/**
AnnaBridge	165:d1b4690b3f8b	4933	* @brief Generate Capture/Compare 4 event.
AnnaBridge	165:d1b4690b3f8b	4934	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	165:d1b4690b3f8b	4935	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4936	* @retval None
AnnaBridge	165:d1b4690b3f8b	4937	*/
AnnaBridge	165:d1b4690b3f8b	4938	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4939	{
AnnaBridge	165:d1b4690b3f8b	4940	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	165:d1b4690b3f8b	4941	}
AnnaBridge	165:d1b4690b3f8b	4942
AnnaBridge	165:d1b4690b3f8b	4943	/**
AnnaBridge	165:d1b4690b3f8b	4944	* @brief Generate commutation event.
AnnaBridge	165:d1b4690b3f8b	4945	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	165:d1b4690b3f8b	4946	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4947	* @retval None
AnnaBridge	165:d1b4690b3f8b	4948	*/
AnnaBridge	165:d1b4690b3f8b	4949	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4950	{
AnnaBridge	165:d1b4690b3f8b	4951	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	165:d1b4690b3f8b	4952	}
AnnaBridge	165:d1b4690b3f8b	4953
AnnaBridge	165:d1b4690b3f8b	4954	/**
AnnaBridge	165:d1b4690b3f8b	4955	* @brief Generate trigger event.
AnnaBridge	165:d1b4690b3f8b	4956	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	165:d1b4690b3f8b	4957	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4958	* @retval None
AnnaBridge	165:d1b4690b3f8b	4959	*/
AnnaBridge	165:d1b4690b3f8b	4960	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4961	{
AnnaBridge	165:d1b4690b3f8b	4962	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	165:d1b4690b3f8b	4963	}
AnnaBridge	165:d1b4690b3f8b	4964
AnnaBridge	165:d1b4690b3f8b	4965	/**
AnnaBridge	165:d1b4690b3f8b	4966	* @brief Generate break event.
AnnaBridge	165:d1b4690b3f8b	4967	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	165:d1b4690b3f8b	4968	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4969	* @retval None
AnnaBridge	165:d1b4690b3f8b	4970	*/
AnnaBridge	165:d1b4690b3f8b	4971	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4972	{
AnnaBridge	165:d1b4690b3f8b	4973	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	165:d1b4690b3f8b	4974	}
AnnaBridge	165:d1b4690b3f8b	4975
AnnaBridge	165:d1b4690b3f8b	4976	/**
AnnaBridge	165:d1b4690b3f8b	4977	* @brief Generate break 2 event.
AnnaBridge	165:d1b4690b3f8b	4978	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
AnnaBridge	165:d1b4690b3f8b	4979	* @param TIMx Timer instance
AnnaBridge	165:d1b4690b3f8b	4980	* @retval None
AnnaBridge	165:d1b4690b3f8b	4981	*/
AnnaBridge	165:d1b4690b3f8b	4982	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	165:d1b4690b3f8b	4983	{
AnnaBridge	165:d1b4690b3f8b	4984	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
AnnaBridge	165:d1b4690b3f8b	4985	}
AnnaBridge	165:d1b4690b3f8b	4986
AnnaBridge	165:d1b4690b3f8b	4987	/**
AnnaBridge	165:d1b4690b3f8b	4988	* @}
AnnaBridge	165:d1b4690b3f8b	4989	*/
AnnaBridge	165:d1b4690b3f8b	4990
AnnaBridge	165:d1b4690b3f8b	4991	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	4992	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	165:d1b4690b3f8b	4993	* @{
AnnaBridge	165:d1b4690b3f8b	4994	*/
AnnaBridge	165:d1b4690b3f8b	4995
AnnaBridge	165:d1b4690b3f8b	4996	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	165:d1b4690b3f8b	4997	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	165:d1b4690b3f8b	4998	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	165:d1b4690b3f8b	4999	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	165:d1b4690b3f8b	5000	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	165:d1b4690b3f8b	5001	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	165:d1b4690b3f8b	5002	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	165:d1b4690b3f8b	5003	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	165:d1b4690b3f8b	5004	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	165:d1b4690b3f8b	5005	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	165:d1b4690b3f8b	5006	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	165:d1b4690b3f8b	5007	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	165:d1b4690b3f8b	5008	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	165:d1b4690b3f8b	5009	/**
AnnaBridge	165:d1b4690b3f8b	5010	* @}
AnnaBridge	165:d1b4690b3f8b	5011	*/
AnnaBridge	165:d1b4690b3f8b	5012	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	5013
AnnaBridge	165:d1b4690b3f8b	5014	/**
AnnaBridge	165:d1b4690b3f8b	5015	* @}
AnnaBridge	165:d1b4690b3f8b	5016	*/
AnnaBridge	165:d1b4690b3f8b	5017
AnnaBridge	165:d1b4690b3f8b	5018	/**
AnnaBridge	165:d1b4690b3f8b	5019	* @}
AnnaBridge	165:d1b4690b3f8b	5020	*/
AnnaBridge	165:d1b4690b3f8b	5021
AnnaBridge	165:d1b4690b3f8b	5022	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
AnnaBridge	165:d1b4690b3f8b	5023
AnnaBridge	165:d1b4690b3f8b	5024	/**
AnnaBridge	165:d1b4690b3f8b	5025	* @}
AnnaBridge	165:d1b4690b3f8b	5026	*/
AnnaBridge	165:d1b4690b3f8b	5027
AnnaBridge	165:d1b4690b3f8b	5028	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	5029	}
AnnaBridge	165:d1b4690b3f8b	5030	#endif
AnnaBridge	165:d1b4690b3f8b	5031
AnnaBridge	165:d1b4690b3f8b	5032	#endif /* __STM32L4xx_LL_TIM_H */
AnnaBridge	165:d1b4690b3f8b	5033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/