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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_ll_spi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h@167:84c0a372a020

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32l4xx_ll_spi.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of SPI LL module.
AnnaBridge	145:64910690c574	6	******************************************************************************
AnnaBridge	145:64910690c574	7	* @attention
AnnaBridge	145:64910690c574	8	*
AnnaBridge	145:64910690c574	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	12	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	14	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	17	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	19	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	20	* without specific prior written permission.
AnnaBridge	145:64910690c574	21	*
AnnaBridge	145:64910690c574	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	32	*
AnnaBridge	145:64910690c574	33	******************************************************************************
AnnaBridge	145:64910690c574	34	*/
AnnaBridge	145:64910690c574	35
AnnaBridge	145:64910690c574	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	37	#ifndef __STM32L4xx_LL_SPI_H
AnnaBridge	145:64910690c574	38	#define __STM32L4xx_LL_SPI_H
AnnaBridge	145:64910690c574	39
AnnaBridge	145:64910690c574	40	#ifdef __cplusplus
AnnaBridge	145:64910690c574	41	extern "C" {
AnnaBridge	145:64910690c574	42	#endif
AnnaBridge	145:64910690c574	43
AnnaBridge	145:64910690c574	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	45	#include "stm32l4xx.h"
AnnaBridge	145:64910690c574	46
AnnaBridge	145:64910690c574	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	145:64910690c574	48	* @{
AnnaBridge	145:64910690c574	49	*/
AnnaBridge	145:64910690c574	50
AnnaBridge	145:64910690c574	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	/** @defgroup SPI_LL SPI
AnnaBridge	145:64910690c574	54	* @{
AnnaBridge	145:64910690c574	55	*/
AnnaBridge	145:64910690c574	56
AnnaBridge	145:64910690c574	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60
AnnaBridge	145:64910690c574	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	145:64910690c574	64	* @{
AnnaBridge	145:64910690c574	65	*/
AnnaBridge	145:64910690c574	66
AnnaBridge	145:64910690c574	67	/**
AnnaBridge	145:64910690c574	68	* @brief SPI Init structures definition
AnnaBridge	145:64910690c574	69	*/
AnnaBridge	145:64910690c574	70	typedef struct
AnnaBridge	145:64910690c574	71	{
AnnaBridge	145:64910690c574	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	145:64910690c574	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	145:64910690c574	74
AnnaBridge	145:64910690c574	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	145:64910690c574	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	145:64910690c574	79
AnnaBridge	145:64910690c574	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	145:64910690c574	81
AnnaBridge	145:64910690c574	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	145:64910690c574	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	145:64910690c574	84
AnnaBridge	145:64910690c574	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	145:64910690c574	86
AnnaBridge	145:64910690c574	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	145:64910690c574	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	145:64910690c574	89
AnnaBridge	145:64910690c574	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	145:64910690c574	91
AnnaBridge	145:64910690c574	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	145:64910690c574	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	145:64910690c574	94
AnnaBridge	145:64910690c574	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	145:64910690c574	96
AnnaBridge	145:64910690c574	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	145:64910690c574	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	145:64910690c574	99
AnnaBridge	145:64910690c574	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	145:64910690c574	101
AnnaBridge	145:64910690c574	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	145:64910690c574	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	145:64910690c574	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	145:64910690c574	105
AnnaBridge	145:64910690c574	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	145:64910690c574	107
AnnaBridge	145:64910690c574	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	145:64910690c574	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	145:64910690c574	110
AnnaBridge	145:64910690c574	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	145:64910690c574	112
AnnaBridge	145:64910690c574	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	145:64910690c574	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	145:64910690c574	115
AnnaBridge	145:64910690c574	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	145:64910690c574	117
AnnaBridge	145:64910690c574	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	145:64910690c574	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	145:64910690c574	122
AnnaBridge	145:64910690c574	123	} LL_SPI_InitTypeDef;
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	/**
AnnaBridge	145:64910690c574	126	* @}
AnnaBridge	145:64910690c574	127	*/
AnnaBridge	145:64910690c574	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	129
AnnaBridge	145:64910690c574	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	145:64910690c574	132	* @{
AnnaBridge	145:64910690c574	133	*/
AnnaBridge	145:64910690c574	134
AnnaBridge	145:64910690c574	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	145:64910690c574	137	* @{
AnnaBridge	145:64910690c574	138	*/
AnnaBridge	145:64910690c574	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	145:64910690c574	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	145:64910690c574	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	145:64910690c574	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	145:64910690c574	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	145:64910690c574	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	145:64910690c574	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	145:64910690c574	146	/**
AnnaBridge	145:64910690c574	147	* @}
AnnaBridge	145:64910690c574	148	*/
AnnaBridge	145:64910690c574	149
AnnaBridge	145:64910690c574	150	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	145:64910690c574	152	* @{
AnnaBridge	145:64910690c574	153	*/
AnnaBridge	145:64910690c574	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	145:64910690c574	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	145:64910690c574	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	145:64910690c574	157	/**
AnnaBridge	145:64910690c574	158	* @}
AnnaBridge	145:64910690c574	159	*/
AnnaBridge	145:64910690c574	160
AnnaBridge	145:64910690c574	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	145:64910690c574	162	* @{
AnnaBridge	145:64910690c574	163	*/
AnnaBridge	145:64910690c574	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	145:64910690c574	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	145:64910690c574	166	/**
AnnaBridge	145:64910690c574	167	* @}
AnnaBridge	145:64910690c574	168	*/
AnnaBridge	145:64910690c574	169
AnnaBridge	145:64910690c574	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	145:64910690c574	171	* @{
AnnaBridge	145:64910690c574	172	*/
AnnaBridge	145:64910690c574	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	145:64910690c574	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	145:64910690c574	175	/**
AnnaBridge	145:64910690c574	176	* @}
AnnaBridge	145:64910690c574	177	*/
AnnaBridge	145:64910690c574	178
AnnaBridge	145:64910690c574	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	145:64910690c574	180	* @{
AnnaBridge	145:64910690c574	181	*/
AnnaBridge	145:64910690c574	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	184	/**
AnnaBridge	145:64910690c574	185	* @}
AnnaBridge	145:64910690c574	186	*/
AnnaBridge	145:64910690c574	187
AnnaBridge	145:64910690c574	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	145:64910690c574	189	* @{
AnnaBridge	145:64910690c574	190	*/
AnnaBridge	145:64910690c574	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	145:64910690c574	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	145:64910690c574	193	/**
AnnaBridge	145:64910690c574	194	* @}
AnnaBridge	145:64910690c574	195	*/
AnnaBridge	145:64910690c574	196
AnnaBridge	145:64910690c574	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	145:64910690c574	198	* @{
AnnaBridge	145:64910690c574	199	*/
AnnaBridge	145:64910690c574	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	145:64910690c574	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	145:64910690c574	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	145:64910690c574	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	145:64910690c574	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	145:64910690c574	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	145:64910690c574	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	145:64910690c574	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	145:64910690c574	208	/**
AnnaBridge	145:64910690c574	209	* @}
AnnaBridge	145:64910690c574	210	*/
AnnaBridge	145:64910690c574	211
AnnaBridge	145:64910690c574	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	145:64910690c574	213	* @{
AnnaBridge	145:64910690c574	214	*/
AnnaBridge	145:64910690c574	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	145:64910690c574	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	145:64910690c574	217	/**
AnnaBridge	145:64910690c574	218	* @}
AnnaBridge	145:64910690c574	219	*/
AnnaBridge	145:64910690c574	220
AnnaBridge	145:64910690c574	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	145:64910690c574	222	* @{
AnnaBridge	145:64910690c574	223	*/
AnnaBridge	145:64910690c574	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	145:64910690c574	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	145:64910690c574	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	145:64910690c574	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	145:64910690c574	228	/**
AnnaBridge	145:64910690c574	229	* @}
AnnaBridge	145:64910690c574	230	*/
AnnaBridge	145:64910690c574	231
AnnaBridge	145:64910690c574	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	145:64910690c574	233	* @{
AnnaBridge	145:64910690c574	234	*/
AnnaBridge	145:64910690c574	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	145:64910690c574	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	145:64910690c574	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	145:64910690c574	238	/**
AnnaBridge	145:64910690c574	239	* @}
AnnaBridge	145:64910690c574	240	*/
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	145:64910690c574	243	* @{
AnnaBridge	145:64910690c574	244	*/
AnnaBridge	145:64910690c574	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
AnnaBridge	145:64910690c574	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
AnnaBridge	145:64910690c574	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
AnnaBridge	145:64910690c574	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
AnnaBridge	145:64910690c574	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	145:64910690c574	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
AnnaBridge	145:64910690c574	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
AnnaBridge	145:64910690c574	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
AnnaBridge	145:64910690c574	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
AnnaBridge	145:64910690c574	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
AnnaBridge	145:64910690c574	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
AnnaBridge	145:64910690c574	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
AnnaBridge	145:64910690c574	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	145:64910690c574	258	/**
AnnaBridge	145:64910690c574	259	* @}
AnnaBridge	145:64910690c574	260	*/
AnnaBridge	145:64910690c574	261	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	262
AnnaBridge	145:64910690c574	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	145:64910690c574	264	* @{
AnnaBridge	145:64910690c574	265	*/
AnnaBridge	145:64910690c574	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	145:64910690c574	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	145:64910690c574	268	/**
AnnaBridge	145:64910690c574	269	* @}
AnnaBridge	145:64910690c574	270	*/
AnnaBridge	145:64910690c574	271	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	272
AnnaBridge	145:64910690c574	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
AnnaBridge	145:64910690c574	274	* @{
AnnaBridge	145:64910690c574	275	*/
AnnaBridge	145:64910690c574	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
AnnaBridge	145:64910690c574	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
AnnaBridge	145:64910690c574	278	/**
AnnaBridge	145:64910690c574	279	* @}
AnnaBridge	145:64910690c574	280	*/
AnnaBridge	145:64910690c574	281
AnnaBridge	145:64910690c574	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
AnnaBridge	145:64910690c574	283	* @{
AnnaBridge	145:64910690c574	284	*/
AnnaBridge	145:64910690c574	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
AnnaBridge	145:64910690c574	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
AnnaBridge	145:64910690c574	287	/**
AnnaBridge	145:64910690c574	288	* @}
AnnaBridge	145:64910690c574	289	*/
AnnaBridge	145:64910690c574	290
AnnaBridge	145:64910690c574	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
AnnaBridge	145:64910690c574	292	* @{
AnnaBridge	145:64910690c574	293	*/
AnnaBridge	145:64910690c574	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
AnnaBridge	145:64910690c574	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
AnnaBridge	145:64910690c574	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
AnnaBridge	145:64910690c574	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
AnnaBridge	145:64910690c574	298	/**
AnnaBridge	145:64910690c574	299	* @}
AnnaBridge	145:64910690c574	300	*/
AnnaBridge	145:64910690c574	301
AnnaBridge	145:64910690c574	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
AnnaBridge	145:64910690c574	303	* @{
AnnaBridge	145:64910690c574	304	*/
AnnaBridge	145:64910690c574	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
AnnaBridge	145:64910690c574	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
AnnaBridge	145:64910690c574	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
AnnaBridge	145:64910690c574	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
AnnaBridge	145:64910690c574	309	/**
AnnaBridge	145:64910690c574	310	* @}
AnnaBridge	145:64910690c574	311	*/
AnnaBridge	145:64910690c574	312
AnnaBridge	145:64910690c574	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
AnnaBridge	145:64910690c574	314	* @{
AnnaBridge	145:64910690c574	315	*/
AnnaBridge	145:64910690c574	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
AnnaBridge	145:64910690c574	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
AnnaBridge	145:64910690c574	318
AnnaBridge	145:64910690c574	319	/**
AnnaBridge	145:64910690c574	320	* @}
AnnaBridge	145:64910690c574	321	*/
AnnaBridge	145:64910690c574	322
AnnaBridge	145:64910690c574	323	/**
AnnaBridge	145:64910690c574	324	* @}
AnnaBridge	145:64910690c574	325	*/
AnnaBridge	145:64910690c574	326
AnnaBridge	145:64910690c574	327	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	145:64910690c574	329	* @{
AnnaBridge	145:64910690c574	330	*/
AnnaBridge	145:64910690c574	331
AnnaBridge	145:64910690c574	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	333	* @{
AnnaBridge	145:64910690c574	334	*/
AnnaBridge	145:64910690c574	335
AnnaBridge	145:64910690c574	336	/**
AnnaBridge	145:64910690c574	337	* @brief Write a value in SPI register
AnnaBridge	145:64910690c574	338	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	339	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	340	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	341	* @retval None
AnnaBridge	145:64910690c574	342	*/
AnnaBridge	145:64910690c574	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	344
AnnaBridge	145:64910690c574	345	/**
AnnaBridge	145:64910690c574	346	* @brief Read a value in SPI register
AnnaBridge	145:64910690c574	347	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	348	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	349	* @retval Register value
AnnaBridge	145:64910690c574	350	*/
AnnaBridge	145:64910690c574	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	352	/**
AnnaBridge	145:64910690c574	353	* @}
AnnaBridge	145:64910690c574	354	*/
AnnaBridge	145:64910690c574	355
AnnaBridge	145:64910690c574	356	/**
AnnaBridge	145:64910690c574	357	* @}
AnnaBridge	145:64910690c574	358	*/
AnnaBridge	145:64910690c574	359
AnnaBridge	145:64910690c574	360	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	145:64910690c574	362	* @{
AnnaBridge	145:64910690c574	363	*/
AnnaBridge	145:64910690c574	364
AnnaBridge	145:64910690c574	365	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	366	* @{
AnnaBridge	145:64910690c574	367	*/
AnnaBridge	145:64910690c574	368
AnnaBridge	145:64910690c574	369	/**
AnnaBridge	145:64910690c574	370	* @brief Enable SPI peripheral
AnnaBridge	145:64910690c574	371	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	145:64910690c574	372	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	373	* @retval None
AnnaBridge	145:64910690c574	374	*/
AnnaBridge	145:64910690c574	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	376	{
AnnaBridge	145:64910690c574	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	378	}
AnnaBridge	145:64910690c574	379
AnnaBridge	145:64910690c574	380	/**
AnnaBridge	145:64910690c574	381	* @brief Disable SPI peripheral
AnnaBridge	145:64910690c574	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	145:64910690c574	383	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	145:64910690c574	384	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	385	* @retval None
AnnaBridge	145:64910690c574	386	*/
AnnaBridge	145:64910690c574	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	388	{
AnnaBridge	145:64910690c574	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	390	}
AnnaBridge	145:64910690c574	391
AnnaBridge	145:64910690c574	392	/**
AnnaBridge	145:64910690c574	393	* @brief Check if SPI peripheral is enabled
AnnaBridge	145:64910690c574	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	145:64910690c574	395	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	396	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	397	*/
AnnaBridge	145:64910690c574	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	399	{
AnnaBridge	145:64910690c574	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	145:64910690c574	401	}
AnnaBridge	145:64910690c574	402
AnnaBridge	145:64910690c574	403	/**
AnnaBridge	145:64910690c574	404	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	145:64910690c574	405	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	145:64910690c574	407	* CR1 SSI LL_SPI_SetMode
AnnaBridge	145:64910690c574	408	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	409	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	410	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	411	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	412	* @retval None
AnnaBridge	145:64910690c574	413	*/
AnnaBridge	145:64910690c574	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	145:64910690c574	415	{
AnnaBridge	145:64910690c574	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	145:64910690c574	417	}
AnnaBridge	145:64910690c574	418
AnnaBridge	145:64910690c574	419	/**
AnnaBridge	145:64910690c574	420	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	145:64910690c574	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	145:64910690c574	422	* CR1 SSI LL_SPI_GetMode
AnnaBridge	145:64910690c574	423	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	424	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	425	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	426	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	427	*/
AnnaBridge	145:64910690c574	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	429	{
AnnaBridge	145:64910690c574	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	145:64910690c574	431	}
AnnaBridge	145:64910690c574	432
AnnaBridge	145:64910690c574	433	/**
AnnaBridge	145:64910690c574	434	* @brief Set serial protocol used
AnnaBridge	145:64910690c574	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	145:64910690c574	437	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	438	* @param Standard This parameter can be one of the following values:
AnnaBridge	145:64910690c574	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	440	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	441	* @retval None
AnnaBridge	145:64910690c574	442	*/
AnnaBridge	145:64910690c574	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	145:64910690c574	444	{
AnnaBridge	145:64910690c574	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	145:64910690c574	446	}
AnnaBridge	145:64910690c574	447
AnnaBridge	145:64910690c574	448	/**
AnnaBridge	145:64910690c574	449	* @brief Get serial protocol used
AnnaBridge	145:64910690c574	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	145:64910690c574	451	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	452	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	454	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	455	*/
AnnaBridge	145:64910690c574	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	457	{
AnnaBridge	145:64910690c574	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	145:64910690c574	459	}
AnnaBridge	145:64910690c574	460
AnnaBridge	145:64910690c574	461	/**
AnnaBridge	145:64910690c574	462	* @brief Set clock phase
AnnaBridge	145:64910690c574	463	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	464	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	145:64910690c574	466	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	467	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	145:64910690c574	468	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	469	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	470	* @retval None
AnnaBridge	145:64910690c574	471	*/
AnnaBridge	145:64910690c574	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	145:64910690c574	473	{
AnnaBridge	145:64910690c574	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	145:64910690c574	475	}
AnnaBridge	145:64910690c574	476
AnnaBridge	145:64910690c574	477	/**
AnnaBridge	145:64910690c574	478	* @brief Get clock phase
AnnaBridge	145:64910690c574	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	145:64910690c574	480	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	481	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	482	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	483	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	484	*/
AnnaBridge	145:64910690c574	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	486	{
AnnaBridge	145:64910690c574	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	145:64910690c574	488	}
AnnaBridge	145:64910690c574	489
AnnaBridge	145:64910690c574	490	/**
AnnaBridge	145:64910690c574	491	* @brief Set clock polarity
AnnaBridge	145:64910690c574	492	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	493	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	145:64910690c574	495	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	496	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	497	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	498	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	499	* @retval None
AnnaBridge	145:64910690c574	500	*/
AnnaBridge	145:64910690c574	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	145:64910690c574	502	{
AnnaBridge	145:64910690c574	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	145:64910690c574	504	}
AnnaBridge	145:64910690c574	505
AnnaBridge	145:64910690c574	506	/**
AnnaBridge	145:64910690c574	507	* @brief Get clock polarity
AnnaBridge	145:64910690c574	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	145:64910690c574	509	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	510	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	511	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	512	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	513	*/
AnnaBridge	145:64910690c574	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	515	{
AnnaBridge	145:64910690c574	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	145:64910690c574	517	}
AnnaBridge	145:64910690c574	518
AnnaBridge	145:64910690c574	519	/**
AnnaBridge	145:64910690c574	520	* @brief Set baud rate prescaler
AnnaBridge	145:64910690c574	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	145:64910690c574	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	145:64910690c574	523	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	524	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	145:64910690c574	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	533	* @retval None
AnnaBridge	145:64910690c574	534	*/
AnnaBridge	145:64910690c574	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	145:64910690c574	536	{
AnnaBridge	145:64910690c574	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	145:64910690c574	538	}
AnnaBridge	145:64910690c574	539
AnnaBridge	145:64910690c574	540	/**
AnnaBridge	145:64910690c574	541	* @brief Get baud rate prescaler
AnnaBridge	145:64910690c574	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	145:64910690c574	543	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	544	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	553	*/
AnnaBridge	145:64910690c574	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	555	{
AnnaBridge	145:64910690c574	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	145:64910690c574	557	}
AnnaBridge	145:64910690c574	558
AnnaBridge	145:64910690c574	559	/**
AnnaBridge	145:64910690c574	560	* @brief Set transfer bit order
AnnaBridge	145:64910690c574	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	145:64910690c574	563	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	564	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	145:64910690c574	565	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	566	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	567	* @retval None
AnnaBridge	145:64910690c574	568	*/
AnnaBridge	145:64910690c574	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	145:64910690c574	570	{
AnnaBridge	145:64910690c574	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	145:64910690c574	572	}
AnnaBridge	145:64910690c574	573
AnnaBridge	145:64910690c574	574	/**
AnnaBridge	145:64910690c574	575	* @brief Get transfer bit order
AnnaBridge	145:64910690c574	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	145:64910690c574	577	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	578	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	579	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	580	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	581	*/
AnnaBridge	145:64910690c574	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	583	{
AnnaBridge	145:64910690c574	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	145:64910690c574	585	}
AnnaBridge	145:64910690c574	586
AnnaBridge	145:64910690c574	587	/**
AnnaBridge	145:64910690c574	588	* @brief Set transfer direction mode
AnnaBridge	145:64910690c574	589	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	145:64910690c574	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	145:64910690c574	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	145:64910690c574	594	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	595	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	145:64910690c574	596	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	597	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	600	* @retval None
AnnaBridge	145:64910690c574	601	*/
AnnaBridge	145:64910690c574	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	145:64910690c574	603	{
AnnaBridge	145:64910690c574	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	145:64910690c574	605	}
AnnaBridge	145:64910690c574	606
AnnaBridge	145:64910690c574	607	/**
AnnaBridge	145:64910690c574	608	* @brief Get transfer direction mode
AnnaBridge	145:64910690c574	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	145:64910690c574	612	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	613	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	614	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	615	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	618	*/
AnnaBridge	145:64910690c574	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	620	{
AnnaBridge	145:64910690c574	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	145:64910690c574	622	}
AnnaBridge	145:64910690c574	623
AnnaBridge	145:64910690c574	624	/**
AnnaBridge	145:64910690c574	625	* @brief Set frame data width
AnnaBridge	145:64910690c574	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
AnnaBridge	145:64910690c574	627	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	628	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	145:64910690c574	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	145:64910690c574	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	145:64910690c574	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	145:64910690c574	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	145:64910690c574	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	145:64910690c574	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	145:64910690c574	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	145:64910690c574	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	145:64910690c574	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	145:64910690c574	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	145:64910690c574	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	145:64910690c574	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	642	* @retval None
AnnaBridge	145:64910690c574	643	*/
AnnaBridge	145:64910690c574	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	145:64910690c574	645	{
AnnaBridge	145:64910690c574	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
AnnaBridge	145:64910690c574	647	}
AnnaBridge	145:64910690c574	648
AnnaBridge	145:64910690c574	649	/**
AnnaBridge	145:64910690c574	650	* @brief Get frame data width
AnnaBridge	145:64910690c574	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
AnnaBridge	145:64910690c574	652	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	653	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	145:64910690c574	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	145:64910690c574	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	145:64910690c574	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	145:64910690c574	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	145:64910690c574	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	145:64910690c574	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	145:64910690c574	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	145:64910690c574	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	145:64910690c574	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	145:64910690c574	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	145:64910690c574	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	667	*/
AnnaBridge	145:64910690c574	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	669	{
AnnaBridge	145:64910690c574	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
AnnaBridge	145:64910690c574	671	}
AnnaBridge	145:64910690c574	672
AnnaBridge	145:64910690c574	673	/**
AnnaBridge	145:64910690c574	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
AnnaBridge	145:64910690c574	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
AnnaBridge	145:64910690c574	676	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	677	* @param Threshold This parameter can be one of the following values:
AnnaBridge	145:64910690c574	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	145:64910690c574	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	145:64910690c574	680	* @retval None
AnnaBridge	145:64910690c574	681	*/
AnnaBridge	145:64910690c574	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	145:64910690c574	683	{
AnnaBridge	145:64910690c574	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
AnnaBridge	145:64910690c574	685	}
AnnaBridge	145:64910690c574	686
AnnaBridge	145:64910690c574	687	/**
AnnaBridge	145:64910690c574	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
AnnaBridge	145:64910690c574	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
AnnaBridge	145:64910690c574	690	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	691	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	145:64910690c574	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	145:64910690c574	694	*/
AnnaBridge	145:64910690c574	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	696	{
AnnaBridge	145:64910690c574	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
AnnaBridge	145:64910690c574	698	}
AnnaBridge	145:64910690c574	699
AnnaBridge	145:64910690c574	700	/**
AnnaBridge	145:64910690c574	701	* @}
AnnaBridge	145:64910690c574	702	*/
AnnaBridge	145:64910690c574	703
AnnaBridge	145:64910690c574	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	145:64910690c574	705	* @{
AnnaBridge	145:64910690c574	706	*/
AnnaBridge	145:64910690c574	707
AnnaBridge	145:64910690c574	708	/**
AnnaBridge	145:64910690c574	709	* @brief Enable CRC
AnnaBridge	145:64910690c574	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	145:64910690c574	712	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	713	* @retval None
AnnaBridge	145:64910690c574	714	*/
AnnaBridge	145:64910690c574	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	716	{
AnnaBridge	145:64910690c574	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	718	}
AnnaBridge	145:64910690c574	719
AnnaBridge	145:64910690c574	720	/**
AnnaBridge	145:64910690c574	721	* @brief Disable CRC
AnnaBridge	145:64910690c574	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	145:64910690c574	724	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	725	* @retval None
AnnaBridge	145:64910690c574	726	*/
AnnaBridge	145:64910690c574	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	728	{
AnnaBridge	145:64910690c574	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	730	}
AnnaBridge	145:64910690c574	731
AnnaBridge	145:64910690c574	732	/**
AnnaBridge	145:64910690c574	733	* @brief Check if CRC is enabled
AnnaBridge	145:64910690c574	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	145:64910690c574	736	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	737	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	738	*/
AnnaBridge	145:64910690c574	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	740	{
AnnaBridge	145:64910690c574	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	145:64910690c574	742	}
AnnaBridge	145:64910690c574	743
AnnaBridge	145:64910690c574	744	/**
AnnaBridge	145:64910690c574	745	* @brief Set CRC Length
AnnaBridge	145:64910690c574	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
AnnaBridge	145:64910690c574	748	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	749	* @param CRCLength This parameter can be one of the following values:
AnnaBridge	145:64910690c574	750	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	145:64910690c574	751	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	145:64910690c574	752	* @retval None
AnnaBridge	145:64910690c574	753	*/
AnnaBridge	145:64910690c574	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge	145:64910690c574	755	{
AnnaBridge	145:64910690c574	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
AnnaBridge	145:64910690c574	757	}
AnnaBridge	145:64910690c574	758
AnnaBridge	145:64910690c574	759	/**
AnnaBridge	145:64910690c574	760	* @brief Get CRC Length
AnnaBridge	145:64910690c574	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
AnnaBridge	145:64910690c574	762	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	763	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	764	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	145:64910690c574	765	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	145:64910690c574	766	*/
AnnaBridge	145:64910690c574	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	768	{
AnnaBridge	145:64910690c574	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
AnnaBridge	145:64910690c574	770	}
AnnaBridge	145:64910690c574	771
AnnaBridge	145:64910690c574	772	/**
AnnaBridge	145:64910690c574	773	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	145:64910690c574	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	145:64910690c574	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	145:64910690c574	776	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	777	* @retval None
AnnaBridge	145:64910690c574	778	*/
AnnaBridge	145:64910690c574	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	780	{
AnnaBridge	145:64910690c574	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	145:64910690c574	782	}
AnnaBridge	145:64910690c574	783
AnnaBridge	145:64910690c574	784	/**
AnnaBridge	145:64910690c574	785	* @brief Set polynomial for CRC calculation
AnnaBridge	145:64910690c574	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	145:64910690c574	787	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	789	* @retval None
AnnaBridge	145:64910690c574	790	*/
AnnaBridge	145:64910690c574	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	145:64910690c574	792	{
AnnaBridge	145:64910690c574	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	145:64910690c574	794	}
AnnaBridge	145:64910690c574	795
AnnaBridge	145:64910690c574	796	/**
AnnaBridge	145:64910690c574	797	* @brief Get polynomial for CRC calculation
AnnaBridge	145:64910690c574	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	145:64910690c574	799	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	801	*/
AnnaBridge	145:64910690c574	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	803	{
AnnaBridge	145:64910690c574	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	145:64910690c574	805	}
AnnaBridge	145:64910690c574	806
AnnaBridge	145:64910690c574	807	/**
AnnaBridge	145:64910690c574	808	* @brief Get Rx CRC
AnnaBridge	145:64910690c574	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	145:64910690c574	810	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	812	*/
AnnaBridge	145:64910690c574	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	814	{
AnnaBridge	145:64910690c574	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	145:64910690c574	816	}
AnnaBridge	145:64910690c574	817
AnnaBridge	145:64910690c574	818	/**
AnnaBridge	145:64910690c574	819	* @brief Get Tx CRC
AnnaBridge	145:64910690c574	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	145:64910690c574	821	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	823	*/
AnnaBridge	145:64910690c574	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	825	{
AnnaBridge	145:64910690c574	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	145:64910690c574	827	}
AnnaBridge	145:64910690c574	828
AnnaBridge	145:64910690c574	829	/**
AnnaBridge	145:64910690c574	830	* @}
AnnaBridge	145:64910690c574	831	*/
AnnaBridge	145:64910690c574	832
AnnaBridge	145:64910690c574	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	145:64910690c574	834	* @{
AnnaBridge	145:64910690c574	835	*/
AnnaBridge	145:64910690c574	836
AnnaBridge	145:64910690c574	837	/**
AnnaBridge	145:64910690c574	838	* @brief Set NSS mode
AnnaBridge	145:64910690c574	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	145:64910690c574	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	145:64910690c574	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	145:64910690c574	842	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	843	* @param NSS This parameter can be one of the following values:
AnnaBridge	145:64910690c574	844	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	847	* @retval None
AnnaBridge	145:64910690c574	848	*/
AnnaBridge	145:64910690c574	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	145:64910690c574	850	{
AnnaBridge	145:64910690c574	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	145:64910690c574	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	145:64910690c574	853	}
AnnaBridge	145:64910690c574	854
AnnaBridge	145:64910690c574	855	/**
AnnaBridge	145:64910690c574	856	* @brief Get NSS mode
AnnaBridge	145:64910690c574	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	145:64910690c574	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	145:64910690c574	859	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	860	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	861	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	864	*/
AnnaBridge	145:64910690c574	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	866	{
AnnaBridge	145:64910690c574	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	145:64910690c574	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	145:64910690c574	869	return (Ssm \| Ssoe);
AnnaBridge	145:64910690c574	870	}
AnnaBridge	145:64910690c574	871
AnnaBridge	145:64910690c574	872	/**
AnnaBridge	145:64910690c574	873	* @brief Enable NSS pulse management
AnnaBridge	145:64910690c574	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
AnnaBridge	145:64910690c574	876	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	877	* @retval None
AnnaBridge	145:64910690c574	878	*/
AnnaBridge	145:64910690c574	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	880	{
AnnaBridge	145:64910690c574	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	145:64910690c574	882	}
AnnaBridge	145:64910690c574	883
AnnaBridge	145:64910690c574	884	/**
AnnaBridge	145:64910690c574	885	* @brief Disable NSS pulse management
AnnaBridge	145:64910690c574	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
AnnaBridge	145:64910690c574	888	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	889	* @retval None
AnnaBridge	145:64910690c574	890	*/
AnnaBridge	145:64910690c574	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	892	{
AnnaBridge	145:64910690c574	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	145:64910690c574	894	}
AnnaBridge	145:64910690c574	895
AnnaBridge	145:64910690c574	896	/**
AnnaBridge	145:64910690c574	897	* @brief Check if NSS pulse is enabled
AnnaBridge	145:64910690c574	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
AnnaBridge	145:64910690c574	900	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	901	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	902	*/
AnnaBridge	145:64910690c574	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	904	{
AnnaBridge	145:64910690c574	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
AnnaBridge	145:64910690c574	906	}
AnnaBridge	145:64910690c574	907
AnnaBridge	145:64910690c574	908	/**
AnnaBridge	145:64910690c574	909	* @}
AnnaBridge	145:64910690c574	910	*/
AnnaBridge	145:64910690c574	911
AnnaBridge	145:64910690c574	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	145:64910690c574	913	* @{
AnnaBridge	145:64910690c574	914	*/
AnnaBridge	145:64910690c574	915
AnnaBridge	145:64910690c574	916	/**
AnnaBridge	145:64910690c574	917	* @brief Check if Rx buffer is not empty
AnnaBridge	145:64910690c574	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	145:64910690c574	919	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	920	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	921	*/
AnnaBridge	145:64910690c574	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	923	{
AnnaBridge	145:64910690c574	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	145:64910690c574	925	}
AnnaBridge	145:64910690c574	926
AnnaBridge	145:64910690c574	927	/**
AnnaBridge	145:64910690c574	928	* @brief Check if Tx buffer is empty
AnnaBridge	145:64910690c574	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	145:64910690c574	930	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	931	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	932	*/
AnnaBridge	145:64910690c574	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	934	{
AnnaBridge	145:64910690c574	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	145:64910690c574	936	}
AnnaBridge	145:64910690c574	937
AnnaBridge	145:64910690c574	938	/**
AnnaBridge	145:64910690c574	939	* @brief Get CRC error flag
AnnaBridge	145:64910690c574	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	145:64910690c574	941	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	942	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	943	*/
AnnaBridge	145:64910690c574	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	945	{
AnnaBridge	145:64910690c574	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	145:64910690c574	947	}
AnnaBridge	145:64910690c574	948
AnnaBridge	145:64910690c574	949	/**
AnnaBridge	145:64910690c574	950	* @brief Get mode fault error flag
AnnaBridge	145:64910690c574	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	145:64910690c574	952	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	953	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	954	*/
AnnaBridge	145:64910690c574	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	956	{
AnnaBridge	145:64910690c574	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	145:64910690c574	958	}
AnnaBridge	145:64910690c574	959
AnnaBridge	145:64910690c574	960	/**
AnnaBridge	145:64910690c574	961	* @brief Get overrun error flag
AnnaBridge	145:64910690c574	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	145:64910690c574	963	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	964	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	965	*/
AnnaBridge	145:64910690c574	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	967	{
AnnaBridge	145:64910690c574	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	145:64910690c574	969	}
AnnaBridge	145:64910690c574	970
AnnaBridge	145:64910690c574	971	/**
AnnaBridge	145:64910690c574	972	* @brief Get busy flag
AnnaBridge	145:64910690c574	973	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	145:64910690c574	974	* -When the SPI is correctly disabled
AnnaBridge	145:64910690c574	975	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	145:64910690c574	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	145:64910690c574	977	* sent
AnnaBridge	145:64910690c574	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	145:64910690c574	979	* each data transfer.
AnnaBridge	145:64910690c574	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	145:64910690c574	981	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	982	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	983	*/
AnnaBridge	145:64910690c574	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	985	{
AnnaBridge	145:64910690c574	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	145:64910690c574	987	}
AnnaBridge	145:64910690c574	988
AnnaBridge	145:64910690c574	989	/**
AnnaBridge	145:64910690c574	990	* @brief Get frame format error flag
AnnaBridge	145:64910690c574	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	145:64910690c574	992	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	993	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	994	*/
AnnaBridge	145:64910690c574	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	996	{
AnnaBridge	145:64910690c574	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	145:64910690c574	998	}
AnnaBridge	145:64910690c574	999
AnnaBridge	145:64910690c574	1000	/**
AnnaBridge	145:64910690c574	1001	* @brief Get FIFO reception Level
AnnaBridge	145:64910690c574	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
AnnaBridge	145:64910690c574	1003	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1004	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
AnnaBridge	145:64910690c574	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
AnnaBridge	145:64910690c574	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
AnnaBridge	145:64910690c574	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
AnnaBridge	145:64910690c574	1009	*/
AnnaBridge	145:64910690c574	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1011	{
AnnaBridge	145:64910690c574	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
AnnaBridge	145:64910690c574	1013	}
AnnaBridge	145:64910690c574	1014
AnnaBridge	145:64910690c574	1015	/**
AnnaBridge	145:64910690c574	1016	* @brief Get FIFO Transmission Level
AnnaBridge	145:64910690c574	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
AnnaBridge	145:64910690c574	1018	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1019	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
AnnaBridge	145:64910690c574	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
AnnaBridge	145:64910690c574	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
AnnaBridge	145:64910690c574	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
AnnaBridge	145:64910690c574	1024	*/
AnnaBridge	145:64910690c574	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1026	{
AnnaBridge	145:64910690c574	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
AnnaBridge	145:64910690c574	1028	}
AnnaBridge	145:64910690c574	1029
AnnaBridge	145:64910690c574	1030	/**
AnnaBridge	145:64910690c574	1031	* @brief Clear CRC error flag
AnnaBridge	145:64910690c574	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	145:64910690c574	1033	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1034	* @retval None
AnnaBridge	145:64910690c574	1035	*/
AnnaBridge	145:64910690c574	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1037	{
AnnaBridge	145:64910690c574	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	145:64910690c574	1039	}
AnnaBridge	145:64910690c574	1040
AnnaBridge	145:64910690c574	1041	/**
AnnaBridge	145:64910690c574	1042	* @brief Clear mode fault error flag
AnnaBridge	145:64910690c574	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	145:64910690c574	1044	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	145:64910690c574	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	145:64910690c574	1046	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1047	* @retval None
AnnaBridge	145:64910690c574	1048	*/
AnnaBridge	145:64910690c574	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1050	{
AnnaBridge	145:64910690c574	1051	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1052	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	1053	(void) tmpreg;
AnnaBridge	145:64910690c574	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	1055	(void) tmpreg;
AnnaBridge	145:64910690c574	1056	}
AnnaBridge	145:64910690c574	1057
AnnaBridge	145:64910690c574	1058	/**
AnnaBridge	145:64910690c574	1059	* @brief Clear overrun error flag
AnnaBridge	145:64910690c574	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	145:64910690c574	1061	* register followed by a read access to the SPIx_SR register
AnnaBridge	145:64910690c574	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	145:64910690c574	1063	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1064	* @retval None
AnnaBridge	145:64910690c574	1065	*/
AnnaBridge	145:64910690c574	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1067	{
AnnaBridge	145:64910690c574	1068	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1069	tmpreg = SPIx->DR;
AnnaBridge	145:64910690c574	1070	(void) tmpreg;
AnnaBridge	145:64910690c574	1071	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	1072	(void) tmpreg;
AnnaBridge	145:64910690c574	1073	}
AnnaBridge	145:64910690c574	1074
AnnaBridge	145:64910690c574	1075	/**
AnnaBridge	145:64910690c574	1076	* @brief Clear frame format error flag
AnnaBridge	145:64910690c574	1077	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	145:64910690c574	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	145:64910690c574	1079	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1080	* @retval None
AnnaBridge	145:64910690c574	1081	*/
AnnaBridge	145:64910690c574	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1083	{
AnnaBridge	145:64910690c574	1084	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1085	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	1086	(void) tmpreg;
AnnaBridge	145:64910690c574	1087	}
AnnaBridge	145:64910690c574	1088
AnnaBridge	145:64910690c574	1089	/**
AnnaBridge	145:64910690c574	1090	* @}
AnnaBridge	145:64910690c574	1091	*/
AnnaBridge	145:64910690c574	1092
AnnaBridge	145:64910690c574	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	145:64910690c574	1094	* @{
AnnaBridge	145:64910690c574	1095	*/
AnnaBridge	145:64910690c574	1096
AnnaBridge	145:64910690c574	1097	/**
AnnaBridge	145:64910690c574	1098	* @brief Enable error interrupt
AnnaBridge	145:64910690c574	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	145:64910690c574	1101	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1102	* @retval None
AnnaBridge	145:64910690c574	1103	*/
AnnaBridge	145:64910690c574	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1105	{
AnnaBridge	145:64910690c574	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	1107	}
AnnaBridge	145:64910690c574	1108
AnnaBridge	145:64910690c574	1109	/**
AnnaBridge	145:64910690c574	1110	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	145:64910690c574	1112	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1113	* @retval None
AnnaBridge	145:64910690c574	1114	*/
AnnaBridge	145:64910690c574	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1116	{
AnnaBridge	145:64910690c574	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	1118	}
AnnaBridge	145:64910690c574	1119
AnnaBridge	145:64910690c574	1120	/**
AnnaBridge	145:64910690c574	1121	* @brief Enable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	145:64910690c574	1123	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1124	* @retval None
AnnaBridge	145:64910690c574	1125	*/
AnnaBridge	145:64910690c574	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1127	{
AnnaBridge	145:64910690c574	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	1129	}
AnnaBridge	145:64910690c574	1130
AnnaBridge	145:64910690c574	1131	/**
AnnaBridge	145:64910690c574	1132	* @brief Disable error interrupt
AnnaBridge	145:64910690c574	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	145:64910690c574	1135	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1136	* @retval None
AnnaBridge	145:64910690c574	1137	*/
AnnaBridge	145:64910690c574	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1139	{
AnnaBridge	145:64910690c574	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	1141	}
AnnaBridge	145:64910690c574	1142
AnnaBridge	145:64910690c574	1143	/**
AnnaBridge	145:64910690c574	1144	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	145:64910690c574	1146	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1147	* @retval None
AnnaBridge	145:64910690c574	1148	*/
AnnaBridge	145:64910690c574	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1150	{
AnnaBridge	145:64910690c574	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	1152	}
AnnaBridge	145:64910690c574	1153
AnnaBridge	145:64910690c574	1154	/**
AnnaBridge	145:64910690c574	1155	* @brief Disable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	145:64910690c574	1157	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1158	* @retval None
AnnaBridge	145:64910690c574	1159	*/
AnnaBridge	145:64910690c574	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1161	{
AnnaBridge	145:64910690c574	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	1163	}
AnnaBridge	145:64910690c574	1164
AnnaBridge	145:64910690c574	1165	/**
AnnaBridge	145:64910690c574	1166	* @brief Check if error interrupt is enabled
AnnaBridge	145:64910690c574	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	145:64910690c574	1168	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1169	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1170	*/
AnnaBridge	145:64910690c574	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1172	{
AnnaBridge	145:64910690c574	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	145:64910690c574	1174	}
AnnaBridge	145:64910690c574	1175
AnnaBridge	145:64910690c574	1176	/**
AnnaBridge	145:64910690c574	1177	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	145:64910690c574	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	145:64910690c574	1179	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1180	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1181	*/
AnnaBridge	145:64910690c574	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1183	{
AnnaBridge	145:64910690c574	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	145:64910690c574	1185	}
AnnaBridge	145:64910690c574	1186
AnnaBridge	145:64910690c574	1187	/**
AnnaBridge	145:64910690c574	1188	* @brief Check if Tx buffer empty interrupt
AnnaBridge	145:64910690c574	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	145:64910690c574	1190	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1191	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1192	*/
AnnaBridge	145:64910690c574	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1194	{
AnnaBridge	145:64910690c574	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	145:64910690c574	1196	}
AnnaBridge	145:64910690c574	1197
AnnaBridge	145:64910690c574	1198	/**
AnnaBridge	145:64910690c574	1199	* @}
AnnaBridge	145:64910690c574	1200	*/
AnnaBridge	145:64910690c574	1201
AnnaBridge	145:64910690c574	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	145:64910690c574	1203	* @{
AnnaBridge	145:64910690c574	1204	*/
AnnaBridge	145:64910690c574	1205
AnnaBridge	145:64910690c574	1206	/**
AnnaBridge	145:64910690c574	1207	* @brief Enable DMA Rx
AnnaBridge	145:64910690c574	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	145:64910690c574	1209	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1210	* @retval None
AnnaBridge	145:64910690c574	1211	*/
AnnaBridge	145:64910690c574	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1213	{
AnnaBridge	145:64910690c574	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1215	}
AnnaBridge	145:64910690c574	1216
AnnaBridge	145:64910690c574	1217	/**
AnnaBridge	145:64910690c574	1218	* @brief Disable DMA Rx
AnnaBridge	145:64910690c574	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	145:64910690c574	1220	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1221	* @retval None
AnnaBridge	145:64910690c574	1222	*/
AnnaBridge	145:64910690c574	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1224	{
AnnaBridge	145:64910690c574	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1226	}
AnnaBridge	145:64910690c574	1227
AnnaBridge	145:64910690c574	1228	/**
AnnaBridge	145:64910690c574	1229	* @brief Check if DMA Rx is enabled
AnnaBridge	145:64910690c574	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	145:64910690c574	1231	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1232	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1233	*/
AnnaBridge	145:64910690c574	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1235	{
AnnaBridge	145:64910690c574	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	145:64910690c574	1237	}
AnnaBridge	145:64910690c574	1238
AnnaBridge	145:64910690c574	1239	/**
AnnaBridge	145:64910690c574	1240	* @brief Enable DMA Tx
AnnaBridge	145:64910690c574	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	145:64910690c574	1242	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1243	* @retval None
AnnaBridge	145:64910690c574	1244	*/
AnnaBridge	145:64910690c574	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1246	{
AnnaBridge	145:64910690c574	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1248	}
AnnaBridge	145:64910690c574	1249
AnnaBridge	145:64910690c574	1250	/**
AnnaBridge	145:64910690c574	1251	* @brief Disable DMA Tx
AnnaBridge	145:64910690c574	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	145:64910690c574	1253	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1254	* @retval None
AnnaBridge	145:64910690c574	1255	*/
AnnaBridge	145:64910690c574	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1257	{
AnnaBridge	145:64910690c574	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1259	}
AnnaBridge	145:64910690c574	1260
AnnaBridge	145:64910690c574	1261	/**
AnnaBridge	145:64910690c574	1262	* @brief Check if DMA Tx is enabled
AnnaBridge	145:64910690c574	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	145:64910690c574	1264	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1265	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1266	*/
AnnaBridge	145:64910690c574	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1268	{
AnnaBridge	145:64910690c574	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	145:64910690c574	1270	}
AnnaBridge	145:64910690c574	1271
AnnaBridge	145:64910690c574	1272	/**
AnnaBridge	145:64910690c574	1273	* @brief Set parity of Last DMA reception
AnnaBridge	145:64910690c574	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
AnnaBridge	145:64910690c574	1275	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1276	* @param Parity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	145:64910690c574	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	145:64910690c574	1279	* @retval None
AnnaBridge	145:64910690c574	1280	*/
AnnaBridge	145:64910690c574	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	145:64910690c574	1282	{
AnnaBridge	145:64910690c574	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
AnnaBridge	145:64910690c574	1284	}
AnnaBridge	145:64910690c574	1285
AnnaBridge	145:64910690c574	1286	/**
AnnaBridge	145:64910690c574	1287	* @brief Get parity configuration for Last DMA reception
AnnaBridge	145:64910690c574	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
AnnaBridge	145:64910690c574	1289	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1290	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	145:64910690c574	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	145:64910690c574	1293	*/
AnnaBridge	145:64910690c574	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1295	{
AnnaBridge	145:64910690c574	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
AnnaBridge	145:64910690c574	1297	}
AnnaBridge	145:64910690c574	1298
AnnaBridge	145:64910690c574	1299	/**
AnnaBridge	145:64910690c574	1300	* @brief Set parity of Last DMA transmission
AnnaBridge	145:64910690c574	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
AnnaBridge	145:64910690c574	1302	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1303	* @param Parity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	145:64910690c574	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	145:64910690c574	1306	* @retval None
AnnaBridge	145:64910690c574	1307	*/
AnnaBridge	145:64910690c574	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	145:64910690c574	1309	{
AnnaBridge	145:64910690c574	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
AnnaBridge	145:64910690c574	1311	}
AnnaBridge	145:64910690c574	1312
AnnaBridge	145:64910690c574	1313	/**
AnnaBridge	145:64910690c574	1314	* @brief Get parity configuration for Last DMA transmission
AnnaBridge	145:64910690c574	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
AnnaBridge	145:64910690c574	1316	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1317	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	145:64910690c574	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	145:64910690c574	1320	*/
AnnaBridge	145:64910690c574	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1322	{
AnnaBridge	145:64910690c574	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
AnnaBridge	145:64910690c574	1324	}
AnnaBridge	145:64910690c574	1325
AnnaBridge	145:64910690c574	1326	/**
AnnaBridge	145:64910690c574	1327	* @brief Get the data register address used for DMA transfer
AnnaBridge	145:64910690c574	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	145:64910690c574	1329	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1330	* @retval Address of data register
AnnaBridge	145:64910690c574	1331	*/
AnnaBridge	145:64910690c574	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1333	{
AnnaBridge	145:64910690c574	1334	return (uint32_t) & (SPIx->DR);
AnnaBridge	145:64910690c574	1335	}
AnnaBridge	145:64910690c574	1336
AnnaBridge	145:64910690c574	1337	/**
AnnaBridge	145:64910690c574	1338	* @}
AnnaBridge	145:64910690c574	1339	*/
AnnaBridge	145:64910690c574	1340
AnnaBridge	145:64910690c574	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	145:64910690c574	1342	* @{
AnnaBridge	145:64910690c574	1343	*/
AnnaBridge	145:64910690c574	1344
AnnaBridge	145:64910690c574	1345	/**
AnnaBridge	145:64910690c574	1346	* @brief Read 8-Bits in the data register
AnnaBridge	145:64910690c574	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	145:64910690c574	1348	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1350	*/
AnnaBridge	145:64910690c574	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1352	{
AnnaBridge	145:64910690c574	1353	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1354	}
AnnaBridge	145:64910690c574	1355
AnnaBridge	145:64910690c574	1356	/**
AnnaBridge	145:64910690c574	1357	* @brief Read 16-Bits in the data register
AnnaBridge	145:64910690c574	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	145:64910690c574	1359	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1361	*/
AnnaBridge	145:64910690c574	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1363	{
AnnaBridge	145:64910690c574	1364	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1365	}
AnnaBridge	145:64910690c574	1366
AnnaBridge	145:64910690c574	1367	/**
AnnaBridge	145:64910690c574	1368	* @brief Write 8-Bits in the data register
AnnaBridge	145:64910690c574	1369	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	145:64910690c574	1370	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1372	* @retval None
AnnaBridge	145:64910690c574	1373	*/
AnnaBridge	145:64910690c574	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	145:64910690c574	1375	{
AnnaBridge	145:64910690c574	1376	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	145:64910690c574	1377	}
AnnaBridge	145:64910690c574	1378
AnnaBridge	167:84c0a372a020	1379	#if __GNUC__
AnnaBridge	167:84c0a372a020	1380	# define MAY_ALIAS __attribute__ ((__may_alias__))
AnnaBridge	167:84c0a372a020	1381	#else
AnnaBridge	167:84c0a372a020	1382	# define MAY_ALIAS
AnnaBridge	167:84c0a372a020	1383	#endif
AnnaBridge	167:84c0a372a020	1384
AnnaBridge	167:84c0a372a020	1385	typedef __IO uint16_t MAY_ALIAS uint16_io_t;
AnnaBridge	167:84c0a372a020	1386
AnnaBridge	145:64910690c574	1387	/**
AnnaBridge	145:64910690c574	1388	* @brief Write 16-Bits in the data register
AnnaBridge	145:64910690c574	1389	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	145:64910690c574	1390	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1391	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1392	* @retval None
AnnaBridge	145:64910690c574	1393	*/
AnnaBridge	145:64910690c574	1394	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	145:64910690c574	1395	{
AnnaBridge	167:84c0a372a020	1396	((uint16_io_t)&SPIx->DR) = TxData;
AnnaBridge	145:64910690c574	1397	}
AnnaBridge	145:64910690c574	1398
AnnaBridge	145:64910690c574	1399	/**
AnnaBridge	145:64910690c574	1400	* @}
AnnaBridge	145:64910690c574	1401	*/
AnnaBridge	145:64910690c574	1402	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1403	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	1404	* @{
AnnaBridge	145:64910690c574	1405	*/
AnnaBridge	145:64910690c574	1406
AnnaBridge	145:64910690c574	1407	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	145:64910690c574	1408	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	145:64910690c574	1409	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	145:64910690c574	1410
AnnaBridge	145:64910690c574	1411	/**
AnnaBridge	145:64910690c574	1412	* @}
AnnaBridge	145:64910690c574	1413	*/
AnnaBridge	145:64910690c574	1414	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1415	/**
AnnaBridge	145:64910690c574	1416	* @}
AnnaBridge	145:64910690c574	1417	*/
AnnaBridge	145:64910690c574	1418
AnnaBridge	145:64910690c574	1419	/**
AnnaBridge	145:64910690c574	1420	* @}
AnnaBridge	145:64910690c574	1421	*/
AnnaBridge	145:64910690c574	1422
AnnaBridge	145:64910690c574	1423	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	145:64910690c574	1424
AnnaBridge	145:64910690c574	1425	/**
AnnaBridge	145:64910690c574	1426	* @}
AnnaBridge	145:64910690c574	1427	*/
AnnaBridge	145:64910690c574	1428
AnnaBridge	145:64910690c574	1429	#ifdef __cplusplus
AnnaBridge	145:64910690c574	1430	}
AnnaBridge	145:64910690c574	1431	#endif
AnnaBridge	145:64910690c574	1432
AnnaBridge	145:64910690c574	1433	#endif /* __STM32L4xx_LL_SPI_H */
AnnaBridge	145:64910690c574	1434
AnnaBridge	145:64910690c574	1435	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/