mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_ll_sdmmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_ll_sdmmc.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of low layer SDMMC HAL module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_LL_SDMMC_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_LL_SDMMC_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	#if defined(SDMMC1)
AnnaBridge	165:d1b4690b3f8b	45
AnnaBridge	165:d1b4690b3f8b	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	47	#include "stm32l4xx_hal_def.h"
AnnaBridge	165:d1b4690b3f8b	48
AnnaBridge	165:d1b4690b3f8b	49	/** @addtogroup STM32L4xx_Driver
AnnaBridge	165:d1b4690b3f8b	50	* @{
AnnaBridge	165:d1b4690b3f8b	51	*/
AnnaBridge	165:d1b4690b3f8b	52
AnnaBridge	165:d1b4690b3f8b	53	/** @addtogroup SDMMC_LL
AnnaBridge	165:d1b4690b3f8b	54	* @{
AnnaBridge	165:d1b4690b3f8b	55	*/
AnnaBridge	165:d1b4690b3f8b	56
AnnaBridge	165:d1b4690b3f8b	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	165:d1b4690b3f8b	59	* @{
AnnaBridge	165:d1b4690b3f8b	60	*/
AnnaBridge	165:d1b4690b3f8b	61
AnnaBridge	165:d1b4690b3f8b	62	/**
AnnaBridge	165:d1b4690b3f8b	63	* @brief SDMMC Configuration Structure definition
AnnaBridge	165:d1b4690b3f8b	64	*/
AnnaBridge	165:d1b4690b3f8b	65	typedef struct
AnnaBridge	165:d1b4690b3f8b	66	{
AnnaBridge	165:d1b4690b3f8b	67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	165:d1b4690b3f8b	68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	165:d1b4690b3f8b	69
AnnaBridge	165:d1b4690b3f8b	70	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	71	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	165:d1b4690b3f8b	72	enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	73	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	165:d1b4690b3f8b	74	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	75
AnnaBridge	165:d1b4690b3f8b	76	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	165:d1b4690b3f8b	77	disabled when the bus is idle.
AnnaBridge	165:d1b4690b3f8b	78	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	165:d1b4690b3f8b	79
AnnaBridge	165:d1b4690b3f8b	80	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	165:d1b4690b3f8b	81	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	165:d1b4690b3f8b	82
AnnaBridge	165:d1b4690b3f8b	83	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	84	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	165:d1b4690b3f8b	85
AnnaBridge	165:d1b4690b3f8b	86	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	165:d1b4690b3f8b	87	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	165:d1b4690b3f8b	88
AnnaBridge	165:d1b4690b3f8b	89	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	90	uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	91	This parameter can be a value of @ref SDMMC_LL_Transceiver */
AnnaBridge	165:d1b4690b3f8b	92	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	93
AnnaBridge	165:d1b4690b3f8b	94	}SDMMC_InitTypeDef;
AnnaBridge	165:d1b4690b3f8b	95
AnnaBridge	165:d1b4690b3f8b	96
AnnaBridge	165:d1b4690b3f8b	97	/**
AnnaBridge	165:d1b4690b3f8b	98	* @brief SDMMC Command Control structure
AnnaBridge	165:d1b4690b3f8b	99	*/
AnnaBridge	165:d1b4690b3f8b	100	typedef struct
AnnaBridge	165:d1b4690b3f8b	101	{
AnnaBridge	165:d1b4690b3f8b	102	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	165:d1b4690b3f8b	103	to a card as part of a command message. If a command
AnnaBridge	165:d1b4690b3f8b	104	contains an argument, it must be loaded into this register
AnnaBridge	165:d1b4690b3f8b	105	before writing the command to the command register. */
AnnaBridge	165:d1b4690b3f8b	106
AnnaBridge	165:d1b4690b3f8b	107	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	165:d1b4690b3f8b	108	Max_Data = 64 */
AnnaBridge	165:d1b4690b3f8b	109
AnnaBridge	165:d1b4690b3f8b	110	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	165:d1b4690b3f8b	111	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	165:d1b4690b3f8b	112
AnnaBridge	165:d1b4690b3f8b	113	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	165:d1b4690b3f8b	114	enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	115	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	165:d1b4690b3f8b	116
AnnaBridge	165:d1b4690b3f8b	117	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	165:d1b4690b3f8b	118	is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	119	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	165:d1b4690b3f8b	120	}SDMMC_CmdInitTypeDef;
AnnaBridge	165:d1b4690b3f8b	121
AnnaBridge	165:d1b4690b3f8b	122
AnnaBridge	165:d1b4690b3f8b	123	/**
AnnaBridge	165:d1b4690b3f8b	124	* @brief SDMMC Data Control structure
AnnaBridge	165:d1b4690b3f8b	125	*/
AnnaBridge	165:d1b4690b3f8b	126	typedef struct
AnnaBridge	165:d1b4690b3f8b	127	{
AnnaBridge	165:d1b4690b3f8b	128	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	165:d1b4690b3f8b	129
AnnaBridge	165:d1b4690b3f8b	130	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	165:d1b4690b3f8b	131
AnnaBridge	165:d1b4690b3f8b	132	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	165:d1b4690b3f8b	133	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	165:d1b4690b3f8b	134
AnnaBridge	165:d1b4690b3f8b	135	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	165:d1b4690b3f8b	136	is a read or write.
AnnaBridge	165:d1b4690b3f8b	137	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	165:d1b4690b3f8b	138
AnnaBridge	165:d1b4690b3f8b	139	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	165:d1b4690b3f8b	140	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	165:d1b4690b3f8b	141
AnnaBridge	165:d1b4690b3f8b	142	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	165:d1b4690b3f8b	143	is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	144	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	165:d1b4690b3f8b	145	}SDMMC_DataInitTypeDef;
AnnaBridge	165:d1b4690b3f8b	146
AnnaBridge	165:d1b4690b3f8b	147	/**
AnnaBridge	165:d1b4690b3f8b	148	* @}
AnnaBridge	165:d1b4690b3f8b	149	*/
AnnaBridge	165:d1b4690b3f8b	150
AnnaBridge	165:d1b4690b3f8b	151	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	152	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	165:d1b4690b3f8b	153	* @{
AnnaBridge	165:d1b4690b3f8b	154	*/
AnnaBridge	165:d1b4690b3f8b	155	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	165:d1b4690b3f8b	156	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
AnnaBridge	165:d1b4690b3f8b	157	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
AnnaBridge	165:d1b4690b3f8b	158	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
AnnaBridge	165:d1b4690b3f8b	159	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
AnnaBridge	165:d1b4690b3f8b	160	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
AnnaBridge	165:d1b4690b3f8b	161	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
AnnaBridge	165:d1b4690b3f8b	162	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
AnnaBridge	165:d1b4690b3f8b	163	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge	165:d1b4690b3f8b	164	number of transferred bytes does not match the block length */
AnnaBridge	165:d1b4690b3f8b	165	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
AnnaBridge	165:d1b4690b3f8b	166	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
AnnaBridge	165:d1b4690b3f8b	167	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
AnnaBridge	165:d1b4690b3f8b	168	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge	165:d1b4690b3f8b	169	command or if there was an attempt to access a locked card */
AnnaBridge	165:d1b4690b3f8b	170	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
AnnaBridge	165:d1b4690b3f8b	171	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
AnnaBridge	165:d1b4690b3f8b	172	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	165:d1b4690b3f8b	173	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
AnnaBridge	165:d1b4690b3f8b	174	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
AnnaBridge	165:d1b4690b3f8b	175	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
AnnaBridge	165:d1b4690b3f8b	176	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
AnnaBridge	165:d1b4690b3f8b	177	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
AnnaBridge	165:d1b4690b3f8b	178	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
AnnaBridge	165:d1b4690b3f8b	179	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
AnnaBridge	165:d1b4690b3f8b	180	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge	165:d1b4690b3f8b	181	of erase sequence command was received */
AnnaBridge	165:d1b4690b3f8b	182	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
AnnaBridge	165:d1b4690b3f8b	183	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
AnnaBridge	165:d1b4690b3f8b	184	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
AnnaBridge	165:d1b4690b3f8b	185	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
AnnaBridge	165:d1b4690b3f8b	186	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
AnnaBridge	165:d1b4690b3f8b	187	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
AnnaBridge	165:d1b4690b3f8b	188	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
AnnaBridge	165:d1b4690b3f8b	189	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
AnnaBridge	165:d1b4690b3f8b	190	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
AnnaBridge	165:d1b4690b3f8b	191
AnnaBridge	165:d1b4690b3f8b	192	/**
AnnaBridge	165:d1b4690b3f8b	193	* @brief SDMMC Commands Index
AnnaBridge	165:d1b4690b3f8b	194	*/
AnnaBridge	165:d1b4690b3f8b	195	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
AnnaBridge	165:d1b4690b3f8b	196	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	165:d1b4690b3f8b	197	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	165:d1b4690b3f8b	198	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	165:d1b4690b3f8b	199	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
AnnaBridge	165:d1b4690b3f8b	200	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	165:d1b4690b3f8b	201	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	165:d1b4690b3f8b	202	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	165:d1b4690b3f8b	203	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	165:d1b4690b3f8b	204	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	165:d1b4690b3f8b	205	and asks the card whether card supports voltage. */
AnnaBridge	165:d1b4690b3f8b	206	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	165:d1b4690b3f8b	207	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	165:d1b4690b3f8b	208	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	209	#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /!< SD card Voltage switch to 1.8V mode. /
AnnaBridge	165:d1b4690b3f8b	210	#else
AnnaBridge	165:d1b4690b3f8b	211	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
AnnaBridge	165:d1b4690b3f8b	212	#endif
AnnaBridge	165:d1b4690b3f8b	213	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
AnnaBridge	165:d1b4690b3f8b	214	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
AnnaBridge	165:d1b4690b3f8b	215	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
AnnaBridge	165:d1b4690b3f8b	216	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
AnnaBridge	165:d1b4690b3f8b	217	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	165:d1b4690b3f8b	218	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	165:d1b4690b3f8b	219	for SDHS and SDXC. */
AnnaBridge	165:d1b4690b3f8b	220	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	165:d1b4690b3f8b	221	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	165:d1b4690b3f8b	222	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	165:d1b4690b3f8b	223	STOP_TRANSMISSION command. */
AnnaBridge	165:d1b4690b3f8b	224	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	165:d1b4690b3f8b	225	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
AnnaBridge	165:d1b4690b3f8b	226	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	165:d1b4690b3f8b	227	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	165:d1b4690b3f8b	228	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	165:d1b4690b3f8b	229	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	165:d1b4690b3f8b	230	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
AnnaBridge	165:d1b4690b3f8b	231	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	165:d1b4690b3f8b	232	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	165:d1b4690b3f8b	233	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	165:d1b4690b3f8b	234	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	165:d1b4690b3f8b	235	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	165:d1b4690b3f8b	236	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	165:d1b4690b3f8b	237	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	165:d1b4690b3f8b	238	system set by switch function command (CMD6). */
AnnaBridge	165:d1b4690b3f8b	239	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	165:d1b4690b3f8b	240	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	165:d1b4690b3f8b	241	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
AnnaBridge	165:d1b4690b3f8b	242	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	165:d1b4690b3f8b	243	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	165:d1b4690b3f8b	244	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	165:d1b4690b3f8b	245	the SET_BLOCK_LEN command. */
AnnaBridge	165:d1b4690b3f8b	246	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	165:d1b4690b3f8b	247	than a standard command. */
AnnaBridge	165:d1b4690b3f8b	248	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	165:d1b4690b3f8b	249	for general purpose/application specific commands. */
AnnaBridge	165:d1b4690b3f8b	250	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
AnnaBridge	165:d1b4690b3f8b	251
AnnaBridge	165:d1b4690b3f8b	252	/**
AnnaBridge	165:d1b4690b3f8b	253	* @brief Following commands are SD Card Specific commands.
AnnaBridge	165:d1b4690b3f8b	254	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	165:d1b4690b3f8b	255	*/
AnnaBridge	165:d1b4690b3f8b	256	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	165:d1b4690b3f8b	257	widths are given in SCR register. */
AnnaBridge	165:d1b4690b3f8b	258	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
AnnaBridge	165:d1b4690b3f8b	259	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	165:d1b4690b3f8b	260	32bit+CRC data block. */
AnnaBridge	165:d1b4690b3f8b	261	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	165:d1b4690b3f8b	262	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	165:d1b4690b3f8b	263	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	165:d1b4690b3f8b	264	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	165:d1b4690b3f8b	265	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	165:d1b4690b3f8b	266	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	165:d1b4690b3f8b	267
AnnaBridge	165:d1b4690b3f8b	268	/**
AnnaBridge	165:d1b4690b3f8b	269	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	165:d1b4690b3f8b	270	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	165:d1b4690b3f8b	271	*/
AnnaBridge	165:d1b4690b3f8b	272	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge	165:d1b4690b3f8b	273	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge	165:d1b4690b3f8b	274	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge	165:d1b4690b3f8b	275	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge	165:d1b4690b3f8b	276	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge	165:d1b4690b3f8b	277	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge	165:d1b4690b3f8b	278	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge	165:d1b4690b3f8b	279	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge	165:d1b4690b3f8b	280	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge	165:d1b4690b3f8b	281	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge	165:d1b4690b3f8b	282	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge	165:d1b4690b3f8b	283
AnnaBridge	165:d1b4690b3f8b	284	/**
AnnaBridge	165:d1b4690b3f8b	285	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	165:d1b4690b3f8b	286	*/
AnnaBridge	165:d1b4690b3f8b	287	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge	165:d1b4690b3f8b	288	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge	165:d1b4690b3f8b	289	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge	165:d1b4690b3f8b	290	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge	165:d1b4690b3f8b	291	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge	165:d1b4690b3f8b	292	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge	165:d1b4690b3f8b	293	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge	165:d1b4690b3f8b	294	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge	165:d1b4690b3f8b	295	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge	165:d1b4690b3f8b	296	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge	165:d1b4690b3f8b	297	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge	165:d1b4690b3f8b	298	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge	165:d1b4690b3f8b	299	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge	165:d1b4690b3f8b	300	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge	165:d1b4690b3f8b	301	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge	165:d1b4690b3f8b	302	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge	165:d1b4690b3f8b	303	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge	165:d1b4690b3f8b	304	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge	165:d1b4690b3f8b	305	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge	165:d1b4690b3f8b	306	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge	165:d1b4690b3f8b	307
AnnaBridge	165:d1b4690b3f8b	308	/**
AnnaBridge	165:d1b4690b3f8b	309	* @brief Masks for R6 Response
AnnaBridge	165:d1b4690b3f8b	310	*/
AnnaBridge	165:d1b4690b3f8b	311	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge	165:d1b4690b3f8b	312	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge	165:d1b4690b3f8b	313	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge	165:d1b4690b3f8b	314
AnnaBridge	165:d1b4690b3f8b	315	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge	165:d1b4690b3f8b	316	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge	165:d1b4690b3f8b	317	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	318	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge	165:d1b4690b3f8b	319	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	320	#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
AnnaBridge	165:d1b4690b3f8b	321	#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
AnnaBridge	165:d1b4690b3f8b	322	#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
AnnaBridge	165:d1b4690b3f8b	323	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	324
AnnaBridge	165:d1b4690b3f8b	325	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	165:d1b4690b3f8b	326
AnnaBridge	165:d1b4690b3f8b	327	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	165:d1b4690b3f8b	328
AnnaBridge	165:d1b4690b3f8b	329	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	330
AnnaBridge	165:d1b4690b3f8b	331	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge	165:d1b4690b3f8b	332	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge	165:d1b4690b3f8b	333	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge	165:d1b4690b3f8b	334
AnnaBridge	165:d1b4690b3f8b	335	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge	165:d1b4690b3f8b	336
AnnaBridge	165:d1b4690b3f8b	337	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge	165:d1b4690b3f8b	338	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge	165:d1b4690b3f8b	339	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge	165:d1b4690b3f8b	340	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge	165:d1b4690b3f8b	341	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge	165:d1b4690b3f8b	342
AnnaBridge	165:d1b4690b3f8b	343	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge	165:d1b4690b3f8b	344	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge	165:d1b4690b3f8b	345
AnnaBridge	165:d1b4690b3f8b	346	/**
AnnaBridge	165:d1b4690b3f8b	347	* @brief Command Class supported
AnnaBridge	165:d1b4690b3f8b	348	*/
AnnaBridge	165:d1b4690b3f8b	349	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge	165:d1b4690b3f8b	350
AnnaBridge	165:d1b4690b3f8b	351	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge	165:d1b4690b3f8b	352	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge	165:d1b4690b3f8b	353	#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
AnnaBridge	165:d1b4690b3f8b	354
AnnaBridge	165:d1b4690b3f8b	355	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
AnnaBridge	165:d1b4690b3f8b	356	* @{
AnnaBridge	165:d1b4690b3f8b	357	*/
AnnaBridge	165:d1b4690b3f8b	358	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	359	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
AnnaBridge	165:d1b4690b3f8b	360
AnnaBridge	165:d1b4690b3f8b	361	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	165:d1b4690b3f8b	362	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
AnnaBridge	165:d1b4690b3f8b	363	/**
AnnaBridge	165:d1b4690b3f8b	364	* @}
AnnaBridge	165:d1b4690b3f8b	365	*/
AnnaBridge	165:d1b4690b3f8b	366
AnnaBridge	165:d1b4690b3f8b	367	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	368	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
AnnaBridge	165:d1b4690b3f8b	369	* @{
AnnaBridge	165:d1b4690b3f8b	370	*/
AnnaBridge	165:d1b4690b3f8b	371	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	372	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
AnnaBridge	165:d1b4690b3f8b	373
AnnaBridge	165:d1b4690b3f8b	374	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	375	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
AnnaBridge	165:d1b4690b3f8b	376	/**
AnnaBridge	165:d1b4690b3f8b	377	* @}
AnnaBridge	165:d1b4690b3f8b	378	*/
AnnaBridge	165:d1b4690b3f8b	379	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	380
AnnaBridge	165:d1b4690b3f8b	381	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	165:d1b4690b3f8b	382	* @{
AnnaBridge	165:d1b4690b3f8b	383	*/
AnnaBridge	165:d1b4690b3f8b	384	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	385	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
AnnaBridge	165:d1b4690b3f8b	386
AnnaBridge	165:d1b4690b3f8b	387	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	388	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	165:d1b4690b3f8b	389	/**
AnnaBridge	165:d1b4690b3f8b	390	* @}
AnnaBridge	165:d1b4690b3f8b	391	*/
AnnaBridge	165:d1b4690b3f8b	392
AnnaBridge	165:d1b4690b3f8b	393	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
AnnaBridge	165:d1b4690b3f8b	394	* @{
AnnaBridge	165:d1b4690b3f8b	395	*/
AnnaBridge	165:d1b4690b3f8b	396	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	397	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
AnnaBridge	165:d1b4690b3f8b	398	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
AnnaBridge	165:d1b4690b3f8b	399
AnnaBridge	165:d1b4690b3f8b	400	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
AnnaBridge	165:d1b4690b3f8b	401	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
AnnaBridge	165:d1b4690b3f8b	402	((WIDE) == SDMMC_BUS_WIDE_8B))
AnnaBridge	165:d1b4690b3f8b	403	/**
AnnaBridge	165:d1b4690b3f8b	404	* @}
AnnaBridge	165:d1b4690b3f8b	405	*/
AnnaBridge	165:d1b4690b3f8b	406
AnnaBridge	165:d1b4690b3f8b	407	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	165:d1b4690b3f8b	408	* @{
AnnaBridge	165:d1b4690b3f8b	409	*/
AnnaBridge	165:d1b4690b3f8b	410	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	411	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
AnnaBridge	165:d1b4690b3f8b	412
AnnaBridge	165:d1b4690b3f8b	413	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	414	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	165:d1b4690b3f8b	415	/**
AnnaBridge	165:d1b4690b3f8b	416	* @}
AnnaBridge	165:d1b4690b3f8b	417	*/
AnnaBridge	165:d1b4690b3f8b	418
AnnaBridge	165:d1b4690b3f8b	419	/** @defgroup SDMMC_LL_Clock_Division Clock Division
AnnaBridge	165:d1b4690b3f8b	420	* @{
AnnaBridge	165:d1b4690b3f8b	421	*/
AnnaBridge	165:d1b4690b3f8b	422	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	423	/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
AnnaBridge	165:d1b4690b3f8b	424	#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400)
AnnaBridge	165:d1b4690b3f8b	425	#else
AnnaBridge	165:d1b4690b3f8b	426	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
AnnaBridge	165:d1b4690b3f8b	427	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	428	/**
AnnaBridge	165:d1b4690b3f8b	429	* @}
AnnaBridge	165:d1b4690b3f8b	430	*/
AnnaBridge	165:d1b4690b3f8b	431
AnnaBridge	165:d1b4690b3f8b	432
AnnaBridge	165:d1b4690b3f8b	433	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	434	/** @defgroup SDMMC_LL_Transceiver Transceiver
AnnaBridge	165:d1b4690b3f8b	435	* @{
AnnaBridge	165:d1b4690b3f8b	436	*/
AnnaBridge	165:d1b4690b3f8b	437	#define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	438	#define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U)
AnnaBridge	165:d1b4690b3f8b	439
AnnaBridge	165:d1b4690b3f8b	440	#define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	441	((MODE) == SDMMC_TRANSCEIVER_ENABLE))
AnnaBridge	165:d1b4690b3f8b	442	/**
AnnaBridge	165:d1b4690b3f8b	443	* @}
AnnaBridge	165:d1b4690b3f8b	444	*/
AnnaBridge	165:d1b4690b3f8b	445	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	446
AnnaBridge	165:d1b4690b3f8b	447	/** @defgroup SDMMC_LL_Command_Index Command Index
AnnaBridge	165:d1b4690b3f8b	448	* @{
AnnaBridge	165:d1b4690b3f8b	449	*/
AnnaBridge	165:d1b4690b3f8b	450	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
AnnaBridge	165:d1b4690b3f8b	451	/**
AnnaBridge	165:d1b4690b3f8b	452	* @}
AnnaBridge	165:d1b4690b3f8b	453	*/
AnnaBridge	165:d1b4690b3f8b	454
AnnaBridge	165:d1b4690b3f8b	455	/** @defgroup SDMMC_LL_Response_Type Response Type
AnnaBridge	165:d1b4690b3f8b	456	* @{
AnnaBridge	165:d1b4690b3f8b	457	*/
AnnaBridge	165:d1b4690b3f8b	458	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	459	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
AnnaBridge	165:d1b4690b3f8b	460	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
AnnaBridge	165:d1b4690b3f8b	461
AnnaBridge	165:d1b4690b3f8b	462	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
AnnaBridge	165:d1b4690b3f8b	463	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
AnnaBridge	165:d1b4690b3f8b	464	((RESPONSE) == SDMMC_RESPONSE_LONG))
AnnaBridge	165:d1b4690b3f8b	465	/**
AnnaBridge	165:d1b4690b3f8b	466	* @}
AnnaBridge	165:d1b4690b3f8b	467	*/
AnnaBridge	165:d1b4690b3f8b	468
AnnaBridge	165:d1b4690b3f8b	469	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	165:d1b4690b3f8b	470	* @{
AnnaBridge	165:d1b4690b3f8b	471	*/
AnnaBridge	165:d1b4690b3f8b	472	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	473	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
AnnaBridge	165:d1b4690b3f8b	474	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
AnnaBridge	165:d1b4690b3f8b	475
AnnaBridge	165:d1b4690b3f8b	476	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
AnnaBridge	165:d1b4690b3f8b	477	((WAIT) == SDMMC_WAIT_IT) \|\| \
AnnaBridge	165:d1b4690b3f8b	478	((WAIT) == SDMMC_WAIT_PEND))
AnnaBridge	165:d1b4690b3f8b	479	/**
AnnaBridge	165:d1b4690b3f8b	480	* @}
AnnaBridge	165:d1b4690b3f8b	481	*/
AnnaBridge	165:d1b4690b3f8b	482
AnnaBridge	165:d1b4690b3f8b	483	/** @defgroup SDMMC_LL_CPSM_State CPSM State
AnnaBridge	165:d1b4690b3f8b	484	* @{
AnnaBridge	165:d1b4690b3f8b	485	*/
AnnaBridge	165:d1b4690b3f8b	486	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	487	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
AnnaBridge	165:d1b4690b3f8b	488
AnnaBridge	165:d1b4690b3f8b	489	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	490	((CPSM) == SDMMC_CPSM_ENABLE))
AnnaBridge	165:d1b4690b3f8b	491	/**
AnnaBridge	165:d1b4690b3f8b	492	* @}
AnnaBridge	165:d1b4690b3f8b	493	*/
AnnaBridge	165:d1b4690b3f8b	494
AnnaBridge	165:d1b4690b3f8b	495	/** @defgroup SDMMC_LL_Response_Registers Response Register
AnnaBridge	165:d1b4690b3f8b	496	* @{
AnnaBridge	165:d1b4690b3f8b	497	*/
AnnaBridge	165:d1b4690b3f8b	498	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	499	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge	165:d1b4690b3f8b	500	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge	165:d1b4690b3f8b	501	#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
AnnaBridge	165:d1b4690b3f8b	502
AnnaBridge	165:d1b4690b3f8b	503	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
AnnaBridge	165:d1b4690b3f8b	504	((RESP) == SDMMC_RESP2) \|\| \
AnnaBridge	165:d1b4690b3f8b	505	((RESP) == SDMMC_RESP3) \|\| \
AnnaBridge	165:d1b4690b3f8b	506	((RESP) == SDMMC_RESP4))
AnnaBridge	165:d1b4690b3f8b	507
AnnaBridge	165:d1b4690b3f8b	508	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	509	/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
AnnaBridge	165:d1b4690b3f8b	510	* @{
AnnaBridge	165:d1b4690b3f8b	511	*/
AnnaBridge	165:d1b4690b3f8b	512	#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
AnnaBridge	165:d1b4690b3f8b	513	#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
AnnaBridge	165:d1b4690b3f8b	514	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE)
AnnaBridge	165:d1b4690b3f8b	515	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE \| SDMMC_IDMA_IDMABACT)
AnnaBridge	165:d1b4690b3f8b	516
AnnaBridge	165:d1b4690b3f8b	517	/**
AnnaBridge	165:d1b4690b3f8b	518	* @}
AnnaBridge	165:d1b4690b3f8b	519	*/
AnnaBridge	165:d1b4690b3f8b	520	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	521	/**
AnnaBridge	165:d1b4690b3f8b	522	* @}
AnnaBridge	165:d1b4690b3f8b	523	*/
AnnaBridge	165:d1b4690b3f8b	524
AnnaBridge	165:d1b4690b3f8b	525	/** @defgroup SDMMC_LL_Data_Length Data Lenght
AnnaBridge	165:d1b4690b3f8b	526	* @{
AnnaBridge	165:d1b4690b3f8b	527	*/
AnnaBridge	165:d1b4690b3f8b	528	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
AnnaBridge	165:d1b4690b3f8b	529	/**
AnnaBridge	165:d1b4690b3f8b	530	* @}
AnnaBridge	165:d1b4690b3f8b	531	*/
AnnaBridge	165:d1b4690b3f8b	532
AnnaBridge	165:d1b4690b3f8b	533	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
AnnaBridge	165:d1b4690b3f8b	534	* @{
AnnaBridge	165:d1b4690b3f8b	535	*/
AnnaBridge	165:d1b4690b3f8b	536	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	537	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
AnnaBridge	165:d1b4690b3f8b	538	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
AnnaBridge	165:d1b4690b3f8b	539	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
AnnaBridge	165:d1b4690b3f8b	540	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
AnnaBridge	165:d1b4690b3f8b	541	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	165:d1b4690b3f8b	542	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	165:d1b4690b3f8b	543	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	165:d1b4690b3f8b	544	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
AnnaBridge	165:d1b4690b3f8b	545	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	546	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	547	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	548	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	549	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	550	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	165:d1b4690b3f8b	551
AnnaBridge	165:d1b4690b3f8b	552	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	165:d1b4690b3f8b	553	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	165:d1b4690b3f8b	554	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	165:d1b4690b3f8b	555	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	165:d1b4690b3f8b	556	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	165:d1b4690b3f8b	557	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	165:d1b4690b3f8b	558	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	165:d1b4690b3f8b	559	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	165:d1b4690b3f8b	560	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	165:d1b4690b3f8b	561	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	165:d1b4690b3f8b	562	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	165:d1b4690b3f8b	563	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	165:d1b4690b3f8b	564	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	165:d1b4690b3f8b	565	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	165:d1b4690b3f8b	566	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
AnnaBridge	165:d1b4690b3f8b	567	/**
AnnaBridge	165:d1b4690b3f8b	568	* @}
AnnaBridge	165:d1b4690b3f8b	569	*/
AnnaBridge	165:d1b4690b3f8b	570
AnnaBridge	165:d1b4690b3f8b	571	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
AnnaBridge	165:d1b4690b3f8b	572	* @{
AnnaBridge	165:d1b4690b3f8b	573	*/
AnnaBridge	165:d1b4690b3f8b	574	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	575	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
AnnaBridge	165:d1b4690b3f8b	576
AnnaBridge	165:d1b4690b3f8b	577	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	165:d1b4690b3f8b	578	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
AnnaBridge	165:d1b4690b3f8b	579	/**
AnnaBridge	165:d1b4690b3f8b	580	* @}
AnnaBridge	165:d1b4690b3f8b	581	*/
AnnaBridge	165:d1b4690b3f8b	582
AnnaBridge	165:d1b4690b3f8b	583	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
AnnaBridge	165:d1b4690b3f8b	584	* @{
AnnaBridge	165:d1b4690b3f8b	585	*/
AnnaBridge	165:d1b4690b3f8b	586	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	587	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	588	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
AnnaBridge	165:d1b4690b3f8b	589	#else
AnnaBridge	165:d1b4690b3f8b	590	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
AnnaBridge	165:d1b4690b3f8b	591	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	592
AnnaBridge	165:d1b4690b3f8b	593	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	165:d1b4690b3f8b	594	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
AnnaBridge	165:d1b4690b3f8b	595	/**
AnnaBridge	165:d1b4690b3f8b	596	* @}
AnnaBridge	165:d1b4690b3f8b	597	*/
AnnaBridge	165:d1b4690b3f8b	598
AnnaBridge	165:d1b4690b3f8b	599	/** @defgroup SDMMC_LL_DPSM_State DPSM State
AnnaBridge	165:d1b4690b3f8b	600	* @{
AnnaBridge	165:d1b4690b3f8b	601	*/
AnnaBridge	165:d1b4690b3f8b	602	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	603	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
AnnaBridge	165:d1b4690b3f8b	604
AnnaBridge	165:d1b4690b3f8b	605	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
AnnaBridge	165:d1b4690b3f8b	606	((DPSM) == SDMMC_DPSM_ENABLE))
AnnaBridge	165:d1b4690b3f8b	607	/**
AnnaBridge	165:d1b4690b3f8b	608	* @}
AnnaBridge	165:d1b4690b3f8b	609	*/
AnnaBridge	165:d1b4690b3f8b	610
AnnaBridge	165:d1b4690b3f8b	611	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	165:d1b4690b3f8b	612	* @{
AnnaBridge	165:d1b4690b3f8b	613	*/
AnnaBridge	165:d1b4690b3f8b	614	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
AnnaBridge	165:d1b4690b3f8b	615	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
AnnaBridge	165:d1b4690b3f8b	616
AnnaBridge	165:d1b4690b3f8b	617	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	165:d1b4690b3f8b	618	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
AnnaBridge	165:d1b4690b3f8b	619	/**
AnnaBridge	165:d1b4690b3f8b	620	* @}
AnnaBridge	165:d1b4690b3f8b	621	*/
AnnaBridge	165:d1b4690b3f8b	622
AnnaBridge	165:d1b4690b3f8b	623	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
AnnaBridge	165:d1b4690b3f8b	624	* @{
AnnaBridge	165:d1b4690b3f8b	625	*/
AnnaBridge	165:d1b4690b3f8b	626	#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
AnnaBridge	165:d1b4690b3f8b	627	#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
AnnaBridge	165:d1b4690b3f8b	628	#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
AnnaBridge	165:d1b4690b3f8b	629	#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
AnnaBridge	165:d1b4690b3f8b	630	#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
AnnaBridge	165:d1b4690b3f8b	631	#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
AnnaBridge	165:d1b4690b3f8b	632	#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
AnnaBridge	165:d1b4690b3f8b	633	#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
AnnaBridge	165:d1b4690b3f8b	634	#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
AnnaBridge	165:d1b4690b3f8b	635	#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
AnnaBridge	165:d1b4690b3f8b	636	#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
AnnaBridge	165:d1b4690b3f8b	637	#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
AnnaBridge	165:d1b4690b3f8b	638	#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
AnnaBridge	165:d1b4690b3f8b	639	#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
AnnaBridge	165:d1b4690b3f8b	640	#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
AnnaBridge	165:d1b4690b3f8b	641	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	642	#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
AnnaBridge	165:d1b4690b3f8b	643	#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
AnnaBridge	165:d1b4690b3f8b	644	#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
AnnaBridge	165:d1b4690b3f8b	645	#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
AnnaBridge	165:d1b4690b3f8b	646	#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
AnnaBridge	165:d1b4690b3f8b	647	#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
AnnaBridge	165:d1b4690b3f8b	648	#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
AnnaBridge	165:d1b4690b3f8b	649	#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
AnnaBridge	165:d1b4690b3f8b	650	#else
AnnaBridge	165:d1b4690b3f8b	651	#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
AnnaBridge	165:d1b4690b3f8b	652	#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
AnnaBridge	165:d1b4690b3f8b	653	#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
AnnaBridge	165:d1b4690b3f8b	654	#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
AnnaBridge	165:d1b4690b3f8b	655	#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
AnnaBridge	165:d1b4690b3f8b	656	#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
AnnaBridge	165:d1b4690b3f8b	657	#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
AnnaBridge	165:d1b4690b3f8b	658	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	659	/**
AnnaBridge	165:d1b4690b3f8b	660	* @}
AnnaBridge	165:d1b4690b3f8b	661	*/
AnnaBridge	165:d1b4690b3f8b	662
AnnaBridge	165:d1b4690b3f8b	663	/** @defgroup SDMMC_LL_Flags Flags
AnnaBridge	165:d1b4690b3f8b	664	* @{
AnnaBridge	165:d1b4690b3f8b	665	*/
AnnaBridge	165:d1b4690b3f8b	666	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge	165:d1b4690b3f8b	667	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge	165:d1b4690b3f8b	668	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge	165:d1b4690b3f8b	669	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge	165:d1b4690b3f8b	670	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge	165:d1b4690b3f8b	671	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge	165:d1b4690b3f8b	672	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
AnnaBridge	165:d1b4690b3f8b	673	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge	165:d1b4690b3f8b	674	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
AnnaBridge	165:d1b4690b3f8b	675	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge	165:d1b4690b3f8b	676	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge	165:d1b4690b3f8b	677	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge	165:d1b4690b3f8b	678	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge	165:d1b4690b3f8b	679	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge	165:d1b4690b3f8b	680	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge	165:d1b4690b3f8b	681	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	165:d1b4690b3f8b	682	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	165:d1b4690b3f8b	683	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	684	#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
AnnaBridge	165:d1b4690b3f8b	685	#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
AnnaBridge	165:d1b4690b3f8b	686	#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
AnnaBridge	165:d1b4690b3f8b	687	#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
AnnaBridge	165:d1b4690b3f8b	688	#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
AnnaBridge	165:d1b4690b3f8b	689	#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
AnnaBridge	165:d1b4690b3f8b	690	#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
AnnaBridge	165:d1b4690b3f8b	691	#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
AnnaBridge	165:d1b4690b3f8b	692	#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
AnnaBridge	165:d1b4690b3f8b	693	#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
AnnaBridge	165:d1b4690b3f8b	694	#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
AnnaBridge	165:d1b4690b3f8b	695	#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
AnnaBridge	165:d1b4690b3f8b	696	#else
AnnaBridge	165:d1b4690b3f8b	697	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
AnnaBridge	165:d1b4690b3f8b	698	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
AnnaBridge	165:d1b4690b3f8b	699	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
AnnaBridge	165:d1b4690b3f8b	700	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
AnnaBridge	165:d1b4690b3f8b	701	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge	165:d1b4690b3f8b	702	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	703
AnnaBridge	165:d1b4690b3f8b	704	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	705	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	165:d1b4690b3f8b	706	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	165:d1b4690b3f8b	707	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	165:d1b4690b3f8b	708	SDMMC_FLAG_DHOLD \| SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \|\
AnnaBridge	165:d1b4690b3f8b	709	SDMMC_FLAG_BUSYD0END \| SDMMC_FLAG_SDIOIT \| SDMMC_FLAG_ACKFAIL \|\
AnnaBridge	165:d1b4690b3f8b	710	SDMMC_FLAG_ACKTIMEOUT \| SDMMC_FLAG_VSWEND \| SDMMC_FLAG_CKSTOP \|\
AnnaBridge	165:d1b4690b3f8b	711	SDMMC_FLAG_IDMATE \| SDMMC_FLAG_IDMABTC))
AnnaBridge	165:d1b4690b3f8b	712
AnnaBridge	165:d1b4690b3f8b	713	#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_CTIMEOUT \| SDMMC_FLAG_CMDREND \|\
AnnaBridge	165:d1b4690b3f8b	714	SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_BUSYD0END))
AnnaBridge	165:d1b4690b3f8b	715
AnnaBridge	165:d1b4690b3f8b	716	#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \|\
AnnaBridge	165:d1b4690b3f8b	717	SDMMC_FLAG_RXOVERR \| SDMMC_FLAG_DATAEND \| SDMMC_FLAG_DHOLD \|\
AnnaBridge	165:d1b4690b3f8b	718	SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \| SDMMC_FLAG_IDMATE \|\
AnnaBridge	165:d1b4690b3f8b	719	SDMMC_FLAG_IDMABTC))
AnnaBridge	165:d1b4690b3f8b	720
AnnaBridge	165:d1b4690b3f8b	721	#else
AnnaBridge	165:d1b4690b3f8b	722	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	165:d1b4690b3f8b	723	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	165:d1b4690b3f8b	724	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	165:d1b4690b3f8b	725	SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_SDIOIT))
AnnaBridge	165:d1b4690b3f8b	726
AnnaBridge	165:d1b4690b3f8b	727	#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_CTIMEOUT \| SDMMC_FLAG_CMDREND \|\
AnnaBridge	165:d1b4690b3f8b	728	SDMMC_FLAG_CMDSENT))
AnnaBridge	165:d1b4690b3f8b	729
AnnaBridge	165:d1b4690b3f8b	730	#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \|\
AnnaBridge	165:d1b4690b3f8b	731	SDMMC_FLAG_RXOVERR \| SDMMC_FLAG_DATAEND \| SDMMC_FLAG_DBCKEND))
AnnaBridge	165:d1b4690b3f8b	732	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	733
AnnaBridge	165:d1b4690b3f8b	734	/**
AnnaBridge	165:d1b4690b3f8b	735	* @}
AnnaBridge	165:d1b4690b3f8b	736	*/
AnnaBridge	165:d1b4690b3f8b	737
AnnaBridge	165:d1b4690b3f8b	738	/**
AnnaBridge	165:d1b4690b3f8b	739	* @}
AnnaBridge	165:d1b4690b3f8b	740	*/
AnnaBridge	165:d1b4690b3f8b	741
AnnaBridge	165:d1b4690b3f8b	742	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	743	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
AnnaBridge	165:d1b4690b3f8b	744	* @{
AnnaBridge	165:d1b4690b3f8b	745	*/
AnnaBridge	165:d1b4690b3f8b	746
AnnaBridge	165:d1b4690b3f8b	747	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
AnnaBridge	165:d1b4690b3f8b	748	* @brief SDMMC_LL registers bit address in the alias region
AnnaBridge	165:d1b4690b3f8b	749	* @{
AnnaBridge	165:d1b4690b3f8b	750	*/
AnnaBridge	165:d1b4690b3f8b	751	/* ---------------------- SDMMC registers bit mask --------------------------- */
AnnaBridge	165:d1b4690b3f8b	752	/* --- CLKCR Register ---*/
AnnaBridge	165:d1b4690b3f8b	753	/* CLKCR register clear mask */
AnnaBridge	165:d1b4690b3f8b	754	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	755	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	165:d1b4690b3f8b	756	SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	165:d1b4690b3f8b	757	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
AnnaBridge	165:d1b4690b3f8b	758	#else
AnnaBridge	165:d1b4690b3f8b	759	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	165:d1b4690b3f8b	760	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	165:d1b4690b3f8b	761	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
AnnaBridge	165:d1b4690b3f8b	762	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	763
AnnaBridge	165:d1b4690b3f8b	764	/* --- DCTRL Register ---*/
AnnaBridge	165:d1b4690b3f8b	765	/* SDMMC DCTRL Clear Mask */
AnnaBridge	165:d1b4690b3f8b	766	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
AnnaBridge	165:d1b4690b3f8b	767	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
AnnaBridge	165:d1b4690b3f8b	768
AnnaBridge	165:d1b4690b3f8b	769	/* --- CMD Register ---*/
AnnaBridge	165:d1b4690b3f8b	770	/* CMD Register clear mask */
AnnaBridge	165:d1b4690b3f8b	771	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	772	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	165:d1b4690b3f8b	773	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	165:d1b4690b3f8b	774	SDMMC_CMD_CPSMEN \| SDMMC_CMD_CMDSUSPEND))
AnnaBridge	165:d1b4690b3f8b	775	#else
AnnaBridge	165:d1b4690b3f8b	776	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	165:d1b4690b3f8b	777	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	165:d1b4690b3f8b	778	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
AnnaBridge	165:d1b4690b3f8b	779	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	780
AnnaBridge	165:d1b4690b3f8b	781	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	782	/* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge	165:d1b4690b3f8b	783	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */
AnnaBridge	165:d1b4690b3f8b	784
AnnaBridge	165:d1b4690b3f8b	785	/* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge	165:d1b4690b3f8b	786	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */
AnnaBridge	165:d1b4690b3f8b	787	#else
AnnaBridge	165:d1b4690b3f8b	788	/* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge	165:d1b4690b3f8b	789	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
AnnaBridge	165:d1b4690b3f8b	790
AnnaBridge	165:d1b4690b3f8b	791	/* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge	165:d1b4690b3f8b	792	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
AnnaBridge	165:d1b4690b3f8b	793	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	794
AnnaBridge	165:d1b4690b3f8b	795	/**
AnnaBridge	165:d1b4690b3f8b	796	* @}
AnnaBridge	165:d1b4690b3f8b	797	*/
AnnaBridge	165:d1b4690b3f8b	798
AnnaBridge	165:d1b4690b3f8b	799	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	165:d1b4690b3f8b	800	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	165:d1b4690b3f8b	801	* @{
AnnaBridge	165:d1b4690b3f8b	802	*/
AnnaBridge	165:d1b4690b3f8b	803
AnnaBridge	165:d1b4690b3f8b	804	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	805	/**
AnnaBridge	165:d1b4690b3f8b	806	* @brief Enable the SDMMC device.
AnnaBridge	165:d1b4690b3f8b	807	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	165:d1b4690b3f8b	808	* @retval None
AnnaBridge	165:d1b4690b3f8b	809	*/
AnnaBridge	165:d1b4690b3f8b	810	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
AnnaBridge	165:d1b4690b3f8b	811
AnnaBridge	165:d1b4690b3f8b	812	/**
AnnaBridge	165:d1b4690b3f8b	813	* @brief Disable the SDMMC device.
AnnaBridge	165:d1b4690b3f8b	814	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	165:d1b4690b3f8b	815	* @retval None
AnnaBridge	165:d1b4690b3f8b	816	*/
AnnaBridge	165:d1b4690b3f8b	817	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
AnnaBridge	165:d1b4690b3f8b	818
AnnaBridge	165:d1b4690b3f8b	819	/**
AnnaBridge	165:d1b4690b3f8b	820	* @brief Enable the SDMMC DMA transfer.
AnnaBridge	165:d1b4690b3f8b	821	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	165:d1b4690b3f8b	822	* @retval None
AnnaBridge	165:d1b4690b3f8b	823	*/
AnnaBridge	165:d1b4690b3f8b	824	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
AnnaBridge	165:d1b4690b3f8b	825	/**
AnnaBridge	165:d1b4690b3f8b	826	* @brief Disable the SDMMC DMA transfer.
AnnaBridge	165:d1b4690b3f8b	827	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	165:d1b4690b3f8b	828	* @retval None
AnnaBridge	165:d1b4690b3f8b	829	*/
AnnaBridge	165:d1b4690b3f8b	830	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
AnnaBridge	165:d1b4690b3f8b	831	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	832
AnnaBridge	165:d1b4690b3f8b	833	/**
AnnaBridge	165:d1b4690b3f8b	834	* @brief Enable the SDMMC device interrupt.
AnnaBridge	165:d1b4690b3f8b	835	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	836	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
AnnaBridge	165:d1b4690b3f8b	837	* This parameter can be one or a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	838	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	839	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	840	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	165:d1b4690b3f8b	841	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	165:d1b4690b3f8b	842	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	165:d1b4690b3f8b	843	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	165:d1b4690b3f8b	844	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	845	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	165:d1b4690b3f8b	846	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	165:d1b4690b3f8b	847	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	848	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	165:d1b4690b3f8b	849	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	165:d1b4690b3f8b	850	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	165:d1b4690b3f8b	851	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	852	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	853	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	854	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	855	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	165:d1b4690b3f8b	856	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	165:d1b4690b3f8b	857	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	165:d1b4690b3f8b	858	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	165:d1b4690b3f8b	859	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	165:d1b4690b3f8b	860	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	165:d1b4690b3f8b	861	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	165:d1b4690b3f8b	862	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	165:d1b4690b3f8b	863	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	165:d1b4690b3f8b	864	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	165:d1b4690b3f8b	865	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	165:d1b4690b3f8b	866	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	867	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	868	* @retval None
AnnaBridge	165:d1b4690b3f8b	869	*/
AnnaBridge	165:d1b4690b3f8b	870	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	165:d1b4690b3f8b	871
AnnaBridge	165:d1b4690b3f8b	872	/**
AnnaBridge	165:d1b4690b3f8b	873	* @brief Disable the SDMMC device interrupt.
AnnaBridge	165:d1b4690b3f8b	874	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	875	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
AnnaBridge	165:d1b4690b3f8b	876	* This parameter can be one or a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	877	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	878	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	879	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	165:d1b4690b3f8b	880	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	165:d1b4690b3f8b	881	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	165:d1b4690b3f8b	882	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	165:d1b4690b3f8b	883	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	884	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	165:d1b4690b3f8b	885	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	165:d1b4690b3f8b	886	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	887	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	165:d1b4690b3f8b	888	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	165:d1b4690b3f8b	889	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	165:d1b4690b3f8b	890	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	891	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	892	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	893	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	894	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	165:d1b4690b3f8b	895	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	165:d1b4690b3f8b	896	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	165:d1b4690b3f8b	897	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	165:d1b4690b3f8b	898	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	165:d1b4690b3f8b	899	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	165:d1b4690b3f8b	900	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	165:d1b4690b3f8b	901	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	165:d1b4690b3f8b	902	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	165:d1b4690b3f8b	903	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	165:d1b4690b3f8b	904	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	165:d1b4690b3f8b	905	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	906	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	907	* @retval None
AnnaBridge	165:d1b4690b3f8b	908	*/
AnnaBridge	165:d1b4690b3f8b	909	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	165:d1b4690b3f8b	910
AnnaBridge	165:d1b4690b3f8b	911	/**
AnnaBridge	165:d1b4690b3f8b	912	* @brief Checks whether the specified SDMMC flag is set or not.
AnnaBridge	165:d1b4690b3f8b	913	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	914	* @param __FLAG__: specifies the flag to check.
AnnaBridge	165:d1b4690b3f8b	915	* This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	916	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	165:d1b4690b3f8b	917	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	165:d1b4690b3f8b	918	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	165:d1b4690b3f8b	919	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	165:d1b4690b3f8b	920	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	165:d1b4690b3f8b	921	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	165:d1b4690b3f8b	922	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	165:d1b4690b3f8b	923	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	165:d1b4690b3f8b	924	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	165:d1b4690b3f8b	925	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	165:d1b4690b3f8b	926	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
AnnaBridge	165:d1b4690b3f8b	927	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	165:d1b4690b3f8b	928	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	165:d1b4690b3f8b	929	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	165:d1b4690b3f8b	930	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	165:d1b4690b3f8b	931	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	165:d1b4690b3f8b	932	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	165:d1b4690b3f8b	933	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	165:d1b4690b3f8b	934	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	165:d1b4690b3f8b	935	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	165:d1b4690b3f8b	936	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	165:d1b4690b3f8b	937	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	165:d1b4690b3f8b	938	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	165:d1b4690b3f8b	939	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	165:d1b4690b3f8b	940	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	165:d1b4690b3f8b	941	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	165:d1b4690b3f8b	942	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	165:d1b4690b3f8b	943	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
AnnaBridge	165:d1b4690b3f8b	944	* @arg SDMMC_FLAG_RXACT: Data receive in progress
AnnaBridge	165:d1b4690b3f8b	945	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	165:d1b4690b3f8b	946	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	165:d1b4690b3f8b	947	* @retval The new state of SDMMC_FLAG (SET or RESET).
AnnaBridge	165:d1b4690b3f8b	948	*/
AnnaBridge	165:d1b4690b3f8b	949	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	165:d1b4690b3f8b	950
AnnaBridge	165:d1b4690b3f8b	951
AnnaBridge	165:d1b4690b3f8b	952	/**
AnnaBridge	165:d1b4690b3f8b	953	* @brief Clears the SDMMC pending flags.
AnnaBridge	165:d1b4690b3f8b	954	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	955	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	165:d1b4690b3f8b	956	* This parameter can be one or a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	957	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	165:d1b4690b3f8b	958	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	165:d1b4690b3f8b	959	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	165:d1b4690b3f8b	960	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	165:d1b4690b3f8b	961	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	165:d1b4690b3f8b	962	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	165:d1b4690b3f8b	963	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	165:d1b4690b3f8b	964	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	165:d1b4690b3f8b	965	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	165:d1b4690b3f8b	966	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	165:d1b4690b3f8b	967	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	165:d1b4690b3f8b	968	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	165:d1b4690b3f8b	969	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	165:d1b4690b3f8b	970	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	165:d1b4690b3f8b	971	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	165:d1b4690b3f8b	972	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	165:d1b4690b3f8b	973	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	165:d1b4690b3f8b	974	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	165:d1b4690b3f8b	975	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	165:d1b4690b3f8b	976	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	165:d1b4690b3f8b	977	* @retval None
AnnaBridge	165:d1b4690b3f8b	978	*/
AnnaBridge	165:d1b4690b3f8b	979	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	165:d1b4690b3f8b	980
AnnaBridge	165:d1b4690b3f8b	981	/**
AnnaBridge	165:d1b4690b3f8b	982	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
AnnaBridge	165:d1b4690b3f8b	983	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	984	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
AnnaBridge	165:d1b4690b3f8b	985	* This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	986	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	987	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	988	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	165:d1b4690b3f8b	989	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	165:d1b4690b3f8b	990	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	165:d1b4690b3f8b	991	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	165:d1b4690b3f8b	992	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	993	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	165:d1b4690b3f8b	994	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	165:d1b4690b3f8b	995	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	996	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	165:d1b4690b3f8b	997	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	165:d1b4690b3f8b	998	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	165:d1b4690b3f8b	999	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	1000	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	165:d1b4690b3f8b	1001	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	1002	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	165:d1b4690b3f8b	1003	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	165:d1b4690b3f8b	1004	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	165:d1b4690b3f8b	1005	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	165:d1b4690b3f8b	1006	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	165:d1b4690b3f8b	1007	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	165:d1b4690b3f8b	1008	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	165:d1b4690b3f8b	1009	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	165:d1b4690b3f8b	1010	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	165:d1b4690b3f8b	1011	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	165:d1b4690b3f8b	1012	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	165:d1b4690b3f8b	1013	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	165:d1b4690b3f8b	1014	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	1015	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	165:d1b4690b3f8b	1016	* @retval The new state of SDMMC_IT (SET or RESET).
AnnaBridge	165:d1b4690b3f8b	1017	*/
AnnaBridge	165:d1b4690b3f8b	1018	#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	165:d1b4690b3f8b	1019
AnnaBridge	165:d1b4690b3f8b	1020	/**
AnnaBridge	165:d1b4690b3f8b	1021	* @brief Clears the SDMMC's interrupt pending bits.
AnnaBridge	165:d1b4690b3f8b	1022	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1023	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	165:d1b4690b3f8b	1024	* This parameter can be one or a combination of the following values:
AnnaBridge	165:d1b4690b3f8b	1025	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	1026	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	165:d1b4690b3f8b	1027	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	165:d1b4690b3f8b	1028	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	165:d1b4690b3f8b	1029	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	165:d1b4690b3f8b	1030	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	165:d1b4690b3f8b	1031	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	165:d1b4690b3f8b	1032	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	165:d1b4690b3f8b	1033	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
AnnaBridge	165:d1b4690b3f8b	1034	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	165:d1b4690b3f8b	1035	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	165:d1b4690b3f8b	1036	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	165:d1b4690b3f8b	1037	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	165:d1b4690b3f8b	1038	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	165:d1b4690b3f8b	1039	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	165:d1b4690b3f8b	1040	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	165:d1b4690b3f8b	1041	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	165:d1b4690b3f8b	1042	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	165:d1b4690b3f8b	1043	* @retval None
AnnaBridge	165:d1b4690b3f8b	1044	*/
AnnaBridge	165:d1b4690b3f8b	1045	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	165:d1b4690b3f8b	1046
AnnaBridge	165:d1b4690b3f8b	1047	/**
AnnaBridge	165:d1b4690b3f8b	1048	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	165:d1b4690b3f8b	1049	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1050	* @retval None
AnnaBridge	165:d1b4690b3f8b	1051	*/
AnnaBridge	165:d1b4690b3f8b	1052	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
AnnaBridge	165:d1b4690b3f8b	1053
AnnaBridge	165:d1b4690b3f8b	1054	/**
AnnaBridge	165:d1b4690b3f8b	1055	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	165:d1b4690b3f8b	1056	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1057	* @retval None
AnnaBridge	165:d1b4690b3f8b	1058	*/
AnnaBridge	165:d1b4690b3f8b	1059	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
AnnaBridge	165:d1b4690b3f8b	1060
AnnaBridge	165:d1b4690b3f8b	1061	/**
AnnaBridge	165:d1b4690b3f8b	1062	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	165:d1b4690b3f8b	1063	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1064	* @retval None
AnnaBridge	165:d1b4690b3f8b	1065	*/
AnnaBridge	165:d1b4690b3f8b	1066	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
AnnaBridge	165:d1b4690b3f8b	1067
AnnaBridge	165:d1b4690b3f8b	1068	/**
AnnaBridge	165:d1b4690b3f8b	1069	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	165:d1b4690b3f8b	1070	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1071	* @retval None
AnnaBridge	165:d1b4690b3f8b	1072	*/
AnnaBridge	165:d1b4690b3f8b	1073	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
AnnaBridge	165:d1b4690b3f8b	1074
AnnaBridge	165:d1b4690b3f8b	1075	/**
AnnaBridge	165:d1b4690b3f8b	1076	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	165:d1b4690b3f8b	1077	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1078	* @retval None
AnnaBridge	165:d1b4690b3f8b	1079	*/
AnnaBridge	165:d1b4690b3f8b	1080	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
AnnaBridge	165:d1b4690b3f8b	1081
AnnaBridge	165:d1b4690b3f8b	1082	/**
AnnaBridge	165:d1b4690b3f8b	1083	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	165:d1b4690b3f8b	1084	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1085	* @retval None
AnnaBridge	165:d1b4690b3f8b	1086	*/
AnnaBridge	165:d1b4690b3f8b	1087	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
AnnaBridge	165:d1b4690b3f8b	1088
AnnaBridge	165:d1b4690b3f8b	1089	/**
AnnaBridge	165:d1b4690b3f8b	1090	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	165:d1b4690b3f8b	1091	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1092	* @retval None
AnnaBridge	165:d1b4690b3f8b	1093	*/
AnnaBridge	165:d1b4690b3f8b	1094	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1095	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	165:d1b4690b3f8b	1096	#else
AnnaBridge	165:d1b4690b3f8b	1097	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDSUSPEND)
AnnaBridge	165:d1b4690b3f8b	1098	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	1099
AnnaBridge	165:d1b4690b3f8b	1100	/**
AnnaBridge	165:d1b4690b3f8b	1101	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	165:d1b4690b3f8b	1102	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1103	* @retval None
AnnaBridge	165:d1b4690b3f8b	1104	*/
AnnaBridge	165:d1b4690b3f8b	1105	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1106	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	165:d1b4690b3f8b	1107	#else
AnnaBridge	165:d1b4690b3f8b	1108	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
AnnaBridge	165:d1b4690b3f8b	1109	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	1110
AnnaBridge	165:d1b4690b3f8b	1111	/**
AnnaBridge	165:d1b4690b3f8b	1112	* @brief Enable the CMDTRANS mode.
AnnaBridge	165:d1b4690b3f8b	1113	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1114	* @retval None
AnnaBridge	165:d1b4690b3f8b	1115	*/
AnnaBridge	165:d1b4690b3f8b	1116	#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDTRANS)
AnnaBridge	165:d1b4690b3f8b	1117
AnnaBridge	165:d1b4690b3f8b	1118	/**
AnnaBridge	165:d1b4690b3f8b	1119	* @brief Disable the CMDTRANS mode.
AnnaBridge	165:d1b4690b3f8b	1120	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	165:d1b4690b3f8b	1121	* @retval None
AnnaBridge	165:d1b4690b3f8b	1122	*/
AnnaBridge	165:d1b4690b3f8b	1123	#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
AnnaBridge	165:d1b4690b3f8b	1124	/**
AnnaBridge	165:d1b4690b3f8b	1125	* @}
AnnaBridge	165:d1b4690b3f8b	1126	*/
AnnaBridge	165:d1b4690b3f8b	1127
AnnaBridge	165:d1b4690b3f8b	1128	/**
AnnaBridge	165:d1b4690b3f8b	1129	* @}
AnnaBridge	165:d1b4690b3f8b	1130	*/
AnnaBridge	165:d1b4690b3f8b	1131
AnnaBridge	165:d1b4690b3f8b	1132	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1133	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	165:d1b4690b3f8b	1134	* @{
AnnaBridge	165:d1b4690b3f8b	1135	*/
AnnaBridge	165:d1b4690b3f8b	1136
AnnaBridge	165:d1b4690b3f8b	1137	/* Initialization/de-initialization functions **********************************/
AnnaBridge	165:d1b4690b3f8b	1138	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	165:d1b4690b3f8b	1139	* @{
AnnaBridge	165:d1b4690b3f8b	1140	*/
AnnaBridge	165:d1b4690b3f8b	1141	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
AnnaBridge	165:d1b4690b3f8b	1142	/**
AnnaBridge	165:d1b4690b3f8b	1143	* @}
AnnaBridge	165:d1b4690b3f8b	1144	*/
AnnaBridge	165:d1b4690b3f8b	1145
AnnaBridge	165:d1b4690b3f8b	1146	/* I/O operation functions *****************************************************/
AnnaBridge	165:d1b4690b3f8b	1147	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	165:d1b4690b3f8b	1148	* @{
AnnaBridge	165:d1b4690b3f8b	1149	*/
AnnaBridge	165:d1b4690b3f8b	1150	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1151	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
AnnaBridge	165:d1b4690b3f8b	1152	/**
AnnaBridge	165:d1b4690b3f8b	1153	* @}
AnnaBridge	165:d1b4690b3f8b	1154	*/
AnnaBridge	165:d1b4690b3f8b	1155
AnnaBridge	165:d1b4690b3f8b	1156	/* Peripheral Control functions ************************************************/
AnnaBridge	165:d1b4690b3f8b	1157	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	165:d1b4690b3f8b	1158	* @{
AnnaBridge	165:d1b4690b3f8b	1159	*/
AnnaBridge	165:d1b4690b3f8b	1160	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1161	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1162	HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1163	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	1164	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1165	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1166
AnnaBridge	165:d1b4690b3f8b	1167	/* Command path state machine (CPSM) management functions */
AnnaBridge	165:d1b4690b3f8b	1168	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
AnnaBridge	165:d1b4690b3f8b	1169	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1170	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
AnnaBridge	165:d1b4690b3f8b	1171
AnnaBridge	165:d1b4690b3f8b	1172	/* Data path state machine (DPSM) management functions */
AnnaBridge	165:d1b4690b3f8b	1173	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
AnnaBridge	165:d1b4690b3f8b	1174	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1175	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1176
AnnaBridge	165:d1b4690b3f8b	1177	/* SDMMC Cards mode management functions */
AnnaBridge	165:d1b4690b3f8b	1178	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
AnnaBridge	165:d1b4690b3f8b	1179
AnnaBridge	165:d1b4690b3f8b	1180	/* SDMMC Commands management functions */
AnnaBridge	165:d1b4690b3f8b	1181	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge	165:d1b4690b3f8b	1182	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	165:d1b4690b3f8b	1183	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	165:d1b4690b3f8b	1184	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	165:d1b4690b3f8b	1185	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	165:d1b4690b3f8b	1186	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	165:d1b4690b3f8b	1187	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	165:d1b4690b3f8b	1188	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	165:d1b4690b3f8b	1189	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	165:d1b4690b3f8b	1190	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1191	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1192	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge	165:d1b4690b3f8b	1193	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1194	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1195	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1196	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1197	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge	165:d1b4690b3f8b	1198	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1199	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1200	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1201	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
AnnaBridge	165:d1b4690b3f8b	1202	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1203	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1204	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1205	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	165:d1b4690b3f8b	1206	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1207	uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
AnnaBridge	165:d1b4690b3f8b	1208	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	165:d1b4690b3f8b	1209
AnnaBridge	165:d1b4690b3f8b	1210	/**
AnnaBridge	165:d1b4690b3f8b	1211	* @}
AnnaBridge	165:d1b4690b3f8b	1212	*/
AnnaBridge	165:d1b4690b3f8b	1213
AnnaBridge	165:d1b4690b3f8b	1214	/**
AnnaBridge	165:d1b4690b3f8b	1215	* @}
AnnaBridge	165:d1b4690b3f8b	1216	*/
AnnaBridge	165:d1b4690b3f8b	1217
AnnaBridge	165:d1b4690b3f8b	1218	/**
AnnaBridge	165:d1b4690b3f8b	1219	* @}
AnnaBridge	165:d1b4690b3f8b	1220	*/
AnnaBridge	165:d1b4690b3f8b	1221
AnnaBridge	165:d1b4690b3f8b	1222	/**
AnnaBridge	165:d1b4690b3f8b	1223	* @}
AnnaBridge	165:d1b4690b3f8b	1224	*/
AnnaBridge	165:d1b4690b3f8b	1225
AnnaBridge	165:d1b4690b3f8b	1226	#endif /* SDMMC1 */
AnnaBridge	165:d1b4690b3f8b	1227
AnnaBridge	165:d1b4690b3f8b	1228	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	1229	}
AnnaBridge	165:d1b4690b3f8b	1230	#endif
AnnaBridge	165:d1b4690b3f8b	1231
AnnaBridge	165:d1b4690b3f8b	1232	#endif /* __STM32L4xx_LL_SDMMC_H */
AnnaBridge	165:d1b4690b3f8b	1233
AnnaBridge	165:d1b4690b3f8b	1234	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/