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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_pwr_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_hal_pwr_ex.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of PWR HAL Extended module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_HAL_PWR_EX_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_HAL_PWR_EX_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	165:d1b4690b3f8b	48	* @{
AnnaBridge	165:d1b4690b3f8b	49	*/
AnnaBridge	165:d1b4690b3f8b	50
AnnaBridge	165:d1b4690b3f8b	51	/** @addtogroup PWREx
AnnaBridge	165:d1b4690b3f8b	52	* @{
AnnaBridge	165:d1b4690b3f8b	53	*/
AnnaBridge	165:d1b4690b3f8b	54
AnnaBridge	165:d1b4690b3f8b	55
AnnaBridge	165:d1b4690b3f8b	56	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	57
AnnaBridge	165:d1b4690b3f8b	58	/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
AnnaBridge	165:d1b4690b3f8b	59	* @{
AnnaBridge	165:d1b4690b3f8b	60	*/
AnnaBridge	165:d1b4690b3f8b	61
AnnaBridge	165:d1b4690b3f8b	62
AnnaBridge	165:d1b4690b3f8b	63	/**
AnnaBridge	165:d1b4690b3f8b	64	* @brief PWR PVM configuration structure definition
AnnaBridge	165:d1b4690b3f8b	65	*/
AnnaBridge	165:d1b4690b3f8b	66	typedef struct
AnnaBridge	165:d1b4690b3f8b	67	{
AnnaBridge	165:d1b4690b3f8b	68	uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
AnnaBridge	165:d1b4690b3f8b	69	This parameter can be a value of @ref PWREx_PVM_Type.
AnnaBridge	165:d1b4690b3f8b	70	@arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
AnnaBridge	165:d1b4690b3f8b	71	@if STM32L486xx
AnnaBridge	165:d1b4690b3f8b	72	@arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
AnnaBridge	165:d1b4690b3f8b	73	@endif
AnnaBridge	165:d1b4690b3f8b	74	@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
AnnaBridge	165:d1b4690b3f8b	75	@arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
AnnaBridge	165:d1b4690b3f8b	76
AnnaBridge	165:d1b4690b3f8b	77	uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
AnnaBridge	165:d1b4690b3f8b	78	This parameter can be a value of @ref PWREx_PVM_Mode. */
AnnaBridge	165:d1b4690b3f8b	79	}PWR_PVMTypeDef;
AnnaBridge	165:d1b4690b3f8b	80
AnnaBridge	165:d1b4690b3f8b	81	/**
AnnaBridge	165:d1b4690b3f8b	82	* @}
AnnaBridge	165:d1b4690b3f8b	83	*/
AnnaBridge	165:d1b4690b3f8b	84
AnnaBridge	165:d1b4690b3f8b	85	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	86
AnnaBridge	165:d1b4690b3f8b	87	/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
AnnaBridge	165:d1b4690b3f8b	88	* @{
AnnaBridge	165:d1b4690b3f8b	89	*/
AnnaBridge	165:d1b4690b3f8b	90
AnnaBridge	165:d1b4690b3f8b	91	/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
AnnaBridge	165:d1b4690b3f8b	92	* @{
AnnaBridge	165:d1b4690b3f8b	93	*/
AnnaBridge	165:d1b4690b3f8b	94	#define PWR_WUP_POLARITY_SHIFT 0x05 /!< Internal constant used to retrieve wakeup pin polariry /
AnnaBridge	165:d1b4690b3f8b	95	/**
AnnaBridge	165:d1b4690b3f8b	96	* @}
AnnaBridge	165:d1b4690b3f8b	97	*/
AnnaBridge	165:d1b4690b3f8b	98
AnnaBridge	165:d1b4690b3f8b	99
AnnaBridge	165:d1b4690b3f8b	100	/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
AnnaBridge	165:d1b4690b3f8b	101	* @{
AnnaBridge	165:d1b4690b3f8b	102	*/
AnnaBridge	165:d1b4690b3f8b	103	#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /!< Wakeup pin 1 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	104	#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /!< Wakeup pin 2 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	105	#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /!< Wakeup pin 3 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	106	#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /!< Wakeup pin 4 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	107	#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /!< Wakeup pin 5 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	108	#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /!< Wakeup pin 1 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	109	#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /!< Wakeup pin 2 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	110	#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /!< Wakeup pin 3 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	111	#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /!< Wakeup pin 4 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	112	#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /!< Wakeup pin 5 (with high level polarity) /
AnnaBridge	165:d1b4690b3f8b	113	#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) \| PWR_CR3_EWUP1) /!< Wakeup pin 1 (with low level polarity) /
AnnaBridge	165:d1b4690b3f8b	114	#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) \| PWR_CR3_EWUP2) /!< Wakeup pin 2 (with low level polarity) /
AnnaBridge	165:d1b4690b3f8b	115	#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) \| PWR_CR3_EWUP3) /!< Wakeup pin 3 (with low level polarity) /
AnnaBridge	165:d1b4690b3f8b	116	#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) \| PWR_CR3_EWUP4) /!< Wakeup pin 4 (with low level polarity) /
AnnaBridge	165:d1b4690b3f8b	117	#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) \| PWR_CR3_EWUP5) /!< Wakeup pin 5 (with low level polarity) /
AnnaBridge	165:d1b4690b3f8b	118	/**
AnnaBridge	165:d1b4690b3f8b	119	* @}
AnnaBridge	165:d1b4690b3f8b	120	*/
AnnaBridge	165:d1b4690b3f8b	121
AnnaBridge	165:d1b4690b3f8b	122	/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
AnnaBridge	165:d1b4690b3f8b	123	* @{
AnnaBridge	165:d1b4690b3f8b	124	*/
AnnaBridge	165:d1b4690b3f8b	125	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	126	#define PWR_PVM_1 PWR_CR2_PVME1 /!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) /
AnnaBridge	165:d1b4690b3f8b	127	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	128	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	129	#define PWR_PVM_2 PWR_CR2_PVME2 /!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) /
AnnaBridge	165:d1b4690b3f8b	130	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	131	#define PWR_PVM_3 PWR_CR2_PVME3 /!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V /
AnnaBridge	165:d1b4690b3f8b	132	#define PWR_PVM_4 PWR_CR2_PVME4 /!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V /
AnnaBridge	165:d1b4690b3f8b	133	/**
AnnaBridge	165:d1b4690b3f8b	134	* @}
AnnaBridge	165:d1b4690b3f8b	135	*/
AnnaBridge	165:d1b4690b3f8b	136
AnnaBridge	165:d1b4690b3f8b	137	/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
AnnaBridge	165:d1b4690b3f8b	138	* @{
AnnaBridge	165:d1b4690b3f8b	139	*/
AnnaBridge	165:d1b4690b3f8b	140	#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /!< basic mode is used /
AnnaBridge	165:d1b4690b3f8b	141	#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /!< External Interrupt Mode with Rising edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	142	#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /!< External Interrupt Mode with Falling edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	143	#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /!< External Interrupt Mode with Rising/Falling edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	144	#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /!< Event Mode with Rising edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	145	#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /!< Event Mode with Falling edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	146	#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /!< Event Mode with Rising/Falling edge trigger detection /
AnnaBridge	165:d1b4690b3f8b	147	/**
AnnaBridge	165:d1b4690b3f8b	148	* @}
AnnaBridge	165:d1b4690b3f8b	149	*/
AnnaBridge	165:d1b4690b3f8b	150
AnnaBridge	165:d1b4690b3f8b	151
AnnaBridge	165:d1b4690b3f8b	152
AnnaBridge	165:d1b4690b3f8b	153	/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
AnnaBridge	165:d1b4690b3f8b	154	* @{
AnnaBridge	165:d1b4690b3f8b	155	*/
AnnaBridge	165:d1b4690b3f8b	156	#if defined(PWR_CR5_R1MODE)
AnnaBridge	165:d1b4690b3f8b	157	#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /!< Voltage scaling range 1 boost mode /
AnnaBridge	165:d1b4690b3f8b	158	#endif
AnnaBridge	165:d1b4690b3f8b	159	#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /!< Voltage scaling range 1 normal mode /
AnnaBridge	165:d1b4690b3f8b	160	#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /!< Voltage scaling range 2 /
AnnaBridge	165:d1b4690b3f8b	161	/**
AnnaBridge	165:d1b4690b3f8b	162	* @}
AnnaBridge	165:d1b4690b3f8b	163	*/
AnnaBridge	165:d1b4690b3f8b	164
AnnaBridge	165:d1b4690b3f8b	165
AnnaBridge	165:d1b4690b3f8b	166	/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
AnnaBridge	165:d1b4690b3f8b	167	* @{
AnnaBridge	165:d1b4690b3f8b	168	*/
AnnaBridge	165:d1b4690b3f8b	169	#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /!< VBAT charging through a 5 kOhms resistor /
AnnaBridge	165:d1b4690b3f8b	170	#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /!< VBAT charging through a 1.5 kOhms resistor /
AnnaBridge	165:d1b4690b3f8b	171	/**
AnnaBridge	165:d1b4690b3f8b	172	* @}
AnnaBridge	165:d1b4690b3f8b	173	*/
AnnaBridge	165:d1b4690b3f8b	174
AnnaBridge	165:d1b4690b3f8b	175	/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
AnnaBridge	165:d1b4690b3f8b	176	* @{
AnnaBridge	165:d1b4690b3f8b	177	*/
AnnaBridge	165:d1b4690b3f8b	178	#define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
AnnaBridge	165:d1b4690b3f8b	179	#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
AnnaBridge	165:d1b4690b3f8b	180	/**
AnnaBridge	165:d1b4690b3f8b	181	* @}
AnnaBridge	165:d1b4690b3f8b	182	*/
AnnaBridge	165:d1b4690b3f8b	183
AnnaBridge	165:d1b4690b3f8b	184	/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
AnnaBridge	165:d1b4690b3f8b	185	* @{
AnnaBridge	165:d1b4690b3f8b	186	*/
AnnaBridge	165:d1b4690b3f8b	187	#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /!< GPIO port I/O pin 0 /
AnnaBridge	165:d1b4690b3f8b	188	#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /!< GPIO port I/O pin 1 /
AnnaBridge	165:d1b4690b3f8b	189	#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /!< GPIO port I/O pin 2 /
AnnaBridge	165:d1b4690b3f8b	190	#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /!< GPIO port I/O pin 3 /
AnnaBridge	165:d1b4690b3f8b	191	#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /!< GPIO port I/O pin 4 /
AnnaBridge	165:d1b4690b3f8b	192	#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /!< GPIO port I/O pin 5 /
AnnaBridge	165:d1b4690b3f8b	193	#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /!< GPIO port I/O pin 6 /
AnnaBridge	165:d1b4690b3f8b	194	#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /!< GPIO port I/O pin 7 /
AnnaBridge	165:d1b4690b3f8b	195	#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /!< GPIO port I/O pin 8 /
AnnaBridge	165:d1b4690b3f8b	196	#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /!< GPIO port I/O pin 9 /
AnnaBridge	165:d1b4690b3f8b	197	#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /!< GPIO port I/O pin 10 /
AnnaBridge	165:d1b4690b3f8b	198	#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /!< GPIO port I/O pin 11 /
AnnaBridge	165:d1b4690b3f8b	199	#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /!< GPIO port I/O pin 12 /
AnnaBridge	165:d1b4690b3f8b	200	#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /!< GPIO port I/O pin 13 /
AnnaBridge	165:d1b4690b3f8b	201	#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /!< GPIO port I/O pin 14 /
AnnaBridge	165:d1b4690b3f8b	202	#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /!< GPIO port I/O pin 15 /
AnnaBridge	165:d1b4690b3f8b	203	/**
AnnaBridge	165:d1b4690b3f8b	204	* @}
AnnaBridge	165:d1b4690b3f8b	205	*/
AnnaBridge	165:d1b4690b3f8b	206
AnnaBridge	165:d1b4690b3f8b	207	/** @defgroup PWREx_GPIO GPIO port
AnnaBridge	165:d1b4690b3f8b	208	* @{
AnnaBridge	165:d1b4690b3f8b	209	*/
AnnaBridge	165:d1b4690b3f8b	210	#define PWR_GPIO_A 0x00000000 /!< GPIO port A /
AnnaBridge	165:d1b4690b3f8b	211	#define PWR_GPIO_B 0x00000001 /!< GPIO port B /
AnnaBridge	165:d1b4690b3f8b	212	#define PWR_GPIO_C 0x00000002 /!< GPIO port C /
AnnaBridge	165:d1b4690b3f8b	213	#if defined(GPIOD_BASE)
AnnaBridge	165:d1b4690b3f8b	214	#define PWR_GPIO_D 0x00000003 /!< GPIO port D /
AnnaBridge	165:d1b4690b3f8b	215	#endif
AnnaBridge	165:d1b4690b3f8b	216	#if defined(GPIOE_BASE)
AnnaBridge	165:d1b4690b3f8b	217	#define PWR_GPIO_E 0x00000004 /!< GPIO port E /
AnnaBridge	165:d1b4690b3f8b	218	#endif
AnnaBridge	165:d1b4690b3f8b	219	#if defined(GPIOF_BASE)
AnnaBridge	165:d1b4690b3f8b	220	#define PWR_GPIO_F 0x00000005 /!< GPIO port F /
AnnaBridge	165:d1b4690b3f8b	221	#endif
AnnaBridge	165:d1b4690b3f8b	222	#if defined(GPIOG_BASE)
AnnaBridge	165:d1b4690b3f8b	223	#define PWR_GPIO_G 0x00000006 /!< GPIO port G /
AnnaBridge	165:d1b4690b3f8b	224	#endif
AnnaBridge	165:d1b4690b3f8b	225	#define PWR_GPIO_H 0x00000007 /!< GPIO port H /
AnnaBridge	165:d1b4690b3f8b	226	#if defined(GPIOI_BASE)
AnnaBridge	165:d1b4690b3f8b	227	#define PWR_GPIO_I 0x00000008 /!< GPIO port I /
AnnaBridge	165:d1b4690b3f8b	228	#endif
AnnaBridge	165:d1b4690b3f8b	229	/**
AnnaBridge	165:d1b4690b3f8b	230	* @}
AnnaBridge	165:d1b4690b3f8b	231	*/
AnnaBridge	165:d1b4690b3f8b	232
AnnaBridge	165:d1b4690b3f8b	233	/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
AnnaBridge	165:d1b4690b3f8b	234	* @{
AnnaBridge	165:d1b4690b3f8b	235	*/
AnnaBridge	165:d1b4690b3f8b	236	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	237	#define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /!< External interrupt line 35 Connected to the PVM1 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	238	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	239	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	240	#define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /!< External interrupt line 36 Connected to the PVM2 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	241	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	242	#define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /!< External interrupt line 37 Connected to the PVM3 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	243	#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /!< External interrupt line 38 Connected to the PVM4 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	244	/**
AnnaBridge	165:d1b4690b3f8b	245	* @}
AnnaBridge	165:d1b4690b3f8b	246	*/
AnnaBridge	165:d1b4690b3f8b	247
AnnaBridge	165:d1b4690b3f8b	248	/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
AnnaBridge	165:d1b4690b3f8b	249	* @{
AnnaBridge	165:d1b4690b3f8b	250	*/
AnnaBridge	165:d1b4690b3f8b	251	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	252	#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /!< Event line 35 Connected to the PVM1 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	253	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	254	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	255	#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /!< Event line 36 Connected to the PVM2 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	256	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	257	#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /!< Event line 37 Connected to the PVM3 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	258	#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /!< Event line 38 Connected to the PVM4 EXTI Line /
AnnaBridge	165:d1b4690b3f8b	259	/**
AnnaBridge	165:d1b4690b3f8b	260	* @}
AnnaBridge	165:d1b4690b3f8b	261	*/
AnnaBridge	165:d1b4690b3f8b	262
AnnaBridge	165:d1b4690b3f8b	263	/** @defgroup PWREx_Flag PWR Status Flags
AnnaBridge	165:d1b4690b3f8b	264	* Elements values convention: 0000 0000 0XXY YYYYb
AnnaBridge	165:d1b4690b3f8b	265	* - Y YYYY : Flag position in the XX register (5 bits)
AnnaBridge	165:d1b4690b3f8b	266	* - XX : Status register (2 bits)
AnnaBridge	165:d1b4690b3f8b	267	* - 01: SR1 register
AnnaBridge	165:d1b4690b3f8b	268	* - 10: SR2 register
AnnaBridge	165:d1b4690b3f8b	269	* The only exception is PWR_FLAG_WU, encompassing all
AnnaBridge	165:d1b4690b3f8b	270	* wake-up flags and set to PWR_SR1_WUF.
AnnaBridge	165:d1b4690b3f8b	271	* @{
AnnaBridge	165:d1b4690b3f8b	272	*/
AnnaBridge	165:d1b4690b3f8b	273	#define PWR_FLAG_WUF1 ((uint32_t)0x0020) /!< Wakeup event on wakeup pin 1 /
AnnaBridge	165:d1b4690b3f8b	274	#define PWR_FLAG_WUF2 ((uint32_t)0x0021) /!< Wakeup event on wakeup pin 2 /
AnnaBridge	165:d1b4690b3f8b	275	#define PWR_FLAG_WUF3 ((uint32_t)0x0022) /!< Wakeup event on wakeup pin 3 /
AnnaBridge	165:d1b4690b3f8b	276	#define PWR_FLAG_WUF4 ((uint32_t)0x0023) /!< Wakeup event on wakeup pin 4 /
AnnaBridge	165:d1b4690b3f8b	277	#define PWR_FLAG_WUF5 ((uint32_t)0x0024) /!< Wakeup event on wakeup pin 5 /
AnnaBridge	165:d1b4690b3f8b	278	#define PWR_FLAG_WU PWR_SR1_WUF /!< Encompass wakeup event on all wakeup pins /
AnnaBridge	165:d1b4690b3f8b	279	#define PWR_FLAG_SB ((uint32_t)0x0028) /!< Standby flag /
AnnaBridge	165:d1b4690b3f8b	280	#define PWR_FLAG_WUFI ((uint32_t)0x002F) /!< Wakeup on internal wakeup line /
AnnaBridge	165:d1b4690b3f8b	281
AnnaBridge	165:d1b4690b3f8b	282	#define PWR_FLAG_REGLPS ((uint32_t)0x0048) /!< Low-power regulator start flag /
AnnaBridge	165:d1b4690b3f8b	283	#define PWR_FLAG_REGLPF ((uint32_t)0x0049) /!< Low-power regulator flag /
AnnaBridge	165:d1b4690b3f8b	284	#define PWR_FLAG_VOSF ((uint32_t)0x004A) /!< Voltage scaling flag /
AnnaBridge	165:d1b4690b3f8b	285	#define PWR_FLAG_PVDO ((uint32_t)0x004B) /!< Power Voltage Detector output flag /
AnnaBridge	165:d1b4690b3f8b	286	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	287	#define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /!< Power Voltage Monitoring 1 output flag /
AnnaBridge	165:d1b4690b3f8b	288	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	289	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	290	#define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /!< Power Voltage Monitoring 2 output flag /
AnnaBridge	165:d1b4690b3f8b	291	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	292	#define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /!< Power Voltage Monitoring 3 output flag /
AnnaBridge	165:d1b4690b3f8b	293	#define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /!< Power Voltage Monitoring 4 output flag /
AnnaBridge	165:d1b4690b3f8b	294	/**
AnnaBridge	165:d1b4690b3f8b	295	* @}
AnnaBridge	165:d1b4690b3f8b	296	*/
AnnaBridge	165:d1b4690b3f8b	297
AnnaBridge	165:d1b4690b3f8b	298	/**
AnnaBridge	165:d1b4690b3f8b	299	* @}
AnnaBridge	165:d1b4690b3f8b	300	*/
AnnaBridge	165:d1b4690b3f8b	301
AnnaBridge	165:d1b4690b3f8b	302	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	303	/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
AnnaBridge	165:d1b4690b3f8b	304	* @{
AnnaBridge	165:d1b4690b3f8b	305	*/
AnnaBridge	165:d1b4690b3f8b	306
AnnaBridge	165:d1b4690b3f8b	307	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	308	/**
AnnaBridge	165:d1b4690b3f8b	309	* @brief Enable the PVM1 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	310	* @retval None
AnnaBridge	165:d1b4690b3f8b	311	*/
AnnaBridge	165:d1b4690b3f8b	312	#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	313
AnnaBridge	165:d1b4690b3f8b	314	/**
AnnaBridge	165:d1b4690b3f8b	315	* @brief Disable the PVM1 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	316	* @retval None
AnnaBridge	165:d1b4690b3f8b	317	*/
AnnaBridge	165:d1b4690b3f8b	318	#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	319
AnnaBridge	165:d1b4690b3f8b	320	/**
AnnaBridge	165:d1b4690b3f8b	321	* @brief Enable the PVM1 Event Line.
AnnaBridge	165:d1b4690b3f8b	322	* @retval None
AnnaBridge	165:d1b4690b3f8b	323	*/
AnnaBridge	165:d1b4690b3f8b	324	#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	325
AnnaBridge	165:d1b4690b3f8b	326	/**
AnnaBridge	165:d1b4690b3f8b	327	* @brief Disable the PVM1 Event Line.
AnnaBridge	165:d1b4690b3f8b	328	* @retval None
AnnaBridge	165:d1b4690b3f8b	329	*/
AnnaBridge	165:d1b4690b3f8b	330	#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	331
AnnaBridge	165:d1b4690b3f8b	332	/**
AnnaBridge	165:d1b4690b3f8b	333	* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	334	* @retval None
AnnaBridge	165:d1b4690b3f8b	335	*/
AnnaBridge	165:d1b4690b3f8b	336	#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	337
AnnaBridge	165:d1b4690b3f8b	338	/**
AnnaBridge	165:d1b4690b3f8b	339	* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	340	* @retval None
AnnaBridge	165:d1b4690b3f8b	341	*/
AnnaBridge	165:d1b4690b3f8b	342	#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	343
AnnaBridge	165:d1b4690b3f8b	344	/**
AnnaBridge	165:d1b4690b3f8b	345	* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	346	* @retval None
AnnaBridge	165:d1b4690b3f8b	347	*/
AnnaBridge	165:d1b4690b3f8b	348	#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	349
AnnaBridge	165:d1b4690b3f8b	350
AnnaBridge	165:d1b4690b3f8b	351	/**
AnnaBridge	165:d1b4690b3f8b	352	* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	353	* @retval None
AnnaBridge	165:d1b4690b3f8b	354	*/
AnnaBridge	165:d1b4690b3f8b	355	#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	356
AnnaBridge	165:d1b4690b3f8b	357
AnnaBridge	165:d1b4690b3f8b	358	/**
AnnaBridge	165:d1b4690b3f8b	359	* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
AnnaBridge	165:d1b4690b3f8b	360	* @retval None
AnnaBridge	165:d1b4690b3f8b	361	*/
AnnaBridge	165:d1b4690b3f8b	362	#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	363	do { \
AnnaBridge	165:d1b4690b3f8b	364	__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	365	__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	366	} while(0)
AnnaBridge	165:d1b4690b3f8b	367
AnnaBridge	165:d1b4690b3f8b	368	/**
AnnaBridge	165:d1b4690b3f8b	369	* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	370	* @retval None
AnnaBridge	165:d1b4690b3f8b	371	*/
AnnaBridge	165:d1b4690b3f8b	372	#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	373	do { \
AnnaBridge	165:d1b4690b3f8b	374	__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	375	__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	376	} while(0)
AnnaBridge	165:d1b4690b3f8b	377
AnnaBridge	165:d1b4690b3f8b	378	/**
AnnaBridge	165:d1b4690b3f8b	379	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	165:d1b4690b3f8b	380	* @retval None
AnnaBridge	165:d1b4690b3f8b	381	*/
AnnaBridge	165:d1b4690b3f8b	382	#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	383
AnnaBridge	165:d1b4690b3f8b	384	/**
AnnaBridge	165:d1b4690b3f8b	385	* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
AnnaBridge	165:d1b4690b3f8b	386	* @retval EXTI PVM1 Line Status.
AnnaBridge	165:d1b4690b3f8b	387	*/
AnnaBridge	165:d1b4690b3f8b	388	#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	389
AnnaBridge	165:d1b4690b3f8b	390	/**
AnnaBridge	165:d1b4690b3f8b	391	* @brief Clear the PVM1 EXTI flag.
AnnaBridge	165:d1b4690b3f8b	392	* @retval None
AnnaBridge	165:d1b4690b3f8b	393	*/
AnnaBridge	165:d1b4690b3f8b	394	#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
AnnaBridge	165:d1b4690b3f8b	395
AnnaBridge	165:d1b4690b3f8b	396	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	397
AnnaBridge	165:d1b4690b3f8b	398
AnnaBridge	165:d1b4690b3f8b	399	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	400	/**
AnnaBridge	165:d1b4690b3f8b	401	* @brief Enable the PVM2 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	402	* @retval None
AnnaBridge	165:d1b4690b3f8b	403	*/
AnnaBridge	165:d1b4690b3f8b	404	#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	405
AnnaBridge	165:d1b4690b3f8b	406	/**
AnnaBridge	165:d1b4690b3f8b	407	* @brief Disable the PVM2 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	408	* @retval None
AnnaBridge	165:d1b4690b3f8b	409	*/
AnnaBridge	165:d1b4690b3f8b	410	#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	411
AnnaBridge	165:d1b4690b3f8b	412	/**
AnnaBridge	165:d1b4690b3f8b	413	* @brief Enable the PVM2 Event Line.
AnnaBridge	165:d1b4690b3f8b	414	* @retval None
AnnaBridge	165:d1b4690b3f8b	415	*/
AnnaBridge	165:d1b4690b3f8b	416	#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	417
AnnaBridge	165:d1b4690b3f8b	418	/**
AnnaBridge	165:d1b4690b3f8b	419	* @brief Disable the PVM2 Event Line.
AnnaBridge	165:d1b4690b3f8b	420	* @retval None
AnnaBridge	165:d1b4690b3f8b	421	*/
AnnaBridge	165:d1b4690b3f8b	422	#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	423
AnnaBridge	165:d1b4690b3f8b	424	/**
AnnaBridge	165:d1b4690b3f8b	425	* @brief Enable the PVM2 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	426	* @retval None
AnnaBridge	165:d1b4690b3f8b	427	*/
AnnaBridge	165:d1b4690b3f8b	428	#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	429
AnnaBridge	165:d1b4690b3f8b	430	/**
AnnaBridge	165:d1b4690b3f8b	431	* @brief Disable the PVM2 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	432	* @retval None
AnnaBridge	165:d1b4690b3f8b	433	*/
AnnaBridge	165:d1b4690b3f8b	434	#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	435
AnnaBridge	165:d1b4690b3f8b	436	/**
AnnaBridge	165:d1b4690b3f8b	437	* @brief Enable the PVM2 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	438	* @retval None
AnnaBridge	165:d1b4690b3f8b	439	*/
AnnaBridge	165:d1b4690b3f8b	440	#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	441
AnnaBridge	165:d1b4690b3f8b	442
AnnaBridge	165:d1b4690b3f8b	443	/**
AnnaBridge	165:d1b4690b3f8b	444	* @brief Disable the PVM2 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	445	* @retval None
AnnaBridge	165:d1b4690b3f8b	446	*/
AnnaBridge	165:d1b4690b3f8b	447	#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	448
AnnaBridge	165:d1b4690b3f8b	449
AnnaBridge	165:d1b4690b3f8b	450	/**
AnnaBridge	165:d1b4690b3f8b	451	* @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
AnnaBridge	165:d1b4690b3f8b	452	* @retval None
AnnaBridge	165:d1b4690b3f8b	453	*/
AnnaBridge	165:d1b4690b3f8b	454	#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	455	do { \
AnnaBridge	165:d1b4690b3f8b	456	__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	457	__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	458	} while(0)
AnnaBridge	165:d1b4690b3f8b	459
AnnaBridge	165:d1b4690b3f8b	460	/**
AnnaBridge	165:d1b4690b3f8b	461	* @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	462	* @retval None
AnnaBridge	165:d1b4690b3f8b	463	*/
AnnaBridge	165:d1b4690b3f8b	464	#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	465	do { \
AnnaBridge	165:d1b4690b3f8b	466	__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	467	__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	468	} while(0)
AnnaBridge	165:d1b4690b3f8b	469
AnnaBridge	165:d1b4690b3f8b	470	/**
AnnaBridge	165:d1b4690b3f8b	471	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	165:d1b4690b3f8b	472	* @retval None
AnnaBridge	165:d1b4690b3f8b	473	*/
AnnaBridge	165:d1b4690b3f8b	474	#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	475
AnnaBridge	165:d1b4690b3f8b	476	/**
AnnaBridge	165:d1b4690b3f8b	477	* @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
AnnaBridge	165:d1b4690b3f8b	478	* @retval EXTI PVM2 Line Status.
AnnaBridge	165:d1b4690b3f8b	479	*/
AnnaBridge	165:d1b4690b3f8b	480	#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	481
AnnaBridge	165:d1b4690b3f8b	482	/**
AnnaBridge	165:d1b4690b3f8b	483	* @brief Clear the PVM2 EXTI flag.
AnnaBridge	165:d1b4690b3f8b	484	* @retval None
AnnaBridge	165:d1b4690b3f8b	485	*/
AnnaBridge	165:d1b4690b3f8b	486	#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
AnnaBridge	165:d1b4690b3f8b	487
AnnaBridge	165:d1b4690b3f8b	488	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	489
AnnaBridge	165:d1b4690b3f8b	490
AnnaBridge	165:d1b4690b3f8b	491	/**
AnnaBridge	165:d1b4690b3f8b	492	* @brief Enable the PVM3 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	493	* @retval None
AnnaBridge	165:d1b4690b3f8b	494	*/
AnnaBridge	165:d1b4690b3f8b	495	#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	496
AnnaBridge	165:d1b4690b3f8b	497	/**
AnnaBridge	165:d1b4690b3f8b	498	* @brief Disable the PVM3 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	499	* @retval None
AnnaBridge	165:d1b4690b3f8b	500	*/
AnnaBridge	165:d1b4690b3f8b	501	#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	502
AnnaBridge	165:d1b4690b3f8b	503	/**
AnnaBridge	165:d1b4690b3f8b	504	* @brief Enable the PVM3 Event Line.
AnnaBridge	165:d1b4690b3f8b	505	* @retval None
AnnaBridge	165:d1b4690b3f8b	506	*/
AnnaBridge	165:d1b4690b3f8b	507	#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	508
AnnaBridge	165:d1b4690b3f8b	509	/**
AnnaBridge	165:d1b4690b3f8b	510	* @brief Disable the PVM3 Event Line.
AnnaBridge	165:d1b4690b3f8b	511	* @retval None
AnnaBridge	165:d1b4690b3f8b	512	*/
AnnaBridge	165:d1b4690b3f8b	513	#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	514
AnnaBridge	165:d1b4690b3f8b	515	/**
AnnaBridge	165:d1b4690b3f8b	516	* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	517	* @retval None
AnnaBridge	165:d1b4690b3f8b	518	*/
AnnaBridge	165:d1b4690b3f8b	519	#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	520
AnnaBridge	165:d1b4690b3f8b	521	/**
AnnaBridge	165:d1b4690b3f8b	522	* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	523	* @retval None
AnnaBridge	165:d1b4690b3f8b	524	*/
AnnaBridge	165:d1b4690b3f8b	525	#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	526
AnnaBridge	165:d1b4690b3f8b	527	/**
AnnaBridge	165:d1b4690b3f8b	528	* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	529	* @retval None
AnnaBridge	165:d1b4690b3f8b	530	*/
AnnaBridge	165:d1b4690b3f8b	531	#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	532
AnnaBridge	165:d1b4690b3f8b	533
AnnaBridge	165:d1b4690b3f8b	534	/**
AnnaBridge	165:d1b4690b3f8b	535	* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	536	* @retval None
AnnaBridge	165:d1b4690b3f8b	537	*/
AnnaBridge	165:d1b4690b3f8b	538	#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	539
AnnaBridge	165:d1b4690b3f8b	540
AnnaBridge	165:d1b4690b3f8b	541	/**
AnnaBridge	165:d1b4690b3f8b	542	* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
AnnaBridge	165:d1b4690b3f8b	543	* @retval None
AnnaBridge	165:d1b4690b3f8b	544	*/
AnnaBridge	165:d1b4690b3f8b	545	#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	546	do { \
AnnaBridge	165:d1b4690b3f8b	547	__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	548	__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	549	} while(0)
AnnaBridge	165:d1b4690b3f8b	550
AnnaBridge	165:d1b4690b3f8b	551	/**
AnnaBridge	165:d1b4690b3f8b	552	* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	553	* @retval None
AnnaBridge	165:d1b4690b3f8b	554	*/
AnnaBridge	165:d1b4690b3f8b	555	#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	556	do { \
AnnaBridge	165:d1b4690b3f8b	557	__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	558	__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	559	} while(0)
AnnaBridge	165:d1b4690b3f8b	560
AnnaBridge	165:d1b4690b3f8b	561	/**
AnnaBridge	165:d1b4690b3f8b	562	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	165:d1b4690b3f8b	563	* @retval None
AnnaBridge	165:d1b4690b3f8b	564	*/
AnnaBridge	165:d1b4690b3f8b	565	#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	566
AnnaBridge	165:d1b4690b3f8b	567	/**
AnnaBridge	165:d1b4690b3f8b	568	* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
AnnaBridge	165:d1b4690b3f8b	569	* @retval EXTI PVM3 Line Status.
AnnaBridge	165:d1b4690b3f8b	570	*/
AnnaBridge	165:d1b4690b3f8b	571	#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	572
AnnaBridge	165:d1b4690b3f8b	573	/**
AnnaBridge	165:d1b4690b3f8b	574	* @brief Clear the PVM3 EXTI flag.
AnnaBridge	165:d1b4690b3f8b	575	* @retval None
AnnaBridge	165:d1b4690b3f8b	576	*/
AnnaBridge	165:d1b4690b3f8b	577	#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
AnnaBridge	165:d1b4690b3f8b	578
AnnaBridge	165:d1b4690b3f8b	579
AnnaBridge	165:d1b4690b3f8b	580
AnnaBridge	165:d1b4690b3f8b	581
AnnaBridge	165:d1b4690b3f8b	582	/**
AnnaBridge	165:d1b4690b3f8b	583	* @brief Enable the PVM4 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	584	* @retval None
AnnaBridge	165:d1b4690b3f8b	585	*/
AnnaBridge	165:d1b4690b3f8b	586	#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	587
AnnaBridge	165:d1b4690b3f8b	588	/**
AnnaBridge	165:d1b4690b3f8b	589	* @brief Disable the PVM4 Extended Interrupt Line.
AnnaBridge	165:d1b4690b3f8b	590	* @retval None
AnnaBridge	165:d1b4690b3f8b	591	*/
AnnaBridge	165:d1b4690b3f8b	592	#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	593
AnnaBridge	165:d1b4690b3f8b	594	/**
AnnaBridge	165:d1b4690b3f8b	595	* @brief Enable the PVM4 Event Line.
AnnaBridge	165:d1b4690b3f8b	596	* @retval None
AnnaBridge	165:d1b4690b3f8b	597	*/
AnnaBridge	165:d1b4690b3f8b	598	#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	599
AnnaBridge	165:d1b4690b3f8b	600	/**
AnnaBridge	165:d1b4690b3f8b	601	* @brief Disable the PVM4 Event Line.
AnnaBridge	165:d1b4690b3f8b	602	* @retval None
AnnaBridge	165:d1b4690b3f8b	603	*/
AnnaBridge	165:d1b4690b3f8b	604	#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	605
AnnaBridge	165:d1b4690b3f8b	606	/**
AnnaBridge	165:d1b4690b3f8b	607	* @brief Enable the PVM4 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	608	* @retval None
AnnaBridge	165:d1b4690b3f8b	609	*/
AnnaBridge	165:d1b4690b3f8b	610	#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	611
AnnaBridge	165:d1b4690b3f8b	612	/**
AnnaBridge	165:d1b4690b3f8b	613	* @brief Disable the PVM4 Extended Interrupt Rising Trigger.
AnnaBridge	165:d1b4690b3f8b	614	* @retval None
AnnaBridge	165:d1b4690b3f8b	615	*/
AnnaBridge	165:d1b4690b3f8b	616	#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	617
AnnaBridge	165:d1b4690b3f8b	618	/**
AnnaBridge	165:d1b4690b3f8b	619	* @brief Enable the PVM4 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	620	* @retval None
AnnaBridge	165:d1b4690b3f8b	621	*/
AnnaBridge	165:d1b4690b3f8b	622	#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	623
AnnaBridge	165:d1b4690b3f8b	624
AnnaBridge	165:d1b4690b3f8b	625	/**
AnnaBridge	165:d1b4690b3f8b	626	* @brief Disable the PVM4 Extended Interrupt Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	627	* @retval None
AnnaBridge	165:d1b4690b3f8b	628	*/
AnnaBridge	165:d1b4690b3f8b	629	#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	630
AnnaBridge	165:d1b4690b3f8b	631
AnnaBridge	165:d1b4690b3f8b	632	/**
AnnaBridge	165:d1b4690b3f8b	633	* @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
AnnaBridge	165:d1b4690b3f8b	634	* @retval None
AnnaBridge	165:d1b4690b3f8b	635	*/
AnnaBridge	165:d1b4690b3f8b	636	#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	637	do { \
AnnaBridge	165:d1b4690b3f8b	638	__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	639	__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	640	} while(0)
AnnaBridge	165:d1b4690b3f8b	641
AnnaBridge	165:d1b4690b3f8b	642	/**
AnnaBridge	165:d1b4690b3f8b	643	* @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
AnnaBridge	165:d1b4690b3f8b	644	* @retval None
AnnaBridge	165:d1b4690b3f8b	645	*/
AnnaBridge	165:d1b4690b3f8b	646	#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	165:d1b4690b3f8b	647	do { \
AnnaBridge	165:d1b4690b3f8b	648	__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	649	__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	165:d1b4690b3f8b	650	} while(0)
AnnaBridge	165:d1b4690b3f8b	651
AnnaBridge	165:d1b4690b3f8b	652	/**
AnnaBridge	165:d1b4690b3f8b	653	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	165:d1b4690b3f8b	654	* @retval None
AnnaBridge	165:d1b4690b3f8b	655	*/
AnnaBridge	165:d1b4690b3f8b	656	#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	657
AnnaBridge	165:d1b4690b3f8b	658	/**
AnnaBridge	165:d1b4690b3f8b	659	* @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
AnnaBridge	165:d1b4690b3f8b	660	* @retval EXTI PVM4 Line Status.
AnnaBridge	165:d1b4690b3f8b	661	*/
AnnaBridge	165:d1b4690b3f8b	662	#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	663
AnnaBridge	165:d1b4690b3f8b	664	/**
AnnaBridge	165:d1b4690b3f8b	665	* @brief Clear the PVM4 EXTI flag.
AnnaBridge	165:d1b4690b3f8b	666	* @retval None
AnnaBridge	165:d1b4690b3f8b	667	*/
AnnaBridge	165:d1b4690b3f8b	668	#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
AnnaBridge	165:d1b4690b3f8b	669
AnnaBridge	165:d1b4690b3f8b	670
AnnaBridge	165:d1b4690b3f8b	671	/**
AnnaBridge	165:d1b4690b3f8b	672	* @brief Configure the main internal regulator output voltage.
AnnaBridge	165:d1b4690b3f8b	673	* @param __REGULATOR__: specifies the regulator output voltage to achieve
AnnaBridge	165:d1b4690b3f8b	674	* a tradeoff between performance and power consumption.
AnnaBridge	165:d1b4690b3f8b	675	* This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	676	* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
AnnaBridge	165:d1b4690b3f8b	677	* typical output voltage at 1.2 V,
AnnaBridge	165:d1b4690b3f8b	678	* system frequency up to 80 MHz.
AnnaBridge	165:d1b4690b3f8b	679	* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
AnnaBridge	165:d1b4690b3f8b	680	* typical output voltage at 1.0 V,
AnnaBridge	165:d1b4690b3f8b	681	* system frequency up to 26 MHz.
AnnaBridge	165:d1b4690b3f8b	682	* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
AnnaBridge	165:d1b4690b3f8b	683	* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
AnnaBridge	165:d1b4690b3f8b	684	* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
AnnaBridge	165:d1b4690b3f8b	685	* @retval None
AnnaBridge	165:d1b4690b3f8b	686	*/
AnnaBridge	165:d1b4690b3f8b	687	#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
AnnaBridge	165:d1b4690b3f8b	688	__IO uint32_t tmpreg; \
AnnaBridge	165:d1b4690b3f8b	689	MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
AnnaBridge	165:d1b4690b3f8b	690	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	165:d1b4690b3f8b	691	tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
AnnaBridge	165:d1b4690b3f8b	692	UNUSED(tmpreg); \
AnnaBridge	165:d1b4690b3f8b	693	} while(0)
AnnaBridge	165:d1b4690b3f8b	694
AnnaBridge	165:d1b4690b3f8b	695	/**
AnnaBridge	165:d1b4690b3f8b	696	* @}
AnnaBridge	165:d1b4690b3f8b	697	*/
AnnaBridge	165:d1b4690b3f8b	698
AnnaBridge	165:d1b4690b3f8b	699	/* Private macros --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	700	/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
AnnaBridge	165:d1b4690b3f8b	701	* @{
AnnaBridge	165:d1b4690b3f8b	702	*/
AnnaBridge	165:d1b4690b3f8b	703
AnnaBridge	165:d1b4690b3f8b	704	#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) \|\| \
AnnaBridge	165:d1b4690b3f8b	705	((PIN) == PWR_WAKEUP_PIN2) \|\| \
AnnaBridge	165:d1b4690b3f8b	706	((PIN) == PWR_WAKEUP_PIN3) \|\| \
AnnaBridge	165:d1b4690b3f8b	707	((PIN) == PWR_WAKEUP_PIN4) \|\| \
AnnaBridge	165:d1b4690b3f8b	708	((PIN) == PWR_WAKEUP_PIN5) \|\| \
AnnaBridge	165:d1b4690b3f8b	709	((PIN) == PWR_WAKEUP_PIN1_HIGH) \|\| \
AnnaBridge	165:d1b4690b3f8b	710	((PIN) == PWR_WAKEUP_PIN2_HIGH) \|\| \
AnnaBridge	165:d1b4690b3f8b	711	((PIN) == PWR_WAKEUP_PIN3_HIGH) \|\| \
AnnaBridge	165:d1b4690b3f8b	712	((PIN) == PWR_WAKEUP_PIN4_HIGH) \|\| \
AnnaBridge	165:d1b4690b3f8b	713	((PIN) == PWR_WAKEUP_PIN5_HIGH) \|\| \
AnnaBridge	165:d1b4690b3f8b	714	((PIN) == PWR_WAKEUP_PIN1_LOW) \|\| \
AnnaBridge	165:d1b4690b3f8b	715	((PIN) == PWR_WAKEUP_PIN2_LOW) \|\| \
AnnaBridge	165:d1b4690b3f8b	716	((PIN) == PWR_WAKEUP_PIN3_LOW) \|\| \
AnnaBridge	165:d1b4690b3f8b	717	((PIN) == PWR_WAKEUP_PIN4_LOW) \|\| \
AnnaBridge	165:d1b4690b3f8b	718	((PIN) == PWR_WAKEUP_PIN5_LOW))
AnnaBridge	165:d1b4690b3f8b	719
AnnaBridge	165:d1b4690b3f8b	720	#if defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	721	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	722	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	723	#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) \|\|\
AnnaBridge	165:d1b4690b3f8b	724	((TYPE) == PWR_PVM_2) \|\|\
AnnaBridge	165:d1b4690b3f8b	725	((TYPE) == PWR_PVM_3) \|\|\
AnnaBridge	165:d1b4690b3f8b	726	((TYPE) == PWR_PVM_4))
AnnaBridge	165:d1b4690b3f8b	727	#elif defined (STM32L471xx)
AnnaBridge	165:d1b4690b3f8b	728	#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) \|\|\
AnnaBridge	165:d1b4690b3f8b	729	((TYPE) == PWR_PVM_3) \|\|\
AnnaBridge	165:d1b4690b3f8b	730	((TYPE) == PWR_PVM_4))
AnnaBridge	165:d1b4690b3f8b	731	#endif
AnnaBridge	165:d1b4690b3f8b	732
AnnaBridge	165:d1b4690b3f8b	733	#if defined (STM32L433xx) \|\| defined (STM32L443xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	165:d1b4690b3f8b	734	#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) \|\|\
AnnaBridge	165:d1b4690b3f8b	735	((TYPE) == PWR_PVM_3) \|\|\
AnnaBridge	165:d1b4690b3f8b	736	((TYPE) == PWR_PVM_4))
AnnaBridge	165:d1b4690b3f8b	737	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L442xx) \|\| defined (STM32L451xx)
AnnaBridge	165:d1b4690b3f8b	738	#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) \|\|\
AnnaBridge	165:d1b4690b3f8b	739	((TYPE) == PWR_PVM_4))
AnnaBridge	165:d1b4690b3f8b	740	#endif
AnnaBridge	165:d1b4690b3f8b	741
AnnaBridge	165:d1b4690b3f8b	742	#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) \|\|\
AnnaBridge	165:d1b4690b3f8b	743	((MODE) == PWR_PVM_MODE_IT_RISING) \|\|\
AnnaBridge	165:d1b4690b3f8b	744	((MODE) == PWR_PVM_MODE_IT_FALLING) \|\|\
AnnaBridge	165:d1b4690b3f8b	745	((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) \|\|\
AnnaBridge	165:d1b4690b3f8b	746	((MODE) == PWR_PVM_MODE_EVENT_RISING) \|\|\
AnnaBridge	165:d1b4690b3f8b	747	((MODE) == PWR_PVM_MODE_EVENT_FALLING) \|\|\
AnnaBridge	165:d1b4690b3f8b	748	((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
AnnaBridge	165:d1b4690b3f8b	749
AnnaBridge	165:d1b4690b3f8b	750	#if defined(PWR_CR5_R1MODE)
AnnaBridge	165:d1b4690b3f8b	751	#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) \|\| \
AnnaBridge	165:d1b4690b3f8b	752	((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) \|\| \
AnnaBridge	165:d1b4690b3f8b	753	((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
AnnaBridge	165:d1b4690b3f8b	754	#else
AnnaBridge	165:d1b4690b3f8b	755	#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) \|\| \
AnnaBridge	165:d1b4690b3f8b	756	((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
AnnaBridge	165:d1b4690b3f8b	757	#endif
AnnaBridge	165:d1b4690b3f8b	758
AnnaBridge	165:d1b4690b3f8b	759
AnnaBridge	165:d1b4690b3f8b	760	#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) \|\|\
AnnaBridge	165:d1b4690b3f8b	761	((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
AnnaBridge	165:d1b4690b3f8b	762
AnnaBridge	165:d1b4690b3f8b	763	#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) \|\|\
AnnaBridge	165:d1b4690b3f8b	764	((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
AnnaBridge	165:d1b4690b3f8b	765
AnnaBridge	165:d1b4690b3f8b	766	#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
AnnaBridge	165:d1b4690b3f8b	767
AnnaBridge	165:d1b4690b3f8b	768
AnnaBridge	165:d1b4690b3f8b	769	#if defined (STM32L431xx) \|\| defined (STM32L433xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	770	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	165:d1b4690b3f8b	771	#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) \|\|\
AnnaBridge	165:d1b4690b3f8b	772	((GPIO) == PWR_GPIO_B) \|\|\
AnnaBridge	165:d1b4690b3f8b	773	((GPIO) == PWR_GPIO_C) \|\|\
AnnaBridge	165:d1b4690b3f8b	774	((GPIO) == PWR_GPIO_D) \|\|\
AnnaBridge	165:d1b4690b3f8b	775	((GPIO) == PWR_GPIO_E) \|\|\
AnnaBridge	165:d1b4690b3f8b	776	((GPIO) == PWR_GPIO_H))
AnnaBridge	165:d1b4690b3f8b	777	#elif defined (STM32L432xx) \|\| defined (STM32L442xx)
AnnaBridge	165:d1b4690b3f8b	778	#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) \|\|\
AnnaBridge	165:d1b4690b3f8b	779	((GPIO) == PWR_GPIO_B) \|\|\
AnnaBridge	165:d1b4690b3f8b	780	((GPIO) == PWR_GPIO_C) \|\|\
AnnaBridge	165:d1b4690b3f8b	781	((GPIO) == PWR_GPIO_H))
AnnaBridge	165:d1b4690b3f8b	782	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
AnnaBridge	165:d1b4690b3f8b	783	#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) \|\|\
AnnaBridge	165:d1b4690b3f8b	784	((GPIO) == PWR_GPIO_B) \|\|\
AnnaBridge	165:d1b4690b3f8b	785	((GPIO) == PWR_GPIO_C) \|\|\
AnnaBridge	165:d1b4690b3f8b	786	((GPIO) == PWR_GPIO_D) \|\|\
AnnaBridge	165:d1b4690b3f8b	787	((GPIO) == PWR_GPIO_E) \|\|\
AnnaBridge	165:d1b4690b3f8b	788	((GPIO) == PWR_GPIO_F) \|\|\
AnnaBridge	165:d1b4690b3f8b	789	((GPIO) == PWR_GPIO_G) \|\|\
AnnaBridge	165:d1b4690b3f8b	790	((GPIO) == PWR_GPIO_H))
AnnaBridge	165:d1b4690b3f8b	791	#elif defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	792	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	793	#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) \|\|\
AnnaBridge	165:d1b4690b3f8b	794	((GPIO) == PWR_GPIO_B) \|\|\
AnnaBridge	165:d1b4690b3f8b	795	((GPIO) == PWR_GPIO_C) \|\|\
AnnaBridge	165:d1b4690b3f8b	796	((GPIO) == PWR_GPIO_D) \|\|\
AnnaBridge	165:d1b4690b3f8b	797	((GPIO) == PWR_GPIO_E) \|\|\
AnnaBridge	165:d1b4690b3f8b	798	((GPIO) == PWR_GPIO_F) \|\|\
AnnaBridge	165:d1b4690b3f8b	799	((GPIO) == PWR_GPIO_G) \|\|\
AnnaBridge	165:d1b4690b3f8b	800	((GPIO) == PWR_GPIO_H) \|\|\
AnnaBridge	165:d1b4690b3f8b	801	((GPIO) == PWR_GPIO_I))
AnnaBridge	165:d1b4690b3f8b	802	#endif
AnnaBridge	165:d1b4690b3f8b	803
AnnaBridge	165:d1b4690b3f8b	804
AnnaBridge	165:d1b4690b3f8b	805	/**
AnnaBridge	165:d1b4690b3f8b	806	* @}
AnnaBridge	165:d1b4690b3f8b	807	*/
AnnaBridge	165:d1b4690b3f8b	808
AnnaBridge	165:d1b4690b3f8b	809
AnnaBridge	165:d1b4690b3f8b	810	/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
AnnaBridge	165:d1b4690b3f8b	811	* @{
AnnaBridge	165:d1b4690b3f8b	812	*/
AnnaBridge	165:d1b4690b3f8b	813
AnnaBridge	165:d1b4690b3f8b	814	/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
AnnaBridge	165:d1b4690b3f8b	815	* @{
AnnaBridge	165:d1b4690b3f8b	816	*/
AnnaBridge	165:d1b4690b3f8b	817
AnnaBridge	165:d1b4690b3f8b	818
AnnaBridge	165:d1b4690b3f8b	819	/* Peripheral Control functions **********************************************/
AnnaBridge	165:d1b4690b3f8b	820	uint32_t HAL_PWREx_GetVoltageRange(void);
AnnaBridge	165:d1b4690b3f8b	821	HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
AnnaBridge	165:d1b4690b3f8b	822	void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
AnnaBridge	165:d1b4690b3f8b	823	void HAL_PWREx_DisableBatteryCharging(void);
AnnaBridge	165:d1b4690b3f8b	824	#if defined(PWR_CR2_USV)
AnnaBridge	165:d1b4690b3f8b	825	void HAL_PWREx_EnableVddUSB(void);
AnnaBridge	165:d1b4690b3f8b	826	void HAL_PWREx_DisableVddUSB(void);
AnnaBridge	165:d1b4690b3f8b	827	#endif /* PWR_CR2_USV */
AnnaBridge	165:d1b4690b3f8b	828	#if defined(PWR_CR2_IOSV)
AnnaBridge	165:d1b4690b3f8b	829	void HAL_PWREx_EnableVddIO2(void);
AnnaBridge	165:d1b4690b3f8b	830	void HAL_PWREx_DisableVddIO2(void);
AnnaBridge	165:d1b4690b3f8b	831	#endif /* PWR_CR2_IOSV */
AnnaBridge	165:d1b4690b3f8b	832	void HAL_PWREx_EnableInternalWakeUpLine(void);
AnnaBridge	165:d1b4690b3f8b	833	void HAL_PWREx_DisableInternalWakeUpLine(void);
AnnaBridge	165:d1b4690b3f8b	834	HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
AnnaBridge	165:d1b4690b3f8b	835	HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
AnnaBridge	165:d1b4690b3f8b	836	HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
AnnaBridge	165:d1b4690b3f8b	837	HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
AnnaBridge	165:d1b4690b3f8b	838	void HAL_PWREx_EnablePullUpPullDownConfig(void);
AnnaBridge	165:d1b4690b3f8b	839	void HAL_PWREx_DisablePullUpPullDownConfig(void);
AnnaBridge	165:d1b4690b3f8b	840	void HAL_PWREx_EnableSRAM2ContentRetention(void);
AnnaBridge	165:d1b4690b3f8b	841	void HAL_PWREx_DisableSRAM2ContentRetention(void);
AnnaBridge	165:d1b4690b3f8b	842	#if defined(PWR_CR1_RRSTP)
AnnaBridge	165:d1b4690b3f8b	843	void HAL_PWREx_EnableSRAM3ContentRetention(void);
AnnaBridge	165:d1b4690b3f8b	844	void HAL_PWREx_DisableSRAM3ContentRetention(void);
AnnaBridge	165:d1b4690b3f8b	845	#endif /* PWR_CR1_RRSTP */
AnnaBridge	165:d1b4690b3f8b	846	#if defined(PWR_CR3_DSIPDEN)
AnnaBridge	165:d1b4690b3f8b	847	void HAL_PWREx_EnableDSIPinsPDActivation(void);
AnnaBridge	165:d1b4690b3f8b	848	void HAL_PWREx_DisableDSIPinsPDActivation(void);
AnnaBridge	165:d1b4690b3f8b	849	#endif /* PWR_CR3_DSIPDEN */
AnnaBridge	165:d1b4690b3f8b	850	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	851	void HAL_PWREx_EnablePVM1(void);
AnnaBridge	165:d1b4690b3f8b	852	void HAL_PWREx_DisablePVM1(void);
AnnaBridge	165:d1b4690b3f8b	853	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	854	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	855	void HAL_PWREx_EnablePVM2(void);
AnnaBridge	165:d1b4690b3f8b	856	void HAL_PWREx_DisablePVM2(void);
AnnaBridge	165:d1b4690b3f8b	857	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	858	void HAL_PWREx_EnablePVM3(void);
AnnaBridge	165:d1b4690b3f8b	859	void HAL_PWREx_DisablePVM3(void);
AnnaBridge	165:d1b4690b3f8b	860	void HAL_PWREx_EnablePVM4(void);
AnnaBridge	165:d1b4690b3f8b	861	void HAL_PWREx_DisablePVM4(void);
AnnaBridge	165:d1b4690b3f8b	862	HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
AnnaBridge	165:d1b4690b3f8b	863
AnnaBridge	165:d1b4690b3f8b	864
AnnaBridge	165:d1b4690b3f8b	865	/* Low Power modes configuration functions ************************************/
AnnaBridge	165:d1b4690b3f8b	866	void HAL_PWREx_EnableLowPowerRunMode(void);
AnnaBridge	165:d1b4690b3f8b	867	HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
AnnaBridge	165:d1b4690b3f8b	868	void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
AnnaBridge	165:d1b4690b3f8b	869	void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
AnnaBridge	165:d1b4690b3f8b	870	void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
AnnaBridge	165:d1b4690b3f8b	871	void HAL_PWREx_EnterSHUTDOWNMode(void);
AnnaBridge	165:d1b4690b3f8b	872
AnnaBridge	165:d1b4690b3f8b	873	void HAL_PWREx_PVD_PVM_IRQHandler(void);
AnnaBridge	165:d1b4690b3f8b	874	#if defined(PWR_CR2_PVME1)
AnnaBridge	165:d1b4690b3f8b	875	void HAL_PWREx_PVM1Callback(void);
AnnaBridge	165:d1b4690b3f8b	876	#endif /* PWR_CR2_PVME1 */
AnnaBridge	165:d1b4690b3f8b	877	#if defined(PWR_CR2_PVME2)
AnnaBridge	165:d1b4690b3f8b	878	void HAL_PWREx_PVM2Callback(void);
AnnaBridge	165:d1b4690b3f8b	879	#endif /* PWR_CR2_PVME2 */
AnnaBridge	165:d1b4690b3f8b	880	void HAL_PWREx_PVM3Callback(void);
AnnaBridge	165:d1b4690b3f8b	881	void HAL_PWREx_PVM4Callback(void);
AnnaBridge	165:d1b4690b3f8b	882
AnnaBridge	165:d1b4690b3f8b	883	/**
AnnaBridge	165:d1b4690b3f8b	884	* @}
AnnaBridge	165:d1b4690b3f8b	885	*/
AnnaBridge	165:d1b4690b3f8b	886
AnnaBridge	165:d1b4690b3f8b	887	/**
AnnaBridge	165:d1b4690b3f8b	888	* @}
AnnaBridge	165:d1b4690b3f8b	889	*/
AnnaBridge	165:d1b4690b3f8b	890
AnnaBridge	165:d1b4690b3f8b	891	/**
AnnaBridge	165:d1b4690b3f8b	892	* @}
AnnaBridge	165:d1b4690b3f8b	893	*/
AnnaBridge	165:d1b4690b3f8b	894
AnnaBridge	165:d1b4690b3f8b	895	/**
AnnaBridge	165:d1b4690b3f8b	896	* @}
AnnaBridge	165:d1b4690b3f8b	897	*/
AnnaBridge	165:d1b4690b3f8b	898
AnnaBridge	165:d1b4690b3f8b	899	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	900	}
AnnaBridge	165:d1b4690b3f8b	901	#endif
AnnaBridge	165:d1b4690b3f8b	902
AnnaBridge	165:d1b4690b3f8b	903
AnnaBridge	165:d1b4690b3f8b	904	#endif /* __STM32L4xx_HAL_PWR_EX_H */
AnnaBridge	165:d1b4690b3f8b	905
AnnaBridge	165:d1b4690b3f8b	906	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/