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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h@165:d1b4690b3f8b
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 165:d1b4690b3f8b | 1 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 2 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 3 | * @file stm32l4xx_hal_pwr.h |
| AnnaBridge | 165:d1b4690b3f8b | 4 | * @author MCD Application Team |
| AnnaBridge | 165:d1b4690b3f8b | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 165:d1b4690b3f8b | 6 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 7 | * @attention |
| AnnaBridge | 165:d1b4690b3f8b | 8 | * |
| AnnaBridge | 165:d1b4690b3f8b | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 165:d1b4690b3f8b | 10 | * |
| AnnaBridge | 165:d1b4690b3f8b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 165:d1b4690b3f8b | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 165:d1b4690b3f8b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 165:d1b4690b3f8b | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 165:d1b4690b3f8b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 165:d1b4690b3f8b | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 165:d1b4690b3f8b | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 165:d1b4690b3f8b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 165:d1b4690b3f8b | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 165:d1b4690b3f8b | 20 | * without specific prior written permission. |
| AnnaBridge | 165:d1b4690b3f8b | 21 | * |
| AnnaBridge | 165:d1b4690b3f8b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 165:d1b4690b3f8b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 165:d1b4690b3f8b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 165:d1b4690b3f8b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 165:d1b4690b3f8b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 165:d1b4690b3f8b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 165:d1b4690b3f8b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 165:d1b4690b3f8b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 165:d1b4690b3f8b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 165:d1b4690b3f8b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 165:d1b4690b3f8b | 32 | * |
| AnnaBridge | 165:d1b4690b3f8b | 33 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 34 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 35 | |
| AnnaBridge | 165:d1b4690b3f8b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 37 | #ifndef __STM32L4xx_HAL_PWR_H |
| AnnaBridge | 165:d1b4690b3f8b | 38 | #define __STM32L4xx_HAL_PWR_H |
| AnnaBridge | 165:d1b4690b3f8b | 39 | |
| AnnaBridge | 165:d1b4690b3f8b | 40 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 41 | extern "C" { |
| AnnaBridge | 165:d1b4690b3f8b | 42 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 43 | |
| AnnaBridge | 165:d1b4690b3f8b | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 165:d1b4690b3f8b | 46 | |
| AnnaBridge | 165:d1b4690b3f8b | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 165:d1b4690b3f8b | 48 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 49 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 50 | |
| AnnaBridge | 165:d1b4690b3f8b | 51 | /** @addtogroup PWR |
| AnnaBridge | 165:d1b4690b3f8b | 52 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 53 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 54 | |
| AnnaBridge | 165:d1b4690b3f8b | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 56 | |
| AnnaBridge | 165:d1b4690b3f8b | 57 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 165:d1b4690b3f8b | 58 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 59 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 60 | |
| AnnaBridge | 165:d1b4690b3f8b | 61 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 62 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 165:d1b4690b3f8b | 63 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 64 | typedef struct |
| AnnaBridge | 165:d1b4690b3f8b | 65 | { |
| AnnaBridge | 165:d1b4690b3f8b | 66 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 165:d1b4690b3f8b | 67 | This parameter can be a value of @ref PWR_PVD_detection_level. */ |
| AnnaBridge | 165:d1b4690b3f8b | 68 | |
| AnnaBridge | 165:d1b4690b3f8b | 69 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 165:d1b4690b3f8b | 70 | This parameter can be a value of @ref PWR_PVD_Mode. */ |
| AnnaBridge | 165:d1b4690b3f8b | 71 | }PWR_PVDTypeDef; |
| AnnaBridge | 165:d1b4690b3f8b | 72 | |
| AnnaBridge | 165:d1b4690b3f8b | 73 | |
| AnnaBridge | 165:d1b4690b3f8b | 74 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 75 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 76 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 77 | |
| AnnaBridge | 165:d1b4690b3f8b | 78 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 79 | |
| AnnaBridge | 165:d1b4690b3f8b | 80 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 165:d1b4690b3f8b | 81 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 82 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 83 | |
| AnnaBridge | 165:d1b4690b3f8b | 84 | |
| AnnaBridge | 165:d1b4690b3f8b | 85 | /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels |
| AnnaBridge | 165:d1b4690b3f8b | 86 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 87 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 88 | #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 89 | #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 90 | #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 91 | #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 92 | #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 93 | #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 94 | #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ |
| AnnaBridge | 165:d1b4690b3f8b | 95 | #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ |
| AnnaBridge | 165:d1b4690b3f8b | 96 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 97 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 98 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 99 | |
| AnnaBridge | 165:d1b4690b3f8b | 100 | /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode |
| AnnaBridge | 165:d1b4690b3f8b | 101 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 102 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 103 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ |
| AnnaBridge | 165:d1b4690b3f8b | 104 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 105 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 106 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 107 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 108 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 109 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 165:d1b4690b3f8b | 110 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 111 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 112 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 113 | |
| AnnaBridge | 165:d1b4690b3f8b | 114 | |
| AnnaBridge | 165:d1b4690b3f8b | 115 | |
| AnnaBridge | 165:d1b4690b3f8b | 116 | |
| AnnaBridge | 165:d1b4690b3f8b | 117 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode |
| AnnaBridge | 165:d1b4690b3f8b | 118 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 119 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 120 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 121 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 122 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 123 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 124 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 125 | |
| AnnaBridge | 165:d1b4690b3f8b | 126 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 165:d1b4690b3f8b | 127 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 128 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 129 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 130 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 131 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 132 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 133 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 134 | |
| AnnaBridge | 165:d1b4690b3f8b | 135 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 165:d1b4690b3f8b | 136 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 137 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 138 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 139 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 140 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 141 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 142 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 143 | |
| AnnaBridge | 165:d1b4690b3f8b | 144 | |
| AnnaBridge | 165:d1b4690b3f8b | 145 | /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line |
| AnnaBridge | 165:d1b4690b3f8b | 146 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 147 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 148 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 165:d1b4690b3f8b | 149 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 150 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 151 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 152 | |
| AnnaBridge | 165:d1b4690b3f8b | 153 | /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line |
| AnnaBridge | 165:d1b4690b3f8b | 154 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 155 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 156 | #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ |
| AnnaBridge | 165:d1b4690b3f8b | 157 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 158 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 159 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 160 | |
| AnnaBridge | 165:d1b4690b3f8b | 161 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 162 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 163 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 164 | |
| AnnaBridge | 165:d1b4690b3f8b | 165 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 166 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
| AnnaBridge | 165:d1b4690b3f8b | 167 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 168 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 169 | |
| AnnaBridge | 165:d1b4690b3f8b | 170 | /** @brief Check whether or not a specific PWR flag is set. |
| AnnaBridge | 165:d1b4690b3f8b | 171 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 165:d1b4690b3f8b | 172 | * This parameter can be one of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 173 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 174 | * was received from the WKUP pin 1. |
| AnnaBridge | 165:d1b4690b3f8b | 175 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 176 | * was received from the WKUP pin 2. |
| AnnaBridge | 165:d1b4690b3f8b | 177 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 178 | * was received from the WKUP pin 3. |
| AnnaBridge | 165:d1b4690b3f8b | 179 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 180 | * was received from the WKUP pin 4. |
| AnnaBridge | 165:d1b4690b3f8b | 181 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 182 | * was received from the WKUP pin 5. |
| AnnaBridge | 165:d1b4690b3f8b | 183 | * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system |
| AnnaBridge | 165:d1b4690b3f8b | 184 | * entered StandBy mode. |
| AnnaBridge | 165:d1b4690b3f8b | 185 | * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on |
| AnnaBridge | 165:d1b4690b3f8b | 186 | * the internal wakeup line. |
| AnnaBridge | 165:d1b4690b3f8b | 187 | * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the |
| AnnaBridge | 165:d1b4690b3f8b | 188 | * low-power regulator is ready. |
| AnnaBridge | 165:d1b4690b3f8b | 189 | * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the |
| AnnaBridge | 165:d1b4690b3f8b | 190 | * regulator is ready in main mode or is in low-power mode. |
| AnnaBridge | 165:d1b4690b3f8b | 191 | * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready |
| AnnaBridge | 165:d1b4690b3f8b | 192 | * in the selected voltage range or is still changing to the required voltage level. |
| AnnaBridge | 165:d1b4690b3f8b | 193 | * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is |
| AnnaBridge | 165:d1b4690b3f8b | 194 | * below or above the selected PVD threshold. |
| AnnaBridge | 165:d1b4690b3f8b | 195 | * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is |
| AnnaBridge | 165:d1b4690b3f8b | 196 | * is below or above PVM1 threshold (applicable when USB feature is supported). |
| AnnaBridge | 165:d1b4690b3f8b | 197 | @if STM32L486xx |
| AnnaBridge | 165:d1b4690b3f8b | 198 | * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is |
| AnnaBridge | 165:d1b4690b3f8b | 199 | * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). |
| AnnaBridge | 165:d1b4690b3f8b | 200 | @endif |
| AnnaBridge | 165:d1b4690b3f8b | 201 | * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is |
| AnnaBridge | 165:d1b4690b3f8b | 202 | * is below or above PVM3 threshold. |
| AnnaBridge | 165:d1b4690b3f8b | 203 | * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is |
| AnnaBridge | 165:d1b4690b3f8b | 204 | * is below or above PVM4 threshold. |
| AnnaBridge | 165:d1b4690b3f8b | 205 | * |
| AnnaBridge | 165:d1b4690b3f8b | 206 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 165:d1b4690b3f8b | 207 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 208 | #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ |
| AnnaBridge | 165:d1b4690b3f8b | 209 | (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ |
| AnnaBridge | 165:d1b4690b3f8b | 210 | (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) |
| AnnaBridge | 165:d1b4690b3f8b | 211 | |
| AnnaBridge | 165:d1b4690b3f8b | 212 | /** @brief Clear a specific PWR flag. |
| AnnaBridge | 165:d1b4690b3f8b | 213 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 165:d1b4690b3f8b | 214 | * This parameter can be one of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 215 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 216 | * was received from the WKUP pin 1. |
| AnnaBridge | 165:d1b4690b3f8b | 217 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 218 | * was received from the WKUP pin 2. |
| AnnaBridge | 165:d1b4690b3f8b | 219 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 220 | * was received from the WKUP pin 3. |
| AnnaBridge | 165:d1b4690b3f8b | 221 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 222 | * was received from the WKUP pin 4. |
| AnnaBridge | 165:d1b4690b3f8b | 223 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event |
| AnnaBridge | 165:d1b4690b3f8b | 224 | * was received from the WKUP pin 5. |
| AnnaBridge | 165:d1b4690b3f8b | 225 | * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. |
| AnnaBridge | 165:d1b4690b3f8b | 226 | * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system |
| AnnaBridge | 165:d1b4690b3f8b | 227 | * entered Standby mode. |
| AnnaBridge | 165:d1b4690b3f8b | 228 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 229 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 230 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ |
| AnnaBridge | 165:d1b4690b3f8b | 231 | (PWR->SCR = (__FLAG__)) :\ |
| AnnaBridge | 165:d1b4690b3f8b | 232 | (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) |
| AnnaBridge | 165:d1b4690b3f8b | 233 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 234 | * @brief Enable the PVD Extended Interrupt Line. |
| AnnaBridge | 165:d1b4690b3f8b | 235 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 236 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 237 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 238 | |
| AnnaBridge | 165:d1b4690b3f8b | 239 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 240 | * @brief Disable the PVD Extended Interrupt Line. |
| AnnaBridge | 165:d1b4690b3f8b | 241 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 242 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 243 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 244 | |
| AnnaBridge | 165:d1b4690b3f8b | 245 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 246 | * @brief Enable the PVD Event Line. |
| AnnaBridge | 165:d1b4690b3f8b | 247 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 248 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 249 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 250 | |
| AnnaBridge | 165:d1b4690b3f8b | 251 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 252 | * @brief Disable the PVD Event Line. |
| AnnaBridge | 165:d1b4690b3f8b | 253 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 254 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 255 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 256 | |
| AnnaBridge | 165:d1b4690b3f8b | 257 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 258 | * @brief Enable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 259 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 260 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 261 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 262 | |
| AnnaBridge | 165:d1b4690b3f8b | 263 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 264 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 265 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 266 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 267 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 268 | |
| AnnaBridge | 165:d1b4690b3f8b | 269 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 270 | * @brief Enable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 271 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 272 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 273 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 274 | |
| AnnaBridge | 165:d1b4690b3f8b | 275 | |
| AnnaBridge | 165:d1b4690b3f8b | 276 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 277 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 278 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 279 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 280 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 281 | |
| AnnaBridge | 165:d1b4690b3f8b | 282 | |
| AnnaBridge | 165:d1b4690b3f8b | 283 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 284 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 285 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 286 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 287 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 165:d1b4690b3f8b | 288 | do { \ |
| AnnaBridge | 165:d1b4690b3f8b | 289 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 165:d1b4690b3f8b | 290 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 165:d1b4690b3f8b | 291 | } while(0) |
| AnnaBridge | 165:d1b4690b3f8b | 292 | |
| AnnaBridge | 165:d1b4690b3f8b | 293 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 294 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 165:d1b4690b3f8b | 295 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 296 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 297 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 165:d1b4690b3f8b | 298 | do { \ |
| AnnaBridge | 165:d1b4690b3f8b | 299 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 165:d1b4690b3f8b | 300 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 165:d1b4690b3f8b | 301 | } while(0) |
| AnnaBridge | 165:d1b4690b3f8b | 302 | |
| AnnaBridge | 165:d1b4690b3f8b | 303 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 304 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 165:d1b4690b3f8b | 305 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 306 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 307 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 308 | |
| AnnaBridge | 165:d1b4690b3f8b | 309 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 310 | * @brief Check whether or not the PVD EXTI interrupt flag is set. |
| AnnaBridge | 165:d1b4690b3f8b | 311 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 165:d1b4690b3f8b | 312 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 313 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 314 | |
| AnnaBridge | 165:d1b4690b3f8b | 315 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 316 | * @brief Clear the PVD EXTI interrupt flag. |
| AnnaBridge | 165:d1b4690b3f8b | 317 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 318 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 319 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 165:d1b4690b3f8b | 320 | |
| AnnaBridge | 165:d1b4690b3f8b | 321 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 322 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 323 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 324 | |
| AnnaBridge | 165:d1b4690b3f8b | 325 | |
| AnnaBridge | 165:d1b4690b3f8b | 326 | /* Private macros --------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 327 | /** @addtogroup PWR_Private_Macros PWR Private Macros |
| AnnaBridge | 165:d1b4690b3f8b | 328 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 329 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 330 | |
| AnnaBridge | 165:d1b4690b3f8b | 331 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 165:d1b4690b3f8b | 332 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 165:d1b4690b3f8b | 333 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 165:d1b4690b3f8b | 334 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 165:d1b4690b3f8b | 335 | |
| AnnaBridge | 165:d1b4690b3f8b | 336 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 337 | ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 338 | ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 339 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 340 | ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 341 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ |
| AnnaBridge | 165:d1b4690b3f8b | 342 | ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) |
| AnnaBridge | 165:d1b4690b3f8b | 343 | |
| AnnaBridge | 165:d1b4690b3f8b | 344 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 345 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 165:d1b4690b3f8b | 346 | |
| AnnaBridge | 165:d1b4690b3f8b | 347 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 165:d1b4690b3f8b | 348 | |
| AnnaBridge | 165:d1b4690b3f8b | 349 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
| AnnaBridge | 165:d1b4690b3f8b | 350 | |
| AnnaBridge | 165:d1b4690b3f8b | 351 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 352 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 353 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 354 | |
| AnnaBridge | 165:d1b4690b3f8b | 355 | /* Include PWR HAL Extended module */ |
| AnnaBridge | 165:d1b4690b3f8b | 356 | #include "stm32l4xx_hal_pwr_ex.h" |
| AnnaBridge | 165:d1b4690b3f8b | 357 | |
| AnnaBridge | 165:d1b4690b3f8b | 358 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 359 | |
| AnnaBridge | 165:d1b4690b3f8b | 360 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 165:d1b4690b3f8b | 361 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 362 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 363 | |
| AnnaBridge | 165:d1b4690b3f8b | 364 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 165:d1b4690b3f8b | 365 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 366 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 367 | |
| AnnaBridge | 165:d1b4690b3f8b | 368 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 369 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 165:d1b4690b3f8b | 370 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 165:d1b4690b3f8b | 371 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 165:d1b4690b3f8b | 372 | |
| AnnaBridge | 165:d1b4690b3f8b | 373 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 374 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 375 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 376 | |
| AnnaBridge | 165:d1b4690b3f8b | 377 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 165:d1b4690b3f8b | 378 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 379 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 380 | |
| AnnaBridge | 165:d1b4690b3f8b | 381 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 382 | HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 165:d1b4690b3f8b | 383 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 165:d1b4690b3f8b | 384 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 165:d1b4690b3f8b | 385 | |
| AnnaBridge | 165:d1b4690b3f8b | 386 | |
| AnnaBridge | 165:d1b4690b3f8b | 387 | /* WakeUp pins configuration functions ****************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 388 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); |
| AnnaBridge | 165:d1b4690b3f8b | 389 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 165:d1b4690b3f8b | 390 | |
| AnnaBridge | 165:d1b4690b3f8b | 391 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 392 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 165:d1b4690b3f8b | 393 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 165:d1b4690b3f8b | 394 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 165:d1b4690b3f8b | 395 | |
| AnnaBridge | 165:d1b4690b3f8b | 396 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 165:d1b4690b3f8b | 397 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 165:d1b4690b3f8b | 398 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 165:d1b4690b3f8b | 399 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 165:d1b4690b3f8b | 400 | |
| AnnaBridge | 165:d1b4690b3f8b | 401 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 165:d1b4690b3f8b | 402 | |
| AnnaBridge | 165:d1b4690b3f8b | 403 | |
| AnnaBridge | 165:d1b4690b3f8b | 404 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 405 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 406 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 407 | |
| AnnaBridge | 165:d1b4690b3f8b | 408 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 409 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 410 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 411 | |
| AnnaBridge | 165:d1b4690b3f8b | 412 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 413 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 414 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 415 | |
| AnnaBridge | 165:d1b4690b3f8b | 416 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 417 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 418 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 419 | |
| AnnaBridge | 165:d1b4690b3f8b | 420 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 421 | } |
| AnnaBridge | 165:d1b4690b3f8b | 422 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 423 | |
| AnnaBridge | 165:d1b4690b3f8b | 424 | |
| AnnaBridge | 165:d1b4690b3f8b | 425 | #endif /* __STM32L4xx_HAL_PWR_H */ |
| AnnaBridge | 165:d1b4690b3f8b | 426 | |
| AnnaBridge | 165:d1b4690b3f8b | 427 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
