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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_nand.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h@161:aa5281ff4a02 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**
AnnaBridge 145:64910690c574 2 ******************************************************************************
AnnaBridge 145:64910690c574 3 * @file stm32l4xx_hal_nand.h
AnnaBridge 145:64910690c574 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @brief Header file of NAND HAL module.
AnnaBridge 145:64910690c574 6 ******************************************************************************
AnnaBridge 145:64910690c574 7 * @attention
AnnaBridge 145:64910690c574 8 *
AnnaBridge 145:64910690c574 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 145:64910690c574 10 *
AnnaBridge 145:64910690c574 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 12 * are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 145:64910690c574 14 * this list of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 145:64910690c574 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 145:64910690c574 17 * and/or other materials provided with the distribution.
AnnaBridge 145:64910690c574 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 145:64910690c574 19 * may be used to endorse or promote products derived from this software
AnnaBridge 145:64910690c574 20 * without specific prior written permission.
AnnaBridge 145:64910690c574 21 *
AnnaBridge 145:64910690c574 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 145:64910690c574 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 145:64910690c574 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 145:64910690c574 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 145:64910690c574 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 145:64910690c574 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 145:64910690c574 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 145:64910690c574 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 145:64910690c574 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 32 *
AnnaBridge 145:64910690c574 33 ******************************************************************************
AnnaBridge 145:64910690c574 34 */
AnnaBridge 145:64910690c574 35
AnnaBridge 145:64910690c574 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 145:64910690c574 37 #ifndef __STM32L4xx_HAL_NAND_H
AnnaBridge 145:64910690c574 38 #define __STM32L4xx_HAL_NAND_H
AnnaBridge 145:64910690c574 39
AnnaBridge 145:64910690c574 40 #ifdef __cplusplus
AnnaBridge 145:64910690c574 41 extern "C" {
AnnaBridge 145:64910690c574 42 #endif
AnnaBridge 145:64910690c574 43
AnnaBridge 145:64910690c574 44 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 161:aa5281ff4a02 45 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 161:aa5281ff4a02 46 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 145:64910690c574 47
AnnaBridge 145:64910690c574 48 /* Includes ------------------------------------------------------------------*/
AnnaBridge 145:64910690c574 49 #include "stm32l4xx_ll_fmc.h"
AnnaBridge 145:64910690c574 50
AnnaBridge 145:64910690c574 51 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 145:64910690c574 52 * @{
AnnaBridge 145:64910690c574 53 */
AnnaBridge 145:64910690c574 54
AnnaBridge 145:64910690c574 55 /** @addtogroup NAND
AnnaBridge 145:64910690c574 56 * @{
AnnaBridge 145:64910690c574 57 */
AnnaBridge 145:64910690c574 58
AnnaBridge 145:64910690c574 59 /** @addtogroup NAND_Private_Constants
AnnaBridge 145:64910690c574 60 * @{
AnnaBridge 145:64910690c574 61 */
AnnaBridge 145:64910690c574 62
AnnaBridge 145:64910690c574 63 #define NAND_DEVICE FMC_BANK3
AnnaBridge 145:64910690c574 64 #define NAND_WRITE_TIMEOUT ((uint32_t)1000)
AnnaBridge 145:64910690c574 65
AnnaBridge 145:64910690c574 66 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
AnnaBridge 145:64910690c574 67 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
AnnaBridge 145:64910690c574 68
AnnaBridge 145:64910690c574 69 #define NAND_CMD_AREA_A ((uint8_t)0x00)
AnnaBridge 145:64910690c574 70 #define NAND_CMD_AREA_B ((uint8_t)0x01)
AnnaBridge 145:64910690c574 71 #define NAND_CMD_AREA_C ((uint8_t)0x50)
AnnaBridge 145:64910690c574 72 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
AnnaBridge 145:64910690c574 73
AnnaBridge 145:64910690c574 74 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
AnnaBridge 145:64910690c574 75 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
AnnaBridge 145:64910690c574 76 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
AnnaBridge 145:64910690c574 77 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
AnnaBridge 145:64910690c574 78 #define NAND_CMD_READID ((uint8_t)0x90)
AnnaBridge 145:64910690c574 79 #define NAND_CMD_STATUS ((uint8_t)0x70)
AnnaBridge 145:64910690c574 80 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
AnnaBridge 145:64910690c574 81 #define NAND_CMD_RESET ((uint8_t)0xFF)
AnnaBridge 145:64910690c574 82
AnnaBridge 145:64910690c574 83 /* NAND memory status */
AnnaBridge 145:64910690c574 84 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
AnnaBridge 145:64910690c574 85 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
AnnaBridge 145:64910690c574 86 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
AnnaBridge 145:64910690c574 87 #define NAND_BUSY ((uint32_t)0x00000000)
AnnaBridge 145:64910690c574 88 #define NAND_ERROR ((uint32_t)0x00000001)
AnnaBridge 145:64910690c574 89 #define NAND_READY ((uint32_t)0x00000040)
AnnaBridge 145:64910690c574 90
AnnaBridge 145:64910690c574 91 /**
AnnaBridge 145:64910690c574 92 * @}
AnnaBridge 145:64910690c574 93 */
AnnaBridge 145:64910690c574 94
AnnaBridge 145:64910690c574 95 /** @addtogroup NAND_Private_Macros
AnnaBridge 145:64910690c574 96 * @{
AnnaBridge 145:64910690c574 97 */
AnnaBridge 145:64910690c574 98
AnnaBridge 145:64910690c574 99 /**
AnnaBridge 145:64910690c574 100 * @brief NAND memory address computation.
AnnaBridge 145:64910690c574 101 * @param __ADDRESS__: NAND memory address.
AnnaBridge 145:64910690c574 102 * @param __HANDLE__: NAND handle.
AnnaBridge 145:64910690c574 103 * @retval NAND Raw address value
AnnaBridge 145:64910690c574 104 */
AnnaBridge 145:64910690c574 105 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
AnnaBridge 145:64910690c574 106 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
AnnaBridge 145:64910690c574 107
AnnaBridge 145:64910690c574 108 /**
AnnaBridge 145:64910690c574 109 * @brief NAND memory address cycling.
AnnaBridge 145:64910690c574 110 * @param __ADDRESS__: NAND memory address.
AnnaBridge 145:64910690c574 111 * @retval NAND address cycling value.
AnnaBridge 145:64910690c574 112 */
AnnaBridge 145:64910690c574 113 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
AnnaBridge 145:64910690c574 114 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
AnnaBridge 145:64910690c574 115 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
AnnaBridge 145:64910690c574 116 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
AnnaBridge 145:64910690c574 117
AnnaBridge 145:64910690c574 118 /**
AnnaBridge 145:64910690c574 119 * @}
AnnaBridge 145:64910690c574 120 */
AnnaBridge 145:64910690c574 121
AnnaBridge 145:64910690c574 122 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 145:64910690c574 123 /* Exported types ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 124 /** @defgroup NAND_Exported_Types NAND Exported Types
AnnaBridge 145:64910690c574 125 * @{
AnnaBridge 145:64910690c574 126 */
AnnaBridge 145:64910690c574 127
AnnaBridge 145:64910690c574 128 /**
AnnaBridge 145:64910690c574 129 * @brief HAL NAND State structures definition
AnnaBridge 145:64910690c574 130 */
AnnaBridge 145:64910690c574 131 typedef enum
AnnaBridge 145:64910690c574 132 {
AnnaBridge 145:64910690c574 133 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
AnnaBridge 145:64910690c574 134 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
AnnaBridge 145:64910690c574 135 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
AnnaBridge 145:64910690c574 136 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
AnnaBridge 145:64910690c574 137 }HAL_NAND_StateTypeDef;
AnnaBridge 145:64910690c574 138
AnnaBridge 145:64910690c574 139 /**
AnnaBridge 145:64910690c574 140 * @brief NAND Memory electronic signature Structure definition
AnnaBridge 145:64910690c574 141 */
AnnaBridge 145:64910690c574 142 typedef struct
AnnaBridge 145:64910690c574 143 {
AnnaBridge 145:64910690c574 144 /*<! NAND memory electronic signature maker and device IDs */
AnnaBridge 145:64910690c574 145
AnnaBridge 145:64910690c574 146 uint8_t Maker_Id;
AnnaBridge 145:64910690c574 147
AnnaBridge 145:64910690c574 148 uint8_t Device_Id;
AnnaBridge 145:64910690c574 149
AnnaBridge 145:64910690c574 150 uint8_t Third_Id;
AnnaBridge 145:64910690c574 151
AnnaBridge 145:64910690c574 152 uint8_t Fourth_Id;
AnnaBridge 145:64910690c574 153 }NAND_IDTypeDef;
AnnaBridge 145:64910690c574 154
AnnaBridge 145:64910690c574 155 /**
AnnaBridge 145:64910690c574 156 * @brief NAND Memory address Structure definition
AnnaBridge 145:64910690c574 157 */
AnnaBridge 145:64910690c574 158 typedef struct
AnnaBridge 145:64910690c574 159 {
AnnaBridge 145:64910690c574 160 uint16_t Page; /*!< NAND memory Page address */
AnnaBridge 145:64910690c574 161
AnnaBridge 145:64910690c574 162 uint16_t Zone; /*!< NAND memory Zone address */
AnnaBridge 145:64910690c574 163
AnnaBridge 145:64910690c574 164 uint16_t Block; /*!< NAND memory Block address */
AnnaBridge 145:64910690c574 165
AnnaBridge 145:64910690c574 166 }NAND_AddressTypeDef;
AnnaBridge 145:64910690c574 167
AnnaBridge 145:64910690c574 168 /**
AnnaBridge 145:64910690c574 169 * @brief NAND Memory info Structure definition
AnnaBridge 145:64910690c574 170 */
AnnaBridge 145:64910690c574 171 typedef struct
AnnaBridge 145:64910690c574 172 {
AnnaBridge 145:64910690c574 173 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
AnnaBridge 145:64910690c574 174
AnnaBridge 145:64910690c574 175 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
AnnaBridge 145:64910690c574 176
AnnaBridge 145:64910690c574 177 uint32_t BlockSize; /*!< NAND memory block size number of pages */
AnnaBridge 145:64910690c574 178
AnnaBridge 145:64910690c574 179 uint32_t BlockNbr; /*!< NAND memory number of blocks */
AnnaBridge 145:64910690c574 180
AnnaBridge 145:64910690c574 181 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
AnnaBridge 145:64910690c574 182 }NAND_InfoTypeDef;
AnnaBridge 145:64910690c574 183
AnnaBridge 145:64910690c574 184 /**
AnnaBridge 145:64910690c574 185 * @brief NAND handle Structure definition
AnnaBridge 145:64910690c574 186 */
AnnaBridge 145:64910690c574 187 typedef struct
AnnaBridge 145:64910690c574 188 {
AnnaBridge 145:64910690c574 189 FMC_NAND_TypeDef *Instance; /*!< Register base address */
AnnaBridge 145:64910690c574 190
AnnaBridge 145:64910690c574 191 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
AnnaBridge 145:64910690c574 192
AnnaBridge 145:64910690c574 193 HAL_LockTypeDef Lock; /*!< NAND locking object */
AnnaBridge 145:64910690c574 194
AnnaBridge 145:64910690c574 195 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
AnnaBridge 145:64910690c574 196
AnnaBridge 145:64910690c574 197 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
AnnaBridge 145:64910690c574 198 }NAND_HandleTypeDef;
AnnaBridge 145:64910690c574 199
AnnaBridge 145:64910690c574 200 /**
AnnaBridge 145:64910690c574 201 * @}
AnnaBridge 145:64910690c574 202 */
AnnaBridge 145:64910690c574 203
AnnaBridge 145:64910690c574 204 /* Exported constants --------------------------------------------------------*/
AnnaBridge 145:64910690c574 205 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 206 /** @defgroup NAND_Exported_Macros NAND Exported Macros
AnnaBridge 145:64910690c574 207 * @{
AnnaBridge 145:64910690c574 208 */
AnnaBridge 145:64910690c574 209
AnnaBridge 145:64910690c574 210 /** @brief Reset NAND handle state.
AnnaBridge 145:64910690c574 211 * @param __HANDLE__: specifies the NAND handle.
AnnaBridge 145:64910690c574 212 * @retval None
AnnaBridge 145:64910690c574 213 */
AnnaBridge 145:64910690c574 214 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
AnnaBridge 145:64910690c574 215
AnnaBridge 145:64910690c574 216 /**
AnnaBridge 145:64910690c574 217 * @}
AnnaBridge 145:64910690c574 218 */
AnnaBridge 145:64910690c574 219
AnnaBridge 145:64910690c574 220 /* Exported functions --------------------------------------------------------*/
AnnaBridge 145:64910690c574 221 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
AnnaBridge 145:64910690c574 222 * @{
AnnaBridge 145:64910690c574 223 */
AnnaBridge 145:64910690c574 224
AnnaBridge 145:64910690c574 225 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 145:64910690c574 226 * @{
AnnaBridge 145:64910690c574 227 */
AnnaBridge 145:64910690c574 228
AnnaBridge 145:64910690c574 229 /* Initialization/de-initialization functions ********************************/
AnnaBridge 145:64910690c574 230 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
AnnaBridge 145:64910690c574 231 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 232 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 233 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 234 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 235 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 236
AnnaBridge 145:64910690c574 237 /**
AnnaBridge 145:64910690c574 238 * @}
AnnaBridge 145:64910690c574 239 */
AnnaBridge 145:64910690c574 240
AnnaBridge 145:64910690c574 241 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
AnnaBridge 145:64910690c574 242 * @{
AnnaBridge 145:64910690c574 243 */
AnnaBridge 145:64910690c574 244
AnnaBridge 145:64910690c574 245 /* IO operation functions ****************************************************/
AnnaBridge 145:64910690c574 246 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
AnnaBridge 145:64910690c574 247 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 248 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
AnnaBridge 145:64910690c574 249 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
AnnaBridge 145:64910690c574 250 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
AnnaBridge 145:64910690c574 251 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
AnnaBridge 145:64910690c574 252 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 145:64910690c574 253 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 254 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 145:64910690c574 255
AnnaBridge 145:64910690c574 256 /**
AnnaBridge 145:64910690c574 257 * @}
AnnaBridge 145:64910690c574 258 */
AnnaBridge 145:64910690c574 259
AnnaBridge 145:64910690c574 260 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 145:64910690c574 261 * @{
AnnaBridge 145:64910690c574 262 */
AnnaBridge 145:64910690c574 263
AnnaBridge 145:64910690c574 264 /* NAND Control functions ****************************************************/
AnnaBridge 145:64910690c574 265 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 266 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 267 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
AnnaBridge 145:64910690c574 268
AnnaBridge 145:64910690c574 269 /**
AnnaBridge 145:64910690c574 270 * @}
AnnaBridge 145:64910690c574 271 */
AnnaBridge 145:64910690c574 272
AnnaBridge 145:64910690c574 273 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 145:64910690c574 274 * @{
AnnaBridge 145:64910690c574 275 */
AnnaBridge 145:64910690c574 276
AnnaBridge 145:64910690c574 277 /* NAND State functions *******************************************************/
AnnaBridge 145:64910690c574 278 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 279 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 145:64910690c574 280
AnnaBridge 145:64910690c574 281 /**
AnnaBridge 145:64910690c574 282 * @}
AnnaBridge 145:64910690c574 283 */
AnnaBridge 145:64910690c574 284
AnnaBridge 145:64910690c574 285 /**
AnnaBridge 145:64910690c574 286 * @}
AnnaBridge 145:64910690c574 287 */
AnnaBridge 145:64910690c574 288
AnnaBridge 145:64910690c574 289 /**
AnnaBridge 145:64910690c574 290 * @}
AnnaBridge 145:64910690c574 291 */
AnnaBridge 145:64910690c574 292
AnnaBridge 145:64910690c574 293 /**
AnnaBridge 145:64910690c574 294 * @}
AnnaBridge 145:64910690c574 295 */
AnnaBridge 145:64910690c574 296
AnnaBridge 145:64910690c574 297 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 145:64910690c574 298 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 161:aa5281ff4a02 299 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 145:64910690c574 300
AnnaBridge 145:64910690c574 301 #ifdef __cplusplus
AnnaBridge 145:64910690c574 302 }
AnnaBridge 145:64910690c574 303 #endif
AnnaBridge 145:64910690c574 304
AnnaBridge 145:64910690c574 305 #endif /* __STM32L4xx_HAL_NAND_H */
AnnaBridge 145:64910690c574 306
AnnaBridge 145:64910690c574 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/