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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_flash.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_hal_flash.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of FLASH HAL module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_HAL_FLASH_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_HAL_FLASH_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	165:d1b4690b3f8b	48	* @{
AnnaBridge	165:d1b4690b3f8b	49	*/
AnnaBridge	165:d1b4690b3f8b	50
AnnaBridge	165:d1b4690b3f8b	51	/** @addtogroup FLASH
AnnaBridge	165:d1b4690b3f8b	52	* @{
AnnaBridge	165:d1b4690b3f8b	53	*/
AnnaBridge	165:d1b4690b3f8b	54
AnnaBridge	165:d1b4690b3f8b	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	56	/** @defgroup FLASH_Exported_Types FLASH Exported Types
AnnaBridge	165:d1b4690b3f8b	57	* @{
AnnaBridge	165:d1b4690b3f8b	58	*/
AnnaBridge	165:d1b4690b3f8b	59
AnnaBridge	165:d1b4690b3f8b	60	/**
AnnaBridge	165:d1b4690b3f8b	61	* @brief FLASH Erase structure definition
AnnaBridge	165:d1b4690b3f8b	62	*/
AnnaBridge	165:d1b4690b3f8b	63	typedef struct
AnnaBridge	165:d1b4690b3f8b	64	{
AnnaBridge	165:d1b4690b3f8b	65	uint32_t TypeErase; /*!< Mass erase or page erase.
AnnaBridge	165:d1b4690b3f8b	66	This parameter can be a value of @ref FLASH_Type_Erase */
AnnaBridge	165:d1b4690b3f8b	67	uint32_t Banks; /*!< Select bank to erase.
AnnaBridge	165:d1b4690b3f8b	68	This parameter must be a value of @ref FLASH_Banks
AnnaBridge	165:d1b4690b3f8b	69	(FLASH_BANK_BOTH should be used only for mass erase) */
AnnaBridge	165:d1b4690b3f8b	70	uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
AnnaBridge	165:d1b4690b3f8b	71	This parameter must be a value between 0 and (max number of pages in the bank - 1)
AnnaBridge	165:d1b4690b3f8b	72	(eg : 255 for 1MB dual bank) */
AnnaBridge	165:d1b4690b3f8b	73	uint32_t NbPages; /*!< Number of pages to be erased.
AnnaBridge	165:d1b4690b3f8b	74	This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
AnnaBridge	165:d1b4690b3f8b	75	} FLASH_EraseInitTypeDef;
AnnaBridge	165:d1b4690b3f8b	76
AnnaBridge	165:d1b4690b3f8b	77	/**
AnnaBridge	165:d1b4690b3f8b	78	* @brief FLASH Option Bytes Program structure definition
AnnaBridge	165:d1b4690b3f8b	79	*/
AnnaBridge	165:d1b4690b3f8b	80	typedef struct
AnnaBridge	165:d1b4690b3f8b	81	{
AnnaBridge	165:d1b4690b3f8b	82	uint32_t OptionType; /*!< Option byte to be configured.
AnnaBridge	165:d1b4690b3f8b	83	This parameter can be a combination of the values of @ref FLASH_OB_Type */
AnnaBridge	165:d1b4690b3f8b	84	uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
AnnaBridge	165:d1b4690b3f8b	85	Only one WRP area could be programmed at the same time.
AnnaBridge	165:d1b4690b3f8b	86	This parameter can be value of @ref FLASH_OB_WRP_Area */
AnnaBridge	165:d1b4690b3f8b	87	uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
AnnaBridge	165:d1b4690b3f8b	88	This parameter must be a value between 0 and (max number of pages in the bank - 1)
AnnaBridge	165:d1b4690b3f8b	89	(eg : 25 for 1MB dual bank) */
AnnaBridge	165:d1b4690b3f8b	90	uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
AnnaBridge	165:d1b4690b3f8b	91	This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
AnnaBridge	165:d1b4690b3f8b	92	uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
AnnaBridge	165:d1b4690b3f8b	93	This parameter can be a value of @ref FLASH_OB_Read_Protection */
AnnaBridge	165:d1b4690b3f8b	94	uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
AnnaBridge	165:d1b4690b3f8b	95	This parameter can be a combination of @ref FLASH_OB_USER_Type */
AnnaBridge	165:d1b4690b3f8b	96	uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
AnnaBridge	165:d1b4690b3f8b	97	This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
AnnaBridge	165:d1b4690b3f8b	98	@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
AnnaBridge	165:d1b4690b3f8b	99	@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
AnnaBridge	165:d1b4690b3f8b	100	@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
AnnaBridge	165:d1b4690b3f8b	101	@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
AnnaBridge	165:d1b4690b3f8b	102	@ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
AnnaBridge	165:d1b4690b3f8b	103	@ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
AnnaBridge	165:d1b4690b3f8b	104	uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
AnnaBridge	165:d1b4690b3f8b	105	This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
AnnaBridge	165:d1b4690b3f8b	106	and @ref FLASH_OB_PCROP_RDP */
AnnaBridge	165:d1b4690b3f8b	107	uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
AnnaBridge	165:d1b4690b3f8b	108	This parameter must be a value between begin and end of bank
AnnaBridge	165:d1b4690b3f8b	109	=> Be careful of the bank swapping for the address */
AnnaBridge	165:d1b4690b3f8b	110	uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
AnnaBridge	165:d1b4690b3f8b	111	This parameter must be a value between PCROP Start address and end of bank */
AnnaBridge	165:d1b4690b3f8b	112	} FLASH_OBProgramInitTypeDef;
AnnaBridge	165:d1b4690b3f8b	113
AnnaBridge	165:d1b4690b3f8b	114	/**
AnnaBridge	165:d1b4690b3f8b	115	* @brief FLASH Procedure structure definition
AnnaBridge	165:d1b4690b3f8b	116	*/
AnnaBridge	165:d1b4690b3f8b	117	typedef enum
AnnaBridge	165:d1b4690b3f8b	118	{
AnnaBridge	165:d1b4690b3f8b	119	FLASH_PROC_NONE = 0,
AnnaBridge	165:d1b4690b3f8b	120	FLASH_PROC_PAGE_ERASE,
AnnaBridge	165:d1b4690b3f8b	121	FLASH_PROC_MASS_ERASE,
AnnaBridge	165:d1b4690b3f8b	122	FLASH_PROC_PROGRAM,
AnnaBridge	165:d1b4690b3f8b	123	FLASH_PROC_PROGRAM_LAST
AnnaBridge	165:d1b4690b3f8b	124	} FLASH_ProcedureTypeDef;
AnnaBridge	165:d1b4690b3f8b	125
AnnaBridge	165:d1b4690b3f8b	126	/**
AnnaBridge	165:d1b4690b3f8b	127	* @brief FLASH Cache structure definition
AnnaBridge	165:d1b4690b3f8b	128	*/
AnnaBridge	165:d1b4690b3f8b	129	typedef enum
AnnaBridge	165:d1b4690b3f8b	130	{
AnnaBridge	165:d1b4690b3f8b	131	FLASH_CACHE_DISABLED = 0,
AnnaBridge	165:d1b4690b3f8b	132	FLASH_CACHE_ICACHE_ENABLED,
AnnaBridge	165:d1b4690b3f8b	133	FLASH_CACHE_DCACHE_ENABLED,
AnnaBridge	165:d1b4690b3f8b	134	FLASH_CACHE_ICACHE_DCACHE_ENABLED
AnnaBridge	165:d1b4690b3f8b	135	} FLASH_CacheTypeDef;
AnnaBridge	165:d1b4690b3f8b	136
AnnaBridge	165:d1b4690b3f8b	137	/**
AnnaBridge	165:d1b4690b3f8b	138	* @brief FLASH handle Structure definition
AnnaBridge	165:d1b4690b3f8b	139	*/
AnnaBridge	165:d1b4690b3f8b	140	typedef struct
AnnaBridge	165:d1b4690b3f8b	141	{
AnnaBridge	165:d1b4690b3f8b	142	HAL_LockTypeDef Lock; /* FLASH locking object */
AnnaBridge	165:d1b4690b3f8b	143	__IO uint32_t ErrorCode; /* FLASH error code */
AnnaBridge	165:d1b4690b3f8b	144	__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
AnnaBridge	165:d1b4690b3f8b	145	__IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
AnnaBridge	165:d1b4690b3f8b	146	__IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
AnnaBridge	165:d1b4690b3f8b	147	__IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
AnnaBridge	165:d1b4690b3f8b	148	__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
AnnaBridge	165:d1b4690b3f8b	149	__IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
AnnaBridge	165:d1b4690b3f8b	150	}FLASH_ProcessTypeDef;
AnnaBridge	165:d1b4690b3f8b	151
AnnaBridge	165:d1b4690b3f8b	152	/**
AnnaBridge	165:d1b4690b3f8b	153	* @}
AnnaBridge	165:d1b4690b3f8b	154	*/
AnnaBridge	165:d1b4690b3f8b	155
AnnaBridge	165:d1b4690b3f8b	156	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	157	/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
AnnaBridge	165:d1b4690b3f8b	158	* @{
AnnaBridge	165:d1b4690b3f8b	159	*/
AnnaBridge	165:d1b4690b3f8b	160
AnnaBridge	165:d1b4690b3f8b	161	/** @defgroup FLASH_Error FLASH Error
AnnaBridge	165:d1b4690b3f8b	162	* @{
AnnaBridge	165:d1b4690b3f8b	163	*/
AnnaBridge	165:d1b4690b3f8b	164	#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
AnnaBridge	165:d1b4690b3f8b	165	#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
AnnaBridge	165:d1b4690b3f8b	166	#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
AnnaBridge	165:d1b4690b3f8b	167	#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
AnnaBridge	165:d1b4690b3f8b	168	#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
AnnaBridge	165:d1b4690b3f8b	169	#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
AnnaBridge	165:d1b4690b3f8b	170	#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
AnnaBridge	165:d1b4690b3f8b	171	#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
AnnaBridge	165:d1b4690b3f8b	172	#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
AnnaBridge	165:d1b4690b3f8b	173	#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
AnnaBridge	165:d1b4690b3f8b	174	#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
AnnaBridge	165:d1b4690b3f8b	175	#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
AnnaBridge	165:d1b4690b3f8b	176	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	177	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	178	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	179	#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800)
AnnaBridge	165:d1b4690b3f8b	180	#endif
AnnaBridge	165:d1b4690b3f8b	181	/**
AnnaBridge	165:d1b4690b3f8b	182	* @}
AnnaBridge	165:d1b4690b3f8b	183	*/
AnnaBridge	165:d1b4690b3f8b	184
AnnaBridge	165:d1b4690b3f8b	185	/** @defgroup FLASH_Type_Erase FLASH Erase Type
AnnaBridge	165:d1b4690b3f8b	186	* @{
AnnaBridge	165:d1b4690b3f8b	187	*/
AnnaBridge	165:d1b4690b3f8b	188	#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /!<Pages erase only/
AnnaBridge	165:d1b4690b3f8b	189	#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /!<Flash mass erase activation/
AnnaBridge	165:d1b4690b3f8b	190	/**
AnnaBridge	165:d1b4690b3f8b	191	* @}
AnnaBridge	165:d1b4690b3f8b	192	*/
AnnaBridge	165:d1b4690b3f8b	193
AnnaBridge	165:d1b4690b3f8b	194	/** @defgroup FLASH_Banks FLASH Banks
AnnaBridge	165:d1b4690b3f8b	195	* @{
AnnaBridge	165:d1b4690b3f8b	196	*/
AnnaBridge	165:d1b4690b3f8b	197	#define FLASH_BANK_1 ((uint32_t)0x01) /!< Bank 1 /
AnnaBridge	165:d1b4690b3f8b	198	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	199	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	200	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	201	#define FLASH_BANK_2 ((uint32_t)0x02) /!< Bank 2 /
AnnaBridge	165:d1b4690b3f8b	202	#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 \| FLASH_BANK_2)) /!< Bank1 and Bank2 /
AnnaBridge	165:d1b4690b3f8b	203	#else
AnnaBridge	165:d1b4690b3f8b	204	#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /!< Bank 1 /
AnnaBridge	165:d1b4690b3f8b	205	#endif
AnnaBridge	165:d1b4690b3f8b	206	/**
AnnaBridge	165:d1b4690b3f8b	207	* @}
AnnaBridge	165:d1b4690b3f8b	208	*/
AnnaBridge	165:d1b4690b3f8b	209
AnnaBridge	165:d1b4690b3f8b	210
AnnaBridge	165:d1b4690b3f8b	211	/** @defgroup FLASH_Type_Program FLASH Program Type
AnnaBridge	165:d1b4690b3f8b	212	* @{
AnnaBridge	165:d1b4690b3f8b	213	*/
AnnaBridge	165:d1b4690b3f8b	214	#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /!<Program a double-word (64-bit) at a specified address./
AnnaBridge	165:d1b4690b3f8b	215	#define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
AnnaBridge	165:d1b4690b3f8b	216	And another 32 row double-word (64-bit) will be programmed */
AnnaBridge	165:d1b4690b3f8b	217	#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
AnnaBridge	165:d1b4690b3f8b	218	And this is the last 32 row double-word (64-bit) programmed */
AnnaBridge	165:d1b4690b3f8b	219	/**
AnnaBridge	165:d1b4690b3f8b	220	* @}
AnnaBridge	165:d1b4690b3f8b	221	*/
AnnaBridge	165:d1b4690b3f8b	222
AnnaBridge	165:d1b4690b3f8b	223	/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
AnnaBridge	165:d1b4690b3f8b	224	* @{
AnnaBridge	165:d1b4690b3f8b	225	*/
AnnaBridge	165:d1b4690b3f8b	226	#define OPTIONBYTE_WRP ((uint32_t)0x01) /!< WRP option byte configuration /
AnnaBridge	165:d1b4690b3f8b	227	#define OPTIONBYTE_RDP ((uint32_t)0x02) /!< RDP option byte configuration /
AnnaBridge	165:d1b4690b3f8b	228	#define OPTIONBYTE_USER ((uint32_t)0x04) /!< USER option byte configuration /
AnnaBridge	165:d1b4690b3f8b	229	#define OPTIONBYTE_PCROP ((uint32_t)0x08) /!< PCROP option byte configuration /
AnnaBridge	165:d1b4690b3f8b	230	/**
AnnaBridge	165:d1b4690b3f8b	231	* @}
AnnaBridge	165:d1b4690b3f8b	232	*/
AnnaBridge	165:d1b4690b3f8b	233
AnnaBridge	165:d1b4690b3f8b	234	/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
AnnaBridge	165:d1b4690b3f8b	235	* @{
AnnaBridge	165:d1b4690b3f8b	236	*/
AnnaBridge	165:d1b4690b3f8b	237	#define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /!< Flash Bank 1 Area A /
AnnaBridge	165:d1b4690b3f8b	238	#define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /!< Flash Bank 1 Area B /
AnnaBridge	165:d1b4690b3f8b	239	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	240	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	241	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	242	#define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /!< Flash Bank 2 Area A /
AnnaBridge	165:d1b4690b3f8b	243	#define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /!< Flash Bank 2 Area B /
AnnaBridge	165:d1b4690b3f8b	244	#endif
AnnaBridge	165:d1b4690b3f8b	245	/**
AnnaBridge	165:d1b4690b3f8b	246	* @}
AnnaBridge	165:d1b4690b3f8b	247	*/
AnnaBridge	165:d1b4690b3f8b	248
AnnaBridge	165:d1b4690b3f8b	249	/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
AnnaBridge	165:d1b4690b3f8b	250	* @{
AnnaBridge	165:d1b4690b3f8b	251	*/
AnnaBridge	165:d1b4690b3f8b	252	#define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
AnnaBridge	165:d1b4690b3f8b	253	#define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
AnnaBridge	165:d1b4690b3f8b	254	#define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
AnnaBridge	165:d1b4690b3f8b	255	it's no more possible to go back to level 1 or 0 */
AnnaBridge	165:d1b4690b3f8b	256	/**
AnnaBridge	165:d1b4690b3f8b	257	* @}
AnnaBridge	165:d1b4690b3f8b	258	*/
AnnaBridge	165:d1b4690b3f8b	259
AnnaBridge	165:d1b4690b3f8b	260	/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
AnnaBridge	165:d1b4690b3f8b	261	* @{
AnnaBridge	165:d1b4690b3f8b	262	*/
AnnaBridge	165:d1b4690b3f8b	263	#define OB_USER_BOR_LEV ((uint32_t)0x0001) /!< BOR reset Level /
AnnaBridge	165:d1b4690b3f8b	264	#define OB_USER_nRST_STOP ((uint32_t)0x0002) /!< Reset generated when entering the stop mode /
AnnaBridge	165:d1b4690b3f8b	265	#define OB_USER_nRST_STDBY ((uint32_t)0x0004) /!< Reset generated when entering the standby mode /
AnnaBridge	165:d1b4690b3f8b	266	#define OB_USER_IWDG_SW ((uint32_t)0x0008) /!< Independent watchdog selection /
AnnaBridge	165:d1b4690b3f8b	267	#define OB_USER_IWDG_STOP ((uint32_t)0x0010) /!< Independent watchdog counter freeze in stop mode /
AnnaBridge	165:d1b4690b3f8b	268	#define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /!< Independent watchdog counter freeze in standby mode /
AnnaBridge	165:d1b4690b3f8b	269	#define OB_USER_WWDG_SW ((uint32_t)0x0040) /!< Window watchdog selection /
AnnaBridge	165:d1b4690b3f8b	270	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	271	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	272	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	273	#define OB_USER_BFB2 ((uint32_t)0x0080) /!< Dual-bank boot /
AnnaBridge	165:d1b4690b3f8b	274	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	275	#define OB_USER_DUALBANK ((uint32_t)0x0100) /!< Dual-Bank on 1MB or 512kB Flash memory devices /
AnnaBridge	165:d1b4690b3f8b	276	#else
AnnaBridge	165:d1b4690b3f8b	277	#define OB_USER_DUALBANK ((uint32_t)0x0100) /!< Dual-Bank on 512KB or 256KB Flash memory devices /
AnnaBridge	165:d1b4690b3f8b	278	#endif
AnnaBridge	165:d1b4690b3f8b	279	#endif
AnnaBridge	165:d1b4690b3f8b	280	#define OB_USER_nBOOT1 ((uint32_t)0x0200) /!< Boot configuration /
AnnaBridge	165:d1b4690b3f8b	281	#define OB_USER_SRAM2_PE ((uint32_t)0x0400) /!< SRAM2 parity check enable /
AnnaBridge	165:d1b4690b3f8b	282	#define OB_USER_SRAM2_RST ((uint32_t)0x0800) /!< SRAM2 Erase when system reset /
AnnaBridge	165:d1b4690b3f8b	283	#define OB_USER_nRST_SHDW ((uint32_t)0x1000) /!< Reset generated when entering the shutdown mode /
AnnaBridge	165:d1b4690b3f8b	284	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	285	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	286	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	287	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	288	#define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /!< Software BOOT0 /
AnnaBridge	165:d1b4690b3f8b	289	#define OB_USER_nBOOT0 ((uint32_t)0x4000) /!< nBOOT0 option bit /
AnnaBridge	165:d1b4690b3f8b	290	#endif
AnnaBridge	165:d1b4690b3f8b	291	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	292	#define OB_USER_DBANK ((uint32_t)0x8000) /!< Single bank with 128-bits data or two banks with 64-bits data /
AnnaBridge	165:d1b4690b3f8b	293	#endif
AnnaBridge	165:d1b4690b3f8b	294	/**
AnnaBridge	165:d1b4690b3f8b	295	* @}
AnnaBridge	165:d1b4690b3f8b	296	*/
AnnaBridge	165:d1b4690b3f8b	297
AnnaBridge	165:d1b4690b3f8b	298	/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
AnnaBridge	165:d1b4690b3f8b	299	* @{
AnnaBridge	165:d1b4690b3f8b	300	*/
AnnaBridge	165:d1b4690b3f8b	301	#define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /!< Reset level threshold is around 1.7V /
AnnaBridge	165:d1b4690b3f8b	302	#define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /!< Reset level threshold is around 2.0V /
AnnaBridge	165:d1b4690b3f8b	303	#define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /!< Reset level threshold is around 2.2V /
AnnaBridge	165:d1b4690b3f8b	304	#define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /!< Reset level threshold is around 2.5V /
AnnaBridge	165:d1b4690b3f8b	305	#define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /!< Reset level threshold is around 2.8V /
AnnaBridge	165:d1b4690b3f8b	306	/**
AnnaBridge	165:d1b4690b3f8b	307	* @}
AnnaBridge	165:d1b4690b3f8b	308	*/
AnnaBridge	165:d1b4690b3f8b	309
AnnaBridge	165:d1b4690b3f8b	310	/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
AnnaBridge	165:d1b4690b3f8b	311	* @{
AnnaBridge	165:d1b4690b3f8b	312	*/
AnnaBridge	165:d1b4690b3f8b	313	#define OB_STOP_RST ((uint32_t)0x0000) /!< Reset generated when entering the stop mode /
AnnaBridge	165:d1b4690b3f8b	314	#define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /!< No reset generated when entering the stop mode /
AnnaBridge	165:d1b4690b3f8b	315	/**
AnnaBridge	165:d1b4690b3f8b	316	* @}
AnnaBridge	165:d1b4690b3f8b	317	*/
AnnaBridge	165:d1b4690b3f8b	318
AnnaBridge	165:d1b4690b3f8b	319	/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
AnnaBridge	165:d1b4690b3f8b	320	* @{
AnnaBridge	165:d1b4690b3f8b	321	*/
AnnaBridge	165:d1b4690b3f8b	322	#define OB_STANDBY_RST ((uint32_t)0x0000) /!< Reset generated when entering the standby mode /
AnnaBridge	165:d1b4690b3f8b	323	#define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /!< No reset generated when entering the standby mode /
AnnaBridge	165:d1b4690b3f8b	324	/**
AnnaBridge	165:d1b4690b3f8b	325	* @}
AnnaBridge	165:d1b4690b3f8b	326	*/
AnnaBridge	165:d1b4690b3f8b	327
AnnaBridge	165:d1b4690b3f8b	328	/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
AnnaBridge	165:d1b4690b3f8b	329	* @{
AnnaBridge	165:d1b4690b3f8b	330	*/
AnnaBridge	165:d1b4690b3f8b	331	#define OB_SHUTDOWN_RST ((uint32_t)0x0000) /!< Reset generated when entering the shutdown mode /
AnnaBridge	165:d1b4690b3f8b	332	#define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /!< No reset generated when entering the shutdown mode /
AnnaBridge	165:d1b4690b3f8b	333	/**
AnnaBridge	165:d1b4690b3f8b	334	* @}
AnnaBridge	165:d1b4690b3f8b	335	*/
AnnaBridge	165:d1b4690b3f8b	336
AnnaBridge	165:d1b4690b3f8b	337	/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
AnnaBridge	165:d1b4690b3f8b	338	* @{
AnnaBridge	165:d1b4690b3f8b	339	*/
AnnaBridge	165:d1b4690b3f8b	340	#define OB_IWDG_HW ((uint32_t)0x00000) /!< Hardware independent watchdog /
AnnaBridge	165:d1b4690b3f8b	341	#define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /!< Software independent watchdog /
AnnaBridge	165:d1b4690b3f8b	342	/**
AnnaBridge	165:d1b4690b3f8b	343	* @}
AnnaBridge	165:d1b4690b3f8b	344	*/
AnnaBridge	165:d1b4690b3f8b	345
AnnaBridge	165:d1b4690b3f8b	346	/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
AnnaBridge	165:d1b4690b3f8b	347	* @{
AnnaBridge	165:d1b4690b3f8b	348	*/
AnnaBridge	165:d1b4690b3f8b	349	#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /!< Independent watchdog counter is frozen in Stop mode /
AnnaBridge	165:d1b4690b3f8b	350	#define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /!< Independent watchdog counter is running in Stop mode /
AnnaBridge	165:d1b4690b3f8b	351	/**
AnnaBridge	165:d1b4690b3f8b	352	* @}
AnnaBridge	165:d1b4690b3f8b	353	*/
AnnaBridge	165:d1b4690b3f8b	354
AnnaBridge	165:d1b4690b3f8b	355	/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
AnnaBridge	165:d1b4690b3f8b	356	* @{
AnnaBridge	165:d1b4690b3f8b	357	*/
AnnaBridge	165:d1b4690b3f8b	358	#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /!< Independent watchdog counter is frozen in Standby mode /
AnnaBridge	165:d1b4690b3f8b	359	#define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /!< Independent watchdog counter is running in Standby mode /
AnnaBridge	165:d1b4690b3f8b	360	/**
AnnaBridge	165:d1b4690b3f8b	361	* @}
AnnaBridge	165:d1b4690b3f8b	362	*/
AnnaBridge	165:d1b4690b3f8b	363
AnnaBridge	165:d1b4690b3f8b	364	/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
AnnaBridge	165:d1b4690b3f8b	365	* @{
AnnaBridge	165:d1b4690b3f8b	366	*/
AnnaBridge	165:d1b4690b3f8b	367	#define OB_WWDG_HW ((uint32_t)0x00000) /!< Hardware window watchdog /
AnnaBridge	165:d1b4690b3f8b	368	#define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /!< Software window watchdog /
AnnaBridge	165:d1b4690b3f8b	369	/**
AnnaBridge	165:d1b4690b3f8b	370	* @}
AnnaBridge	165:d1b4690b3f8b	371	*/
AnnaBridge	165:d1b4690b3f8b	372
AnnaBridge	165:d1b4690b3f8b	373	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	374	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	375	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	376	/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
AnnaBridge	165:d1b4690b3f8b	377	* @{
AnnaBridge	165:d1b4690b3f8b	378	*/
AnnaBridge	165:d1b4690b3f8b	379	#define OB_BFB2_DISABLE ((uint32_t)0x000000) /!< Dual-bank boot disable /
AnnaBridge	165:d1b4690b3f8b	380	#define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /!< Dual-bank boot enable /
AnnaBridge	165:d1b4690b3f8b	381	/**
AnnaBridge	165:d1b4690b3f8b	382	* @}
AnnaBridge	165:d1b4690b3f8b	383	*/
AnnaBridge	165:d1b4690b3f8b	384	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	385	/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
AnnaBridge	165:d1b4690b3f8b	386	* @{
AnnaBridge	165:d1b4690b3f8b	387	*/
AnnaBridge	165:d1b4690b3f8b	388	#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /!< 1 MB/512 kB Single-bank Flash /
AnnaBridge	165:d1b4690b3f8b	389	#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /!< 1 MB/512 kB Dual-bank Flash /
AnnaBridge	165:d1b4690b3f8b	390	/**
AnnaBridge	165:d1b4690b3f8b	391	* @}
AnnaBridge	165:d1b4690b3f8b	392	*/
AnnaBridge	165:d1b4690b3f8b	393	#else
AnnaBridge	165:d1b4690b3f8b	394	/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
AnnaBridge	165:d1b4690b3f8b	395	* @{
AnnaBridge	165:d1b4690b3f8b	396	*/
AnnaBridge	165:d1b4690b3f8b	397	#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /!< 256 KB/512 KB Single-bank Flash /
AnnaBridge	165:d1b4690b3f8b	398	#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /!< 256 KB/512 KB Dual-bank Flash /
AnnaBridge	165:d1b4690b3f8b	399	/**
AnnaBridge	165:d1b4690b3f8b	400	* @}
AnnaBridge	165:d1b4690b3f8b	401	*/
AnnaBridge	165:d1b4690b3f8b	402	#endif
AnnaBridge	165:d1b4690b3f8b	403	#endif
AnnaBridge	165:d1b4690b3f8b	404
AnnaBridge	165:d1b4690b3f8b	405	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	406	/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
AnnaBridge	165:d1b4690b3f8b	407	* @{
AnnaBridge	165:d1b4690b3f8b	408	*/
AnnaBridge	165:d1b4690b3f8b	409	#define OB_DBANK_128_BITS ((uint32_t)0x000000) /!< Single-bank with 128-bits data /
AnnaBridge	165:d1b4690b3f8b	410	#define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /!< Dual-bank with 64-bits data /
AnnaBridge	165:d1b4690b3f8b	411	#endif
AnnaBridge	165:d1b4690b3f8b	412	/**
AnnaBridge	165:d1b4690b3f8b	413	* @}
AnnaBridge	165:d1b4690b3f8b	414	*/
AnnaBridge	165:d1b4690b3f8b	415	/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
AnnaBridge	165:d1b4690b3f8b	416	* @{
AnnaBridge	165:d1b4690b3f8b	417	*/
AnnaBridge	165:d1b4690b3f8b	418	#define OB_BOOT1_SRAM ((uint32_t)0x000000) /!< Embedded SRAM1 is selected as boot space (if BOOT0=1) /
AnnaBridge	165:d1b4690b3f8b	419	#define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /!< System memory is selected as boot space (if BOOT0=1) /
AnnaBridge	165:d1b4690b3f8b	420	/**
AnnaBridge	165:d1b4690b3f8b	421	* @}
AnnaBridge	165:d1b4690b3f8b	422	*/
AnnaBridge	165:d1b4690b3f8b	423
AnnaBridge	165:d1b4690b3f8b	424	/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
AnnaBridge	165:d1b4690b3f8b	425	* @{
AnnaBridge	165:d1b4690b3f8b	426	*/
AnnaBridge	165:d1b4690b3f8b	427	#define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /!< SRAM2 parity check enable /
AnnaBridge	165:d1b4690b3f8b	428	#define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /!< SRAM2 parity check disable /
AnnaBridge	165:d1b4690b3f8b	429	/**
AnnaBridge	165:d1b4690b3f8b	430	* @}
AnnaBridge	165:d1b4690b3f8b	431	*/
AnnaBridge	165:d1b4690b3f8b	432
AnnaBridge	165:d1b4690b3f8b	433	/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
AnnaBridge	165:d1b4690b3f8b	434	* @{
AnnaBridge	165:d1b4690b3f8b	435	*/
AnnaBridge	165:d1b4690b3f8b	436	#define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /!< SRAM2 erased when a system reset occurs /
AnnaBridge	165:d1b4690b3f8b	437	#define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /!< SRAM2 is not erased when a system reset occurs /
AnnaBridge	165:d1b4690b3f8b	438	/**
AnnaBridge	165:d1b4690b3f8b	439	* @}
AnnaBridge	165:d1b4690b3f8b	440	*/
AnnaBridge	165:d1b4690b3f8b	441
AnnaBridge	165:d1b4690b3f8b	442	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	443	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	444	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	445	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	446	/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
AnnaBridge	165:d1b4690b3f8b	447	* @{
AnnaBridge	165:d1b4690b3f8b	448	*/
AnnaBridge	165:d1b4690b3f8b	449	#define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /!< BOOT0 taken from the option bit nBOOT0 /
AnnaBridge	165:d1b4690b3f8b	450	#define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /!< BOOT0 taken from PH3/BOOT0 pin /
AnnaBridge	165:d1b4690b3f8b	451	/**
AnnaBridge	165:d1b4690b3f8b	452	* @}
AnnaBridge	165:d1b4690b3f8b	453	*/
AnnaBridge	165:d1b4690b3f8b	454
AnnaBridge	165:d1b4690b3f8b	455	/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
AnnaBridge	165:d1b4690b3f8b	456	* @{
AnnaBridge	165:d1b4690b3f8b	457	*/
AnnaBridge	165:d1b4690b3f8b	458	#define OB_BOOT0_RESET ((uint32_t)0x0000000) /!< nBOOT0 = 0 /
AnnaBridge	165:d1b4690b3f8b	459	#define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /!< nBOOT0 = 1 /
AnnaBridge	165:d1b4690b3f8b	460	/**
AnnaBridge	165:d1b4690b3f8b	461	* @}
AnnaBridge	165:d1b4690b3f8b	462	*/
AnnaBridge	165:d1b4690b3f8b	463	#endif
AnnaBridge	165:d1b4690b3f8b	464
AnnaBridge	165:d1b4690b3f8b	465	/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
AnnaBridge	165:d1b4690b3f8b	466	* @{
AnnaBridge	165:d1b4690b3f8b	467	*/
AnnaBridge	165:d1b4690b3f8b	468	#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level
AnnaBridge	165:d1b4690b3f8b	469	is decreased from Level 1 to Level 0 */
AnnaBridge	165:d1b4690b3f8b	470	#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
AnnaBridge	165:d1b4690b3f8b	471	decreased from Level 1 to Level 0 (full mass erase) */
AnnaBridge	165:d1b4690b3f8b	472	/**
AnnaBridge	165:d1b4690b3f8b	473	* @}
AnnaBridge	165:d1b4690b3f8b	474	*/
AnnaBridge	165:d1b4690b3f8b	475
AnnaBridge	165:d1b4690b3f8b	476	/** @defgroup FLASH_Latency FLASH Latency
AnnaBridge	165:d1b4690b3f8b	477	* @{
AnnaBridge	165:d1b4690b3f8b	478	*/
AnnaBridge	165:d1b4690b3f8b	479	#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
AnnaBridge	165:d1b4690b3f8b	480	#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
AnnaBridge	165:d1b4690b3f8b	481	#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
AnnaBridge	165:d1b4690b3f8b	482	#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
AnnaBridge	165:d1b4690b3f8b	483	#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
AnnaBridge	165:d1b4690b3f8b	484	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	485	#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH Five wait state /
AnnaBridge	165:d1b4690b3f8b	486	#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH Six wait state /
AnnaBridge	165:d1b4690b3f8b	487	#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH Seven wait states /
AnnaBridge	165:d1b4690b3f8b	488	#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH Eight wait states /
AnnaBridge	165:d1b4690b3f8b	489	#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH Nine wait states /
AnnaBridge	165:d1b4690b3f8b	490	#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH Ten wait state /
AnnaBridge	165:d1b4690b3f8b	491	#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH Eleven wait state /
AnnaBridge	165:d1b4690b3f8b	492	#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH Twelve wait states /
AnnaBridge	165:d1b4690b3f8b	493	#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH Thirteen wait states /
AnnaBridge	165:d1b4690b3f8b	494	#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH Fourteen wait states /
AnnaBridge	165:d1b4690b3f8b	495	#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH Fifteen wait states /
AnnaBridge	165:d1b4690b3f8b	496	#endif
AnnaBridge	165:d1b4690b3f8b	497	/**
AnnaBridge	165:d1b4690b3f8b	498	* @}
AnnaBridge	165:d1b4690b3f8b	499	*/
AnnaBridge	165:d1b4690b3f8b	500
AnnaBridge	165:d1b4690b3f8b	501	/** @defgroup FLASH_Keys FLASH Keys
AnnaBridge	165:d1b4690b3f8b	502	* @{
AnnaBridge	165:d1b4690b3f8b	503	*/
AnnaBridge	165:d1b4690b3f8b	504	#define FLASH_KEY1 0x45670123U /!< Flash key1 /
AnnaBridge	165:d1b4690b3f8b	505	#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
AnnaBridge	165:d1b4690b3f8b	506	to unlock the FLASH registers access */
AnnaBridge	165:d1b4690b3f8b	507
AnnaBridge	165:d1b4690b3f8b	508	#define FLASH_PDKEY1 0x04152637U /!< Flash power down key1 /
AnnaBridge	165:d1b4690b3f8b	509	#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
AnnaBridge	165:d1b4690b3f8b	510	to unlock the RUN_PD bit in FLASH_ACR */
AnnaBridge	165:d1b4690b3f8b	511
AnnaBridge	165:d1b4690b3f8b	512	#define FLASH_OPTKEY1 0x08192A3BU /!< Flash option byte key1 /
AnnaBridge	165:d1b4690b3f8b	513	#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
AnnaBridge	165:d1b4690b3f8b	514	to allow option bytes operations */
AnnaBridge	165:d1b4690b3f8b	515	/**
AnnaBridge	165:d1b4690b3f8b	516	* @}
AnnaBridge	165:d1b4690b3f8b	517	*/
AnnaBridge	165:d1b4690b3f8b	518
AnnaBridge	165:d1b4690b3f8b	519	/** @defgroup FLASH_Flags FLASH Flags Definition
AnnaBridge	165:d1b4690b3f8b	520	* @{
AnnaBridge	165:d1b4690b3f8b	521	*/
AnnaBridge	165:d1b4690b3f8b	522	#define FLASH_FLAG_EOP FLASH_SR_EOP /!< FLASH End of operation flag /
AnnaBridge	165:d1b4690b3f8b	523	#define FLASH_FLAG_OPERR FLASH_SR_OPERR /!< FLASH Operation error flag /
AnnaBridge	165:d1b4690b3f8b	524	#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /!< FLASH Programming error flag /
AnnaBridge	165:d1b4690b3f8b	525	#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /!< FLASH Write protection error flag /
AnnaBridge	165:d1b4690b3f8b	526	#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /!< FLASH Programming alignment error flag /
AnnaBridge	165:d1b4690b3f8b	527	#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /!< FLASH Size error flag /
AnnaBridge	165:d1b4690b3f8b	528	#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /!< FLASH Programming sequence error flag /
AnnaBridge	165:d1b4690b3f8b	529	#define FLASH_FLAG_MISERR FLASH_SR_MISERR /!< FLASH Fast programming data miss error flag /
AnnaBridge	165:d1b4690b3f8b	530	#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /!< FLASH Fast programming error flag /
AnnaBridge	165:d1b4690b3f8b	531	#define FLASH_FLAG_RDERR FLASH_SR_RDERR /!< FLASH PCROP read error flag /
AnnaBridge	165:d1b4690b3f8b	532	#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /!< FLASH Option validity error flag /
AnnaBridge	165:d1b4690b3f8b	533	#define FLASH_FLAG_BSY FLASH_SR_BSY /!< FLASH Busy flag /
AnnaBridge	165:d1b4690b3f8b	534	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	535	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	536	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	537	#define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /!< FLASH Program empty /
AnnaBridge	165:d1b4690b3f8b	538	#endif
AnnaBridge	165:d1b4690b3f8b	539	#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /!< FLASH ECC correction /
AnnaBridge	165:d1b4690b3f8b	540	#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /!< FLASH ECC detection /
AnnaBridge	165:d1b4690b3f8b	541
AnnaBridge	165:d1b4690b3f8b	542	#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR \| FLASH_FLAG_PROGERR \| FLASH_FLAG_WRPERR \| \
AnnaBridge	165:d1b4690b3f8b	543	FLASH_FLAG_PGAERR \| FLASH_FLAG_SIZERR \| FLASH_FLAG_PGSERR \| \
AnnaBridge	165:d1b4690b3f8b	544	FLASH_FLAG_MISERR \| FLASH_FLAG_FASTERR \| FLASH_FLAG_RDERR \| \
AnnaBridge	165:d1b4690b3f8b	545	FLASH_FLAG_OPTVERR \| FLASH_FLAG_ECCD)
AnnaBridge	165:d1b4690b3f8b	546	/**
AnnaBridge	165:d1b4690b3f8b	547	* @}
AnnaBridge	165:d1b4690b3f8b	548	*/
AnnaBridge	165:d1b4690b3f8b	549
AnnaBridge	165:d1b4690b3f8b	550	/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
AnnaBridge	165:d1b4690b3f8b	551	* @brief FLASH Interrupt definition
AnnaBridge	165:d1b4690b3f8b	552	* @{
AnnaBridge	165:d1b4690b3f8b	553	*/
AnnaBridge	165:d1b4690b3f8b	554	#define FLASH_IT_EOP FLASH_CR_EOPIE /!< End of FLASH Operation Interrupt source /
AnnaBridge	165:d1b4690b3f8b	555	#define FLASH_IT_OPERR FLASH_CR_ERRIE /!< Error Interrupt source /
AnnaBridge	165:d1b4690b3f8b	556	#define FLASH_IT_RDERR FLASH_CR_RDERRIE /!< PCROP Read Error Interrupt source/
AnnaBridge	165:d1b4690b3f8b	557	#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /!< ECC Correction Interrupt source /
AnnaBridge	165:d1b4690b3f8b	558	/**
AnnaBridge	165:d1b4690b3f8b	559	* @}
AnnaBridge	165:d1b4690b3f8b	560	*/
AnnaBridge	165:d1b4690b3f8b	561
AnnaBridge	165:d1b4690b3f8b	562	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	563	/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
AnnaBridge	165:d1b4690b3f8b	564	* @brief macros to control FLASH features
AnnaBridge	165:d1b4690b3f8b	565	* @{
AnnaBridge	165:d1b4690b3f8b	566	*/
AnnaBridge	165:d1b4690b3f8b	567
AnnaBridge	165:d1b4690b3f8b	568	/**
AnnaBridge	165:d1b4690b3f8b	569	* @brief Set the FLASH Latency.
AnnaBridge	165:d1b4690b3f8b	570	* @param __LATENCY__: FLASH Latency
AnnaBridge	165:d1b4690b3f8b	571	* This parameter can be one of the following values :
AnnaBridge	165:d1b4690b3f8b	572	* @arg FLASH_LATENCY_0: FLASH Zero wait state
AnnaBridge	165:d1b4690b3f8b	573	* @arg FLASH_LATENCY_1: FLASH One wait state
AnnaBridge	165:d1b4690b3f8b	574	* @arg FLASH_LATENCY_2: FLASH Two wait states
AnnaBridge	165:d1b4690b3f8b	575	* @arg FLASH_LATENCY_3: FLASH Three wait states
AnnaBridge	165:d1b4690b3f8b	576	* @arg FLASH_LATENCY_4: FLASH Four wait states
AnnaBridge	165:d1b4690b3f8b	577	* @retval None
AnnaBridge	165:d1b4690b3f8b	578	*/
AnnaBridge	165:d1b4690b3f8b	579	#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
AnnaBridge	165:d1b4690b3f8b	580
AnnaBridge	165:d1b4690b3f8b	581	/**
AnnaBridge	165:d1b4690b3f8b	582	* @brief Get the FLASH Latency.
AnnaBridge	165:d1b4690b3f8b	583	* @retval FLASH Latency
AnnaBridge	165:d1b4690b3f8b	584	* This parameter can be one of the following values :
AnnaBridge	165:d1b4690b3f8b	585	* @arg FLASH_LATENCY_0: FLASH Zero wait state
AnnaBridge	165:d1b4690b3f8b	586	* @arg FLASH_LATENCY_1: FLASH One wait state
AnnaBridge	165:d1b4690b3f8b	587	* @arg FLASH_LATENCY_2: FLASH Two wait states
AnnaBridge	165:d1b4690b3f8b	588	* @arg FLASH_LATENCY_3: FLASH Three wait states
AnnaBridge	165:d1b4690b3f8b	589	* @arg FLASH_LATENCY_4: FLASH Four wait states
AnnaBridge	165:d1b4690b3f8b	590	*/
AnnaBridge	165:d1b4690b3f8b	591	#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
AnnaBridge	165:d1b4690b3f8b	592
AnnaBridge	165:d1b4690b3f8b	593	/**
AnnaBridge	165:d1b4690b3f8b	594	* @brief Enable the FLASH prefetch buffer.
AnnaBridge	165:d1b4690b3f8b	595	* @retval None
AnnaBridge	165:d1b4690b3f8b	596	*/
AnnaBridge	165:d1b4690b3f8b	597	#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
AnnaBridge	165:d1b4690b3f8b	598
AnnaBridge	165:d1b4690b3f8b	599	/**
AnnaBridge	165:d1b4690b3f8b	600	* @brief Disable the FLASH prefetch buffer.
AnnaBridge	165:d1b4690b3f8b	601	* @retval None
AnnaBridge	165:d1b4690b3f8b	602	*/
AnnaBridge	165:d1b4690b3f8b	603	#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
AnnaBridge	165:d1b4690b3f8b	604
AnnaBridge	165:d1b4690b3f8b	605	/**
AnnaBridge	165:d1b4690b3f8b	606	* @brief Enable the FLASH instruction cache.
AnnaBridge	165:d1b4690b3f8b	607	* @retval none
AnnaBridge	165:d1b4690b3f8b	608	*/
AnnaBridge	165:d1b4690b3f8b	609	#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
AnnaBridge	165:d1b4690b3f8b	610
AnnaBridge	165:d1b4690b3f8b	611	/**
AnnaBridge	165:d1b4690b3f8b	612	* @brief Disable the FLASH instruction cache.
AnnaBridge	165:d1b4690b3f8b	613	* @retval none
AnnaBridge	165:d1b4690b3f8b	614	*/
AnnaBridge	165:d1b4690b3f8b	615	#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
AnnaBridge	165:d1b4690b3f8b	616
AnnaBridge	165:d1b4690b3f8b	617	/**
AnnaBridge	165:d1b4690b3f8b	618	* @brief Enable the FLASH data cache.
AnnaBridge	165:d1b4690b3f8b	619	* @retval none
AnnaBridge	165:d1b4690b3f8b	620	*/
AnnaBridge	165:d1b4690b3f8b	621	#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
AnnaBridge	165:d1b4690b3f8b	622
AnnaBridge	165:d1b4690b3f8b	623	/**
AnnaBridge	165:d1b4690b3f8b	624	* @brief Disable the FLASH data cache.
AnnaBridge	165:d1b4690b3f8b	625	* @retval none
AnnaBridge	165:d1b4690b3f8b	626	*/
AnnaBridge	165:d1b4690b3f8b	627	#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
AnnaBridge	165:d1b4690b3f8b	628
AnnaBridge	165:d1b4690b3f8b	629	/**
AnnaBridge	165:d1b4690b3f8b	630	* @brief Reset the FLASH instruction Cache.
AnnaBridge	165:d1b4690b3f8b	631	* @note This function must be used only when the Instruction Cache is disabled.
AnnaBridge	165:d1b4690b3f8b	632	* @retval None
AnnaBridge	165:d1b4690b3f8b	633	*/
AnnaBridge	165:d1b4690b3f8b	634	#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
AnnaBridge	165:d1b4690b3f8b	635	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
AnnaBridge	165:d1b4690b3f8b	636	} while (0)
AnnaBridge	165:d1b4690b3f8b	637
AnnaBridge	165:d1b4690b3f8b	638	/**
AnnaBridge	165:d1b4690b3f8b	639	* @brief Reset the FLASH data Cache.
AnnaBridge	165:d1b4690b3f8b	640	* @note This function must be used only when the data Cache is disabled.
AnnaBridge	165:d1b4690b3f8b	641	* @retval None
AnnaBridge	165:d1b4690b3f8b	642	*/
AnnaBridge	165:d1b4690b3f8b	643	#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
AnnaBridge	165:d1b4690b3f8b	644	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
AnnaBridge	165:d1b4690b3f8b	645	} while (0)
AnnaBridge	165:d1b4690b3f8b	646
AnnaBridge	165:d1b4690b3f8b	647	/**
AnnaBridge	165:d1b4690b3f8b	648	* @brief Enable the FLASH power down during Low-power run mode.
AnnaBridge	165:d1b4690b3f8b	649	* @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge	165:d1b4690b3f8b	650	* loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge	165:d1b4690b3f8b	651	*/
AnnaBridge	165:d1b4690b3f8b	652	#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
AnnaBridge	165:d1b4690b3f8b	653	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
AnnaBridge	165:d1b4690b3f8b	654	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
AnnaBridge	165:d1b4690b3f8b	655	} while (0)
AnnaBridge	165:d1b4690b3f8b	656
AnnaBridge	165:d1b4690b3f8b	657	/**
AnnaBridge	165:d1b4690b3f8b	658	* @brief Disable the FLASH power down during Low-power run mode.
AnnaBridge	165:d1b4690b3f8b	659	* @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge	165:d1b4690b3f8b	660	* loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge	165:d1b4690b3f8b	661	*/
AnnaBridge	165:d1b4690b3f8b	662	#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
AnnaBridge	165:d1b4690b3f8b	663	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
AnnaBridge	165:d1b4690b3f8b	664	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
AnnaBridge	165:d1b4690b3f8b	665	} while (0)
AnnaBridge	165:d1b4690b3f8b	666
AnnaBridge	165:d1b4690b3f8b	667	/**
AnnaBridge	165:d1b4690b3f8b	668	* @brief Enable the FLASH power down during Low-Power sleep mode
AnnaBridge	165:d1b4690b3f8b	669	* @retval none
AnnaBridge	165:d1b4690b3f8b	670	*/
AnnaBridge	165:d1b4690b3f8b	671	#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge	165:d1b4690b3f8b	672
AnnaBridge	165:d1b4690b3f8b	673	/**
AnnaBridge	165:d1b4690b3f8b	674	* @brief Disable the FLASH power down during Low-Power sleep mode
AnnaBridge	165:d1b4690b3f8b	675	* @retval none
AnnaBridge	165:d1b4690b3f8b	676	*/
AnnaBridge	165:d1b4690b3f8b	677	#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge	165:d1b4690b3f8b	678
AnnaBridge	165:d1b4690b3f8b	679	/**
AnnaBridge	165:d1b4690b3f8b	680	* @}
AnnaBridge	165:d1b4690b3f8b	681	*/
AnnaBridge	165:d1b4690b3f8b	682
AnnaBridge	165:d1b4690b3f8b	683	/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
AnnaBridge	165:d1b4690b3f8b	684	* @brief macros to handle FLASH interrupts
AnnaBridge	165:d1b4690b3f8b	685	* @{
AnnaBridge	165:d1b4690b3f8b	686	*/
AnnaBridge	165:d1b4690b3f8b	687
AnnaBridge	165:d1b4690b3f8b	688	/**
AnnaBridge	165:d1b4690b3f8b	689	* @brief Enable the specified FLASH interrupt.
AnnaBridge	165:d1b4690b3f8b	690	* @param __INTERRUPT__: FLASH interrupt
AnnaBridge	165:d1b4690b3f8b	691	* This parameter can be any combination of the following values:
AnnaBridge	165:d1b4690b3f8b	692	* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
AnnaBridge	165:d1b4690b3f8b	693	* @arg FLASH_IT_OPERR: Error Interrupt
AnnaBridge	165:d1b4690b3f8b	694	* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
AnnaBridge	165:d1b4690b3f8b	695	* @arg FLASH_IT_ECCC: ECC Correction Interrupt
AnnaBridge	165:d1b4690b3f8b	696	* @retval none
AnnaBridge	165:d1b4690b3f8b	697	*/
AnnaBridge	165:d1b4690b3f8b	698	#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
AnnaBridge	165:d1b4690b3f8b	699	if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
AnnaBridge	165:d1b4690b3f8b	700	} while(0)
AnnaBridge	165:d1b4690b3f8b	701
AnnaBridge	165:d1b4690b3f8b	702	/**
AnnaBridge	165:d1b4690b3f8b	703	* @brief Disable the specified FLASH interrupt.
AnnaBridge	165:d1b4690b3f8b	704	* @param __INTERRUPT__: FLASH interrupt
AnnaBridge	165:d1b4690b3f8b	705	* This parameter can be any combination of the following values:
AnnaBridge	165:d1b4690b3f8b	706	* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
AnnaBridge	165:d1b4690b3f8b	707	* @arg FLASH_IT_OPERR: Error Interrupt
AnnaBridge	165:d1b4690b3f8b	708	* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
AnnaBridge	165:d1b4690b3f8b	709	* @arg FLASH_IT_ECCC: ECC Correction Interrupt
AnnaBridge	165:d1b4690b3f8b	710	* @retval none
AnnaBridge	165:d1b4690b3f8b	711	*/
AnnaBridge	165:d1b4690b3f8b	712	#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
AnnaBridge	165:d1b4690b3f8b	713	if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
AnnaBridge	165:d1b4690b3f8b	714	} while(0)
AnnaBridge	165:d1b4690b3f8b	715
AnnaBridge	165:d1b4690b3f8b	716	/**
AnnaBridge	165:d1b4690b3f8b	717	* @brief Check whether the specified FLASH flag is set or not.
AnnaBridge	165:d1b4690b3f8b	718	* @param __FLAG__: specifies the FLASH flag to check.
AnnaBridge	165:d1b4690b3f8b	719	* This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	720	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
AnnaBridge	165:d1b4690b3f8b	721	* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
AnnaBridge	165:d1b4690b3f8b	722	* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
AnnaBridge	165:d1b4690b3f8b	723	* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
AnnaBridge	165:d1b4690b3f8b	724	* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
AnnaBridge	165:d1b4690b3f8b	725	* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
AnnaBridge	165:d1b4690b3f8b	726	* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
AnnaBridge	165:d1b4690b3f8b	727	* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
AnnaBridge	165:d1b4690b3f8b	728	* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
AnnaBridge	165:d1b4690b3f8b	729	* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
AnnaBridge	165:d1b4690b3f8b	730	* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
AnnaBridge	165:d1b4690b3f8b	731	* @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
AnnaBridge	165:d1b4690b3f8b	732	* @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
AnnaBridge	165:d1b4690b3f8b	733	* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
AnnaBridge	165:d1b4690b3f8b	734	* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
AnnaBridge	165:d1b4690b3f8b	735	* @retval The new state of FLASH_FLAG (SET or RESET).
AnnaBridge	165:d1b4690b3f8b	736	*/
AnnaBridge	165:d1b4690b3f8b	737	#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) ? \
AnnaBridge	165:d1b4690b3f8b	738	(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
AnnaBridge	165:d1b4690b3f8b	739	(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
AnnaBridge	165:d1b4690b3f8b	740
AnnaBridge	165:d1b4690b3f8b	741	/**
AnnaBridge	165:d1b4690b3f8b	742	* @brief Clear the FLASH's pending flags.
AnnaBridge	165:d1b4690b3f8b	743	* @param __FLAG__: specifies the FLASH flags to clear.
AnnaBridge	165:d1b4690b3f8b	744	* This parameter can be any combination of the following values:
AnnaBridge	165:d1b4690b3f8b	745	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
AnnaBridge	165:d1b4690b3f8b	746	* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
AnnaBridge	165:d1b4690b3f8b	747	* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
AnnaBridge	165:d1b4690b3f8b	748	* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
AnnaBridge	165:d1b4690b3f8b	749	* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
AnnaBridge	165:d1b4690b3f8b	750	* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
AnnaBridge	165:d1b4690b3f8b	751	* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
AnnaBridge	165:d1b4690b3f8b	752	* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
AnnaBridge	165:d1b4690b3f8b	753	* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
AnnaBridge	165:d1b4690b3f8b	754	* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
AnnaBridge	165:d1b4690b3f8b	755	* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
AnnaBridge	165:d1b4690b3f8b	756	* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
AnnaBridge	165:d1b4690b3f8b	757	* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
AnnaBridge	165:d1b4690b3f8b	758	* @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
AnnaBridge	165:d1b4690b3f8b	759	* @retval None
AnnaBridge	165:d1b4690b3f8b	760	*/
AnnaBridge	165:d1b4690b3f8b	761	#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD))); }\
AnnaBridge	165:d1b4690b3f8b	762	if((__FLAG__) & ~(FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD))); }\
AnnaBridge	165:d1b4690b3f8b	763	} while(0)
AnnaBridge	165:d1b4690b3f8b	764	/**
AnnaBridge	165:d1b4690b3f8b	765	* @}
AnnaBridge	165:d1b4690b3f8b	766	*/
AnnaBridge	165:d1b4690b3f8b	767
AnnaBridge	165:d1b4690b3f8b	768	/* Include FLASH HAL Extended module */
AnnaBridge	165:d1b4690b3f8b	769	#include "stm32l4xx_hal_flash_ex.h"
AnnaBridge	165:d1b4690b3f8b	770	#include "stm32l4xx_hal_flash_ramfunc.h"
AnnaBridge	165:d1b4690b3f8b	771
AnnaBridge	165:d1b4690b3f8b	772	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	773	/** @addtogroup FLASH_Exported_Functions
AnnaBridge	165:d1b4690b3f8b	774	* @{
AnnaBridge	165:d1b4690b3f8b	775	*/
AnnaBridge	165:d1b4690b3f8b	776
AnnaBridge	165:d1b4690b3f8b	777	/* Program operation functions ***********************************************/
AnnaBridge	165:d1b4690b3f8b	778	/** @addtogroup FLASH_Exported_Functions_Group1
AnnaBridge	165:d1b4690b3f8b	779	* @{
AnnaBridge	165:d1b4690b3f8b	780	*/
AnnaBridge	165:d1b4690b3f8b	781	HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
AnnaBridge	165:d1b4690b3f8b	782	HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
AnnaBridge	165:d1b4690b3f8b	783	/* FLASH IRQ handler method */
AnnaBridge	165:d1b4690b3f8b	784	void HAL_FLASH_IRQHandler(void);
AnnaBridge	165:d1b4690b3f8b	785	/* Callbacks in non blocking modes */
AnnaBridge	165:d1b4690b3f8b	786	void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
AnnaBridge	165:d1b4690b3f8b	787	void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
AnnaBridge	165:d1b4690b3f8b	788	/**
AnnaBridge	165:d1b4690b3f8b	789	* @}
AnnaBridge	165:d1b4690b3f8b	790	*/
AnnaBridge	165:d1b4690b3f8b	791
AnnaBridge	165:d1b4690b3f8b	792	/* Peripheral Control functions **********************************************/
AnnaBridge	165:d1b4690b3f8b	793	/** @addtogroup FLASH_Exported_Functions_Group2
AnnaBridge	165:d1b4690b3f8b	794	* @{
AnnaBridge	165:d1b4690b3f8b	795	*/
AnnaBridge	165:d1b4690b3f8b	796	HAL_StatusTypeDef HAL_FLASH_Unlock(void);
AnnaBridge	165:d1b4690b3f8b	797	HAL_StatusTypeDef HAL_FLASH_Lock(void);
AnnaBridge	165:d1b4690b3f8b	798	/* Option bytes control */
AnnaBridge	165:d1b4690b3f8b	799	HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
AnnaBridge	165:d1b4690b3f8b	800	HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
AnnaBridge	165:d1b4690b3f8b	801	HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
AnnaBridge	165:d1b4690b3f8b	802	/**
AnnaBridge	165:d1b4690b3f8b	803	* @}
AnnaBridge	165:d1b4690b3f8b	804	*/
AnnaBridge	165:d1b4690b3f8b	805
AnnaBridge	165:d1b4690b3f8b	806	/* Peripheral State functions ************************************************/
AnnaBridge	165:d1b4690b3f8b	807	/** @addtogroup FLASH_Exported_Functions_Group3
AnnaBridge	165:d1b4690b3f8b	808	* @{
AnnaBridge	165:d1b4690b3f8b	809	*/
AnnaBridge	165:d1b4690b3f8b	810	uint32_t HAL_FLASH_GetError(void);
AnnaBridge	165:d1b4690b3f8b	811	/**
AnnaBridge	165:d1b4690b3f8b	812	* @}
AnnaBridge	165:d1b4690b3f8b	813	*/
AnnaBridge	165:d1b4690b3f8b	814
AnnaBridge	165:d1b4690b3f8b	815	/**
AnnaBridge	165:d1b4690b3f8b	816	* @}
AnnaBridge	165:d1b4690b3f8b	817	*/
AnnaBridge	165:d1b4690b3f8b	818
AnnaBridge	165:d1b4690b3f8b	819	/* Private constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	820	/** @defgroup FLASH_Private_Constants FLASH Private Constants
AnnaBridge	165:d1b4690b3f8b	821	* @{
AnnaBridge	165:d1b4690b3f8b	822	*/
AnnaBridge	165:d1b4690b3f8b	823	#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
AnnaBridge	165:d1b4690b3f8b	824
AnnaBridge	165:d1b4690b3f8b	825	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	826	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \
AnnaBridge	165:d1b4690b3f8b	827	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	165:d1b4690b3f8b	828	#elif defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	165:d1b4690b3f8b	829	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
AnnaBridge	165:d1b4690b3f8b	830	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	165:d1b4690b3f8b	831	#else
AnnaBridge	165:d1b4690b3f8b	832	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
AnnaBridge	165:d1b4690b3f8b	833	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	165:d1b4690b3f8b	834	#endif
AnnaBridge	165:d1b4690b3f8b	835
AnnaBridge	165:d1b4690b3f8b	836	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	837	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	838	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	839	#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
AnnaBridge	165:d1b4690b3f8b	840	#else
AnnaBridge	165:d1b4690b3f8b	841	#define FLASH_BANK_SIZE (FLASH_SIZE)
AnnaBridge	165:d1b4690b3f8b	842	#endif
AnnaBridge	165:d1b4690b3f8b	843
AnnaBridge	165:d1b4690b3f8b	844	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	845	#define FLASH_PAGE_SIZE ((uint32_t)0x1000)
AnnaBridge	165:d1b4690b3f8b	846	#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000)
AnnaBridge	165:d1b4690b3f8b	847	#else
AnnaBridge	165:d1b4690b3f8b	848	#define FLASH_PAGE_SIZE ((uint32_t)0x800)
AnnaBridge	165:d1b4690b3f8b	849	#endif
AnnaBridge	165:d1b4690b3f8b	850
AnnaBridge	165:d1b4690b3f8b	851	#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
AnnaBridge	165:d1b4690b3f8b	852	/**
AnnaBridge	165:d1b4690b3f8b	853	* @}
AnnaBridge	165:d1b4690b3f8b	854	*/
AnnaBridge	165:d1b4690b3f8b	855
AnnaBridge	165:d1b4690b3f8b	856	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	857	/** @defgroup FLASH_Private_Macros FLASH Private Macros
AnnaBridge	165:d1b4690b3f8b	858	* @{
AnnaBridge	165:d1b4690b3f8b	859	*/
AnnaBridge	165:d1b4690b3f8b	860
AnnaBridge	165:d1b4690b3f8b	861	#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) \|\| \
AnnaBridge	165:d1b4690b3f8b	862	((VALUE) == FLASH_TYPEERASE_MASSERASE))
AnnaBridge	165:d1b4690b3f8b	863
AnnaBridge	165:d1b4690b3f8b	864	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	865	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	866	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	867	#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	868	((BANK) == FLASH_BANK_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	869	((BANK) == FLASH_BANK_BOTH))
AnnaBridge	165:d1b4690b3f8b	870
AnnaBridge	165:d1b4690b3f8b	871	#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	872	((BANK) == FLASH_BANK_2))
AnnaBridge	165:d1b4690b3f8b	873	#else
AnnaBridge	165:d1b4690b3f8b	874	#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
AnnaBridge	165:d1b4690b3f8b	875
AnnaBridge	165:d1b4690b3f8b	876	#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
AnnaBridge	165:d1b4690b3f8b	877	#endif
AnnaBridge	165:d1b4690b3f8b	878
AnnaBridge	165:d1b4690b3f8b	879	#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) \|\| \
AnnaBridge	165:d1b4690b3f8b	880	((VALUE) == FLASH_TYPEPROGRAM_FAST) \|\| \
AnnaBridge	165:d1b4690b3f8b	881	((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
AnnaBridge	165:d1b4690b3f8b	882
AnnaBridge	165:d1b4690b3f8b	883	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	884	#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF))
AnnaBridge	165:d1b4690b3f8b	885	#else
AnnaBridge	165:d1b4690b3f8b	886	#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
AnnaBridge	165:d1b4690b3f8b	887	((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
AnnaBridge	165:d1b4690b3f8b	888	((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
AnnaBridge	165:d1b4690b3f8b	889	((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
AnnaBridge	165:d1b4690b3f8b	890	((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
AnnaBridge	165:d1b4690b3f8b	891	#endif
AnnaBridge	165:d1b4690b3f8b	892
AnnaBridge	165:d1b4690b3f8b	893	#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
AnnaBridge	165:d1b4690b3f8b	894
AnnaBridge	165:d1b4690b3f8b	895	#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) \|\| IS_FLASH_OTP_ADDRESS(ADDRESS))
AnnaBridge	165:d1b4690b3f8b	896
AnnaBridge	165:d1b4690b3f8b	897	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	898	#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256)
AnnaBridge	165:d1b4690b3f8b	899	#elif defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	900	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
AnnaBridge	165:d1b4690b3f8b	901	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
AnnaBridge	165:d1b4690b3f8b	902	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
AnnaBridge	165:d1b4690b3f8b	903	((PAGE) < 256)))))
AnnaBridge	165:d1b4690b3f8b	904	#elif defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	165:d1b4690b3f8b	905	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
AnnaBridge	165:d1b4690b3f8b	906	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
AnnaBridge	165:d1b4690b3f8b	907	((PAGE) < 256))))
AnnaBridge	165:d1b4690b3f8b	908	#else
AnnaBridge	165:d1b4690b3f8b	909	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
AnnaBridge	165:d1b4690b3f8b	910	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \
AnnaBridge	165:d1b4690b3f8b	911	((PAGE) < 128))))
AnnaBridge	165:d1b4690b3f8b	912	#endif
AnnaBridge	165:d1b4690b3f8b	913
AnnaBridge	165:d1b4690b3f8b	914	#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP \| OPTIONBYTE_RDP \| OPTIONBYTE_USER \| OPTIONBYTE_PCROP)))
AnnaBridge	165:d1b4690b3f8b	915
AnnaBridge	165:d1b4690b3f8b	916	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	917	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	918	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	919	#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK1_AREAB) \|\| \
AnnaBridge	165:d1b4690b3f8b	920	((VALUE) == OB_WRPAREA_BANK2_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK2_AREAB))
AnnaBridge	165:d1b4690b3f8b	921	#else
AnnaBridge	165:d1b4690b3f8b	922	#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK1_AREAB))
AnnaBridge	165:d1b4690b3f8b	923	#endif
AnnaBridge	165:d1b4690b3f8b	924
AnnaBridge	165:d1b4690b3f8b	925	#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) \|\|\
AnnaBridge	165:d1b4690b3f8b	926	((LEVEL) == OB_RDP_LEVEL_1)/* \|\|\
AnnaBridge	165:d1b4690b3f8b	927	((LEVEL) == OB_RDP_LEVEL_2)*/)
AnnaBridge	165:d1b4690b3f8b	928
AnnaBridge	165:d1b4690b3f8b	929	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	930	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0))
AnnaBridge	165:d1b4690b3f8b	931	#elif defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	932	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
AnnaBridge	165:d1b4690b3f8b	933	#else
AnnaBridge	165:d1b4690b3f8b	934	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
AnnaBridge	165:d1b4690b3f8b	935	#endif
AnnaBridge	165:d1b4690b3f8b	936
AnnaBridge	165:d1b4690b3f8b	937	#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) \|\| ((LEVEL) == OB_BOR_LEVEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	938	((LEVEL) == OB_BOR_LEVEL_2) \|\| ((LEVEL) == OB_BOR_LEVEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	939	((LEVEL) == OB_BOR_LEVEL_4))
AnnaBridge	165:d1b4690b3f8b	940
AnnaBridge	165:d1b4690b3f8b	941	#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) \|\| ((VALUE) == OB_STOP_NORST))
AnnaBridge	165:d1b4690b3f8b	942
AnnaBridge	165:d1b4690b3f8b	943	#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) \|\| ((VALUE) == OB_STANDBY_NORST))
AnnaBridge	165:d1b4690b3f8b	944
AnnaBridge	165:d1b4690b3f8b	945	#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) \|\| ((VALUE) == OB_SHUTDOWN_NORST))
AnnaBridge	165:d1b4690b3f8b	946
AnnaBridge	165:d1b4690b3f8b	947	#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) \|\| ((VALUE) == OB_IWDG_SW))
AnnaBridge	165:d1b4690b3f8b	948
AnnaBridge	165:d1b4690b3f8b	949	#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) \|\| ((VALUE) == OB_IWDG_STOP_RUN))
AnnaBridge	165:d1b4690b3f8b	950
AnnaBridge	165:d1b4690b3f8b	951	#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) \|\| ((VALUE) == OB_IWDG_STDBY_RUN))
AnnaBridge	165:d1b4690b3f8b	952
AnnaBridge	165:d1b4690b3f8b	953	#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) \|\| ((VALUE) == OB_WWDG_SW))
AnnaBridge	165:d1b4690b3f8b	954
AnnaBridge	165:d1b4690b3f8b	955	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	956	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	957	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	958	#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) \|\| ((VALUE) == OB_BFB2_ENABLE))
AnnaBridge	165:d1b4690b3f8b	959
AnnaBridge	165:d1b4690b3f8b	960	#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) \|\| ((VALUE) == OB_DUALBANK_DUAL))
AnnaBridge	165:d1b4690b3f8b	961	#endif
AnnaBridge	165:d1b4690b3f8b	962
AnnaBridge	165:d1b4690b3f8b	963	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	964	#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) \|\| ((VALUE) == OB_DBANK_64_BITS))
AnnaBridge	165:d1b4690b3f8b	965	#endif
AnnaBridge	165:d1b4690b3f8b	966
AnnaBridge	165:d1b4690b3f8b	967	#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) \|\| ((VALUE) == OB_BOOT1_SYSTEM))
AnnaBridge	165:d1b4690b3f8b	968
AnnaBridge	165:d1b4690b3f8b	969	#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) \|\| ((VALUE) == OB_SRAM2_PARITY_DISABLE))
AnnaBridge	165:d1b4690b3f8b	970
AnnaBridge	165:d1b4690b3f8b	971	#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) \|\| ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
AnnaBridge	165:d1b4690b3f8b	972
AnnaBridge	165:d1b4690b3f8b	973	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	974	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	975	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	165:d1b4690b3f8b	976	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	977	#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) \|\| ((VALUE) == OB_BOOT0_FROM_PIN))
AnnaBridge	165:d1b4690b3f8b	978
AnnaBridge	165:d1b4690b3f8b	979	#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) \|\| ((VALUE) == OB_BOOT0_SET))
AnnaBridge	165:d1b4690b3f8b	980	#endif
AnnaBridge	165:d1b4690b3f8b	981
AnnaBridge	165:d1b4690b3f8b	982	#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) \|\| ((VALUE) == OB_PCROP_RDP_ERASE))
AnnaBridge	165:d1b4690b3f8b	983
AnnaBridge	165:d1b4690b3f8b	984	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	985	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| ((LATENCY) == FLASH_LATENCY_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	986	((LATENCY) == FLASH_LATENCY_2) \|\| ((LATENCY) == FLASH_LATENCY_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	987	((LATENCY) == FLASH_LATENCY_4) \|\| ((LATENCY) == FLASH_LATENCY_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	988	((LATENCY) == FLASH_LATENCY_6) \|\| ((LATENCY) == FLASH_LATENCY_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	989	((LATENCY) == FLASH_LATENCY_8) \|\| ((LATENCY) == FLASH_LATENCY_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	990	((LATENCY) == FLASH_LATENCY_10) \|\| ((LATENCY) == FLASH_LATENCY_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	991	((LATENCY) == FLASH_LATENCY_12) \|\| ((LATENCY) == FLASH_LATENCY_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	992	((LATENCY) == FLASH_LATENCY_14) \|\| ((LATENCY) == FLASH_LATENCY_15))
AnnaBridge	165:d1b4690b3f8b	993	#else
AnnaBridge	165:d1b4690b3f8b	994	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| \
AnnaBridge	165:d1b4690b3f8b	995	((LATENCY) == FLASH_LATENCY_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	996	((LATENCY) == FLASH_LATENCY_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	997	((LATENCY) == FLASH_LATENCY_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	998	((LATENCY) == FLASH_LATENCY_4))
AnnaBridge	165:d1b4690b3f8b	999	#endif
AnnaBridge	165:d1b4690b3f8b	1000	/**
AnnaBridge	165:d1b4690b3f8b	1001	* @}
AnnaBridge	165:d1b4690b3f8b	1002	*/
AnnaBridge	165:d1b4690b3f8b	1003
AnnaBridge	165:d1b4690b3f8b	1004	/**
AnnaBridge	165:d1b4690b3f8b	1005	* @}
AnnaBridge	165:d1b4690b3f8b	1006	*/
AnnaBridge	165:d1b4690b3f8b	1007
AnnaBridge	165:d1b4690b3f8b	1008	/**
AnnaBridge	165:d1b4690b3f8b	1009	* @}
AnnaBridge	165:d1b4690b3f8b	1010	*/
AnnaBridge	165:d1b4690b3f8b	1011
AnnaBridge	165:d1b4690b3f8b	1012	/**
AnnaBridge	165:d1b4690b3f8b	1013	* @}
AnnaBridge	165:d1b4690b3f8b	1014	*/
AnnaBridge	165:d1b4690b3f8b	1015
AnnaBridge	165:d1b4690b3f8b	1016	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	1017	}
AnnaBridge	165:d1b4690b3f8b	1018	#endif
AnnaBridge	165:d1b4690b3f8b	1019
AnnaBridge	165:d1b4690b3f8b	1020	#endif /* __STM32L4xx_HAL_FLASH_H */
AnnaBridge	165:d1b4690b3f8b	1021
AnnaBridge	165:d1b4690b3f8b	1022	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/