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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_dsi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h@161:aa5281ff4a02 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /**
AnnaBridge 161:aa5281ff4a02 2 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 3 * @file stm32l4xx_hal_dsi.h
AnnaBridge 161:aa5281ff4a02 4 * @author MCD Application Team
AnnaBridge 161:aa5281ff4a02 5 * @brief Header file of DSI HAL module.
AnnaBridge 161:aa5281ff4a02 6 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 7 * @attention
AnnaBridge 161:aa5281ff4a02 8 *
AnnaBridge 161:aa5281ff4a02 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 161:aa5281ff4a02 10 *
AnnaBridge 161:aa5281ff4a02 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 161:aa5281ff4a02 12 * are permitted provided that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 161:aa5281ff4a02 14 * this list of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 161:aa5281ff4a02 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 161:aa5281ff4a02 17 * and/or other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 161:aa5281ff4a02 19 * may be used to endorse or promote products derived from this software
AnnaBridge 161:aa5281ff4a02 20 * without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 21 *
AnnaBridge 161:aa5281ff4a02 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 161:aa5281ff4a02 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 161:aa5281ff4a02 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 161:aa5281ff4a02 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 161:aa5281ff4a02 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 161:aa5281ff4a02 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 161:aa5281ff4a02 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 161:aa5281ff4a02 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 161:aa5281ff4a02 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 32 *
AnnaBridge 161:aa5281ff4a02 33 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 34 */
AnnaBridge 161:aa5281ff4a02 35
AnnaBridge 161:aa5281ff4a02 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 161:aa5281ff4a02 37 #ifndef __STM32L4xx_HAL_DSI_H
AnnaBridge 161:aa5281ff4a02 38 #define __STM32L4xx_HAL_DSI_H
AnnaBridge 161:aa5281ff4a02 39
AnnaBridge 161:aa5281ff4a02 40 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 41 extern "C" {
AnnaBridge 161:aa5281ff4a02 42 #endif
AnnaBridge 161:aa5281ff4a02 43
AnnaBridge 161:aa5281ff4a02 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 161:aa5281ff4a02 46
AnnaBridge 161:aa5281ff4a02 47 #if defined(DSI)
AnnaBridge 161:aa5281ff4a02 48
AnnaBridge 161:aa5281ff4a02 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 161:aa5281ff4a02 50 * @{
AnnaBridge 161:aa5281ff4a02 51 */
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 /** @defgroup DSI DSI
AnnaBridge 161:aa5281ff4a02 54 * @brief DSI HAL module driver
AnnaBridge 161:aa5281ff4a02 55 * @{
AnnaBridge 161:aa5281ff4a02 56 */
AnnaBridge 161:aa5281ff4a02 57
AnnaBridge 161:aa5281ff4a02 58 /* Exported types ------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 59 /**
AnnaBridge 161:aa5281ff4a02 60 * @brief DSI Init Structure definition
AnnaBridge 161:aa5281ff4a02 61 */
AnnaBridge 161:aa5281ff4a02 62 typedef struct
AnnaBridge 161:aa5281ff4a02 63 {
AnnaBridge 161:aa5281ff4a02 64 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
AnnaBridge 161:aa5281ff4a02 65 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
AnnaBridge 161:aa5281ff4a02 66
AnnaBridge 161:aa5281ff4a02 67 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
AnnaBridge 161:aa5281ff4a02 68 The values 0 and 1 stop the TX_ESC clock generation */
AnnaBridge 161:aa5281ff4a02 69
AnnaBridge 161:aa5281ff4a02 70 uint32_t NumberOfLanes; /*!< Number of lanes
AnnaBridge 161:aa5281ff4a02 71 This parameter can be any value of @ref DSI_Number_Of_Lanes */
AnnaBridge 161:aa5281ff4a02 72
AnnaBridge 161:aa5281ff4a02 73 }DSI_InitTypeDef;
AnnaBridge 161:aa5281ff4a02 74
AnnaBridge 161:aa5281ff4a02 75 /**
AnnaBridge 161:aa5281ff4a02 76 * @brief DSI PLL Clock structure definition
AnnaBridge 161:aa5281ff4a02 77 */
AnnaBridge 161:aa5281ff4a02 78 typedef struct
AnnaBridge 161:aa5281ff4a02 79 {
AnnaBridge 161:aa5281ff4a02 80 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
AnnaBridge 161:aa5281ff4a02 81 This parameter must be a value between 10 and 125 */
AnnaBridge 161:aa5281ff4a02 82
AnnaBridge 161:aa5281ff4a02 83 uint32_t PLLIDF; /*!< PLL Input Division Factor
AnnaBridge 161:aa5281ff4a02 84 This parameter can be any value of @ref DSI_PLL_IDF */
AnnaBridge 161:aa5281ff4a02 85
AnnaBridge 161:aa5281ff4a02 86 uint32_t PLLODF; /*!< PLL Output Division Factor
AnnaBridge 161:aa5281ff4a02 87 This parameter can be any value of @ref DSI_PLL_ODF */
AnnaBridge 161:aa5281ff4a02 88
AnnaBridge 161:aa5281ff4a02 89 }DSI_PLLInitTypeDef;
AnnaBridge 161:aa5281ff4a02 90
AnnaBridge 161:aa5281ff4a02 91 /**
AnnaBridge 161:aa5281ff4a02 92 * @brief DSI Video mode configuration
AnnaBridge 161:aa5281ff4a02 93 */
AnnaBridge 161:aa5281ff4a02 94 typedef struct
AnnaBridge 161:aa5281ff4a02 95 {
AnnaBridge 161:aa5281ff4a02 96 uint32_t VirtualChannelID; /*!< Virtual channel ID */
AnnaBridge 161:aa5281ff4a02 97
AnnaBridge 161:aa5281ff4a02 98 uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge 161:aa5281ff4a02 99 This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge 161:aa5281ff4a02 100
AnnaBridge 161:aa5281ff4a02 101 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
AnnaBridge 161:aa5281ff4a02 102 18-bit configuration).
AnnaBridge 161:aa5281ff4a02 103 This parameter can be any value of @ref DSI_LooselyPacked */
AnnaBridge 161:aa5281ff4a02 104
AnnaBridge 161:aa5281ff4a02 105 uint32_t Mode; /*!< Video mode type
AnnaBridge 161:aa5281ff4a02 106 This parameter can be any value of @ref DSI_Video_Mode_Type */
AnnaBridge 161:aa5281ff4a02 107
AnnaBridge 161:aa5281ff4a02 108 uint32_t PacketSize; /*!< Video packet size */
AnnaBridge 161:aa5281ff4a02 109
AnnaBridge 161:aa5281ff4a02 110 uint32_t NumberOfChunks; /*!< Number of chunks */
AnnaBridge 161:aa5281ff4a02 111
AnnaBridge 161:aa5281ff4a02 112 uint32_t NullPacketSize; /*!< Null packet size */
AnnaBridge 161:aa5281ff4a02 113
AnnaBridge 161:aa5281ff4a02 114 uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge 161:aa5281ff4a02 115 This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge 161:aa5281ff4a02 116
AnnaBridge 161:aa5281ff4a02 117 uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge 161:aa5281ff4a02 118 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge 161:aa5281ff4a02 119
AnnaBridge 161:aa5281ff4a02 120 uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge 161:aa5281ff4a02 121 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge 161:aa5281ff4a02 122
AnnaBridge 161:aa5281ff4a02 123 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
AnnaBridge 161:aa5281ff4a02 124
AnnaBridge 161:aa5281ff4a02 125 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
AnnaBridge 161:aa5281ff4a02 126
AnnaBridge 161:aa5281ff4a02 127 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
AnnaBridge 161:aa5281ff4a02 128
AnnaBridge 161:aa5281ff4a02 129 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
AnnaBridge 161:aa5281ff4a02 130
AnnaBridge 161:aa5281ff4a02 131 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
AnnaBridge 161:aa5281ff4a02 132
AnnaBridge 161:aa5281ff4a02 133 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
AnnaBridge 161:aa5281ff4a02 134
AnnaBridge 161:aa5281ff4a02 135 uint32_t VerticalActive; /*!< Vertical active duration */
AnnaBridge 161:aa5281ff4a02 136
AnnaBridge 161:aa5281ff4a02 137 uint32_t LPCommandEnable; /*!< Low-power command enable
AnnaBridge 161:aa5281ff4a02 138 This parameter can be any value of @ref DSI_LP_Command */
AnnaBridge 161:aa5281ff4a02 139
AnnaBridge 161:aa5281ff4a02 140 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge 161:aa5281ff4a02 141 can fit in a line during VSA, VBP and VFP regions */
AnnaBridge 161:aa5281ff4a02 142
AnnaBridge 161:aa5281ff4a02 143 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge 161:aa5281ff4a02 144 can fit in a line during VACT region */
AnnaBridge 161:aa5281ff4a02 145
AnnaBridge 161:aa5281ff4a02 146 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
AnnaBridge 161:aa5281ff4a02 147 This parameter can be any value of @ref DSI_LP_HFP */
AnnaBridge 161:aa5281ff4a02 148
AnnaBridge 161:aa5281ff4a02 149 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
AnnaBridge 161:aa5281ff4a02 150 This parameter can be any value of @ref DSI_LP_HBP */
AnnaBridge 161:aa5281ff4a02 151
AnnaBridge 161:aa5281ff4a02 152 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
AnnaBridge 161:aa5281ff4a02 153 This parameter can be any value of @ref DSI_LP_VACT */
AnnaBridge 161:aa5281ff4a02 154
AnnaBridge 161:aa5281ff4a02 155 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
AnnaBridge 161:aa5281ff4a02 156 This parameter can be any value of @ref DSI_LP_VFP */
AnnaBridge 161:aa5281ff4a02 157
AnnaBridge 161:aa5281ff4a02 158 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
AnnaBridge 161:aa5281ff4a02 159 This parameter can be any value of @ref DSI_LP_VBP */
AnnaBridge 161:aa5281ff4a02 160
AnnaBridge 161:aa5281ff4a02 161 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
AnnaBridge 161:aa5281ff4a02 162 This parameter can be any value of @ref DSI_LP_VSYNC */
AnnaBridge 161:aa5281ff4a02 163
AnnaBridge 161:aa5281ff4a02 164 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
AnnaBridge 161:aa5281ff4a02 165 This parameter can be any value of @ref DSI_FBTA_acknowledge */
AnnaBridge 161:aa5281ff4a02 166
AnnaBridge 161:aa5281ff4a02 167 }DSI_VidCfgTypeDef;
AnnaBridge 161:aa5281ff4a02 168
AnnaBridge 161:aa5281ff4a02 169 /**
AnnaBridge 161:aa5281ff4a02 170 * @brief DSI Adapted command mode configuration
AnnaBridge 161:aa5281ff4a02 171 */
AnnaBridge 161:aa5281ff4a02 172 typedef struct
AnnaBridge 161:aa5281ff4a02 173 {
AnnaBridge 161:aa5281ff4a02 174 uint32_t VirtualChannelID; /*!< Virtual channel ID */
AnnaBridge 161:aa5281ff4a02 175
AnnaBridge 161:aa5281ff4a02 176 uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge 161:aa5281ff4a02 177 This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge 161:aa5281ff4a02 178
AnnaBridge 161:aa5281ff4a02 179 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
AnnaBridge 161:aa5281ff4a02 180 pixels. This parameter can be any value between 0x00 and 0xFFFFU */
AnnaBridge 161:aa5281ff4a02 181
AnnaBridge 161:aa5281ff4a02 182 uint32_t TearingEffectSource; /*!< Tearing effect source
AnnaBridge 161:aa5281ff4a02 183 This parameter can be any value of @ref DSI_TearingEffectSource */
AnnaBridge 161:aa5281ff4a02 184
AnnaBridge 161:aa5281ff4a02 185 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
AnnaBridge 161:aa5281ff4a02 186 This parameter can be any value of @ref DSI_TearingEffectPolarity */
AnnaBridge 161:aa5281ff4a02 187
AnnaBridge 161:aa5281ff4a02 188 uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge 161:aa5281ff4a02 189 This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge 161:aa5281ff4a02 190
AnnaBridge 161:aa5281ff4a02 191 uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge 161:aa5281ff4a02 192 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge 161:aa5281ff4a02 193
AnnaBridge 161:aa5281ff4a02 194 uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge 161:aa5281ff4a02 195 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge 161:aa5281ff4a02 196
AnnaBridge 161:aa5281ff4a02 197 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
AnnaBridge 161:aa5281ff4a02 198 This parameter can be any value of @ref DSI_Vsync_Polarity */
AnnaBridge 161:aa5281ff4a02 199
AnnaBridge 161:aa5281ff4a02 200 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
AnnaBridge 161:aa5281ff4a02 201 This parameter can be any value of @ref DSI_AutomaticRefresh */
AnnaBridge 161:aa5281ff4a02 202
AnnaBridge 161:aa5281ff4a02 203 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
AnnaBridge 161:aa5281ff4a02 204 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
AnnaBridge 161:aa5281ff4a02 205
AnnaBridge 161:aa5281ff4a02 206 }DSI_CmdCfgTypeDef;
AnnaBridge 161:aa5281ff4a02 207
AnnaBridge 161:aa5281ff4a02 208 /**
AnnaBridge 161:aa5281ff4a02 209 * @brief DSI command transmission mode configuration
AnnaBridge 161:aa5281ff4a02 210 */
AnnaBridge 161:aa5281ff4a02 211 typedef struct
AnnaBridge 161:aa5281ff4a02 212 {
AnnaBridge 161:aa5281ff4a02 213 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
AnnaBridge 161:aa5281ff4a02 214 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
AnnaBridge 161:aa5281ff4a02 215
AnnaBridge 161:aa5281ff4a02 216 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
AnnaBridge 161:aa5281ff4a02 217 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
AnnaBridge 161:aa5281ff4a02 218
AnnaBridge 161:aa5281ff4a02 219 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
AnnaBridge 161:aa5281ff4a02 220 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
AnnaBridge 161:aa5281ff4a02 221
AnnaBridge 161:aa5281ff4a02 222 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
AnnaBridge 161:aa5281ff4a02 223 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
AnnaBridge 161:aa5281ff4a02 224
AnnaBridge 161:aa5281ff4a02 225 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
AnnaBridge 161:aa5281ff4a02 226 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
AnnaBridge 161:aa5281ff4a02 227
AnnaBridge 161:aa5281ff4a02 228 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
AnnaBridge 161:aa5281ff4a02 229 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
AnnaBridge 161:aa5281ff4a02 230
AnnaBridge 161:aa5281ff4a02 231 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
AnnaBridge 161:aa5281ff4a02 232 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
AnnaBridge 161:aa5281ff4a02 233
AnnaBridge 161:aa5281ff4a02 234 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
AnnaBridge 161:aa5281ff4a02 235 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
AnnaBridge 161:aa5281ff4a02 236
AnnaBridge 161:aa5281ff4a02 237 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
AnnaBridge 161:aa5281ff4a02 238 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
AnnaBridge 161:aa5281ff4a02 239
AnnaBridge 161:aa5281ff4a02 240 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
AnnaBridge 161:aa5281ff4a02 241 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
AnnaBridge 161:aa5281ff4a02 242
AnnaBridge 161:aa5281ff4a02 243 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
AnnaBridge 161:aa5281ff4a02 244 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
AnnaBridge 161:aa5281ff4a02 245
AnnaBridge 161:aa5281ff4a02 246 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
AnnaBridge 161:aa5281ff4a02 247 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
AnnaBridge 161:aa5281ff4a02 248
AnnaBridge 161:aa5281ff4a02 249 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
AnnaBridge 161:aa5281ff4a02 250 This parameter can be any value of @ref DSI_AcknowledgeRequest */
AnnaBridge 161:aa5281ff4a02 251
AnnaBridge 161:aa5281ff4a02 252 }DSI_LPCmdTypeDef;
AnnaBridge 161:aa5281ff4a02 253
AnnaBridge 161:aa5281ff4a02 254 /**
AnnaBridge 161:aa5281ff4a02 255 * @brief DSI PHY Timings definition
AnnaBridge 161:aa5281ff4a02 256 */
AnnaBridge 161:aa5281ff4a02 257 typedef struct
AnnaBridge 161:aa5281ff4a02 258 {
AnnaBridge 161:aa5281ff4a02 259 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
AnnaBridge 161:aa5281ff4a02 260 to low-power transmission */
AnnaBridge 161:aa5281ff4a02 261
AnnaBridge 161:aa5281ff4a02 262 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
AnnaBridge 161:aa5281ff4a02 263 to high-speed transmission */
AnnaBridge 161:aa5281ff4a02 264
AnnaBridge 161:aa5281ff4a02 265 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
AnnaBridge 161:aa5281ff4a02 266 to low-power transmission */
AnnaBridge 161:aa5281ff4a02 267
AnnaBridge 161:aa5281ff4a02 268 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
AnnaBridge 161:aa5281ff4a02 269 to high-speed transmission */
AnnaBridge 161:aa5281ff4a02 270
AnnaBridge 161:aa5281ff4a02 271 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
AnnaBridge 161:aa5281ff4a02 272
AnnaBridge 161:aa5281ff4a02 273 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
AnnaBridge 161:aa5281ff4a02 274 Stop state */
AnnaBridge 161:aa5281ff4a02 275
AnnaBridge 161:aa5281ff4a02 276 }DSI_PHY_TimerTypeDef;
AnnaBridge 161:aa5281ff4a02 277
AnnaBridge 161:aa5281ff4a02 278 /**
AnnaBridge 161:aa5281ff4a02 279 * @brief DSI HOST Timeouts definition
AnnaBridge 161:aa5281ff4a02 280 */
AnnaBridge 161:aa5281ff4a02 281 typedef struct
AnnaBridge 161:aa5281ff4a02 282 {
AnnaBridge 161:aa5281ff4a02 283 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
AnnaBridge 161:aa5281ff4a02 284
AnnaBridge 161:aa5281ff4a02 285 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
AnnaBridge 161:aa5281ff4a02 286
AnnaBridge 161:aa5281ff4a02 287 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
AnnaBridge 161:aa5281ff4a02 288
AnnaBridge 161:aa5281ff4a02 289 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
AnnaBridge 161:aa5281ff4a02 290
AnnaBridge 161:aa5281ff4a02 291 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
AnnaBridge 161:aa5281ff4a02 292
AnnaBridge 161:aa5281ff4a02 293 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
AnnaBridge 161:aa5281ff4a02 294
AnnaBridge 161:aa5281ff4a02 295 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
AnnaBridge 161:aa5281ff4a02 296 This parameter can be any value of @ref DSI_HS_PrespMode */
AnnaBridge 161:aa5281ff4a02 297
AnnaBridge 161:aa5281ff4a02 298 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
AnnaBridge 161:aa5281ff4a02 299
AnnaBridge 161:aa5281ff4a02 300 uint32_t BTATimeout; /*!< BTA time-out */
AnnaBridge 161:aa5281ff4a02 301
AnnaBridge 161:aa5281ff4a02 302 }DSI_HOST_TimeoutTypeDef;
AnnaBridge 161:aa5281ff4a02 303
AnnaBridge 161:aa5281ff4a02 304 /**
AnnaBridge 161:aa5281ff4a02 305 * @brief DSI States Structure definition
AnnaBridge 161:aa5281ff4a02 306 */
AnnaBridge 161:aa5281ff4a02 307 typedef enum
AnnaBridge 161:aa5281ff4a02 308 {
AnnaBridge 161:aa5281ff4a02 309 HAL_DSI_STATE_RESET = 0x00U,
AnnaBridge 161:aa5281ff4a02 310 HAL_DSI_STATE_READY = 0x01U,
AnnaBridge 161:aa5281ff4a02 311 HAL_DSI_STATE_ERROR = 0x02U,
AnnaBridge 161:aa5281ff4a02 312 HAL_DSI_STATE_BUSY = 0x03U,
AnnaBridge 161:aa5281ff4a02 313 HAL_DSI_STATE_TIMEOUT = 0x04U
AnnaBridge 161:aa5281ff4a02 314 }HAL_DSI_StateTypeDef;
AnnaBridge 161:aa5281ff4a02 315
AnnaBridge 161:aa5281ff4a02 316 /**
AnnaBridge 161:aa5281ff4a02 317 * @brief DSI Handle Structure definition
AnnaBridge 161:aa5281ff4a02 318 */
AnnaBridge 161:aa5281ff4a02 319 typedef struct
AnnaBridge 161:aa5281ff4a02 320 {
AnnaBridge 161:aa5281ff4a02 321 DSI_TypeDef *Instance; /*!< Register base address */
AnnaBridge 161:aa5281ff4a02 322 DSI_InitTypeDef Init; /*!< DSI required parameters */
AnnaBridge 161:aa5281ff4a02 323 HAL_LockTypeDef Lock; /*!< DSI peripheral status */
AnnaBridge 161:aa5281ff4a02 324 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
AnnaBridge 161:aa5281ff4a02 325 __IO uint32_t ErrorCode; /*!< DSI Error code */
AnnaBridge 161:aa5281ff4a02 326 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
AnnaBridge 161:aa5281ff4a02 327 }DSI_HandleTypeDef;
AnnaBridge 161:aa5281ff4a02 328
AnnaBridge 161:aa5281ff4a02 329 /* Exported constants --------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 330 /** @defgroup DSI_DCS_Command DSI DCS Command
AnnaBridge 161:aa5281ff4a02 331 * @{
AnnaBridge 161:aa5281ff4a02 332 */
AnnaBridge 161:aa5281ff4a02 333 #define DSI_ENTER_IDLE_MODE 0x39U
AnnaBridge 161:aa5281ff4a02 334 #define DSI_ENTER_INVERT_MODE 0x21U
AnnaBridge 161:aa5281ff4a02 335 #define DSI_ENTER_NORMAL_MODE 0x13U
AnnaBridge 161:aa5281ff4a02 336 #define DSI_ENTER_PARTIAL_MODE 0x12U
AnnaBridge 161:aa5281ff4a02 337 #define DSI_ENTER_SLEEP_MODE 0x10U
AnnaBridge 161:aa5281ff4a02 338 #define DSI_EXIT_IDLE_MODE 0x38U
AnnaBridge 161:aa5281ff4a02 339 #define DSI_EXIT_INVERT_MODE 0x20U
AnnaBridge 161:aa5281ff4a02 340 #define DSI_EXIT_SLEEP_MODE 0x11U
AnnaBridge 161:aa5281ff4a02 341 #define DSI_GET_3D_CONTROL 0x3FU
AnnaBridge 161:aa5281ff4a02 342 #define DSI_GET_ADDRESS_MODE 0x0BU
AnnaBridge 161:aa5281ff4a02 343 #define DSI_GET_BLUE_CHANNEL 0x08U
AnnaBridge 161:aa5281ff4a02 344 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
AnnaBridge 161:aa5281ff4a02 345 #define DSI_GET_DISPLAY_MODE 0x0DU
AnnaBridge 161:aa5281ff4a02 346 #define DSI_GET_GREEN_CHANNEL 0x07U
AnnaBridge 161:aa5281ff4a02 347 #define DSI_GET_PIXEL_FORMAT 0x0CU
AnnaBridge 161:aa5281ff4a02 348 #define DSI_GET_POWER_MODE 0x0AU
AnnaBridge 161:aa5281ff4a02 349 #define DSI_GET_RED_CHANNEL 0x06U
AnnaBridge 161:aa5281ff4a02 350 #define DSI_GET_SCANLINE 0x45U
AnnaBridge 161:aa5281ff4a02 351 #define DSI_GET_SIGNAL_MODE 0x0EU
AnnaBridge 161:aa5281ff4a02 352 #define DSI_NOP 0x00U
AnnaBridge 161:aa5281ff4a02 353 #define DSI_READ_DDB_CONTINUE 0xA8U
AnnaBridge 161:aa5281ff4a02 354 #define DSI_READ_DDB_START 0xA1U
AnnaBridge 161:aa5281ff4a02 355 #define DSI_READ_MEMORY_CONTINUE 0x3EU
AnnaBridge 161:aa5281ff4a02 356 #define DSI_READ_MEMORY_START 0x2EU
AnnaBridge 161:aa5281ff4a02 357 #define DSI_SET_3D_CONTROL 0x3DU
AnnaBridge 161:aa5281ff4a02 358 #define DSI_SET_ADDRESS_MODE 0x36U
AnnaBridge 161:aa5281ff4a02 359 #define DSI_SET_COLUMN_ADDRESS 0x2AU
AnnaBridge 161:aa5281ff4a02 360 #define DSI_SET_DISPLAY_OFF 0x28U
AnnaBridge 161:aa5281ff4a02 361 #define DSI_SET_DISPLAY_ON 0x29U
AnnaBridge 161:aa5281ff4a02 362 #define DSI_SET_GAMMA_CURVE 0x26U
AnnaBridge 161:aa5281ff4a02 363 #define DSI_SET_PAGE_ADDRESS 0x2BU
AnnaBridge 161:aa5281ff4a02 364 #define DSI_SET_PARTIAL_COLUMNS 0x31U
AnnaBridge 161:aa5281ff4a02 365 #define DSI_SET_PARTIAL_ROWS 0x30U
AnnaBridge 161:aa5281ff4a02 366 #define DSI_SET_PIXEL_FORMAT 0x3AU
AnnaBridge 161:aa5281ff4a02 367 #define DSI_SET_SCROLL_AREA 0x33U
AnnaBridge 161:aa5281ff4a02 368 #define DSI_SET_SCROLL_START 0x37U
AnnaBridge 161:aa5281ff4a02 369 #define DSI_SET_TEAR_OFF 0x34U
AnnaBridge 161:aa5281ff4a02 370 #define DSI_SET_TEAR_ON 0x35U
AnnaBridge 161:aa5281ff4a02 371 #define DSI_SET_TEAR_SCANLINE 0x44U
AnnaBridge 161:aa5281ff4a02 372 #define DSI_SET_VSYNC_TIMING 0x40U
AnnaBridge 161:aa5281ff4a02 373 #define DSI_SOFT_RESET 0x01U
AnnaBridge 161:aa5281ff4a02 374 #define DSI_WRITE_LUT 0x2DU
AnnaBridge 161:aa5281ff4a02 375 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
AnnaBridge 161:aa5281ff4a02 376 #define DSI_WRITE_MEMORY_START 0x2CU
AnnaBridge 161:aa5281ff4a02 377 /**
AnnaBridge 161:aa5281ff4a02 378 * @}
AnnaBridge 161:aa5281ff4a02 379 */
AnnaBridge 161:aa5281ff4a02 380
AnnaBridge 161:aa5281ff4a02 381 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
AnnaBridge 161:aa5281ff4a02 382 * @{
AnnaBridge 161:aa5281ff4a02 383 */
AnnaBridge 161:aa5281ff4a02 384 #define DSI_VID_MODE_NB_PULSES 0U
AnnaBridge 161:aa5281ff4a02 385 #define DSI_VID_MODE_NB_EVENTS 1U
AnnaBridge 161:aa5281ff4a02 386 #define DSI_VID_MODE_BURST 2U
AnnaBridge 161:aa5281ff4a02 387 /**
AnnaBridge 161:aa5281ff4a02 388 * @}
AnnaBridge 161:aa5281ff4a02 389 */
AnnaBridge 161:aa5281ff4a02 390
AnnaBridge 161:aa5281ff4a02 391 /** @defgroup DSI_Color_Mode DSI Color Mode
AnnaBridge 161:aa5281ff4a02 392 * @{
AnnaBridge 161:aa5281ff4a02 393 */
AnnaBridge 161:aa5281ff4a02 394 #define DSI_COLOR_MODE_FULL 0x00000000U
AnnaBridge 161:aa5281ff4a02 395 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
AnnaBridge 161:aa5281ff4a02 396 /**
AnnaBridge 161:aa5281ff4a02 397 * @}
AnnaBridge 161:aa5281ff4a02 398 */
AnnaBridge 161:aa5281ff4a02 399
AnnaBridge 161:aa5281ff4a02 400 /** @defgroup DSI_ShutDown DSI ShutDown
AnnaBridge 161:aa5281ff4a02 401 * @{
AnnaBridge 161:aa5281ff4a02 402 */
AnnaBridge 161:aa5281ff4a02 403 #define DSI_DISPLAY_ON 0x00000000U
AnnaBridge 161:aa5281ff4a02 404 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
AnnaBridge 161:aa5281ff4a02 405 /**
AnnaBridge 161:aa5281ff4a02 406 * @}
AnnaBridge 161:aa5281ff4a02 407 */
AnnaBridge 161:aa5281ff4a02 408
AnnaBridge 161:aa5281ff4a02 409 /** @defgroup DSI_LP_Command DSI LP Command
AnnaBridge 161:aa5281ff4a02 410 * @{
AnnaBridge 161:aa5281ff4a02 411 */
AnnaBridge 161:aa5281ff4a02 412 #define DSI_LP_COMMAND_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 413 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
AnnaBridge 161:aa5281ff4a02 414 /**
AnnaBridge 161:aa5281ff4a02 415 * @}
AnnaBridge 161:aa5281ff4a02 416 */
AnnaBridge 161:aa5281ff4a02 417
AnnaBridge 161:aa5281ff4a02 418 /** @defgroup DSI_LP_HFP DSI LP HFP
AnnaBridge 161:aa5281ff4a02 419 * @{
AnnaBridge 161:aa5281ff4a02 420 */
AnnaBridge 161:aa5281ff4a02 421 #define DSI_LP_HFP_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 422 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
AnnaBridge 161:aa5281ff4a02 423 /**
AnnaBridge 161:aa5281ff4a02 424 * @}
AnnaBridge 161:aa5281ff4a02 425 */
AnnaBridge 161:aa5281ff4a02 426
AnnaBridge 161:aa5281ff4a02 427 /** @defgroup DSI_LP_HBP DSI LP HBP
AnnaBridge 161:aa5281ff4a02 428 * @{
AnnaBridge 161:aa5281ff4a02 429 */
AnnaBridge 161:aa5281ff4a02 430 #define DSI_LP_HBP_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 431 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
AnnaBridge 161:aa5281ff4a02 432 /**
AnnaBridge 161:aa5281ff4a02 433 * @}
AnnaBridge 161:aa5281ff4a02 434 */
AnnaBridge 161:aa5281ff4a02 435
AnnaBridge 161:aa5281ff4a02 436 /** @defgroup DSI_LP_VACT DSI LP VACT
AnnaBridge 161:aa5281ff4a02 437 * @{
AnnaBridge 161:aa5281ff4a02 438 */
AnnaBridge 161:aa5281ff4a02 439 #define DSI_LP_VACT_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 440 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
AnnaBridge 161:aa5281ff4a02 441 /**
AnnaBridge 161:aa5281ff4a02 442 * @}
AnnaBridge 161:aa5281ff4a02 443 */
AnnaBridge 161:aa5281ff4a02 444
AnnaBridge 161:aa5281ff4a02 445 /** @defgroup DSI_LP_VFP DSI LP VFP
AnnaBridge 161:aa5281ff4a02 446 * @{
AnnaBridge 161:aa5281ff4a02 447 */
AnnaBridge 161:aa5281ff4a02 448 #define DSI_LP_VFP_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 449 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
AnnaBridge 161:aa5281ff4a02 450 /**
AnnaBridge 161:aa5281ff4a02 451 * @}
AnnaBridge 161:aa5281ff4a02 452 */
AnnaBridge 161:aa5281ff4a02 453
AnnaBridge 161:aa5281ff4a02 454 /** @defgroup DSI_LP_VBP DSI LP VBP
AnnaBridge 161:aa5281ff4a02 455 * @{
AnnaBridge 161:aa5281ff4a02 456 */
AnnaBridge 161:aa5281ff4a02 457 #define DSI_LP_VBP_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 458 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
AnnaBridge 161:aa5281ff4a02 459 /**
AnnaBridge 161:aa5281ff4a02 460 * @}
AnnaBridge 161:aa5281ff4a02 461 */
AnnaBridge 161:aa5281ff4a02 462
AnnaBridge 161:aa5281ff4a02 463 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
AnnaBridge 161:aa5281ff4a02 464 * @{
AnnaBridge 161:aa5281ff4a02 465 */
AnnaBridge 161:aa5281ff4a02 466 #define DSI_LP_VSYNC_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 467 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
AnnaBridge 161:aa5281ff4a02 468 /**
AnnaBridge 161:aa5281ff4a02 469 * @}
AnnaBridge 161:aa5281ff4a02 470 */
AnnaBridge 161:aa5281ff4a02 471
AnnaBridge 161:aa5281ff4a02 472 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
AnnaBridge 161:aa5281ff4a02 473 * @{
AnnaBridge 161:aa5281ff4a02 474 */
AnnaBridge 161:aa5281ff4a02 475 #define DSI_FBTAA_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 476 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
AnnaBridge 161:aa5281ff4a02 477 /**
AnnaBridge 161:aa5281ff4a02 478 * @}
AnnaBridge 161:aa5281ff4a02 479 */
AnnaBridge 161:aa5281ff4a02 480
AnnaBridge 161:aa5281ff4a02 481 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
AnnaBridge 161:aa5281ff4a02 482 * @{
AnnaBridge 161:aa5281ff4a02 483 */
AnnaBridge 161:aa5281ff4a02 484 #define DSI_TE_DSILINK 0x00000000U
AnnaBridge 161:aa5281ff4a02 485 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
AnnaBridge 161:aa5281ff4a02 486 /**
AnnaBridge 161:aa5281ff4a02 487 * @}
AnnaBridge 161:aa5281ff4a02 488 */
AnnaBridge 161:aa5281ff4a02 489
AnnaBridge 161:aa5281ff4a02 490 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
AnnaBridge 161:aa5281ff4a02 491 * @{
AnnaBridge 161:aa5281ff4a02 492 */
AnnaBridge 161:aa5281ff4a02 493 #define DSI_TE_RISING_EDGE 0x00000000U
AnnaBridge 161:aa5281ff4a02 494 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
AnnaBridge 161:aa5281ff4a02 495 /**
AnnaBridge 161:aa5281ff4a02 496 * @}
AnnaBridge 161:aa5281ff4a02 497 */
AnnaBridge 161:aa5281ff4a02 498
AnnaBridge 161:aa5281ff4a02 499 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
AnnaBridge 161:aa5281ff4a02 500 * @{
AnnaBridge 161:aa5281ff4a02 501 */
AnnaBridge 161:aa5281ff4a02 502 #define DSI_VSYNC_FALLING 0x00000000U
AnnaBridge 161:aa5281ff4a02 503 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
AnnaBridge 161:aa5281ff4a02 504 /**
AnnaBridge 161:aa5281ff4a02 505 * @}
AnnaBridge 161:aa5281ff4a02 506 */
AnnaBridge 161:aa5281ff4a02 507
AnnaBridge 161:aa5281ff4a02 508 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
AnnaBridge 161:aa5281ff4a02 509 * @{
AnnaBridge 161:aa5281ff4a02 510 */
AnnaBridge 161:aa5281ff4a02 511 #define DSI_AR_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 512 #define DSI_AR_ENABLE DSI_WCFGR_AR
AnnaBridge 161:aa5281ff4a02 513 /**
AnnaBridge 161:aa5281ff4a02 514 * @}
AnnaBridge 161:aa5281ff4a02 515 */
AnnaBridge 161:aa5281ff4a02 516
AnnaBridge 161:aa5281ff4a02 517 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
AnnaBridge 161:aa5281ff4a02 518 * @{
AnnaBridge 161:aa5281ff4a02 519 */
AnnaBridge 161:aa5281ff4a02 520 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 521 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
AnnaBridge 161:aa5281ff4a02 522 /**
AnnaBridge 161:aa5281ff4a02 523 * @}
AnnaBridge 161:aa5281ff4a02 524 */
AnnaBridge 161:aa5281ff4a02 525
AnnaBridge 161:aa5281ff4a02 526 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
AnnaBridge 161:aa5281ff4a02 527 * @{
AnnaBridge 161:aa5281ff4a02 528 */
AnnaBridge 161:aa5281ff4a02 529 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 530 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
AnnaBridge 161:aa5281ff4a02 531 /**
AnnaBridge 161:aa5281ff4a02 532 * @}
AnnaBridge 161:aa5281ff4a02 533 */
AnnaBridge 161:aa5281ff4a02 534
AnnaBridge 161:aa5281ff4a02 535 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
AnnaBridge 161:aa5281ff4a02 536 * @{
AnnaBridge 161:aa5281ff4a02 537 */
AnnaBridge 161:aa5281ff4a02 538 #define DSI_LP_GSW0P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 539 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
AnnaBridge 161:aa5281ff4a02 540 /**
AnnaBridge 161:aa5281ff4a02 541 * @}
AnnaBridge 161:aa5281ff4a02 542 */
AnnaBridge 161:aa5281ff4a02 543
AnnaBridge 161:aa5281ff4a02 544 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
AnnaBridge 161:aa5281ff4a02 545 * @{
AnnaBridge 161:aa5281ff4a02 546 */
AnnaBridge 161:aa5281ff4a02 547 #define DSI_LP_GSW1P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 548 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
AnnaBridge 161:aa5281ff4a02 549 /**
AnnaBridge 161:aa5281ff4a02 550 * @}
AnnaBridge 161:aa5281ff4a02 551 */
AnnaBridge 161:aa5281ff4a02 552
AnnaBridge 161:aa5281ff4a02 553 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
AnnaBridge 161:aa5281ff4a02 554 * @{
AnnaBridge 161:aa5281ff4a02 555 */
AnnaBridge 161:aa5281ff4a02 556 #define DSI_LP_GSW2P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 557 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
AnnaBridge 161:aa5281ff4a02 558 /**
AnnaBridge 161:aa5281ff4a02 559 * @}
AnnaBridge 161:aa5281ff4a02 560 */
AnnaBridge 161:aa5281ff4a02 561
AnnaBridge 161:aa5281ff4a02 562 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
AnnaBridge 161:aa5281ff4a02 563 * @{
AnnaBridge 161:aa5281ff4a02 564 */
AnnaBridge 161:aa5281ff4a02 565 #define DSI_LP_GSR0P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 566 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
AnnaBridge 161:aa5281ff4a02 567 /**
AnnaBridge 161:aa5281ff4a02 568 * @}
AnnaBridge 161:aa5281ff4a02 569 */
AnnaBridge 161:aa5281ff4a02 570
AnnaBridge 161:aa5281ff4a02 571 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
AnnaBridge 161:aa5281ff4a02 572 * @{
AnnaBridge 161:aa5281ff4a02 573 */
AnnaBridge 161:aa5281ff4a02 574 #define DSI_LP_GSR1P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 575 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
AnnaBridge 161:aa5281ff4a02 576 /**
AnnaBridge 161:aa5281ff4a02 577 * @}
AnnaBridge 161:aa5281ff4a02 578 */
AnnaBridge 161:aa5281ff4a02 579
AnnaBridge 161:aa5281ff4a02 580 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
AnnaBridge 161:aa5281ff4a02 581 * @{
AnnaBridge 161:aa5281ff4a02 582 */
AnnaBridge 161:aa5281ff4a02 583 #define DSI_LP_GSR2P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 584 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
AnnaBridge 161:aa5281ff4a02 585 /**
AnnaBridge 161:aa5281ff4a02 586 * @}
AnnaBridge 161:aa5281ff4a02 587 */
AnnaBridge 161:aa5281ff4a02 588
AnnaBridge 161:aa5281ff4a02 589 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
AnnaBridge 161:aa5281ff4a02 590 * @{
AnnaBridge 161:aa5281ff4a02 591 */
AnnaBridge 161:aa5281ff4a02 592 #define DSI_LP_GLW_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 593 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
AnnaBridge 161:aa5281ff4a02 594 /**
AnnaBridge 161:aa5281ff4a02 595 * @}
AnnaBridge 161:aa5281ff4a02 596 */
AnnaBridge 161:aa5281ff4a02 597
AnnaBridge 161:aa5281ff4a02 598 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
AnnaBridge 161:aa5281ff4a02 599 * @{
AnnaBridge 161:aa5281ff4a02 600 */
AnnaBridge 161:aa5281ff4a02 601 #define DSI_LP_DSW0P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 602 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
AnnaBridge 161:aa5281ff4a02 603 /**
AnnaBridge 161:aa5281ff4a02 604 * @}
AnnaBridge 161:aa5281ff4a02 605 */
AnnaBridge 161:aa5281ff4a02 606
AnnaBridge 161:aa5281ff4a02 607 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
AnnaBridge 161:aa5281ff4a02 608 * @{
AnnaBridge 161:aa5281ff4a02 609 */
AnnaBridge 161:aa5281ff4a02 610 #define DSI_LP_DSW1P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 611 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
AnnaBridge 161:aa5281ff4a02 612 /**
AnnaBridge 161:aa5281ff4a02 613 * @}
AnnaBridge 161:aa5281ff4a02 614 */
AnnaBridge 161:aa5281ff4a02 615
AnnaBridge 161:aa5281ff4a02 616 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
AnnaBridge 161:aa5281ff4a02 617 * @{
AnnaBridge 161:aa5281ff4a02 618 */
AnnaBridge 161:aa5281ff4a02 619 #define DSI_LP_DSR0P_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 620 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
AnnaBridge 161:aa5281ff4a02 621 /**
AnnaBridge 161:aa5281ff4a02 622 * @}
AnnaBridge 161:aa5281ff4a02 623 */
AnnaBridge 161:aa5281ff4a02 624
AnnaBridge 161:aa5281ff4a02 625 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
AnnaBridge 161:aa5281ff4a02 626 * @{
AnnaBridge 161:aa5281ff4a02 627 */
AnnaBridge 161:aa5281ff4a02 628 #define DSI_LP_DLW_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 629 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
AnnaBridge 161:aa5281ff4a02 630 /**
AnnaBridge 161:aa5281ff4a02 631 * @}
AnnaBridge 161:aa5281ff4a02 632 */
AnnaBridge 161:aa5281ff4a02 633
AnnaBridge 161:aa5281ff4a02 634 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
AnnaBridge 161:aa5281ff4a02 635 * @{
AnnaBridge 161:aa5281ff4a02 636 */
AnnaBridge 161:aa5281ff4a02 637 #define DSI_LP_MRDP_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 638 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
AnnaBridge 161:aa5281ff4a02 639 /**
AnnaBridge 161:aa5281ff4a02 640 * @}
AnnaBridge 161:aa5281ff4a02 641 */
AnnaBridge 161:aa5281ff4a02 642
AnnaBridge 161:aa5281ff4a02 643 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
AnnaBridge 161:aa5281ff4a02 644 * @{
AnnaBridge 161:aa5281ff4a02 645 */
AnnaBridge 161:aa5281ff4a02 646 #define DSI_HS_PM_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 647 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
AnnaBridge 161:aa5281ff4a02 648 /**
AnnaBridge 161:aa5281ff4a02 649 * @}
AnnaBridge 161:aa5281ff4a02 650 */
AnnaBridge 161:aa5281ff4a02 651
AnnaBridge 161:aa5281ff4a02 652
AnnaBridge 161:aa5281ff4a02 653 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
AnnaBridge 161:aa5281ff4a02 654 * @{
AnnaBridge 161:aa5281ff4a02 655 */
AnnaBridge 161:aa5281ff4a02 656 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 657 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
AnnaBridge 161:aa5281ff4a02 658 /**
AnnaBridge 161:aa5281ff4a02 659 * @}
AnnaBridge 161:aa5281ff4a02 660 */
AnnaBridge 161:aa5281ff4a02 661
AnnaBridge 161:aa5281ff4a02 662 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
AnnaBridge 161:aa5281ff4a02 663 * @{
AnnaBridge 161:aa5281ff4a02 664 */
AnnaBridge 161:aa5281ff4a02 665 #define DSI_ONE_DATA_LANE 0U
AnnaBridge 161:aa5281ff4a02 666 #define DSI_TWO_DATA_LANES 1U
AnnaBridge 161:aa5281ff4a02 667 /**
AnnaBridge 161:aa5281ff4a02 668 * @}
AnnaBridge 161:aa5281ff4a02 669 */
AnnaBridge 161:aa5281ff4a02 670
AnnaBridge 161:aa5281ff4a02 671 /** @defgroup DSI_FlowControl DSI Flow Control
AnnaBridge 161:aa5281ff4a02 672 * @{
AnnaBridge 161:aa5281ff4a02 673 */
AnnaBridge 161:aa5281ff4a02 674 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
AnnaBridge 161:aa5281ff4a02 675 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
AnnaBridge 161:aa5281ff4a02 676 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
AnnaBridge 161:aa5281ff4a02 677 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
AnnaBridge 161:aa5281ff4a02 678 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
AnnaBridge 161:aa5281ff4a02 679 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
AnnaBridge 161:aa5281ff4a02 680 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
AnnaBridge 161:aa5281ff4a02 681 DSI_FLOW_CONTROL_EOTP_TX)
AnnaBridge 161:aa5281ff4a02 682 /**
AnnaBridge 161:aa5281ff4a02 683 * @}
AnnaBridge 161:aa5281ff4a02 684 */
AnnaBridge 161:aa5281ff4a02 685
AnnaBridge 161:aa5281ff4a02 686 /** @defgroup DSI_Color_Coding DSI Color Coding
AnnaBridge 161:aa5281ff4a02 687 * @{
AnnaBridge 161:aa5281ff4a02 688 */
AnnaBridge 161:aa5281ff4a02 689 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
AnnaBridge 161:aa5281ff4a02 690 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
AnnaBridge 161:aa5281ff4a02 691 #define DSI_RGB888 0x00000005U
AnnaBridge 161:aa5281ff4a02 692 /**
AnnaBridge 161:aa5281ff4a02 693 * @}
AnnaBridge 161:aa5281ff4a02 694 */
AnnaBridge 161:aa5281ff4a02 695
AnnaBridge 161:aa5281ff4a02 696 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
AnnaBridge 161:aa5281ff4a02 697 * @{
AnnaBridge 161:aa5281ff4a02 698 */
AnnaBridge 161:aa5281ff4a02 699 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
AnnaBridge 161:aa5281ff4a02 700 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
AnnaBridge 161:aa5281ff4a02 701 /**
AnnaBridge 161:aa5281ff4a02 702 * @}
AnnaBridge 161:aa5281ff4a02 703 */
AnnaBridge 161:aa5281ff4a02 704
AnnaBridge 161:aa5281ff4a02 705 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
AnnaBridge 161:aa5281ff4a02 706 * @{
AnnaBridge 161:aa5281ff4a02 707 */
AnnaBridge 161:aa5281ff4a02 708 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge 161:aa5281ff4a02 709 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
AnnaBridge 161:aa5281ff4a02 710 /**
AnnaBridge 161:aa5281ff4a02 711 * @}
AnnaBridge 161:aa5281ff4a02 712 */
AnnaBridge 161:aa5281ff4a02 713
AnnaBridge 161:aa5281ff4a02 714 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
AnnaBridge 161:aa5281ff4a02 715 * @{
AnnaBridge 161:aa5281ff4a02 716 */
AnnaBridge 161:aa5281ff4a02 717 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge 161:aa5281ff4a02 718 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
AnnaBridge 161:aa5281ff4a02 719 /**
AnnaBridge 161:aa5281ff4a02 720 * @}
AnnaBridge 161:aa5281ff4a02 721 */
AnnaBridge 161:aa5281ff4a02 722
AnnaBridge 161:aa5281ff4a02 723 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
AnnaBridge 161:aa5281ff4a02 724 * @{
AnnaBridge 161:aa5281ff4a02 725 */
AnnaBridge 161:aa5281ff4a02 726 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
AnnaBridge 161:aa5281ff4a02 727 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
AnnaBridge 161:aa5281ff4a02 728 /**
AnnaBridge 161:aa5281ff4a02 729 * @}
AnnaBridge 161:aa5281ff4a02 730 */
AnnaBridge 161:aa5281ff4a02 731
AnnaBridge 161:aa5281ff4a02 732 /** @defgroup DSI_PLL_IDF DSI PLL IDF
AnnaBridge 161:aa5281ff4a02 733 * @{
AnnaBridge 161:aa5281ff4a02 734 */
AnnaBridge 161:aa5281ff4a02 735 #define DSI_PLL_IN_DIV1 0x00000001U
AnnaBridge 161:aa5281ff4a02 736 #define DSI_PLL_IN_DIV2 0x00000002U
AnnaBridge 161:aa5281ff4a02 737 #define DSI_PLL_IN_DIV3 0x00000003U
AnnaBridge 161:aa5281ff4a02 738 #define DSI_PLL_IN_DIV4 0x00000004U
AnnaBridge 161:aa5281ff4a02 739 #define DSI_PLL_IN_DIV5 0x00000005U
AnnaBridge 161:aa5281ff4a02 740 #define DSI_PLL_IN_DIV6 0x00000006U
AnnaBridge 161:aa5281ff4a02 741 #define DSI_PLL_IN_DIV7 0x00000007U
AnnaBridge 161:aa5281ff4a02 742 /**
AnnaBridge 161:aa5281ff4a02 743 * @}
AnnaBridge 161:aa5281ff4a02 744 */
AnnaBridge 161:aa5281ff4a02 745
AnnaBridge 161:aa5281ff4a02 746 /** @defgroup DSI_PLL_ODF DSI PLL ODF
AnnaBridge 161:aa5281ff4a02 747 * @{
AnnaBridge 161:aa5281ff4a02 748 */
AnnaBridge 161:aa5281ff4a02 749 #define DSI_PLL_OUT_DIV1 0x00000000U
AnnaBridge 161:aa5281ff4a02 750 #define DSI_PLL_OUT_DIV2 0x00000001U
AnnaBridge 161:aa5281ff4a02 751 #define DSI_PLL_OUT_DIV4 0x00000002U
AnnaBridge 161:aa5281ff4a02 752 #define DSI_PLL_OUT_DIV8 0x00000003U
AnnaBridge 161:aa5281ff4a02 753 /**
AnnaBridge 161:aa5281ff4a02 754 * @}
AnnaBridge 161:aa5281ff4a02 755 */
AnnaBridge 161:aa5281ff4a02 756
AnnaBridge 161:aa5281ff4a02 757 /** @defgroup DSI_Flags DSI Flags
AnnaBridge 161:aa5281ff4a02 758 * @{
AnnaBridge 161:aa5281ff4a02 759 */
AnnaBridge 161:aa5281ff4a02 760 #define DSI_FLAG_TE DSI_WISR_TEIF
AnnaBridge 161:aa5281ff4a02 761 #define DSI_FLAG_ER DSI_WISR_ERIF
AnnaBridge 161:aa5281ff4a02 762 #define DSI_FLAG_BUSY DSI_WISR_BUSY
AnnaBridge 161:aa5281ff4a02 763 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
AnnaBridge 161:aa5281ff4a02 764 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
AnnaBridge 161:aa5281ff4a02 765 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
AnnaBridge 161:aa5281ff4a02 766 #define DSI_FLAG_RRS DSI_WISR_RRS
AnnaBridge 161:aa5281ff4a02 767 #define DSI_FLAG_RR DSI_WISR_RRIF
AnnaBridge 161:aa5281ff4a02 768 /**
AnnaBridge 161:aa5281ff4a02 769 * @}
AnnaBridge 161:aa5281ff4a02 770 */
AnnaBridge 161:aa5281ff4a02 771
AnnaBridge 161:aa5281ff4a02 772 /** @defgroup DSI_Interrupts DSI Interrupts
AnnaBridge 161:aa5281ff4a02 773 * @{
AnnaBridge 161:aa5281ff4a02 774 */
AnnaBridge 161:aa5281ff4a02 775 #define DSI_IT_TE DSI_WIER_TEIE
AnnaBridge 161:aa5281ff4a02 776 #define DSI_IT_ER DSI_WIER_ERIE
AnnaBridge 161:aa5281ff4a02 777 #define DSI_IT_PLLL DSI_WIER_PLLLIE
AnnaBridge 161:aa5281ff4a02 778 #define DSI_IT_PLLU DSI_WIER_PLLUIE
AnnaBridge 161:aa5281ff4a02 779 #define DSI_IT_RR DSI_WIER_RRIE
AnnaBridge 161:aa5281ff4a02 780 /**
AnnaBridge 161:aa5281ff4a02 781 * @}
AnnaBridge 161:aa5281ff4a02 782 */
AnnaBridge 161:aa5281ff4a02 783
AnnaBridge 161:aa5281ff4a02 784 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
AnnaBridge 161:aa5281ff4a02 785 * @{
AnnaBridge 161:aa5281ff4a02 786 */
AnnaBridge 161:aa5281ff4a02 787 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
AnnaBridge 161:aa5281ff4a02 788 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
AnnaBridge 161:aa5281ff4a02 789 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
AnnaBridge 161:aa5281ff4a02 790 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
AnnaBridge 161:aa5281ff4a02 791 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
AnnaBridge 161:aa5281ff4a02 792 /**
AnnaBridge 161:aa5281ff4a02 793 * @}
AnnaBridge 161:aa5281ff4a02 794 */
AnnaBridge 161:aa5281ff4a02 795
AnnaBridge 161:aa5281ff4a02 796 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
AnnaBridge 161:aa5281ff4a02 797 * @{
AnnaBridge 161:aa5281ff4a02 798 */
AnnaBridge 161:aa5281ff4a02 799 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
AnnaBridge 161:aa5281ff4a02 800 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
AnnaBridge 161:aa5281ff4a02 801 /**
AnnaBridge 161:aa5281ff4a02 802 * @}
AnnaBridge 161:aa5281ff4a02 803 */
AnnaBridge 161:aa5281ff4a02 804
AnnaBridge 161:aa5281ff4a02 805 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
AnnaBridge 161:aa5281ff4a02 806 * @{
AnnaBridge 161:aa5281ff4a02 807 */
AnnaBridge 161:aa5281ff4a02 808 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
AnnaBridge 161:aa5281ff4a02 809 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
AnnaBridge 161:aa5281ff4a02 810 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
AnnaBridge 161:aa5281ff4a02 811 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
AnnaBridge 161:aa5281ff4a02 812 /**
AnnaBridge 161:aa5281ff4a02 813 * @}
AnnaBridge 161:aa5281ff4a02 814 */
AnnaBridge 161:aa5281ff4a02 815
AnnaBridge 161:aa5281ff4a02 816 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
AnnaBridge 161:aa5281ff4a02 817 * @{
AnnaBridge 161:aa5281ff4a02 818 */
AnnaBridge 161:aa5281ff4a02 819 #define HAL_DSI_ERROR_NONE 0U
AnnaBridge 161:aa5281ff4a02 820 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
AnnaBridge 161:aa5281ff4a02 821 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
AnnaBridge 161:aa5281ff4a02 822 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
AnnaBridge 161:aa5281ff4a02 823 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
AnnaBridge 161:aa5281ff4a02 824 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
AnnaBridge 161:aa5281ff4a02 825 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
AnnaBridge 161:aa5281ff4a02 826 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
AnnaBridge 161:aa5281ff4a02 827 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
AnnaBridge 161:aa5281ff4a02 828 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
AnnaBridge 161:aa5281ff4a02 829 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
AnnaBridge 161:aa5281ff4a02 830 /**
AnnaBridge 161:aa5281ff4a02 831 * @}
AnnaBridge 161:aa5281ff4a02 832 */
AnnaBridge 161:aa5281ff4a02 833
AnnaBridge 161:aa5281ff4a02 834 /** @defgroup DSI_Lane_Group DSI Lane Group
AnnaBridge 161:aa5281ff4a02 835 * @{
AnnaBridge 161:aa5281ff4a02 836 */
AnnaBridge 161:aa5281ff4a02 837 #define DSI_CLOCK_LANE 0x00000000U
AnnaBridge 161:aa5281ff4a02 838 #define DSI_DATA_LANES 0x00000001U
AnnaBridge 161:aa5281ff4a02 839 /**
AnnaBridge 161:aa5281ff4a02 840 * @}
AnnaBridge 161:aa5281ff4a02 841 */
AnnaBridge 161:aa5281ff4a02 842
AnnaBridge 161:aa5281ff4a02 843 /** @defgroup DSI_Communication_Delay DSI Communication Delay
AnnaBridge 161:aa5281ff4a02 844 * @{
AnnaBridge 161:aa5281ff4a02 845 */
AnnaBridge 161:aa5281ff4a02 846 #define DSI_SLEW_RATE_HSTX 0x00000000U
AnnaBridge 161:aa5281ff4a02 847 #define DSI_SLEW_RATE_LPTX 0x00000001U
AnnaBridge 161:aa5281ff4a02 848 #define DSI_HS_DELAY 0x00000002U
AnnaBridge 161:aa5281ff4a02 849 /**
AnnaBridge 161:aa5281ff4a02 850 * @}
AnnaBridge 161:aa5281ff4a02 851 */
AnnaBridge 161:aa5281ff4a02 852
AnnaBridge 161:aa5281ff4a02 853 /** @defgroup DSI_CustomLane DSI CustomLane
AnnaBridge 161:aa5281ff4a02 854 * @{
AnnaBridge 161:aa5281ff4a02 855 */
AnnaBridge 161:aa5281ff4a02 856 #define DSI_SWAP_LANE_PINS 0x00000000U
AnnaBridge 161:aa5281ff4a02 857 #define DSI_INVERT_HS_SIGNAL 0x00000001U
AnnaBridge 161:aa5281ff4a02 858 /**
AnnaBridge 161:aa5281ff4a02 859 * @}
AnnaBridge 161:aa5281ff4a02 860 */
AnnaBridge 161:aa5281ff4a02 861
AnnaBridge 161:aa5281ff4a02 862 /** @defgroup DSI_Lane_Select DSI Lane Select
AnnaBridge 161:aa5281ff4a02 863 * @{
AnnaBridge 161:aa5281ff4a02 864 */
AnnaBridge 161:aa5281ff4a02 865 #define DSI_CLK_LANE 0x00000000U
AnnaBridge 161:aa5281ff4a02 866 #define DSI_DATA_LANE0 0x00000001U
AnnaBridge 161:aa5281ff4a02 867 #define DSI_DATA_LANE1 0x00000002U
AnnaBridge 161:aa5281ff4a02 868 /**
AnnaBridge 161:aa5281ff4a02 869 * @}
AnnaBridge 161:aa5281ff4a02 870 */
AnnaBridge 161:aa5281ff4a02 871
AnnaBridge 161:aa5281ff4a02 872 /** @defgroup DSI_PHY_Timing DSI PHY Timing
AnnaBridge 161:aa5281ff4a02 873 * @{
AnnaBridge 161:aa5281ff4a02 874 */
AnnaBridge 161:aa5281ff4a02 875 #define DSI_TCLK_POST 0x00000000U
AnnaBridge 161:aa5281ff4a02 876 #define DSI_TLPX_CLK 0x00000001U
AnnaBridge 161:aa5281ff4a02 877 #define DSI_THS_EXIT 0x00000002U
AnnaBridge 161:aa5281ff4a02 878 #define DSI_TLPX_DATA 0x00000003U
AnnaBridge 161:aa5281ff4a02 879 #define DSI_THS_ZERO 0x00000004U
AnnaBridge 161:aa5281ff4a02 880 #define DSI_THS_TRAIL 0x00000005U
AnnaBridge 161:aa5281ff4a02 881 #define DSI_THS_PREPARE 0x00000006U
AnnaBridge 161:aa5281ff4a02 882 #define DSI_TCLK_ZERO 0x00000007U
AnnaBridge 161:aa5281ff4a02 883 #define DSI_TCLK_PREPARE 0x00000008U
AnnaBridge 161:aa5281ff4a02 884 /**
AnnaBridge 161:aa5281ff4a02 885 * @}
AnnaBridge 161:aa5281ff4a02 886 */
AnnaBridge 161:aa5281ff4a02 887
AnnaBridge 161:aa5281ff4a02 888 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 889 /**
AnnaBridge 161:aa5281ff4a02 890 * @brief Reset DSI handle state.
AnnaBridge 161:aa5281ff4a02 891 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 892 * @retval None
AnnaBridge 161:aa5281ff4a02 893 */
AnnaBridge 161:aa5281ff4a02 894 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
AnnaBridge 161:aa5281ff4a02 895
AnnaBridge 161:aa5281ff4a02 896 /**
AnnaBridge 161:aa5281ff4a02 897 * @brief Enables the DSI host.
AnnaBridge 161:aa5281ff4a02 898 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 899 * @retval None.
AnnaBridge 161:aa5281ff4a02 900 */
AnnaBridge 161:aa5281ff4a02 901 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 902 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 903 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge 161:aa5281ff4a02 904 /* Delay after an DSI Host enabling */ \
AnnaBridge 161:aa5281ff4a02 905 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge 161:aa5281ff4a02 906 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 907 }while(0U)
AnnaBridge 161:aa5281ff4a02 908
AnnaBridge 161:aa5281ff4a02 909 /**
AnnaBridge 161:aa5281ff4a02 910 * @brief Disables the DSI host.
AnnaBridge 161:aa5281ff4a02 911 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 912 * @retval None.
AnnaBridge 161:aa5281ff4a02 913 */
AnnaBridge 161:aa5281ff4a02 914 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 915 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 916 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge 161:aa5281ff4a02 917 /* Delay after an DSI Host disabling */ \
AnnaBridge 161:aa5281ff4a02 918 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge 161:aa5281ff4a02 919 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 920 }while(0U)
AnnaBridge 161:aa5281ff4a02 921
AnnaBridge 161:aa5281ff4a02 922 /**
AnnaBridge 161:aa5281ff4a02 923 * @brief Enables the DSI wrapper.
AnnaBridge 161:aa5281ff4a02 924 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 925 * @retval None.
AnnaBridge 161:aa5281ff4a02 926 */
AnnaBridge 161:aa5281ff4a02 927 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 928 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 929 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge 161:aa5281ff4a02 930 /* Delay after an DSI warpper enabling */ \
AnnaBridge 161:aa5281ff4a02 931 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge 161:aa5281ff4a02 932 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 933 }while(0U)
AnnaBridge 161:aa5281ff4a02 934
AnnaBridge 161:aa5281ff4a02 935 /**
AnnaBridge 161:aa5281ff4a02 936 * @brief Disable the DSI wrapper.
AnnaBridge 161:aa5281ff4a02 937 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 938 * @retval None.
AnnaBridge 161:aa5281ff4a02 939 */
AnnaBridge 161:aa5281ff4a02 940 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 941 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 942 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge 161:aa5281ff4a02 943 /* Delay after an DSI warpper disabling*/ \
AnnaBridge 161:aa5281ff4a02 944 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge 161:aa5281ff4a02 945 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 946 }while(0U)
AnnaBridge 161:aa5281ff4a02 947
AnnaBridge 161:aa5281ff4a02 948 /**
AnnaBridge 161:aa5281ff4a02 949 * @brief Enables the DSI PLL.
AnnaBridge 161:aa5281ff4a02 950 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 951 * @retval None.
AnnaBridge 161:aa5281ff4a02 952 */
AnnaBridge 161:aa5281ff4a02 953 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 954 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 955 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge 161:aa5281ff4a02 956 /* Delay after an DSI PLL enabling */ \
AnnaBridge 161:aa5281ff4a02 957 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge 161:aa5281ff4a02 958 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 959 }while(0U)
AnnaBridge 161:aa5281ff4a02 960
AnnaBridge 161:aa5281ff4a02 961 /**
AnnaBridge 161:aa5281ff4a02 962 * @brief Disables the DSI PLL.
AnnaBridge 161:aa5281ff4a02 963 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 964 * @retval None.
AnnaBridge 161:aa5281ff4a02 965 */
AnnaBridge 161:aa5281ff4a02 966 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 967 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 968 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge 161:aa5281ff4a02 969 /* Delay after an DSI PLL disabling */ \
AnnaBridge 161:aa5281ff4a02 970 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge 161:aa5281ff4a02 971 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 972 }while(0U)
AnnaBridge 161:aa5281ff4a02 973
AnnaBridge 161:aa5281ff4a02 974 /**
AnnaBridge 161:aa5281ff4a02 975 * @brief Enables the DSI regulator.
AnnaBridge 161:aa5281ff4a02 976 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 977 * @retval None.
AnnaBridge 161:aa5281ff4a02 978 */
AnnaBridge 161:aa5281ff4a02 979 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 980 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 981 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge 161:aa5281ff4a02 982 /* Delay after an DSI regulator enabling */ \
AnnaBridge 161:aa5281ff4a02 983 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge 161:aa5281ff4a02 984 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 985 }while(0U)
AnnaBridge 161:aa5281ff4a02 986
AnnaBridge 161:aa5281ff4a02 987 /**
AnnaBridge 161:aa5281ff4a02 988 * @brief Disables the DSI regulator.
AnnaBridge 161:aa5281ff4a02 989 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 990 * @retval None.
AnnaBridge 161:aa5281ff4a02 991 */
AnnaBridge 161:aa5281ff4a02 992 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
AnnaBridge 161:aa5281ff4a02 993 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 161:aa5281ff4a02 994 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge 161:aa5281ff4a02 995 /* Delay after an DSI regulator disabling */ \
AnnaBridge 161:aa5281ff4a02 996 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge 161:aa5281ff4a02 997 UNUSED(tmpreg); \
AnnaBridge 161:aa5281ff4a02 998 }while(0U)
AnnaBridge 161:aa5281ff4a02 999
AnnaBridge 161:aa5281ff4a02 1000 /**
AnnaBridge 161:aa5281ff4a02 1001 * @brief Get the DSI pending flags.
AnnaBridge 161:aa5281ff4a02 1002 * @param __HANDLE__: DSI handle.
AnnaBridge 161:aa5281ff4a02 1003 * @param __FLAG__: Get the specified flag.
AnnaBridge 161:aa5281ff4a02 1004 * This parameter can be any combination of the following values:
AnnaBridge 161:aa5281ff4a02 1005 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1006 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1007 * @arg DSI_FLAG_BUSY : Busy Flag
AnnaBridge 161:aa5281ff4a02 1008 * @arg DSI_FLAG_PLLLS: PLL Lock Status
AnnaBridge 161:aa5281ff4a02 1009 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1010 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1011 * @arg DSI_FLAG_RRS : Regulator Ready Flag
AnnaBridge 161:aa5281ff4a02 1012 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1013 * @retval The state of FLAG (SET or RESET).
AnnaBridge 161:aa5281ff4a02 1014 */
AnnaBridge 161:aa5281ff4a02 1015 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
AnnaBridge 161:aa5281ff4a02 1016
AnnaBridge 161:aa5281ff4a02 1017 /**
AnnaBridge 161:aa5281ff4a02 1018 * @brief Clears the DSI pending flags.
AnnaBridge 161:aa5281ff4a02 1019 * @param __HANDLE__: DSI handle.
AnnaBridge 161:aa5281ff4a02 1020 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 161:aa5281ff4a02 1021 * This parameter can be any combination of the following values:
AnnaBridge 161:aa5281ff4a02 1022 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1023 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1024 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1025 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1026 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge 161:aa5281ff4a02 1027 * @retval None
AnnaBridge 161:aa5281ff4a02 1028 */
AnnaBridge 161:aa5281ff4a02 1029 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
AnnaBridge 161:aa5281ff4a02 1030
AnnaBridge 161:aa5281ff4a02 1031 /**
AnnaBridge 161:aa5281ff4a02 1032 * @brief Enables the specified DSI interrupts.
AnnaBridge 161:aa5281ff4a02 1033 * @param __HANDLE__: DSI handle.
AnnaBridge 161:aa5281ff4a02 1034 * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
AnnaBridge 161:aa5281ff4a02 1035 * This parameter can be any combination of the following values:
AnnaBridge 161:aa5281ff4a02 1036 * @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge 161:aa5281ff4a02 1037 * @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge 161:aa5281ff4a02 1038 * @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge 161:aa5281ff4a02 1039 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge 161:aa5281ff4a02 1040 * @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge 161:aa5281ff4a02 1041 * @retval None
AnnaBridge 161:aa5281ff4a02 1042 */
AnnaBridge 161:aa5281ff4a02 1043 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
AnnaBridge 161:aa5281ff4a02 1044
AnnaBridge 161:aa5281ff4a02 1045 /**
AnnaBridge 161:aa5281ff4a02 1046 * @brief Disables the specified DSI interrupts.
AnnaBridge 161:aa5281ff4a02 1047 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 1048 * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
AnnaBridge 161:aa5281ff4a02 1049 * This parameter can be any combination of the following values:
AnnaBridge 161:aa5281ff4a02 1050 * @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge 161:aa5281ff4a02 1051 * @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge 161:aa5281ff4a02 1052 * @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge 161:aa5281ff4a02 1053 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge 161:aa5281ff4a02 1054 * @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge 161:aa5281ff4a02 1055 * @retval None
AnnaBridge 161:aa5281ff4a02 1056 */
AnnaBridge 161:aa5281ff4a02 1057 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
AnnaBridge 161:aa5281ff4a02 1058
AnnaBridge 161:aa5281ff4a02 1059 /**
AnnaBridge 161:aa5281ff4a02 1060 * @brief Checks whether the specified DSI interrupt source is enabled or not.
AnnaBridge 161:aa5281ff4a02 1061 * @param __HANDLE__: DSI handle
AnnaBridge 161:aa5281ff4a02 1062 * @param __INTERRUPT__: specifies the DSI interrupt source to check.
AnnaBridge 161:aa5281ff4a02 1063 * This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 1064 * @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge 161:aa5281ff4a02 1065 * @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge 161:aa5281ff4a02 1066 * @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge 161:aa5281ff4a02 1067 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge 161:aa5281ff4a02 1068 * @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge 161:aa5281ff4a02 1069 * @retval The state of INTERRUPT (SET or RESET).
AnnaBridge 161:aa5281ff4a02 1070 */
AnnaBridge 161:aa5281ff4a02 1071 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
AnnaBridge 161:aa5281ff4a02 1072
AnnaBridge 161:aa5281ff4a02 1073 /* Exported functions --------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1074 /** @defgroup DSI_Exported_Functions DSI Exported Functions
AnnaBridge 161:aa5281ff4a02 1075 * @{
AnnaBridge 161:aa5281ff4a02 1076 */
AnnaBridge 161:aa5281ff4a02 1077 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
AnnaBridge 161:aa5281ff4a02 1078 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1079 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1080 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1081
AnnaBridge 161:aa5281ff4a02 1082 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1083 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1084 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1085 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1086
AnnaBridge 161:aa5281ff4a02 1087 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
AnnaBridge 161:aa5281ff4a02 1088 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
AnnaBridge 161:aa5281ff4a02 1089 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
AnnaBridge 161:aa5281ff4a02 1090 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
AnnaBridge 161:aa5281ff4a02 1091 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
AnnaBridge 161:aa5281ff4a02 1092 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
AnnaBridge 161:aa5281ff4a02 1093 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
AnnaBridge 161:aa5281ff4a02 1094 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1095 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1096 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1097 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
AnnaBridge 161:aa5281ff4a02 1098 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
AnnaBridge 161:aa5281ff4a02 1099 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge 161:aa5281ff4a02 1100 uint32_t ChannelID,
AnnaBridge 161:aa5281ff4a02 1101 uint32_t Mode,
AnnaBridge 161:aa5281ff4a02 1102 uint32_t Param1,
AnnaBridge 161:aa5281ff4a02 1103 uint32_t Param2);
AnnaBridge 161:aa5281ff4a02 1104 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge 161:aa5281ff4a02 1105 uint32_t ChannelID,
AnnaBridge 161:aa5281ff4a02 1106 uint32_t Mode,
AnnaBridge 161:aa5281ff4a02 1107 uint32_t NbParams,
AnnaBridge 161:aa5281ff4a02 1108 uint32_t Param1,
AnnaBridge 161:aa5281ff4a02 1109 uint8_t* ParametersTable);
AnnaBridge 161:aa5281ff4a02 1110 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
AnnaBridge 161:aa5281ff4a02 1111 uint32_t ChannelNbr,
AnnaBridge 161:aa5281ff4a02 1112 uint8_t* Array,
AnnaBridge 161:aa5281ff4a02 1113 uint32_t Size,
AnnaBridge 161:aa5281ff4a02 1114 uint32_t Mode,
AnnaBridge 161:aa5281ff4a02 1115 uint32_t DCSCmd,
AnnaBridge 161:aa5281ff4a02 1116 uint8_t* ParametersTable);
AnnaBridge 161:aa5281ff4a02 1117 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1118 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1119 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1120 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1121
AnnaBridge 161:aa5281ff4a02 1122 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
AnnaBridge 161:aa5281ff4a02 1123 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1124
AnnaBridge 161:aa5281ff4a02 1125 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
AnnaBridge 161:aa5281ff4a02 1126 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
AnnaBridge 161:aa5281ff4a02 1127 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1128 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1129 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
AnnaBridge 161:aa5281ff4a02 1130 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1131 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1132 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1133 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1134 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge 161:aa5281ff4a02 1135
AnnaBridge 161:aa5281ff4a02 1136 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1137 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
AnnaBridge 161:aa5281ff4a02 1138 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
AnnaBridge 161:aa5281ff4a02 1139 /**
AnnaBridge 161:aa5281ff4a02 1140 * @}
AnnaBridge 161:aa5281ff4a02 1141 */
AnnaBridge 161:aa5281ff4a02 1142
AnnaBridge 161:aa5281ff4a02 1143 /* Private types -------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1144 /** @defgroup DSI_Private_Types DSI Private Types
AnnaBridge 161:aa5281ff4a02 1145 * @{
AnnaBridge 161:aa5281ff4a02 1146 */
AnnaBridge 161:aa5281ff4a02 1147
AnnaBridge 161:aa5281ff4a02 1148 /**
AnnaBridge 161:aa5281ff4a02 1149 * @}
AnnaBridge 161:aa5281ff4a02 1150 */
AnnaBridge 161:aa5281ff4a02 1151
AnnaBridge 161:aa5281ff4a02 1152 /* Private defines -----------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1153 /** @defgroup DSI_Private_Defines DSI Private Defines
AnnaBridge 161:aa5281ff4a02 1154 * @{
AnnaBridge 161:aa5281ff4a02 1155 */
AnnaBridge 161:aa5281ff4a02 1156
AnnaBridge 161:aa5281ff4a02 1157 /**
AnnaBridge 161:aa5281ff4a02 1158 * @}
AnnaBridge 161:aa5281ff4a02 1159 */
AnnaBridge 161:aa5281ff4a02 1160
AnnaBridge 161:aa5281ff4a02 1161 /* Private variables ---------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1162 /** @defgroup DSI_Private_Variables DSI Private Variables
AnnaBridge 161:aa5281ff4a02 1163 * @{
AnnaBridge 161:aa5281ff4a02 1164 */
AnnaBridge 161:aa5281ff4a02 1165
AnnaBridge 161:aa5281ff4a02 1166 /**
AnnaBridge 161:aa5281ff4a02 1167 * @}
AnnaBridge 161:aa5281ff4a02 1168 */
AnnaBridge 161:aa5281ff4a02 1169
AnnaBridge 161:aa5281ff4a02 1170 /* Private constants ---------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1171 /** @defgroup DSI_Private_Constants DSI Private Constants
AnnaBridge 161:aa5281ff4a02 1172 * @{
AnnaBridge 161:aa5281ff4a02 1173 */
AnnaBridge 161:aa5281ff4a02 1174 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
AnnaBridge 161:aa5281ff4a02 1175 /**
AnnaBridge 161:aa5281ff4a02 1176 * @}
AnnaBridge 161:aa5281ff4a02 1177 */
AnnaBridge 161:aa5281ff4a02 1178
AnnaBridge 161:aa5281ff4a02 1179 /* Private macros ------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1180 /** @defgroup DSI_Private_Macros DSI Private Macros
AnnaBridge 161:aa5281ff4a02 1181 * @{
AnnaBridge 161:aa5281ff4a02 1182 */
AnnaBridge 161:aa5281ff4a02 1183 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
AnnaBridge 161:aa5281ff4a02 1184 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
AnnaBridge 161:aa5281ff4a02 1185 ((IDF) == DSI_PLL_IN_DIV2) || \
AnnaBridge 161:aa5281ff4a02 1186 ((IDF) == DSI_PLL_IN_DIV3) || \
AnnaBridge 161:aa5281ff4a02 1187 ((IDF) == DSI_PLL_IN_DIV4) || \
AnnaBridge 161:aa5281ff4a02 1188 ((IDF) == DSI_PLL_IN_DIV5) || \
AnnaBridge 161:aa5281ff4a02 1189 ((IDF) == DSI_PLL_IN_DIV6) || \
AnnaBridge 161:aa5281ff4a02 1190 ((IDF) == DSI_PLL_IN_DIV7))
AnnaBridge 161:aa5281ff4a02 1191 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
AnnaBridge 161:aa5281ff4a02 1192 ((ODF) == DSI_PLL_OUT_DIV2) || \
AnnaBridge 161:aa5281ff4a02 1193 ((ODF) == DSI_PLL_OUT_DIV4) || \
AnnaBridge 161:aa5281ff4a02 1194 ((ODF) == DSI_PLL_OUT_DIV8))
AnnaBridge 161:aa5281ff4a02 1195 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
AnnaBridge 161:aa5281ff4a02 1196 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
AnnaBridge 161:aa5281ff4a02 1197 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
AnnaBridge 161:aa5281ff4a02 1198 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
AnnaBridge 161:aa5281ff4a02 1199 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
AnnaBridge 161:aa5281ff4a02 1200 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
AnnaBridge 161:aa5281ff4a02 1201 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
AnnaBridge 161:aa5281ff4a02 1202 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
AnnaBridge 161:aa5281ff4a02 1203 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
AnnaBridge 161:aa5281ff4a02 1204 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
AnnaBridge 161:aa5281ff4a02 1205 ((VideoModeType) == DSI_VID_MODE_BURST))
AnnaBridge 161:aa5281ff4a02 1206 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
AnnaBridge 161:aa5281ff4a02 1207 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
AnnaBridge 161:aa5281ff4a02 1208 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
AnnaBridge 161:aa5281ff4a02 1209 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
AnnaBridge 161:aa5281ff4a02 1210 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
AnnaBridge 161:aa5281ff4a02 1211 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
AnnaBridge 161:aa5281ff4a02 1212 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
AnnaBridge 161:aa5281ff4a02 1213 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
AnnaBridge 161:aa5281ff4a02 1214 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
AnnaBridge 161:aa5281ff4a02 1215 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
AnnaBridge 161:aa5281ff4a02 1216 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
AnnaBridge 161:aa5281ff4a02 1217 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
AnnaBridge 161:aa5281ff4a02 1218 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
AnnaBridge 161:aa5281ff4a02 1219 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
AnnaBridge 161:aa5281ff4a02 1220 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
AnnaBridge 161:aa5281ff4a02 1221 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
AnnaBridge 161:aa5281ff4a02 1222 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1223 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1224 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1225 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1226 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1227 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1228 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
AnnaBridge 161:aa5281ff4a02 1229 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1230 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1231 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
AnnaBridge 161:aa5281ff4a02 1232 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
AnnaBridge 161:aa5281ff4a02 1233 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
AnnaBridge 161:aa5281ff4a02 1234 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
AnnaBridge 161:aa5281ff4a02 1235 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
AnnaBridge 161:aa5281ff4a02 1236 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
AnnaBridge 161:aa5281ff4a02 1237 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
AnnaBridge 161:aa5281ff4a02 1238 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
AnnaBridge 161:aa5281ff4a02 1239 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
AnnaBridge 161:aa5281ff4a02 1240 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
AnnaBridge 161:aa5281ff4a02 1241 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
AnnaBridge 161:aa5281ff4a02 1242 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
AnnaBridge 161:aa5281ff4a02 1243 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
AnnaBridge 161:aa5281ff4a02 1244 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
AnnaBridge 161:aa5281ff4a02 1245 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
AnnaBridge 161:aa5281ff4a02 1246 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
AnnaBridge 161:aa5281ff4a02 1247 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
AnnaBridge 161:aa5281ff4a02 1248 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
AnnaBridge 161:aa5281ff4a02 1249 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
AnnaBridge 161:aa5281ff4a02 1250 ((Timing) == DSI_TLPX_CLK ) || \
AnnaBridge 161:aa5281ff4a02 1251 ((Timing) == DSI_THS_EXIT ) || \
AnnaBridge 161:aa5281ff4a02 1252 ((Timing) == DSI_TLPX_DATA ) || \
AnnaBridge 161:aa5281ff4a02 1253 ((Timing) == DSI_THS_ZERO ) || \
AnnaBridge 161:aa5281ff4a02 1254 ((Timing) == DSI_THS_TRAIL ) || \
AnnaBridge 161:aa5281ff4a02 1255 ((Timing) == DSI_THS_PREPARE ) || \
AnnaBridge 161:aa5281ff4a02 1256 ((Timing) == DSI_TCLK_ZERO ) || \
AnnaBridge 161:aa5281ff4a02 1257 ((Timing) == DSI_TCLK_PREPARE))
AnnaBridge 161:aa5281ff4a02 1258
AnnaBridge 161:aa5281ff4a02 1259 /**
AnnaBridge 161:aa5281ff4a02 1260 * @}
AnnaBridge 161:aa5281ff4a02 1261 */
AnnaBridge 161:aa5281ff4a02 1262
AnnaBridge 161:aa5281ff4a02 1263 /* Private functions prototypes ----------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1264 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
AnnaBridge 161:aa5281ff4a02 1265 * @{
AnnaBridge 161:aa5281ff4a02 1266 */
AnnaBridge 161:aa5281ff4a02 1267
AnnaBridge 161:aa5281ff4a02 1268 /**
AnnaBridge 161:aa5281ff4a02 1269 * @}
AnnaBridge 161:aa5281ff4a02 1270 */
AnnaBridge 161:aa5281ff4a02 1271
AnnaBridge 161:aa5281ff4a02 1272 /* Private functions ---------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 1273 /** @defgroup DSI_Private_Functions DSI Private Functions
AnnaBridge 161:aa5281ff4a02 1274 * @{
AnnaBridge 161:aa5281ff4a02 1275 */
AnnaBridge 161:aa5281ff4a02 1276
AnnaBridge 161:aa5281ff4a02 1277 /**
AnnaBridge 161:aa5281ff4a02 1278 * @}
AnnaBridge 161:aa5281ff4a02 1279 */
AnnaBridge 161:aa5281ff4a02 1280
AnnaBridge 161:aa5281ff4a02 1281 /**
AnnaBridge 161:aa5281ff4a02 1282 * @}
AnnaBridge 161:aa5281ff4a02 1283 */
AnnaBridge 161:aa5281ff4a02 1284
AnnaBridge 161:aa5281ff4a02 1285 /**
AnnaBridge 161:aa5281ff4a02 1286 * @}
AnnaBridge 161:aa5281ff4a02 1287 */
AnnaBridge 161:aa5281ff4a02 1288 #endif /* DSI */
AnnaBridge 161:aa5281ff4a02 1289
AnnaBridge 161:aa5281ff4a02 1290 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 1291 }
AnnaBridge 161:aa5281ff4a02 1292 #endif
AnnaBridge 161:aa5281ff4a02 1293
AnnaBridge 161:aa5281ff4a02 1294 #endif /* __STM32L4xx_HAL_DSI_H */
AnnaBridge 161:aa5281ff4a02 1295
AnnaBridge 161:aa5281ff4a02 1296 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/