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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_dac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h@165:d1b4690b3f8b
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 165:d1b4690b3f8b | 1 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 2 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 3 | * @file stm32l4xx_hal_dac.h |
| AnnaBridge | 165:d1b4690b3f8b | 4 | * @author MCD Application Team |
| AnnaBridge | 165:d1b4690b3f8b | 5 | * @brief Header file of DAC HAL module. |
| AnnaBridge | 165:d1b4690b3f8b | 6 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 7 | * @attention |
| AnnaBridge | 165:d1b4690b3f8b | 8 | * |
| AnnaBridge | 165:d1b4690b3f8b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 165:d1b4690b3f8b | 10 | * |
| AnnaBridge | 165:d1b4690b3f8b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 165:d1b4690b3f8b | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 165:d1b4690b3f8b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 165:d1b4690b3f8b | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 165:d1b4690b3f8b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 165:d1b4690b3f8b | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 165:d1b4690b3f8b | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 165:d1b4690b3f8b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 165:d1b4690b3f8b | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 165:d1b4690b3f8b | 20 | * without specific prior written permission. |
| AnnaBridge | 165:d1b4690b3f8b | 21 | * |
| AnnaBridge | 165:d1b4690b3f8b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 165:d1b4690b3f8b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 165:d1b4690b3f8b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 165:d1b4690b3f8b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 165:d1b4690b3f8b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 165:d1b4690b3f8b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 165:d1b4690b3f8b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 165:d1b4690b3f8b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 165:d1b4690b3f8b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 165:d1b4690b3f8b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 165:d1b4690b3f8b | 32 | * |
| AnnaBridge | 165:d1b4690b3f8b | 33 | ****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 34 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 35 | |
| AnnaBridge | 165:d1b4690b3f8b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 37 | #ifndef __STM32L4xx_HAL_DAC_H |
| AnnaBridge | 165:d1b4690b3f8b | 38 | #define __STM32L4xx_HAL_DAC_H |
| AnnaBridge | 165:d1b4690b3f8b | 39 | |
| AnnaBridge | 165:d1b4690b3f8b | 40 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 41 | extern "C" { |
| AnnaBridge | 165:d1b4690b3f8b | 42 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 43 | |
| AnnaBridge | 165:d1b4690b3f8b | 44 | |
| AnnaBridge | 165:d1b4690b3f8b | 45 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 46 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 165:d1b4690b3f8b | 47 | |
| AnnaBridge | 165:d1b4690b3f8b | 48 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 165:d1b4690b3f8b | 49 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 50 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 51 | |
| AnnaBridge | 165:d1b4690b3f8b | 52 | /** @addtogroup DAC |
| AnnaBridge | 165:d1b4690b3f8b | 53 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 54 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 55 | |
| AnnaBridge | 165:d1b4690b3f8b | 56 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 57 | |
| AnnaBridge | 165:d1b4690b3f8b | 58 | /** @defgroup DAC_Exported_Types DAC Exported Types |
| AnnaBridge | 165:d1b4690b3f8b | 59 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 60 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 61 | |
| AnnaBridge | 165:d1b4690b3f8b | 62 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 63 | * @brief HAL State structures definition |
| AnnaBridge | 165:d1b4690b3f8b | 64 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 65 | typedef enum |
| AnnaBridge | 165:d1b4690b3f8b | 66 | { |
| AnnaBridge | 165:d1b4690b3f8b | 67 | HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ |
| AnnaBridge | 165:d1b4690b3f8b | 68 | HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ |
| AnnaBridge | 165:d1b4690b3f8b | 69 | HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ |
| AnnaBridge | 165:d1b4690b3f8b | 70 | HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ |
| AnnaBridge | 165:d1b4690b3f8b | 71 | HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ |
| AnnaBridge | 165:d1b4690b3f8b | 72 | |
| AnnaBridge | 165:d1b4690b3f8b | 73 | }HAL_DAC_StateTypeDef; |
| AnnaBridge | 165:d1b4690b3f8b | 74 | |
| AnnaBridge | 165:d1b4690b3f8b | 75 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 76 | * @brief DAC handle Structure definition |
| AnnaBridge | 165:d1b4690b3f8b | 77 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 78 | typedef struct |
| AnnaBridge | 165:d1b4690b3f8b | 79 | { |
| AnnaBridge | 165:d1b4690b3f8b | 80 | DAC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 165:d1b4690b3f8b | 81 | |
| AnnaBridge | 165:d1b4690b3f8b | 82 | __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ |
| AnnaBridge | 165:d1b4690b3f8b | 83 | |
| AnnaBridge | 165:d1b4690b3f8b | 84 | HAL_LockTypeDef Lock; /*!< DAC locking object */ |
| AnnaBridge | 165:d1b4690b3f8b | 85 | |
| AnnaBridge | 165:d1b4690b3f8b | 86 | DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 87 | |
| AnnaBridge | 165:d1b4690b3f8b | 88 | DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 89 | |
| AnnaBridge | 165:d1b4690b3f8b | 90 | __IO uint32_t ErrorCode; /*!< DAC Error code */ |
| AnnaBridge | 165:d1b4690b3f8b | 91 | |
| AnnaBridge | 165:d1b4690b3f8b | 92 | }DAC_HandleTypeDef; |
| AnnaBridge | 165:d1b4690b3f8b | 93 | |
| AnnaBridge | 165:d1b4690b3f8b | 94 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 95 | * @brief DAC Configuration sample and hold Channel structure definition |
| AnnaBridge | 165:d1b4690b3f8b | 96 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 97 | typedef struct |
| AnnaBridge | 165:d1b4690b3f8b | 98 | { |
| AnnaBridge | 165:d1b4690b3f8b | 99 | uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. |
| AnnaBridge | 165:d1b4690b3f8b | 100 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 165:d1b4690b3f8b | 101 | This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ |
| AnnaBridge | 165:d1b4690b3f8b | 102 | |
| AnnaBridge | 165:d1b4690b3f8b | 103 | uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel |
| AnnaBridge | 165:d1b4690b3f8b | 104 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 165:d1b4690b3f8b | 105 | This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ |
| AnnaBridge | 165:d1b4690b3f8b | 106 | |
| AnnaBridge | 165:d1b4690b3f8b | 107 | uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel |
| AnnaBridge | 165:d1b4690b3f8b | 108 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 165:d1b4690b3f8b | 109 | This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 165:d1b4690b3f8b | 110 | } |
| AnnaBridge | 165:d1b4690b3f8b | 111 | DAC_SampleAndHoldConfTypeDef; |
| AnnaBridge | 165:d1b4690b3f8b | 112 | |
| AnnaBridge | 165:d1b4690b3f8b | 113 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 114 | * @brief DAC Configuration regular Channel structure definition |
| AnnaBridge | 165:d1b4690b3f8b | 115 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 116 | typedef struct |
| AnnaBridge | 165:d1b4690b3f8b | 117 | { |
| AnnaBridge | 165:d1b4690b3f8b | 118 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 165:d1b4690b3f8b | 119 | uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode |
| AnnaBridge | 165:d1b4690b3f8b | 120 | This parameter can be a value of @ref DAC_HighFrequency */ |
| AnnaBridge | 165:d1b4690b3f8b | 121 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 122 | |
| AnnaBridge | 165:d1b4690b3f8b | 123 | uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. |
| AnnaBridge | 165:d1b4690b3f8b | 124 | This parameter can be a value of @ref DAC_SampleAndHold */ |
| AnnaBridge | 165:d1b4690b3f8b | 125 | |
| AnnaBridge | 165:d1b4690b3f8b | 126 | uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. |
| AnnaBridge | 165:d1b4690b3f8b | 127 | This parameter can be a value of @ref DAC_trigger_selection */ |
| AnnaBridge | 165:d1b4690b3f8b | 128 | |
| AnnaBridge | 165:d1b4690b3f8b | 129 | uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. |
| AnnaBridge | 165:d1b4690b3f8b | 130 | This parameter can be a value of @ref DAC_output_buffer */ |
| AnnaBridge | 165:d1b4690b3f8b | 131 | |
| AnnaBridge | 165:d1b4690b3f8b | 132 | uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . |
| AnnaBridge | 165:d1b4690b3f8b | 133 | This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ |
| AnnaBridge | 165:d1b4690b3f8b | 134 | |
| AnnaBridge | 165:d1b4690b3f8b | 135 | uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode |
| AnnaBridge | 165:d1b4690b3f8b | 136 | This parameter must be a value of @ref DAC_UserTrimming |
| AnnaBridge | 165:d1b4690b3f8b | 137 | DAC_UserTrimming is either factory or user trimming */ |
| AnnaBridge | 165:d1b4690b3f8b | 138 | |
| AnnaBridge | 165:d1b4690b3f8b | 139 | uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value |
| AnnaBridge | 165:d1b4690b3f8b | 140 | i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. |
| AnnaBridge | 165:d1b4690b3f8b | 141 | This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ |
| AnnaBridge | 165:d1b4690b3f8b | 142 | |
| AnnaBridge | 165:d1b4690b3f8b | 143 | DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ |
| AnnaBridge | 165:d1b4690b3f8b | 144 | |
| AnnaBridge | 165:d1b4690b3f8b | 145 | }DAC_ChannelConfTypeDef; |
| AnnaBridge | 165:d1b4690b3f8b | 146 | |
| AnnaBridge | 165:d1b4690b3f8b | 147 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 148 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 149 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 150 | |
| AnnaBridge | 165:d1b4690b3f8b | 151 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 152 | |
| AnnaBridge | 165:d1b4690b3f8b | 153 | /** @defgroup DAC_Exported_Constants DAC Exported Constants |
| AnnaBridge | 165:d1b4690b3f8b | 154 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 155 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 156 | |
| AnnaBridge | 165:d1b4690b3f8b | 157 | /** @defgroup DAC_Error_Code DAC Error Code |
| AnnaBridge | 165:d1b4690b3f8b | 158 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 159 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 160 | #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ |
| AnnaBridge | 165:d1b4690b3f8b | 161 | #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ |
| AnnaBridge | 165:d1b4690b3f8b | 162 | #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ |
| AnnaBridge | 165:d1b4690b3f8b | 163 | #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ |
| AnnaBridge | 165:d1b4690b3f8b | 164 | #define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */ |
| AnnaBridge | 165:d1b4690b3f8b | 165 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 166 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 167 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 168 | |
| AnnaBridge | 165:d1b4690b3f8b | 169 | /** @defgroup DAC_trigger_selection DAC trigger selection |
| AnnaBridge | 165:d1b4690b3f8b | 170 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 171 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 172 | |
| AnnaBridge | 165:d1b4690b3f8b | 173 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) |
| AnnaBridge | 165:d1b4690b3f8b | 174 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 165:d1b4690b3f8b | 175 | has been loaded, and not by external trigger */ |
| AnnaBridge | 165:d1b4690b3f8b | 176 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 177 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 178 | #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 179 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 180 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 181 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 182 | |
| AnnaBridge | 165:d1b4690b3f8b | 183 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 165:d1b4690b3f8b | 184 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 165:d1b4690b3f8b | 185 | has been loaded, and not by external trigger */ |
| AnnaBridge | 165:d1b4690b3f8b | 186 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 187 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 188 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 189 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 190 | #endif /* STM32L451xx STM32L452xx STM32L462xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 191 | |
| AnnaBridge | 165:d1b4690b3f8b | 192 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) |
| AnnaBridge | 165:d1b4690b3f8b | 193 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 165:d1b4690b3f8b | 194 | has been loaded, and not by external trigger */ |
| AnnaBridge | 165:d1b4690b3f8b | 195 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 196 | #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 197 | #define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 198 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 199 | #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 200 | #define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 201 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 202 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 203 | #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ |
| AnnaBridge | 165:d1b4690b3f8b | 204 | |
| AnnaBridge | 165:d1b4690b3f8b | 205 | |
| AnnaBridge | 165:d1b4690b3f8b | 206 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 165:d1b4690b3f8b | 207 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 165:d1b4690b3f8b | 208 | has been loaded, and not by external trigger */ |
| AnnaBridge | 165:d1b4690b3f8b | 209 | #define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 210 | #define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 211 | #define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 212 | #define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 213 | #define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 214 | #define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 215 | #define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 216 | #define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 217 | #define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 218 | #define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 219 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 220 | #define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 165:d1b4690b3f8b | 221 | |
| AnnaBridge | 165:d1b4690b3f8b | 222 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 223 | |
| AnnaBridge | 165:d1b4690b3f8b | 224 | |
| AnnaBridge | 165:d1b4690b3f8b | 225 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 226 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 227 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 228 | |
| AnnaBridge | 165:d1b4690b3f8b | 229 | /** @defgroup DAC_output_buffer DAC output buffer |
| AnnaBridge | 165:d1b4690b3f8b | 230 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 231 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 232 | #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) |
| AnnaBridge | 165:d1b4690b3f8b | 233 | #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1) |
| AnnaBridge | 165:d1b4690b3f8b | 234 | |
| AnnaBridge | 165:d1b4690b3f8b | 235 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 236 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 237 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 238 | |
| AnnaBridge | 165:d1b4690b3f8b | 239 | /** @defgroup DAC_Channel_selection DAC Channel selection |
| AnnaBridge | 165:d1b4690b3f8b | 240 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 241 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 242 | #define DAC_CHANNEL_1 ((uint32_t)0x00000000) |
| AnnaBridge | 165:d1b4690b3f8b | 243 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 244 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 245 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 165:d1b4690b3f8b | 246 | #define DAC_CHANNEL_2 ((uint32_t)0x00000010) |
| AnnaBridge | 165:d1b4690b3f8b | 247 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 248 | /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 249 | /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 250 | |
| AnnaBridge | 165:d1b4690b3f8b | 251 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 252 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 253 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 254 | |
| AnnaBridge | 165:d1b4690b3f8b | 255 | /** @defgroup DAC_data_alignment DAC data alignment |
| AnnaBridge | 165:d1b4690b3f8b | 256 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 257 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 258 | #define DAC_ALIGN_12B_R ((uint32_t)0x00000000) |
| AnnaBridge | 165:d1b4690b3f8b | 259 | #define DAC_ALIGN_12B_L ((uint32_t)0x00000004) |
| AnnaBridge | 165:d1b4690b3f8b | 260 | #define DAC_ALIGN_8B_R ((uint32_t)0x00000008) |
| AnnaBridge | 165:d1b4690b3f8b | 261 | |
| AnnaBridge | 165:d1b4690b3f8b | 262 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 263 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 264 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 265 | |
| AnnaBridge | 165:d1b4690b3f8b | 266 | /** @defgroup DAC_flags_definition DAC flags definition |
| AnnaBridge | 165:d1b4690b3f8b | 267 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 268 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 269 | #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 165:d1b4690b3f8b | 270 | #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 165:d1b4690b3f8b | 271 | |
| AnnaBridge | 165:d1b4690b3f8b | 272 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 273 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 274 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 275 | |
| AnnaBridge | 165:d1b4690b3f8b | 276 | /** @defgroup DAC_IT_definition DAC IT definition |
| AnnaBridge | 165:d1b4690b3f8b | 277 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 278 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 279 | #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 165:d1b4690b3f8b | 280 | #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 165:d1b4690b3f8b | 281 | |
| AnnaBridge | 165:d1b4690b3f8b | 282 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 283 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 284 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 285 | |
| AnnaBridge | 165:d1b4690b3f8b | 286 | /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral |
| AnnaBridge | 165:d1b4690b3f8b | 287 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 288 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 289 | #define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 165:d1b4690b3f8b | 290 | #define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0) |
| AnnaBridge | 165:d1b4690b3f8b | 291 | |
| AnnaBridge | 165:d1b4690b3f8b | 292 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 293 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 294 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 295 | |
| AnnaBridge | 165:d1b4690b3f8b | 296 | /** @defgroup DAC_UserTrimming DAC User Trimming |
| AnnaBridge | 165:d1b4690b3f8b | 297 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 298 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 299 | |
| AnnaBridge | 165:d1b4690b3f8b | 300 | #define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ |
| AnnaBridge | 165:d1b4690b3f8b | 301 | #define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */ |
| AnnaBridge | 165:d1b4690b3f8b | 302 | |
| AnnaBridge | 165:d1b4690b3f8b | 303 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 304 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 305 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 306 | |
| AnnaBridge | 165:d1b4690b3f8b | 307 | /** @defgroup DAC_SampleAndHold DAC power mode |
| AnnaBridge | 165:d1b4690b3f8b | 308 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 309 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 310 | #define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 165:d1b4690b3f8b | 311 | #define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2) |
| AnnaBridge | 165:d1b4690b3f8b | 312 | |
| AnnaBridge | 165:d1b4690b3f8b | 313 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 314 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 315 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 316 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 165:d1b4690b3f8b | 317 | /** @defgroup DAC_HighFrequency DAC high frequency interface mode |
| AnnaBridge | 165:d1b4690b3f8b | 318 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 319 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 320 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ |
| AnnaBridge | 165:d1b4690b3f8b | 321 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ |
| AnnaBridge | 165:d1b4690b3f8b | 322 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ |
| AnnaBridge | 165:d1b4690b3f8b | 323 | |
| AnnaBridge | 165:d1b4690b3f8b | 324 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 325 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 326 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 327 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 328 | |
| AnnaBridge | 165:d1b4690b3f8b | 329 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 330 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 331 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 332 | |
| AnnaBridge | 165:d1b4690b3f8b | 333 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 334 | |
| AnnaBridge | 165:d1b4690b3f8b | 335 | /** @defgroup DAC_Exported_Macros DAC Exported Macros |
| AnnaBridge | 165:d1b4690b3f8b | 336 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 337 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 338 | |
| AnnaBridge | 165:d1b4690b3f8b | 339 | /** @brief Reset DAC handle state. |
| AnnaBridge | 165:d1b4690b3f8b | 340 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 165:d1b4690b3f8b | 341 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 342 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 343 | #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) |
| AnnaBridge | 165:d1b4690b3f8b | 344 | |
| AnnaBridge | 165:d1b4690b3f8b | 345 | /** @brief Enable the DAC channel. |
| AnnaBridge | 165:d1b4690b3f8b | 346 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 165:d1b4690b3f8b | 347 | * @param __DAC_Channel__: specifies the DAC channel |
| AnnaBridge | 165:d1b4690b3f8b | 348 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 349 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 350 | #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ |
| AnnaBridge | 165:d1b4690b3f8b | 351 | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) |
| AnnaBridge | 165:d1b4690b3f8b | 352 | |
| AnnaBridge | 165:d1b4690b3f8b | 353 | /** @brief Disable the DAC channel. |
| AnnaBridge | 165:d1b4690b3f8b | 354 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 165:d1b4690b3f8b | 355 | * @param __DAC_Channel__: specifies the DAC channel. |
| AnnaBridge | 165:d1b4690b3f8b | 356 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 357 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 358 | #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ |
| AnnaBridge | 165:d1b4690b3f8b | 359 | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) |
| AnnaBridge | 165:d1b4690b3f8b | 360 | |
| AnnaBridge | 165:d1b4690b3f8b | 361 | /** @brief Set DHR12R1 alignment. |
| AnnaBridge | 165:d1b4690b3f8b | 362 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 165:d1b4690b3f8b | 363 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 364 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 365 | #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 366 | |
| AnnaBridge | 165:d1b4690b3f8b | 367 | /** @brief Set DHR12R2 alignment. |
| AnnaBridge | 165:d1b4690b3f8b | 368 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 165:d1b4690b3f8b | 369 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 370 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 371 | #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 372 | |
| AnnaBridge | 165:d1b4690b3f8b | 373 | /** @brief Set DHR12RD alignment. |
| AnnaBridge | 165:d1b4690b3f8b | 374 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 165:d1b4690b3f8b | 375 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 376 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 377 | #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 378 | |
| AnnaBridge | 165:d1b4690b3f8b | 379 | /** @brief Enable the DAC interrupt. |
| AnnaBridge | 165:d1b4690b3f8b | 380 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 165:d1b4690b3f8b | 381 | * @param __INTERRUPT__: specifies the DAC interrupt. |
| AnnaBridge | 165:d1b4690b3f8b | 382 | * This parameter can be any combination of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 383 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 384 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 385 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 386 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 387 | #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 388 | |
| AnnaBridge | 165:d1b4690b3f8b | 389 | /** @brief Disable the DAC interrupt. |
| AnnaBridge | 165:d1b4690b3f8b | 390 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 165:d1b4690b3f8b | 391 | * @param __INTERRUPT__: specifies the DAC interrupt. |
| AnnaBridge | 165:d1b4690b3f8b | 392 | * This parameter can be any combination of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 393 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 394 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 395 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 396 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 397 | #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 398 | |
| AnnaBridge | 165:d1b4690b3f8b | 399 | /** @brief Check whether the specified DAC interrupt source is enabled or not. |
| AnnaBridge | 165:d1b4690b3f8b | 400 | * @param __HANDLE__: DAC handle |
| AnnaBridge | 165:d1b4690b3f8b | 401 | * @param __INTERRUPT__: DAC interrupt source to check |
| AnnaBridge | 165:d1b4690b3f8b | 402 | * This parameter can be any combination of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 403 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 404 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 165:d1b4690b3f8b | 405 | * @retval State of interruption (SET or RESET) |
| AnnaBridge | 165:d1b4690b3f8b | 406 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 407 | #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 165:d1b4690b3f8b | 408 | |
| AnnaBridge | 165:d1b4690b3f8b | 409 | /** @brief Get the selected DAC's flag status. |
| AnnaBridge | 165:d1b4690b3f8b | 410 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 165:d1b4690b3f8b | 411 | * @param __FLAG__: specifies the DAC flag to get. |
| AnnaBridge | 165:d1b4690b3f8b | 412 | * This parameter can be any combination of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 413 | * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag |
| AnnaBridge | 165:d1b4690b3f8b | 414 | * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag |
| AnnaBridge | 165:d1b4690b3f8b | 415 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 416 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 417 | #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 165:d1b4690b3f8b | 418 | |
| AnnaBridge | 165:d1b4690b3f8b | 419 | /** @brief Clear the DAC's flag. |
| AnnaBridge | 165:d1b4690b3f8b | 420 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 165:d1b4690b3f8b | 421 | * @param __FLAG__: specifies the DAC flag to clear. |
| AnnaBridge | 165:d1b4690b3f8b | 422 | * This parameter can be any combination of the following values: |
| AnnaBridge | 165:d1b4690b3f8b | 423 | * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag |
| AnnaBridge | 165:d1b4690b3f8b | 424 | * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag |
| AnnaBridge | 165:d1b4690b3f8b | 425 | * @retval None |
| AnnaBridge | 165:d1b4690b3f8b | 426 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 427 | #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) |
| AnnaBridge | 165:d1b4690b3f8b | 428 | |
| AnnaBridge | 165:d1b4690b3f8b | 429 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 430 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 431 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 432 | |
| AnnaBridge | 165:d1b4690b3f8b | 433 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 434 | |
| AnnaBridge | 165:d1b4690b3f8b | 435 | /** @defgroup DAC_Private_Macros DAC Private Macros |
| AnnaBridge | 165:d1b4690b3f8b | 436 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 437 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 438 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 439 | ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) |
| AnnaBridge | 165:d1b4690b3f8b | 440 | |
| AnnaBridge | 165:d1b4690b3f8b | 441 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 442 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 443 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 165:d1b4690b3f8b | 444 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 445 | ((CHANNEL) == DAC_CHANNEL_2)) |
| AnnaBridge | 165:d1b4690b3f8b | 446 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 447 | /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 448 | /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 449 | |
| AnnaBridge | 165:d1b4690b3f8b | 450 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 165:d1b4690b3f8b | 451 | #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) |
| AnnaBridge | 165:d1b4690b3f8b | 452 | #endif /* STM32L451xx STM32L452xx STM32L462xx */ |
| AnnaBridge | 165:d1b4690b3f8b | 453 | |
| AnnaBridge | 165:d1b4690b3f8b | 454 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 455 | ((ALIGN) == DAC_ALIGN_12B_L) || \ |
| AnnaBridge | 165:d1b4690b3f8b | 456 | ((ALIGN) == DAC_ALIGN_8B_R)) |
| AnnaBridge | 165:d1b4690b3f8b | 457 | |
| AnnaBridge | 165:d1b4690b3f8b | 458 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) |
| AnnaBridge | 165:d1b4690b3f8b | 459 | |
| AnnaBridge | 165:d1b4690b3f8b | 460 | #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) |
| AnnaBridge | 165:d1b4690b3f8b | 461 | |
| AnnaBridge | 165:d1b4690b3f8b | 462 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 463 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 464 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 465 | |
| AnnaBridge | 165:d1b4690b3f8b | 466 | /* Include DAC HAL Extended module */ |
| AnnaBridge | 165:d1b4690b3f8b | 467 | #include "stm32l4xx_hal_dac_ex.h" |
| AnnaBridge | 165:d1b4690b3f8b | 468 | |
| AnnaBridge | 165:d1b4690b3f8b | 469 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 165:d1b4690b3f8b | 470 | |
| AnnaBridge | 165:d1b4690b3f8b | 471 | /** @addtogroup DAC_Exported_Functions |
| AnnaBridge | 165:d1b4690b3f8b | 472 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 473 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 474 | |
| AnnaBridge | 165:d1b4690b3f8b | 475 | /** @addtogroup DAC_Exported_Functions_Group1 |
| AnnaBridge | 165:d1b4690b3f8b | 476 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 477 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 478 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 479 | HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 480 | HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 481 | void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 482 | void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 483 | |
| AnnaBridge | 165:d1b4690b3f8b | 484 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 485 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 486 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 487 | |
| AnnaBridge | 165:d1b4690b3f8b | 488 | /** @addtogroup DAC_Exported_Functions_Group2 |
| AnnaBridge | 165:d1b4690b3f8b | 489 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 490 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 491 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 492 | HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 165:d1b4690b3f8b | 493 | HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 165:d1b4690b3f8b | 494 | HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); |
| AnnaBridge | 165:d1b4690b3f8b | 495 | HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 165:d1b4690b3f8b | 496 | |
| AnnaBridge | 165:d1b4690b3f8b | 497 | void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 498 | |
| AnnaBridge | 165:d1b4690b3f8b | 499 | HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); |
| AnnaBridge | 165:d1b4690b3f8b | 500 | |
| AnnaBridge | 165:d1b4690b3f8b | 501 | void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 502 | void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 503 | void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 504 | void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 505 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 506 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 507 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 508 | |
| AnnaBridge | 165:d1b4690b3f8b | 509 | /** @addtogroup DAC_Exported_Functions_Group3 |
| AnnaBridge | 165:d1b4690b3f8b | 510 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 511 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 512 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 513 | uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 165:d1b4690b3f8b | 514 | |
| AnnaBridge | 165:d1b4690b3f8b | 515 | HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); |
| AnnaBridge | 165:d1b4690b3f8b | 516 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 517 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 518 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 519 | |
| AnnaBridge | 165:d1b4690b3f8b | 520 | /** @addtogroup DAC_Exported_Functions_Group4 |
| AnnaBridge | 165:d1b4690b3f8b | 521 | * @{ |
| AnnaBridge | 165:d1b4690b3f8b | 522 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 523 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 524 | HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 525 | uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 165:d1b4690b3f8b | 526 | |
| AnnaBridge | 165:d1b4690b3f8b | 527 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 528 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 529 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 530 | |
| AnnaBridge | 165:d1b4690b3f8b | 531 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 532 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 533 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 534 | |
| AnnaBridge | 165:d1b4690b3f8b | 535 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 536 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 537 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 538 | |
| AnnaBridge | 165:d1b4690b3f8b | 539 | /** |
| AnnaBridge | 165:d1b4690b3f8b | 540 | * @} |
| AnnaBridge | 165:d1b4690b3f8b | 541 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 542 | |
| AnnaBridge | 165:d1b4690b3f8b | 543 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 544 | } |
| AnnaBridge | 165:d1b4690b3f8b | 545 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 546 | |
| AnnaBridge | 165:d1b4690b3f8b | 547 | |
| AnnaBridge | 165:d1b4690b3f8b | 548 | #endif /*__STM32L4xx_HAL_DAC_H */ |
| AnnaBridge | 165:d1b4690b3f8b | 549 | |
| AnnaBridge | 165:d1b4690b3f8b | 550 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 165:d1b4690b3f8b | 551 |
