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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_cortex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h@165:d1b4690b3f8b 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**
AnnaBridge 165:d1b4690b3f8b 2 ******************************************************************************
AnnaBridge 165:d1b4690b3f8b 3 * @file stm32l4xx_ll_cortex.h
AnnaBridge 165:d1b4690b3f8b 4 * @author MCD Application Team
AnnaBridge 165:d1b4690b3f8b 5 * @brief Header file of CORTEX LL module.
AnnaBridge 165:d1b4690b3f8b 6 @verbatim
AnnaBridge 165:d1b4690b3f8b 7 ==============================================================================
AnnaBridge 165:d1b4690b3f8b 8 ##### How to use this driver #####
AnnaBridge 165:d1b4690b3f8b 9 ==============================================================================
AnnaBridge 165:d1b4690b3f8b 10 [..]
AnnaBridge 165:d1b4690b3f8b 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 165:d1b4690b3f8b 12 used by user:
AnnaBridge 165:d1b4690b3f8b 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 165:d1b4690b3f8b 14 functions
AnnaBridge 165:d1b4690b3f8b 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 165:d1b4690b3f8b 16 (+) MPU API to configure and enable regions
AnnaBridge 165:d1b4690b3f8b 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 165:d1b4690b3f8b 18 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 165:d1b4690b3f8b 19
AnnaBridge 165:d1b4690b3f8b 20 @endverbatim
AnnaBridge 165:d1b4690b3f8b 21 ******************************************************************************
AnnaBridge 165:d1b4690b3f8b 22 * @attention
AnnaBridge 165:d1b4690b3f8b 23 *
AnnaBridge 165:d1b4690b3f8b 24 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 165:d1b4690b3f8b 25 *
AnnaBridge 165:d1b4690b3f8b 26 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 165:d1b4690b3f8b 27 * are permitted provided that the following conditions are met:
AnnaBridge 165:d1b4690b3f8b 28 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 165:d1b4690b3f8b 29 * this list of conditions and the following disclaimer.
AnnaBridge 165:d1b4690b3f8b 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 165:d1b4690b3f8b 31 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 165:d1b4690b3f8b 32 * and/or other materials provided with the distribution.
AnnaBridge 165:d1b4690b3f8b 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 165:d1b4690b3f8b 34 * may be used to endorse or promote products derived from this software
AnnaBridge 165:d1b4690b3f8b 35 * without specific prior written permission.
AnnaBridge 165:d1b4690b3f8b 36 *
AnnaBridge 165:d1b4690b3f8b 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 165:d1b4690b3f8b 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 165:d1b4690b3f8b 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 165:d1b4690b3f8b 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 165:d1b4690b3f8b 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 165:d1b4690b3f8b 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 165:d1b4690b3f8b 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 165:d1b4690b3f8b 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 165:d1b4690b3f8b 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 165:d1b4690b3f8b 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 165:d1b4690b3f8b 47 *
AnnaBridge 165:d1b4690b3f8b 48 ******************************************************************************
AnnaBridge 165:d1b4690b3f8b 49 */
AnnaBridge 165:d1b4690b3f8b 50
AnnaBridge 165:d1b4690b3f8b 51 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 52 #ifndef __STM32L4xx_LL_CORTEX_H
AnnaBridge 165:d1b4690b3f8b 53 #define __STM32L4xx_LL_CORTEX_H
AnnaBridge 165:d1b4690b3f8b 54
AnnaBridge 165:d1b4690b3f8b 55 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 56 extern "C" {
AnnaBridge 165:d1b4690b3f8b 57 #endif
AnnaBridge 165:d1b4690b3f8b 58
AnnaBridge 165:d1b4690b3f8b 59 /* Includes ------------------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 60 #include "stm32l4xx.h"
AnnaBridge 165:d1b4690b3f8b 61
AnnaBridge 165:d1b4690b3f8b 62 /** @addtogroup STM32L4xx_LL_Driver
AnnaBridge 165:d1b4690b3f8b 63 * @{
AnnaBridge 165:d1b4690b3f8b 64 */
AnnaBridge 165:d1b4690b3f8b 65
AnnaBridge 165:d1b4690b3f8b 66 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 165:d1b4690b3f8b 67 * @{
AnnaBridge 165:d1b4690b3f8b 68 */
AnnaBridge 165:d1b4690b3f8b 69
AnnaBridge 165:d1b4690b3f8b 70 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 71 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 72
AnnaBridge 165:d1b4690b3f8b 73 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 74
AnnaBridge 165:d1b4690b3f8b 75 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 76
AnnaBridge 165:d1b4690b3f8b 77 /* Exported types ------------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 78 /* Exported constants --------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 165:d1b4690b3f8b 80 * @{
AnnaBridge 165:d1b4690b3f8b 81 */
AnnaBridge 165:d1b4690b3f8b 82
AnnaBridge 165:d1b4690b3f8b 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 165:d1b4690b3f8b 84 * @{
AnnaBridge 165:d1b4690b3f8b 85 */
AnnaBridge 165:d1b4690b3f8b 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 165:d1b4690b3f8b 87 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 165:d1b4690b3f8b 88 /**
AnnaBridge 165:d1b4690b3f8b 89 * @}
AnnaBridge 165:d1b4690b3f8b 90 */
AnnaBridge 165:d1b4690b3f8b 91
AnnaBridge 165:d1b4690b3f8b 92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 165:d1b4690b3f8b 93 * @{
AnnaBridge 165:d1b4690b3f8b 94 */
AnnaBridge 165:d1b4690b3f8b 95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 165:d1b4690b3f8b 96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 165:d1b4690b3f8b 97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 165:d1b4690b3f8b 98 /**
AnnaBridge 165:d1b4690b3f8b 99 * @}
AnnaBridge 165:d1b4690b3f8b 100 */
AnnaBridge 165:d1b4690b3f8b 101
AnnaBridge 165:d1b4690b3f8b 102 #if __MPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 103
AnnaBridge 165:d1b4690b3f8b 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 165:d1b4690b3f8b 105 * @{
AnnaBridge 165:d1b4690b3f8b 106 */
AnnaBridge 165:d1b4690b3f8b 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 165:d1b4690b3f8b 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 165:d1b4690b3f8b 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 165:d1b4690b3f8b 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 165:d1b4690b3f8b 111 /**
AnnaBridge 165:d1b4690b3f8b 112 * @}
AnnaBridge 165:d1b4690b3f8b 113 */
AnnaBridge 165:d1b4690b3f8b 114
AnnaBridge 165:d1b4690b3f8b 115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 165:d1b4690b3f8b 116 * @{
AnnaBridge 165:d1b4690b3f8b 117 */
AnnaBridge 165:d1b4690b3f8b 118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 165:d1b4690b3f8b 119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 165:d1b4690b3f8b 120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 165:d1b4690b3f8b 121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 165:d1b4690b3f8b 122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 165:d1b4690b3f8b 123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 165:d1b4690b3f8b 124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 165:d1b4690b3f8b 125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 165:d1b4690b3f8b 126 /**
AnnaBridge 165:d1b4690b3f8b 127 * @}
AnnaBridge 165:d1b4690b3f8b 128 */
AnnaBridge 165:d1b4690b3f8b 129
AnnaBridge 165:d1b4690b3f8b 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 165:d1b4690b3f8b 131 * @{
AnnaBridge 165:d1b4690b3f8b 132 */
AnnaBridge 165:d1b4690b3f8b 133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 165:d1b4690b3f8b 161 /**
AnnaBridge 165:d1b4690b3f8b 162 * @}
AnnaBridge 165:d1b4690b3f8b 163 */
AnnaBridge 165:d1b4690b3f8b 164
AnnaBridge 165:d1b4690b3f8b 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 165:d1b4690b3f8b 166 * @{
AnnaBridge 165:d1b4690b3f8b 167 */
AnnaBridge 165:d1b4690b3f8b 168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 165:d1b4690b3f8b 169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 165:d1b4690b3f8b 170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 165:d1b4690b3f8b 171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 165:d1b4690b3f8b 172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 165:d1b4690b3f8b 173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 165:d1b4690b3f8b 174 /**
AnnaBridge 165:d1b4690b3f8b 175 * @}
AnnaBridge 165:d1b4690b3f8b 176 */
AnnaBridge 165:d1b4690b3f8b 177
AnnaBridge 165:d1b4690b3f8b 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 165:d1b4690b3f8b 179 * @{
AnnaBridge 165:d1b4690b3f8b 180 */
AnnaBridge 165:d1b4690b3f8b 181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 165:d1b4690b3f8b 182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 165:d1b4690b3f8b 183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 165:d1b4690b3f8b 184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 165:d1b4690b3f8b 185 /**
AnnaBridge 165:d1b4690b3f8b 186 * @}
AnnaBridge 165:d1b4690b3f8b 187 */
AnnaBridge 165:d1b4690b3f8b 188
AnnaBridge 165:d1b4690b3f8b 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 165:d1b4690b3f8b 190 * @{
AnnaBridge 165:d1b4690b3f8b 191 */
AnnaBridge 165:d1b4690b3f8b 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 165:d1b4690b3f8b 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 165:d1b4690b3f8b 194 /**
AnnaBridge 165:d1b4690b3f8b 195 * @}
AnnaBridge 165:d1b4690b3f8b 196 */
AnnaBridge 165:d1b4690b3f8b 197
AnnaBridge 165:d1b4690b3f8b 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 165:d1b4690b3f8b 199 * @{
AnnaBridge 165:d1b4690b3f8b 200 */
AnnaBridge 165:d1b4690b3f8b 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 165:d1b4690b3f8b 202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 165:d1b4690b3f8b 203 /**
AnnaBridge 165:d1b4690b3f8b 204 * @}
AnnaBridge 165:d1b4690b3f8b 205 */
AnnaBridge 165:d1b4690b3f8b 206
AnnaBridge 165:d1b4690b3f8b 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 165:d1b4690b3f8b 208 * @{
AnnaBridge 165:d1b4690b3f8b 209 */
AnnaBridge 165:d1b4690b3f8b 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 165:d1b4690b3f8b 211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 165:d1b4690b3f8b 212 /**
AnnaBridge 165:d1b4690b3f8b 213 * @}
AnnaBridge 165:d1b4690b3f8b 214 */
AnnaBridge 165:d1b4690b3f8b 215
AnnaBridge 165:d1b4690b3f8b 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 165:d1b4690b3f8b 217 * @{
AnnaBridge 165:d1b4690b3f8b 218 */
AnnaBridge 165:d1b4690b3f8b 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 165:d1b4690b3f8b 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 165:d1b4690b3f8b 221 /**
AnnaBridge 165:d1b4690b3f8b 222 * @}
AnnaBridge 165:d1b4690b3f8b 223 */
AnnaBridge 165:d1b4690b3f8b 224 #endif /* __MPU_PRESENT */
AnnaBridge 165:d1b4690b3f8b 225 /**
AnnaBridge 165:d1b4690b3f8b 226 * @}
AnnaBridge 165:d1b4690b3f8b 227 */
AnnaBridge 165:d1b4690b3f8b 228
AnnaBridge 165:d1b4690b3f8b 229 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 230
AnnaBridge 165:d1b4690b3f8b 231 /* Exported functions --------------------------------------------------------*/
AnnaBridge 165:d1b4690b3f8b 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 165:d1b4690b3f8b 233 * @{
AnnaBridge 165:d1b4690b3f8b 234 */
AnnaBridge 165:d1b4690b3f8b 235
AnnaBridge 165:d1b4690b3f8b 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 165:d1b4690b3f8b 237 * @{
AnnaBridge 165:d1b4690b3f8b 238 */
AnnaBridge 165:d1b4690b3f8b 239
AnnaBridge 165:d1b4690b3f8b 240 /**
AnnaBridge 165:d1b4690b3f8b 241 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 165:d1b4690b3f8b 242 * @note It can be used in timeout function on application side.
AnnaBridge 165:d1b4690b3f8b 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 165:d1b4690b3f8b 244 * @retval State of bit (1 or 0).
AnnaBridge 165:d1b4690b3f8b 245 */
AnnaBridge 165:d1b4690b3f8b 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 165:d1b4690b3f8b 247 {
AnnaBridge 165:d1b4690b3f8b 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 165:d1b4690b3f8b 249 }
AnnaBridge 165:d1b4690b3f8b 250
AnnaBridge 165:d1b4690b3f8b 251 /**
AnnaBridge 165:d1b4690b3f8b 252 * @brief Configures the SysTick clock source
AnnaBridge 165:d1b4690b3f8b 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 165:d1b4690b3f8b 254 * @param Source This parameter can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 165:d1b4690b3f8b 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 165:d1b4690b3f8b 257 * @retval None
AnnaBridge 165:d1b4690b3f8b 258 */
AnnaBridge 165:d1b4690b3f8b 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 165:d1b4690b3f8b 260 {
AnnaBridge 165:d1b4690b3f8b 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 165:d1b4690b3f8b 262 {
AnnaBridge 165:d1b4690b3f8b 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 165:d1b4690b3f8b 264 }
AnnaBridge 165:d1b4690b3f8b 265 else
AnnaBridge 165:d1b4690b3f8b 266 {
AnnaBridge 165:d1b4690b3f8b 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 165:d1b4690b3f8b 268 }
AnnaBridge 165:d1b4690b3f8b 269 }
AnnaBridge 165:d1b4690b3f8b 270
AnnaBridge 165:d1b4690b3f8b 271 /**
AnnaBridge 165:d1b4690b3f8b 272 * @brief Get the SysTick clock source
AnnaBridge 165:d1b4690b3f8b 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 165:d1b4690b3f8b 274 * @retval Returned value can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 165:d1b4690b3f8b 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 165:d1b4690b3f8b 277 */
AnnaBridge 165:d1b4690b3f8b 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 165:d1b4690b3f8b 279 {
AnnaBridge 165:d1b4690b3f8b 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 165:d1b4690b3f8b 281 }
AnnaBridge 165:d1b4690b3f8b 282
AnnaBridge 165:d1b4690b3f8b 283 /**
AnnaBridge 165:d1b4690b3f8b 284 * @brief Enable SysTick exception request
AnnaBridge 165:d1b4690b3f8b 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 165:d1b4690b3f8b 286 * @retval None
AnnaBridge 165:d1b4690b3f8b 287 */
AnnaBridge 165:d1b4690b3f8b 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 165:d1b4690b3f8b 289 {
AnnaBridge 165:d1b4690b3f8b 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 165:d1b4690b3f8b 291 }
AnnaBridge 165:d1b4690b3f8b 292
AnnaBridge 165:d1b4690b3f8b 293 /**
AnnaBridge 165:d1b4690b3f8b 294 * @brief Disable SysTick exception request
AnnaBridge 165:d1b4690b3f8b 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 165:d1b4690b3f8b 296 * @retval None
AnnaBridge 165:d1b4690b3f8b 297 */
AnnaBridge 165:d1b4690b3f8b 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 165:d1b4690b3f8b 299 {
AnnaBridge 165:d1b4690b3f8b 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 165:d1b4690b3f8b 301 }
AnnaBridge 165:d1b4690b3f8b 302
AnnaBridge 165:d1b4690b3f8b 303 /**
AnnaBridge 165:d1b4690b3f8b 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 165:d1b4690b3f8b 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 165:d1b4690b3f8b 306 * @retval State of bit (1 or 0).
AnnaBridge 165:d1b4690b3f8b 307 */
AnnaBridge 165:d1b4690b3f8b 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 165:d1b4690b3f8b 309 {
AnnaBridge 165:d1b4690b3f8b 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 165:d1b4690b3f8b 311 }
AnnaBridge 165:d1b4690b3f8b 312
AnnaBridge 165:d1b4690b3f8b 313 /**
AnnaBridge 165:d1b4690b3f8b 314 * @}
AnnaBridge 165:d1b4690b3f8b 315 */
AnnaBridge 165:d1b4690b3f8b 316
AnnaBridge 165:d1b4690b3f8b 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 165:d1b4690b3f8b 318 * @{
AnnaBridge 165:d1b4690b3f8b 319 */
AnnaBridge 165:d1b4690b3f8b 320
AnnaBridge 165:d1b4690b3f8b 321 /**
AnnaBridge 165:d1b4690b3f8b 322 * @brief Processor uses sleep as its low power mode
AnnaBridge 165:d1b4690b3f8b 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 165:d1b4690b3f8b 324 * @retval None
AnnaBridge 165:d1b4690b3f8b 325 */
AnnaBridge 165:d1b4690b3f8b 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 165:d1b4690b3f8b 327 {
AnnaBridge 165:d1b4690b3f8b 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 165:d1b4690b3f8b 330 }
AnnaBridge 165:d1b4690b3f8b 331
AnnaBridge 165:d1b4690b3f8b 332 /**
AnnaBridge 165:d1b4690b3f8b 333 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 165:d1b4690b3f8b 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 165:d1b4690b3f8b 335 * @retval None
AnnaBridge 165:d1b4690b3f8b 336 */
AnnaBridge 165:d1b4690b3f8b 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 165:d1b4690b3f8b 338 {
AnnaBridge 165:d1b4690b3f8b 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 165:d1b4690b3f8b 341 }
AnnaBridge 165:d1b4690b3f8b 342
AnnaBridge 165:d1b4690b3f8b 343 /**
AnnaBridge 165:d1b4690b3f8b 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 165:d1b4690b3f8b 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 165:d1b4690b3f8b 346 * empty main application.
AnnaBridge 165:d1b4690b3f8b 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 165:d1b4690b3f8b 348 * @retval None
AnnaBridge 165:d1b4690b3f8b 349 */
AnnaBridge 165:d1b4690b3f8b 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 165:d1b4690b3f8b 351 {
AnnaBridge 165:d1b4690b3f8b 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 165:d1b4690b3f8b 354 }
AnnaBridge 165:d1b4690b3f8b 355
AnnaBridge 165:d1b4690b3f8b 356 /**
AnnaBridge 165:d1b4690b3f8b 357 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 165:d1b4690b3f8b 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 165:d1b4690b3f8b 359 * @retval None
AnnaBridge 165:d1b4690b3f8b 360 */
AnnaBridge 165:d1b4690b3f8b 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 165:d1b4690b3f8b 362 {
AnnaBridge 165:d1b4690b3f8b 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 165:d1b4690b3f8b 365 }
AnnaBridge 165:d1b4690b3f8b 366
AnnaBridge 165:d1b4690b3f8b 367 /**
AnnaBridge 165:d1b4690b3f8b 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 165:d1b4690b3f8b 369 * processor.
AnnaBridge 165:d1b4690b3f8b 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 165:d1b4690b3f8b 371 * @retval None
AnnaBridge 165:d1b4690b3f8b 372 */
AnnaBridge 165:d1b4690b3f8b 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 165:d1b4690b3f8b 374 {
AnnaBridge 165:d1b4690b3f8b 375 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 165:d1b4690b3f8b 377 }
AnnaBridge 165:d1b4690b3f8b 378
AnnaBridge 165:d1b4690b3f8b 379 /**
AnnaBridge 165:d1b4690b3f8b 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 165:d1b4690b3f8b 381 * excluded
AnnaBridge 165:d1b4690b3f8b 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 165:d1b4690b3f8b 383 * @retval None
AnnaBridge 165:d1b4690b3f8b 384 */
AnnaBridge 165:d1b4690b3f8b 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 165:d1b4690b3f8b 386 {
AnnaBridge 165:d1b4690b3f8b 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 165:d1b4690b3f8b 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 165:d1b4690b3f8b 389 }
AnnaBridge 165:d1b4690b3f8b 390
AnnaBridge 165:d1b4690b3f8b 391 /**
AnnaBridge 165:d1b4690b3f8b 392 * @}
AnnaBridge 165:d1b4690b3f8b 393 */
AnnaBridge 165:d1b4690b3f8b 394
AnnaBridge 165:d1b4690b3f8b 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 165:d1b4690b3f8b 396 * @{
AnnaBridge 165:d1b4690b3f8b 397 */
AnnaBridge 165:d1b4690b3f8b 398
AnnaBridge 165:d1b4690b3f8b 399 /**
AnnaBridge 165:d1b4690b3f8b 400 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 165:d1b4690b3f8b 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 165:d1b4690b3f8b 402 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 165:d1b4690b3f8b 403 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 165:d1b4690b3f8b 404 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 165:d1b4690b3f8b 405 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 165:d1b4690b3f8b 406 * @retval None
AnnaBridge 165:d1b4690b3f8b 407 */
AnnaBridge 165:d1b4690b3f8b 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 165:d1b4690b3f8b 409 {
AnnaBridge 165:d1b4690b3f8b 410 /* Enable the system handler fault */
AnnaBridge 165:d1b4690b3f8b 411 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 165:d1b4690b3f8b 412 }
AnnaBridge 165:d1b4690b3f8b 413
AnnaBridge 165:d1b4690b3f8b 414 /**
AnnaBridge 165:d1b4690b3f8b 415 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 165:d1b4690b3f8b 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 165:d1b4690b3f8b 417 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 165:d1b4690b3f8b 418 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 165:d1b4690b3f8b 419 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 165:d1b4690b3f8b 420 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 165:d1b4690b3f8b 421 * @retval None
AnnaBridge 165:d1b4690b3f8b 422 */
AnnaBridge 165:d1b4690b3f8b 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 165:d1b4690b3f8b 424 {
AnnaBridge 165:d1b4690b3f8b 425 /* Disable the system handler fault */
AnnaBridge 165:d1b4690b3f8b 426 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 165:d1b4690b3f8b 427 }
AnnaBridge 165:d1b4690b3f8b 428
AnnaBridge 165:d1b4690b3f8b 429 /**
AnnaBridge 165:d1b4690b3f8b 430 * @}
AnnaBridge 165:d1b4690b3f8b 431 */
AnnaBridge 165:d1b4690b3f8b 432
AnnaBridge 165:d1b4690b3f8b 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 165:d1b4690b3f8b 434 * @{
AnnaBridge 165:d1b4690b3f8b 435 */
AnnaBridge 165:d1b4690b3f8b 436
AnnaBridge 165:d1b4690b3f8b 437 /**
AnnaBridge 165:d1b4690b3f8b 438 * @brief Get Implementer code
AnnaBridge 165:d1b4690b3f8b 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 165:d1b4690b3f8b 440 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 165:d1b4690b3f8b 441 */
AnnaBridge 165:d1b4690b3f8b 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 165:d1b4690b3f8b 443 {
AnnaBridge 165:d1b4690b3f8b 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 165:d1b4690b3f8b 445 }
AnnaBridge 165:d1b4690b3f8b 446
AnnaBridge 165:d1b4690b3f8b 447 /**
AnnaBridge 165:d1b4690b3f8b 448 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 165:d1b4690b3f8b 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 165:d1b4690b3f8b 450 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 165:d1b4690b3f8b 451 */
AnnaBridge 165:d1b4690b3f8b 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 165:d1b4690b3f8b 453 {
AnnaBridge 165:d1b4690b3f8b 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 165:d1b4690b3f8b 455 }
AnnaBridge 165:d1b4690b3f8b 456
AnnaBridge 165:d1b4690b3f8b 457 /**
AnnaBridge 165:d1b4690b3f8b 458 * @brief Get Constant number
AnnaBridge 165:d1b4690b3f8b 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 165:d1b4690b3f8b 460 * @retval Value should be equal to 0xF for Cortex-M4 devices
AnnaBridge 165:d1b4690b3f8b 461 */
AnnaBridge 165:d1b4690b3f8b 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 165:d1b4690b3f8b 463 {
AnnaBridge 165:d1b4690b3f8b 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 165:d1b4690b3f8b 465 }
AnnaBridge 165:d1b4690b3f8b 466
AnnaBridge 165:d1b4690b3f8b 467 /**
AnnaBridge 165:d1b4690b3f8b 468 * @brief Get Part number
AnnaBridge 165:d1b4690b3f8b 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 165:d1b4690b3f8b 470 * @retval Value should be equal to 0xC24 for Cortex-M4
AnnaBridge 165:d1b4690b3f8b 471 */
AnnaBridge 165:d1b4690b3f8b 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 165:d1b4690b3f8b 473 {
AnnaBridge 165:d1b4690b3f8b 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 165:d1b4690b3f8b 475 }
AnnaBridge 165:d1b4690b3f8b 476
AnnaBridge 165:d1b4690b3f8b 477 /**
AnnaBridge 165:d1b4690b3f8b 478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 165:d1b4690b3f8b 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 165:d1b4690b3f8b 480 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 165:d1b4690b3f8b 481 */
AnnaBridge 165:d1b4690b3f8b 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 165:d1b4690b3f8b 483 {
AnnaBridge 165:d1b4690b3f8b 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 165:d1b4690b3f8b 485 }
AnnaBridge 165:d1b4690b3f8b 486
AnnaBridge 165:d1b4690b3f8b 487 /**
AnnaBridge 165:d1b4690b3f8b 488 * @}
AnnaBridge 165:d1b4690b3f8b 489 */
AnnaBridge 165:d1b4690b3f8b 490
AnnaBridge 165:d1b4690b3f8b 491 #if __MPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 492 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 165:d1b4690b3f8b 493 * @{
AnnaBridge 165:d1b4690b3f8b 494 */
AnnaBridge 165:d1b4690b3f8b 495
AnnaBridge 165:d1b4690b3f8b 496 /**
AnnaBridge 165:d1b4690b3f8b 497 * @brief Enable MPU with input options
AnnaBridge 165:d1b4690b3f8b 498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 165:d1b4690b3f8b 499 * @param Options This parameter can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 165:d1b4690b3f8b 501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 165:d1b4690b3f8b 502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 165:d1b4690b3f8b 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 165:d1b4690b3f8b 504 * @retval None
AnnaBridge 165:d1b4690b3f8b 505 */
AnnaBridge 165:d1b4690b3f8b 506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 165:d1b4690b3f8b 507 {
AnnaBridge 165:d1b4690b3f8b 508 /* Enable the MPU*/
AnnaBridge 165:d1b4690b3f8b 509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 165:d1b4690b3f8b 510 /* Ensure MPU settings take effects */
AnnaBridge 165:d1b4690b3f8b 511 __DSB();
AnnaBridge 165:d1b4690b3f8b 512 /* Sequence instruction fetches using update settings */
AnnaBridge 165:d1b4690b3f8b 513 __ISB();
AnnaBridge 165:d1b4690b3f8b 514 }
AnnaBridge 165:d1b4690b3f8b 515
AnnaBridge 165:d1b4690b3f8b 516 /**
AnnaBridge 165:d1b4690b3f8b 517 * @brief Disable MPU
AnnaBridge 165:d1b4690b3f8b 518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 165:d1b4690b3f8b 519 * @retval None
AnnaBridge 165:d1b4690b3f8b 520 */
AnnaBridge 165:d1b4690b3f8b 521 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 522 {
AnnaBridge 165:d1b4690b3f8b 523 /* Make sure outstanding transfers are done */
AnnaBridge 165:d1b4690b3f8b 524 __DMB();
AnnaBridge 165:d1b4690b3f8b 525 /* Disable MPU*/
AnnaBridge 165:d1b4690b3f8b 526 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 165:d1b4690b3f8b 527 }
AnnaBridge 165:d1b4690b3f8b 528
AnnaBridge 165:d1b4690b3f8b 529 /**
AnnaBridge 165:d1b4690b3f8b 530 * @brief Check if MPU is enabled or not
AnnaBridge 165:d1b4690b3f8b 531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 165:d1b4690b3f8b 532 * @retval State of bit (1 or 0).
AnnaBridge 165:d1b4690b3f8b 533 */
AnnaBridge 165:d1b4690b3f8b 534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 165:d1b4690b3f8b 535 {
AnnaBridge 165:d1b4690b3f8b 536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 165:d1b4690b3f8b 537 }
AnnaBridge 165:d1b4690b3f8b 538
AnnaBridge 165:d1b4690b3f8b 539 /**
AnnaBridge 165:d1b4690b3f8b 540 * @brief Enable a MPU region
AnnaBridge 165:d1b4690b3f8b 541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 165:d1b4690b3f8b 542 * @param Region This parameter can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 543 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 165:d1b4690b3f8b 544 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 165:d1b4690b3f8b 545 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 165:d1b4690b3f8b 546 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 165:d1b4690b3f8b 547 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 165:d1b4690b3f8b 548 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 165:d1b4690b3f8b 549 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 165:d1b4690b3f8b 550 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 165:d1b4690b3f8b 551 * @retval None
AnnaBridge 165:d1b4690b3f8b 552 */
AnnaBridge 165:d1b4690b3f8b 553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 165:d1b4690b3f8b 554 {
AnnaBridge 165:d1b4690b3f8b 555 /* Set Region number */
AnnaBridge 165:d1b4690b3f8b 556 WRITE_REG(MPU->RNR, Region);
AnnaBridge 165:d1b4690b3f8b 557 /* Enable the MPU region */
AnnaBridge 165:d1b4690b3f8b 558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 165:d1b4690b3f8b 559 }
AnnaBridge 165:d1b4690b3f8b 560
AnnaBridge 165:d1b4690b3f8b 561 /**
AnnaBridge 165:d1b4690b3f8b 562 * @brief Configure and enable a region
AnnaBridge 165:d1b4690b3f8b 563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 566 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 567 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 568 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 569 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 570 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 165:d1b4690b3f8b 571 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 165:d1b4690b3f8b 572 * @param Region This parameter can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 573 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 165:d1b4690b3f8b 574 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 165:d1b4690b3f8b 575 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 165:d1b4690b3f8b 576 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 165:d1b4690b3f8b 577 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 165:d1b4690b3f8b 578 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 165:d1b4690b3f8b 579 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 165:d1b4690b3f8b 580 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 165:d1b4690b3f8b 581 * @param Address Value of region base address
AnnaBridge 165:d1b4690b3f8b 582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 165:d1b4690b3f8b 583 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 165:d1b4690b3f8b 584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 165:d1b4690b3f8b 585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 165:d1b4690b3f8b 586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 165:d1b4690b3f8b 587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 165:d1b4690b3f8b 588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 165:d1b4690b3f8b 589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 165:d1b4690b3f8b 590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 165:d1b4690b3f8b 591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 165:d1b4690b3f8b 592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 165:d1b4690b3f8b 593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 165:d1b4690b3f8b 594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 165:d1b4690b3f8b 595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 165:d1b4690b3f8b 596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 165:d1b4690b3f8b 597 * @retval None
AnnaBridge 165:d1b4690b3f8b 598 */
AnnaBridge 165:d1b4690b3f8b 599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 165:d1b4690b3f8b 600 {
AnnaBridge 165:d1b4690b3f8b 601 /* Set Region number */
AnnaBridge 165:d1b4690b3f8b 602 WRITE_REG(MPU->RNR, Region);
AnnaBridge 165:d1b4690b3f8b 603 /* Set base address */
AnnaBridge 165:d1b4690b3f8b 604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 165:d1b4690b3f8b 605 /* Configure MPU */
AnnaBridge 165:d1b4690b3f8b 606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 165:d1b4690b3f8b 607 }
AnnaBridge 165:d1b4690b3f8b 608
AnnaBridge 165:d1b4690b3f8b 609 /**
AnnaBridge 165:d1b4690b3f8b 610 * @brief Disable a region
AnnaBridge 165:d1b4690b3f8b 611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 165:d1b4690b3f8b 612 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 165:d1b4690b3f8b 613 * @param Region This parameter can be one of the following values:
AnnaBridge 165:d1b4690b3f8b 614 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 165:d1b4690b3f8b 615 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 165:d1b4690b3f8b 616 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 165:d1b4690b3f8b 617 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 165:d1b4690b3f8b 618 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 165:d1b4690b3f8b 619 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 165:d1b4690b3f8b 620 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 165:d1b4690b3f8b 621 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 165:d1b4690b3f8b 622 * @retval None
AnnaBridge 165:d1b4690b3f8b 623 */
AnnaBridge 165:d1b4690b3f8b 624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 165:d1b4690b3f8b 625 {
AnnaBridge 165:d1b4690b3f8b 626 /* Set Region number */
AnnaBridge 165:d1b4690b3f8b 627 WRITE_REG(MPU->RNR, Region);
AnnaBridge 165:d1b4690b3f8b 628 /* Disable the MPU region */
AnnaBridge 165:d1b4690b3f8b 629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 165:d1b4690b3f8b 630 }
AnnaBridge 165:d1b4690b3f8b 631
AnnaBridge 165:d1b4690b3f8b 632 /**
AnnaBridge 165:d1b4690b3f8b 633 * @}
AnnaBridge 165:d1b4690b3f8b 634 */
AnnaBridge 165:d1b4690b3f8b 635
AnnaBridge 165:d1b4690b3f8b 636 #endif /* __MPU_PRESENT */
AnnaBridge 165:d1b4690b3f8b 637 /**
AnnaBridge 165:d1b4690b3f8b 638 * @}
AnnaBridge 165:d1b4690b3f8b 639 */
AnnaBridge 165:d1b4690b3f8b 640
AnnaBridge 165:d1b4690b3f8b 641 /**
AnnaBridge 165:d1b4690b3f8b 642 * @}
AnnaBridge 165:d1b4690b3f8b 643 */
AnnaBridge 165:d1b4690b3f8b 644
AnnaBridge 165:d1b4690b3f8b 645 /**
AnnaBridge 165:d1b4690b3f8b 646 * @}
AnnaBridge 165:d1b4690b3f8b 647 */
AnnaBridge 165:d1b4690b3f8b 648
AnnaBridge 165:d1b4690b3f8b 649 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 650 }
AnnaBridge 165:d1b4690b3f8b 651 #endif
AnnaBridge 165:d1b4690b3f8b 652
AnnaBridge 165:d1b4690b3f8b 653 #endif /* __STM32L4xx_LL_CORTEX_H */
AnnaBridge 165:d1b4690b3f8b 654
AnnaBridge 165:d1b4690b3f8b 655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/