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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_hal_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_hal_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32L1xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32L1xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32l1xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup RCC
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/** @addtogroup RCC_Private_Constants
AnnaBridge	171:3a7713b1edbc	56	* @{
AnnaBridge	171:3a7713b1edbc	57	*/
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup RCC_Timeout RCC Timeout
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	/* Disable Backup domain write protection state change timeout */
AnnaBridge	171:3a7713b1edbc	64	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
AnnaBridge	171:3a7713b1edbc	65	/* LSE state change timeout */
AnnaBridge	171:3a7713b1edbc	66	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	67	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
AnnaBridge	171:3a7713b1edbc	68	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	69	#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	70	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	71	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	72	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	73	/**
AnnaBridge	171:3a7713b1edbc	74	* @}
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	/** @defgroup RCC_Register_Offset Register offsets
AnnaBridge	171:3a7713b1edbc	78	* @{
AnnaBridge	171:3a7713b1edbc	79	*/
AnnaBridge	171:3a7713b1edbc	80	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	171:3a7713b1edbc	81	#define RCC_CR_OFFSET 0x00
AnnaBridge	171:3a7713b1edbc	82	#define RCC_CFGR_OFFSET 0x08
AnnaBridge	171:3a7713b1edbc	83	#define RCC_CIR_OFFSET 0x0C
AnnaBridge	171:3a7713b1edbc	84	#define RCC_CSR_OFFSET 0x34
AnnaBridge	171:3a7713b1edbc	85	/**
AnnaBridge	171:3a7713b1edbc	86	* @}
AnnaBridge	171:3a7713b1edbc	87	*/
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge	171:3a7713b1edbc	90	* @brief RCC registers bit address in the alias region
AnnaBridge	171:3a7713b1edbc	91	* @{
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
AnnaBridge	171:3a7713b1edbc	94	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
AnnaBridge	171:3a7713b1edbc	95	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
AnnaBridge	171:3a7713b1edbc	96	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	/* --- CR Register ---*/
AnnaBridge	171:3a7713b1edbc	99	/* Alias word address of HSION bit */
AnnaBridge	171:3a7713b1edbc	100	#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
AnnaBridge	171:3a7713b1edbc	101	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	102	/* Alias word address of MSION bit */
AnnaBridge	171:3a7713b1edbc	103	#define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION)
AnnaBridge	171:3a7713b1edbc	104	#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	105	/* Alias word address of HSEON bit */
AnnaBridge	171:3a7713b1edbc	106	#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
AnnaBridge	171:3a7713b1edbc	107	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	108	/* Alias word address of CSSON bit */
AnnaBridge	171:3a7713b1edbc	109	#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
AnnaBridge	171:3a7713b1edbc	110	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	111	/* Alias word address of PLLON bit */
AnnaBridge	171:3a7713b1edbc	112	#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
AnnaBridge	171:3a7713b1edbc	113	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	/* --- CSR Register ---*/
AnnaBridge	171:3a7713b1edbc	116	/* Alias word address of LSION bit */
AnnaBridge	171:3a7713b1edbc	117	#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
AnnaBridge	171:3a7713b1edbc	118	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	119
AnnaBridge	171:3a7713b1edbc	120	/* Alias word address of RMVF bit */
AnnaBridge	171:3a7713b1edbc	121	#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
AnnaBridge	171:3a7713b1edbc	122	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	/* Alias word address of LSEON bit */
AnnaBridge	171:3a7713b1edbc	125	#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON)
AnnaBridge	171:3a7713b1edbc	126	#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128	/* Alias word address of LSEON bit */
AnnaBridge	171:3a7713b1edbc	129	#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP)
AnnaBridge	171:3a7713b1edbc	130	#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	/* Alias word address of RTCEN bit */
AnnaBridge	171:3a7713b1edbc	133	#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN)
AnnaBridge	171:3a7713b1edbc	134	#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	135
AnnaBridge	171:3a7713b1edbc	136	/* Alias word address of RTCRST bit */
AnnaBridge	171:3a7713b1edbc	137	#define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST)
AnnaBridge	171:3a7713b1edbc	138	#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	/**
AnnaBridge	171:3a7713b1edbc	141	* @}
AnnaBridge	171:3a7713b1edbc	142	*/
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	145	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	/* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge	171:3a7713b1edbc	148	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150	/* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	151	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge	171:3a7713b1edbc	152
AnnaBridge	171:3a7713b1edbc	153	/* Defines used for Flags */
AnnaBridge	171:3a7713b1edbc	154	#define CR_REG_INDEX ((uint8_t)1U)
AnnaBridge	171:3a7713b1edbc	155	#define CSR_REG_INDEX ((uint8_t)2U)
AnnaBridge	171:3a7713b1edbc	156
AnnaBridge	171:3a7713b1edbc	157	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/**
AnnaBridge	171:3a7713b1edbc	160	* @}
AnnaBridge	171:3a7713b1edbc	161	*/
AnnaBridge	171:3a7713b1edbc	162
AnnaBridge	171:3a7713b1edbc	163	/** @addtogroup RCC_Private_Macros
AnnaBridge	171:3a7713b1edbc	164	* @{
AnnaBridge	171:3a7713b1edbc	165	*/
AnnaBridge	171:3a7713b1edbc	166	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	167	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	171:3a7713b1edbc	168	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	171:3a7713b1edbc	169	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	171:3a7713b1edbc	170	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	171	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	171:3a7713b1edbc	172	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
AnnaBridge	171:3a7713b1edbc	174	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	175	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	176	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	177	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	178	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	171:3a7713b1edbc	179	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge	171:3a7713b1edbc	180	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
AnnaBridge	171:3a7713b1edbc	181	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
AnnaBridge	171:3a7713b1edbc	182	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
AnnaBridge	171:3a7713b1edbc	183	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
AnnaBridge	171:3a7713b1edbc	184	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
AnnaBridge	171:3a7713b1edbc	185	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	171:3a7713b1edbc	186	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	171:3a7713b1edbc	187	((__RANGE__) == RCC_MSIRANGE_6))
AnnaBridge	171:3a7713b1edbc	188	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	171:3a7713b1edbc	189	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
AnnaBridge	171:3a7713b1edbc	190
AnnaBridge	171:3a7713b1edbc	191	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	171:3a7713b1edbc	192	((__PLL__) == RCC_PLL_ON))
AnnaBridge	171:3a7713b1edbc	193	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	194	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
AnnaBridge	171:3a7713b1edbc	197	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
AnnaBridge	171:3a7713b1edbc	198	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
AnnaBridge	171:3a7713b1edbc	199	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
AnnaBridge	171:3a7713b1edbc	200	((__MUL__) == RCC_PLL_MUL48))
AnnaBridge	171:3a7713b1edbc	201	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	202	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	203	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
AnnaBridge	171:3a7713b1edbc	204	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge	171:3a7713b1edbc	205	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
AnnaBridge	171:3a7713b1edbc	206	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	207	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	171:3a7713b1edbc	208	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	171:3a7713b1edbc	209	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) \|\| \
AnnaBridge	171:3a7713b1edbc	210	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	211	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	171:3a7713b1edbc	212	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge	171:3a7713b1edbc	213	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	214	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	215	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	171:3a7713b1edbc	216	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	171:3a7713b1edbc	217	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	171:3a7713b1edbc	218	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	219	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	220	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	171:3a7713b1edbc	221	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge	171:3a7713b1edbc	222	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
AnnaBridge	171:3a7713b1edbc	223	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
AnnaBridge	171:3a7713b1edbc	224	((__DIV__) == RCC_MCODIV_16))
AnnaBridge	171:3a7713b1edbc	225	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
AnnaBridge	171:3a7713b1edbc	226	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
AnnaBridge	171:3a7713b1edbc	227	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
AnnaBridge	171:3a7713b1edbc	228	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
AnnaBridge	171:3a7713b1edbc	229	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	171:3a7713b1edbc	230	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	231	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	171:3a7713b1edbc	232	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	233	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	234	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	235	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	/**
AnnaBridge	171:3a7713b1edbc	238	* @}
AnnaBridge	171:3a7713b1edbc	239	*/
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	242
AnnaBridge	171:3a7713b1edbc	243	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	244	* @{
AnnaBridge	171:3a7713b1edbc	245	*/
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	/**
AnnaBridge	171:3a7713b1edbc	248	* @brief RCC PLL configuration structure definition
AnnaBridge	171:3a7713b1edbc	249	*/
AnnaBridge	171:3a7713b1edbc	250	typedef struct
AnnaBridge	171:3a7713b1edbc	251	{
AnnaBridge	171:3a7713b1edbc	252	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge	171:3a7713b1edbc	253	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	256	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	171:3a7713b1edbc	257
AnnaBridge	171:3a7713b1edbc	258	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	259	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	262	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
AnnaBridge	171:3a7713b1edbc	263	} RCC_PLLInitTypeDef;
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	/**
AnnaBridge	171:3a7713b1edbc	266	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	171:3a7713b1edbc	267	*/
AnnaBridge	171:3a7713b1edbc	268	typedef struct
AnnaBridge	171:3a7713b1edbc	269	{
AnnaBridge	171:3a7713b1edbc	270	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	171:3a7713b1edbc	271	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	171:3a7713b1edbc	274	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	171:3a7713b1edbc	275
AnnaBridge	171:3a7713b1edbc	276	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	171:3a7713b1edbc	277	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	171:3a7713b1edbc	280	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	171:3a7713b1edbc	281
AnnaBridge	171:3a7713b1edbc	282	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	283	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
AnnaBridge	171:3a7713b1edbc	284
AnnaBridge	171:3a7713b1edbc	285	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	171:3a7713b1edbc	286	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge	171:3a7713b1edbc	289	This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	292	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
AnnaBridge	171:3a7713b1edbc	293
AnnaBridge	171:3a7713b1edbc	294	uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge	171:3a7713b1edbc	295	This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	} RCC_OscInitTypeDef;
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	/**
AnnaBridge	171:3a7713b1edbc	302	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	171:3a7713b1edbc	303	*/
AnnaBridge	171:3a7713b1edbc	304	typedef struct
AnnaBridge	171:3a7713b1edbc	305	{
AnnaBridge	171:3a7713b1edbc	306	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	171:3a7713b1edbc	307	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	171:3a7713b1edbc	310	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	171:3a7713b1edbc	311
AnnaBridge	171:3a7713b1edbc	312	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	171:3a7713b1edbc	313	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	171:3a7713b1edbc	316	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	171:3a7713b1edbc	317
AnnaBridge	171:3a7713b1edbc	318	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	171:3a7713b1edbc	319	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	171:3a7713b1edbc	320	} RCC_ClkInitTypeDef;
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322	/**
AnnaBridge	171:3a7713b1edbc	323	* @}
AnnaBridge	171:3a7713b1edbc	324	*/
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	327	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	328	* @{
AnnaBridge	171:3a7713b1edbc	329	*/
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	171:3a7713b1edbc	332	* @{
AnnaBridge	171:3a7713b1edbc	333	*/
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	336	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/**
AnnaBridge	171:3a7713b1edbc	339	* @}
AnnaBridge	171:3a7713b1edbc	340	*/
AnnaBridge	171:3a7713b1edbc	341
AnnaBridge	171:3a7713b1edbc	342	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	171:3a7713b1edbc	343	* @{
AnnaBridge	171:3a7713b1edbc	344	*/
AnnaBridge	171:3a7713b1edbc	345	#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
AnnaBridge	171:3a7713b1edbc	346	#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
AnnaBridge	171:3a7713b1edbc	347	#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
AnnaBridge	171:3a7713b1edbc	348	#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
AnnaBridge	171:3a7713b1edbc	349	#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
AnnaBridge	171:3a7713b1edbc	350	#define RCC_OSCILLATORTYPE_MSI (0x00000010U)
AnnaBridge	171:3a7713b1edbc	351	/**
AnnaBridge	171:3a7713b1edbc	352	* @}
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	171:3a7713b1edbc	356	* @{
AnnaBridge	171:3a7713b1edbc	357	*/
AnnaBridge	171:3a7713b1edbc	358	#define RCC_HSE_OFF (0x00000000U) /!< HSE clock deactivation /
AnnaBridge	171:3a7713b1edbc	359	#define RCC_HSE_ON (0x00000001U) /!< HSE clock activation /
AnnaBridge	171:3a7713b1edbc	360	#define RCC_HSE_BYPASS (0x00000005U) /!< External clock source for HSE clock /
AnnaBridge	171:3a7713b1edbc	361	/**
AnnaBridge	171:3a7713b1edbc	362	* @}
AnnaBridge	171:3a7713b1edbc	363	*/
AnnaBridge	171:3a7713b1edbc	364
AnnaBridge	171:3a7713b1edbc	365	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	171:3a7713b1edbc	366	* @{
AnnaBridge	171:3a7713b1edbc	367	*/
AnnaBridge	171:3a7713b1edbc	368	#define RCC_LSE_OFF (0x00000000U) /!< LSE clock deactivation /
AnnaBridge	171:3a7713b1edbc	369	#define RCC_LSE_ON (0x00000001U) /!< LSE clock activation /
AnnaBridge	171:3a7713b1edbc	370	#define RCC_LSE_BYPASS (0x00000005U) /!< External clock source for LSE clock /
AnnaBridge	171:3a7713b1edbc	371
AnnaBridge	171:3a7713b1edbc	372	/**
AnnaBridge	171:3a7713b1edbc	373	* @}
AnnaBridge	171:3a7713b1edbc	374	*/
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	171:3a7713b1edbc	377	* @{
AnnaBridge	171:3a7713b1edbc	378	*/
AnnaBridge	171:3a7713b1edbc	379	#define RCC_HSI_OFF (0x00000000U) /!< HSI clock deactivation /
AnnaBridge	171:3a7713b1edbc	380	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382	#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
AnnaBridge	171:3a7713b1edbc	383
AnnaBridge	171:3a7713b1edbc	384	/**
AnnaBridge	171:3a7713b1edbc	385	* @}
AnnaBridge	171:3a7713b1edbc	386	*/
AnnaBridge	171:3a7713b1edbc	387
AnnaBridge	171:3a7713b1edbc	388	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
AnnaBridge	171:3a7713b1edbc	389	* @{
AnnaBridge	171:3a7713b1edbc	390	*/
AnnaBridge	171:3a7713b1edbc	391
AnnaBridge	171:3a7713b1edbc	392	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
AnnaBridge	171:3a7713b1edbc	393	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
AnnaBridge	171:3a7713b1edbc	394	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
AnnaBridge	171:3a7713b1edbc	395	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
AnnaBridge	171:3a7713b1edbc	396	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
AnnaBridge	171:3a7713b1edbc	397	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
AnnaBridge	171:3a7713b1edbc	398	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
AnnaBridge	171:3a7713b1edbc	399
AnnaBridge	171:3a7713b1edbc	400	/**
AnnaBridge	171:3a7713b1edbc	401	* @}
AnnaBridge	171:3a7713b1edbc	402	*/
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	171:3a7713b1edbc	405	* @{
AnnaBridge	171:3a7713b1edbc	406	*/
AnnaBridge	171:3a7713b1edbc	407	#define RCC_LSI_OFF (0x00000000U) /!< LSI clock deactivation /
AnnaBridge	171:3a7713b1edbc	408	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	171:3a7713b1edbc	409
AnnaBridge	171:3a7713b1edbc	410	/**
AnnaBridge	171:3a7713b1edbc	411	* @}
AnnaBridge	171:3a7713b1edbc	412	*/
AnnaBridge	171:3a7713b1edbc	413
AnnaBridge	171:3a7713b1edbc	414	/** @defgroup RCC_MSI_Config MSI Config
AnnaBridge	171:3a7713b1edbc	415	* @{
AnnaBridge	171:3a7713b1edbc	416	*/
AnnaBridge	171:3a7713b1edbc	417	#define RCC_MSI_OFF (0x00000000U)
AnnaBridge	171:3a7713b1edbc	418	#define RCC_MSI_ON (0x00000001U)
AnnaBridge	171:3a7713b1edbc	419
AnnaBridge	171:3a7713b1edbc	420	#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	/**
AnnaBridge	171:3a7713b1edbc	423	* @}
AnnaBridge	171:3a7713b1edbc	424	*/
AnnaBridge	171:3a7713b1edbc	425
AnnaBridge	171:3a7713b1edbc	426	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	171:3a7713b1edbc	427	* @{
AnnaBridge	171:3a7713b1edbc	428	*/
AnnaBridge	171:3a7713b1edbc	429	#define RCC_PLL_NONE (0x00000000U) /!< PLL is not configured /
AnnaBridge	171:3a7713b1edbc	430	#define RCC_PLL_OFF (0x00000001U) /!< PLL deactivation /
AnnaBridge	171:3a7713b1edbc	431	#define RCC_PLL_ON (0x00000002U) /!< PLL activation /
AnnaBridge	171:3a7713b1edbc	432
AnnaBridge	171:3a7713b1edbc	433	/**
AnnaBridge	171:3a7713b1edbc	434	* @}
AnnaBridge	171:3a7713b1edbc	435	*/
AnnaBridge	171:3a7713b1edbc	436
AnnaBridge	171:3a7713b1edbc	437	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	171:3a7713b1edbc	438	* @{
AnnaBridge	171:3a7713b1edbc	439	*/
AnnaBridge	171:3a7713b1edbc	440	#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /!< SYSCLK to configure /
AnnaBridge	171:3a7713b1edbc	441	#define RCC_CLOCKTYPE_HCLK (0x00000002U) /!< HCLK to configure /
AnnaBridge	171:3a7713b1edbc	442	#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /!< PCLK1 to configure /
AnnaBridge	171:3a7713b1edbc	443	#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /!< PCLK2 to configure /
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	/**
AnnaBridge	171:3a7713b1edbc	446	* @}
AnnaBridge	171:3a7713b1edbc	447	*/
AnnaBridge	171:3a7713b1edbc	448
AnnaBridge	171:3a7713b1edbc	449	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	171:3a7713b1edbc	450	* @{
AnnaBridge	171:3a7713b1edbc	451	*/
AnnaBridge	171:3a7713b1edbc	452	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selected as system clock /
AnnaBridge	171:3a7713b1edbc	453	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
AnnaBridge	171:3a7713b1edbc	454	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
AnnaBridge	171:3a7713b1edbc	455	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
AnnaBridge	171:3a7713b1edbc	456
AnnaBridge	171:3a7713b1edbc	457	/**
AnnaBridge	171:3a7713b1edbc	458	* @}
AnnaBridge	171:3a7713b1edbc	459	*/
AnnaBridge	171:3a7713b1edbc	460
AnnaBridge	171:3a7713b1edbc	461	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	171:3a7713b1edbc	462	* @{
AnnaBridge	171:3a7713b1edbc	463	*/
AnnaBridge	171:3a7713b1edbc	464	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	171:3a7713b1edbc	465	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	466	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	467	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	/**
AnnaBridge	171:3a7713b1edbc	470	* @}
AnnaBridge	171:3a7713b1edbc	471	*/
AnnaBridge	171:3a7713b1edbc	472
AnnaBridge	171:3a7713b1edbc	473	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	171:3a7713b1edbc	474	* @{
AnnaBridge	171:3a7713b1edbc	475	*/
AnnaBridge	171:3a7713b1edbc	476	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	171:3a7713b1edbc	477	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	478	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	479	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	480	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	481	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	171:3a7713b1edbc	482	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	171:3a7713b1edbc	483	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	171:3a7713b1edbc	484	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	171:3a7713b1edbc	485
AnnaBridge	171:3a7713b1edbc	486	/**
AnnaBridge	171:3a7713b1edbc	487	* @}
AnnaBridge	171:3a7713b1edbc	488	*/
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge	171:3a7713b1edbc	491	* @{
AnnaBridge	171:3a7713b1edbc	492	*/
AnnaBridge	171:3a7713b1edbc	493	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	494	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	495	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	496	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	497	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	498
AnnaBridge	171:3a7713b1edbc	499	/**
AnnaBridge	171:3a7713b1edbc	500	* @}
AnnaBridge	171:3a7713b1edbc	501	*/
AnnaBridge	171:3a7713b1edbc	502
AnnaBridge	171:3a7713b1edbc	503	/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
AnnaBridge	171:3a7713b1edbc	504	* @{
AnnaBridge	171:3a7713b1edbc	505	*/
AnnaBridge	171:3a7713b1edbc	506	#define RCC_RTC_HSE_DIV_2 0x00000000U /!< HSE is divided by 2 for RTC clock /
AnnaBridge	171:3a7713b1edbc	507	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
AnnaBridge	171:3a7713b1edbc	508	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
AnnaBridge	171:3a7713b1edbc	509	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
AnnaBridge	171:3a7713b1edbc	510	/**
AnnaBridge	171:3a7713b1edbc	511	* @}
AnnaBridge	171:3a7713b1edbc	512	*/
AnnaBridge	171:3a7713b1edbc	513
AnnaBridge	171:3a7713b1edbc	514	/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
AnnaBridge	171:3a7713b1edbc	515	* @{
AnnaBridge	171:3a7713b1edbc	516	*/
AnnaBridge	171:3a7713b1edbc	517	#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /!< No clock /
AnnaBridge	171:3a7713b1edbc	518	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	519	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	520	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /!< HSE oscillator clock divided by X used as RTC clock /
AnnaBridge	171:3a7713b1edbc	521	#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 2 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	522	#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 4 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	523	#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 8 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	524	#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 16 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	525	/**
AnnaBridge	171:3a7713b1edbc	526	* @}
AnnaBridge	171:3a7713b1edbc	527	*/
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
AnnaBridge	171:3a7713b1edbc	530	* @{
AnnaBridge	171:3a7713b1edbc	531	*/
AnnaBridge	171:3a7713b1edbc	532
AnnaBridge	171:3a7713b1edbc	533	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
AnnaBridge	171:3a7713b1edbc	534	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
AnnaBridge	171:3a7713b1edbc	535	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
AnnaBridge	171:3a7713b1edbc	536
AnnaBridge	171:3a7713b1edbc	537	/**
AnnaBridge	171:3a7713b1edbc	538	* @}
AnnaBridge	171:3a7713b1edbc	539	*/
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
AnnaBridge	171:3a7713b1edbc	542	* @{
AnnaBridge	171:3a7713b1edbc	543	*/
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
AnnaBridge	171:3a7713b1edbc	546	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
AnnaBridge	171:3a7713b1edbc	547	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
AnnaBridge	171:3a7713b1edbc	548	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
AnnaBridge	171:3a7713b1edbc	549	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
AnnaBridge	171:3a7713b1edbc	550	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
AnnaBridge	171:3a7713b1edbc	551	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
AnnaBridge	171:3a7713b1edbc	552	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
AnnaBridge	171:3a7713b1edbc	553	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/**
AnnaBridge	171:3a7713b1edbc	556	* @}
AnnaBridge	171:3a7713b1edbc	557	*/
AnnaBridge	171:3a7713b1edbc	558
AnnaBridge	171:3a7713b1edbc	559	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	171:3a7713b1edbc	560	* @{
AnnaBridge	171:3a7713b1edbc	561	*/
AnnaBridge	171:3a7713b1edbc	562	#define RCC_MCO1 (0x00000000U)
AnnaBridge	171:3a7713b1edbc	563	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/**
AnnaBridge	171:3a7713b1edbc	566	* @}
AnnaBridge	171:3a7713b1edbc	567	*/
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
AnnaBridge	171:3a7713b1edbc	570	* @{
AnnaBridge	171:3a7713b1edbc	571	*/
AnnaBridge	171:3a7713b1edbc	572	#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
AnnaBridge	171:3a7713b1edbc	573	#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
AnnaBridge	171:3a7713b1edbc	574	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
AnnaBridge	171:3a7713b1edbc	575	#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
AnnaBridge	171:3a7713b1edbc	576	#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
AnnaBridge	171:3a7713b1edbc	577
AnnaBridge	171:3a7713b1edbc	578	/**
AnnaBridge	171:3a7713b1edbc	579	* @}
AnnaBridge	171:3a7713b1edbc	580	*/
AnnaBridge	171:3a7713b1edbc	581
AnnaBridge	171:3a7713b1edbc	582	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	171:3a7713b1edbc	583	* @{
AnnaBridge	171:3a7713b1edbc	584	*/
AnnaBridge	171:3a7713b1edbc	585	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge	171:3a7713b1edbc	586	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge	171:3a7713b1edbc	587	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
AnnaBridge	171:3a7713b1edbc	588	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge	171:3a7713b1edbc	589	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge	171:3a7713b1edbc	590	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge	171:3a7713b1edbc	591	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge	171:3a7713b1edbc	592	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
AnnaBridge	171:3a7713b1edbc	593
AnnaBridge	171:3a7713b1edbc	594	/**
AnnaBridge	171:3a7713b1edbc	595	* @}
AnnaBridge	171:3a7713b1edbc	596	*/
AnnaBridge	171:3a7713b1edbc	597	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	171:3a7713b1edbc	598	* @{
AnnaBridge	171:3a7713b1edbc	599	*/
AnnaBridge	171:3a7713b1edbc	600	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	601	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	602	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	603	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	604	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	605	#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /!< MSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	606	#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /!< LSE Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	607	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	608	/**
AnnaBridge	171:3a7713b1edbc	609	* @}
AnnaBridge	171:3a7713b1edbc	610	*/
AnnaBridge	171:3a7713b1edbc	611
AnnaBridge	171:3a7713b1edbc	612	/** @defgroup RCC_Flag Flags
AnnaBridge	171:3a7713b1edbc	613	* Elements values convention: XXXYYYYYb
AnnaBridge	171:3a7713b1edbc	614	* - YYYYY : Flag position in the register
AnnaBridge	171:3a7713b1edbc	615	* - XXX : Register index
AnnaBridge	171:3a7713b1edbc	616	* - 001: CR register
AnnaBridge	171:3a7713b1edbc	617	* - 010: CSR register
AnnaBridge	171:3a7713b1edbc	618	* @{
AnnaBridge	171:3a7713b1edbc	619	*/
AnnaBridge	171:3a7713b1edbc	620	/* Flags in the CR register */
AnnaBridge	171:3a7713b1edbc	621	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
AnnaBridge	171:3a7713b1edbc	622	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI clock ready flag /
AnnaBridge	171:3a7713b1edbc	623	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
AnnaBridge	171:3a7713b1edbc	624	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
AnnaBridge	171:3a7713b1edbc	625
AnnaBridge	171:3a7713b1edbc	626	/* Flags in the CSR register */
AnnaBridge	171:3a7713b1edbc	627	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
AnnaBridge	171:3a7713b1edbc	628	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSECSSD))) /!< CSS on LSE failure Detection /
AnnaBridge	171:3a7713b1edbc	629	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Options bytes loading reset flag /
AnnaBridge	171:3a7713b1edbc	630	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
AnnaBridge	171:3a7713b1edbc	631	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
AnnaBridge	171:3a7713b1edbc	632	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
AnnaBridge	171:3a7713b1edbc	633	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	634	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	635	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
AnnaBridge	171:3a7713b1edbc	636	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSERDY))) /!< External Low Speed oscillator Ready /
AnnaBridge	171:3a7713b1edbc	637
AnnaBridge	171:3a7713b1edbc	638	/**
AnnaBridge	171:3a7713b1edbc	639	* @}
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	/**
AnnaBridge	171:3a7713b1edbc	643	* @}
AnnaBridge	171:3a7713b1edbc	644	*/
AnnaBridge	171:3a7713b1edbc	645
AnnaBridge	171:3a7713b1edbc	646	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	649	* @{
AnnaBridge	171:3a7713b1edbc	650	*/
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	653	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	654	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	655	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	656	* using it.
AnnaBridge	171:3a7713b1edbc	657	* @{
AnnaBridge	171:3a7713b1edbc	658	*/
AnnaBridge	171:3a7713b1edbc	659	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	660	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	661	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	662	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	663	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	664	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	665	} while(0U)
AnnaBridge	171:3a7713b1edbc	666	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	667	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	668	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	669	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	670	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	671	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	672	} while(0U)
AnnaBridge	171:3a7713b1edbc	673	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	674	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	675	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	676	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	677	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	678	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	679	} while(0U)
AnnaBridge	171:3a7713b1edbc	680	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	681	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	682	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	171:3a7713b1edbc	683	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	684	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	171:3a7713b1edbc	685	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	686	} while(0U)
AnnaBridge	171:3a7713b1edbc	687	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	688	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	689	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge	171:3a7713b1edbc	690	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	691	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge	171:3a7713b1edbc	692	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	693	} while(0U)
AnnaBridge	171:3a7713b1edbc	694	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	695	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	696	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	697	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	698	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	699	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	700	} while(0U)
AnnaBridge	171:3a7713b1edbc	701	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	702	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	703	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	171:3a7713b1edbc	704	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	705	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	171:3a7713b1edbc	706	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	707	} while(0U)
AnnaBridge	171:3a7713b1edbc	708	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	709	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	710	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	711	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	712	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	713	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	714	} while(0U)
AnnaBridge	171:3a7713b1edbc	715
AnnaBridge	171:3a7713b1edbc	716	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
AnnaBridge	171:3a7713b1edbc	717	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
AnnaBridge	171:3a7713b1edbc	718	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
AnnaBridge	171:3a7713b1edbc	719	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
AnnaBridge	171:3a7713b1edbc	720	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
AnnaBridge	171:3a7713b1edbc	723	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
AnnaBridge	171:3a7713b1edbc	724	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	/**
AnnaBridge	171:3a7713b1edbc	727	* @}
AnnaBridge	171:3a7713b1edbc	728	*/
AnnaBridge	171:3a7713b1edbc	729
AnnaBridge	171:3a7713b1edbc	730	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	731	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	171:3a7713b1edbc	732	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	733	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	734	* using it.
AnnaBridge	171:3a7713b1edbc	735	* @{
AnnaBridge	171:3a7713b1edbc	736	*/
AnnaBridge	171:3a7713b1edbc	737	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	738	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	739	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	171:3a7713b1edbc	740	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	741	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	171:3a7713b1edbc	742	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	743	} while(0U)
AnnaBridge	171:3a7713b1edbc	744	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	745	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	746	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	747	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	748	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	749	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	750	} while(0U)
AnnaBridge	171:3a7713b1edbc	751	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	752	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	753	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	754	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	755	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	756	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	757	} while(0U)
AnnaBridge	171:3a7713b1edbc	758	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	759	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	760	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	761	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	762	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	763	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	764	} while(0U)
AnnaBridge	171:3a7713b1edbc	765	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	766	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	767	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	768	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	769	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	770	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	771	} while(0U)
AnnaBridge	171:3a7713b1edbc	772	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	773	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	774	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	775	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	776	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	777	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	778	} while(0U)
AnnaBridge	171:3a7713b1edbc	779	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	780	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	781	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	782	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	783	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	784	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	785	} while(0U)
AnnaBridge	171:3a7713b1edbc	786	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	787	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	788	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	171:3a7713b1edbc	789	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	790	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	171:3a7713b1edbc	791	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	792	} while(0U)
AnnaBridge	171:3a7713b1edbc	793	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	794	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	795	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	796	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	797	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	798	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	799	} while(0U)
AnnaBridge	171:3a7713b1edbc	800	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	801	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	802	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	803	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	804	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	805	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	806	} while(0U)
AnnaBridge	171:3a7713b1edbc	807	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	808	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	809	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	810	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	811	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	812	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	813	} while(0U)
AnnaBridge	171:3a7713b1edbc	814	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	815	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	816	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	171:3a7713b1edbc	817	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	818	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	171:3a7713b1edbc	819	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	820	} while(0U)
AnnaBridge	171:3a7713b1edbc	821	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	822	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	823	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	824	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	825	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	826	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	827	} while(0U)
AnnaBridge	171:3a7713b1edbc	828	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	829	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	830	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	831	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	832	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	833	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	834	} while(0U)
AnnaBridge	171:3a7713b1edbc	835	#define __HAL_RCC_COMP_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	836	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	837	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
AnnaBridge	171:3a7713b1edbc	838	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	839	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
AnnaBridge	171:3a7713b1edbc	840	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	841	} while(0U)
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	171:3a7713b1edbc	845	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	171:3a7713b1edbc	846	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	171:3a7713b1edbc	847	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	171:3a7713b1edbc	848	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	171:3a7713b1edbc	849	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge	171:3a7713b1edbc	850	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	171:3a7713b1edbc	851	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge	171:3a7713b1edbc	852	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	171:3a7713b1edbc	853	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge	171:3a7713b1edbc	854	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	171:3a7713b1edbc	855	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
AnnaBridge	171:3a7713b1edbc	856	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge	171:3a7713b1edbc	857	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	171:3a7713b1edbc	858	#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	/**
AnnaBridge	171:3a7713b1edbc	861	* @}
AnnaBridge	171:3a7713b1edbc	862	*/
AnnaBridge	171:3a7713b1edbc	863
AnnaBridge	171:3a7713b1edbc	864	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	865	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	171:3a7713b1edbc	866	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	867	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	868	* using it.
AnnaBridge	171:3a7713b1edbc	869	* @{
AnnaBridge	171:3a7713b1edbc	870	*/
AnnaBridge	171:3a7713b1edbc	871	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	872	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	873	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	874	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	875	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	876	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	877	} while(0U)
AnnaBridge	171:3a7713b1edbc	878	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	879	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	880	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	881	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	882	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	883	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	884	} while(0U)
AnnaBridge	171:3a7713b1edbc	885	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	886	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	887	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	888	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	889	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	890	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	891	} while(0U)
AnnaBridge	171:3a7713b1edbc	892	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	893	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	894	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	895	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	896	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	897	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	898	} while(0U)
AnnaBridge	171:3a7713b1edbc	899	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	900	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	901	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	902	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	903	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	904	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	905	} while(0U)
AnnaBridge	171:3a7713b1edbc	906	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	907	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	908	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	909	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	910	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	911	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	912	} while(0U)
AnnaBridge	171:3a7713b1edbc	913	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	914	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	915	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	916	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	917	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	918	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	919	} while(0U)
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge	171:3a7713b1edbc	922	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge	171:3a7713b1edbc	923	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	171:3a7713b1edbc	924	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge	171:3a7713b1edbc	925	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge	171:3a7713b1edbc	926	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	171:3a7713b1edbc	927	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929	/**
AnnaBridge	171:3a7713b1edbc	930	* @}
AnnaBridge	171:3a7713b1edbc	931	*/
AnnaBridge	171:3a7713b1edbc	932
AnnaBridge	171:3a7713b1edbc	933	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
AnnaBridge	171:3a7713b1edbc	934	* @brief Force or release AHB peripheral reset.
AnnaBridge	171:3a7713b1edbc	935	* @{
AnnaBridge	171:3a7713b1edbc	936	*/
AnnaBridge	171:3a7713b1edbc	937	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	938	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	939	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	940	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	941	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
AnnaBridge	171:3a7713b1edbc	942	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
AnnaBridge	171:3a7713b1edbc	943
AnnaBridge	171:3a7713b1edbc	944	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
AnnaBridge	171:3a7713b1edbc	945	#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FLITFRST))
AnnaBridge	171:3a7713b1edbc	946	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
AnnaBridge	171:3a7713b1edbc	947
AnnaBridge	171:3a7713b1edbc	948	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	949	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	950	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	951	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	952	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
AnnaBridge	171:3a7713b1edbc	953	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
AnnaBridge	171:3a7713b1edbc	956	#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
AnnaBridge	171:3a7713b1edbc	957	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
AnnaBridge	171:3a7713b1edbc	958
AnnaBridge	171:3a7713b1edbc	959	/**
AnnaBridge	171:3a7713b1edbc	960	* @}
AnnaBridge	171:3a7713b1edbc	961	*/
AnnaBridge	171:3a7713b1edbc	962
AnnaBridge	171:3a7713b1edbc	963	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	171:3a7713b1edbc	964	* @brief Force or release APB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	965	* @{
AnnaBridge	171:3a7713b1edbc	966	*/
AnnaBridge	171:3a7713b1edbc	967	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	968	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	171:3a7713b1edbc	969	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	970	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	971	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	972	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	973	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	974	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	975	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
AnnaBridge	171:3a7713b1edbc	976	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	977	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	978	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	979	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
AnnaBridge	171:3a7713b1edbc	980	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	981	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	982	#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_COMPRST))
AnnaBridge	171:3a7713b1edbc	983
AnnaBridge	171:3a7713b1edbc	984	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	985	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	171:3a7713b1edbc	986	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	987	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	988	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	989	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	990	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	991	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	992	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge	171:3a7713b1edbc	993	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	994	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	995	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	996	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
AnnaBridge	171:3a7713b1edbc	997	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	998	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	999	#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
AnnaBridge	171:3a7713b1edbc	1000
AnnaBridge	171:3a7713b1edbc	1001	/**
AnnaBridge	171:3a7713b1edbc	1002	* @}
AnnaBridge	171:3a7713b1edbc	1003	*/
AnnaBridge	171:3a7713b1edbc	1004
AnnaBridge	171:3a7713b1edbc	1005	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1006	* @brief Force or release APB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1007	* @{
AnnaBridge	171:3a7713b1edbc	1008	*/
AnnaBridge	171:3a7713b1edbc	1009	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1010	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	1011	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1012	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1013	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1014	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
AnnaBridge	171:3a7713b1edbc	1015	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	1016	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	1017
AnnaBridge	171:3a7713b1edbc	1018	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	1019	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	1020	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1021	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1022	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1023	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
AnnaBridge	171:3a7713b1edbc	1024	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	1025	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	1026
AnnaBridge	171:3a7713b1edbc	1027	/**
AnnaBridge	171:3a7713b1edbc	1028	* @}
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
AnnaBridge	171:3a7713b1edbc	1032	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1033	* power consumption.
AnnaBridge	171:3a7713b1edbc	1034	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1035	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1036	* @{
AnnaBridge	171:3a7713b1edbc	1037	*/
AnnaBridge	171:3a7713b1edbc	1038	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOALPEN))
AnnaBridge	171:3a7713b1edbc	1039	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOBLPEN))
AnnaBridge	171:3a7713b1edbc	1040	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOCLPEN))
AnnaBridge	171:3a7713b1edbc	1041	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIODLPEN))
AnnaBridge	171:3a7713b1edbc	1042	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOHLPEN))
AnnaBridge	171:3a7713b1edbc	1043
AnnaBridge	171:3a7713b1edbc	1044	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_CRCLPEN))
AnnaBridge	171:3a7713b1edbc	1045	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_FLITFLPEN))
AnnaBridge	171:3a7713b1edbc	1046	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_DMA1LPEN))
AnnaBridge	171:3a7713b1edbc	1047
AnnaBridge	171:3a7713b1edbc	1048	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
AnnaBridge	171:3a7713b1edbc	1049	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
AnnaBridge	171:3a7713b1edbc	1050	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
AnnaBridge	171:3a7713b1edbc	1051	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
AnnaBridge	171:3a7713b1edbc	1052	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
AnnaBridge	171:3a7713b1edbc	1053
AnnaBridge	171:3a7713b1edbc	1054	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
AnnaBridge	171:3a7713b1edbc	1055	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
AnnaBridge	171:3a7713b1edbc	1056	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
AnnaBridge	171:3a7713b1edbc	1057
AnnaBridge	171:3a7713b1edbc	1058	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1059	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1060	* power consumption.
AnnaBridge	171:3a7713b1edbc	1061	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1062	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1063	*/
AnnaBridge	171:3a7713b1edbc	1064	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	171:3a7713b1edbc	1065	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	171:3a7713b1edbc	1066	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	171:3a7713b1edbc	1067	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	171:3a7713b1edbc	1068	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	171:3a7713b1edbc	1069	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
AnnaBridge	171:3a7713b1edbc	1070	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	171:3a7713b1edbc	1071	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
AnnaBridge	171:3a7713b1edbc	1072	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	171:3a7713b1edbc	1073	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	171:3a7713b1edbc	1074	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	171:3a7713b1edbc	1075	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USBLPEN))
AnnaBridge	171:3a7713b1edbc	1076	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
AnnaBridge	171:3a7713b1edbc	1077	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	171:3a7713b1edbc	1078	#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_COMPLPEN))
AnnaBridge	171:3a7713b1edbc	1079
AnnaBridge	171:3a7713b1edbc	1080	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	171:3a7713b1edbc	1081	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	171:3a7713b1edbc	1082	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	171:3a7713b1edbc	1083	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	171:3a7713b1edbc	1084	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	171:3a7713b1edbc	1085	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
AnnaBridge	171:3a7713b1edbc	1086	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	171:3a7713b1edbc	1087	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
AnnaBridge	171:3a7713b1edbc	1088	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	171:3a7713b1edbc	1089	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	171:3a7713b1edbc	1090	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	171:3a7713b1edbc	1091	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
AnnaBridge	171:3a7713b1edbc	1092	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
AnnaBridge	171:3a7713b1edbc	1093	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	171:3a7713b1edbc	1094	#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
AnnaBridge	171:3a7713b1edbc	1095
AnnaBridge	171:3a7713b1edbc	1096	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1097	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1098	* power consumption.
AnnaBridge	171:3a7713b1edbc	1099	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1100	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1101	*/
AnnaBridge	171:3a7713b1edbc	1102	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge	171:3a7713b1edbc	1103	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	171:3a7713b1edbc	1104	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	171:3a7713b1edbc	1105	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	171:3a7713b1edbc	1106	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	171:3a7713b1edbc	1107	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	171:3a7713b1edbc	1108	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
AnnaBridge	171:3a7713b1edbc	1109
AnnaBridge	171:3a7713b1edbc	1110	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge	171:3a7713b1edbc	1111	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	171:3a7713b1edbc	1112	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	171:3a7713b1edbc	1113	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	171:3a7713b1edbc	1114	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	171:3a7713b1edbc	1115	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	171:3a7713b1edbc	1116	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/**
AnnaBridge	171:3a7713b1edbc	1119	* @}
AnnaBridge	171:3a7713b1edbc	1120	*/
AnnaBridge	171:3a7713b1edbc	1121
AnnaBridge	171:3a7713b1edbc	1122	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1123	* @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge	171:3a7713b1edbc	1124	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1125	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1126	* using it.
AnnaBridge	171:3a7713b1edbc	1127	* @{
AnnaBridge	171:3a7713b1edbc	1128	*/
AnnaBridge	171:3a7713b1edbc	1129
AnnaBridge	171:3a7713b1edbc	1130	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1131	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1132	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1133	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1134	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1135	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1136	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1137	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1138	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1139	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1140	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1141	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1142	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1143	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1144	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1145	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1146
AnnaBridge	171:3a7713b1edbc	1147	/**
AnnaBridge	171:3a7713b1edbc	1148	* @}
AnnaBridge	171:3a7713b1edbc	1149	*/
AnnaBridge	171:3a7713b1edbc	1150
AnnaBridge	171:3a7713b1edbc	1151	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1152	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	1153	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1154	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1155	* using it.
AnnaBridge	171:3a7713b1edbc	1156	* @{
AnnaBridge	171:3a7713b1edbc	1157	*/
AnnaBridge	171:3a7713b1edbc	1158
AnnaBridge	171:3a7713b1edbc	1159	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1160	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1161	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1162	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1163	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1164	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1165	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1166	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1167	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1168	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1169	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1170	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1171	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1172	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1173	#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1174	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1175	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1176	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1177	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1178	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1179	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1180	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1181	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1182	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1183	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1184	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1185	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1186	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1187	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1188	#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1189
AnnaBridge	171:3a7713b1edbc	1190	/**
AnnaBridge	171:3a7713b1edbc	1191	* @}
AnnaBridge	171:3a7713b1edbc	1192	*/
AnnaBridge	171:3a7713b1edbc	1193
AnnaBridge	171:3a7713b1edbc	1194	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1195	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	1196	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1197	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1198	* using it.
AnnaBridge	171:3a7713b1edbc	1199	* @{
AnnaBridge	171:3a7713b1edbc	1200	*/
AnnaBridge	171:3a7713b1edbc	1201
AnnaBridge	171:3a7713b1edbc	1202	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1203	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1204	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1205	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1206	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1207	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1208	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1209	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1210	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1211	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1212	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1213	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1214	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1215	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/**
AnnaBridge	171:3a7713b1edbc	1218	* @}
AnnaBridge	171:3a7713b1edbc	1219	*/
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1222	* @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1223	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1224	* power consumption.
AnnaBridge	171:3a7713b1edbc	1225	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1226	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1227	* @{
AnnaBridge	171:3a7713b1edbc	1228	*/
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1231	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1232	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1233	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1234	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1235	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1236	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1237	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1238	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1239	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1240	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1241	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1242	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1243	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1244	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1245	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1246
AnnaBridge	171:3a7713b1edbc	1247	/**
AnnaBridge	171:3a7713b1edbc	1248	* @}
AnnaBridge	171:3a7713b1edbc	1249	*/
AnnaBridge	171:3a7713b1edbc	1250
AnnaBridge	171:3a7713b1edbc	1251	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1252	* @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1253	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1254	* power consumption.
AnnaBridge	171:3a7713b1edbc	1255	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1256	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1257	* @{
AnnaBridge	171:3a7713b1edbc	1258	*/
AnnaBridge	171:3a7713b1edbc	1259
AnnaBridge	171:3a7713b1edbc	1260	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1261	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1262	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1263	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1264	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1265	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1266	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1267	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1268	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1269	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1270	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1271	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1272	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1273	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1274	#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1275	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1276	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1277	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1278	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1279	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1280	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1281	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1282	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1283	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1284	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1285	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1286	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1287	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1288	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1289	#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1290
AnnaBridge	171:3a7713b1edbc	1291	/**
AnnaBridge	171:3a7713b1edbc	1292	* @}
AnnaBridge	171:3a7713b1edbc	1293	*/
AnnaBridge	171:3a7713b1edbc	1294
AnnaBridge	171:3a7713b1edbc	1295	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1296	* @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1297	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1298	* power consumption.
AnnaBridge	171:3a7713b1edbc	1299	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1300	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1301	* @{
AnnaBridge	171:3a7713b1edbc	1302	*/
AnnaBridge	171:3a7713b1edbc	1303
AnnaBridge	171:3a7713b1edbc	1304	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1305	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1306	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1307	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1308	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1309	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1310	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1311	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1312	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1313	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1314	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1315	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1316	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1317	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1318
AnnaBridge	171:3a7713b1edbc	1319	/**
AnnaBridge	171:3a7713b1edbc	1320	* @}
AnnaBridge	171:3a7713b1edbc	1321	*/
AnnaBridge	171:3a7713b1edbc	1322
AnnaBridge	171:3a7713b1edbc	1323	/** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge	171:3a7713b1edbc	1324	* @{
AnnaBridge	171:3a7713b1edbc	1325	*/
AnnaBridge	171:3a7713b1edbc	1326
AnnaBridge	171:3a7713b1edbc	1327	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	171:3a7713b1edbc	1328	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1329	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	171:3a7713b1edbc	1330	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	171:3a7713b1edbc	1331	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	171:3a7713b1edbc	1332	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	171:3a7713b1edbc	1333	* system clock source.
AnnaBridge	171:3a7713b1edbc	1334	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	171:3a7713b1edbc	1335	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1336	*/
AnnaBridge	171:3a7713b1edbc	1337	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1338	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1339
AnnaBridge	171:3a7713b1edbc	1340	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	171:3a7713b1edbc	1341	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	171:3a7713b1edbc	1342	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	171:3a7713b1edbc	1343	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	171:3a7713b1edbc	1344	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	1345	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	171:3a7713b1edbc	1346	*/
AnnaBridge	171:3a7713b1edbc	1347	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge	171:3a7713b1edbc	1348	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
AnnaBridge	171:3a7713b1edbc	1349
AnnaBridge	171:3a7713b1edbc	1350	/**
AnnaBridge	171:3a7713b1edbc	1351	* @}
AnnaBridge	171:3a7713b1edbc	1352	*/
AnnaBridge	171:3a7713b1edbc	1353
AnnaBridge	171:3a7713b1edbc	1354	/** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge	171:3a7713b1edbc	1355	* @{
AnnaBridge	171:3a7713b1edbc	1356	*/
AnnaBridge	171:3a7713b1edbc	1357
AnnaBridge	171:3a7713b1edbc	1358	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge	171:3a7713b1edbc	1359	* @note After enabling the LSI, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1360	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	171:3a7713b1edbc	1361	* be used to clock the IWDG and/or the RTC.
AnnaBridge	171:3a7713b1edbc	1362	*/
AnnaBridge	171:3a7713b1edbc	1363	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge	171:3a7713b1edbc	1366	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	171:3a7713b1edbc	1367	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	171:3a7713b1edbc	1368	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1369	*/
AnnaBridge	171:3a7713b1edbc	1370	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1371
AnnaBridge	171:3a7713b1edbc	1372	/**
AnnaBridge	171:3a7713b1edbc	1373	* @}
AnnaBridge	171:3a7713b1edbc	1374	*/
AnnaBridge	171:3a7713b1edbc	1375
AnnaBridge	171:3a7713b1edbc	1376	/** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge	171:3a7713b1edbc	1377	* @{
AnnaBridge	171:3a7713b1edbc	1378	*/
AnnaBridge	171:3a7713b1edbc	1379
AnnaBridge	171:3a7713b1edbc	1380	/**
AnnaBridge	171:3a7713b1edbc	1381	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	171:3a7713b1edbc	1382	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	171:3a7713b1edbc	1383	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	171:3a7713b1edbc	1384	* first and then HSE On or HSE Bypass.
AnnaBridge	171:3a7713b1edbc	1385	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	171:3a7713b1edbc	1386	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	171:3a7713b1edbc	1387	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	171:3a7713b1edbc	1388	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	171:3a7713b1edbc	1389	* PLL as system clock. In this case, you have to select another source
AnnaBridge	171:3a7713b1edbc	1390	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	171:3a7713b1edbc	1391	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1392	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	171:3a7713b1edbc	1393	* was previously enabled you have to enable it again after calling this
AnnaBridge	171:3a7713b1edbc	1394	* function.
AnnaBridge	171:3a7713b1edbc	1395	* @param __STATE__ specifies the new state of the HSE.
AnnaBridge	171:3a7713b1edbc	1396	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1397	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1398	* 6 HSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1399	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge	171:3a7713b1edbc	1400	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge	171:3a7713b1edbc	1401	*/
AnnaBridge	171:3a7713b1edbc	1402	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	171:3a7713b1edbc	1403	do{ \
AnnaBridge	171:3a7713b1edbc	1404	if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge	171:3a7713b1edbc	1405	{ \
AnnaBridge	171:3a7713b1edbc	1406	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1407	} \
AnnaBridge	171:3a7713b1edbc	1408	else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge	171:3a7713b1edbc	1409	{ \
AnnaBridge	171:3a7713b1edbc	1410	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1411	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1412	} \
AnnaBridge	171:3a7713b1edbc	1413	else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	171:3a7713b1edbc	1414	{ \
AnnaBridge	171:3a7713b1edbc	1415	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1416	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1417	} \
AnnaBridge	171:3a7713b1edbc	1418	else \
AnnaBridge	171:3a7713b1edbc	1419	{ \
AnnaBridge	171:3a7713b1edbc	1420	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1421	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1422	} \
AnnaBridge	171:3a7713b1edbc	1423	}while(0U)
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	/**
AnnaBridge	171:3a7713b1edbc	1426	* @}
AnnaBridge	171:3a7713b1edbc	1427	*/
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	/** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge	171:3a7713b1edbc	1430	* @{
AnnaBridge	171:3a7713b1edbc	1431	*/
AnnaBridge	171:3a7713b1edbc	1432
AnnaBridge	171:3a7713b1edbc	1433	/**
AnnaBridge	171:3a7713b1edbc	1434	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	171:3a7713b1edbc	1435	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge	171:3a7713b1edbc	1436	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	171:3a7713b1edbc	1437	* this domain after reset, you have to enable write access using
AnnaBridge	171:3a7713b1edbc	1438	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	171:3a7713b1edbc	1439	* (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1440	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	171:3a7713b1edbc	1441	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	171:3a7713b1edbc	1442	* is stable and can be used to clock the RTC.
AnnaBridge	171:3a7713b1edbc	1443	* @param __STATE__ specifies the new state of the LSE.
AnnaBridge	171:3a7713b1edbc	1444	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1445	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1446	* 6 LSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1447	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge	171:3a7713b1edbc	1448	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	171:3a7713b1edbc	1449	*/
AnnaBridge	171:3a7713b1edbc	1450	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	171:3a7713b1edbc	1451	do{ \
AnnaBridge	171:3a7713b1edbc	1452	if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge	171:3a7713b1edbc	1453	{ \
AnnaBridge	171:3a7713b1edbc	1454	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1455	} \
AnnaBridge	171:3a7713b1edbc	1456	else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge	171:3a7713b1edbc	1457	{ \
AnnaBridge	171:3a7713b1edbc	1458	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1459	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1460	} \
AnnaBridge	171:3a7713b1edbc	1461	else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	171:3a7713b1edbc	1462	{ \
AnnaBridge	171:3a7713b1edbc	1463	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1464	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1465	} \
AnnaBridge	171:3a7713b1edbc	1466	else \
AnnaBridge	171:3a7713b1edbc	1467	{ \
AnnaBridge	171:3a7713b1edbc	1468	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1469	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1470	} \
AnnaBridge	171:3a7713b1edbc	1471	}while(0U)
AnnaBridge	171:3a7713b1edbc	1472
AnnaBridge	171:3a7713b1edbc	1473	/**
AnnaBridge	171:3a7713b1edbc	1474	* @}
AnnaBridge	171:3a7713b1edbc	1475	*/
AnnaBridge	171:3a7713b1edbc	1476
AnnaBridge	171:3a7713b1edbc	1477	/** @defgroup RCC_MSI_Configuration MSI Configuration
AnnaBridge	171:3a7713b1edbc	1478	* @{
AnnaBridge	171:3a7713b1edbc	1479	*/
AnnaBridge	171:3a7713b1edbc	1480
AnnaBridge	171:3a7713b1edbc	1481	/** @brief Macro to enable Internal Multi Speed oscillator (MSI).
AnnaBridge	171:3a7713b1edbc	1482	* @note After enabling the MSI, the application software should wait on MSIRDY
AnnaBridge	171:3a7713b1edbc	1483	* flag to be set indicating that MSI clock is stable and can be used as
AnnaBridge	171:3a7713b1edbc	1484	* system clock source.
AnnaBridge	171:3a7713b1edbc	1485	*/
AnnaBridge	171:3a7713b1edbc	1486	#define __HAL_RCC_MSI_ENABLE() ((__IO uint32_t ) RCC_CR_MSION_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1487
AnnaBridge	171:3a7713b1edbc	1488	/** @brief Macro to disable the Internal Multi Speed oscillator (MSI).
AnnaBridge	171:3a7713b1edbc	1489	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1490	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	171:3a7713b1edbc	1491	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	171:3a7713b1edbc	1492	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	171:3a7713b1edbc	1493	* Security System CSS is enabled).
AnnaBridge	171:3a7713b1edbc	1494	* @note MSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	171:3a7713b1edbc	1495	* you have to select another source of the system clock then stop the MSI.
AnnaBridge	171:3a7713b1edbc	1496	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge	171:3a7713b1edbc	1497	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1498	*/
AnnaBridge	171:3a7713b1edbc	1499	#define __HAL_RCC_MSI_DISABLE() ((__IO uint32_t ) RCC_CR_MSION_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1500
AnnaBridge	171:3a7713b1edbc	1501	/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge	171:3a7713b1edbc	1502	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	171:3a7713b1edbc	1503	* and temperature that influence the frequency of the internal MSI RC.
AnnaBridge	171:3a7713b1edbc	1504	* @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	171:3a7713b1edbc	1505	* (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	1506	* This parameter must be a number between 0 and 0xFF.
AnnaBridge	171:3a7713b1edbc	1507	*/
AnnaBridge	171:3a7713b1edbc	1508	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
AnnaBridge	171:3a7713b1edbc	1509	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
AnnaBridge	171:3a7713b1edbc	1510
AnnaBridge	171:3a7713b1edbc	1511	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
AnnaBridge	171:3a7713b1edbc	1512	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
AnnaBridge	171:3a7713b1edbc	1513	* around 2.097 MHz. The MSI clock does not change after wake-up from
AnnaBridge	171:3a7713b1edbc	1514	* STOP mode.
AnnaBridge	171:3a7713b1edbc	1515	* @note The MSI clock range can be modified on the fly.
AnnaBridge	171:3a7713b1edbc	1516	* @param _MSIRANGEVALUE_ specifies the MSI Clock range.
AnnaBridge	171:3a7713b1edbc	1517	* This parameter must be one of the following values:
AnnaBridge	171:3a7713b1edbc	1518	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
AnnaBridge	171:3a7713b1edbc	1519	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
AnnaBridge	171:3a7713b1edbc	1520	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
AnnaBridge	171:3a7713b1edbc	1521	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
AnnaBridge	171:3a7713b1edbc	1522	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
AnnaBridge	171:3a7713b1edbc	1523	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	171:3a7713b1edbc	1524	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
AnnaBridge	171:3a7713b1edbc	1525	*/
AnnaBridge	171:3a7713b1edbc	1526	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
AnnaBridge	171:3a7713b1edbc	1527	RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
AnnaBridge	171:3a7713b1edbc	1528
AnnaBridge	171:3a7713b1edbc	1529	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	171:3a7713b1edbc	1530	* @retval MSI clock range.
AnnaBridge	171:3a7713b1edbc	1531	* This parameter must be one of the following values:
AnnaBridge	171:3a7713b1edbc	1532	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
AnnaBridge	171:3a7713b1edbc	1533	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
AnnaBridge	171:3a7713b1edbc	1534	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
AnnaBridge	171:3a7713b1edbc	1535	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
AnnaBridge	171:3a7713b1edbc	1536	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
AnnaBridge	171:3a7713b1edbc	1537	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	171:3a7713b1edbc	1538	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
AnnaBridge	171:3a7713b1edbc	1539	*/
AnnaBridge	171:3a7713b1edbc	1540	#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
AnnaBridge	171:3a7713b1edbc	1541
AnnaBridge	171:3a7713b1edbc	1542	/**
AnnaBridge	171:3a7713b1edbc	1543	* @}
AnnaBridge	171:3a7713b1edbc	1544	*/
AnnaBridge	171:3a7713b1edbc	1545
AnnaBridge	171:3a7713b1edbc	1546	/** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge	171:3a7713b1edbc	1547	* @{
AnnaBridge	171:3a7713b1edbc	1548	*/
AnnaBridge	171:3a7713b1edbc	1549
AnnaBridge	171:3a7713b1edbc	1550	/** @brief Macro to enable the main PLL.
AnnaBridge	171:3a7713b1edbc	1551	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1552	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	171:3a7713b1edbc	1553	* be used as system clock source.
AnnaBridge	171:3a7713b1edbc	1554	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1555	*/
AnnaBridge	171:3a7713b1edbc	1556	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1557
AnnaBridge	171:3a7713b1edbc	1558	/** @brief Macro to disable the main PLL.
AnnaBridge	171:3a7713b1edbc	1559	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	171:3a7713b1edbc	1560	*/
AnnaBridge	171:3a7713b1edbc	1561	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1562
AnnaBridge	171:3a7713b1edbc	1563	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	171:3a7713b1edbc	1564	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	171:3a7713b1edbc	1565	*
AnnaBridge	171:3a7713b1edbc	1566	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	1567	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1568	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1569	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1570	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	171:3a7713b1edbc	1571	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1572	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
AnnaBridge	171:3a7713b1edbc	1573	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
AnnaBridge	171:3a7713b1edbc	1574	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
AnnaBridge	171:3a7713b1edbc	1575	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
AnnaBridge	171:3a7713b1edbc	1576	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
AnnaBridge	171:3a7713b1edbc	1577	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
AnnaBridge	171:3a7713b1edbc	1578	* @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24
AnnaBridge	171:3a7713b1edbc	1579	* @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32
AnnaBridge	171:3a7713b1edbc	1580	* @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48
AnnaBridge	171:3a7713b1edbc	1581	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
AnnaBridge	171:3a7713b1edbc	1582	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
AnnaBridge	171:3a7713b1edbc	1583	* in Range 3.
AnnaBridge	171:3a7713b1edbc	1584	*
AnnaBridge	171:3a7713b1edbc	1585	* @param __PLLDIV__ specifies the division factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	1586	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1587	* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
AnnaBridge	171:3a7713b1edbc	1588	* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
AnnaBridge	171:3a7713b1edbc	1589	* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
AnnaBridge	171:3a7713b1edbc	1590	*
AnnaBridge	171:3a7713b1edbc	1591	*/
AnnaBridge	171:3a7713b1edbc	1592	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
AnnaBridge	171:3a7713b1edbc	1593	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
AnnaBridge	171:3a7713b1edbc	1594
AnnaBridge	171:3a7713b1edbc	1595	/** @brief Get oscillator clock selected as PLL input clock
AnnaBridge	171:3a7713b1edbc	1596	* @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1597	* of the following:
AnnaBridge	171:3a7713b1edbc	1598	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
AnnaBridge	171:3a7713b1edbc	1599	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge	171:3a7713b1edbc	1600	*/
AnnaBridge	171:3a7713b1edbc	1601	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge	171:3a7713b1edbc	1602
AnnaBridge	171:3a7713b1edbc	1603	/**
AnnaBridge	171:3a7713b1edbc	1604	* @}
AnnaBridge	171:3a7713b1edbc	1605	*/
AnnaBridge	171:3a7713b1edbc	1606
AnnaBridge	171:3a7713b1edbc	1607	/** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge	171:3a7713b1edbc	1608	* @{
AnnaBridge	171:3a7713b1edbc	1609	*/
AnnaBridge	171:3a7713b1edbc	1610
AnnaBridge	171:3a7713b1edbc	1611	/**
AnnaBridge	171:3a7713b1edbc	1612	* @brief Macro to configure the system clock source.
AnnaBridge	171:3a7713b1edbc	1613	* @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge	171:3a7713b1edbc	1614	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1615	* @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1616	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1617	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1618	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1619	*/
AnnaBridge	171:3a7713b1edbc	1620	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1621	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	171:3a7713b1edbc	1624	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1625	* of the following:
AnnaBridge	171:3a7713b1edbc	1626	* @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
AnnaBridge	171:3a7713b1edbc	1627	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge	171:3a7713b1edbc	1628	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge	171:3a7713b1edbc	1629	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge	171:3a7713b1edbc	1630	*/
AnnaBridge	171:3a7713b1edbc	1631	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge	171:3a7713b1edbc	1632
AnnaBridge	171:3a7713b1edbc	1633	/**
AnnaBridge	171:3a7713b1edbc	1634	* @}
AnnaBridge	171:3a7713b1edbc	1635	*/
AnnaBridge	171:3a7713b1edbc	1636
AnnaBridge	171:3a7713b1edbc	1637	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge	171:3a7713b1edbc	1638	* @{
AnnaBridge	171:3a7713b1edbc	1639	*/
AnnaBridge	171:3a7713b1edbc	1640
AnnaBridge	171:3a7713b1edbc	1641	/** @brief Macro to configure the MCO clock.
AnnaBridge	171:3a7713b1edbc	1642	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	171:3a7713b1edbc	1643	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1644	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1645	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1646	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1647	* @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1648	* @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1649	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1650	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1651	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1652	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	171:3a7713b1edbc	1653	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1654	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	171:3a7713b1edbc	1655	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	171:3a7713b1edbc	1656	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	171:3a7713b1edbc	1657	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	171:3a7713b1edbc	1658	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	171:3a7713b1edbc	1659	*/
AnnaBridge	171:3a7713b1edbc	1660	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	171:3a7713b1edbc	1661	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	171:3a7713b1edbc	1662
AnnaBridge	171:3a7713b1edbc	1663	/**
AnnaBridge	171:3a7713b1edbc	1664	* @}
AnnaBridge	171:3a7713b1edbc	1665	*/
AnnaBridge	171:3a7713b1edbc	1666
AnnaBridge	171:3a7713b1edbc	1667	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	171:3a7713b1edbc	1668	* @{
AnnaBridge	171:3a7713b1edbc	1669	*/
AnnaBridge	171:3a7713b1edbc	1670
AnnaBridge	171:3a7713b1edbc	1671	/** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge	171:3a7713b1edbc	1672	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	171:3a7713b1edbc	1673	* access is denied to this domain after reset, you have to enable write
AnnaBridge	171:3a7713b1edbc	1674	* access using the Power Backup Access macro before to configure
AnnaBridge	171:3a7713b1edbc	1675	* the RTC clock source (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1676	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	171:3a7713b1edbc	1677	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	171:3a7713b1edbc	1678	* a Power On Reset (POR).
AnnaBridge	171:3a7713b1edbc	1679	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
AnnaBridge	171:3a7713b1edbc	1680	*
AnnaBridge	171:3a7713b1edbc	1681	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge	171:3a7713b1edbc	1682	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1683	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1684	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1685	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1686	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1687	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1688	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1689	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1690	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	171:3a7713b1edbc	1691	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	171:3a7713b1edbc	1692	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	171:3a7713b1edbc	1693	* cannot be used in STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1694	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	171:3a7713b1edbc	1695	* RTC clock source).
AnnaBridge	171:3a7713b1edbc	1696	*/
AnnaBridge	171:3a7713b1edbc	1697	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
AnnaBridge	171:3a7713b1edbc	1698	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
AnnaBridge	171:3a7713b1edbc	1699	{ \
AnnaBridge	171:3a7713b1edbc	1700	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
AnnaBridge	171:3a7713b1edbc	1701	} \
AnnaBridge	171:3a7713b1edbc	1702	} while (0U)
AnnaBridge	171:3a7713b1edbc	1703
AnnaBridge	171:3a7713b1edbc	1704	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
AnnaBridge	171:3a7713b1edbc	1705	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
AnnaBridge	171:3a7713b1edbc	1706	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
AnnaBridge	171:3a7713b1edbc	1707	} while (0U)
AnnaBridge	171:3a7713b1edbc	1708
AnnaBridge	171:3a7713b1edbc	1709	/** @brief Macro to get the RTC clock source.
AnnaBridge	171:3a7713b1edbc	1710	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1711	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1712	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1713	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1714	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge	171:3a7713b1edbc	1715	*/
AnnaBridge	171:3a7713b1edbc	1716	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
AnnaBridge	171:3a7713b1edbc	1717
AnnaBridge	171:3a7713b1edbc	1718	/**
AnnaBridge	171:3a7713b1edbc	1719	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
AnnaBridge	171:3a7713b1edbc	1720	*
AnnaBridge	171:3a7713b1edbc	1721	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1722	* @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1723	* @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1724	* @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1725	* @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1726	*
AnnaBridge	171:3a7713b1edbc	1727	*/
AnnaBridge	171:3a7713b1edbc	1728	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
AnnaBridge	171:3a7713b1edbc	1729
AnnaBridge	171:3a7713b1edbc	1730	/** @brief Macro to enable the the RTC clock.
AnnaBridge	171:3a7713b1edbc	1731	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	171:3a7713b1edbc	1732	*/
AnnaBridge	171:3a7713b1edbc	1733	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_CSR_RTCEN_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1734
AnnaBridge	171:3a7713b1edbc	1735	/** @brief Macro to disable the the RTC clock.
AnnaBridge	171:3a7713b1edbc	1736	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	171:3a7713b1edbc	1737	*/
AnnaBridge	171:3a7713b1edbc	1738	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_CSR_RTCEN_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1739
AnnaBridge	171:3a7713b1edbc	1740	/** @brief Macro to force the Backup domain reset.
AnnaBridge	171:3a7713b1edbc	1741	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	171:3a7713b1edbc	1742	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	171:3a7713b1edbc	1743	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	171:3a7713b1edbc	1744	*/
AnnaBridge	171:3a7713b1edbc	1745	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_CSR_RTCRST_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1746
AnnaBridge	171:3a7713b1edbc	1747	/** @brief Macros to release the Backup domain reset.
AnnaBridge	171:3a7713b1edbc	1748	*/
AnnaBridge	171:3a7713b1edbc	1749	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_CSR_RTCRST_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1750
AnnaBridge	171:3a7713b1edbc	1751	/**
AnnaBridge	171:3a7713b1edbc	1752	* @}
AnnaBridge	171:3a7713b1edbc	1753	*/
AnnaBridge	171:3a7713b1edbc	1754
AnnaBridge	171:3a7713b1edbc	1755	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	171:3a7713b1edbc	1756	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	171:3a7713b1edbc	1757	* @{
AnnaBridge	171:3a7713b1edbc	1758	*/
AnnaBridge	171:3a7713b1edbc	1759
AnnaBridge	171:3a7713b1edbc	1760	/** @brief Enable RCC interrupt.
AnnaBridge	171:3a7713b1edbc	1761	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	1762	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1763	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1764	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1765	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1766	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1767	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1768	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1769	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
AnnaBridge	171:3a7713b1edbc	1770	*/
AnnaBridge	171:3a7713b1edbc	1771	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1772
AnnaBridge	171:3a7713b1edbc	1773	/** @brief Disable RCC interrupt.
AnnaBridge	171:3a7713b1edbc	1774	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	1775	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1776	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1777	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1778	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1779	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1780	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1781	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1782	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
AnnaBridge	171:3a7713b1edbc	1783	*/
AnnaBridge	171:3a7713b1edbc	1784	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	1785
AnnaBridge	171:3a7713b1edbc	1786	/** @brief Clear the RCC's interrupt pending bits.
AnnaBridge	171:3a7713b1edbc	1787	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	1788	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1789	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1790	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1791	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1792	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1793	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1794	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1795	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
AnnaBridge	171:3a7713b1edbc	1796	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1797	*/
AnnaBridge	171:3a7713b1edbc	1798	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1799
AnnaBridge	171:3a7713b1edbc	1800	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	1801	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge	171:3a7713b1edbc	1802	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1803	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1804	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1805	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1806	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1807	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1808	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1809	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
AnnaBridge	171:3a7713b1edbc	1810	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1811	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1812	*/
AnnaBridge	171:3a7713b1edbc	1813	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1814
AnnaBridge	171:3a7713b1edbc	1815	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	171:3a7713b1edbc	1816	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge	171:3a7713b1edbc	1817	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge	171:3a7713b1edbc	1818	*/
AnnaBridge	171:3a7713b1edbc	1819	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	171:3a7713b1edbc	1820
AnnaBridge	171:3a7713b1edbc	1821	/** @brief Check RCC flag is set or not.
AnnaBridge	171:3a7713b1edbc	1822	* @param __FLAG__ specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	1823	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1824	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1825	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1826	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1827	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
AnnaBridge	171:3a7713b1edbc	1828	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1829	* @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
AnnaBridge	171:3a7713b1edbc	1830	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1831	* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
AnnaBridge	171:3a7713b1edbc	1832	* @arg @ref RCC_FLAG_PINRST Pin reset.
AnnaBridge	171:3a7713b1edbc	1833	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
AnnaBridge	171:3a7713b1edbc	1834	* @arg @ref RCC_FLAG_SFTRST Software reset.
AnnaBridge	171:3a7713b1edbc	1835	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1836	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1837	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
AnnaBridge	171:3a7713b1edbc	1838	* @note (*) This bit is available in high and medium+ density devices only.
AnnaBridge	171:3a7713b1edbc	1839	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1840	*/
AnnaBridge	171:3a7713b1edbc	1841	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
AnnaBridge	171:3a7713b1edbc	1842
AnnaBridge	171:3a7713b1edbc	1843	/**
AnnaBridge	171:3a7713b1edbc	1844	* @}
AnnaBridge	171:3a7713b1edbc	1845	*/
AnnaBridge	171:3a7713b1edbc	1846
AnnaBridge	171:3a7713b1edbc	1847	/**
AnnaBridge	171:3a7713b1edbc	1848	* @}
AnnaBridge	171:3a7713b1edbc	1849	*/
AnnaBridge	171:3a7713b1edbc	1850
AnnaBridge	171:3a7713b1edbc	1851	/* Include RCC HAL Extension module */
AnnaBridge	171:3a7713b1edbc	1852	#include "stm32l1xx_hal_rcc_ex.h"
AnnaBridge	171:3a7713b1edbc	1853
AnnaBridge	171:3a7713b1edbc	1854	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1855	/** @addtogroup RCC_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1856	* @{
AnnaBridge	171:3a7713b1edbc	1857	*/
AnnaBridge	171:3a7713b1edbc	1858
AnnaBridge	171:3a7713b1edbc	1859	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1860	* @{
AnnaBridge	171:3a7713b1edbc	1861	*/
AnnaBridge	171:3a7713b1edbc	1862
AnnaBridge	171:3a7713b1edbc	1863	/* Initialization and de-initialization functions ******************************/
AnnaBridge	171:3a7713b1edbc	1864	void HAL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	1865	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1866	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	171:3a7713b1edbc	1867
AnnaBridge	171:3a7713b1edbc	1868	/**
AnnaBridge	171:3a7713b1edbc	1869	* @}
AnnaBridge	171:3a7713b1edbc	1870	*/
AnnaBridge	171:3a7713b1edbc	1871
AnnaBridge	171:3a7713b1edbc	1872	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1873	* @{
AnnaBridge	171:3a7713b1edbc	1874	*/
AnnaBridge	171:3a7713b1edbc	1875
AnnaBridge	171:3a7713b1edbc	1876	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	1877	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	171:3a7713b1edbc	1878	void HAL_RCC_EnableCSS(void);
AnnaBridge	171:3a7713b1edbc	1879	/* CSS NMI IRQ handler */
AnnaBridge	171:3a7713b1edbc	1880	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	171:3a7713b1edbc	1881	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	171:3a7713b1edbc	1882	void HAL_RCC_CSSCallback(void);
AnnaBridge	171:3a7713b1edbc	1883	void HAL_RCC_DisableCSS(void);
AnnaBridge	171:3a7713b1edbc	1884	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	171:3a7713b1edbc	1885	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	171:3a7713b1edbc	1886	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	171:3a7713b1edbc	1887	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	171:3a7713b1edbc	1888	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1889	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	171:3a7713b1edbc	1890
AnnaBridge	171:3a7713b1edbc	1891	/**
AnnaBridge	171:3a7713b1edbc	1892	* @}
AnnaBridge	171:3a7713b1edbc	1893	*/
AnnaBridge	171:3a7713b1edbc	1894
AnnaBridge	171:3a7713b1edbc	1895	/**
AnnaBridge	171:3a7713b1edbc	1896	* @}
AnnaBridge	171:3a7713b1edbc	1897	*/
AnnaBridge	171:3a7713b1edbc	1898
AnnaBridge	171:3a7713b1edbc	1899	/**
AnnaBridge	171:3a7713b1edbc	1900	* @}
AnnaBridge	171:3a7713b1edbc	1901	*/
AnnaBridge	171:3a7713b1edbc	1902
AnnaBridge	171:3a7713b1edbc	1903	/**
AnnaBridge	171:3a7713b1edbc	1904	* @}
AnnaBridge	171:3a7713b1edbc	1905	*/
AnnaBridge	171:3a7713b1edbc	1906
AnnaBridge	171:3a7713b1edbc	1907	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1908	}
AnnaBridge	171:3a7713b1edbc	1909	#endif
AnnaBridge	171:3a7713b1edbc	1910
AnnaBridge	171:3a7713b1edbc	1911	#endif /* __STM32L1xx_HAL_RCC_H */
AnnaBridge	171:3a7713b1edbc	1912
AnnaBridge	171:3a7713b1edbc	1913	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	171:3a7713b1edbc	1914