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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_hal_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_hal_pwr.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_HAL_PWR_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_HAL_PWR_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32l1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup PWR |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 59 | */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /** |
| AnnaBridge | 171:3a7713b1edbc | 62 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 171:3a7713b1edbc | 63 | */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 65 | { |
| AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 171:3a7713b1edbc | 67 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 171:3a7713b1edbc | 70 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | }PWR_PVDTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | /** |
| AnnaBridge | 171:3a7713b1edbc | 74 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 75 | */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /* Internal constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /** @addtogroup PWR_Private_Constants |
| AnnaBridge | 171:3a7713b1edbc | 80 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 81 | */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | /** |
| AnnaBridge | 171:3a7713b1edbc | 85 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 86 | */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 93 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 94 | */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | |
| AnnaBridge | 171:3a7713b1edbc | 96 | /** @defgroup PWR_register_alias_address PWR Register alias address |
| AnnaBridge | 171:3a7713b1edbc | 97 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 98 | */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define PWR_CR_OFFSET 0x00 |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define PWR_CSR_OFFSET 0x04 |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
| AnnaBridge | 171:3a7713b1edbc | 105 | /** |
| AnnaBridge | 171:3a7713b1edbc | 106 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 107 | */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | |
| AnnaBridge | 171:3a7713b1edbc | 109 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
| AnnaBridge | 171:3a7713b1edbc | 110 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 111 | */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | /* --- CR Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 113 | /* Alias word address of LPSDSR bit */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 116 | |
| AnnaBridge | 171:3a7713b1edbc | 117 | /* Alias word address of DBP bit */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | /* Alias word address of LPRUN bit */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | /* Alias word address of PVDE bit */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 128 | |
| AnnaBridge | 171:3a7713b1edbc | 129 | /* Alias word address of FWU bit */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 132 | |
| AnnaBridge | 171:3a7713b1edbc | 133 | /* Alias word address of ULP bit */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 136 | /** |
| AnnaBridge | 171:3a7713b1edbc | 137 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 138 | */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
| AnnaBridge | 171:3a7713b1edbc | 141 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 142 | */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | |
| AnnaBridge | 171:3a7713b1edbc | 144 | /* --- CSR Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 145 | /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) |
| AnnaBridge | 171:3a7713b1edbc | 147 | /** |
| AnnaBridge | 171:3a7713b1edbc | 148 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 149 | */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| AnnaBridge | 171:3a7713b1edbc | 152 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
| AnnaBridge | 171:3a7713b1edbc | 162 | (Compare internally to VREFINT) */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | /** |
| AnnaBridge | 171:3a7713b1edbc | 165 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | |
| AnnaBridge | 171:3a7713b1edbc | 168 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| AnnaBridge | 171:3a7713b1edbc | 169 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 170 | */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | |
| AnnaBridge | 171:3a7713b1edbc | 179 | /** |
| AnnaBridge | 171:3a7713b1edbc | 180 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 181 | */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | |
| AnnaBridge | 171:3a7713b1edbc | 183 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 184 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 185 | */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define PWR_MAINREGULATOR_ON (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
| AnnaBridge | 171:3a7713b1edbc | 188 | |
| AnnaBridge | 171:3a7713b1edbc | 189 | /** |
| AnnaBridge | 171:3a7713b1edbc | 190 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 191 | */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
| AnnaBridge | 171:3a7713b1edbc | 198 | |
| AnnaBridge | 171:3a7713b1edbc | 199 | /** |
| AnnaBridge | 171:3a7713b1edbc | 200 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 201 | */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | |
| AnnaBridge | 171:3a7713b1edbc | 203 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 205 | */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
| AnnaBridge | 171:3a7713b1edbc | 208 | |
| AnnaBridge | 171:3a7713b1edbc | 209 | /** |
| AnnaBridge | 171:3a7713b1edbc | 210 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 211 | */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | |
| AnnaBridge | 171:3a7713b1edbc | 213 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 215 | */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
| AnnaBridge | 171:3a7713b1edbc | 220 | |
| AnnaBridge | 171:3a7713b1edbc | 221 | |
| AnnaBridge | 171:3a7713b1edbc | 222 | /** |
| AnnaBridge | 171:3a7713b1edbc | 223 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 224 | */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | /** @defgroup PWR_Flag PWR Flag |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 228 | */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
| AnnaBridge | 171:3a7713b1edbc | 235 | |
| AnnaBridge | 171:3a7713b1edbc | 236 | /** |
| AnnaBridge | 171:3a7713b1edbc | 237 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 238 | */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | |
| AnnaBridge | 171:3a7713b1edbc | 240 | /** |
| AnnaBridge | 171:3a7713b1edbc | 241 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 242 | */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | |
| AnnaBridge | 171:3a7713b1edbc | 244 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 245 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 246 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 247 | */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | |
| AnnaBridge | 171:3a7713b1edbc | 249 | /** @brief macros configure the main internal regulator output voltage. |
| AnnaBridge | 171:3a7713b1edbc | 250 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| AnnaBridge | 171:3a7713b1edbc | 251 | * a tradeoff between performance and power consumption when the device does |
| AnnaBridge | 171:3a7713b1edbc | 252 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| AnnaBridge | 171:3a7713b1edbc | 253 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 254 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
| AnnaBridge | 171:3a7713b1edbc | 255 | * System frequency up to 32 MHz. |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
| AnnaBridge | 171:3a7713b1edbc | 257 | * System frequency up to 16 MHz. |
| AnnaBridge | 171:3a7713b1edbc | 258 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
| AnnaBridge | 171:3a7713b1edbc | 259 | * System frequency up to 4.2 MHz |
| AnnaBridge | 171:3a7713b1edbc | 260 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 261 | */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
| AnnaBridge | 171:3a7713b1edbc | 263 | |
| AnnaBridge | 171:3a7713b1edbc | 264 | /** @brief Check PWR flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 266 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 267 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| AnnaBridge | 171:3a7713b1edbc | 268 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
| AnnaBridge | 171:3a7713b1edbc | 269 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
| AnnaBridge | 171:3a7713b1edbc | 270 | * An additional wakeup event is detected if the WKUP pin is enabled |
| AnnaBridge | 171:3a7713b1edbc | 271 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| AnnaBridge | 171:3a7713b1edbc | 272 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| AnnaBridge | 171:3a7713b1edbc | 273 | * resumed from StandBy mode. |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| AnnaBridge | 171:3a7713b1edbc | 275 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
| AnnaBridge | 171:3a7713b1edbc | 276 | * For this reason, this bit is equal to 0 after Standby or reset |
| AnnaBridge | 171:3a7713b1edbc | 277 | * until the PVDE bit is set. |
| AnnaBridge | 171:3a7713b1edbc | 278 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
| AnnaBridge | 171:3a7713b1edbc | 279 | * This bit indicates the state of the internal voltage reference, VREFINT. |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
| AnnaBridge | 171:3a7713b1edbc | 281 | * the internal regulator to be ready after the voltage range is changed. |
| AnnaBridge | 171:3a7713b1edbc | 282 | * The VOSF bit indicates that the regulator has reached the voltage level |
| AnnaBridge | 171:3a7713b1edbc | 283 | * defined with bits VOS of PWR_CR register. |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
| AnnaBridge | 171:3a7713b1edbc | 285 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
| AnnaBridge | 171:3a7713b1edbc | 286 | * A polling on this bit is recommended to wait for the regulator main mode. |
| AnnaBridge | 171:3a7713b1edbc | 287 | * This bit is reset by hardware when the regulator is ready. |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 289 | */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 291 | |
| AnnaBridge | 171:3a7713b1edbc | 292 | /** @brief Clear the PWR's pending flags. |
| AnnaBridge | 171:3a7713b1edbc | 293 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 294 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 295 | * @arg PWR_FLAG_WU: Wake Up flag |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @arg PWR_FLAG_SB: StandBy flag |
| AnnaBridge | 171:3a7713b1edbc | 297 | */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
| AnnaBridge | 171:3a7713b1edbc | 299 | |
| AnnaBridge | 171:3a7713b1edbc | 300 | /** |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @brief Enable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 303 | */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 305 | |
| AnnaBridge | 171:3a7713b1edbc | 306 | /** |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @brief Disable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 309 | */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 311 | |
| AnnaBridge | 171:3a7713b1edbc | 312 | /** |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @brief Enable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 317 | |
| AnnaBridge | 171:3a7713b1edbc | 318 | /** |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @brief Disable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 321 | */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | |
| AnnaBridge | 171:3a7713b1edbc | 325 | /** |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 327 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 328 | */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 330 | |
| AnnaBridge | 171:3a7713b1edbc | 331 | |
| AnnaBridge | 171:3a7713b1edbc | 332 | /** |
| AnnaBridge | 171:3a7713b1edbc | 333 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 334 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 335 | */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 337 | |
| AnnaBridge | 171:3a7713b1edbc | 338 | |
| AnnaBridge | 171:3a7713b1edbc | 339 | /** |
| AnnaBridge | 171:3a7713b1edbc | 340 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 342 | */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 344 | |
| AnnaBridge | 171:3a7713b1edbc | 345 | /** |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 347 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 348 | */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 350 | |
| AnnaBridge | 171:3a7713b1edbc | 351 | /** |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 353 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 354 | */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 171:3a7713b1edbc | 356 | do { \ |
| AnnaBridge | 171:3a7713b1edbc | 357 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 358 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 359 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 360 | |
| AnnaBridge | 171:3a7713b1edbc | 361 | /** |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 364 | */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 171:3a7713b1edbc | 366 | do { \ |
| AnnaBridge | 171:3a7713b1edbc | 367 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 368 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 369 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 370 | |
| AnnaBridge | 171:3a7713b1edbc | 371 | |
| AnnaBridge | 171:3a7713b1edbc | 372 | |
| AnnaBridge | 171:3a7713b1edbc | 373 | /** |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 171:3a7713b1edbc | 376 | */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 378 | |
| AnnaBridge | 171:3a7713b1edbc | 379 | /** |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @brief Clear the PVD EXTI flag. |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 382 | */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 384 | |
| AnnaBridge | 171:3a7713b1edbc | 385 | /** |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 388 | */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 390 | |
| AnnaBridge | 171:3a7713b1edbc | 391 | /** |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 393 | */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | |
| AnnaBridge | 171:3a7713b1edbc | 395 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 396 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 398 | */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 401 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 402 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 403 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 171:3a7713b1edbc | 404 | |
| AnnaBridge | 171:3a7713b1edbc | 405 | |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 407 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 408 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 409 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| AnnaBridge | 171:3a7713b1edbc | 410 | |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 171:3a7713b1edbc | 412 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 171:3a7713b1edbc | 413 | |
| AnnaBridge | 171:3a7713b1edbc | 414 | |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 171:3a7713b1edbc | 416 | |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 420 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 421 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
| AnnaBridge | 171:3a7713b1edbc | 422 | |
| AnnaBridge | 171:3a7713b1edbc | 423 | |
| AnnaBridge | 171:3a7713b1edbc | 424 | /** |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 426 | */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | |
| AnnaBridge | 171:3a7713b1edbc | 430 | /* Include PWR HAL Extension module */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #include "stm32l1xx_hal_pwr_ex.h" |
| AnnaBridge | 171:3a7713b1edbc | 432 | |
| AnnaBridge | 171:3a7713b1edbc | 433 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 434 | |
| AnnaBridge | 171:3a7713b1edbc | 435 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 437 | */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | |
| AnnaBridge | 171:3a7713b1edbc | 439 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 171:3a7713b1edbc | 440 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 441 | */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | |
| AnnaBridge | 171:3a7713b1edbc | 443 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 171:3a7713b1edbc | 444 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 171:3a7713b1edbc | 445 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 171:3a7713b1edbc | 446 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 171:3a7713b1edbc | 447 | |
| AnnaBridge | 171:3a7713b1edbc | 448 | /** |
| AnnaBridge | 171:3a7713b1edbc | 449 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 450 | */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 454 | */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 457 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 171:3a7713b1edbc | 458 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 459 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 460 | |
| AnnaBridge | 171:3a7713b1edbc | 461 | /* WakeUp pins configuration functions ****************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 462 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 171:3a7713b1edbc | 463 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 171:3a7713b1edbc | 464 | |
| AnnaBridge | 171:3a7713b1edbc | 465 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 466 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 171:3a7713b1edbc | 467 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 171:3a7713b1edbc | 468 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 171:3a7713b1edbc | 469 | |
| AnnaBridge | 171:3a7713b1edbc | 470 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 171:3a7713b1edbc | 471 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 171:3a7713b1edbc | 472 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 171:3a7713b1edbc | 473 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 171:3a7713b1edbc | 474 | |
| AnnaBridge | 171:3a7713b1edbc | 475 | |
| AnnaBridge | 171:3a7713b1edbc | 476 | |
| AnnaBridge | 171:3a7713b1edbc | 477 | void HAL_PWR_PVD_IRQHandler(void); |
| AnnaBridge | 171:3a7713b1edbc | 478 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 171:3a7713b1edbc | 479 | /** |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 481 | */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | |
| AnnaBridge | 171:3a7713b1edbc | 483 | /** |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | |
| AnnaBridge | 171:3a7713b1edbc | 487 | /** |
| AnnaBridge | 171:3a7713b1edbc | 488 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 489 | */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | |
| AnnaBridge | 171:3a7713b1edbc | 491 | /** |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 493 | */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | |
| AnnaBridge | 171:3a7713b1edbc | 495 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 496 | } |
| AnnaBridge | 171:3a7713b1edbc | 497 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 498 | |
| AnnaBridge | 171:3a7713b1edbc | 499 | |
| AnnaBridge | 171:3a7713b1edbc | 500 | #endif /* __STM32L1xx_HAL_PWR_H */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | |
| AnnaBridge | 171:3a7713b1edbc | 502 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
