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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_pwr.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 143:86740a56073b | 1 | /** |
| AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_ll_pwr.h |
| AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
| AnnaBridge | 143:86740a56073b | 5 | * @brief Header file of PWR LL module. |
| AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 7 | * @attention |
| AnnaBridge | 143:86740a56073b | 8 | * |
| AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 143:86740a56073b | 10 | * |
| AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
| AnnaBridge | 143:86740a56073b | 21 | * |
| AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 143:86740a56073b | 32 | * |
| AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 34 | */ |
| AnnaBridge | 143:86740a56073b | 35 | |
| AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 37 | #ifndef __STM32L0xx_LL_PWR_H |
| AnnaBridge | 143:86740a56073b | 38 | #define __STM32L0xx_LL_PWR_H |
| AnnaBridge | 143:86740a56073b | 39 | |
| AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 41 | extern "C" { |
| AnnaBridge | 143:86740a56073b | 42 | #endif |
| AnnaBridge | 143:86740a56073b | 43 | |
| AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 45 | #include "stm32l0xx.h" |
| AnnaBridge | 143:86740a56073b | 46 | |
| AnnaBridge | 143:86740a56073b | 47 | /** @addtogroup STM32L0xx_LL_Driver |
| AnnaBridge | 143:86740a56073b | 48 | * @{ |
| AnnaBridge | 143:86740a56073b | 49 | */ |
| AnnaBridge | 143:86740a56073b | 50 | |
| AnnaBridge | 143:86740a56073b | 51 | #if defined(PWR) |
| AnnaBridge | 143:86740a56073b | 52 | |
| AnnaBridge | 143:86740a56073b | 53 | /** @defgroup PWR_LL PWR |
| AnnaBridge | 143:86740a56073b | 54 | * @{ |
| AnnaBridge | 143:86740a56073b | 55 | */ |
| AnnaBridge | 143:86740a56073b | 56 | |
| AnnaBridge | 143:86740a56073b | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 59 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 60 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 61 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 62 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
| AnnaBridge | 143:86740a56073b | 64 | * @{ |
| AnnaBridge | 143:86740a56073b | 65 | */ |
| AnnaBridge | 143:86740a56073b | 66 | |
| AnnaBridge | 143:86740a56073b | 67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 143:86740a56073b | 68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
| AnnaBridge | 143:86740a56073b | 69 | * @{ |
| AnnaBridge | 143:86740a56073b | 70 | */ |
| AnnaBridge | 143:86740a56073b | 71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
| AnnaBridge | 143:86740a56073b | 72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
| AnnaBridge | 143:86740a56073b | 73 | /** |
| AnnaBridge | 143:86740a56073b | 74 | * @} |
| AnnaBridge | 143:86740a56073b | 75 | */ |
| AnnaBridge | 143:86740a56073b | 76 | |
| AnnaBridge | 143:86740a56073b | 77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 143:86740a56073b | 78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
| AnnaBridge | 143:86740a56073b | 79 | * @{ |
| AnnaBridge | 143:86740a56073b | 80 | */ |
| AnnaBridge | 143:86740a56073b | 81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
| AnnaBridge | 143:86740a56073b | 82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
| AnnaBridge | 167:84c0a372a020 | 83 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 143:86740a56073b | 84 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
| AnnaBridge | 167:84c0a372a020 | 85 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 167:84c0a372a020 | 86 | #if defined(PWR_CSR_VREFINTRDYF) |
| AnnaBridge | 143:86740a56073b | 87 | #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ |
| AnnaBridge | 167:84c0a372a020 | 88 | #endif /* PWR_CSR_VREFINTRDYF */ |
| AnnaBridge | 167:84c0a372a020 | 89 | #define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag */ |
| AnnaBridge | 143:86740a56073b | 90 | #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */ |
| AnnaBridge | 143:86740a56073b | 91 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
| AnnaBridge | 143:86740a56073b | 92 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
| AnnaBridge | 167:84c0a372a020 | 93 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 143:86740a56073b | 94 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
| AnnaBridge | 143:86740a56073b | 95 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 143:86740a56073b | 96 | /** |
| AnnaBridge | 143:86740a56073b | 97 | * @} |
| AnnaBridge | 143:86740a56073b | 98 | */ |
| AnnaBridge | 143:86740a56073b | 99 | |
| AnnaBridge | 143:86740a56073b | 100 | /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage |
| AnnaBridge | 143:86740a56073b | 101 | * @{ |
| AnnaBridge | 143:86740a56073b | 102 | */ |
| AnnaBridge | 143:86740a56073b | 103 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */ |
| AnnaBridge | 143:86740a56073b | 104 | #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */ |
| AnnaBridge | 143:86740a56073b | 105 | #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */ |
| AnnaBridge | 143:86740a56073b | 106 | /** |
| AnnaBridge | 143:86740a56073b | 107 | * @} |
| AnnaBridge | 143:86740a56073b | 108 | */ |
| AnnaBridge | 143:86740a56073b | 109 | |
| AnnaBridge | 143:86740a56073b | 110 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
| AnnaBridge | 143:86740a56073b | 111 | * @{ |
| AnnaBridge | 143:86740a56073b | 112 | */ |
| AnnaBridge | 167:84c0a372a020 | 113 | #define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
| AnnaBridge | 167:84c0a372a020 | 114 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
| AnnaBridge | 143:86740a56073b | 115 | /** |
| AnnaBridge | 143:86740a56073b | 116 | * @} |
| AnnaBridge | 143:86740a56073b | 117 | */ |
| AnnaBridge | 143:86740a56073b | 118 | |
| AnnaBridge | 143:86740a56073b | 119 | /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes |
| AnnaBridge | 143:86740a56073b | 120 | * @{ |
| AnnaBridge | 143:86740a56073b | 121 | */ |
| AnnaBridge | 167:84c0a372a020 | 122 | #define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */ |
| AnnaBridge | 167:84c0a372a020 | 123 | #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */ |
| AnnaBridge | 143:86740a56073b | 124 | /** |
| AnnaBridge | 143:86740a56073b | 125 | * @} |
| AnnaBridge | 143:86740a56073b | 126 | */ |
| AnnaBridge | 143:86740a56073b | 127 | #if defined(PWR_CR_LPDS) |
| AnnaBridge | 143:86740a56073b | 128 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
| AnnaBridge | 143:86740a56073b | 129 | * @{ |
| AnnaBridge | 143:86740a56073b | 130 | */ |
| AnnaBridge | 167:84c0a372a020 | 131 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ |
| AnnaBridge | 167:84c0a372a020 | 132 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ |
| AnnaBridge | 143:86740a56073b | 133 | /** |
| AnnaBridge | 167:84c0a372a020 | 134 | * @} |
| AnnaBridge | 167:84c0a372a020 | 135 | */ |
| AnnaBridge | 143:86740a56073b | 136 | #endif /* PWR_CR_LPDS */ |
| AnnaBridge | 143:86740a56073b | 137 | |
| AnnaBridge | 167:84c0a372a020 | 138 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 143:86740a56073b | 139 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
| AnnaBridge | 143:86740a56073b | 140 | * @{ |
| AnnaBridge | 143:86740a56073b | 141 | */ |
| AnnaBridge | 143:86740a56073b | 142 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */ |
| AnnaBridge | 143:86740a56073b | 143 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */ |
| AnnaBridge | 143:86740a56073b | 144 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */ |
| AnnaBridge | 143:86740a56073b | 145 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
| AnnaBridge | 143:86740a56073b | 146 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */ |
| AnnaBridge | 143:86740a56073b | 147 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */ |
| AnnaBridge | 143:86740a56073b | 148 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */ |
| AnnaBridge | 143:86740a56073b | 149 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */ |
| AnnaBridge | 143:86740a56073b | 150 | /** |
| AnnaBridge | 143:86740a56073b | 151 | * @} |
| AnnaBridge | 143:86740a56073b | 152 | */ |
| AnnaBridge | 167:84c0a372a020 | 153 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 143:86740a56073b | 154 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
| AnnaBridge | 167:84c0a372a020 | 155 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 156 | */ |
| AnnaBridge | 143:86740a56073b | 157 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
| AnnaBridge | 143:86740a56073b | 158 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ |
| AnnaBridge | 167:84c0a372a020 | 159 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 143:86740a56073b | 160 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ |
| AnnaBridge | 143:86740a56073b | 161 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 143:86740a56073b | 162 | /** |
| AnnaBridge | 143:86740a56073b | 163 | * @} |
| AnnaBridge | 143:86740a56073b | 164 | */ |
| AnnaBridge | 143:86740a56073b | 165 | |
| AnnaBridge | 143:86740a56073b | 166 | /** |
| AnnaBridge | 143:86740a56073b | 167 | * @} |
| AnnaBridge | 143:86740a56073b | 168 | */ |
| AnnaBridge | 143:86740a56073b | 169 | |
| AnnaBridge | 143:86740a56073b | 170 | |
| AnnaBridge | 143:86740a56073b | 171 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 172 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
| AnnaBridge | 143:86740a56073b | 173 | * @{ |
| AnnaBridge | 143:86740a56073b | 174 | */ |
| AnnaBridge | 143:86740a56073b | 175 | |
| AnnaBridge | 143:86740a56073b | 176 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
| AnnaBridge | 143:86740a56073b | 177 | * @{ |
| AnnaBridge | 143:86740a56073b | 178 | */ |
| AnnaBridge | 143:86740a56073b | 179 | |
| AnnaBridge | 143:86740a56073b | 180 | /** |
| AnnaBridge | 143:86740a56073b | 181 | * @brief Write a value in PWR register |
| AnnaBridge | 143:86740a56073b | 182 | * @param __REG__ Register to be written |
| AnnaBridge | 143:86740a56073b | 183 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 143:86740a56073b | 184 | * @retval None |
| AnnaBridge | 143:86740a56073b | 185 | */ |
| AnnaBridge | 143:86740a56073b | 186 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
| AnnaBridge | 143:86740a56073b | 187 | |
| AnnaBridge | 143:86740a56073b | 188 | /** |
| AnnaBridge | 143:86740a56073b | 189 | * @brief Read a value in PWR register |
| AnnaBridge | 143:86740a56073b | 190 | * @param __REG__ Register to be read |
| AnnaBridge | 143:86740a56073b | 191 | * @retval Register value |
| AnnaBridge | 143:86740a56073b | 192 | */ |
| AnnaBridge | 143:86740a56073b | 193 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
| AnnaBridge | 143:86740a56073b | 194 | /** |
| AnnaBridge | 143:86740a56073b | 195 | * @} |
| AnnaBridge | 143:86740a56073b | 196 | */ |
| AnnaBridge | 143:86740a56073b | 197 | |
| AnnaBridge | 143:86740a56073b | 198 | /** |
| AnnaBridge | 143:86740a56073b | 199 | * @} |
| AnnaBridge | 143:86740a56073b | 200 | */ |
| AnnaBridge | 143:86740a56073b | 201 | |
| AnnaBridge | 143:86740a56073b | 202 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 203 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
| AnnaBridge | 143:86740a56073b | 204 | * @{ |
| AnnaBridge | 143:86740a56073b | 205 | */ |
| AnnaBridge | 143:86740a56073b | 206 | |
| AnnaBridge | 143:86740a56073b | 207 | /** @defgroup PWR_LL_EF_Configuration Configuration |
| AnnaBridge | 143:86740a56073b | 208 | * @{ |
| AnnaBridge | 143:86740a56073b | 209 | */ |
| AnnaBridge | 143:86740a56073b | 210 | /** |
| AnnaBridge | 143:86740a56073b | 211 | * @brief Switch the regulator from main mode to low-power mode |
| AnnaBridge | 143:86740a56073b | 212 | * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode |
| AnnaBridge | 143:86740a56073b | 213 | * @note Remind to set the regulator to low power before enabling |
| AnnaBridge | 143:86740a56073b | 214 | * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER). |
| AnnaBridge | 143:86740a56073b | 215 | * @retval None |
| AnnaBridge | 143:86740a56073b | 216 | */ |
| AnnaBridge | 143:86740a56073b | 217 | __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) |
| AnnaBridge | 143:86740a56073b | 218 | { |
| AnnaBridge | 143:86740a56073b | 219 | SET_BIT(PWR->CR, PWR_CR_LPRUN); |
| AnnaBridge | 143:86740a56073b | 220 | } |
| AnnaBridge | 143:86740a56073b | 221 | |
| AnnaBridge | 143:86740a56073b | 222 | /** |
| AnnaBridge | 143:86740a56073b | 223 | * @brief Switch the regulator from low-power mode to main mode |
| AnnaBridge | 143:86740a56073b | 224 | * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode |
| AnnaBridge | 143:86740a56073b | 225 | * @retval None |
| AnnaBridge | 143:86740a56073b | 226 | */ |
| AnnaBridge | 143:86740a56073b | 227 | __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) |
| AnnaBridge | 143:86740a56073b | 228 | { |
| AnnaBridge | 143:86740a56073b | 229 | CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); |
| AnnaBridge | 143:86740a56073b | 230 | } |
| AnnaBridge | 143:86740a56073b | 231 | |
| AnnaBridge | 143:86740a56073b | 232 | /** |
| AnnaBridge | 143:86740a56073b | 233 | * @brief Check if the regulator is in low-power mode |
| AnnaBridge | 143:86740a56073b | 234 | * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode |
| AnnaBridge | 143:86740a56073b | 235 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 236 | */ |
| AnnaBridge | 143:86740a56073b | 237 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) |
| AnnaBridge | 143:86740a56073b | 238 | { |
| AnnaBridge | 143:86740a56073b | 239 | return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN)); |
| AnnaBridge | 143:86740a56073b | 240 | } |
| AnnaBridge | 143:86740a56073b | 241 | |
| AnnaBridge | 143:86740a56073b | 242 | /** |
| AnnaBridge | 143:86740a56073b | 243 | * @brief Set voltage regulator to low-power and switch from |
| AnnaBridge | 143:86740a56073b | 244 | * run main mode to run low-power mode. |
| AnnaBridge | 143:86740a56073b | 245 | * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n |
| AnnaBridge | 143:86740a56073b | 246 | * CR LPRUN LL_PWR_EnterLowPowerRunMode |
| AnnaBridge | 143:86740a56073b | 247 | * @note This "high level" function is introduced to provide functional |
| AnnaBridge | 143:86740a56073b | 248 | * compatibility with other families. Notice that the two registers |
| AnnaBridge | 143:86740a56073b | 249 | * have to be written sequentially, so this function is not atomic. |
| AnnaBridge | 143:86740a56073b | 250 | * To assure atomicity you can call separately the following functions: |
| AnnaBridge | 143:86740a56073b | 251 | * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER); |
| AnnaBridge | 143:86740a56073b | 252 | * - @ref LL_PWR_EnableLowPowerRunMode(); |
| AnnaBridge | 143:86740a56073b | 253 | * @retval None |
| AnnaBridge | 143:86740a56073b | 254 | */ |
| AnnaBridge | 143:86740a56073b | 255 | __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) |
| AnnaBridge | 143:86740a56073b | 256 | { |
| AnnaBridge | 143:86740a56073b | 257 | SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */ |
| AnnaBridge | 143:86740a56073b | 258 | SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */ |
| AnnaBridge | 143:86740a56073b | 259 | } |
| AnnaBridge | 143:86740a56073b | 260 | |
| AnnaBridge | 143:86740a56073b | 261 | /** |
| AnnaBridge | 143:86740a56073b | 262 | * @brief Set voltage regulator to main and switch from |
| AnnaBridge | 143:86740a56073b | 263 | * run main mode to low-power mode. |
| AnnaBridge | 143:86740a56073b | 264 | * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n |
| AnnaBridge | 143:86740a56073b | 265 | * CR LPRUN LL_PWR_ExitLowPowerRunMode |
| AnnaBridge | 143:86740a56073b | 266 | * @note This "high level" function is introduced to provide functional |
| AnnaBridge | 143:86740a56073b | 267 | * compatibility with other families. Notice that the two registers |
| AnnaBridge | 143:86740a56073b | 268 | * have to be written sequentially, so this function is not atomic. |
| AnnaBridge | 143:86740a56073b | 269 | * To assure atomicity you can call separately the following functions: |
| AnnaBridge | 143:86740a56073b | 270 | * - @ref LL_PWR_DisableLowPowerRunMode(); |
| AnnaBridge | 143:86740a56073b | 271 | * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN); |
| AnnaBridge | 143:86740a56073b | 272 | * @retval None |
| AnnaBridge | 143:86740a56073b | 273 | */ |
| AnnaBridge | 143:86740a56073b | 274 | __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) |
| AnnaBridge | 143:86740a56073b | 275 | { |
| AnnaBridge | 143:86740a56073b | 276 | CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */ |
| AnnaBridge | 143:86740a56073b | 277 | CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */ |
| AnnaBridge | 143:86740a56073b | 278 | } |
| AnnaBridge | 143:86740a56073b | 279 | /** |
| AnnaBridge | 143:86740a56073b | 280 | * @brief Set the main internal regulator output voltage |
| AnnaBridge | 143:86740a56073b | 281 | * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling |
| AnnaBridge | 143:86740a56073b | 282 | * @param VoltageScaling This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 283 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 143:86740a56073b | 284 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 143:86740a56073b | 285 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 143:86740a56073b | 286 | * @retval None |
| AnnaBridge | 143:86740a56073b | 287 | */ |
| AnnaBridge | 143:86740a56073b | 288 | __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) |
| AnnaBridge | 143:86740a56073b | 289 | { |
| AnnaBridge | 143:86740a56073b | 290 | MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); |
| AnnaBridge | 143:86740a56073b | 291 | } |
| AnnaBridge | 143:86740a56073b | 292 | |
| AnnaBridge | 143:86740a56073b | 293 | /** |
| AnnaBridge | 143:86740a56073b | 294 | * @brief Get the main internal regulator output voltage |
| AnnaBridge | 143:86740a56073b | 295 | * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling |
| AnnaBridge | 143:86740a56073b | 296 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 297 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 143:86740a56073b | 298 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 143:86740a56073b | 299 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 143:86740a56073b | 300 | */ |
| AnnaBridge | 143:86740a56073b | 301 | __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) |
| AnnaBridge | 143:86740a56073b | 302 | { |
| AnnaBridge | 143:86740a56073b | 303 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); |
| AnnaBridge | 143:86740a56073b | 304 | } |
| AnnaBridge | 143:86740a56073b | 305 | |
| AnnaBridge | 143:86740a56073b | 306 | /** |
| AnnaBridge | 143:86740a56073b | 307 | * @brief Enable access to the backup domain |
| AnnaBridge | 143:86740a56073b | 308 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
| AnnaBridge | 143:86740a56073b | 309 | * @retval None |
| AnnaBridge | 143:86740a56073b | 310 | */ |
| AnnaBridge | 143:86740a56073b | 311 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
| AnnaBridge | 143:86740a56073b | 312 | { |
| AnnaBridge | 143:86740a56073b | 313 | SET_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 143:86740a56073b | 314 | } |
| AnnaBridge | 143:86740a56073b | 315 | |
| AnnaBridge | 143:86740a56073b | 316 | /** |
| AnnaBridge | 143:86740a56073b | 317 | * @brief Disable access to the backup domain |
| AnnaBridge | 143:86740a56073b | 318 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
| AnnaBridge | 143:86740a56073b | 319 | * @retval None |
| AnnaBridge | 143:86740a56073b | 320 | */ |
| AnnaBridge | 143:86740a56073b | 321 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
| AnnaBridge | 143:86740a56073b | 322 | { |
| AnnaBridge | 143:86740a56073b | 323 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 143:86740a56073b | 324 | } |
| AnnaBridge | 143:86740a56073b | 325 | |
| AnnaBridge | 143:86740a56073b | 326 | /** |
| AnnaBridge | 143:86740a56073b | 327 | * @brief Check if the backup domain is enabled |
| AnnaBridge | 143:86740a56073b | 328 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
| AnnaBridge | 143:86740a56073b | 329 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 330 | */ |
| AnnaBridge | 143:86740a56073b | 331 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
| AnnaBridge | 143:86740a56073b | 332 | { |
| AnnaBridge | 143:86740a56073b | 333 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
| AnnaBridge | 143:86740a56073b | 334 | } |
| AnnaBridge | 143:86740a56073b | 335 | |
| AnnaBridge | 143:86740a56073b | 336 | /** |
| AnnaBridge | 143:86740a56073b | 337 | * @brief Set voltage regulator mode during low power modes |
| AnnaBridge | 143:86740a56073b | 338 | * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP |
| AnnaBridge | 143:86740a56073b | 339 | * @param RegulMode This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 340 | * @arg @ref LL_PWR_REGU_LPMODES_MAIN |
| AnnaBridge | 143:86740a56073b | 341 | * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER |
| AnnaBridge | 143:86740a56073b | 342 | * @retval None |
| AnnaBridge | 143:86740a56073b | 343 | */ |
| AnnaBridge | 143:86740a56073b | 344 | __STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode) |
| AnnaBridge | 143:86740a56073b | 345 | { |
| AnnaBridge | 143:86740a56073b | 346 | MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode); |
| AnnaBridge | 143:86740a56073b | 347 | } |
| AnnaBridge | 143:86740a56073b | 348 | |
| AnnaBridge | 143:86740a56073b | 349 | /** |
| AnnaBridge | 143:86740a56073b | 350 | * @brief Get voltage regulator mode during low power modes |
| AnnaBridge | 143:86740a56073b | 351 | * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP |
| AnnaBridge | 143:86740a56073b | 352 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 353 | * @arg @ref LL_PWR_REGU_LPMODES_MAIN |
| AnnaBridge | 143:86740a56073b | 354 | * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER |
| AnnaBridge | 143:86740a56073b | 355 | */ |
| AnnaBridge | 143:86740a56073b | 356 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void) |
| AnnaBridge | 143:86740a56073b | 357 | { |
| AnnaBridge | 143:86740a56073b | 358 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR)); |
| AnnaBridge | 143:86740a56073b | 359 | } |
| AnnaBridge | 143:86740a56073b | 360 | |
| AnnaBridge | 143:86740a56073b | 361 | #if defined(PWR_CR_LPDS) |
| AnnaBridge | 143:86740a56073b | 362 | /** |
| AnnaBridge | 143:86740a56073b | 363 | * @brief Set voltage regulator mode during deep sleep mode |
| AnnaBridge | 143:86740a56073b | 364 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
| AnnaBridge | 143:86740a56073b | 365 | * @param RegulMode This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 366 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 143:86740a56073b | 367 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 143:86740a56073b | 368 | * @retval None |
| AnnaBridge | 143:86740a56073b | 369 | */ |
| AnnaBridge | 143:86740a56073b | 370 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
| AnnaBridge | 143:86740a56073b | 371 | { |
| AnnaBridge | 143:86740a56073b | 372 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
| AnnaBridge | 143:86740a56073b | 373 | } |
| AnnaBridge | 143:86740a56073b | 374 | |
| AnnaBridge | 143:86740a56073b | 375 | /** |
| AnnaBridge | 143:86740a56073b | 376 | * @brief Get voltage regulator mode during deep sleep mode |
| AnnaBridge | 143:86740a56073b | 377 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
| AnnaBridge | 143:86740a56073b | 378 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 379 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 143:86740a56073b | 380 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 143:86740a56073b | 381 | */ |
| AnnaBridge | 143:86740a56073b | 382 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
| AnnaBridge | 143:86740a56073b | 383 | { |
| AnnaBridge | 143:86740a56073b | 384 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
| AnnaBridge | 143:86740a56073b | 385 | } |
| AnnaBridge | 143:86740a56073b | 386 | #endif /* PWR_CR_LPDS */ |
| AnnaBridge | 143:86740a56073b | 387 | |
| AnnaBridge | 143:86740a56073b | 388 | /** |
| AnnaBridge | 143:86740a56073b | 389 | * @brief Set power down mode when CPU enters deepsleep |
| AnnaBridge | 143:86740a56073b | 390 | * @rmtoll CR PDDS LL_PWR_SetPowerMode |
| AnnaBridge | 143:86740a56073b | 391 | * @param PDMode This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 392 | * @arg @ref LL_PWR_MODE_STOP |
| AnnaBridge | 143:86740a56073b | 393 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 143:86740a56073b | 394 | * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER) |
| AnnaBridge | 143:86740a56073b | 395 | * before setting MODE_STOP. If the regulator remains in "main mode", |
| AnnaBridge | 143:86740a56073b | 396 | * it consumes more power without providing any additional feature. |
| AnnaBridge | 143:86740a56073b | 397 | * In MODE_STANDBY the regulator is automatically off. |
| AnnaBridge | 143:86740a56073b | 398 | * @retval None |
| AnnaBridge | 143:86740a56073b | 399 | */ |
| AnnaBridge | 143:86740a56073b | 400 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
| AnnaBridge | 143:86740a56073b | 401 | { |
| AnnaBridge | 143:86740a56073b | 402 | MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode); |
| AnnaBridge | 143:86740a56073b | 403 | } |
| AnnaBridge | 143:86740a56073b | 404 | |
| AnnaBridge | 143:86740a56073b | 405 | /** |
| AnnaBridge | 143:86740a56073b | 406 | * @brief Get power down mode when CPU enters deepsleep |
| AnnaBridge | 143:86740a56073b | 407 | * @rmtoll CR PDDS LL_PWR_GetPowerMode |
| AnnaBridge | 143:86740a56073b | 408 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 409 | * @arg @ref LL_PWR_MODE_STOP |
| AnnaBridge | 143:86740a56073b | 410 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 143:86740a56073b | 411 | */ |
| AnnaBridge | 143:86740a56073b | 412 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
| AnnaBridge | 143:86740a56073b | 413 | { |
| AnnaBridge | 143:86740a56073b | 414 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS)); |
| AnnaBridge | 143:86740a56073b | 415 | } |
| AnnaBridge | 143:86740a56073b | 416 | |
| AnnaBridge | 167:84c0a372a020 | 417 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 143:86740a56073b | 418 | /** |
| AnnaBridge | 143:86740a56073b | 419 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
| AnnaBridge | 143:86740a56073b | 420 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
| AnnaBridge | 143:86740a56073b | 421 | * @param PVDLevel This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 422 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 143:86740a56073b | 423 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 143:86740a56073b | 424 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 143:86740a56073b | 425 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 143:86740a56073b | 426 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 143:86740a56073b | 427 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 143:86740a56073b | 428 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 143:86740a56073b | 429 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 143:86740a56073b | 430 | * @retval None |
| AnnaBridge | 143:86740a56073b | 431 | */ |
| AnnaBridge | 143:86740a56073b | 432 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
| AnnaBridge | 143:86740a56073b | 433 | { |
| AnnaBridge | 143:86740a56073b | 434 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
| AnnaBridge | 143:86740a56073b | 435 | } |
| AnnaBridge | 143:86740a56073b | 436 | |
| AnnaBridge | 143:86740a56073b | 437 | /** |
| AnnaBridge | 143:86740a56073b | 438 | * @brief Get the voltage threshold detection |
| AnnaBridge | 143:86740a56073b | 439 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
| AnnaBridge | 143:86740a56073b | 440 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 441 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 143:86740a56073b | 442 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 143:86740a56073b | 443 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 143:86740a56073b | 444 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 143:86740a56073b | 445 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 143:86740a56073b | 446 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 143:86740a56073b | 447 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 143:86740a56073b | 448 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 143:86740a56073b | 449 | */ |
| AnnaBridge | 143:86740a56073b | 450 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
| AnnaBridge | 143:86740a56073b | 451 | { |
| AnnaBridge | 143:86740a56073b | 452 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
| AnnaBridge | 143:86740a56073b | 453 | } |
| AnnaBridge | 143:86740a56073b | 454 | |
| AnnaBridge | 143:86740a56073b | 455 | /** |
| AnnaBridge | 143:86740a56073b | 456 | * @brief Enable Power Voltage Detector |
| AnnaBridge | 143:86740a56073b | 457 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
| AnnaBridge | 143:86740a56073b | 458 | * @retval None |
| AnnaBridge | 143:86740a56073b | 459 | */ |
| AnnaBridge | 143:86740a56073b | 460 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
| AnnaBridge | 143:86740a56073b | 461 | { |
| AnnaBridge | 143:86740a56073b | 462 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 143:86740a56073b | 463 | } |
| AnnaBridge | 143:86740a56073b | 464 | |
| AnnaBridge | 143:86740a56073b | 465 | /** |
| AnnaBridge | 143:86740a56073b | 466 | * @brief Disable Power Voltage Detector |
| AnnaBridge | 143:86740a56073b | 467 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
| AnnaBridge | 143:86740a56073b | 468 | * @retval None |
| AnnaBridge | 143:86740a56073b | 469 | */ |
| AnnaBridge | 143:86740a56073b | 470 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
| AnnaBridge | 143:86740a56073b | 471 | { |
| AnnaBridge | 143:86740a56073b | 472 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 143:86740a56073b | 473 | } |
| AnnaBridge | 143:86740a56073b | 474 | |
| AnnaBridge | 143:86740a56073b | 475 | /** |
| AnnaBridge | 143:86740a56073b | 476 | * @brief Check if Power Voltage Detector is enabled |
| AnnaBridge | 143:86740a56073b | 477 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
| AnnaBridge | 143:86740a56073b | 478 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 479 | */ |
| AnnaBridge | 143:86740a56073b | 480 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
| AnnaBridge | 143:86740a56073b | 481 | { |
| AnnaBridge | 143:86740a56073b | 482 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
| AnnaBridge | 143:86740a56073b | 483 | } |
| AnnaBridge | 167:84c0a372a020 | 484 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 143:86740a56073b | 485 | |
| AnnaBridge | 143:86740a56073b | 486 | /** |
| AnnaBridge | 143:86740a56073b | 487 | * @brief Enable the WakeUp PINx functionality |
| AnnaBridge | 143:86740a56073b | 488 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 489 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 490 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin |
| AnnaBridge | 143:86740a56073b | 491 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 492 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 143:86740a56073b | 493 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 143:86740a56073b | 494 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 143:86740a56073b | 495 | * |
| AnnaBridge | 143:86740a56073b | 496 | * (*) not available on all devices |
| AnnaBridge | 143:86740a56073b | 497 | * @retval None |
| AnnaBridge | 143:86740a56073b | 498 | */ |
| AnnaBridge | 143:86740a56073b | 499 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 143:86740a56073b | 500 | { |
| AnnaBridge | 143:86740a56073b | 501 | SET_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 143:86740a56073b | 502 | } |
| AnnaBridge | 143:86740a56073b | 503 | |
| AnnaBridge | 143:86740a56073b | 504 | /** |
| AnnaBridge | 143:86740a56073b | 505 | * @brief Disable the WakeUp PINx functionality |
| AnnaBridge | 143:86740a56073b | 506 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 507 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 508 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin |
| AnnaBridge | 143:86740a56073b | 509 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 510 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 143:86740a56073b | 511 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 143:86740a56073b | 512 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 143:86740a56073b | 513 | * |
| AnnaBridge | 143:86740a56073b | 514 | * (*) not available on all devices |
| AnnaBridge | 143:86740a56073b | 515 | * @retval None |
| AnnaBridge | 143:86740a56073b | 516 | */ |
| AnnaBridge | 143:86740a56073b | 517 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 143:86740a56073b | 518 | { |
| AnnaBridge | 143:86740a56073b | 519 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 143:86740a56073b | 520 | } |
| AnnaBridge | 143:86740a56073b | 521 | |
| AnnaBridge | 143:86740a56073b | 522 | /** |
| AnnaBridge | 143:86740a56073b | 523 | * @brief Check if the WakeUp PINx functionality is enabled |
| AnnaBridge | 143:86740a56073b | 524 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 525 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 167:84c0a372a020 | 526 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin |
| AnnaBridge | 143:86740a56073b | 527 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 528 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 143:86740a56073b | 529 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 143:86740a56073b | 530 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 143:86740a56073b | 531 | * |
| AnnaBridge | 143:86740a56073b | 532 | * (*) not available on all devices |
| AnnaBridge | 143:86740a56073b | 533 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 534 | */ |
| AnnaBridge | 143:86740a56073b | 535 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 143:86740a56073b | 536 | { |
| AnnaBridge | 143:86740a56073b | 537 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
| AnnaBridge | 143:86740a56073b | 538 | } |
| AnnaBridge | 143:86740a56073b | 539 | |
| AnnaBridge | 143:86740a56073b | 540 | /** |
| AnnaBridge | 143:86740a56073b | 541 | * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes |
| AnnaBridge | 143:86740a56073b | 542 | * @rmtoll CR ULP LL_PWR_EnableUltraLowPower |
| AnnaBridge | 143:86740a56073b | 543 | * @retval None |
| AnnaBridge | 143:86740a56073b | 544 | */ |
| AnnaBridge | 143:86740a56073b | 545 | __STATIC_INLINE void LL_PWR_EnableUltraLowPower(void) |
| AnnaBridge | 143:86740a56073b | 546 | { |
| AnnaBridge | 143:86740a56073b | 547 | SET_BIT(PWR->CR, PWR_CR_ULP); |
| AnnaBridge | 143:86740a56073b | 548 | } |
| AnnaBridge | 143:86740a56073b | 549 | |
| AnnaBridge | 143:86740a56073b | 550 | /** |
| AnnaBridge | 143:86740a56073b | 551 | * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes |
| AnnaBridge | 143:86740a56073b | 552 | * @rmtoll CR ULP LL_PWR_DisableUltraLowPower |
| AnnaBridge | 143:86740a56073b | 553 | * @retval None |
| AnnaBridge | 143:86740a56073b | 554 | */ |
| AnnaBridge | 143:86740a56073b | 555 | __STATIC_INLINE void LL_PWR_DisableUltraLowPower(void) |
| AnnaBridge | 143:86740a56073b | 556 | { |
| AnnaBridge | 143:86740a56073b | 557 | CLEAR_BIT(PWR->CR, PWR_CR_ULP); |
| AnnaBridge | 143:86740a56073b | 558 | } |
| AnnaBridge | 143:86740a56073b | 559 | |
| AnnaBridge | 143:86740a56073b | 560 | /** |
| AnnaBridge | 143:86740a56073b | 561 | * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled |
| AnnaBridge | 143:86740a56073b | 562 | * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower |
| AnnaBridge | 143:86740a56073b | 563 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 564 | */ |
| AnnaBridge | 143:86740a56073b | 565 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void) |
| AnnaBridge | 143:86740a56073b | 566 | { |
| AnnaBridge | 143:86740a56073b | 567 | return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP)); |
| AnnaBridge | 143:86740a56073b | 568 | } |
| AnnaBridge | 143:86740a56073b | 569 | |
| AnnaBridge | 143:86740a56073b | 570 | /** |
| AnnaBridge | 143:86740a56073b | 571 | * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode |
| AnnaBridge | 143:86740a56073b | 572 | * @rmtoll CR FWU LL_PWR_EnableFastWakeUp |
| AnnaBridge | 143:86740a56073b | 573 | * @note Works in conjunction with ultra low power mode. |
| AnnaBridge | 143:86740a56073b | 574 | * @retval None |
| AnnaBridge | 143:86740a56073b | 575 | */ |
| AnnaBridge | 143:86740a56073b | 576 | __STATIC_INLINE void LL_PWR_EnableFastWakeUp(void) |
| AnnaBridge | 143:86740a56073b | 577 | { |
| AnnaBridge | 143:86740a56073b | 578 | SET_BIT(PWR->CR, PWR_CR_FWU); |
| AnnaBridge | 143:86740a56073b | 579 | } |
| AnnaBridge | 143:86740a56073b | 580 | |
| AnnaBridge | 143:86740a56073b | 581 | /** |
| AnnaBridge | 143:86740a56073b | 582 | * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode |
| AnnaBridge | 143:86740a56073b | 583 | * @rmtoll CR FWU LL_PWR_DisableFastWakeUp |
| AnnaBridge | 143:86740a56073b | 584 | * @note Works in conjunction with ultra low power mode. |
| AnnaBridge | 143:86740a56073b | 585 | * @retval None |
| AnnaBridge | 143:86740a56073b | 586 | */ |
| AnnaBridge | 143:86740a56073b | 587 | __STATIC_INLINE void LL_PWR_DisableFastWakeUp(void) |
| AnnaBridge | 143:86740a56073b | 588 | { |
| AnnaBridge | 143:86740a56073b | 589 | CLEAR_BIT(PWR->CR, PWR_CR_FWU); |
| AnnaBridge | 143:86740a56073b | 590 | } |
| AnnaBridge | 143:86740a56073b | 591 | |
| AnnaBridge | 143:86740a56073b | 592 | /** |
| AnnaBridge | 143:86740a56073b | 593 | * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored |
| AnnaBridge | 143:86740a56073b | 594 | * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp |
| AnnaBridge | 143:86740a56073b | 595 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 596 | */ |
| AnnaBridge | 143:86740a56073b | 597 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void) |
| AnnaBridge | 143:86740a56073b | 598 | { |
| AnnaBridge | 143:86740a56073b | 599 | return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU)); |
| AnnaBridge | 143:86740a56073b | 600 | } |
| AnnaBridge | 143:86740a56073b | 601 | |
| AnnaBridge | 143:86740a56073b | 602 | /** |
| AnnaBridge | 143:86740a56073b | 603 | * @brief Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode |
| AnnaBridge | 143:86740a56073b | 604 | * @rmtoll CR DS_EE_KOFF LL_PWR_EnableNVMKeptOff |
| AnnaBridge | 143:86740a56073b | 605 | * @note When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register |
| AnnaBridge | 143:86740a56073b | 606 | * is also set, the Flash memory will not be woken up when exiting from deepsleep mode. |
| AnnaBridge | 143:86740a56073b | 607 | * When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set) |
| AnnaBridge | 143:86740a56073b | 608 | * @retval None |
| AnnaBridge | 143:86740a56073b | 609 | */ |
| AnnaBridge | 143:86740a56073b | 610 | __STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void) |
| AnnaBridge | 143:86740a56073b | 611 | { |
| AnnaBridge | 143:86740a56073b | 612 | SET_BIT(PWR->CR, PWR_CR_DSEEKOFF); |
| AnnaBridge | 143:86740a56073b | 613 | } |
| AnnaBridge | 143:86740a56073b | 614 | |
| AnnaBridge | 143:86740a56073b | 615 | /** |
| AnnaBridge | 143:86740a56073b | 616 | * @brief Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode |
| AnnaBridge | 143:86740a56073b | 617 | * @rmtoll CR DS_EE_KOFF LL_PWR_DisableNVMKeptOff |
| AnnaBridge | 143:86740a56073b | 618 | * @note When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set |
| AnnaBridge | 143:86740a56073b | 619 | * @retval None |
| AnnaBridge | 143:86740a56073b | 620 | */ |
| AnnaBridge | 143:86740a56073b | 621 | __STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void) |
| AnnaBridge | 143:86740a56073b | 622 | { |
| AnnaBridge | 143:86740a56073b | 623 | CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF); |
| AnnaBridge | 143:86740a56073b | 624 | } |
| AnnaBridge | 143:86740a56073b | 625 | |
| AnnaBridge | 143:86740a56073b | 626 | /** |
| AnnaBridge | 143:86740a56073b | 627 | * @brief Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled |
| AnnaBridge | 143:86740a56073b | 628 | * @rmtoll CR DS_EE_KOFF LL_PWR_IsEnabledNVMKeptOff |
| AnnaBridge | 143:86740a56073b | 629 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 630 | */ |
| AnnaBridge | 143:86740a56073b | 631 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void) |
| AnnaBridge | 143:86740a56073b | 632 | { |
| AnnaBridge | 143:86740a56073b | 633 | return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF)); |
| AnnaBridge | 143:86740a56073b | 634 | } |
| AnnaBridge | 143:86740a56073b | 635 | |
| AnnaBridge | 143:86740a56073b | 636 | /** |
| AnnaBridge | 143:86740a56073b | 637 | * @} |
| AnnaBridge | 143:86740a56073b | 638 | */ |
| AnnaBridge | 143:86740a56073b | 639 | |
| AnnaBridge | 143:86740a56073b | 640 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 143:86740a56073b | 641 | * @{ |
| AnnaBridge | 143:86740a56073b | 642 | */ |
| AnnaBridge | 143:86740a56073b | 643 | |
| AnnaBridge | 143:86740a56073b | 644 | /** |
| AnnaBridge | 143:86740a56073b | 645 | * @brief Get Wake-up Flag |
| AnnaBridge | 143:86740a56073b | 646 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
| AnnaBridge | 143:86740a56073b | 647 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 648 | */ |
| AnnaBridge | 143:86740a56073b | 649 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
| AnnaBridge | 143:86740a56073b | 650 | { |
| AnnaBridge | 143:86740a56073b | 651 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
| AnnaBridge | 143:86740a56073b | 652 | } |
| AnnaBridge | 143:86740a56073b | 653 | |
| AnnaBridge | 143:86740a56073b | 654 | /** |
| AnnaBridge | 143:86740a56073b | 655 | * @brief Get Standby Flag |
| AnnaBridge | 143:86740a56073b | 656 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
| AnnaBridge | 143:86740a56073b | 657 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 658 | */ |
| AnnaBridge | 143:86740a56073b | 659 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
| AnnaBridge | 143:86740a56073b | 660 | { |
| AnnaBridge | 143:86740a56073b | 661 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
| AnnaBridge | 143:86740a56073b | 662 | } |
| AnnaBridge | 143:86740a56073b | 663 | |
| AnnaBridge | 167:84c0a372a020 | 664 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 143:86740a56073b | 665 | /** |
| AnnaBridge | 143:86740a56073b | 666 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
| AnnaBridge | 143:86740a56073b | 667 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
| AnnaBridge | 143:86740a56073b | 668 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 669 | */ |
| AnnaBridge | 143:86740a56073b | 670 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
| AnnaBridge | 143:86740a56073b | 671 | { |
| AnnaBridge | 143:86740a56073b | 672 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
| AnnaBridge | 143:86740a56073b | 673 | } |
| AnnaBridge | 167:84c0a372a020 | 674 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 143:86740a56073b | 675 | |
| AnnaBridge | 167:84c0a372a020 | 676 | #if defined(PWR_CSR_VREFINTRDYF) |
| AnnaBridge | 143:86740a56073b | 677 | /** |
| AnnaBridge | 143:86740a56073b | 678 | * @brief Get Internal Reference VrefInt Flag |
| AnnaBridge | 143:86740a56073b | 679 | * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY |
| AnnaBridge | 143:86740a56073b | 680 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 681 | */ |
| AnnaBridge | 143:86740a56073b | 682 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) |
| AnnaBridge | 143:86740a56073b | 683 | { |
| AnnaBridge | 143:86740a56073b | 684 | return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); |
| AnnaBridge | 143:86740a56073b | 685 | } |
| AnnaBridge | 167:84c0a372a020 | 686 | #endif /* PWR_CSR_VREFINTRDYF */ |
| AnnaBridge | 143:86740a56073b | 687 | /** |
| AnnaBridge | 143:86740a56073b | 688 | * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level |
| AnnaBridge | 143:86740a56073b | 689 | * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOSF |
| AnnaBridge | 143:86740a56073b | 690 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 691 | */ |
| AnnaBridge | 143:86740a56073b | 692 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void) |
| AnnaBridge | 143:86740a56073b | 693 | { |
| AnnaBridge | 167:84c0a372a020 | 694 | return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); |
| AnnaBridge | 143:86740a56073b | 695 | } |
| AnnaBridge | 143:86740a56073b | 696 | /** |
| AnnaBridge | 143:86740a56073b | 697 | * @brief Indicate whether the regulator is ready in main mode or is in low-power mode |
| AnnaBridge | 143:86740a56073b | 698 | * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF |
| AnnaBridge | 143:86740a56073b | 699 | * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. |
| AnnaBridge | 143:86740a56073b | 700 | * @retval State of bit (1 or 0). |
| AnnaBridge | 143:86740a56073b | 701 | */ |
| AnnaBridge | 143:86740a56073b | 702 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) |
| AnnaBridge | 143:86740a56073b | 703 | { |
| AnnaBridge | 143:86740a56073b | 704 | return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF)); |
| AnnaBridge | 143:86740a56073b | 705 | } |
| AnnaBridge | 143:86740a56073b | 706 | /** |
| AnnaBridge | 143:86740a56073b | 707 | * @brief Clear Standby Flag |
| AnnaBridge | 143:86740a56073b | 708 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
| AnnaBridge | 143:86740a56073b | 709 | * @retval None |
| AnnaBridge | 143:86740a56073b | 710 | */ |
| AnnaBridge | 143:86740a56073b | 711 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
| AnnaBridge | 143:86740a56073b | 712 | { |
| AnnaBridge | 143:86740a56073b | 713 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
| AnnaBridge | 143:86740a56073b | 714 | } |
| AnnaBridge | 143:86740a56073b | 715 | |
| AnnaBridge | 143:86740a56073b | 716 | /** |
| AnnaBridge | 143:86740a56073b | 717 | * @brief Clear Wake-up Flags |
| AnnaBridge | 143:86740a56073b | 718 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
| AnnaBridge | 143:86740a56073b | 719 | * @retval None |
| AnnaBridge | 143:86740a56073b | 720 | */ |
| AnnaBridge | 143:86740a56073b | 721 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
| AnnaBridge | 143:86740a56073b | 722 | { |
| AnnaBridge | 143:86740a56073b | 723 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
| AnnaBridge | 143:86740a56073b | 724 | } |
| AnnaBridge | 143:86740a56073b | 725 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 143:86740a56073b | 726 | /** @defgroup PWR_LL_EF_Init De-initialization function |
| AnnaBridge | 143:86740a56073b | 727 | * @{ |
| AnnaBridge | 143:86740a56073b | 728 | */ |
| AnnaBridge | 143:86740a56073b | 729 | ErrorStatus LL_PWR_DeInit(void); |
| AnnaBridge | 143:86740a56073b | 730 | /** |
| AnnaBridge | 143:86740a56073b | 731 | * @} |
| AnnaBridge | 143:86740a56073b | 732 | */ |
| AnnaBridge | 143:86740a56073b | 733 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 143:86740a56073b | 734 | |
| AnnaBridge | 143:86740a56073b | 735 | /** |
| AnnaBridge | 143:86740a56073b | 736 | * @} |
| AnnaBridge | 143:86740a56073b | 737 | */ |
| AnnaBridge | 143:86740a56073b | 738 | |
| AnnaBridge | 143:86740a56073b | 739 | /** |
| AnnaBridge | 143:86740a56073b | 740 | * @} |
| AnnaBridge | 143:86740a56073b | 741 | */ |
| AnnaBridge | 143:86740a56073b | 742 | |
| AnnaBridge | 143:86740a56073b | 743 | /** |
| AnnaBridge | 143:86740a56073b | 744 | * @} |
| AnnaBridge | 143:86740a56073b | 745 | */ |
| AnnaBridge | 143:86740a56073b | 746 | |
| AnnaBridge | 143:86740a56073b | 747 | #endif /* defined(PWR) */ |
| AnnaBridge | 143:86740a56073b | 748 | |
| AnnaBridge | 143:86740a56073b | 749 | /** |
| AnnaBridge | 143:86740a56073b | 750 | * @} |
| AnnaBridge | 143:86740a56073b | 751 | */ |
| AnnaBridge | 143:86740a56073b | 752 | |
| AnnaBridge | 143:86740a56073b | 753 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 754 | } |
| AnnaBridge | 143:86740a56073b | 755 | #endif |
| AnnaBridge | 143:86740a56073b | 756 | |
| AnnaBridge | 143:86740a56073b | 757 | #endif /* __STM32L0xx_LL_PWR_H */ |
| AnnaBridge | 143:86740a56073b | 758 | |
| AnnaBridge | 143:86740a56073b | 759 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
