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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_dma.h@167:84c0a372a020

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	157:e7ca05fa8600	1	/**
AnnaBridge	157:e7ca05fa8600	2	******************************************************************************
AnnaBridge	157:e7ca05fa8600	3	* @file stm32l0xx_ll_dma.h
AnnaBridge	157:e7ca05fa8600	4	* @author MCD Application Team
AnnaBridge	157:e7ca05fa8600	5	* @brief Header file of DMA LL module.
AnnaBridge	157:e7ca05fa8600	6	******************************************************************************
AnnaBridge	157:e7ca05fa8600	7	* @attention
AnnaBridge	157:e7ca05fa8600	8	*
AnnaBridge	157:e7ca05fa8600	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	157:e7ca05fa8600	10	*
AnnaBridge	157:e7ca05fa8600	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	157:e7ca05fa8600	12	* are permitted provided that the following conditions are met:
AnnaBridge	157:e7ca05fa8600	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	157:e7ca05fa8600	14	* this list of conditions and the following disclaimer.
AnnaBridge	157:e7ca05fa8600	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	157:e7ca05fa8600	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	157:e7ca05fa8600	17	* and/or other materials provided with the distribution.
AnnaBridge	157:e7ca05fa8600	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	157:e7ca05fa8600	19	* may be used to endorse or promote products derived from this software
AnnaBridge	157:e7ca05fa8600	20	* without specific prior written permission.
AnnaBridge	157:e7ca05fa8600	21	*
AnnaBridge	157:e7ca05fa8600	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	157:e7ca05fa8600	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	157:e7ca05fa8600	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	157:e7ca05fa8600	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	157:e7ca05fa8600	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	157:e7ca05fa8600	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	157:e7ca05fa8600	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	157:e7ca05fa8600	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	157:e7ca05fa8600	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	157:e7ca05fa8600	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	157:e7ca05fa8600	32	*
AnnaBridge	157:e7ca05fa8600	33	******************************************************************************
AnnaBridge	157:e7ca05fa8600	34	*/
AnnaBridge	157:e7ca05fa8600	35
AnnaBridge	157:e7ca05fa8600	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	157:e7ca05fa8600	37	#ifndef __STM32L0xx_LL_DMA_H
AnnaBridge	157:e7ca05fa8600	38	#define __STM32L0xx_LL_DMA_H
AnnaBridge	157:e7ca05fa8600	39
AnnaBridge	157:e7ca05fa8600	40	#ifdef __cplusplus
AnnaBridge	157:e7ca05fa8600	41	extern "C" {
AnnaBridge	157:e7ca05fa8600	42	#endif
AnnaBridge	157:e7ca05fa8600	43
AnnaBridge	157:e7ca05fa8600	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	45	#include "stm32l0xx.h"
AnnaBridge	157:e7ca05fa8600	46
AnnaBridge	157:e7ca05fa8600	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	157:e7ca05fa8600	48	* @{
AnnaBridge	157:e7ca05fa8600	49	*/
AnnaBridge	157:e7ca05fa8600	50
AnnaBridge	157:e7ca05fa8600	51	#if defined (DMA1)
AnnaBridge	157:e7ca05fa8600	52
AnnaBridge	157:e7ca05fa8600	53	/** @defgroup DMA_LL DMA
AnnaBridge	157:e7ca05fa8600	54	* @{
AnnaBridge	157:e7ca05fa8600	55	*/
AnnaBridge	157:e7ca05fa8600	56
AnnaBridge	157:e7ca05fa8600	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	157:e7ca05fa8600	60	* @{
AnnaBridge	157:e7ca05fa8600	61	*/
AnnaBridge	157:e7ca05fa8600	62	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	157:e7ca05fa8600	63	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	157:e7ca05fa8600	64	{
AnnaBridge	157:e7ca05fa8600	65	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	66	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	67	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	68	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	69	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	70	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	71	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	157:e7ca05fa8600	72	#endif /DMA1_Channel6/
AnnaBridge	157:e7ca05fa8600	73	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	74	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	157:e7ca05fa8600	75	#endif /DMA1_Channel7/
AnnaBridge	157:e7ca05fa8600	76	};
AnnaBridge	157:e7ca05fa8600	77	/**
AnnaBridge	157:e7ca05fa8600	78	* @}
AnnaBridge	157:e7ca05fa8600	79	*/
AnnaBridge	157:e7ca05fa8600	80
AnnaBridge	157:e7ca05fa8600	81	/* Private constants ---------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	82	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	157:e7ca05fa8600	83	* @{
AnnaBridge	157:e7ca05fa8600	84	*/
AnnaBridge	157:e7ca05fa8600	85	/* Define used to get CSELR register offset */
AnnaBridge	157:e7ca05fa8600	86	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	157:e7ca05fa8600	87
AnnaBridge	157:e7ca05fa8600	88	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	157:e7ca05fa8600	89	#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
AnnaBridge	157:e7ca05fa8600	90	/**
AnnaBridge	157:e7ca05fa8600	91	* @}
AnnaBridge	157:e7ca05fa8600	92	*/
AnnaBridge	157:e7ca05fa8600	93
AnnaBridge	157:e7ca05fa8600	94	/* Private macros ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	95	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	96	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	157:e7ca05fa8600	97	* @{
AnnaBridge	157:e7ca05fa8600	98	*/
AnnaBridge	157:e7ca05fa8600	99	/**
AnnaBridge	157:e7ca05fa8600	100	* @}
AnnaBridge	157:e7ca05fa8600	101	*/
AnnaBridge	157:e7ca05fa8600	102	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	157:e7ca05fa8600	103
AnnaBridge	157:e7ca05fa8600	104	/* Exported types ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	105	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	106	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	157:e7ca05fa8600	107	* @{
AnnaBridge	157:e7ca05fa8600	108	*/
AnnaBridge	157:e7ca05fa8600	109	typedef struct
AnnaBridge	157:e7ca05fa8600	110	{
AnnaBridge	157:e7ca05fa8600	111	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	157:e7ca05fa8600	112	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	157:e7ca05fa8600	113
AnnaBridge	157:e7ca05fa8600	114	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	157:e7ca05fa8600	115
AnnaBridge	157:e7ca05fa8600	116	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	157:e7ca05fa8600	117	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	157:e7ca05fa8600	118
AnnaBridge	157:e7ca05fa8600	119	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	157:e7ca05fa8600	120
AnnaBridge	157:e7ca05fa8600	121	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	157:e7ca05fa8600	122	from memory to memory or from peripheral to memory.
AnnaBridge	157:e7ca05fa8600	123	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	157:e7ca05fa8600	124
AnnaBridge	157:e7ca05fa8600	125	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	157:e7ca05fa8600	126
AnnaBridge	157:e7ca05fa8600	127	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	157:e7ca05fa8600	128	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	157:e7ca05fa8600	129	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	157:e7ca05fa8600	130	data transfer direction is configured on the selected Channel
AnnaBridge	157:e7ca05fa8600	131
AnnaBridge	157:e7ca05fa8600	132	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	157:e7ca05fa8600	133
AnnaBridge	157:e7ca05fa8600	134	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	157:e7ca05fa8600	135	is incremented or not.
AnnaBridge	157:e7ca05fa8600	136	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	157:e7ca05fa8600	137
AnnaBridge	157:e7ca05fa8600	138	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	157:e7ca05fa8600	139
AnnaBridge	157:e7ca05fa8600	140	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	157:e7ca05fa8600	141	is incremented or not.
AnnaBridge	157:e7ca05fa8600	142	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	157:e7ca05fa8600	143
AnnaBridge	157:e7ca05fa8600	144	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	157:e7ca05fa8600	145
AnnaBridge	157:e7ca05fa8600	146	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	157:e7ca05fa8600	147	in case of memory to memory transfer direction.
AnnaBridge	157:e7ca05fa8600	148	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	157:e7ca05fa8600	149
AnnaBridge	157:e7ca05fa8600	150	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	157:e7ca05fa8600	151
AnnaBridge	157:e7ca05fa8600	152	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	157:e7ca05fa8600	153	in case of memory to memory transfer direction.
AnnaBridge	157:e7ca05fa8600	154	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	157:e7ca05fa8600	155
AnnaBridge	157:e7ca05fa8600	156	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	157:e7ca05fa8600	157
AnnaBridge	157:e7ca05fa8600	158	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	157:e7ca05fa8600	159	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	157:e7ca05fa8600	160	or MemorySize parameters depending in the transfer direction.
AnnaBridge	157:e7ca05fa8600	161	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	157:e7ca05fa8600	162
AnnaBridge	157:e7ca05fa8600	163	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	157:e7ca05fa8600	164
AnnaBridge	157:e7ca05fa8600	165	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	157:e7ca05fa8600	166	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	157:e7ca05fa8600	167
AnnaBridge	157:e7ca05fa8600	168	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	157:e7ca05fa8600	169
AnnaBridge	157:e7ca05fa8600	170	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	157:e7ca05fa8600	171	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	157:e7ca05fa8600	172
AnnaBridge	157:e7ca05fa8600	173	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	157:e7ca05fa8600	174
AnnaBridge	157:e7ca05fa8600	175	} LL_DMA_InitTypeDef;
AnnaBridge	157:e7ca05fa8600	176	/**
AnnaBridge	157:e7ca05fa8600	177	* @}
AnnaBridge	157:e7ca05fa8600	178	*/
AnnaBridge	157:e7ca05fa8600	179	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	157:e7ca05fa8600	180
AnnaBridge	157:e7ca05fa8600	181	/* Exported constants --------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	182	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	157:e7ca05fa8600	183	* @{
AnnaBridge	157:e7ca05fa8600	184	*/
AnnaBridge	157:e7ca05fa8600	185	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	157:e7ca05fa8600	186	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	157:e7ca05fa8600	187	* @{
AnnaBridge	157:e7ca05fa8600	188	*/
AnnaBridge	157:e7ca05fa8600	189	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	157:e7ca05fa8600	190	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	191	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	157:e7ca05fa8600	192	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	157:e7ca05fa8600	193	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	157:e7ca05fa8600	194	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	195	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	157:e7ca05fa8600	196	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	157:e7ca05fa8600	197	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	157:e7ca05fa8600	198	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	199	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	157:e7ca05fa8600	200	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	157:e7ca05fa8600	201	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	157:e7ca05fa8600	202	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	203	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	157:e7ca05fa8600	204	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	157:e7ca05fa8600	205	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	157:e7ca05fa8600	206	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	207	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	157:e7ca05fa8600	208	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	157:e7ca05fa8600	209	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	210	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	157:e7ca05fa8600	211	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	212	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	157:e7ca05fa8600	213	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	157:e7ca05fa8600	214	#endif
AnnaBridge	157:e7ca05fa8600	215	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	216	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	157:e7ca05fa8600	217	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	218	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	157:e7ca05fa8600	219	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	157:e7ca05fa8600	220	#endif
AnnaBridge	157:e7ca05fa8600	221	/**
AnnaBridge	157:e7ca05fa8600	222	* @}
AnnaBridge	157:e7ca05fa8600	223	*/
AnnaBridge	157:e7ca05fa8600	224
AnnaBridge	157:e7ca05fa8600	225	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	157:e7ca05fa8600	226	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	157:e7ca05fa8600	227	* @{
AnnaBridge	157:e7ca05fa8600	228	*/
AnnaBridge	157:e7ca05fa8600	229	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	157:e7ca05fa8600	230	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	231	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	157:e7ca05fa8600	232	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	157:e7ca05fa8600	233	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	157:e7ca05fa8600	234	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	235	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	157:e7ca05fa8600	236	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	157:e7ca05fa8600	237	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	157:e7ca05fa8600	238	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	239	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	157:e7ca05fa8600	240	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	157:e7ca05fa8600	241	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	157:e7ca05fa8600	242	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	243	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	157:e7ca05fa8600	244	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	157:e7ca05fa8600	245	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	157:e7ca05fa8600	246	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	247	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	157:e7ca05fa8600	248	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	157:e7ca05fa8600	249	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	250	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	157:e7ca05fa8600	251	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	252	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	157:e7ca05fa8600	253	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	157:e7ca05fa8600	254	#endif
AnnaBridge	157:e7ca05fa8600	255	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	256	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	157:e7ca05fa8600	257	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	157:e7ca05fa8600	258	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	157:e7ca05fa8600	259	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	157:e7ca05fa8600	260	#endif
AnnaBridge	157:e7ca05fa8600	261	/**
AnnaBridge	157:e7ca05fa8600	262	* @}
AnnaBridge	157:e7ca05fa8600	263	*/
AnnaBridge	157:e7ca05fa8600	264
AnnaBridge	157:e7ca05fa8600	265	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	157:e7ca05fa8600	266	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	157:e7ca05fa8600	267	* @{
AnnaBridge	157:e7ca05fa8600	268	*/
AnnaBridge	157:e7ca05fa8600	269	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	157:e7ca05fa8600	270	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	157:e7ca05fa8600	271	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	157:e7ca05fa8600	272	/**
AnnaBridge	157:e7ca05fa8600	273	* @}
AnnaBridge	157:e7ca05fa8600	274	*/
AnnaBridge	157:e7ca05fa8600	275
AnnaBridge	157:e7ca05fa8600	276	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	157:e7ca05fa8600	277	* @{
AnnaBridge	157:e7ca05fa8600	278	*/
AnnaBridge	157:e7ca05fa8600	279	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
AnnaBridge	157:e7ca05fa8600	280	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
AnnaBridge	157:e7ca05fa8600	281	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
AnnaBridge	157:e7ca05fa8600	282	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
AnnaBridge	157:e7ca05fa8600	283	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
AnnaBridge	157:e7ca05fa8600	284	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	285	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
AnnaBridge	157:e7ca05fa8600	286	#endif
AnnaBridge	157:e7ca05fa8600	287	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	288	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
AnnaBridge	157:e7ca05fa8600	289	#endif
AnnaBridge	157:e7ca05fa8600	290	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	291	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	157:e7ca05fa8600	292	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	157:e7ca05fa8600	293	/**
AnnaBridge	157:e7ca05fa8600	294	* @}
AnnaBridge	157:e7ca05fa8600	295	*/
AnnaBridge	157:e7ca05fa8600	296
AnnaBridge	157:e7ca05fa8600	297	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	157:e7ca05fa8600	298	* @{
AnnaBridge	157:e7ca05fa8600	299	*/
AnnaBridge	157:e7ca05fa8600	300	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
AnnaBridge	157:e7ca05fa8600	301	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	157:e7ca05fa8600	302	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	157:e7ca05fa8600	303	/**
AnnaBridge	157:e7ca05fa8600	304	* @}
AnnaBridge	157:e7ca05fa8600	305	*/
AnnaBridge	157:e7ca05fa8600	306
AnnaBridge	157:e7ca05fa8600	307	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	157:e7ca05fa8600	308	* @{
AnnaBridge	157:e7ca05fa8600	309	*/
AnnaBridge	157:e7ca05fa8600	310	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
AnnaBridge	157:e7ca05fa8600	311	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	157:e7ca05fa8600	312	/**
AnnaBridge	157:e7ca05fa8600	313	* @}
AnnaBridge	157:e7ca05fa8600	314	*/
AnnaBridge	157:e7ca05fa8600	315
AnnaBridge	157:e7ca05fa8600	316	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	157:e7ca05fa8600	317	* @{
AnnaBridge	157:e7ca05fa8600	318	*/
AnnaBridge	157:e7ca05fa8600	319	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	157:e7ca05fa8600	320	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
AnnaBridge	157:e7ca05fa8600	321	/**
AnnaBridge	157:e7ca05fa8600	322	* @}
AnnaBridge	157:e7ca05fa8600	323	*/
AnnaBridge	157:e7ca05fa8600	324
AnnaBridge	157:e7ca05fa8600	325	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	157:e7ca05fa8600	326	* @{
AnnaBridge	157:e7ca05fa8600	327	*/
AnnaBridge	157:e7ca05fa8600	328	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	157:e7ca05fa8600	329	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
AnnaBridge	157:e7ca05fa8600	330	/**
AnnaBridge	157:e7ca05fa8600	331	* @}
AnnaBridge	157:e7ca05fa8600	332	*/
AnnaBridge	157:e7ca05fa8600	333
AnnaBridge	157:e7ca05fa8600	334	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	157:e7ca05fa8600	335	* @{
AnnaBridge	157:e7ca05fa8600	336	*/
AnnaBridge	157:e7ca05fa8600	337	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
AnnaBridge	157:e7ca05fa8600	338	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	157:e7ca05fa8600	339	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	157:e7ca05fa8600	340	/**
AnnaBridge	157:e7ca05fa8600	341	* @}
AnnaBridge	157:e7ca05fa8600	342	*/
AnnaBridge	157:e7ca05fa8600	343
AnnaBridge	157:e7ca05fa8600	344	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	157:e7ca05fa8600	345	* @{
AnnaBridge	157:e7ca05fa8600	346	*/
AnnaBridge	157:e7ca05fa8600	347	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
AnnaBridge	157:e7ca05fa8600	348	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	157:e7ca05fa8600	349	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	157:e7ca05fa8600	350	/**
AnnaBridge	157:e7ca05fa8600	351	* @}
AnnaBridge	157:e7ca05fa8600	352	*/
AnnaBridge	157:e7ca05fa8600	353
AnnaBridge	157:e7ca05fa8600	354	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	157:e7ca05fa8600	355	* @{
AnnaBridge	157:e7ca05fa8600	356	*/
AnnaBridge	157:e7ca05fa8600	357	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
AnnaBridge	157:e7ca05fa8600	358	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	157:e7ca05fa8600	359	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	157:e7ca05fa8600	360	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	157:e7ca05fa8600	361	/**
AnnaBridge	157:e7ca05fa8600	362	* @}
AnnaBridge	157:e7ca05fa8600	363	*/
AnnaBridge	157:e7ca05fa8600	364
AnnaBridge	157:e7ca05fa8600	365	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	157:e7ca05fa8600	366	* @{
AnnaBridge	157:e7ca05fa8600	367	*/
AnnaBridge	157:e7ca05fa8600	368	#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /!< DMA peripheral request 0 /
AnnaBridge	157:e7ca05fa8600	369	#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /!< DMA peripheral request 1 /
AnnaBridge	157:e7ca05fa8600	370	#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /!< DMA peripheral request 2 /
AnnaBridge	157:e7ca05fa8600	371	#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /!< DMA peripheral request 3 /
AnnaBridge	157:e7ca05fa8600	372	#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /!< DMA peripheral request 4 /
AnnaBridge	157:e7ca05fa8600	373	#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /!< DMA peripheral request 5 /
AnnaBridge	157:e7ca05fa8600	374	#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /!< DMA peripheral request 6 /
AnnaBridge	157:e7ca05fa8600	375	#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /!< DMA peripheral request 7 /
AnnaBridge	157:e7ca05fa8600	376	#define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /!< DMA peripheral request 8 /
AnnaBridge	157:e7ca05fa8600	377	#define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /!< DMA peripheral request 9 /
AnnaBridge	157:e7ca05fa8600	378	#define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /!< DMA peripheral request 10 /
AnnaBridge	157:e7ca05fa8600	379	#define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /!< DMA peripheral request 11 /
AnnaBridge	157:e7ca05fa8600	380	#define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /!< DMA peripheral request 12 /
AnnaBridge	157:e7ca05fa8600	381	#define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /!< DMA peripheral request 13 /
AnnaBridge	157:e7ca05fa8600	382	#define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /!< DMA peripheral request 14 /
AnnaBridge	157:e7ca05fa8600	383	#define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /!< DMA peripheral request 15 /
AnnaBridge	157:e7ca05fa8600	384	/**
AnnaBridge	157:e7ca05fa8600	385	* @}
AnnaBridge	157:e7ca05fa8600	386	*/
AnnaBridge	157:e7ca05fa8600	387
AnnaBridge	157:e7ca05fa8600	388	/**
AnnaBridge	157:e7ca05fa8600	389	* @}
AnnaBridge	157:e7ca05fa8600	390	*/
AnnaBridge	157:e7ca05fa8600	391
AnnaBridge	157:e7ca05fa8600	392	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	393	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	157:e7ca05fa8600	394	* @{
AnnaBridge	157:e7ca05fa8600	395	*/
AnnaBridge	157:e7ca05fa8600	396
AnnaBridge	157:e7ca05fa8600	397	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	157:e7ca05fa8600	398	* @{
AnnaBridge	157:e7ca05fa8600	399	*/
AnnaBridge	157:e7ca05fa8600	400	/**
AnnaBridge	157:e7ca05fa8600	401	* @brief Write a value in DMA register
AnnaBridge	157:e7ca05fa8600	402	* @param __INSTANCE__ DMA Instance
AnnaBridge	157:e7ca05fa8600	403	* @param __REG__ Register to be written
AnnaBridge	157:e7ca05fa8600	404	* @param __VALUE__ Value to be written in the register
AnnaBridge	157:e7ca05fa8600	405	* @retval None
AnnaBridge	157:e7ca05fa8600	406	*/
AnnaBridge	157:e7ca05fa8600	407	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	157:e7ca05fa8600	408
AnnaBridge	157:e7ca05fa8600	409	/**
AnnaBridge	157:e7ca05fa8600	410	* @brief Read a value in DMA register
AnnaBridge	157:e7ca05fa8600	411	* @param __INSTANCE__ DMA Instance
AnnaBridge	157:e7ca05fa8600	412	* @param __REG__ Register to be read
AnnaBridge	157:e7ca05fa8600	413	* @retval Register value
AnnaBridge	157:e7ca05fa8600	414	*/
AnnaBridge	157:e7ca05fa8600	415	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	157:e7ca05fa8600	416	/**
AnnaBridge	157:e7ca05fa8600	417	* @}
AnnaBridge	157:e7ca05fa8600	418	*/
AnnaBridge	157:e7ca05fa8600	419
AnnaBridge	157:e7ca05fa8600	420	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	157:e7ca05fa8600	421	* @{
AnnaBridge	157:e7ca05fa8600	422	*/
AnnaBridge	157:e7ca05fa8600	423	/**
AnnaBridge	157:e7ca05fa8600	424	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	157:e7ca05fa8600	425	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	157:e7ca05fa8600	426	* @retval DMAx
AnnaBridge	157:e7ca05fa8600	427	*/
AnnaBridge	157:e7ca05fa8600	428	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	157:e7ca05fa8600	429
AnnaBridge	157:e7ca05fa8600	430	/**
AnnaBridge	157:e7ca05fa8600	431	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	157:e7ca05fa8600	432	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	157:e7ca05fa8600	433	* @retval LL_DMA_CHANNEL_y
AnnaBridge	157:e7ca05fa8600	434	*/
AnnaBridge	157:e7ca05fa8600	435	#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	436	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	157:e7ca05fa8600	437	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	157:e7ca05fa8600	438	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	157:e7ca05fa8600	439	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	157:e7ca05fa8600	440	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	157:e7ca05fa8600	441	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	157:e7ca05fa8600	442	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	157:e7ca05fa8600	443	LL_DMA_CHANNEL_7)
AnnaBridge	157:e7ca05fa8600	444	#elif defined (DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	445	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	157:e7ca05fa8600	446	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	157:e7ca05fa8600	447	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	157:e7ca05fa8600	448	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	157:e7ca05fa8600	449	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	157:e7ca05fa8600	450	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	157:e7ca05fa8600	451	LL_DMA_CHANNEL_6)
AnnaBridge	157:e7ca05fa8600	452	#else
AnnaBridge	157:e7ca05fa8600	453	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	157:e7ca05fa8600	454	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	157:e7ca05fa8600	455	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	157:e7ca05fa8600	456	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	157:e7ca05fa8600	457	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	157:e7ca05fa8600	458	LL_DMA_CHANNEL_5)
AnnaBridge	157:e7ca05fa8600	459	#endif /* DMA1_Channel6 && DMA1_Channel7 */
AnnaBridge	157:e7ca05fa8600	460
AnnaBridge	157:e7ca05fa8600	461	/**
AnnaBridge	157:e7ca05fa8600	462	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	157:e7ca05fa8600	463	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	157:e7ca05fa8600	464	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	157:e7ca05fa8600	465	* @retval DMAx_Channely
AnnaBridge	157:e7ca05fa8600	466	*/
AnnaBridge	157:e7ca05fa8600	467	#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	468	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	157:e7ca05fa8600	469	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	157:e7ca05fa8600	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	157:e7ca05fa8600	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	157:e7ca05fa8600	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	157:e7ca05fa8600	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	157:e7ca05fa8600	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	157:e7ca05fa8600	475	DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	476	#elif defined (DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	477	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	157:e7ca05fa8600	478	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	157:e7ca05fa8600	479	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	157:e7ca05fa8600	480	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	157:e7ca05fa8600	481	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	157:e7ca05fa8600	482	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	157:e7ca05fa8600	483	DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	484	#else
AnnaBridge	157:e7ca05fa8600	485	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	157:e7ca05fa8600	486	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	157:e7ca05fa8600	487	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	157:e7ca05fa8600	488	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	157:e7ca05fa8600	489	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	157:e7ca05fa8600	490	DMA1_Channel5)
AnnaBridge	157:e7ca05fa8600	491	#endif /* DMA1_Channel6 && DMA1_Channel7 */
AnnaBridge	157:e7ca05fa8600	492
AnnaBridge	157:e7ca05fa8600	493	/**
AnnaBridge	157:e7ca05fa8600	494	* @}
AnnaBridge	157:e7ca05fa8600	495	*/
AnnaBridge	157:e7ca05fa8600	496
AnnaBridge	157:e7ca05fa8600	497	/**
AnnaBridge	157:e7ca05fa8600	498	* @}
AnnaBridge	157:e7ca05fa8600	499	*/
AnnaBridge	157:e7ca05fa8600	500
AnnaBridge	157:e7ca05fa8600	501	/* Exported functions --------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	502	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	157:e7ca05fa8600	503	* @{
AnnaBridge	157:e7ca05fa8600	504	*/
AnnaBridge	157:e7ca05fa8600	505
AnnaBridge	157:e7ca05fa8600	506	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	157:e7ca05fa8600	507	* @{
AnnaBridge	157:e7ca05fa8600	508	*/
AnnaBridge	157:e7ca05fa8600	509	/**
AnnaBridge	157:e7ca05fa8600	510	* @brief Enable DMA channel.
AnnaBridge	157:e7ca05fa8600	511	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	157:e7ca05fa8600	512	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	513	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	514	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	515	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	516	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	517	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	518	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	519	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	520	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	521	* @retval None
AnnaBridge	157:e7ca05fa8600	522	*/
AnnaBridge	157:e7ca05fa8600	523	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	524	{
AnnaBridge	157:e7ca05fa8600	525	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	157:e7ca05fa8600	526	}
AnnaBridge	157:e7ca05fa8600	527
AnnaBridge	157:e7ca05fa8600	528	/**
AnnaBridge	157:e7ca05fa8600	529	* @brief Disable DMA channel.
AnnaBridge	157:e7ca05fa8600	530	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	157:e7ca05fa8600	531	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	532	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	533	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	534	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	535	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	536	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	537	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	538	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	539	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	540	* @retval None
AnnaBridge	157:e7ca05fa8600	541	*/
AnnaBridge	157:e7ca05fa8600	542	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	543	{
AnnaBridge	157:e7ca05fa8600	544	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	157:e7ca05fa8600	545	}
AnnaBridge	157:e7ca05fa8600	546
AnnaBridge	157:e7ca05fa8600	547	/**
AnnaBridge	157:e7ca05fa8600	548	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	549	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	157:e7ca05fa8600	550	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	551	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	552	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	553	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	554	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	555	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	556	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	557	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	558	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	559	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	560	*/
AnnaBridge	157:e7ca05fa8600	561	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	562	{
AnnaBridge	157:e7ca05fa8600	563	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	564	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	157:e7ca05fa8600	565	}
AnnaBridge	157:e7ca05fa8600	566
AnnaBridge	157:e7ca05fa8600	567	/**
AnnaBridge	157:e7ca05fa8600	568	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	157:e7ca05fa8600	569	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	570	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	571	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	572	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	573	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	574	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	575	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	157:e7ca05fa8600	576	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	157:e7ca05fa8600	577	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	578	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	579	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	580	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	581	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	582	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	583	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	584	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	585	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	586	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	157:e7ca05fa8600	587	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	588	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	157:e7ca05fa8600	589	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	590	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	591	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	592	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	593	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	157:e7ca05fa8600	594	* @retval None
AnnaBridge	157:e7ca05fa8600	595	*/
AnnaBridge	157:e7ca05fa8600	596	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	157:e7ca05fa8600	597	{
AnnaBridge	157:e7ca05fa8600	598	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	599	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	157:e7ca05fa8600	600	Configuration);
AnnaBridge	157:e7ca05fa8600	601	}
AnnaBridge	157:e7ca05fa8600	602
AnnaBridge	157:e7ca05fa8600	603	/**
AnnaBridge	157:e7ca05fa8600	604	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	157:e7ca05fa8600	605	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	157:e7ca05fa8600	606	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	157:e7ca05fa8600	607	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	608	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	609	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	610	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	611	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	612	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	613	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	614	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	615	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	616	* @param Direction This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	617	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	618	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	157:e7ca05fa8600	619	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	620	* @retval None
AnnaBridge	157:e7ca05fa8600	621	*/
AnnaBridge	157:e7ca05fa8600	622	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	157:e7ca05fa8600	623	{
AnnaBridge	157:e7ca05fa8600	624	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	625	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	157:e7ca05fa8600	626	}
AnnaBridge	157:e7ca05fa8600	627
AnnaBridge	157:e7ca05fa8600	628	/**
AnnaBridge	157:e7ca05fa8600	629	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	157:e7ca05fa8600	630	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	157:e7ca05fa8600	631	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	157:e7ca05fa8600	632	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	633	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	634	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	635	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	636	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	637	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	638	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	639	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	640	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	641	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	642	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	643	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	157:e7ca05fa8600	644	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	645	*/
AnnaBridge	157:e7ca05fa8600	646	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	647	{
AnnaBridge	157:e7ca05fa8600	648	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	649	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	157:e7ca05fa8600	650	}
AnnaBridge	157:e7ca05fa8600	651
AnnaBridge	157:e7ca05fa8600	652	/**
AnnaBridge	157:e7ca05fa8600	653	* @brief Set DMA mode circular or normal.
AnnaBridge	157:e7ca05fa8600	654	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	157:e7ca05fa8600	655	* data transfer is configured on the selected Channel.
AnnaBridge	157:e7ca05fa8600	656	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	157:e7ca05fa8600	657	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	658	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	659	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	660	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	661	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	662	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	663	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	664	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	665	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	666	* @param Mode This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	667	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	157:e7ca05fa8600	668	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	157:e7ca05fa8600	669	* @retval None
AnnaBridge	157:e7ca05fa8600	670	*/
AnnaBridge	157:e7ca05fa8600	671	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	157:e7ca05fa8600	672	{
AnnaBridge	157:e7ca05fa8600	673	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	157:e7ca05fa8600	674	Mode);
AnnaBridge	157:e7ca05fa8600	675	}
AnnaBridge	157:e7ca05fa8600	676
AnnaBridge	157:e7ca05fa8600	677	/**
AnnaBridge	157:e7ca05fa8600	678	* @brief Get DMA mode circular or normal.
AnnaBridge	157:e7ca05fa8600	679	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	157:e7ca05fa8600	680	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	681	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	682	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	683	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	684	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	685	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	686	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	687	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	688	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	689	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	690	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	157:e7ca05fa8600	691	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	157:e7ca05fa8600	692	*/
AnnaBridge	157:e7ca05fa8600	693	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	694	{
AnnaBridge	157:e7ca05fa8600	695	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	696	DMA_CCR_CIRC));
AnnaBridge	157:e7ca05fa8600	697	}
AnnaBridge	157:e7ca05fa8600	698
AnnaBridge	157:e7ca05fa8600	699	/**
AnnaBridge	157:e7ca05fa8600	700	* @brief Set Peripheral increment mode.
AnnaBridge	157:e7ca05fa8600	701	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	157:e7ca05fa8600	702	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	703	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	704	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	705	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	706	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	707	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	708	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	709	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	710	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	711	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	712	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	157:e7ca05fa8600	713	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	714	* @retval None
AnnaBridge	157:e7ca05fa8600	715	*/
AnnaBridge	157:e7ca05fa8600	716	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	157:e7ca05fa8600	717	{
AnnaBridge	157:e7ca05fa8600	718	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	157:e7ca05fa8600	719	PeriphOrM2MSrcIncMode);
AnnaBridge	157:e7ca05fa8600	720	}
AnnaBridge	157:e7ca05fa8600	721
AnnaBridge	157:e7ca05fa8600	722	/**
AnnaBridge	157:e7ca05fa8600	723	* @brief Get Peripheral increment mode.
AnnaBridge	157:e7ca05fa8600	724	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	157:e7ca05fa8600	725	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	726	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	727	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	728	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	729	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	730	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	731	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	732	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	733	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	734	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	735	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	157:e7ca05fa8600	736	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	737	*/
AnnaBridge	157:e7ca05fa8600	738	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	739	{
AnnaBridge	157:e7ca05fa8600	740	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	741	DMA_CCR_PINC));
AnnaBridge	157:e7ca05fa8600	742	}
AnnaBridge	157:e7ca05fa8600	743
AnnaBridge	157:e7ca05fa8600	744	/**
AnnaBridge	157:e7ca05fa8600	745	* @brief Set Memory increment mode.
AnnaBridge	157:e7ca05fa8600	746	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	157:e7ca05fa8600	747	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	748	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	749	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	750	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	751	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	752	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	753	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	754	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	755	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	756	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	757	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	157:e7ca05fa8600	758	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	759	* @retval None
AnnaBridge	157:e7ca05fa8600	760	*/
AnnaBridge	157:e7ca05fa8600	761	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	157:e7ca05fa8600	762	{
AnnaBridge	157:e7ca05fa8600	763	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	157:e7ca05fa8600	764	MemoryOrM2MDstIncMode);
AnnaBridge	157:e7ca05fa8600	765	}
AnnaBridge	157:e7ca05fa8600	766
AnnaBridge	157:e7ca05fa8600	767	/**
AnnaBridge	157:e7ca05fa8600	768	* @brief Get Memory increment mode.
AnnaBridge	157:e7ca05fa8600	769	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	157:e7ca05fa8600	770	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	771	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	772	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	773	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	774	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	775	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	776	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	777	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	778	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	779	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	780	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	157:e7ca05fa8600	781	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	157:e7ca05fa8600	782	*/
AnnaBridge	157:e7ca05fa8600	783	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	784	{
AnnaBridge	157:e7ca05fa8600	785	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	786	DMA_CCR_MINC));
AnnaBridge	157:e7ca05fa8600	787	}
AnnaBridge	157:e7ca05fa8600	788
AnnaBridge	157:e7ca05fa8600	789	/**
AnnaBridge	157:e7ca05fa8600	790	* @brief Set Peripheral size.
AnnaBridge	157:e7ca05fa8600	791	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	157:e7ca05fa8600	792	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	793	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	794	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	795	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	796	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	797	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	798	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	799	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	800	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	801	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	802	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	157:e7ca05fa8600	803	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	157:e7ca05fa8600	804	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	805	* @retval None
AnnaBridge	157:e7ca05fa8600	806	*/
AnnaBridge	157:e7ca05fa8600	807	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	157:e7ca05fa8600	808	{
AnnaBridge	157:e7ca05fa8600	809	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	157:e7ca05fa8600	810	PeriphOrM2MSrcDataSize);
AnnaBridge	157:e7ca05fa8600	811	}
AnnaBridge	157:e7ca05fa8600	812
AnnaBridge	157:e7ca05fa8600	813	/**
AnnaBridge	157:e7ca05fa8600	814	* @brief Get Peripheral size.
AnnaBridge	157:e7ca05fa8600	815	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	157:e7ca05fa8600	816	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	817	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	818	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	819	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	820	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	821	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	822	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	823	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	824	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	825	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	826	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	157:e7ca05fa8600	827	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	157:e7ca05fa8600	828	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	829	*/
AnnaBridge	157:e7ca05fa8600	830	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	831	{
AnnaBridge	157:e7ca05fa8600	832	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	833	DMA_CCR_PSIZE));
AnnaBridge	157:e7ca05fa8600	834	}
AnnaBridge	157:e7ca05fa8600	835
AnnaBridge	157:e7ca05fa8600	836	/**
AnnaBridge	157:e7ca05fa8600	837	* @brief Set Memory size.
AnnaBridge	157:e7ca05fa8600	838	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	157:e7ca05fa8600	839	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	840	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	841	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	842	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	843	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	844	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	845	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	846	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	847	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	848	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	849	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	157:e7ca05fa8600	850	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	157:e7ca05fa8600	851	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	852	* @retval None
AnnaBridge	157:e7ca05fa8600	853	*/
AnnaBridge	157:e7ca05fa8600	854	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	157:e7ca05fa8600	855	{
AnnaBridge	157:e7ca05fa8600	856	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	157:e7ca05fa8600	857	MemoryOrM2MDstDataSize);
AnnaBridge	157:e7ca05fa8600	858	}
AnnaBridge	157:e7ca05fa8600	859
AnnaBridge	157:e7ca05fa8600	860	/**
AnnaBridge	157:e7ca05fa8600	861	* @brief Get Memory size.
AnnaBridge	157:e7ca05fa8600	862	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	157:e7ca05fa8600	863	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	864	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	865	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	866	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	867	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	868	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	869	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	870	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	871	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	872	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	873	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	157:e7ca05fa8600	874	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	157:e7ca05fa8600	875	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	157:e7ca05fa8600	876	*/
AnnaBridge	157:e7ca05fa8600	877	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	878	{
AnnaBridge	157:e7ca05fa8600	879	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	880	DMA_CCR_MSIZE));
AnnaBridge	157:e7ca05fa8600	881	}
AnnaBridge	157:e7ca05fa8600	882
AnnaBridge	157:e7ca05fa8600	883	/**
AnnaBridge	157:e7ca05fa8600	884	* @brief Set Channel priority level.
AnnaBridge	157:e7ca05fa8600	885	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	157:e7ca05fa8600	886	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	887	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	888	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	889	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	890	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	891	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	892	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	893	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	894	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	895	* @param Priority This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	896	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	157:e7ca05fa8600	897	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	157:e7ca05fa8600	898	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	157:e7ca05fa8600	899	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	157:e7ca05fa8600	900	* @retval None
AnnaBridge	157:e7ca05fa8600	901	*/
AnnaBridge	157:e7ca05fa8600	902	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	157:e7ca05fa8600	903	{
AnnaBridge	157:e7ca05fa8600	904	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	157:e7ca05fa8600	905	Priority);
AnnaBridge	157:e7ca05fa8600	906	}
AnnaBridge	157:e7ca05fa8600	907
AnnaBridge	157:e7ca05fa8600	908	/**
AnnaBridge	157:e7ca05fa8600	909	* @brief Get Channel priority level.
AnnaBridge	157:e7ca05fa8600	910	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	157:e7ca05fa8600	911	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	912	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	913	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	914	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	915	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	916	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	917	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	918	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	919	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	920	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	921	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	157:e7ca05fa8600	922	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	157:e7ca05fa8600	923	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	157:e7ca05fa8600	924	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	157:e7ca05fa8600	925	*/
AnnaBridge	157:e7ca05fa8600	926	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	927	{
AnnaBridge	157:e7ca05fa8600	928	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	929	DMA_CCR_PL));
AnnaBridge	157:e7ca05fa8600	930	}
AnnaBridge	157:e7ca05fa8600	931
AnnaBridge	157:e7ca05fa8600	932	/**
AnnaBridge	157:e7ca05fa8600	933	* @brief Set Number of data to transfer.
AnnaBridge	157:e7ca05fa8600	934	* @note This action has no effect if
AnnaBridge	157:e7ca05fa8600	935	* channel is enabled.
AnnaBridge	157:e7ca05fa8600	936	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	157:e7ca05fa8600	937	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	938	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	939	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	940	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	941	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	942	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	943	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	944	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	945	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	946	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	157:e7ca05fa8600	947	* @retval None
AnnaBridge	157:e7ca05fa8600	948	*/
AnnaBridge	157:e7ca05fa8600	949	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	157:e7ca05fa8600	950	{
AnnaBridge	157:e7ca05fa8600	951	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	157:e7ca05fa8600	952	DMA_CNDTR_NDT, NbData);
AnnaBridge	157:e7ca05fa8600	953	}
AnnaBridge	157:e7ca05fa8600	954
AnnaBridge	157:e7ca05fa8600	955	/**
AnnaBridge	157:e7ca05fa8600	956	* @brief Get Number of data to transfer.
AnnaBridge	157:e7ca05fa8600	957	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	157:e7ca05fa8600	958	* remaining bytes to be transmitted.
AnnaBridge	157:e7ca05fa8600	959	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	157:e7ca05fa8600	960	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	961	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	962	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	963	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	964	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	965	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	966	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	967	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	968	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	969	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	970	*/
AnnaBridge	157:e7ca05fa8600	971	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	972	{
AnnaBridge	157:e7ca05fa8600	973	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	157:e7ca05fa8600	974	DMA_CNDTR_NDT));
AnnaBridge	157:e7ca05fa8600	975	}
AnnaBridge	157:e7ca05fa8600	976
AnnaBridge	157:e7ca05fa8600	977	/**
AnnaBridge	157:e7ca05fa8600	978	* @brief Configure the Source and Destination addresses.
AnnaBridge	157:e7ca05fa8600	979	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
AnnaBridge	157:e7ca05fa8600	980	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	157:e7ca05fa8600	981	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	157:e7ca05fa8600	982	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	983	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	984	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	985	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	986	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	987	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	988	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	989	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	990	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	991	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	992	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	993	* @param Direction This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	994	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	995	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	157:e7ca05fa8600	996	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	157:e7ca05fa8600	997	* @retval None
AnnaBridge	157:e7ca05fa8600	998	*/
AnnaBridge	157:e7ca05fa8600	999	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	157:e7ca05fa8600	1000	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	157:e7ca05fa8600	1001	{
AnnaBridge	157:e7ca05fa8600	1002	/* Direction Memory to Periph */
AnnaBridge	157:e7ca05fa8600	1003	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	157:e7ca05fa8600	1004	{
AnnaBridge	157:e7ca05fa8600	1005	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
AnnaBridge	157:e7ca05fa8600	1006	SrcAddress);
AnnaBridge	157:e7ca05fa8600	1007	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
AnnaBridge	157:e7ca05fa8600	1008	DstAddress);
AnnaBridge	157:e7ca05fa8600	1009	}
AnnaBridge	157:e7ca05fa8600	1010	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	157:e7ca05fa8600	1011	else
AnnaBridge	157:e7ca05fa8600	1012	{
AnnaBridge	157:e7ca05fa8600	1013	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
AnnaBridge	157:e7ca05fa8600	1014	SrcAddress);
AnnaBridge	157:e7ca05fa8600	1015	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
AnnaBridge	157:e7ca05fa8600	1016	DstAddress);
AnnaBridge	157:e7ca05fa8600	1017	}
AnnaBridge	157:e7ca05fa8600	1018	}
AnnaBridge	157:e7ca05fa8600	1019
AnnaBridge	157:e7ca05fa8600	1020	/**
AnnaBridge	157:e7ca05fa8600	1021	* @brief Set the Memory address.
AnnaBridge	157:e7ca05fa8600	1022	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	157:e7ca05fa8600	1023	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	157:e7ca05fa8600	1024	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1025	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1026	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1027	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1028	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1029	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1030	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1031	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1032	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1033	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1034	* @retval None
AnnaBridge	157:e7ca05fa8600	1035	*/
AnnaBridge	157:e7ca05fa8600	1036	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	157:e7ca05fa8600	1037	{
AnnaBridge	157:e7ca05fa8600	1038	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
AnnaBridge	157:e7ca05fa8600	1039	MemoryAddress);
AnnaBridge	157:e7ca05fa8600	1040	}
AnnaBridge	157:e7ca05fa8600	1041
AnnaBridge	157:e7ca05fa8600	1042	/**
AnnaBridge	157:e7ca05fa8600	1043	* @brief Set the Peripheral address.
AnnaBridge	157:e7ca05fa8600	1044	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	157:e7ca05fa8600	1045	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	157:e7ca05fa8600	1046	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1047	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1048	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1049	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1050	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1051	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1052	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1053	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1054	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1055	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1056	* @retval None
AnnaBridge	157:e7ca05fa8600	1057	*/
AnnaBridge	157:e7ca05fa8600	1058	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	157:e7ca05fa8600	1059	{
AnnaBridge	157:e7ca05fa8600	1060	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
AnnaBridge	157:e7ca05fa8600	1061	PeriphAddress);
AnnaBridge	157:e7ca05fa8600	1062	}
AnnaBridge	157:e7ca05fa8600	1063
AnnaBridge	157:e7ca05fa8600	1064	/**
AnnaBridge	157:e7ca05fa8600	1065	* @brief Get Memory address.
AnnaBridge	157:e7ca05fa8600	1066	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	157:e7ca05fa8600	1067	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	157:e7ca05fa8600	1068	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1069	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1070	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1071	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1072	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1073	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1074	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1075	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1076	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1077	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1078	*/
AnnaBridge	157:e7ca05fa8600	1079	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1080	{
AnnaBridge	157:e7ca05fa8600	1081	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
AnnaBridge	157:e7ca05fa8600	1082	DMA_CMAR_MA));
AnnaBridge	157:e7ca05fa8600	1083	}
AnnaBridge	157:e7ca05fa8600	1084
AnnaBridge	157:e7ca05fa8600	1085	/**
AnnaBridge	157:e7ca05fa8600	1086	* @brief Get Peripheral address.
AnnaBridge	157:e7ca05fa8600	1087	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	157:e7ca05fa8600	1088	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	157:e7ca05fa8600	1089	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1090	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1091	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1092	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1093	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1094	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1095	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1096	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1097	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1098	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1099	*/
AnnaBridge	157:e7ca05fa8600	1100	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1101	{
AnnaBridge	157:e7ca05fa8600	1102	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
AnnaBridge	157:e7ca05fa8600	1103	DMA_CPAR_PA));
AnnaBridge	157:e7ca05fa8600	1104	}
AnnaBridge	157:e7ca05fa8600	1105
AnnaBridge	157:e7ca05fa8600	1106	/**
AnnaBridge	157:e7ca05fa8600	1107	* @brief Set the Memory to Memory Source address.
AnnaBridge	157:e7ca05fa8600	1108	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	157:e7ca05fa8600	1109	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	157:e7ca05fa8600	1110	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1111	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1112	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1113	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1114	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1115	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1116	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1117	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1118	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1119	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1120	* @retval None
AnnaBridge	157:e7ca05fa8600	1121	*/
AnnaBridge	157:e7ca05fa8600	1122	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	157:e7ca05fa8600	1123	{
AnnaBridge	157:e7ca05fa8600	1124	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
AnnaBridge	157:e7ca05fa8600	1125	MemoryAddress);
AnnaBridge	157:e7ca05fa8600	1126	}
AnnaBridge	157:e7ca05fa8600	1127
AnnaBridge	157:e7ca05fa8600	1128	/**
AnnaBridge	157:e7ca05fa8600	1129	* @brief Set the Memory to Memory Destination address.
AnnaBridge	157:e7ca05fa8600	1130	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	157:e7ca05fa8600	1131	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	157:e7ca05fa8600	1132	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1133	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1134	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1135	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1136	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1137	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1138	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1139	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1140	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1141	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1142	* @retval None
AnnaBridge	157:e7ca05fa8600	1143	*/
AnnaBridge	157:e7ca05fa8600	1144	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	157:e7ca05fa8600	1145	{
AnnaBridge	157:e7ca05fa8600	1146	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
AnnaBridge	157:e7ca05fa8600	1147	MemoryAddress);
AnnaBridge	157:e7ca05fa8600	1148	}
AnnaBridge	157:e7ca05fa8600	1149
AnnaBridge	157:e7ca05fa8600	1150	/**
AnnaBridge	157:e7ca05fa8600	1151	* @brief Get the Memory to Memory Source address.
AnnaBridge	157:e7ca05fa8600	1152	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	157:e7ca05fa8600	1153	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	157:e7ca05fa8600	1154	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1155	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1156	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1157	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1158	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1159	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1160	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1161	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1162	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1163	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1164	*/
AnnaBridge	157:e7ca05fa8600	1165	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1166	{
AnnaBridge	157:e7ca05fa8600	1167	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
AnnaBridge	157:e7ca05fa8600	1168	DMA_CPAR_PA));
AnnaBridge	157:e7ca05fa8600	1169	}
AnnaBridge	157:e7ca05fa8600	1170
AnnaBridge	157:e7ca05fa8600	1171	/**
AnnaBridge	157:e7ca05fa8600	1172	* @brief Get the Memory to Memory Destination address.
AnnaBridge	157:e7ca05fa8600	1173	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	157:e7ca05fa8600	1174	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	157:e7ca05fa8600	1175	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1176	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1177	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1178	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1179	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1180	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1181	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1182	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1183	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1184	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	157:e7ca05fa8600	1185	*/
AnnaBridge	157:e7ca05fa8600	1186	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1187	{
AnnaBridge	157:e7ca05fa8600	1188	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
AnnaBridge	157:e7ca05fa8600	1189	DMA_CMAR_MA));
AnnaBridge	157:e7ca05fa8600	1190	}
AnnaBridge	157:e7ca05fa8600	1191
AnnaBridge	157:e7ca05fa8600	1192	/**
AnnaBridge	157:e7ca05fa8600	1193	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	157:e7ca05fa8600	1194	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	157:e7ca05fa8600	1195	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1196	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1197	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1198	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1199	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1200	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1201	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	157:e7ca05fa8600	1202	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1203	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1204	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1205	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1206	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1207	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1208	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1209	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1210	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1211	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1212	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	157:e7ca05fa8600	1213	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	157:e7ca05fa8600	1214	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	157:e7ca05fa8600	1215	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	157:e7ca05fa8600	1216	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	157:e7ca05fa8600	1217	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	157:e7ca05fa8600	1218	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	157:e7ca05fa8600	1219	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	157:e7ca05fa8600	1220	* @arg @ref LL_DMA_REQUEST_8
AnnaBridge	157:e7ca05fa8600	1221	* @arg @ref LL_DMA_REQUEST_9
AnnaBridge	157:e7ca05fa8600	1222	* @arg @ref LL_DMA_REQUEST_10
AnnaBridge	157:e7ca05fa8600	1223	* @arg @ref LL_DMA_REQUEST_11
AnnaBridge	157:e7ca05fa8600	1224	* @arg @ref LL_DMA_REQUEST_12
AnnaBridge	157:e7ca05fa8600	1225	* @arg @ref LL_DMA_REQUEST_13
AnnaBridge	157:e7ca05fa8600	1226	* @arg @ref LL_DMA_REQUEST_14
AnnaBridge	157:e7ca05fa8600	1227	* @arg @ref LL_DMA_REQUEST_15
AnnaBridge	157:e7ca05fa8600	1228	* @retval None
AnnaBridge	157:e7ca05fa8600	1229	*/
AnnaBridge	157:e7ca05fa8600	1230	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	157:e7ca05fa8600	1231	{
AnnaBridge	157:e7ca05fa8600	1232	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	157:e7ca05fa8600	1233	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	157:e7ca05fa8600	1234	}
AnnaBridge	157:e7ca05fa8600	1235
AnnaBridge	157:e7ca05fa8600	1236	/**
AnnaBridge	157:e7ca05fa8600	1237	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	157:e7ca05fa8600	1238	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1239	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1240	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1241	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1242	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1243	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	157:e7ca05fa8600	1244	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	157:e7ca05fa8600	1245	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1246	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1247	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1248	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1249	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1250	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1251	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1252	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1253	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1254	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1255	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	157:e7ca05fa8600	1256	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	157:e7ca05fa8600	1257	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	157:e7ca05fa8600	1258	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	157:e7ca05fa8600	1259	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	157:e7ca05fa8600	1260	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	157:e7ca05fa8600	1261	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	157:e7ca05fa8600	1262	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	157:e7ca05fa8600	1263	* @arg @ref LL_DMA_REQUEST_8
AnnaBridge	157:e7ca05fa8600	1264	* @arg @ref LL_DMA_REQUEST_9
AnnaBridge	157:e7ca05fa8600	1265	* @arg @ref LL_DMA_REQUEST_10
AnnaBridge	157:e7ca05fa8600	1266	* @arg @ref LL_DMA_REQUEST_11
AnnaBridge	157:e7ca05fa8600	1267	* @arg @ref LL_DMA_REQUEST_12
AnnaBridge	157:e7ca05fa8600	1268	* @arg @ref LL_DMA_REQUEST_13
AnnaBridge	157:e7ca05fa8600	1269	* @arg @ref LL_DMA_REQUEST_14
AnnaBridge	157:e7ca05fa8600	1270	* @arg @ref LL_DMA_REQUEST_15
AnnaBridge	157:e7ca05fa8600	1271	*/
AnnaBridge	157:e7ca05fa8600	1272	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1273	{
AnnaBridge	157:e7ca05fa8600	1274	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	157:e7ca05fa8600	1275	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	157:e7ca05fa8600	1276	}
AnnaBridge	157:e7ca05fa8600	1277
AnnaBridge	157:e7ca05fa8600	1278	/**
AnnaBridge	157:e7ca05fa8600	1279	* @}
AnnaBridge	157:e7ca05fa8600	1280	*/
AnnaBridge	157:e7ca05fa8600	1281
AnnaBridge	157:e7ca05fa8600	1282	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	157:e7ca05fa8600	1283	* @{
AnnaBridge	157:e7ca05fa8600	1284	*/
AnnaBridge	157:e7ca05fa8600	1285
AnnaBridge	157:e7ca05fa8600	1286	/**
AnnaBridge	157:e7ca05fa8600	1287	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1288	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	157:e7ca05fa8600	1289	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1290	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1291	*/
AnnaBridge	157:e7ca05fa8600	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1293	{
AnnaBridge	157:e7ca05fa8600	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	157:e7ca05fa8600	1295	}
AnnaBridge	157:e7ca05fa8600	1296
AnnaBridge	157:e7ca05fa8600	1297	/**
AnnaBridge	157:e7ca05fa8600	1298	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1299	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	157:e7ca05fa8600	1300	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1301	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1302	*/
AnnaBridge	157:e7ca05fa8600	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1304	{
AnnaBridge	157:e7ca05fa8600	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	157:e7ca05fa8600	1306	}
AnnaBridge	157:e7ca05fa8600	1307
AnnaBridge	157:e7ca05fa8600	1308	/**
AnnaBridge	157:e7ca05fa8600	1309	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1310	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	157:e7ca05fa8600	1311	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1312	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1313	*/
AnnaBridge	157:e7ca05fa8600	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1315	{
AnnaBridge	157:e7ca05fa8600	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	157:e7ca05fa8600	1317	}
AnnaBridge	157:e7ca05fa8600	1318
AnnaBridge	157:e7ca05fa8600	1319	/**
AnnaBridge	157:e7ca05fa8600	1320	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1321	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	157:e7ca05fa8600	1322	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1323	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1324	*/
AnnaBridge	157:e7ca05fa8600	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1326	{
AnnaBridge	157:e7ca05fa8600	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	157:e7ca05fa8600	1328	}
AnnaBridge	157:e7ca05fa8600	1329
AnnaBridge	157:e7ca05fa8600	1330	/**
AnnaBridge	157:e7ca05fa8600	1331	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1332	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	157:e7ca05fa8600	1333	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1334	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1335	*/
AnnaBridge	157:e7ca05fa8600	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1337	{
AnnaBridge	157:e7ca05fa8600	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	157:e7ca05fa8600	1339	}
AnnaBridge	157:e7ca05fa8600	1340
AnnaBridge	157:e7ca05fa8600	1341	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1342	/**
AnnaBridge	157:e7ca05fa8600	1343	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1344	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	157:e7ca05fa8600	1345	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1346	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1347	*/
AnnaBridge	157:e7ca05fa8600	1348	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1349	{
AnnaBridge	157:e7ca05fa8600	1350	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	157:e7ca05fa8600	1351	}
AnnaBridge	157:e7ca05fa8600	1352	#endif
AnnaBridge	157:e7ca05fa8600	1353
AnnaBridge	157:e7ca05fa8600	1354	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1355	/**
AnnaBridge	157:e7ca05fa8600	1356	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1357	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	157:e7ca05fa8600	1358	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1359	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1360	*/
AnnaBridge	157:e7ca05fa8600	1361	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1362	{
AnnaBridge	157:e7ca05fa8600	1363	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	157:e7ca05fa8600	1364	}
AnnaBridge	157:e7ca05fa8600	1365	#endif
AnnaBridge	157:e7ca05fa8600	1366
AnnaBridge	157:e7ca05fa8600	1367	/**
AnnaBridge	157:e7ca05fa8600	1368	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1369	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	157:e7ca05fa8600	1370	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1371	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1372	*/
AnnaBridge	157:e7ca05fa8600	1373	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1374	{
AnnaBridge	157:e7ca05fa8600	1375	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	157:e7ca05fa8600	1376	}
AnnaBridge	157:e7ca05fa8600	1377
AnnaBridge	157:e7ca05fa8600	1378	/**
AnnaBridge	157:e7ca05fa8600	1379	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1380	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	157:e7ca05fa8600	1381	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1382	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1383	*/
AnnaBridge	157:e7ca05fa8600	1384	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1385	{
AnnaBridge	157:e7ca05fa8600	1386	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	157:e7ca05fa8600	1387	}
AnnaBridge	157:e7ca05fa8600	1388
AnnaBridge	157:e7ca05fa8600	1389	/**
AnnaBridge	157:e7ca05fa8600	1390	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1391	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	157:e7ca05fa8600	1392	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1393	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1394	*/
AnnaBridge	157:e7ca05fa8600	1395	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1396	{
AnnaBridge	157:e7ca05fa8600	1397	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	157:e7ca05fa8600	1398	}
AnnaBridge	157:e7ca05fa8600	1399
AnnaBridge	157:e7ca05fa8600	1400	/**
AnnaBridge	157:e7ca05fa8600	1401	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1402	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	157:e7ca05fa8600	1403	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1404	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1405	*/
AnnaBridge	157:e7ca05fa8600	1406	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1407	{
AnnaBridge	157:e7ca05fa8600	1408	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	157:e7ca05fa8600	1409	}
AnnaBridge	157:e7ca05fa8600	1410
AnnaBridge	157:e7ca05fa8600	1411	/**
AnnaBridge	157:e7ca05fa8600	1412	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1413	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	157:e7ca05fa8600	1414	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1415	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1416	*/
AnnaBridge	157:e7ca05fa8600	1417	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1418	{
AnnaBridge	157:e7ca05fa8600	1419	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	157:e7ca05fa8600	1420	}
AnnaBridge	157:e7ca05fa8600	1421
AnnaBridge	157:e7ca05fa8600	1422	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1423	/**
AnnaBridge	157:e7ca05fa8600	1424	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1425	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	157:e7ca05fa8600	1426	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1427	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1428	*/
AnnaBridge	157:e7ca05fa8600	1429	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1430	{
AnnaBridge	157:e7ca05fa8600	1431	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	157:e7ca05fa8600	1432	}
AnnaBridge	157:e7ca05fa8600	1433	#endif
AnnaBridge	157:e7ca05fa8600	1434
AnnaBridge	157:e7ca05fa8600	1435	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1436	/**
AnnaBridge	157:e7ca05fa8600	1437	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1438	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	157:e7ca05fa8600	1439	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1440	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1441	*/
AnnaBridge	157:e7ca05fa8600	1442	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1443	{
AnnaBridge	157:e7ca05fa8600	1444	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	157:e7ca05fa8600	1445	}
AnnaBridge	157:e7ca05fa8600	1446	#endif
AnnaBridge	157:e7ca05fa8600	1447
AnnaBridge	157:e7ca05fa8600	1448	/**
AnnaBridge	157:e7ca05fa8600	1449	* @brief Get Channel 1 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1450	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	157:e7ca05fa8600	1451	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1452	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1453	*/
AnnaBridge	157:e7ca05fa8600	1454	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1455	{
AnnaBridge	157:e7ca05fa8600	1456	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	157:e7ca05fa8600	1457	}
AnnaBridge	157:e7ca05fa8600	1458
AnnaBridge	157:e7ca05fa8600	1459	/**
AnnaBridge	157:e7ca05fa8600	1460	* @brief Get Channel 2 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1461	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	157:e7ca05fa8600	1462	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1463	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1464	*/
AnnaBridge	157:e7ca05fa8600	1465	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1466	{
AnnaBridge	157:e7ca05fa8600	1467	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	157:e7ca05fa8600	1468	}
AnnaBridge	157:e7ca05fa8600	1469
AnnaBridge	157:e7ca05fa8600	1470	/**
AnnaBridge	157:e7ca05fa8600	1471	* @brief Get Channel 3 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1472	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	157:e7ca05fa8600	1473	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1474	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1475	*/
AnnaBridge	157:e7ca05fa8600	1476	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1477	{
AnnaBridge	157:e7ca05fa8600	1478	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	157:e7ca05fa8600	1479	}
AnnaBridge	157:e7ca05fa8600	1480
AnnaBridge	157:e7ca05fa8600	1481	/**
AnnaBridge	157:e7ca05fa8600	1482	* @brief Get Channel 4 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1483	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	157:e7ca05fa8600	1484	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1485	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1486	*/
AnnaBridge	157:e7ca05fa8600	1487	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1488	{
AnnaBridge	157:e7ca05fa8600	1489	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	157:e7ca05fa8600	1490	}
AnnaBridge	157:e7ca05fa8600	1491
AnnaBridge	157:e7ca05fa8600	1492	/**
AnnaBridge	157:e7ca05fa8600	1493	* @brief Get Channel 5 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1494	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	157:e7ca05fa8600	1495	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1496	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1497	*/
AnnaBridge	157:e7ca05fa8600	1498	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1499	{
AnnaBridge	157:e7ca05fa8600	1500	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	157:e7ca05fa8600	1501	}
AnnaBridge	157:e7ca05fa8600	1502
AnnaBridge	157:e7ca05fa8600	1503	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1504	/**
AnnaBridge	157:e7ca05fa8600	1505	* @brief Get Channel 6 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1506	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	157:e7ca05fa8600	1507	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1508	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1509	*/
AnnaBridge	157:e7ca05fa8600	1510	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1511	{
AnnaBridge	157:e7ca05fa8600	1512	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	157:e7ca05fa8600	1513	}
AnnaBridge	157:e7ca05fa8600	1514	#endif
AnnaBridge	157:e7ca05fa8600	1515
AnnaBridge	157:e7ca05fa8600	1516	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1517	/**
AnnaBridge	157:e7ca05fa8600	1518	* @brief Get Channel 7 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1519	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	157:e7ca05fa8600	1520	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1521	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1522	*/
AnnaBridge	157:e7ca05fa8600	1523	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1524	{
AnnaBridge	157:e7ca05fa8600	1525	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	157:e7ca05fa8600	1526	}
AnnaBridge	157:e7ca05fa8600	1527	#endif
AnnaBridge	157:e7ca05fa8600	1528
AnnaBridge	157:e7ca05fa8600	1529	/**
AnnaBridge	157:e7ca05fa8600	1530	* @brief Get Channel 1 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1531	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	157:e7ca05fa8600	1532	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1533	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1534	*/
AnnaBridge	157:e7ca05fa8600	1535	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1536	{
AnnaBridge	157:e7ca05fa8600	1537	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	157:e7ca05fa8600	1538	}
AnnaBridge	157:e7ca05fa8600	1539
AnnaBridge	157:e7ca05fa8600	1540	/**
AnnaBridge	157:e7ca05fa8600	1541	* @brief Get Channel 2 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1542	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	157:e7ca05fa8600	1543	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1544	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1545	*/
AnnaBridge	157:e7ca05fa8600	1546	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1547	{
AnnaBridge	157:e7ca05fa8600	1548	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	157:e7ca05fa8600	1549	}
AnnaBridge	157:e7ca05fa8600	1550
AnnaBridge	157:e7ca05fa8600	1551	/**
AnnaBridge	157:e7ca05fa8600	1552	* @brief Get Channel 3 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1553	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	157:e7ca05fa8600	1554	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1555	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1556	*/
AnnaBridge	157:e7ca05fa8600	1557	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1558	{
AnnaBridge	157:e7ca05fa8600	1559	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	157:e7ca05fa8600	1560	}
AnnaBridge	157:e7ca05fa8600	1561
AnnaBridge	157:e7ca05fa8600	1562	/**
AnnaBridge	157:e7ca05fa8600	1563	* @brief Get Channel 4 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1564	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	157:e7ca05fa8600	1565	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1566	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1567	*/
AnnaBridge	157:e7ca05fa8600	1568	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1569	{
AnnaBridge	157:e7ca05fa8600	1570	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	157:e7ca05fa8600	1571	}
AnnaBridge	157:e7ca05fa8600	1572
AnnaBridge	157:e7ca05fa8600	1573	/**
AnnaBridge	157:e7ca05fa8600	1574	* @brief Get Channel 5 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1575	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	157:e7ca05fa8600	1576	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1577	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1578	*/
AnnaBridge	157:e7ca05fa8600	1579	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1580	{
AnnaBridge	157:e7ca05fa8600	1581	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	157:e7ca05fa8600	1582	}
AnnaBridge	157:e7ca05fa8600	1583
AnnaBridge	157:e7ca05fa8600	1584	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1585	/**
AnnaBridge	157:e7ca05fa8600	1586	* @brief Get Channel 6 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1587	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	157:e7ca05fa8600	1588	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1589	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1590	*/
AnnaBridge	157:e7ca05fa8600	1591	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1592	{
AnnaBridge	157:e7ca05fa8600	1593	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	157:e7ca05fa8600	1594	}
AnnaBridge	157:e7ca05fa8600	1595	#endif
AnnaBridge	157:e7ca05fa8600	1596
AnnaBridge	157:e7ca05fa8600	1597	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1598	/**
AnnaBridge	157:e7ca05fa8600	1599	* @brief Get Channel 7 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1600	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	157:e7ca05fa8600	1601	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1602	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1603	*/
AnnaBridge	157:e7ca05fa8600	1604	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1605	{
AnnaBridge	157:e7ca05fa8600	1606	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	157:e7ca05fa8600	1607	}
AnnaBridge	157:e7ca05fa8600	1608	#endif
AnnaBridge	157:e7ca05fa8600	1609
AnnaBridge	157:e7ca05fa8600	1610	/**
AnnaBridge	157:e7ca05fa8600	1611	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1612	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	157:e7ca05fa8600	1613	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1614	* @retval None
AnnaBridge	157:e7ca05fa8600	1615	*/
AnnaBridge	157:e7ca05fa8600	1616	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1617	{
AnnaBridge	157:e7ca05fa8600	1618	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	157:e7ca05fa8600	1619	}
AnnaBridge	157:e7ca05fa8600	1620
AnnaBridge	157:e7ca05fa8600	1621	/**
AnnaBridge	157:e7ca05fa8600	1622	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1623	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	157:e7ca05fa8600	1624	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1625	* @retval None
AnnaBridge	157:e7ca05fa8600	1626	*/
AnnaBridge	157:e7ca05fa8600	1627	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1628	{
AnnaBridge	157:e7ca05fa8600	1629	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	157:e7ca05fa8600	1630	}
AnnaBridge	157:e7ca05fa8600	1631
AnnaBridge	157:e7ca05fa8600	1632	/**
AnnaBridge	157:e7ca05fa8600	1633	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1634	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	157:e7ca05fa8600	1635	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1636	* @retval None
AnnaBridge	157:e7ca05fa8600	1637	*/
AnnaBridge	157:e7ca05fa8600	1638	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1639	{
AnnaBridge	157:e7ca05fa8600	1640	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	157:e7ca05fa8600	1641	}
AnnaBridge	157:e7ca05fa8600	1642
AnnaBridge	157:e7ca05fa8600	1643	/**
AnnaBridge	157:e7ca05fa8600	1644	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1645	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	157:e7ca05fa8600	1646	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1647	* @retval None
AnnaBridge	157:e7ca05fa8600	1648	*/
AnnaBridge	157:e7ca05fa8600	1649	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1650	{
AnnaBridge	157:e7ca05fa8600	1651	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	157:e7ca05fa8600	1652	}
AnnaBridge	157:e7ca05fa8600	1653
AnnaBridge	157:e7ca05fa8600	1654	/**
AnnaBridge	157:e7ca05fa8600	1655	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1656	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	157:e7ca05fa8600	1657	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1658	* @retval None
AnnaBridge	157:e7ca05fa8600	1659	*/
AnnaBridge	157:e7ca05fa8600	1660	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1661	{
AnnaBridge	157:e7ca05fa8600	1662	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	157:e7ca05fa8600	1663	}
AnnaBridge	157:e7ca05fa8600	1664
AnnaBridge	157:e7ca05fa8600	1665	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1666	/**
AnnaBridge	157:e7ca05fa8600	1667	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1668	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	157:e7ca05fa8600	1669	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1670	* @retval None
AnnaBridge	157:e7ca05fa8600	1671	*/
AnnaBridge	157:e7ca05fa8600	1672	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1673	{
AnnaBridge	157:e7ca05fa8600	1674	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	157:e7ca05fa8600	1675	}
AnnaBridge	157:e7ca05fa8600	1676	#endif
AnnaBridge	157:e7ca05fa8600	1677
AnnaBridge	157:e7ca05fa8600	1678	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1679	/**
AnnaBridge	157:e7ca05fa8600	1680	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	157:e7ca05fa8600	1681	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	157:e7ca05fa8600	1682	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1683	* @retval None
AnnaBridge	157:e7ca05fa8600	1684	*/
AnnaBridge	157:e7ca05fa8600	1685	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1686	{
AnnaBridge	157:e7ca05fa8600	1687	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	157:e7ca05fa8600	1688	}
AnnaBridge	157:e7ca05fa8600	1689	#endif
AnnaBridge	157:e7ca05fa8600	1690
AnnaBridge	157:e7ca05fa8600	1691	/**
AnnaBridge	157:e7ca05fa8600	1692	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1693	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	157:e7ca05fa8600	1694	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1695	* @retval None
AnnaBridge	157:e7ca05fa8600	1696	*/
AnnaBridge	157:e7ca05fa8600	1697	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1698	{
AnnaBridge	157:e7ca05fa8600	1699	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	157:e7ca05fa8600	1700	}
AnnaBridge	157:e7ca05fa8600	1701
AnnaBridge	157:e7ca05fa8600	1702	/**
AnnaBridge	157:e7ca05fa8600	1703	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1704	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	157:e7ca05fa8600	1705	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1706	* @retval None
AnnaBridge	157:e7ca05fa8600	1707	*/
AnnaBridge	157:e7ca05fa8600	1708	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1709	{
AnnaBridge	157:e7ca05fa8600	1710	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	157:e7ca05fa8600	1711	}
AnnaBridge	157:e7ca05fa8600	1712
AnnaBridge	157:e7ca05fa8600	1713	/**
AnnaBridge	157:e7ca05fa8600	1714	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1715	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	157:e7ca05fa8600	1716	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1717	* @retval None
AnnaBridge	157:e7ca05fa8600	1718	*/
AnnaBridge	157:e7ca05fa8600	1719	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1720	{
AnnaBridge	157:e7ca05fa8600	1721	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	157:e7ca05fa8600	1722	}
AnnaBridge	157:e7ca05fa8600	1723
AnnaBridge	157:e7ca05fa8600	1724	/**
AnnaBridge	157:e7ca05fa8600	1725	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1726	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	157:e7ca05fa8600	1727	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1728	* @retval None
AnnaBridge	157:e7ca05fa8600	1729	*/
AnnaBridge	157:e7ca05fa8600	1730	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1731	{
AnnaBridge	157:e7ca05fa8600	1732	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	157:e7ca05fa8600	1733	}
AnnaBridge	157:e7ca05fa8600	1734
AnnaBridge	157:e7ca05fa8600	1735	/**
AnnaBridge	157:e7ca05fa8600	1736	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1737	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	157:e7ca05fa8600	1738	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1739	* @retval None
AnnaBridge	157:e7ca05fa8600	1740	*/
AnnaBridge	157:e7ca05fa8600	1741	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1742	{
AnnaBridge	157:e7ca05fa8600	1743	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	157:e7ca05fa8600	1744	}
AnnaBridge	157:e7ca05fa8600	1745
AnnaBridge	157:e7ca05fa8600	1746	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1747	/**
AnnaBridge	157:e7ca05fa8600	1748	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1749	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	157:e7ca05fa8600	1750	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1751	* @retval None
AnnaBridge	157:e7ca05fa8600	1752	*/
AnnaBridge	157:e7ca05fa8600	1753	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1754	{
AnnaBridge	157:e7ca05fa8600	1755	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	157:e7ca05fa8600	1756	}
AnnaBridge	157:e7ca05fa8600	1757	#endif
AnnaBridge	157:e7ca05fa8600	1758
AnnaBridge	157:e7ca05fa8600	1759	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1760	/**
AnnaBridge	157:e7ca05fa8600	1761	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	157:e7ca05fa8600	1762	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	157:e7ca05fa8600	1763	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1764	* @retval None
AnnaBridge	157:e7ca05fa8600	1765	*/
AnnaBridge	157:e7ca05fa8600	1766	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1767	{
AnnaBridge	157:e7ca05fa8600	1768	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	157:e7ca05fa8600	1769	}
AnnaBridge	157:e7ca05fa8600	1770	#endif
AnnaBridge	157:e7ca05fa8600	1771
AnnaBridge	157:e7ca05fa8600	1772	/**
AnnaBridge	157:e7ca05fa8600	1773	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1774	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	157:e7ca05fa8600	1775	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1776	* @retval None
AnnaBridge	157:e7ca05fa8600	1777	*/
AnnaBridge	157:e7ca05fa8600	1778	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1779	{
AnnaBridge	157:e7ca05fa8600	1780	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	157:e7ca05fa8600	1781	}
AnnaBridge	157:e7ca05fa8600	1782
AnnaBridge	157:e7ca05fa8600	1783	/**
AnnaBridge	157:e7ca05fa8600	1784	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1785	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	157:e7ca05fa8600	1786	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1787	* @retval None
AnnaBridge	157:e7ca05fa8600	1788	*/
AnnaBridge	157:e7ca05fa8600	1789	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1790	{
AnnaBridge	157:e7ca05fa8600	1791	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	157:e7ca05fa8600	1792	}
AnnaBridge	157:e7ca05fa8600	1793
AnnaBridge	157:e7ca05fa8600	1794	/**
AnnaBridge	157:e7ca05fa8600	1795	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1796	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	157:e7ca05fa8600	1797	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1798	* @retval None
AnnaBridge	157:e7ca05fa8600	1799	*/
AnnaBridge	157:e7ca05fa8600	1800	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1801	{
AnnaBridge	157:e7ca05fa8600	1802	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	157:e7ca05fa8600	1803	}
AnnaBridge	157:e7ca05fa8600	1804
AnnaBridge	157:e7ca05fa8600	1805	/**
AnnaBridge	157:e7ca05fa8600	1806	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1807	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	157:e7ca05fa8600	1808	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1809	* @retval None
AnnaBridge	157:e7ca05fa8600	1810	*/
AnnaBridge	157:e7ca05fa8600	1811	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1812	{
AnnaBridge	157:e7ca05fa8600	1813	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	157:e7ca05fa8600	1814	}
AnnaBridge	157:e7ca05fa8600	1815
AnnaBridge	157:e7ca05fa8600	1816	/**
AnnaBridge	157:e7ca05fa8600	1817	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1818	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	157:e7ca05fa8600	1819	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1820	* @retval None
AnnaBridge	157:e7ca05fa8600	1821	*/
AnnaBridge	157:e7ca05fa8600	1822	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1823	{
AnnaBridge	157:e7ca05fa8600	1824	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	157:e7ca05fa8600	1825	}
AnnaBridge	157:e7ca05fa8600	1826
AnnaBridge	157:e7ca05fa8600	1827	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1828	/**
AnnaBridge	157:e7ca05fa8600	1829	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1830	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	157:e7ca05fa8600	1831	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1832	* @retval None
AnnaBridge	157:e7ca05fa8600	1833	*/
AnnaBridge	157:e7ca05fa8600	1834	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1835	{
AnnaBridge	157:e7ca05fa8600	1836	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	157:e7ca05fa8600	1837	}
AnnaBridge	157:e7ca05fa8600	1838	#endif
AnnaBridge	157:e7ca05fa8600	1839
AnnaBridge	157:e7ca05fa8600	1840	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1841	/**
AnnaBridge	157:e7ca05fa8600	1842	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	157:e7ca05fa8600	1843	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	157:e7ca05fa8600	1844	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1845	* @retval None
AnnaBridge	157:e7ca05fa8600	1846	*/
AnnaBridge	157:e7ca05fa8600	1847	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1848	{
AnnaBridge	157:e7ca05fa8600	1849	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	157:e7ca05fa8600	1850	}
AnnaBridge	157:e7ca05fa8600	1851	#endif
AnnaBridge	157:e7ca05fa8600	1852
AnnaBridge	157:e7ca05fa8600	1853	/**
AnnaBridge	157:e7ca05fa8600	1854	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1855	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	157:e7ca05fa8600	1856	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1857	* @retval None
AnnaBridge	157:e7ca05fa8600	1858	*/
AnnaBridge	157:e7ca05fa8600	1859	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1860	{
AnnaBridge	157:e7ca05fa8600	1861	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	157:e7ca05fa8600	1862	}
AnnaBridge	157:e7ca05fa8600	1863
AnnaBridge	157:e7ca05fa8600	1864	/**
AnnaBridge	157:e7ca05fa8600	1865	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1866	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	157:e7ca05fa8600	1867	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1868	* @retval None
AnnaBridge	157:e7ca05fa8600	1869	*/
AnnaBridge	157:e7ca05fa8600	1870	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1871	{
AnnaBridge	157:e7ca05fa8600	1872	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	157:e7ca05fa8600	1873	}
AnnaBridge	157:e7ca05fa8600	1874
AnnaBridge	157:e7ca05fa8600	1875	/**
AnnaBridge	157:e7ca05fa8600	1876	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1877	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	157:e7ca05fa8600	1878	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1879	* @retval None
AnnaBridge	157:e7ca05fa8600	1880	*/
AnnaBridge	157:e7ca05fa8600	1881	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1882	{
AnnaBridge	157:e7ca05fa8600	1883	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	157:e7ca05fa8600	1884	}
AnnaBridge	157:e7ca05fa8600	1885
AnnaBridge	157:e7ca05fa8600	1886	/**
AnnaBridge	157:e7ca05fa8600	1887	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1888	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	157:e7ca05fa8600	1889	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1890	* @retval None
AnnaBridge	157:e7ca05fa8600	1891	*/
AnnaBridge	157:e7ca05fa8600	1892	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1893	{
AnnaBridge	157:e7ca05fa8600	1894	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	157:e7ca05fa8600	1895	}
AnnaBridge	157:e7ca05fa8600	1896
AnnaBridge	157:e7ca05fa8600	1897	/**
AnnaBridge	157:e7ca05fa8600	1898	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1899	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	157:e7ca05fa8600	1900	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1901	* @retval None
AnnaBridge	157:e7ca05fa8600	1902	*/
AnnaBridge	157:e7ca05fa8600	1903	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1904	{
AnnaBridge	157:e7ca05fa8600	1905	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	157:e7ca05fa8600	1906	}
AnnaBridge	157:e7ca05fa8600	1907
AnnaBridge	157:e7ca05fa8600	1908	#if defined(DMA1_Channel6)
AnnaBridge	157:e7ca05fa8600	1909	/**
AnnaBridge	157:e7ca05fa8600	1910	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1911	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	157:e7ca05fa8600	1912	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1913	* @retval None
AnnaBridge	157:e7ca05fa8600	1914	*/
AnnaBridge	157:e7ca05fa8600	1915	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1916	{
AnnaBridge	157:e7ca05fa8600	1917	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	157:e7ca05fa8600	1918	}
AnnaBridge	157:e7ca05fa8600	1919	#endif
AnnaBridge	157:e7ca05fa8600	1920
AnnaBridge	157:e7ca05fa8600	1921	#if defined(DMA1_Channel7)
AnnaBridge	157:e7ca05fa8600	1922	/**
AnnaBridge	157:e7ca05fa8600	1923	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	157:e7ca05fa8600	1924	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	157:e7ca05fa8600	1925	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1926	* @retval None
AnnaBridge	157:e7ca05fa8600	1927	*/
AnnaBridge	157:e7ca05fa8600	1928	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	157:e7ca05fa8600	1929	{
AnnaBridge	157:e7ca05fa8600	1930	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	157:e7ca05fa8600	1931	}
AnnaBridge	157:e7ca05fa8600	1932	#endif
AnnaBridge	157:e7ca05fa8600	1933
AnnaBridge	157:e7ca05fa8600	1934	/**
AnnaBridge	157:e7ca05fa8600	1935	* @}
AnnaBridge	157:e7ca05fa8600	1936	*/
AnnaBridge	157:e7ca05fa8600	1937
AnnaBridge	157:e7ca05fa8600	1938	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	157:e7ca05fa8600	1939	* @{
AnnaBridge	157:e7ca05fa8600	1940	*/
AnnaBridge	157:e7ca05fa8600	1941	/**
AnnaBridge	157:e7ca05fa8600	1942	* @brief Enable Transfer complete interrupt.
AnnaBridge	157:e7ca05fa8600	1943	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	157:e7ca05fa8600	1944	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1945	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1946	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1947	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1948	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1949	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1950	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1951	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1952	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1953	* @retval None
AnnaBridge	157:e7ca05fa8600	1954	*/
AnnaBridge	157:e7ca05fa8600	1955	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1956	{
AnnaBridge	157:e7ca05fa8600	1957	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	157:e7ca05fa8600	1958	}
AnnaBridge	157:e7ca05fa8600	1959
AnnaBridge	157:e7ca05fa8600	1960	/**
AnnaBridge	157:e7ca05fa8600	1961	* @brief Enable Half transfer interrupt.
AnnaBridge	157:e7ca05fa8600	1962	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	157:e7ca05fa8600	1963	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1964	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1965	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1966	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1967	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1968	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1969	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1970	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1971	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1972	* @retval None
AnnaBridge	157:e7ca05fa8600	1973	*/
AnnaBridge	157:e7ca05fa8600	1974	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1975	{
AnnaBridge	157:e7ca05fa8600	1976	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	157:e7ca05fa8600	1977	}
AnnaBridge	157:e7ca05fa8600	1978
AnnaBridge	157:e7ca05fa8600	1979	/**
AnnaBridge	157:e7ca05fa8600	1980	* @brief Enable Transfer error interrupt.
AnnaBridge	157:e7ca05fa8600	1981	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	157:e7ca05fa8600	1982	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	1983	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1984	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	1985	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	1986	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	1987	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	1988	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	1989	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	1990	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	1991	* @retval None
AnnaBridge	157:e7ca05fa8600	1992	*/
AnnaBridge	157:e7ca05fa8600	1993	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	1994	{
AnnaBridge	157:e7ca05fa8600	1995	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	157:e7ca05fa8600	1996	}
AnnaBridge	157:e7ca05fa8600	1997
AnnaBridge	157:e7ca05fa8600	1998	/**
AnnaBridge	157:e7ca05fa8600	1999	* @brief Disable Transfer complete interrupt.
AnnaBridge	157:e7ca05fa8600	2000	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	157:e7ca05fa8600	2001	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2002	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2003	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2004	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2005	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2006	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2007	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2008	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2009	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2010	* @retval None
AnnaBridge	157:e7ca05fa8600	2011	*/
AnnaBridge	157:e7ca05fa8600	2012	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2013	{
AnnaBridge	157:e7ca05fa8600	2014	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	157:e7ca05fa8600	2015	}
AnnaBridge	157:e7ca05fa8600	2016
AnnaBridge	157:e7ca05fa8600	2017	/**
AnnaBridge	157:e7ca05fa8600	2018	* @brief Disable Half transfer interrupt.
AnnaBridge	157:e7ca05fa8600	2019	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	157:e7ca05fa8600	2020	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2021	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2022	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2023	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2024	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2025	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2026	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2027	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2028	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2029	* @retval None
AnnaBridge	157:e7ca05fa8600	2030	*/
AnnaBridge	157:e7ca05fa8600	2031	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2032	{
AnnaBridge	157:e7ca05fa8600	2033	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	157:e7ca05fa8600	2034	}
AnnaBridge	157:e7ca05fa8600	2035
AnnaBridge	157:e7ca05fa8600	2036	/**
AnnaBridge	157:e7ca05fa8600	2037	* @brief Disable Transfer error interrupt.
AnnaBridge	157:e7ca05fa8600	2038	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	157:e7ca05fa8600	2039	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2040	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2041	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2042	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2043	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2044	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2045	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2046	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2047	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2048	* @retval None
AnnaBridge	157:e7ca05fa8600	2049	*/
AnnaBridge	157:e7ca05fa8600	2050	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2051	{
AnnaBridge	157:e7ca05fa8600	2052	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	157:e7ca05fa8600	2053	}
AnnaBridge	157:e7ca05fa8600	2054
AnnaBridge	157:e7ca05fa8600	2055	/**
AnnaBridge	157:e7ca05fa8600	2056	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	157:e7ca05fa8600	2057	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	157:e7ca05fa8600	2058	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2059	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2060	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2061	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2062	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2063	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2064	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2065	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2066	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2067	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	2068	*/
AnnaBridge	157:e7ca05fa8600	2069	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2070	{
AnnaBridge	157:e7ca05fa8600	2071	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	2072	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	157:e7ca05fa8600	2073	}
AnnaBridge	157:e7ca05fa8600	2074
AnnaBridge	157:e7ca05fa8600	2075	/**
AnnaBridge	157:e7ca05fa8600	2076	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	157:e7ca05fa8600	2077	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	157:e7ca05fa8600	2078	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2079	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2080	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2081	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2082	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2083	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2084	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2085	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2086	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2087	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	2088	*/
AnnaBridge	157:e7ca05fa8600	2089	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2090	{
AnnaBridge	157:e7ca05fa8600	2091	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	2092	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	157:e7ca05fa8600	2093	}
AnnaBridge	157:e7ca05fa8600	2094
AnnaBridge	157:e7ca05fa8600	2095	/**
AnnaBridge	157:e7ca05fa8600	2096	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	157:e7ca05fa8600	2097	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	157:e7ca05fa8600	2098	* @param DMAx DMAx Instance
AnnaBridge	157:e7ca05fa8600	2099	* @param Channel This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2100	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	157:e7ca05fa8600	2101	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	157:e7ca05fa8600	2102	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	157:e7ca05fa8600	2103	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	157:e7ca05fa8600	2104	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	157:e7ca05fa8600	2105	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	157:e7ca05fa8600	2106	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	157:e7ca05fa8600	2107	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	2108	*/
AnnaBridge	157:e7ca05fa8600	2109	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	157:e7ca05fa8600	2110	{
AnnaBridge	157:e7ca05fa8600	2111	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	157:e7ca05fa8600	2112	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	157:e7ca05fa8600	2113	}
AnnaBridge	157:e7ca05fa8600	2114
AnnaBridge	157:e7ca05fa8600	2115	/**
AnnaBridge	157:e7ca05fa8600	2116	* @}
AnnaBridge	157:e7ca05fa8600	2117	*/
AnnaBridge	157:e7ca05fa8600	2118
AnnaBridge	157:e7ca05fa8600	2119	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	2120	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	157:e7ca05fa8600	2121	* @{
AnnaBridge	157:e7ca05fa8600	2122	*/
AnnaBridge	157:e7ca05fa8600	2123
AnnaBridge	157:e7ca05fa8600	2124	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	157:e7ca05fa8600	2125	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	157:e7ca05fa8600	2126	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	157:e7ca05fa8600	2127
AnnaBridge	157:e7ca05fa8600	2128	/**
AnnaBridge	157:e7ca05fa8600	2129	* @}
AnnaBridge	157:e7ca05fa8600	2130	*/
AnnaBridge	157:e7ca05fa8600	2131	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	157:e7ca05fa8600	2132
AnnaBridge	157:e7ca05fa8600	2133	/**
AnnaBridge	157:e7ca05fa8600	2134	* @}
AnnaBridge	157:e7ca05fa8600	2135	*/
AnnaBridge	157:e7ca05fa8600	2136
AnnaBridge	157:e7ca05fa8600	2137	/**
AnnaBridge	157:e7ca05fa8600	2138	* @}
AnnaBridge	157:e7ca05fa8600	2139	*/
AnnaBridge	157:e7ca05fa8600	2140
AnnaBridge	157:e7ca05fa8600	2141	#endif /* DMA1 */
AnnaBridge	157:e7ca05fa8600	2142
AnnaBridge	157:e7ca05fa8600	2143	/**
AnnaBridge	157:e7ca05fa8600	2144	* @}
AnnaBridge	157:e7ca05fa8600	2145	*/
AnnaBridge	157:e7ca05fa8600	2146
AnnaBridge	157:e7ca05fa8600	2147	#ifdef __cplusplus
AnnaBridge	157:e7ca05fa8600	2148	}
AnnaBridge	157:e7ca05fa8600	2149	#endif
AnnaBridge	157:e7ca05fa8600	2150
AnnaBridge	157:e7ca05fa8600	2151	#endif /* __STM32L0xx_LL_DMA_H */
AnnaBridge	157:e7ca05fa8600	2152
AnnaBridge	157:e7ca05fa8600	2153	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/