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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_tim_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32l0xx_hal_tim_ex.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @brief Header file of TIM HAL module.
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 7 * @attention
AnnaBridge 157:e7ca05fa8600 8 *
AnnaBridge 157:e7ca05fa8600 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 10 *
AnnaBridge 157:e7ca05fa8600 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 12 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 14 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 17 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 19 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 20 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 21 *
AnnaBridge 157:e7ca05fa8600 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 32 *
AnnaBridge 157:e7ca05fa8600 33 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 34 */
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 37 #ifndef __STM32L0xx_HAL_TIM_EX_H
AnnaBridge 157:e7ca05fa8600 38 #define __STM32L0xx_HAL_TIM_EX_H
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 41 extern "C" {
AnnaBridge 157:e7ca05fa8600 42 #endif
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 45 #include "stm32l0xx_hal_def.h"
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 /** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge 157:e7ca05fa8600 48 * @{
AnnaBridge 157:e7ca05fa8600 49 */
AnnaBridge 157:e7ca05fa8600 50
AnnaBridge 157:e7ca05fa8600 51 /** @defgroup TIMEx TIMEx
AnnaBridge 157:e7ca05fa8600 52 * @{
AnnaBridge 157:e7ca05fa8600 53 */
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 56 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 157:e7ca05fa8600 57 * @{
AnnaBridge 157:e7ca05fa8600 58 */
AnnaBridge 157:e7ca05fa8600 59 /**
AnnaBridge 157:e7ca05fa8600 60 * @brief TIM Master configuration Structure definition
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62 typedef struct {
AnnaBridge 157:e7ca05fa8600 63 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge 157:e7ca05fa8600 64 This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge 157:e7ca05fa8600 65 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge 157:e7ca05fa8600 66 This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge 157:e7ca05fa8600 67 }TIM_MasterConfigTypeDef;
AnnaBridge 157:e7ca05fa8600 68
AnnaBridge 157:e7ca05fa8600 69 /**
AnnaBridge 157:e7ca05fa8600 70 * @}
AnnaBridge 157:e7ca05fa8600 71 */
AnnaBridge 157:e7ca05fa8600 72
AnnaBridge 157:e7ca05fa8600 73 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 74 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
AnnaBridge 157:e7ca05fa8600 75 * @{
AnnaBridge 157:e7ca05fa8600 76 */
AnnaBridge 157:e7ca05fa8600 77
AnnaBridge 157:e7ca05fa8600 78 /** @defgroup TIMEx_Trigger_Selection Trigger selection
AnnaBridge 157:e7ca05fa8600 79 * @{
AnnaBridge 157:e7ca05fa8600 80 */
AnnaBridge 157:e7ca05fa8600 81 #define TIM_TRGO_RESET ((uint32_t)0x0000U)
AnnaBridge 157:e7ca05fa8600 82 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge 157:e7ca05fa8600 83 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge 157:e7ca05fa8600 84 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 157:e7ca05fa8600 85 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge 157:e7ca05fa8600 86 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
AnnaBridge 157:e7ca05fa8600 87 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
AnnaBridge 157:e7ca05fa8600 88 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 157:e7ca05fa8600 89
AnnaBridge 157:e7ca05fa8600 90 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
AnnaBridge 157:e7ca05fa8600 91 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
AnnaBridge 157:e7ca05fa8600 92 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
AnnaBridge 157:e7ca05fa8600 93 ((__SOURCE__) == TIM_TRGO_OC1) || \
AnnaBridge 157:e7ca05fa8600 94 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
AnnaBridge 157:e7ca05fa8600 95 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
AnnaBridge 157:e7ca05fa8600 96 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
AnnaBridge 157:e7ca05fa8600 97 ((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge 157:e7ca05fa8600 98
AnnaBridge 157:e7ca05fa8600 99 /**
AnnaBridge 157:e7ca05fa8600 100 * @}
AnnaBridge 157:e7ca05fa8600 101 */
AnnaBridge 157:e7ca05fa8600 102
AnnaBridge 157:e7ca05fa8600 103 /** @defgroup TIMEx_Remap Remaping
AnnaBridge 157:e7ca05fa8600 104 * @{
AnnaBridge 157:e7ca05fa8600 105 */
AnnaBridge 157:e7ca05fa8600 106 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
AnnaBridge 157:e7ca05fa8600 107 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
AnnaBridge 157:e7ca05fa8600 108
AnnaBridge 157:e7ca05fa8600 109 #define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 110 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
AnnaBridge 157:e7ca05fa8600 111 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
AnnaBridge 157:e7ca05fa8600 112 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
AnnaBridge 157:e7ca05fa8600 113 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
AnnaBridge 157:e7ca05fa8600 114 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge 157:e7ca05fa8600 115
AnnaBridge 157:e7ca05fa8600 116 #elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
AnnaBridge 157:e7ca05fa8600 117
AnnaBridge 157:e7ca05fa8600 118 #define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 119 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
AnnaBridge 157:e7ca05fa8600 120 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
AnnaBridge 157:e7ca05fa8600 121 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
AnnaBridge 157:e7ca05fa8600 122 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #else
AnnaBridge 157:e7ca05fa8600 125
AnnaBridge 157:e7ca05fa8600 126 #define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 127 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
AnnaBridge 157:e7ca05fa8600 128 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
AnnaBridge 157:e7ca05fa8600 129 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
AnnaBridge 157:e7ca05fa8600 130 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge 157:e7ca05fa8600 131
AnnaBridge 157:e7ca05fa8600 132 #endif
AnnaBridge 157:e7ca05fa8600 133
AnnaBridge 157:e7ca05fa8600 134
AnnaBridge 157:e7ca05fa8600 135
AnnaBridge 157:e7ca05fa8600 136 #define TIM2_TI4_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 137 #define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0
AnnaBridge 157:e7ca05fa8600 138 #define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1
AnnaBridge 157:e7ca05fa8600 139
AnnaBridge 157:e7ca05fa8600 140 #define TIM21_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 141 #define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0
AnnaBridge 157:e7ca05fa8600 142 #define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1
AnnaBridge 157:e7ca05fa8600 143 #define TIM21_ETR_LSE TIM21_OR_ETR_RMP
AnnaBridge 157:e7ca05fa8600 144 #define TIM21_TI1_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 145 #define TIM21_TI1_MCO TIM21_OR_TI1_RMP
AnnaBridge 157:e7ca05fa8600 146 #define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0
AnnaBridge 157:e7ca05fa8600 147 #define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1
AnnaBridge 157:e7ca05fa8600 148 #define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1)
AnnaBridge 157:e7ca05fa8600 149 #define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2
AnnaBridge 157:e7ca05fa8600 150 #define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0)
AnnaBridge 157:e7ca05fa8600 151 #define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1)
AnnaBridge 157:e7ca05fa8600 152 #define TIM21_TI2_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 153 #define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP
AnnaBridge 157:e7ca05fa8600 154
AnnaBridge 157:e7ca05fa8600 155 #if !defined(STM32L011xx) && !defined(STM32L021xx)
AnnaBridge 167:84c0a372a020 156 #define TIM22_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 157 #define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0
AnnaBridge 157:e7ca05fa8600 158 #define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1
AnnaBridge 167:84c0a372a020 159 #define TIM22_ETR_LSE TIM22_OR_ETR_RMP
AnnaBridge 157:e7ca05fa8600 160 #define TIM22_TI1_GPIO1 ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 161 #define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0
AnnaBridge 157:e7ca05fa8600 162 #define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1
AnnaBridge 157:e7ca05fa8600 163 #define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP
AnnaBridge 157:e7ca05fa8600 164 #endif
AnnaBridge 157:e7ca05fa8600 165
AnnaBridge 157:e7ca05fa8600 166 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
AnnaBridge 157:e7ca05fa8600 167 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
AnnaBridge 157:e7ca05fa8600 168
AnnaBridge 157:e7ca05fa8600 169 #define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 170 #define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP
AnnaBridge 157:e7ca05fa8600 171 #define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 172 #define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP
AnnaBridge 157:e7ca05fa8600 173 #define TIM3_TI1_USB_SOF ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 174 #define TIM3_TI1_GPIO TIM3_OR_TI1_RMP
AnnaBridge 157:e7ca05fa8600 175 #define TIM3_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge 157:e7ca05fa8600 176 #define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1
AnnaBridge 157:e7ca05fa8600 177
AnnaBridge 157:e7ca05fa8600 178 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */
AnnaBridge 157:e7ca05fa8600 179
AnnaBridge 157:e7ca05fa8600 180
AnnaBridge 157:e7ca05fa8600 181 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
AnnaBridge 157:e7ca05fa8600 182 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
AnnaBridge 157:e7ca05fa8600 183
AnnaBridge 157:e7ca05fa8600 184
AnnaBridge 157:e7ca05fa8600 185 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge 167:84c0a372a020 186 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
AnnaBridge 167:84c0a372a020 187 (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
AnnaBridge 167:84c0a372a020 188 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \
AnnaBridge 167:84c0a372a020 189 (((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP))))
AnnaBridge 157:e7ca05fa8600 190
AnnaBridge 157:e7ca05fa8600 191 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 167:84c0a372a020 192 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 193 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 157:e7ca05fa8600 194 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 157:e7ca05fa8600 195 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
AnnaBridge 167:84c0a372a020 196 (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 197 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 157:e7ca05fa8600 198 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 157:e7ca05fa8600 199 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
AnnaBridge 167:84c0a372a020 200 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 201 ((__CHANNEL__) == TIM_CHANNEL_2))) || \
AnnaBridge 167:84c0a372a020 202 (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 203 ((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge 157:e7ca05fa8600 204
AnnaBridge 157:e7ca05fa8600 205 #elif defined (STM32L011xx) || defined (STM32L021xx)
AnnaBridge 157:e7ca05fa8600 206
AnnaBridge 157:e7ca05fa8600 207 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge 167:84c0a372a020 208 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
AnnaBridge 167:84c0a372a020 209 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
AnnaBridge 157:e7ca05fa8600 210
AnnaBridge 157:e7ca05fa8600 211 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 167:84c0a372a020 212 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 213 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 157:e7ca05fa8600 214 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 157:e7ca05fa8600 215 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
AnnaBridge 167:84c0a372a020 216 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 217 ((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge 157:e7ca05fa8600 218
AnnaBridge 157:e7ca05fa8600 219 #else
AnnaBridge 157:e7ca05fa8600 220
AnnaBridge 157:e7ca05fa8600 221 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge 167:84c0a372a020 222 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
AnnaBridge 167:84c0a372a020 223 (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
AnnaBridge 167:84c0a372a020 224 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
AnnaBridge 157:e7ca05fa8600 225
AnnaBridge 157:e7ca05fa8600 226 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 167:84c0a372a020 227 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 228 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 157:e7ca05fa8600 229 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 157:e7ca05fa8600 230 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
AnnaBridge 167:84c0a372a020 231 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 232 ((__CHANNEL__) == TIM_CHANNEL_2))) || \
AnnaBridge 167:84c0a372a020 233 (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 157:e7ca05fa8600 234 ((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge 157:e7ca05fa8600 235
AnnaBridge 157:e7ca05fa8600 236 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */
AnnaBridge 157:e7ca05fa8600 237
AnnaBridge 157:e7ca05fa8600 238
AnnaBridge 157:e7ca05fa8600 239 /**
AnnaBridge 157:e7ca05fa8600 240 * @}
AnnaBridge 157:e7ca05fa8600 241 */
AnnaBridge 157:e7ca05fa8600 242
AnnaBridge 157:e7ca05fa8600 243 /**
AnnaBridge 157:e7ca05fa8600 244 * @}
AnnaBridge 157:e7ca05fa8600 245 */
AnnaBridge 157:e7ca05fa8600 246
AnnaBridge 157:e7ca05fa8600 247
AnnaBridge 157:e7ca05fa8600 248 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 249 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 250 /* Control functions ***********************************************************/
AnnaBridge 157:e7ca05fa8600 251
AnnaBridge 157:e7ca05fa8600 252 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
AnnaBridge 157:e7ca05fa8600 253 * @{
AnnaBridge 157:e7ca05fa8600 254 */
AnnaBridge 157:e7ca05fa8600 255
AnnaBridge 157:e7ca05fa8600 256 /** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions
AnnaBridge 157:e7ca05fa8600 257 * @{
AnnaBridge 157:e7ca05fa8600 258 */
AnnaBridge 157:e7ca05fa8600 259
AnnaBridge 157:e7ca05fa8600 260 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
AnnaBridge 157:e7ca05fa8600 261 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
AnnaBridge 157:e7ca05fa8600 262
AnnaBridge 157:e7ca05fa8600 263 /**
AnnaBridge 157:e7ca05fa8600 264 * @}
AnnaBridge 157:e7ca05fa8600 265 */
AnnaBridge 157:e7ca05fa8600 266
AnnaBridge 157:e7ca05fa8600 267 /**
AnnaBridge 157:e7ca05fa8600 268 * @}
AnnaBridge 157:e7ca05fa8600 269 */
AnnaBridge 157:e7ca05fa8600 270
AnnaBridge 157:e7ca05fa8600 271 /**
AnnaBridge 157:e7ca05fa8600 272 * @}
AnnaBridge 157:e7ca05fa8600 273 */
AnnaBridge 157:e7ca05fa8600 274
AnnaBridge 157:e7ca05fa8600 275 /**
AnnaBridge 157:e7ca05fa8600 276 * @}
AnnaBridge 157:e7ca05fa8600 277 */
AnnaBridge 157:e7ca05fa8600 278 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 279 }
AnnaBridge 157:e7ca05fa8600 280 #endif
AnnaBridge 157:e7ca05fa8600 281
AnnaBridge 157:e7ca05fa8600 282 #endif /* __STM32L0xx_HAL_TIM_EX_H */
AnnaBridge 157:e7ca05fa8600 283
AnnaBridge 157:e7ca05fa8600 284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 157:e7ca05fa8600 285