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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 143:86740a56073b | 1 | /** |
| AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_hal_pwr.h |
| AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
| AnnaBridge | 143:86740a56073b | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 7 | * @attention |
| AnnaBridge | 143:86740a56073b | 8 | * |
| AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 143:86740a56073b | 10 | * |
| AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
| AnnaBridge | 143:86740a56073b | 21 | * |
| AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 143:86740a56073b | 32 | * |
| AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 34 | */ |
| AnnaBridge | 143:86740a56073b | 35 | |
| AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 37 | #ifndef __STM32L0xx_HAL_PWR_H |
| AnnaBridge | 143:86740a56073b | 38 | #define __STM32L0xx_HAL_PWR_H |
| AnnaBridge | 143:86740a56073b | 39 | |
| AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 41 | extern "C" { |
| AnnaBridge | 143:86740a56073b | 42 | #endif |
| AnnaBridge | 143:86740a56073b | 43 | |
| AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 45 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 143:86740a56073b | 46 | |
| AnnaBridge | 143:86740a56073b | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 143:86740a56073b | 48 | * @{ |
| AnnaBridge | 143:86740a56073b | 49 | */ |
| AnnaBridge | 143:86740a56073b | 50 | |
| AnnaBridge | 143:86740a56073b | 51 | /** @defgroup PWR PWR |
| AnnaBridge | 143:86740a56073b | 52 | * @{ |
| AnnaBridge | 143:86740a56073b | 53 | */ |
| AnnaBridge | 143:86740a56073b | 54 | |
| AnnaBridge | 143:86740a56073b | 55 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 143:86740a56073b | 56 | * @{ |
| AnnaBridge | 143:86740a56073b | 57 | */ |
| AnnaBridge | 143:86740a56073b | 58 | |
| AnnaBridge | 143:86740a56073b | 59 | /** |
| AnnaBridge | 143:86740a56073b | 60 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 143:86740a56073b | 61 | */ |
| AnnaBridge | 143:86740a56073b | 62 | typedef struct |
| AnnaBridge | 143:86740a56073b | 63 | { |
| AnnaBridge | 143:86740a56073b | 64 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 143:86740a56073b | 65 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| AnnaBridge | 143:86740a56073b | 66 | |
| AnnaBridge | 143:86740a56073b | 67 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 143:86740a56073b | 68 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| AnnaBridge | 143:86740a56073b | 69 | }PWR_PVDTypeDef; |
| AnnaBridge | 143:86740a56073b | 70 | |
| AnnaBridge | 143:86740a56073b | 71 | /** |
| AnnaBridge | 143:86740a56073b | 72 | * @} |
| AnnaBridge | 143:86740a56073b | 73 | */ |
| AnnaBridge | 143:86740a56073b | 74 | |
| AnnaBridge | 143:86740a56073b | 75 | /** @addtogroup PWR_Private |
| AnnaBridge | 143:86740a56073b | 76 | * @{ |
| AnnaBridge | 143:86740a56073b | 77 | */ |
| AnnaBridge | 143:86740a56073b | 78 | |
| AnnaBridge | 143:86740a56073b | 79 | #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 143:86740a56073b | 80 | |
| AnnaBridge | 143:86740a56073b | 81 | /** |
| AnnaBridge | 143:86740a56073b | 82 | * @} |
| AnnaBridge | 143:86740a56073b | 83 | */ |
| AnnaBridge | 143:86740a56073b | 84 | |
| AnnaBridge | 143:86740a56073b | 85 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 143:86740a56073b | 86 | * @{ |
| AnnaBridge | 143:86740a56073b | 87 | */ |
| AnnaBridge | 143:86740a56073b | 88 | |
| AnnaBridge | 143:86740a56073b | 89 | /** @defgroup PWR_register_alias_address PWR Register alias address |
| AnnaBridge | 143:86740a56073b | 90 | * @{ |
| AnnaBridge | 143:86740a56073b | 91 | */ |
| AnnaBridge | 143:86740a56073b | 92 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 |
| AnnaBridge | 143:86740a56073b | 93 | #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 |
| AnnaBridge | 143:86740a56073b | 94 | #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || \ |
| AnnaBridge | 143:86740a56073b | 95 | defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 143:86740a56073b | 96 | #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 |
| AnnaBridge | 143:86740a56073b | 97 | #endif |
| AnnaBridge | 143:86740a56073b | 98 | /** |
| AnnaBridge | 143:86740a56073b | 99 | * @} |
| AnnaBridge | 143:86740a56073b | 100 | */ |
| AnnaBridge | 143:86740a56073b | 101 | |
| AnnaBridge | 143:86740a56073b | 102 | /** @defgroup PWR_PVD_detection_level PVD detection level |
| AnnaBridge | 143:86740a56073b | 103 | * @{ |
| AnnaBridge | 143:86740a56073b | 104 | */ |
| AnnaBridge | 143:86740a56073b | 105 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
| AnnaBridge | 143:86740a56073b | 106 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
| AnnaBridge | 143:86740a56073b | 107 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
| AnnaBridge | 143:86740a56073b | 108 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
| AnnaBridge | 143:86740a56073b | 109 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
| AnnaBridge | 143:86740a56073b | 110 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
| AnnaBridge | 143:86740a56073b | 111 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
| AnnaBridge | 143:86740a56073b | 112 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
| AnnaBridge | 143:86740a56073b | 113 | (Compare internally to VREFINT) */ |
| AnnaBridge | 143:86740a56073b | 114 | /** |
| AnnaBridge | 143:86740a56073b | 115 | * @} |
| AnnaBridge | 143:86740a56073b | 116 | */ |
| AnnaBridge | 143:86740a56073b | 117 | |
| AnnaBridge | 143:86740a56073b | 118 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| AnnaBridge | 143:86740a56073b | 119 | * @{ |
| AnnaBridge | 143:86740a56073b | 120 | */ |
| AnnaBridge | 143:86740a56073b | 121 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ |
| AnnaBridge | 143:86740a56073b | 122 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 123 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 124 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 125 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 126 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 127 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 143:86740a56073b | 128 | |
| AnnaBridge | 143:86740a56073b | 129 | /** |
| AnnaBridge | 143:86740a56073b | 130 | * @} |
| AnnaBridge | 143:86740a56073b | 131 | */ |
| AnnaBridge | 143:86740a56073b | 132 | |
| AnnaBridge | 143:86740a56073b | 133 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| AnnaBridge | 143:86740a56073b | 134 | * @{ |
| AnnaBridge | 143:86740a56073b | 135 | */ |
| AnnaBridge | 143:86740a56073b | 136 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) |
| AnnaBridge | 143:86740a56073b | 137 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
| AnnaBridge | 143:86740a56073b | 138 | |
| AnnaBridge | 143:86740a56073b | 139 | /** |
| AnnaBridge | 143:86740a56073b | 140 | * @} |
| AnnaBridge | 143:86740a56073b | 141 | */ |
| AnnaBridge | 143:86740a56073b | 142 | |
| AnnaBridge | 143:86740a56073b | 143 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 143:86740a56073b | 144 | * @{ |
| AnnaBridge | 143:86740a56073b | 145 | */ |
| AnnaBridge | 143:86740a56073b | 146 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) |
| AnnaBridge | 143:86740a56073b | 147 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) |
| AnnaBridge | 143:86740a56073b | 148 | /** |
| AnnaBridge | 143:86740a56073b | 149 | * @} |
| AnnaBridge | 143:86740a56073b | 150 | */ |
| AnnaBridge | 143:86740a56073b | 151 | |
| AnnaBridge | 143:86740a56073b | 152 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 143:86740a56073b | 153 | * @{ |
| AnnaBridge | 143:86740a56073b | 154 | */ |
| AnnaBridge | 143:86740a56073b | 155 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) |
| AnnaBridge | 143:86740a56073b | 156 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) |
| AnnaBridge | 143:86740a56073b | 157 | /** |
| AnnaBridge | 143:86740a56073b | 158 | * @} |
| AnnaBridge | 143:86740a56073b | 159 | */ |
| AnnaBridge | 143:86740a56073b | 160 | |
| AnnaBridge | 143:86740a56073b | 161 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
| AnnaBridge | 143:86740a56073b | 162 | * @{ |
| AnnaBridge | 143:86740a56073b | 163 | */ |
| AnnaBridge | 143:86740a56073b | 164 | |
| AnnaBridge | 143:86740a56073b | 165 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
| AnnaBridge | 143:86740a56073b | 166 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
| AnnaBridge | 143:86740a56073b | 167 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
| AnnaBridge | 143:86740a56073b | 168 | |
| AnnaBridge | 143:86740a56073b | 169 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| AnnaBridge | 143:86740a56073b | 170 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
| AnnaBridge | 143:86740a56073b | 171 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
| AnnaBridge | 143:86740a56073b | 172 | /** |
| AnnaBridge | 143:86740a56073b | 173 | * @} |
| AnnaBridge | 143:86740a56073b | 174 | */ |
| AnnaBridge | 143:86740a56073b | 175 | |
| AnnaBridge | 143:86740a56073b | 176 | /** @defgroup PWR_Flag PWR Flag |
| AnnaBridge | 143:86740a56073b | 177 | * @{ |
| AnnaBridge | 143:86740a56073b | 178 | */ |
| AnnaBridge | 143:86740a56073b | 179 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 143:86740a56073b | 180 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 143:86740a56073b | 181 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| AnnaBridge | 143:86740a56073b | 182 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
| AnnaBridge | 143:86740a56073b | 183 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
| AnnaBridge | 143:86740a56073b | 184 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
| AnnaBridge | 143:86740a56073b | 185 | |
| AnnaBridge | 143:86740a56073b | 186 | |
| AnnaBridge | 143:86740a56073b | 187 | /** |
| AnnaBridge | 143:86740a56073b | 188 | * @} |
| AnnaBridge | 143:86740a56073b | 189 | */ |
| AnnaBridge | 143:86740a56073b | 190 | |
| AnnaBridge | 143:86740a56073b | 191 | /** |
| AnnaBridge | 143:86740a56073b | 192 | * @} |
| AnnaBridge | 143:86740a56073b | 193 | */ |
| AnnaBridge | 143:86740a56073b | 194 | |
| AnnaBridge | 143:86740a56073b | 195 | /** @defgroup PWR_Exported_Macro PWR Exported Macros |
| AnnaBridge | 143:86740a56073b | 196 | * @{ |
| AnnaBridge | 143:86740a56073b | 197 | */ |
| AnnaBridge | 143:86740a56073b | 198 | /** @brief macros configure the main internal regulator output voltage. |
| AnnaBridge | 143:86740a56073b | 199 | * When exiting Low Power Run Mode or during dynamic voltage scaling configuration, |
| AnnaBridge | 143:86740a56073b | 200 | * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator |
| AnnaBridge | 143:86740a56073b | 201 | * to reach main mode (resp. to get stabilized) for a transition from 0 to 1. |
| AnnaBridge | 143:86740a56073b | 202 | * Only then the clock can be increased. |
| AnnaBridge | 143:86740a56073b | 203 | * |
| AnnaBridge | 143:86740a56073b | 204 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| AnnaBridge | 143:86740a56073b | 205 | * a tradeoff between performance and power consumption when the device does |
| AnnaBridge | 143:86740a56073b | 206 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| AnnaBridge | 143:86740a56073b | 207 | * This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 208 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
| AnnaBridge | 143:86740a56073b | 209 | * System frequency up to 32 MHz. |
| AnnaBridge | 143:86740a56073b | 210 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
| AnnaBridge | 143:86740a56073b | 211 | * System frequency up to 16 MHz. |
| AnnaBridge | 143:86740a56073b | 212 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
| AnnaBridge | 143:86740a56073b | 213 | * System frequency up to 4.2 MHz |
| AnnaBridge | 143:86740a56073b | 214 | * @retval None |
| AnnaBridge | 143:86740a56073b | 215 | */ |
| AnnaBridge | 143:86740a56073b | 216 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
| AnnaBridge | 143:86740a56073b | 217 | |
| AnnaBridge | 143:86740a56073b | 218 | /** @brief Check PWR flag is set or not. |
| AnnaBridge | 143:86740a56073b | 219 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 143:86740a56073b | 220 | * This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 221 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| AnnaBridge | 143:86740a56073b | 222 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
| AnnaBridge | 143:86740a56073b | 223 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
| AnnaBridge | 143:86740a56073b | 224 | * An additional wakeup event is detected if the WKUP pin is enabled |
| AnnaBridge | 143:86740a56073b | 225 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| AnnaBridge | 143:86740a56073b | 226 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| AnnaBridge | 143:86740a56073b | 227 | * resumed from StandBy mode. |
| AnnaBridge | 143:86740a56073b | 228 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| AnnaBridge | 143:86740a56073b | 229 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. |
| AnnaBridge | 143:86740a56073b | 230 | * For this reason, this bit is equal to 0 after Standby or reset |
| AnnaBridge | 143:86740a56073b | 231 | * until the PVDE bit is set. |
| AnnaBridge | 143:86740a56073b | 232 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
| AnnaBridge | 143:86740a56073b | 233 | * This bit indicates the state of the internal voltage reference, VREFINT. |
| AnnaBridge | 143:86740a56073b | 234 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
| AnnaBridge | 143:86740a56073b | 235 | * the internal regulator to be ready after the voltage range is changed. |
| AnnaBridge | 143:86740a56073b | 236 | * The VOSF bit indicates that the regulator has reached the voltage level |
| AnnaBridge | 143:86740a56073b | 237 | * defined with bits VOS of PWR_CR register. |
| AnnaBridge | 143:86740a56073b | 238 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
| AnnaBridge | 143:86740a56073b | 239 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
| AnnaBridge | 143:86740a56073b | 240 | * A polling on this bit is recommended to wait for the regulator main mode. |
| AnnaBridge | 143:86740a56073b | 241 | * This bit is reset by hardware when the regulator is ready. |
| AnnaBridge | 143:86740a56073b | 242 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 143:86740a56073b | 243 | */ |
| AnnaBridge | 143:86740a56073b | 244 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 143:86740a56073b | 245 | |
| AnnaBridge | 143:86740a56073b | 246 | /** @brief Clear the PWR pending flags. |
| AnnaBridge | 143:86740a56073b | 247 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 143:86740a56073b | 248 | * This parameter can be one of the following values: |
| AnnaBridge | 143:86740a56073b | 249 | * @arg PWR_FLAG_WU: Wake Up flag |
| AnnaBridge | 143:86740a56073b | 250 | * @arg PWR_FLAG_SB: StandBy flag |
| AnnaBridge | 143:86740a56073b | 251 | */ |
| AnnaBridge | 143:86740a56073b | 252 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U) |
| AnnaBridge | 143:86740a56073b | 253 | |
| AnnaBridge | 143:86740a56073b | 254 | /** |
| AnnaBridge | 143:86740a56073b | 255 | * @brief Enable interrupt on PVD Exti Line 16. |
| AnnaBridge | 143:86740a56073b | 256 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 257 | */ |
| AnnaBridge | 143:86740a56073b | 258 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 259 | |
| AnnaBridge | 143:86740a56073b | 260 | /** |
| AnnaBridge | 143:86740a56073b | 261 | * @brief Disable interrupt on PVD Exti Line 16. |
| AnnaBridge | 143:86740a56073b | 262 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 263 | */ |
| AnnaBridge | 143:86740a56073b | 264 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 265 | |
| AnnaBridge | 143:86740a56073b | 266 | /** |
| AnnaBridge | 143:86740a56073b | 267 | * @brief Enable event on PVD Exti Line 16. |
| AnnaBridge | 143:86740a56073b | 268 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 269 | */ |
| AnnaBridge | 143:86740a56073b | 270 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 271 | |
| AnnaBridge | 143:86740a56073b | 272 | /** |
| AnnaBridge | 143:86740a56073b | 273 | * @brief Disable event on PVD Exti Line 16. |
| AnnaBridge | 143:86740a56073b | 274 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 275 | */ |
| AnnaBridge | 143:86740a56073b | 276 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 277 | |
| AnnaBridge | 143:86740a56073b | 278 | |
| AnnaBridge | 143:86740a56073b | 279 | /** |
| AnnaBridge | 143:86740a56073b | 280 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| AnnaBridge | 143:86740a56073b | 281 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 282 | */ |
| AnnaBridge | 143:86740a56073b | 283 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 284 | |
| AnnaBridge | 143:86740a56073b | 285 | |
| AnnaBridge | 143:86740a56073b | 286 | /** |
| AnnaBridge | 143:86740a56073b | 287 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 143:86740a56073b | 288 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 289 | */ |
| AnnaBridge | 143:86740a56073b | 290 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 291 | |
| AnnaBridge | 143:86740a56073b | 292 | |
| AnnaBridge | 143:86740a56073b | 293 | /** |
| AnnaBridge | 143:86740a56073b | 294 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| AnnaBridge | 143:86740a56073b | 295 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 296 | */ |
| AnnaBridge | 143:86740a56073b | 297 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 298 | |
| AnnaBridge | 143:86740a56073b | 299 | /** |
| AnnaBridge | 143:86740a56073b | 300 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 143:86740a56073b | 301 | * This parameter can be: |
| AnnaBridge | 143:86740a56073b | 302 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 303 | */ |
| AnnaBridge | 143:86740a56073b | 304 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 305 | |
| AnnaBridge | 143:86740a56073b | 306 | /** |
| AnnaBridge | 143:86740a56073b | 307 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 143:86740a56073b | 308 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 309 | */ |
| AnnaBridge | 143:86740a56073b | 310 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); |
| AnnaBridge | 143:86740a56073b | 311 | |
| AnnaBridge | 143:86740a56073b | 312 | /** |
| AnnaBridge | 143:86740a56073b | 313 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 143:86740a56073b | 314 | * This parameter can be: |
| AnnaBridge | 143:86740a56073b | 315 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 316 | */ |
| AnnaBridge | 143:86740a56073b | 317 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); |
| AnnaBridge | 143:86740a56073b | 318 | |
| AnnaBridge | 143:86740a56073b | 319 | |
| AnnaBridge | 143:86740a56073b | 320 | |
| AnnaBridge | 143:86740a56073b | 321 | /** |
| AnnaBridge | 143:86740a56073b | 322 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| AnnaBridge | 143:86740a56073b | 323 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 143:86740a56073b | 324 | */ |
| AnnaBridge | 143:86740a56073b | 325 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 143:86740a56073b | 326 | |
| AnnaBridge | 143:86740a56073b | 327 | /** |
| AnnaBridge | 143:86740a56073b | 328 | * @brief Clear the PVD EXTI flag. |
| AnnaBridge | 143:86740a56073b | 329 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 330 | */ |
| AnnaBridge | 143:86740a56073b | 331 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 143:86740a56073b | 332 | |
| AnnaBridge | 143:86740a56073b | 333 | /** |
| AnnaBridge | 143:86740a56073b | 334 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 143:86740a56073b | 335 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 336 | */ |
| AnnaBridge | 143:86740a56073b | 337 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 338 | |
| AnnaBridge | 143:86740a56073b | 339 | /** |
| AnnaBridge | 143:86740a56073b | 340 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 143:86740a56073b | 341 | * @retval None. |
| AnnaBridge | 143:86740a56073b | 342 | */ |
| AnnaBridge | 143:86740a56073b | 343 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 143:86740a56073b | 344 | |
| AnnaBridge | 143:86740a56073b | 345 | /** |
| AnnaBridge | 143:86740a56073b | 346 | * @} |
| AnnaBridge | 143:86740a56073b | 347 | */ |
| AnnaBridge | 143:86740a56073b | 348 | |
| AnnaBridge | 143:86740a56073b | 349 | /** @addtogroup PWR_Private |
| AnnaBridge | 143:86740a56073b | 350 | * @{ |
| AnnaBridge | 143:86740a56073b | 351 | */ |
| AnnaBridge | 143:86740a56073b | 352 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 143:86740a56073b | 353 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 143:86740a56073b | 354 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 143:86740a56073b | 355 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 143:86740a56073b | 356 | |
| AnnaBridge | 143:86740a56073b | 357 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 143:86740a56073b | 358 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 143:86740a56073b | 359 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 143:86740a56073b | 360 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| AnnaBridge | 143:86740a56073b | 361 | |
| AnnaBridge | 143:86740a56073b | 362 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 143:86740a56073b | 363 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 143:86740a56073b | 364 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 143:86740a56073b | 365 | ((PIN) == PWR_WAKEUP_PIN3)) |
| AnnaBridge | 143:86740a56073b | 366 | #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
| AnnaBridge | 143:86740a56073b | 367 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 143:86740a56073b | 368 | ((PIN) == PWR_WAKEUP_PIN2)) |
| AnnaBridge | 143:86740a56073b | 369 | #elif defined (STM32L031xx) || defined (STM32L041xx) |
| AnnaBridge | 143:86740a56073b | 370 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 143:86740a56073b | 371 | ((PIN) == PWR_WAKEUP_PIN2)) |
| AnnaBridge | 143:86740a56073b | 372 | #elif defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 143:86740a56073b | 373 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 143:86740a56073b | 374 | ((PIN) == PWR_WAKEUP_PIN3)) |
| AnnaBridge | 143:86740a56073b | 375 | #endif |
| AnnaBridge | 143:86740a56073b | 376 | |
| AnnaBridge | 143:86740a56073b | 377 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 143:86740a56073b | 378 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 143:86740a56073b | 379 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 143:86740a56073b | 380 | |
| AnnaBridge | 143:86740a56073b | 381 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| AnnaBridge | 143:86740a56073b | 382 | |
| AnnaBridge | 143:86740a56073b | 383 | /** |
| AnnaBridge | 143:86740a56073b | 384 | * @} |
| AnnaBridge | 143:86740a56073b | 385 | */ |
| AnnaBridge | 143:86740a56073b | 386 | |
| AnnaBridge | 143:86740a56073b | 387 | /* Include PWR HAL Extension module */ |
| AnnaBridge | 143:86740a56073b | 388 | #include "stm32l0xx_hal_pwr_ex.h" |
| AnnaBridge | 143:86740a56073b | 389 | |
| AnnaBridge | 143:86740a56073b | 390 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 143:86740a56073b | 391 | * @{ |
| AnnaBridge | 143:86740a56073b | 392 | */ |
| AnnaBridge | 143:86740a56073b | 393 | |
| AnnaBridge | 143:86740a56073b | 394 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 143:86740a56073b | 395 | * @{ |
| AnnaBridge | 143:86740a56073b | 396 | */ |
| AnnaBridge | 143:86740a56073b | 397 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 143:86740a56073b | 398 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 143:86740a56073b | 399 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 143:86740a56073b | 400 | /** |
| AnnaBridge | 143:86740a56073b | 401 | * @} |
| AnnaBridge | 143:86740a56073b | 402 | */ |
| AnnaBridge | 143:86740a56073b | 403 | |
| AnnaBridge | 143:86740a56073b | 404 | /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions |
| AnnaBridge | 143:86740a56073b | 405 | * @{ |
| AnnaBridge | 143:86740a56073b | 406 | */ |
| AnnaBridge | 143:86740a56073b | 407 | |
| AnnaBridge | 143:86740a56073b | 408 | /* PVD control functions ************************************************/ |
| AnnaBridge | 143:86740a56073b | 409 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 143:86740a56073b | 410 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 143:86740a56073b | 411 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 143:86740a56073b | 412 | void HAL_PWR_PVD_IRQHandler(void); |
| AnnaBridge | 143:86740a56073b | 413 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 143:86740a56073b | 414 | |
| AnnaBridge | 143:86740a56073b | 415 | /* WakeUp pins configuration functions ****************************************/ |
| AnnaBridge | 143:86740a56073b | 416 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 143:86740a56073b | 417 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 143:86740a56073b | 418 | |
| AnnaBridge | 143:86740a56073b | 419 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 143:86740a56073b | 420 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 143:86740a56073b | 421 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 143:86740a56073b | 422 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 143:86740a56073b | 423 | |
| AnnaBridge | 143:86740a56073b | 424 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 143:86740a56073b | 425 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 143:86740a56073b | 426 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 143:86740a56073b | 427 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 143:86740a56073b | 428 | |
| AnnaBridge | 143:86740a56073b | 429 | /** |
| AnnaBridge | 143:86740a56073b | 430 | * @} |
| AnnaBridge | 143:86740a56073b | 431 | */ |
| AnnaBridge | 143:86740a56073b | 432 | |
| AnnaBridge | 143:86740a56073b | 433 | /** |
| AnnaBridge | 143:86740a56073b | 434 | * @} |
| AnnaBridge | 143:86740a56073b | 435 | */ |
| AnnaBridge | 143:86740a56073b | 436 | |
| AnnaBridge | 143:86740a56073b | 437 | /* Define the private group ***********************************/ |
| AnnaBridge | 143:86740a56073b | 438 | /**************************************************************/ |
| AnnaBridge | 143:86740a56073b | 439 | /** @defgroup PWR_Private PWR Private |
| AnnaBridge | 143:86740a56073b | 440 | * @{ |
| AnnaBridge | 143:86740a56073b | 441 | */ |
| AnnaBridge | 143:86740a56073b | 442 | /** |
| AnnaBridge | 143:86740a56073b | 443 | * @} |
| AnnaBridge | 143:86740a56073b | 444 | */ |
| AnnaBridge | 143:86740a56073b | 445 | /**************************************************************/ |
| AnnaBridge | 143:86740a56073b | 446 | |
| AnnaBridge | 143:86740a56073b | 447 | /** |
| AnnaBridge | 143:86740a56073b | 448 | * @} |
| AnnaBridge | 143:86740a56073b | 449 | */ |
| AnnaBridge | 143:86740a56073b | 450 | |
| AnnaBridge | 143:86740a56073b | 451 | /** |
| AnnaBridge | 143:86740a56073b | 452 | * @} |
| AnnaBridge | 143:86740a56073b | 453 | */ |
| AnnaBridge | 143:86740a56073b | 454 | |
| AnnaBridge | 143:86740a56073b | 455 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 456 | } |
| AnnaBridge | 143:86740a56073b | 457 | #endif |
| AnnaBridge | 143:86740a56073b | 458 | |
| AnnaBridge | 143:86740a56073b | 459 | |
| AnnaBridge | 143:86740a56073b | 460 | #endif /* __STM32L0xx_HAL_PWR_H */ |
| AnnaBridge | 143:86740a56073b | 461 | |
| AnnaBridge | 143:86740a56073b | 462 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 143:86740a56073b | 463 |
