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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 157:e7ca05fa8600 | 1 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 2 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 3 | * @file stm32l0xx_hal_dma.h |
| AnnaBridge | 157:e7ca05fa8600 | 4 | * @author MCD Application Team |
| AnnaBridge | 157:e7ca05fa8600 | 5 | * @brief Header file of DMA HAL module. |
| AnnaBridge | 157:e7ca05fa8600 | 6 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 7 | * @attention |
| AnnaBridge | 157:e7ca05fa8600 | 8 | * |
| AnnaBridge | 157:e7ca05fa8600 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 157:e7ca05fa8600 | 10 | * |
| AnnaBridge | 157:e7ca05fa8600 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 157:e7ca05fa8600 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 157:e7ca05fa8600 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 157:e7ca05fa8600 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 157:e7ca05fa8600 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 157:e7ca05fa8600 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 157:e7ca05fa8600 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 157:e7ca05fa8600 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 157:e7ca05fa8600 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 157:e7ca05fa8600 | 20 | * without specific prior written permission. |
| AnnaBridge | 157:e7ca05fa8600 | 21 | * |
| AnnaBridge | 157:e7ca05fa8600 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 157:e7ca05fa8600 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 157:e7ca05fa8600 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 157:e7ca05fa8600 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 157:e7ca05fa8600 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 157:e7ca05fa8600 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 157:e7ca05fa8600 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 157:e7ca05fa8600 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 157:e7ca05fa8600 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 157:e7ca05fa8600 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 157:e7ca05fa8600 | 32 | * |
| AnnaBridge | 157:e7ca05fa8600 | 33 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 34 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 35 | |
| AnnaBridge | 157:e7ca05fa8600 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 37 | #ifndef __STM32L0xx_HAL_DMA_H |
| AnnaBridge | 157:e7ca05fa8600 | 38 | #define __STM32L0xx_HAL_DMA_H |
| AnnaBridge | 157:e7ca05fa8600 | 39 | |
| AnnaBridge | 157:e7ca05fa8600 | 40 | #ifdef __cplusplus |
| AnnaBridge | 157:e7ca05fa8600 | 41 | extern "C" { |
| AnnaBridge | 157:e7ca05fa8600 | 42 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 43 | |
| AnnaBridge | 157:e7ca05fa8600 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 45 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 157:e7ca05fa8600 | 46 | |
| AnnaBridge | 157:e7ca05fa8600 | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 157:e7ca05fa8600 | 48 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 49 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 50 | |
| AnnaBridge | 157:e7ca05fa8600 | 51 | /** @defgroup DMA DMA |
| AnnaBridge | 157:e7ca05fa8600 | 52 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 53 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 54 | |
| AnnaBridge | 157:e7ca05fa8600 | 55 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| AnnaBridge | 157:e7ca05fa8600 | 56 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 57 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 58 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 59 | |
| AnnaBridge | 157:e7ca05fa8600 | 60 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 61 | * @brief DMA Configuration Structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 62 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 63 | typedef struct |
| AnnaBridge | 157:e7ca05fa8600 | 64 | { |
| AnnaBridge | 157:e7ca05fa8600 | 65 | uint32_t Request; /*!< Specifies the request selected for the specified channel. |
| AnnaBridge | 157:e7ca05fa8600 | 66 | This parameter can be a value of @ref DMA_request */ |
| AnnaBridge | 157:e7ca05fa8600 | 67 | |
| AnnaBridge | 157:e7ca05fa8600 | 68 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| AnnaBridge | 157:e7ca05fa8600 | 69 | from memory to memory or from peripheral to memory. |
| AnnaBridge | 157:e7ca05fa8600 | 70 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| AnnaBridge | 157:e7ca05fa8600 | 71 | |
| AnnaBridge | 157:e7ca05fa8600 | 72 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| AnnaBridge | 157:e7ca05fa8600 | 73 | When Memory to Memory transfer is used, this is the Source Increment mode |
| AnnaBridge | 157:e7ca05fa8600 | 74 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 75 | |
| AnnaBridge | 157:e7ca05fa8600 | 76 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| AnnaBridge | 157:e7ca05fa8600 | 77 | When Memory to Memory transfer is used, this is the Destination Increment mode |
| AnnaBridge | 157:e7ca05fa8600 | 78 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 79 | |
| AnnaBridge | 157:e7ca05fa8600 | 80 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| AnnaBridge | 157:e7ca05fa8600 | 81 | When Memory to Memory transfer is used, this is the Source Alignment format |
| AnnaBridge | 157:e7ca05fa8600 | 82 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| AnnaBridge | 157:e7ca05fa8600 | 83 | |
| AnnaBridge | 157:e7ca05fa8600 | 84 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| AnnaBridge | 157:e7ca05fa8600 | 85 | When Memory to Memory transfer is used, this is the Destination Alignment format |
| AnnaBridge | 157:e7ca05fa8600 | 86 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| AnnaBridge | 157:e7ca05fa8600 | 87 | |
| AnnaBridge | 157:e7ca05fa8600 | 88 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular). |
| AnnaBridge | 157:e7ca05fa8600 | 89 | This parameter can be a value of @ref DMA_mode |
| AnnaBridge | 157:e7ca05fa8600 | 90 | @note The circular buffer mode cannot be used if the memory-to-memory |
| AnnaBridge | 157:e7ca05fa8600 | 91 | data transfer is configured on the selected Channel */ |
| AnnaBridge | 157:e7ca05fa8600 | 92 | |
| AnnaBridge | 157:e7ca05fa8600 | 93 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| AnnaBridge | 157:e7ca05fa8600 | 94 | This parameter can be a value of @ref DMA_Priority_level */ |
| AnnaBridge | 157:e7ca05fa8600 | 95 | } DMA_InitTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 96 | |
| AnnaBridge | 157:e7ca05fa8600 | 97 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 98 | * @brief DMA Configuration enumeration values definition |
| AnnaBridge | 157:e7ca05fa8600 | 99 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 100 | typedef enum |
| AnnaBridge | 157:e7ca05fa8600 | 101 | { |
| AnnaBridge | 157:e7ca05fa8600 | 102 | DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| AnnaBridge | 157:e7ca05fa8600 | 103 | DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| AnnaBridge | 157:e7ca05fa8600 | 104 | |
| AnnaBridge | 157:e7ca05fa8600 | 105 | } DMA_ControlTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 106 | |
| AnnaBridge | 157:e7ca05fa8600 | 107 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 108 | * @brief HAL DMA State structures definition |
| AnnaBridge | 157:e7ca05fa8600 | 109 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 110 | typedef enum |
| AnnaBridge | 157:e7ca05fa8600 | 111 | { |
| AnnaBridge | 157:e7ca05fa8600 | 112 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
| AnnaBridge | 157:e7ca05fa8600 | 113 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ |
| AnnaBridge | 157:e7ca05fa8600 | 114 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
| AnnaBridge | 157:e7ca05fa8600 | 115 | HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ |
| AnnaBridge | 157:e7ca05fa8600 | 116 | HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
| AnnaBridge | 157:e7ca05fa8600 | 117 | HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ |
| AnnaBridge | 157:e7ca05fa8600 | 118 | }HAL_DMA_StateTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 119 | |
| AnnaBridge | 157:e7ca05fa8600 | 120 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 121 | * @brief HAL DMA Error Code structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 122 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 123 | typedef enum |
| AnnaBridge | 157:e7ca05fa8600 | 124 | { |
| AnnaBridge | 157:e7ca05fa8600 | 125 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
| AnnaBridge | 157:e7ca05fa8600 | 126 | HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ |
| AnnaBridge | 157:e7ca05fa8600 | 127 | |
| AnnaBridge | 157:e7ca05fa8600 | 128 | }HAL_DMA_LevelCompleteTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 129 | |
| AnnaBridge | 157:e7ca05fa8600 | 130 | |
| AnnaBridge | 157:e7ca05fa8600 | 131 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 132 | * @brief DMA handle Structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 133 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 134 | typedef struct __DMA_HandleTypeDef |
| AnnaBridge | 157:e7ca05fa8600 | 135 | { |
| AnnaBridge | 157:e7ca05fa8600 | 136 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 157:e7ca05fa8600 | 137 | |
| AnnaBridge | 157:e7ca05fa8600 | 138 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| AnnaBridge | 157:e7ca05fa8600 | 139 | |
| AnnaBridge | 157:e7ca05fa8600 | 140 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| AnnaBridge | 157:e7ca05fa8600 | 141 | |
| AnnaBridge | 157:e7ca05fa8600 | 142 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| AnnaBridge | 157:e7ca05fa8600 | 143 | |
| AnnaBridge | 157:e7ca05fa8600 | 144 | void *Parent; /*!< Parent object state */ |
| AnnaBridge | 157:e7ca05fa8600 | 145 | |
| AnnaBridge | 157:e7ca05fa8600 | 146 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| AnnaBridge | 157:e7ca05fa8600 | 147 | |
| AnnaBridge | 157:e7ca05fa8600 | 148 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| AnnaBridge | 157:e7ca05fa8600 | 149 | |
| AnnaBridge | 157:e7ca05fa8600 | 150 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| AnnaBridge | 157:e7ca05fa8600 | 151 | |
| AnnaBridge | 157:e7ca05fa8600 | 152 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
| AnnaBridge | 157:e7ca05fa8600 | 153 | |
| AnnaBridge | 157:e7ca05fa8600 | 154 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| AnnaBridge | 157:e7ca05fa8600 | 155 | |
| AnnaBridge | 157:e7ca05fa8600 | 156 | } DMA_HandleTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 157 | |
| AnnaBridge | 157:e7ca05fa8600 | 158 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 159 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 160 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 161 | |
| AnnaBridge | 157:e7ca05fa8600 | 162 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 163 | |
| AnnaBridge | 157:e7ca05fa8600 | 164 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| AnnaBridge | 157:e7ca05fa8600 | 165 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 166 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 167 | |
| AnnaBridge | 157:e7ca05fa8600 | 168 | /** @defgroup DMA_Error_Code DMA Error Codes |
| AnnaBridge | 157:e7ca05fa8600 | 169 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 170 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 171 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 157:e7ca05fa8600 | 172 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
| AnnaBridge | 157:e7ca05fa8600 | 173 | #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */ |
| AnnaBridge | 157:e7ca05fa8600 | 174 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
| AnnaBridge | 157:e7ca05fa8600 | 175 | |
| AnnaBridge | 157:e7ca05fa8600 | 176 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 157:e7ca05fa8600 | 177 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 178 | ((INSTANCE) == DMA1_Channel2) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 179 | ((INSTANCE) == DMA1_Channel3) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 180 | ((INSTANCE) == DMA1_Channel4) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 181 | ((INSTANCE) == DMA1_Channel5)) |
| AnnaBridge | 157:e7ca05fa8600 | 182 | #else |
| AnnaBridge | 157:e7ca05fa8600 | 183 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 184 | ((INSTANCE) == DMA1_Channel2) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 185 | ((INSTANCE) == DMA1_Channel3) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 186 | ((INSTANCE) == DMA1_Channel4) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 187 | ((INSTANCE) == DMA1_Channel5) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 188 | ((INSTANCE) == DMA1_Channel6) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 189 | ((INSTANCE) == DMA1_Channel7)) |
| AnnaBridge | 157:e7ca05fa8600 | 190 | |
| AnnaBridge | 157:e7ca05fa8600 | 191 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 192 | #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) |
| AnnaBridge | 157:e7ca05fa8600 | 193 | |
| AnnaBridge | 157:e7ca05fa8600 | 194 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 195 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 196 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 197 | |
| AnnaBridge | 157:e7ca05fa8600 | 198 | /** @defgroup DMA_request DMA request defintiions |
| AnnaBridge | 157:e7ca05fa8600 | 199 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 200 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 201 | |
| AnnaBridge | 157:e7ca05fa8600 | 202 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 157:e7ca05fa8600 | 203 | |
| AnnaBridge | 157:e7ca05fa8600 | 204 | #define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 205 | #define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
| AnnaBridge | 157:e7ca05fa8600 | 206 | #define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
| AnnaBridge | 157:e7ca05fa8600 | 207 | #define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
| AnnaBridge | 157:e7ca05fa8600 | 208 | #define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
| AnnaBridge | 157:e7ca05fa8600 | 209 | #define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
| AnnaBridge | 157:e7ca05fa8600 | 210 | #define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
| AnnaBridge | 157:e7ca05fa8600 | 211 | #define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
| AnnaBridge | 157:e7ca05fa8600 | 212 | #define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
| AnnaBridge | 157:e7ca05fa8600 | 213 | #define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
| AnnaBridge | 157:e7ca05fa8600 | 214 | #define DMA_REQUEST_10 ((uint32_t)0x0000000AU) |
| AnnaBridge | 157:e7ca05fa8600 | 215 | #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
| AnnaBridge | 157:e7ca05fa8600 | 216 | #define DMA_REQUEST_12 ((uint32_t)0x0000000CU) |
| AnnaBridge | 157:e7ca05fa8600 | 217 | #define DMA_REQUEST_13 ((uint32_t)0x0000000DU) |
| AnnaBridge | 157:e7ca05fa8600 | 218 | #define DMA_REQUEST_14 ((uint32_t)0x0000000EU) |
| AnnaBridge | 157:e7ca05fa8600 | 219 | #define DMA_REQUEST_15 ((uint32_t)0x0000000FU) |
| AnnaBridge | 157:e7ca05fa8600 | 220 | |
| AnnaBridge | 157:e7ca05fa8600 | 221 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 222 | ((REQUEST) == DMA_REQUEST_1) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 223 | ((REQUEST) == DMA_REQUEST_2) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 224 | ((REQUEST) == DMA_REQUEST_3) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 225 | ((REQUEST) == DMA_REQUEST_4) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 226 | ((REQUEST) == DMA_REQUEST_5) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 227 | ((REQUEST) == DMA_REQUEST_6) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 228 | ((REQUEST) == DMA_REQUEST_7) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 229 | ((REQUEST) == DMA_REQUEST_8) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 230 | ((REQUEST) == DMA_REQUEST_9) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 231 | ((REQUEST) == DMA_REQUEST_10) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 232 | ((REQUEST) == DMA_REQUEST_11) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 233 | ((REQUEST) == DMA_REQUEST_12) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 234 | ((REQUEST) == DMA_REQUEST_13) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 235 | ((REQUEST) == DMA_REQUEST_14) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 236 | ((REQUEST) == DMA_REQUEST_15)) |
| AnnaBridge | 157:e7ca05fa8600 | 237 | |
| AnnaBridge | 157:e7ca05fa8600 | 238 | #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
| AnnaBridge | 157:e7ca05fa8600 | 239 | |
| AnnaBridge | 157:e7ca05fa8600 | 240 | #define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 241 | #define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
| AnnaBridge | 157:e7ca05fa8600 | 242 | #define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
| AnnaBridge | 157:e7ca05fa8600 | 243 | #define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
| AnnaBridge | 157:e7ca05fa8600 | 244 | #define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
| AnnaBridge | 157:e7ca05fa8600 | 245 | #define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
| AnnaBridge | 157:e7ca05fa8600 | 246 | #define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
| AnnaBridge | 157:e7ca05fa8600 | 247 | #define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
| AnnaBridge | 157:e7ca05fa8600 | 248 | #define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
| AnnaBridge | 157:e7ca05fa8600 | 249 | #define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
| AnnaBridge | 157:e7ca05fa8600 | 250 | #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
| AnnaBridge | 157:e7ca05fa8600 | 251 | |
| AnnaBridge | 157:e7ca05fa8600 | 252 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 253 | ((REQUEST) == DMA_REQUEST_1) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 254 | ((REQUEST) == DMA_REQUEST_2) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 255 | ((REQUEST) == DMA_REQUEST_3) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 256 | ((REQUEST) == DMA_REQUEST_4) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 257 | ((REQUEST) == DMA_REQUEST_5) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 258 | ((REQUEST) == DMA_REQUEST_6) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 259 | ((REQUEST) == DMA_REQUEST_7) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 260 | ((REQUEST) == DMA_REQUEST_8) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 261 | ((REQUEST) == DMA_REQUEST_9) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 262 | ((REQUEST) == DMA_REQUEST_11)) |
| AnnaBridge | 157:e7ca05fa8600 | 263 | #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ |
| AnnaBridge | 157:e7ca05fa8600 | 264 | |
| AnnaBridge | 157:e7ca05fa8600 | 265 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 266 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 267 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 268 | |
| AnnaBridge | 157:e7ca05fa8600 | 269 | /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions |
| AnnaBridge | 157:e7ca05fa8600 | 270 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 271 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 272 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ |
| AnnaBridge | 157:e7ca05fa8600 | 273 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| AnnaBridge | 157:e7ca05fa8600 | 274 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| AnnaBridge | 157:e7ca05fa8600 | 275 | |
| AnnaBridge | 157:e7ca05fa8600 | 276 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 277 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 278 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| AnnaBridge | 157:e7ca05fa8600 | 279 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 280 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 281 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 282 | |
| AnnaBridge | 157:e7ca05fa8600 | 283 | /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check |
| AnnaBridge | 157:e7ca05fa8600 | 284 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 285 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 286 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| AnnaBridge | 157:e7ca05fa8600 | 287 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 288 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 289 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 290 | |
| AnnaBridge | 157:e7ca05fa8600 | 291 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode |
| AnnaBridge | 157:e7ca05fa8600 | 292 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 293 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 294 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| AnnaBridge | 157:e7ca05fa8600 | 295 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ |
| AnnaBridge | 157:e7ca05fa8600 | 296 | |
| AnnaBridge | 157:e7ca05fa8600 | 297 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 298 | ((STATE) == DMA_PINC_DISABLE)) |
| AnnaBridge | 157:e7ca05fa8600 | 299 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 300 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 301 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 302 | |
| AnnaBridge | 157:e7ca05fa8600 | 303 | /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode |
| AnnaBridge | 157:e7ca05fa8600 | 304 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 305 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 306 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| AnnaBridge | 157:e7ca05fa8600 | 307 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ |
| AnnaBridge | 157:e7ca05fa8600 | 308 | |
| AnnaBridge | 157:e7ca05fa8600 | 309 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 310 | ((STATE) == DMA_MINC_DISABLE)) |
| AnnaBridge | 157:e7ca05fa8600 | 311 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 312 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 313 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 314 | |
| AnnaBridge | 157:e7ca05fa8600 | 315 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment |
| AnnaBridge | 157:e7ca05fa8600 | 316 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 317 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 318 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ |
| AnnaBridge | 157:e7ca05fa8600 | 319 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| AnnaBridge | 157:e7ca05fa8600 | 320 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| AnnaBridge | 157:e7ca05fa8600 | 321 | |
| AnnaBridge | 157:e7ca05fa8600 | 322 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 323 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 324 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| AnnaBridge | 157:e7ca05fa8600 | 325 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 326 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 327 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 328 | |
| AnnaBridge | 157:e7ca05fa8600 | 329 | |
| AnnaBridge | 157:e7ca05fa8600 | 330 | /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment |
| AnnaBridge | 157:e7ca05fa8600 | 331 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 332 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 333 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ |
| AnnaBridge | 157:e7ca05fa8600 | 334 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| AnnaBridge | 157:e7ca05fa8600 | 335 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| AnnaBridge | 157:e7ca05fa8600 | 336 | |
| AnnaBridge | 157:e7ca05fa8600 | 337 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 338 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 339 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| AnnaBridge | 157:e7ca05fa8600 | 340 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 341 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 342 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 343 | |
| AnnaBridge | 157:e7ca05fa8600 | 344 | /** @defgroup DMA_mode DMA Mode |
| AnnaBridge | 157:e7ca05fa8600 | 345 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 346 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 347 | #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 348 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 349 | |
| AnnaBridge | 157:e7ca05fa8600 | 350 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 351 | ((MODE) == DMA_CIRCULAR)) |
| AnnaBridge | 157:e7ca05fa8600 | 352 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 353 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 354 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 355 | |
| AnnaBridge | 157:e7ca05fa8600 | 356 | /** @defgroup DMA_Priority_level DMA Priority Level |
| AnnaBridge | 157:e7ca05fa8600 | 357 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 358 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 359 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ |
| AnnaBridge | 157:e7ca05fa8600 | 360 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| AnnaBridge | 157:e7ca05fa8600 | 361 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| AnnaBridge | 157:e7ca05fa8600 | 362 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| AnnaBridge | 157:e7ca05fa8600 | 363 | |
| AnnaBridge | 157:e7ca05fa8600 | 364 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 365 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 366 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 367 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| AnnaBridge | 157:e7ca05fa8600 | 368 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 369 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 370 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 371 | |
| AnnaBridge | 157:e7ca05fa8600 | 372 | |
| AnnaBridge | 157:e7ca05fa8600 | 373 | /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions |
| AnnaBridge | 157:e7ca05fa8600 | 374 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 375 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 376 | |
| AnnaBridge | 157:e7ca05fa8600 | 377 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| AnnaBridge | 157:e7ca05fa8600 | 378 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| AnnaBridge | 157:e7ca05fa8600 | 379 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| AnnaBridge | 157:e7ca05fa8600 | 380 | |
| AnnaBridge | 157:e7ca05fa8600 | 381 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 382 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 383 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 384 | |
| AnnaBridge | 157:e7ca05fa8600 | 385 | /** @defgroup DMA_flag_definitions DMA Flag Definitions |
| AnnaBridge | 157:e7ca05fa8600 | 386 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 387 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 388 | |
| AnnaBridge | 157:e7ca05fa8600 | 389 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001U) |
| AnnaBridge | 157:e7ca05fa8600 | 390 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002U) |
| AnnaBridge | 157:e7ca05fa8600 | 391 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004U) |
| AnnaBridge | 157:e7ca05fa8600 | 392 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008U) |
| AnnaBridge | 157:e7ca05fa8600 | 393 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010U) |
| AnnaBridge | 157:e7ca05fa8600 | 394 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020U) |
| AnnaBridge | 157:e7ca05fa8600 | 395 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040U) |
| AnnaBridge | 157:e7ca05fa8600 | 396 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080U) |
| AnnaBridge | 157:e7ca05fa8600 | 397 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100U) |
| AnnaBridge | 157:e7ca05fa8600 | 398 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200U) |
| AnnaBridge | 157:e7ca05fa8600 | 399 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400U) |
| AnnaBridge | 157:e7ca05fa8600 | 400 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800U) |
| AnnaBridge | 157:e7ca05fa8600 | 401 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000U) |
| AnnaBridge | 157:e7ca05fa8600 | 402 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000U) |
| AnnaBridge | 157:e7ca05fa8600 | 403 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000U) |
| AnnaBridge | 157:e7ca05fa8600 | 404 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000U) |
| AnnaBridge | 157:e7ca05fa8600 | 405 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000U) |
| AnnaBridge | 157:e7ca05fa8600 | 406 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000U) |
| AnnaBridge | 157:e7ca05fa8600 | 407 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000U) |
| AnnaBridge | 157:e7ca05fa8600 | 408 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000U) |
| AnnaBridge | 157:e7ca05fa8600 | 409 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000U) |
| AnnaBridge | 157:e7ca05fa8600 | 410 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000U) |
| AnnaBridge | 157:e7ca05fa8600 | 411 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000U) |
| AnnaBridge | 157:e7ca05fa8600 | 412 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000U) |
| AnnaBridge | 157:e7ca05fa8600 | 413 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 414 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 415 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 416 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 417 | |
| AnnaBridge | 157:e7ca05fa8600 | 418 | |
| AnnaBridge | 157:e7ca05fa8600 | 419 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 420 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 421 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 422 | |
| AnnaBridge | 157:e7ca05fa8600 | 423 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 424 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 425 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 426 | |
| AnnaBridge | 157:e7ca05fa8600 | 427 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 428 | |
| AnnaBridge | 157:e7ca05fa8600 | 429 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| AnnaBridge | 157:e7ca05fa8600 | 430 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 431 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 432 | |
| AnnaBridge | 157:e7ca05fa8600 | 433 | /** @brief Reset DMA handle state |
| AnnaBridge | 157:e7ca05fa8600 | 434 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 435 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 436 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 437 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| AnnaBridge | 157:e7ca05fa8600 | 438 | |
| AnnaBridge | 157:e7ca05fa8600 | 439 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 440 | * @brief Enable the specified DMA Channel. |
| AnnaBridge | 157:e7ca05fa8600 | 441 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 442 | * @retval None. |
| AnnaBridge | 157:e7ca05fa8600 | 443 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 444 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| AnnaBridge | 157:e7ca05fa8600 | 445 | |
| AnnaBridge | 157:e7ca05fa8600 | 446 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 447 | * @brief Disable the specified DMA Channel. |
| AnnaBridge | 157:e7ca05fa8600 | 448 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 449 | * @retval None. |
| AnnaBridge | 157:e7ca05fa8600 | 450 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 451 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| AnnaBridge | 157:e7ca05fa8600 | 452 | |
| AnnaBridge | 157:e7ca05fa8600 | 453 | |
| AnnaBridge | 157:e7ca05fa8600 | 454 | /* Interrupt & Flag management */ |
| AnnaBridge | 157:e7ca05fa8600 | 455 | |
| AnnaBridge | 157:e7ca05fa8600 | 456 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 457 | * @brief Returns the current DMA Channel transfer complete flag. |
| AnnaBridge | 157:e7ca05fa8600 | 458 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 459 | * @retval The specified transfer complete flag index. |
| AnnaBridge | 157:e7ca05fa8600 | 460 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 461 | |
| AnnaBridge | 157:e7ca05fa8600 | 462 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 157:e7ca05fa8600 | 463 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| AnnaBridge | 157:e7ca05fa8600 | 464 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 468 | DMA_FLAG_TC5) |
| AnnaBridge | 157:e7ca05fa8600 | 469 | #else |
| AnnaBridge | 157:e7ca05fa8600 | 470 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| AnnaBridge | 157:e7ca05fa8600 | 471 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 472 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 477 | DMA_FLAG_TC7) |
| AnnaBridge | 157:e7ca05fa8600 | 478 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 479 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 480 | * @brief Returns the current DMA Channel half transfer complete flag. |
| AnnaBridge | 157:e7ca05fa8600 | 481 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 482 | * @retval The specified half transfer complete flag index. |
| AnnaBridge | 157:e7ca05fa8600 | 483 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 484 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 157:e7ca05fa8600 | 485 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 486 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 489 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 490 | DMA_FLAG_HT5) |
| AnnaBridge | 157:e7ca05fa8600 | 491 | #else |
| AnnaBridge | 157:e7ca05fa8600 | 492 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 493 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 499 | DMA_FLAG_HT7) |
| AnnaBridge | 157:e7ca05fa8600 | 500 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 501 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 502 | * @brief Returns the current DMA Channel transfer error flag. |
| AnnaBridge | 157:e7ca05fa8600 | 503 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 504 | * @retval The specified transfer error flag index. |
| AnnaBridge | 157:e7ca05fa8600 | 505 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 506 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 157:e7ca05fa8600 | 507 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 508 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 512 | DMA_FLAG_TE5) |
| AnnaBridge | 157:e7ca05fa8600 | 513 | #else |
| AnnaBridge | 157:e7ca05fa8600 | 514 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 515 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 521 | DMA_FLAG_TE7) |
| AnnaBridge | 157:e7ca05fa8600 | 522 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 523 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 524 | * @brief Returns the current DMA Channel Global interrupt flag. |
| AnnaBridge | 157:e7ca05fa8600 | 525 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 526 | * @retval The specified transfer error flag index. |
| AnnaBridge | 157:e7ca05fa8600 | 527 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 528 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| AnnaBridge | 157:e7ca05fa8600 | 529 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 530 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 534 | DMA_ISR_GIF5) |
| AnnaBridge | 157:e7ca05fa8600 | 535 | #else |
| AnnaBridge | 157:e7ca05fa8600 | 536 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 157:e7ca05fa8600 | 537 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ |
| AnnaBridge | 157:e7ca05fa8600 | 543 | DMA_ISR_GIF7) |
| AnnaBridge | 157:e7ca05fa8600 | 544 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 545 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 546 | * @brief Get the DMA Channel pending flags. |
| AnnaBridge | 157:e7ca05fa8600 | 547 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 548 | * @param __FLAG__: Get the specified flag. |
| AnnaBridge | 157:e7ca05fa8600 | 549 | * This parameter can be any combination of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 550 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| AnnaBridge | 157:e7ca05fa8600 | 551 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| AnnaBridge | 157:e7ca05fa8600 | 552 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| AnnaBridge | 157:e7ca05fa8600 | 553 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| AnnaBridge | 157:e7ca05fa8600 | 554 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| AnnaBridge | 157:e7ca05fa8600 | 555 | * @retval The state of FLAG (SET or RESET). |
| AnnaBridge | 157:e7ca05fa8600 | 556 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 557 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| AnnaBridge | 157:e7ca05fa8600 | 558 | |
| AnnaBridge | 157:e7ca05fa8600 | 559 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 560 | * @brief Clears the DMA Channel pending flags. |
| AnnaBridge | 157:e7ca05fa8600 | 561 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 562 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 157:e7ca05fa8600 | 563 | * This parameter can be any combination of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 564 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| AnnaBridge | 157:e7ca05fa8600 | 565 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| AnnaBridge | 157:e7ca05fa8600 | 566 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| AnnaBridge | 157:e7ca05fa8600 | 567 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| AnnaBridge | 157:e7ca05fa8600 | 568 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| AnnaBridge | 157:e7ca05fa8600 | 569 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 570 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 571 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| AnnaBridge | 157:e7ca05fa8600 | 572 | |
| AnnaBridge | 157:e7ca05fa8600 | 573 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 574 | * @brief Enables the specified DMA Channel interrupts. |
| AnnaBridge | 157:e7ca05fa8600 | 575 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 576 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 157:e7ca05fa8600 | 577 | * This parameter can be any combination of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 578 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 579 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 580 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 581 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 582 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 583 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| AnnaBridge | 157:e7ca05fa8600 | 584 | |
| AnnaBridge | 157:e7ca05fa8600 | 585 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 586 | * @brief Disables the specified DMA Channel interrupts. |
| AnnaBridge | 157:e7ca05fa8600 | 587 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 588 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 157:e7ca05fa8600 | 589 | * This parameter can be any combination of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 590 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 591 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 592 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 593 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 594 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 595 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| AnnaBridge | 157:e7ca05fa8600 | 596 | |
| AnnaBridge | 157:e7ca05fa8600 | 597 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 598 | * @brief Checks whether the specified DMA Channel interrupt is enabled or not. |
| AnnaBridge | 157:e7ca05fa8600 | 599 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 600 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| AnnaBridge | 157:e7ca05fa8600 | 601 | * This parameter can be one of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 602 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 603 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 604 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 157:e7ca05fa8600 | 605 | * @retval The state of DMA_IT (SET or RESET). |
| AnnaBridge | 157:e7ca05fa8600 | 606 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 607 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
| AnnaBridge | 157:e7ca05fa8600 | 608 | |
| AnnaBridge | 157:e7ca05fa8600 | 609 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 610 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
| AnnaBridge | 157:e7ca05fa8600 | 611 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 157:e7ca05fa8600 | 612 | * |
| AnnaBridge | 157:e7ca05fa8600 | 613 | * @retval The number of remaining data units in the current DMA Channel transfer. |
| AnnaBridge | 157:e7ca05fa8600 | 614 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 615 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| AnnaBridge | 157:e7ca05fa8600 | 616 | |
| AnnaBridge | 157:e7ca05fa8600 | 617 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 618 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 619 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 620 | |
| AnnaBridge | 157:e7ca05fa8600 | 621 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 622 | |
| AnnaBridge | 157:e7ca05fa8600 | 623 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| AnnaBridge | 157:e7ca05fa8600 | 624 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 625 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 626 | |
| AnnaBridge | 157:e7ca05fa8600 | 627 | /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions |
| AnnaBridge | 157:e7ca05fa8600 | 628 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 629 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 630 | |
| AnnaBridge | 157:e7ca05fa8600 | 631 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 632 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 633 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 634 | |
| AnnaBridge | 157:e7ca05fa8600 | 635 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 636 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 637 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 638 | |
| AnnaBridge | 157:e7ca05fa8600 | 639 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| AnnaBridge | 157:e7ca05fa8600 | 640 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 641 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 642 | |
| AnnaBridge | 157:e7ca05fa8600 | 643 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 644 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 157:e7ca05fa8600 | 645 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 157:e7ca05fa8600 | 646 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 647 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 648 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| AnnaBridge | 157:e7ca05fa8600 | 649 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 650 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 651 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 652 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 653 | |
| AnnaBridge | 157:e7ca05fa8600 | 654 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| AnnaBridge | 157:e7ca05fa8600 | 655 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 656 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 657 | |
| AnnaBridge | 157:e7ca05fa8600 | 658 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 659 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 660 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 157:e7ca05fa8600 | 661 | |
| AnnaBridge | 157:e7ca05fa8600 | 662 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 663 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 664 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 665 | |
| AnnaBridge | 157:e7ca05fa8600 | 666 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 667 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 668 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 669 | /* Define the private group ***********************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 670 | /**************************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 671 | /** @defgroup DMA_Private DMA Private |
| AnnaBridge | 157:e7ca05fa8600 | 672 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 673 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 674 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 675 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 676 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 677 | /**************************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 678 | |
| AnnaBridge | 157:e7ca05fa8600 | 679 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 680 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 681 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 682 | |
| AnnaBridge | 157:e7ca05fa8600 | 683 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 684 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 685 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 686 | |
| AnnaBridge | 157:e7ca05fa8600 | 687 | #ifdef __cplusplus |
| AnnaBridge | 157:e7ca05fa8600 | 688 | } |
| AnnaBridge | 157:e7ca05fa8600 | 689 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 690 | |
| AnnaBridge | 157:e7ca05fa8600 | 691 | #endif /* __STM32L0xx_HAL_DMA_H */ |
| AnnaBridge | 157:e7ca05fa8600 | 692 | |
| AnnaBridge | 157:e7ca05fa8600 | 693 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 157:e7ca05fa8600 | 694 |
