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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32_hal_legacy.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32_hal_legacy.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @brief This file contains aliases definition for the STM32Cube HAL constants
AnnaBridge 157:e7ca05fa8600 6 * macros and functions maintained for legacy purpose.
AnnaBridge 157:e7ca05fa8600 7 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 8 * @attention
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 13 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 14 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 15 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 17 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 18 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 20 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 21 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 22 *
AnnaBridge 157:e7ca05fa8600 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 33 *
AnnaBridge 157:e7ca05fa8600 34 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 35 */
AnnaBridge 157:e7ca05fa8600 36
AnnaBridge 157:e7ca05fa8600 37 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 38 #ifndef __STM32_HAL_LEGACY
AnnaBridge 157:e7ca05fa8600 39 #define __STM32_HAL_LEGACY
AnnaBridge 157:e7ca05fa8600 40
AnnaBridge 157:e7ca05fa8600 41 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 42 extern "C" {
AnnaBridge 157:e7ca05fa8600 43 #endif
AnnaBridge 157:e7ca05fa8600 44
AnnaBridge 157:e7ca05fa8600 45 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 46 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 47 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 48
AnnaBridge 157:e7ca05fa8600 49 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 50 * @{
AnnaBridge 157:e7ca05fa8600 51 */
AnnaBridge 157:e7ca05fa8600 52 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
AnnaBridge 157:e7ca05fa8600 53 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
AnnaBridge 157:e7ca05fa8600 54 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
AnnaBridge 157:e7ca05fa8600 55 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
AnnaBridge 157:e7ca05fa8600 56 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
AnnaBridge 157:e7ca05fa8600 57
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 * @}
AnnaBridge 157:e7ca05fa8600 60 */
AnnaBridge 157:e7ca05fa8600 61
AnnaBridge 157:e7ca05fa8600 62 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 63 * @{
AnnaBridge 157:e7ca05fa8600 64 */
AnnaBridge 157:e7ca05fa8600 65 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
AnnaBridge 157:e7ca05fa8600 66 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
AnnaBridge 157:e7ca05fa8600 67 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
AnnaBridge 157:e7ca05fa8600 68 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
AnnaBridge 157:e7ca05fa8600 69 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
AnnaBridge 157:e7ca05fa8600 70 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
AnnaBridge 157:e7ca05fa8600 71 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
AnnaBridge 157:e7ca05fa8600 72 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AnnaBridge 157:e7ca05fa8600 73 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
AnnaBridge 157:e7ca05fa8600 74 #define REGULAR_GROUP ADC_REGULAR_GROUP
AnnaBridge 157:e7ca05fa8600 75 #define INJECTED_GROUP ADC_INJECTED_GROUP
AnnaBridge 157:e7ca05fa8600 76 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
AnnaBridge 157:e7ca05fa8600 77 #define AWD_EVENT ADC_AWD_EVENT
AnnaBridge 157:e7ca05fa8600 78 #define AWD1_EVENT ADC_AWD1_EVENT
AnnaBridge 157:e7ca05fa8600 79 #define AWD2_EVENT ADC_AWD2_EVENT
AnnaBridge 157:e7ca05fa8600 80 #define AWD3_EVENT ADC_AWD3_EVENT
AnnaBridge 157:e7ca05fa8600 81 #define OVR_EVENT ADC_OVR_EVENT
AnnaBridge 157:e7ca05fa8600 82 #define JQOVF_EVENT ADC_JQOVF_EVENT
AnnaBridge 157:e7ca05fa8600 83 #define ALL_CHANNELS ADC_ALL_CHANNELS
AnnaBridge 157:e7ca05fa8600 84 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
AnnaBridge 157:e7ca05fa8600 85 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
AnnaBridge 157:e7ca05fa8600 86 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
AnnaBridge 157:e7ca05fa8600 87 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
AnnaBridge 157:e7ca05fa8600 88 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
AnnaBridge 157:e7ca05fa8600 89 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
AnnaBridge 157:e7ca05fa8600 90 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
AnnaBridge 157:e7ca05fa8600 91 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
AnnaBridge 157:e7ca05fa8600 92 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
AnnaBridge 157:e7ca05fa8600 93 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
AnnaBridge 157:e7ca05fa8600 94 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
AnnaBridge 157:e7ca05fa8600 95 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
AnnaBridge 157:e7ca05fa8600 96 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
AnnaBridge 157:e7ca05fa8600 97 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
AnnaBridge 157:e7ca05fa8600 98 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
AnnaBridge 157:e7ca05fa8600 99 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
AnnaBridge 157:e7ca05fa8600 100 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
AnnaBridge 157:e7ca05fa8600 101 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
AnnaBridge 157:e7ca05fa8600 102 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
AnnaBridge 157:e7ca05fa8600 103 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
AnnaBridge 157:e7ca05fa8600 104 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
AnnaBridge 157:e7ca05fa8600 105
AnnaBridge 157:e7ca05fa8600 106 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
AnnaBridge 157:e7ca05fa8600 107 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
AnnaBridge 157:e7ca05fa8600 108 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
AnnaBridge 157:e7ca05fa8600 109 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
AnnaBridge 157:e7ca05fa8600 110 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
AnnaBridge 157:e7ca05fa8600 111 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
AnnaBridge 157:e7ca05fa8600 112 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
AnnaBridge 157:e7ca05fa8600 113 /**
AnnaBridge 157:e7ca05fa8600 114 * @}
AnnaBridge 157:e7ca05fa8600 115 */
AnnaBridge 157:e7ca05fa8600 116
AnnaBridge 157:e7ca05fa8600 117 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 118 * @{
AnnaBridge 157:e7ca05fa8600 119 */
AnnaBridge 157:e7ca05fa8600 120
AnnaBridge 157:e7ca05fa8600 121 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
AnnaBridge 157:e7ca05fa8600 122
AnnaBridge 157:e7ca05fa8600 123 /**
AnnaBridge 157:e7ca05fa8600 124 * @}
AnnaBridge 157:e7ca05fa8600 125 */
AnnaBridge 157:e7ca05fa8600 126
AnnaBridge 157:e7ca05fa8600 127 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 128 * @{
AnnaBridge 157:e7ca05fa8600 129 */
AnnaBridge 157:e7ca05fa8600 130 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
AnnaBridge 157:e7ca05fa8600 131 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
AnnaBridge 157:e7ca05fa8600 132 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
AnnaBridge 157:e7ca05fa8600 133 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
AnnaBridge 157:e7ca05fa8600 134 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
AnnaBridge 157:e7ca05fa8600 135 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
AnnaBridge 157:e7ca05fa8600 136 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
AnnaBridge 157:e7ca05fa8600 137 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
AnnaBridge 157:e7ca05fa8600 138 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
AnnaBridge 167:84c0a372a020 139 #if defined(STM32L0)
AnnaBridge 167:84c0a372a020 140 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
AnnaBridge 167:84c0a372a020 141 #endif
AnnaBridge 157:e7ca05fa8600 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
AnnaBridge 157:e7ca05fa8600 143 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 157:e7ca05fa8600 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
AnnaBridge 157:e7ca05fa8600 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
AnnaBridge 157:e7ca05fa8600 146 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 157:e7ca05fa8600 147
AnnaBridge 157:e7ca05fa8600 148 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 149 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
AnnaBridge 157:e7ca05fa8600 150
AnnaBridge 157:e7ca05fa8600 151 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
AnnaBridge 157:e7ca05fa8600 152 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
AnnaBridge 157:e7ca05fa8600 153 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
AnnaBridge 157:e7ca05fa8600 154 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
AnnaBridge 157:e7ca05fa8600 155 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
AnnaBridge 157:e7ca05fa8600 156 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
AnnaBridge 157:e7ca05fa8600 157
AnnaBridge 157:e7ca05fa8600 158 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
AnnaBridge 157:e7ca05fa8600 159 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
AnnaBridge 157:e7ca05fa8600 160 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
AnnaBridge 157:e7ca05fa8600 161 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
AnnaBridge 157:e7ca05fa8600 162 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge 157:e7ca05fa8600 163 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 157:e7ca05fa8600 164 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge 157:e7ca05fa8600 165 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 157:e7ca05fa8600 166 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
AnnaBridge 157:e7ca05fa8600 167 #if defined(STM32L0)
AnnaBridge 157:e7ca05fa8600 168 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
AnnaBridge 157:e7ca05fa8600 169 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
AnnaBridge 157:e7ca05fa8600 170 /* to the second dedicated IO (only for COMP2). */
AnnaBridge 157:e7ca05fa8600 171 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 157:e7ca05fa8600 172 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
AnnaBridge 157:e7ca05fa8600 173 #else
AnnaBridge 157:e7ca05fa8600 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
AnnaBridge 157:e7ca05fa8600 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
AnnaBridge 157:e7ca05fa8600 176 #endif
AnnaBridge 157:e7ca05fa8600 177 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
AnnaBridge 157:e7ca05fa8600 178 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
AnnaBridge 157:e7ca05fa8600 179
AnnaBridge 157:e7ca05fa8600 180 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
AnnaBridge 157:e7ca05fa8600 181 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
AnnaBridge 157:e7ca05fa8600 182
AnnaBridge 157:e7ca05fa8600 183 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
AnnaBridge 157:e7ca05fa8600 184 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
AnnaBridge 157:e7ca05fa8600 185 #if defined(COMP_CSR_LOCK)
AnnaBridge 157:e7ca05fa8600 186 #define COMP_FLAG_LOCK COMP_CSR_LOCK
AnnaBridge 157:e7ca05fa8600 187 #elif defined(COMP_CSR_COMP1LOCK)
AnnaBridge 157:e7ca05fa8600 188 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
AnnaBridge 157:e7ca05fa8600 189 #elif defined(COMP_CSR_COMPxLOCK)
AnnaBridge 157:e7ca05fa8600 190 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
AnnaBridge 157:e7ca05fa8600 191 #endif
AnnaBridge 157:e7ca05fa8600 192
AnnaBridge 157:e7ca05fa8600 193 #if defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 194 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
AnnaBridge 157:e7ca05fa8600 195 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
AnnaBridge 157:e7ca05fa8600 196 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
AnnaBridge 157:e7ca05fa8600 197 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
AnnaBridge 157:e7ca05fa8600 198 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
AnnaBridge 157:e7ca05fa8600 199 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
AnnaBridge 167:84c0a372a020 200 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
AnnaBridge 157:e7ca05fa8600 201 #endif
AnnaBridge 157:e7ca05fa8600 202
AnnaBridge 157:e7ca05fa8600 203 #if defined(STM32L0)
AnnaBridge 157:e7ca05fa8600 204 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge 157:e7ca05fa8600 205 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge 157:e7ca05fa8600 206 #else
AnnaBridge 157:e7ca05fa8600 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
AnnaBridge 157:e7ca05fa8600 208 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge 157:e7ca05fa8600 209 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
AnnaBridge 157:e7ca05fa8600 210 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge 157:e7ca05fa8600 211 #endif
AnnaBridge 157:e7ca05fa8600 212
AnnaBridge 157:e7ca05fa8600 213 #endif
AnnaBridge 157:e7ca05fa8600 214 /**
AnnaBridge 157:e7ca05fa8600 215 * @}
AnnaBridge 157:e7ca05fa8600 216 */
AnnaBridge 157:e7ca05fa8600 217
AnnaBridge 157:e7ca05fa8600 218 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 219 * @{
AnnaBridge 157:e7ca05fa8600 220 */
AnnaBridge 157:e7ca05fa8600 221 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
AnnaBridge 157:e7ca05fa8600 222 /**
AnnaBridge 157:e7ca05fa8600 223 * @}
AnnaBridge 157:e7ca05fa8600 224 */
AnnaBridge 157:e7ca05fa8600 225
AnnaBridge 157:e7ca05fa8600 226 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 227 * @{
AnnaBridge 157:e7ca05fa8600 228 */
AnnaBridge 157:e7ca05fa8600 229
AnnaBridge 157:e7ca05fa8600 230 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
AnnaBridge 157:e7ca05fa8600 231 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
AnnaBridge 157:e7ca05fa8600 232
AnnaBridge 157:e7ca05fa8600 233 /**
AnnaBridge 157:e7ca05fa8600 234 * @}
AnnaBridge 157:e7ca05fa8600 235 */
AnnaBridge 157:e7ca05fa8600 236
AnnaBridge 157:e7ca05fa8600 237 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 238 * @{
AnnaBridge 157:e7ca05fa8600 239 */
AnnaBridge 157:e7ca05fa8600 240
AnnaBridge 157:e7ca05fa8600 241 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge 157:e7ca05fa8600 242 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
AnnaBridge 157:e7ca05fa8600 243 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge 157:e7ca05fa8600 244 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
AnnaBridge 157:e7ca05fa8600 245 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
AnnaBridge 157:e7ca05fa8600 246 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
AnnaBridge 157:e7ca05fa8600 247 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
AnnaBridge 157:e7ca05fa8600 248 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
AnnaBridge 157:e7ca05fa8600 249 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
AnnaBridge 157:e7ca05fa8600 250
AnnaBridge 157:e7ca05fa8600 251 /**
AnnaBridge 157:e7ca05fa8600 252 * @}
AnnaBridge 157:e7ca05fa8600 253 */
AnnaBridge 157:e7ca05fa8600 254
AnnaBridge 157:e7ca05fa8600 255 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 256 * @{
AnnaBridge 157:e7ca05fa8600 257 */
AnnaBridge 157:e7ca05fa8600 258 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
AnnaBridge 157:e7ca05fa8600 259 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
AnnaBridge 157:e7ca05fa8600 260 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
AnnaBridge 157:e7ca05fa8600 261 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
AnnaBridge 157:e7ca05fa8600 262 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
AnnaBridge 157:e7ca05fa8600 263 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge 157:e7ca05fa8600 264 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
AnnaBridge 157:e7ca05fa8600 265 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
AnnaBridge 157:e7ca05fa8600 266 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
AnnaBridge 157:e7ca05fa8600 267 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
AnnaBridge 157:e7ca05fa8600 268 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
AnnaBridge 157:e7ca05fa8600 269 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
AnnaBridge 157:e7ca05fa8600 270 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
AnnaBridge 157:e7ca05fa8600 271 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
AnnaBridge 157:e7ca05fa8600 272
AnnaBridge 157:e7ca05fa8600 273 #define IS_HAL_REMAPDMA IS_DMA_REMAP
AnnaBridge 157:e7ca05fa8600 274 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
AnnaBridge 157:e7ca05fa8600 275 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
AnnaBridge 157:e7ca05fa8600 276
AnnaBridge 157:e7ca05fa8600 277
AnnaBridge 157:e7ca05fa8600 278
AnnaBridge 157:e7ca05fa8600 279 /**
AnnaBridge 157:e7ca05fa8600 280 * @}
AnnaBridge 157:e7ca05fa8600 281 */
AnnaBridge 157:e7ca05fa8600 282
AnnaBridge 157:e7ca05fa8600 283 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 284 * @{
AnnaBridge 157:e7ca05fa8600 285 */
AnnaBridge 157:e7ca05fa8600 286
AnnaBridge 157:e7ca05fa8600 287 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge 157:e7ca05fa8600 288 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge 157:e7ca05fa8600 289 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
AnnaBridge 157:e7ca05fa8600 290 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
AnnaBridge 157:e7ca05fa8600 291 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
AnnaBridge 157:e7ca05fa8600 292 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
AnnaBridge 157:e7ca05fa8600 293 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
AnnaBridge 157:e7ca05fa8600 294 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
AnnaBridge 157:e7ca05fa8600 295 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
AnnaBridge 157:e7ca05fa8600 296 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
AnnaBridge 157:e7ca05fa8600 297 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
AnnaBridge 157:e7ca05fa8600 298 #define OBEX_PCROP OPTIONBYTE_PCROP
AnnaBridge 157:e7ca05fa8600 299 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
AnnaBridge 157:e7ca05fa8600 300 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
AnnaBridge 157:e7ca05fa8600 301 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
AnnaBridge 157:e7ca05fa8600 302 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
AnnaBridge 157:e7ca05fa8600 303 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
AnnaBridge 157:e7ca05fa8600 304 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
AnnaBridge 157:e7ca05fa8600 305 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
AnnaBridge 157:e7ca05fa8600 306 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
AnnaBridge 157:e7ca05fa8600 307 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
AnnaBridge 157:e7ca05fa8600 308 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
AnnaBridge 157:e7ca05fa8600 309 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
AnnaBridge 157:e7ca05fa8600 310 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
AnnaBridge 157:e7ca05fa8600 311 #define PAGESIZE FLASH_PAGE_SIZE
AnnaBridge 157:e7ca05fa8600 312 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge 157:e7ca05fa8600 313 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge 157:e7ca05fa8600 314 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
AnnaBridge 157:e7ca05fa8600 315 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
AnnaBridge 157:e7ca05fa8600 316 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
AnnaBridge 157:e7ca05fa8600 317 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
AnnaBridge 157:e7ca05fa8600 318 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
AnnaBridge 157:e7ca05fa8600 319 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
AnnaBridge 157:e7ca05fa8600 320 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
AnnaBridge 157:e7ca05fa8600 321 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
AnnaBridge 157:e7ca05fa8600 322 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
AnnaBridge 157:e7ca05fa8600 323 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
AnnaBridge 157:e7ca05fa8600 324 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
AnnaBridge 157:e7ca05fa8600 325 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
AnnaBridge 157:e7ca05fa8600 326 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
AnnaBridge 157:e7ca05fa8600 327 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
AnnaBridge 157:e7ca05fa8600 328 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
AnnaBridge 157:e7ca05fa8600 329 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
AnnaBridge 157:e7ca05fa8600 330 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
AnnaBridge 157:e7ca05fa8600 331 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
AnnaBridge 157:e7ca05fa8600 332 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
AnnaBridge 157:e7ca05fa8600 333 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
AnnaBridge 157:e7ca05fa8600 334 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
AnnaBridge 157:e7ca05fa8600 335 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
AnnaBridge 157:e7ca05fa8600 336 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
AnnaBridge 157:e7ca05fa8600 337 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
AnnaBridge 157:e7ca05fa8600 338 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
AnnaBridge 157:e7ca05fa8600 339 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
AnnaBridge 157:e7ca05fa8600 340 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
AnnaBridge 157:e7ca05fa8600 341 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
AnnaBridge 157:e7ca05fa8600 342 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
AnnaBridge 157:e7ca05fa8600 343 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
AnnaBridge 157:e7ca05fa8600 344 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
AnnaBridge 157:e7ca05fa8600 345 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
AnnaBridge 157:e7ca05fa8600 346 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
AnnaBridge 157:e7ca05fa8600 347 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
AnnaBridge 157:e7ca05fa8600 348 #define OB_WDG_SW OB_IWDG_SW
AnnaBridge 157:e7ca05fa8600 349 #define OB_WDG_HW OB_IWDG_HW
AnnaBridge 157:e7ca05fa8600 350 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
AnnaBridge 157:e7ca05fa8600 351 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
AnnaBridge 157:e7ca05fa8600 352 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
AnnaBridge 157:e7ca05fa8600 353 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
AnnaBridge 157:e7ca05fa8600 354 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
AnnaBridge 157:e7ca05fa8600 355 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
AnnaBridge 157:e7ca05fa8600 356 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
AnnaBridge 157:e7ca05fa8600 357 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
AnnaBridge 167:84c0a372a020 358
AnnaBridge 157:e7ca05fa8600 359 /**
AnnaBridge 157:e7ca05fa8600 360 * @}
AnnaBridge 157:e7ca05fa8600 361 */
AnnaBridge 157:e7ca05fa8600 362
AnnaBridge 157:e7ca05fa8600 363 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 364 * @{
AnnaBridge 157:e7ca05fa8600 365 */
AnnaBridge 157:e7ca05fa8600 366
AnnaBridge 157:e7ca05fa8600 367 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
AnnaBridge 157:e7ca05fa8600 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
AnnaBridge 157:e7ca05fa8600 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
AnnaBridge 157:e7ca05fa8600 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
AnnaBridge 157:e7ca05fa8600 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
AnnaBridge 157:e7ca05fa8600 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
AnnaBridge 157:e7ca05fa8600 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
AnnaBridge 157:e7ca05fa8600 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
AnnaBridge 157:e7ca05fa8600 375 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
AnnaBridge 157:e7ca05fa8600 376 /**
AnnaBridge 157:e7ca05fa8600 377 * @}
AnnaBridge 157:e7ca05fa8600 378 */
AnnaBridge 157:e7ca05fa8600 379
AnnaBridge 157:e7ca05fa8600 380
AnnaBridge 157:e7ca05fa8600 381 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
AnnaBridge 157:e7ca05fa8600 382 * @{
AnnaBridge 157:e7ca05fa8600 383 */
AnnaBridge 157:e7ca05fa8600 384 #if defined(STM32L4) || defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 385 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
AnnaBridge 157:e7ca05fa8600 386 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
AnnaBridge 157:e7ca05fa8600 387 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
AnnaBridge 157:e7ca05fa8600 388 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
AnnaBridge 157:e7ca05fa8600 389 #else
AnnaBridge 157:e7ca05fa8600 390 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
AnnaBridge 157:e7ca05fa8600 391 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
AnnaBridge 157:e7ca05fa8600 392 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
AnnaBridge 157:e7ca05fa8600 393 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
AnnaBridge 157:e7ca05fa8600 394 #endif
AnnaBridge 157:e7ca05fa8600 395 /**
AnnaBridge 157:e7ca05fa8600 396 * @}
AnnaBridge 157:e7ca05fa8600 397 */
AnnaBridge 157:e7ca05fa8600 398
AnnaBridge 157:e7ca05fa8600 399 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 400 * @{
AnnaBridge 157:e7ca05fa8600 401 */
AnnaBridge 157:e7ca05fa8600 402
AnnaBridge 157:e7ca05fa8600 403 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
AnnaBridge 157:e7ca05fa8600 404 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge 157:e7ca05fa8600 405 /**
AnnaBridge 157:e7ca05fa8600 406 * @}
AnnaBridge 157:e7ca05fa8600 407 */
AnnaBridge 157:e7ca05fa8600 408
AnnaBridge 157:e7ca05fa8600 409 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 410 * @{
AnnaBridge 157:e7ca05fa8600 411 */
AnnaBridge 157:e7ca05fa8600 412 #define GET_GPIO_SOURCE GPIO_GET_INDEX
AnnaBridge 157:e7ca05fa8600 413 #define GET_GPIO_INDEX GPIO_GET_INDEX
AnnaBridge 157:e7ca05fa8600 414
AnnaBridge 157:e7ca05fa8600 415 #if defined(STM32F4)
AnnaBridge 157:e7ca05fa8600 416 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
AnnaBridge 157:e7ca05fa8600 417 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
AnnaBridge 157:e7ca05fa8600 418 #endif
AnnaBridge 157:e7ca05fa8600 419
AnnaBridge 157:e7ca05fa8600 420 #if defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 421 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge 157:e7ca05fa8600 422 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge 157:e7ca05fa8600 423 #endif
AnnaBridge 157:e7ca05fa8600 424
AnnaBridge 157:e7ca05fa8600 425 #if defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 426 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge 157:e7ca05fa8600 427 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge 157:e7ca05fa8600 428 #endif
AnnaBridge 157:e7ca05fa8600 429
AnnaBridge 157:e7ca05fa8600 430 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
AnnaBridge 157:e7ca05fa8600 431 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
AnnaBridge 157:e7ca05fa8600 432 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
AnnaBridge 157:e7ca05fa8600 433
AnnaBridge 157:e7ca05fa8600 434 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 435 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 157:e7ca05fa8600 436 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 157:e7ca05fa8600 437 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
AnnaBridge 157:e7ca05fa8600 438 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge 157:e7ca05fa8600 439 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
AnnaBridge 157:e7ca05fa8600 440
AnnaBridge 157:e7ca05fa8600 441 #if defined(STM32L1)
AnnaBridge 157:e7ca05fa8600 442 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 157:e7ca05fa8600 443 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 157:e7ca05fa8600 444 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
AnnaBridge 157:e7ca05fa8600 445 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge 157:e7ca05fa8600 446 #endif /* STM32L1 */
AnnaBridge 157:e7ca05fa8600 447
AnnaBridge 157:e7ca05fa8600 448 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
AnnaBridge 157:e7ca05fa8600 449 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 157:e7ca05fa8600 450 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 157:e7ca05fa8600 451 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
AnnaBridge 157:e7ca05fa8600 452 #endif /* STM32F0 || STM32F3 || STM32F1 */
AnnaBridge 157:e7ca05fa8600 453
AnnaBridge 157:e7ca05fa8600 454 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
AnnaBridge 157:e7ca05fa8600 455 /**
AnnaBridge 157:e7ca05fa8600 456 * @}
AnnaBridge 157:e7ca05fa8600 457 */
AnnaBridge 157:e7ca05fa8600 458
AnnaBridge 167:84c0a372a020 459 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
AnnaBridge 167:84c0a372a020 460 * @{
AnnaBridge 167:84c0a372a020 461 */
AnnaBridge 167:84c0a372a020 462
AnnaBridge 167:84c0a372a020 463 #if defined(STM32H7)
AnnaBridge 167:84c0a372a020 464 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
AnnaBridge 167:84c0a372a020 465 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
AnnaBridge 167:84c0a372a020 466 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
AnnaBridge 167:84c0a372a020 467 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
AnnaBridge 167:84c0a372a020 468 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
AnnaBridge 167:84c0a372a020 469 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
AnnaBridge 167:84c0a372a020 470
AnnaBridge 167:84c0a372a020 471 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
AnnaBridge 167:84c0a372a020 472 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
AnnaBridge 167:84c0a372a020 473
AnnaBridge 167:84c0a372a020 474 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
AnnaBridge 167:84c0a372a020 475 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
AnnaBridge 167:84c0a372a020 476
AnnaBridge 167:84c0a372a020 477 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
AnnaBridge 167:84c0a372a020 478 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
AnnaBridge 167:84c0a372a020 479 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
AnnaBridge 167:84c0a372a020 480 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
AnnaBridge 167:84c0a372a020 481 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
AnnaBridge 167:84c0a372a020 482 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
AnnaBridge 167:84c0a372a020 483 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
AnnaBridge 167:84c0a372a020 484 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
AnnaBridge 167:84c0a372a020 485
AnnaBridge 167:84c0a372a020 486 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
AnnaBridge 167:84c0a372a020 487 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
AnnaBridge 167:84c0a372a020 488 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
AnnaBridge 167:84c0a372a020 489 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
AnnaBridge 167:84c0a372a020 490 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
AnnaBridge 167:84c0a372a020 491 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
AnnaBridge 167:84c0a372a020 492 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
AnnaBridge 167:84c0a372a020 493 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
AnnaBridge 167:84c0a372a020 494 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
AnnaBridge 167:84c0a372a020 495 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
AnnaBridge 167:84c0a372a020 496 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
AnnaBridge 167:84c0a372a020 497 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
AnnaBridge 167:84c0a372a020 498 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
AnnaBridge 167:84c0a372a020 499 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
AnnaBridge 167:84c0a372a020 500 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
AnnaBridge 167:84c0a372a020 501 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
AnnaBridge 167:84c0a372a020 502 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
AnnaBridge 167:84c0a372a020 503 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
AnnaBridge 167:84c0a372a020 504 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
AnnaBridge 167:84c0a372a020 505 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
AnnaBridge 167:84c0a372a020 506 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
AnnaBridge 167:84c0a372a020 507 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
AnnaBridge 167:84c0a372a020 508 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
AnnaBridge 167:84c0a372a020 509 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
AnnaBridge 167:84c0a372a020 510 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
AnnaBridge 167:84c0a372a020 511 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
AnnaBridge 167:84c0a372a020 512 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
AnnaBridge 167:84c0a372a020 513 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
AnnaBridge 167:84c0a372a020 514 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
AnnaBridge 167:84c0a372a020 515 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
AnnaBridge 167:84c0a372a020 516
AnnaBridge 167:84c0a372a020 517 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
AnnaBridge 167:84c0a372a020 518 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
AnnaBridge 167:84c0a372a020 519 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
AnnaBridge 167:84c0a372a020 520 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
AnnaBridge 167:84c0a372a020 521
AnnaBridge 167:84c0a372a020 522
AnnaBridge 167:84c0a372a020 523 #endif /* STM32H7 */
AnnaBridge 167:84c0a372a020 524
AnnaBridge 167:84c0a372a020 525
AnnaBridge 167:84c0a372a020 526 /**
AnnaBridge 167:84c0a372a020 527 * @}
AnnaBridge 167:84c0a372a020 528 */
AnnaBridge 167:84c0a372a020 529
AnnaBridge 167:84c0a372a020 530
AnnaBridge 157:e7ca05fa8600 531 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 532 * @{
AnnaBridge 157:e7ca05fa8600 533 */
AnnaBridge 157:e7ca05fa8600 534 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
AnnaBridge 157:e7ca05fa8600 535 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
AnnaBridge 157:e7ca05fa8600 536 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
AnnaBridge 157:e7ca05fa8600 537 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
AnnaBridge 157:e7ca05fa8600 538 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
AnnaBridge 157:e7ca05fa8600 539 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
AnnaBridge 157:e7ca05fa8600 540 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
AnnaBridge 157:e7ca05fa8600 541 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
AnnaBridge 157:e7ca05fa8600 542 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
AnnaBridge 157:e7ca05fa8600 543
AnnaBridge 157:e7ca05fa8600 544 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
AnnaBridge 157:e7ca05fa8600 545 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
AnnaBridge 157:e7ca05fa8600 546 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
AnnaBridge 157:e7ca05fa8600 547 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
AnnaBridge 157:e7ca05fa8600 548 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
AnnaBridge 157:e7ca05fa8600 549 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
AnnaBridge 157:e7ca05fa8600 550 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
AnnaBridge 157:e7ca05fa8600 551 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
AnnaBridge 157:e7ca05fa8600 552 /**
AnnaBridge 157:e7ca05fa8600 553 * @}
AnnaBridge 157:e7ca05fa8600 554 */
AnnaBridge 157:e7ca05fa8600 555
AnnaBridge 157:e7ca05fa8600 556 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 557 * @{
AnnaBridge 157:e7ca05fa8600 558 */
AnnaBridge 157:e7ca05fa8600 559 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
AnnaBridge 157:e7ca05fa8600 560 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
AnnaBridge 157:e7ca05fa8600 561 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
AnnaBridge 157:e7ca05fa8600 562 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
AnnaBridge 157:e7ca05fa8600 563 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
AnnaBridge 157:e7ca05fa8600 564 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
AnnaBridge 157:e7ca05fa8600 565 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
AnnaBridge 157:e7ca05fa8600 566 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
AnnaBridge 157:e7ca05fa8600 567 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 568 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 157:e7ca05fa8600 569 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 157:e7ca05fa8600 570 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 157:e7ca05fa8600 571 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 157:e7ca05fa8600 572 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 157:e7ca05fa8600 573 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 157:e7ca05fa8600 574 #endif
AnnaBridge 157:e7ca05fa8600 575 /**
AnnaBridge 157:e7ca05fa8600 576 * @}
AnnaBridge 157:e7ca05fa8600 577 */
AnnaBridge 157:e7ca05fa8600 578
AnnaBridge 157:e7ca05fa8600 579 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 580 * @{
AnnaBridge 157:e7ca05fa8600 581 */
AnnaBridge 157:e7ca05fa8600 582 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 583 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 584
AnnaBridge 157:e7ca05fa8600 585 /**
AnnaBridge 157:e7ca05fa8600 586 * @}
AnnaBridge 157:e7ca05fa8600 587 */
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 590 * @{
AnnaBridge 157:e7ca05fa8600 591 */
AnnaBridge 157:e7ca05fa8600 592 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
AnnaBridge 157:e7ca05fa8600 593 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
AnnaBridge 157:e7ca05fa8600 594 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
AnnaBridge 157:e7ca05fa8600 595 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
AnnaBridge 157:e7ca05fa8600 596 /**
AnnaBridge 157:e7ca05fa8600 597 * @}
AnnaBridge 157:e7ca05fa8600 598 */
AnnaBridge 157:e7ca05fa8600 599
AnnaBridge 157:e7ca05fa8600 600 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 601 * @{
AnnaBridge 157:e7ca05fa8600 602 */
AnnaBridge 157:e7ca05fa8600 603
AnnaBridge 157:e7ca05fa8600 604 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
AnnaBridge 157:e7ca05fa8600 605 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
AnnaBridge 157:e7ca05fa8600 606 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
AnnaBridge 157:e7ca05fa8600 607 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
AnnaBridge 157:e7ca05fa8600 608
AnnaBridge 157:e7ca05fa8600 609 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
AnnaBridge 157:e7ca05fa8600 610 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 611 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
AnnaBridge 157:e7ca05fa8600 612
AnnaBridge 157:e7ca05fa8600 613 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
AnnaBridge 157:e7ca05fa8600 614 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge 157:e7ca05fa8600 615 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge 157:e7ca05fa8600 616 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge 157:e7ca05fa8600 617
AnnaBridge 157:e7ca05fa8600 618 /* The following 3 definition have also been present in a temporary version of lptim.h */
AnnaBridge 157:e7ca05fa8600 619 /* They need to be renamed also to the right name, just in case */
AnnaBridge 157:e7ca05fa8600 620 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge 157:e7ca05fa8600 621 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge 157:e7ca05fa8600 622 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge 157:e7ca05fa8600 623
AnnaBridge 157:e7ca05fa8600 624 /**
AnnaBridge 157:e7ca05fa8600 625 * @}
AnnaBridge 157:e7ca05fa8600 626 */
AnnaBridge 157:e7ca05fa8600 627
AnnaBridge 157:e7ca05fa8600 628 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 629 * @{
AnnaBridge 157:e7ca05fa8600 630 */
AnnaBridge 157:e7ca05fa8600 631 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
AnnaBridge 157:e7ca05fa8600 632 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
AnnaBridge 157:e7ca05fa8600 633 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
AnnaBridge 157:e7ca05fa8600 634 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
AnnaBridge 157:e7ca05fa8600 635
AnnaBridge 157:e7ca05fa8600 636 #define NAND_AddressTypedef NAND_AddressTypeDef
AnnaBridge 157:e7ca05fa8600 637
AnnaBridge 157:e7ca05fa8600 638 #define __ARRAY_ADDRESS ARRAY_ADDRESS
AnnaBridge 157:e7ca05fa8600 639 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
AnnaBridge 157:e7ca05fa8600 640 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
AnnaBridge 157:e7ca05fa8600 641 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
AnnaBridge 157:e7ca05fa8600 642 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
AnnaBridge 157:e7ca05fa8600 643 /**
AnnaBridge 157:e7ca05fa8600 644 * @}
AnnaBridge 157:e7ca05fa8600 645 */
AnnaBridge 157:e7ca05fa8600 646
AnnaBridge 157:e7ca05fa8600 647 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 648 * @{
AnnaBridge 157:e7ca05fa8600 649 */
AnnaBridge 157:e7ca05fa8600 650 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
AnnaBridge 157:e7ca05fa8600 651 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
AnnaBridge 157:e7ca05fa8600 652 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
AnnaBridge 157:e7ca05fa8600 653 #define NOR_ERROR HAL_NOR_STATUS_ERROR
AnnaBridge 157:e7ca05fa8600 654 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
AnnaBridge 157:e7ca05fa8600 655
AnnaBridge 157:e7ca05fa8600 656 #define __NOR_WRITE NOR_WRITE
AnnaBridge 157:e7ca05fa8600 657 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
AnnaBridge 157:e7ca05fa8600 658 /**
AnnaBridge 157:e7ca05fa8600 659 * @}
AnnaBridge 157:e7ca05fa8600 660 */
AnnaBridge 157:e7ca05fa8600 661
AnnaBridge 157:e7ca05fa8600 662 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 663 * @{
AnnaBridge 157:e7ca05fa8600 664 */
AnnaBridge 157:e7ca05fa8600 665
AnnaBridge 157:e7ca05fa8600 666 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 667 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 668 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
AnnaBridge 157:e7ca05fa8600 669 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
AnnaBridge 157:e7ca05fa8600 670
AnnaBridge 157:e7ca05fa8600 671 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 672 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 673 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
AnnaBridge 157:e7ca05fa8600 674 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
AnnaBridge 157:e7ca05fa8600 675
AnnaBridge 157:e7ca05fa8600 676 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 677 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 678
AnnaBridge 157:e7ca05fa8600 679 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 680 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 681
AnnaBridge 157:e7ca05fa8600 682 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 683 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 684
AnnaBridge 157:e7ca05fa8600 685 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 686
AnnaBridge 157:e7ca05fa8600 687 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
AnnaBridge 157:e7ca05fa8600 688 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
AnnaBridge 157:e7ca05fa8600 689 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
AnnaBridge 157:e7ca05fa8600 690
AnnaBridge 157:e7ca05fa8600 691 /**
AnnaBridge 157:e7ca05fa8600 692 * @}
AnnaBridge 157:e7ca05fa8600 693 */
AnnaBridge 157:e7ca05fa8600 694
AnnaBridge 157:e7ca05fa8600 695 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 696 * @{
AnnaBridge 157:e7ca05fa8600 697 */
AnnaBridge 157:e7ca05fa8600 698 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
AnnaBridge 157:e7ca05fa8600 699 #if defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 700 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
AnnaBridge 157:e7ca05fa8600 701 #endif
AnnaBridge 157:e7ca05fa8600 702 /**
AnnaBridge 157:e7ca05fa8600 703 * @}
AnnaBridge 157:e7ca05fa8600 704 */
AnnaBridge 157:e7ca05fa8600 705
AnnaBridge 157:e7ca05fa8600 706 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 707 * @{
AnnaBridge 157:e7ca05fa8600 708 */
AnnaBridge 157:e7ca05fa8600 709
AnnaBridge 157:e7ca05fa8600 710 /* Compact Flash-ATA registers description */
AnnaBridge 157:e7ca05fa8600 711 #define CF_DATA ATA_DATA
AnnaBridge 157:e7ca05fa8600 712 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
AnnaBridge 157:e7ca05fa8600 713 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
AnnaBridge 157:e7ca05fa8600 714 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
AnnaBridge 157:e7ca05fa8600 715 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
AnnaBridge 157:e7ca05fa8600 716 #define CF_CARD_HEAD ATA_CARD_HEAD
AnnaBridge 157:e7ca05fa8600 717 #define CF_STATUS_CMD ATA_STATUS_CMD
AnnaBridge 157:e7ca05fa8600 718 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
AnnaBridge 157:e7ca05fa8600 719 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
AnnaBridge 157:e7ca05fa8600 720
AnnaBridge 157:e7ca05fa8600 721 /* Compact Flash-ATA commands */
AnnaBridge 157:e7ca05fa8600 722 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
AnnaBridge 157:e7ca05fa8600 723 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
AnnaBridge 157:e7ca05fa8600 724 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
AnnaBridge 157:e7ca05fa8600 725 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
AnnaBridge 157:e7ca05fa8600 726
AnnaBridge 157:e7ca05fa8600 727 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
AnnaBridge 157:e7ca05fa8600 728 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
AnnaBridge 157:e7ca05fa8600 729 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
AnnaBridge 157:e7ca05fa8600 730 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
AnnaBridge 157:e7ca05fa8600 731 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
AnnaBridge 157:e7ca05fa8600 732 /**
AnnaBridge 157:e7ca05fa8600 733 * @}
AnnaBridge 157:e7ca05fa8600 734 */
AnnaBridge 157:e7ca05fa8600 735
AnnaBridge 157:e7ca05fa8600 736 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 737 * @{
AnnaBridge 157:e7ca05fa8600 738 */
AnnaBridge 157:e7ca05fa8600 739
AnnaBridge 157:e7ca05fa8600 740 #define FORMAT_BIN RTC_FORMAT_BIN
AnnaBridge 157:e7ca05fa8600 741 #define FORMAT_BCD RTC_FORMAT_BCD
AnnaBridge 157:e7ca05fa8600 742
AnnaBridge 157:e7ca05fa8600 743 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
AnnaBridge 157:e7ca05fa8600 744 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge 157:e7ca05fa8600 745 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge 157:e7ca05fa8600 746 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge 157:e7ca05fa8600 747
AnnaBridge 157:e7ca05fa8600 748 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge 157:e7ca05fa8600 749 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge 157:e7ca05fa8600 750 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge 157:e7ca05fa8600 751 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge 157:e7ca05fa8600 752 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge 157:e7ca05fa8600 753
AnnaBridge 157:e7ca05fa8600 754 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
AnnaBridge 157:e7ca05fa8600 755 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
AnnaBridge 157:e7ca05fa8600 756 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
AnnaBridge 157:e7ca05fa8600 757 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
AnnaBridge 157:e7ca05fa8600 758
AnnaBridge 157:e7ca05fa8600 759 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
AnnaBridge 157:e7ca05fa8600 760 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
AnnaBridge 157:e7ca05fa8600 761 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
AnnaBridge 157:e7ca05fa8600 762
AnnaBridge 157:e7ca05fa8600 763 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
AnnaBridge 157:e7ca05fa8600 764 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
AnnaBridge 157:e7ca05fa8600 765 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
AnnaBridge 157:e7ca05fa8600 766
AnnaBridge 157:e7ca05fa8600 767 /**
AnnaBridge 157:e7ca05fa8600 768 * @}
AnnaBridge 157:e7ca05fa8600 769 */
AnnaBridge 157:e7ca05fa8600 770
AnnaBridge 157:e7ca05fa8600 771
AnnaBridge 157:e7ca05fa8600 772 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 773 * @{
AnnaBridge 157:e7ca05fa8600 774 */
AnnaBridge 157:e7ca05fa8600 775 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
AnnaBridge 157:e7ca05fa8600 776 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
AnnaBridge 157:e7ca05fa8600 777
AnnaBridge 157:e7ca05fa8600 778 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 779 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 780 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 781 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 782
AnnaBridge 157:e7ca05fa8600 783 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
AnnaBridge 157:e7ca05fa8600 784 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
AnnaBridge 157:e7ca05fa8600 785
AnnaBridge 157:e7ca05fa8600 786 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
AnnaBridge 157:e7ca05fa8600 787 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
AnnaBridge 157:e7ca05fa8600 788 /**
AnnaBridge 157:e7ca05fa8600 789 * @}
AnnaBridge 157:e7ca05fa8600 790 */
AnnaBridge 157:e7ca05fa8600 791
AnnaBridge 157:e7ca05fa8600 792
AnnaBridge 157:e7ca05fa8600 793 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 794 * @{
AnnaBridge 157:e7ca05fa8600 795 */
AnnaBridge 157:e7ca05fa8600 796 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
AnnaBridge 157:e7ca05fa8600 797 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
AnnaBridge 157:e7ca05fa8600 798 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
AnnaBridge 157:e7ca05fa8600 799 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
AnnaBridge 157:e7ca05fa8600 800 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
AnnaBridge 157:e7ca05fa8600 801 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
AnnaBridge 157:e7ca05fa8600 802 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
AnnaBridge 157:e7ca05fa8600 803 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
AnnaBridge 157:e7ca05fa8600 804 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
AnnaBridge 157:e7ca05fa8600 805 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
AnnaBridge 157:e7ca05fa8600 806 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
AnnaBridge 157:e7ca05fa8600 807 /**
AnnaBridge 157:e7ca05fa8600 808 * @}
AnnaBridge 157:e7ca05fa8600 809 */
AnnaBridge 157:e7ca05fa8600 810
AnnaBridge 157:e7ca05fa8600 811 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 812 * @{
AnnaBridge 157:e7ca05fa8600 813 */
AnnaBridge 157:e7ca05fa8600 814 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
AnnaBridge 157:e7ca05fa8600 815 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
AnnaBridge 157:e7ca05fa8600 816
AnnaBridge 157:e7ca05fa8600 817 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
AnnaBridge 157:e7ca05fa8600 818 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
AnnaBridge 157:e7ca05fa8600 819
AnnaBridge 157:e7ca05fa8600 820 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
AnnaBridge 157:e7ca05fa8600 821 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
AnnaBridge 157:e7ca05fa8600 822
AnnaBridge 157:e7ca05fa8600 823 /**
AnnaBridge 157:e7ca05fa8600 824 * @}
AnnaBridge 157:e7ca05fa8600 825 */
AnnaBridge 157:e7ca05fa8600 826
AnnaBridge 157:e7ca05fa8600 827 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 828 * @{
AnnaBridge 157:e7ca05fa8600 829 */
AnnaBridge 157:e7ca05fa8600 830 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
AnnaBridge 157:e7ca05fa8600 831 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
AnnaBridge 157:e7ca05fa8600 832
AnnaBridge 157:e7ca05fa8600 833 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
AnnaBridge 157:e7ca05fa8600 834 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
AnnaBridge 157:e7ca05fa8600 835 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
AnnaBridge 157:e7ca05fa8600 836 #define TIM_DMABase_DIER TIM_DMABASE_DIER
AnnaBridge 157:e7ca05fa8600 837 #define TIM_DMABase_SR TIM_DMABASE_SR
AnnaBridge 157:e7ca05fa8600 838 #define TIM_DMABase_EGR TIM_DMABASE_EGR
AnnaBridge 157:e7ca05fa8600 839 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
AnnaBridge 157:e7ca05fa8600 840 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
AnnaBridge 157:e7ca05fa8600 841 #define TIM_DMABase_CCER TIM_DMABASE_CCER
AnnaBridge 157:e7ca05fa8600 842 #define TIM_DMABase_CNT TIM_DMABASE_CNT
AnnaBridge 157:e7ca05fa8600 843 #define TIM_DMABase_PSC TIM_DMABASE_PSC
AnnaBridge 157:e7ca05fa8600 844 #define TIM_DMABase_ARR TIM_DMABASE_ARR
AnnaBridge 157:e7ca05fa8600 845 #define TIM_DMABase_RCR TIM_DMABASE_RCR
AnnaBridge 157:e7ca05fa8600 846 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
AnnaBridge 157:e7ca05fa8600 847 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
AnnaBridge 157:e7ca05fa8600 848 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
AnnaBridge 157:e7ca05fa8600 849 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
AnnaBridge 157:e7ca05fa8600 850 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
AnnaBridge 157:e7ca05fa8600 851 #define TIM_DMABase_DCR TIM_DMABASE_DCR
AnnaBridge 157:e7ca05fa8600 852 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
AnnaBridge 157:e7ca05fa8600 853 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
AnnaBridge 157:e7ca05fa8600 854 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
AnnaBridge 157:e7ca05fa8600 855 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
AnnaBridge 157:e7ca05fa8600 856 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
AnnaBridge 157:e7ca05fa8600 857 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
AnnaBridge 157:e7ca05fa8600 858 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
AnnaBridge 157:e7ca05fa8600 859 #define TIM_DMABase_OR TIM_DMABASE_OR
AnnaBridge 157:e7ca05fa8600 860
AnnaBridge 157:e7ca05fa8600 861 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
AnnaBridge 157:e7ca05fa8600 862 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
AnnaBridge 157:e7ca05fa8600 863 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
AnnaBridge 157:e7ca05fa8600 864 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
AnnaBridge 157:e7ca05fa8600 865 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
AnnaBridge 157:e7ca05fa8600 866 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
AnnaBridge 157:e7ca05fa8600 867 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
AnnaBridge 157:e7ca05fa8600 868 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
AnnaBridge 157:e7ca05fa8600 869 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
AnnaBridge 157:e7ca05fa8600 870
AnnaBridge 157:e7ca05fa8600 871 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
AnnaBridge 157:e7ca05fa8600 872 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
AnnaBridge 157:e7ca05fa8600 873 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
AnnaBridge 157:e7ca05fa8600 874 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
AnnaBridge 157:e7ca05fa8600 875 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
AnnaBridge 157:e7ca05fa8600 876 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
AnnaBridge 157:e7ca05fa8600 877 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
AnnaBridge 157:e7ca05fa8600 878 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
AnnaBridge 157:e7ca05fa8600 879 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
AnnaBridge 157:e7ca05fa8600 880 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
AnnaBridge 157:e7ca05fa8600 881 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
AnnaBridge 157:e7ca05fa8600 882 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
AnnaBridge 157:e7ca05fa8600 883 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
AnnaBridge 157:e7ca05fa8600 884 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
AnnaBridge 157:e7ca05fa8600 885 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
AnnaBridge 157:e7ca05fa8600 886 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
AnnaBridge 157:e7ca05fa8600 887 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
AnnaBridge 157:e7ca05fa8600 888 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
AnnaBridge 157:e7ca05fa8600 889
AnnaBridge 157:e7ca05fa8600 890 /**
AnnaBridge 157:e7ca05fa8600 891 * @}
AnnaBridge 157:e7ca05fa8600 892 */
AnnaBridge 157:e7ca05fa8600 893
AnnaBridge 157:e7ca05fa8600 894 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 895 * @{
AnnaBridge 157:e7ca05fa8600 896 */
AnnaBridge 157:e7ca05fa8600 897 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 898 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
AnnaBridge 157:e7ca05fa8600 899 /**
AnnaBridge 157:e7ca05fa8600 900 * @}
AnnaBridge 157:e7ca05fa8600 901 */
AnnaBridge 157:e7ca05fa8600 902
AnnaBridge 157:e7ca05fa8600 903 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 904 * @{
AnnaBridge 157:e7ca05fa8600 905 */
AnnaBridge 157:e7ca05fa8600 906 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 907 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 908 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 909 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 910
AnnaBridge 157:e7ca05fa8600 911 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 157:e7ca05fa8600 912 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 157:e7ca05fa8600 913
AnnaBridge 157:e7ca05fa8600 914 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
AnnaBridge 157:e7ca05fa8600 915 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
AnnaBridge 157:e7ca05fa8600 916 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
AnnaBridge 157:e7ca05fa8600 917 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
AnnaBridge 157:e7ca05fa8600 918
AnnaBridge 157:e7ca05fa8600 919 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
AnnaBridge 157:e7ca05fa8600 920 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
AnnaBridge 157:e7ca05fa8600 921 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
AnnaBridge 157:e7ca05fa8600 922 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
AnnaBridge 157:e7ca05fa8600 923
AnnaBridge 167:84c0a372a020 924 #define __DIV_LPUART UART_DIV_LPUART
AnnaBridge 167:84c0a372a020 925
AnnaBridge 157:e7ca05fa8600 926 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
AnnaBridge 157:e7ca05fa8600 927 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
AnnaBridge 157:e7ca05fa8600 928
AnnaBridge 157:e7ca05fa8600 929 /**
AnnaBridge 157:e7ca05fa8600 930 * @}
AnnaBridge 157:e7ca05fa8600 931 */
AnnaBridge 157:e7ca05fa8600 932
AnnaBridge 157:e7ca05fa8600 933
AnnaBridge 157:e7ca05fa8600 934 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 935 * @{
AnnaBridge 157:e7ca05fa8600 936 */
AnnaBridge 157:e7ca05fa8600 937
AnnaBridge 157:e7ca05fa8600 938 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
AnnaBridge 157:e7ca05fa8600 939 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
AnnaBridge 157:e7ca05fa8600 940
AnnaBridge 157:e7ca05fa8600 941 #define USARTNACK_ENABLED USART_NACK_ENABLE
AnnaBridge 157:e7ca05fa8600 942 #define USARTNACK_DISABLED USART_NACK_DISABLE
AnnaBridge 157:e7ca05fa8600 943 /**
AnnaBridge 157:e7ca05fa8600 944 * @}
AnnaBridge 157:e7ca05fa8600 945 */
AnnaBridge 157:e7ca05fa8600 946
AnnaBridge 157:e7ca05fa8600 947 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 948 * @{
AnnaBridge 157:e7ca05fa8600 949 */
AnnaBridge 157:e7ca05fa8600 950 #define CFR_BASE WWDG_CFR_BASE
AnnaBridge 157:e7ca05fa8600 951
AnnaBridge 157:e7ca05fa8600 952 /**
AnnaBridge 157:e7ca05fa8600 953 * @}
AnnaBridge 157:e7ca05fa8600 954 */
AnnaBridge 157:e7ca05fa8600 955
AnnaBridge 157:e7ca05fa8600 956 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 957 * @{
AnnaBridge 157:e7ca05fa8600 958 */
AnnaBridge 157:e7ca05fa8600 959 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
AnnaBridge 157:e7ca05fa8600 960 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
AnnaBridge 157:e7ca05fa8600 961 #define CAN_IT_RQCP0 CAN_IT_TME
AnnaBridge 157:e7ca05fa8600 962 #define CAN_IT_RQCP1 CAN_IT_TME
AnnaBridge 157:e7ca05fa8600 963 #define CAN_IT_RQCP2 CAN_IT_TME
AnnaBridge 157:e7ca05fa8600 964 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge 157:e7ca05fa8600 965 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge 157:e7ca05fa8600 966 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 967 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 968 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
AnnaBridge 157:e7ca05fa8600 969
AnnaBridge 157:e7ca05fa8600 970 /**
AnnaBridge 157:e7ca05fa8600 971 * @}
AnnaBridge 157:e7ca05fa8600 972 */
AnnaBridge 157:e7ca05fa8600 973
AnnaBridge 157:e7ca05fa8600 974 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 975 * @{
AnnaBridge 157:e7ca05fa8600 976 */
AnnaBridge 157:e7ca05fa8600 977
AnnaBridge 157:e7ca05fa8600 978 #define VLAN_TAG ETH_VLAN_TAG
AnnaBridge 157:e7ca05fa8600 979 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
AnnaBridge 157:e7ca05fa8600 980 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
AnnaBridge 157:e7ca05fa8600 981 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
AnnaBridge 157:e7ca05fa8600 982 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
AnnaBridge 157:e7ca05fa8600 983 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
AnnaBridge 157:e7ca05fa8600 984 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
AnnaBridge 157:e7ca05fa8600 985 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
AnnaBridge 157:e7ca05fa8600 986
AnnaBridge 157:e7ca05fa8600 987 #define ETH_MMCCR ((uint32_t)0x00000100U)
AnnaBridge 157:e7ca05fa8600 988 #define ETH_MMCRIR ((uint32_t)0x00000104U)
AnnaBridge 157:e7ca05fa8600 989 #define ETH_MMCTIR ((uint32_t)0x00000108U)
AnnaBridge 157:e7ca05fa8600 990 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
AnnaBridge 157:e7ca05fa8600 991 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
AnnaBridge 157:e7ca05fa8600 992 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
AnnaBridge 157:e7ca05fa8600 993 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
AnnaBridge 157:e7ca05fa8600 994 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
AnnaBridge 157:e7ca05fa8600 995 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
AnnaBridge 157:e7ca05fa8600 996 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
AnnaBridge 157:e7ca05fa8600 997 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
AnnaBridge 157:e7ca05fa8600 998
AnnaBridge 157:e7ca05fa8600 999 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
AnnaBridge 157:e7ca05fa8600 1000 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
AnnaBridge 157:e7ca05fa8600 1001 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
AnnaBridge 157:e7ca05fa8600 1002 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
AnnaBridge 157:e7ca05fa8600 1003 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
AnnaBridge 157:e7ca05fa8600 1004 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
AnnaBridge 157:e7ca05fa8600 1005 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 157:e7ca05fa8600 1006 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
AnnaBridge 157:e7ca05fa8600 1007 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
AnnaBridge 157:e7ca05fa8600 1008 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 157:e7ca05fa8600 1009 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 157:e7ca05fa8600 1010 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
AnnaBridge 157:e7ca05fa8600 1011 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
AnnaBridge 157:e7ca05fa8600 1012 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
AnnaBridge 157:e7ca05fa8600 1013 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
AnnaBridge 157:e7ca05fa8600 1014 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
AnnaBridge 157:e7ca05fa8600 1015 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
AnnaBridge 167:84c0a372a020 1016 #if defined(STM32F1)
AnnaBridge 167:84c0a372a020 1017 #else
AnnaBridge 157:e7ca05fa8600 1018 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
AnnaBridge 157:e7ca05fa8600 1019 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
AnnaBridge 157:e7ca05fa8600 1020 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
AnnaBridge 167:84c0a372a020 1021 #endif
AnnaBridge 157:e7ca05fa8600 1022 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
AnnaBridge 157:e7ca05fa8600 1023 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
AnnaBridge 157:e7ca05fa8600 1024 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
AnnaBridge 157:e7ca05fa8600 1025 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
AnnaBridge 157:e7ca05fa8600 1026 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
AnnaBridge 157:e7ca05fa8600 1027 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
AnnaBridge 157:e7ca05fa8600 1028 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
AnnaBridge 157:e7ca05fa8600 1029
AnnaBridge 157:e7ca05fa8600 1030 /**
AnnaBridge 157:e7ca05fa8600 1031 * @}
AnnaBridge 157:e7ca05fa8600 1032 */
AnnaBridge 157:e7ca05fa8600 1033
AnnaBridge 157:e7ca05fa8600 1034 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1035 * @{
AnnaBridge 157:e7ca05fa8600 1036 */
AnnaBridge 157:e7ca05fa8600 1037 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
AnnaBridge 157:e7ca05fa8600 1038 #define DCMI_IT_OVF DCMI_IT_OVR
AnnaBridge 157:e7ca05fa8600 1039 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
AnnaBridge 157:e7ca05fa8600 1040 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
AnnaBridge 157:e7ca05fa8600 1041
AnnaBridge 157:e7ca05fa8600 1042 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
AnnaBridge 157:e7ca05fa8600 1043 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
AnnaBridge 157:e7ca05fa8600 1044 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
AnnaBridge 157:e7ca05fa8600 1045
AnnaBridge 157:e7ca05fa8600 1046 /**
AnnaBridge 157:e7ca05fa8600 1047 * @}
AnnaBridge 157:e7ca05fa8600 1048 */
AnnaBridge 157:e7ca05fa8600 1049
AnnaBridge 157:e7ca05fa8600 1050 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
AnnaBridge 157:e7ca05fa8600 1051 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
AnnaBridge 157:e7ca05fa8600 1052 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1053 * @{
AnnaBridge 157:e7ca05fa8600 1054 */
AnnaBridge 157:e7ca05fa8600 1055 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
AnnaBridge 157:e7ca05fa8600 1056 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
AnnaBridge 157:e7ca05fa8600 1057 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
AnnaBridge 157:e7ca05fa8600 1058 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
AnnaBridge 157:e7ca05fa8600 1059 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
AnnaBridge 157:e7ca05fa8600 1060
AnnaBridge 157:e7ca05fa8600 1061 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
AnnaBridge 157:e7ca05fa8600 1062 #define CM_RGB888 DMA2D_INPUT_RGB888
AnnaBridge 157:e7ca05fa8600 1063 #define CM_RGB565 DMA2D_INPUT_RGB565
AnnaBridge 157:e7ca05fa8600 1064 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
AnnaBridge 157:e7ca05fa8600 1065 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
AnnaBridge 157:e7ca05fa8600 1066 #define CM_L8 DMA2D_INPUT_L8
AnnaBridge 157:e7ca05fa8600 1067 #define CM_AL44 DMA2D_INPUT_AL44
AnnaBridge 157:e7ca05fa8600 1068 #define CM_AL88 DMA2D_INPUT_AL88
AnnaBridge 157:e7ca05fa8600 1069 #define CM_L4 DMA2D_INPUT_L4
AnnaBridge 157:e7ca05fa8600 1070 #define CM_A8 DMA2D_INPUT_A8
AnnaBridge 157:e7ca05fa8600 1071 #define CM_A4 DMA2D_INPUT_A4
AnnaBridge 157:e7ca05fa8600 1072 /**
AnnaBridge 157:e7ca05fa8600 1073 * @}
AnnaBridge 157:e7ca05fa8600 1074 */
AnnaBridge 157:e7ca05fa8600 1075 #endif /* STM32L4xx || STM32F7*/
AnnaBridge 157:e7ca05fa8600 1076
AnnaBridge 157:e7ca05fa8600 1077 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1078 * @{
AnnaBridge 157:e7ca05fa8600 1079 */
AnnaBridge 157:e7ca05fa8600 1080
AnnaBridge 157:e7ca05fa8600 1081 /**
AnnaBridge 157:e7ca05fa8600 1082 * @}
AnnaBridge 157:e7ca05fa8600 1083 */
AnnaBridge 157:e7ca05fa8600 1084
AnnaBridge 157:e7ca05fa8600 1085 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 1086
AnnaBridge 157:e7ca05fa8600 1087 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1088 * @{
AnnaBridge 157:e7ca05fa8600 1089 */
AnnaBridge 157:e7ca05fa8600 1090 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
AnnaBridge 157:e7ca05fa8600 1091 /**
AnnaBridge 157:e7ca05fa8600 1092 * @}
AnnaBridge 157:e7ca05fa8600 1093 */
AnnaBridge 157:e7ca05fa8600 1094
AnnaBridge 157:e7ca05fa8600 1095 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1096 * @{
AnnaBridge 157:e7ca05fa8600 1097 */
AnnaBridge 157:e7ca05fa8600 1098 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
AnnaBridge 157:e7ca05fa8600 1099 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
AnnaBridge 157:e7ca05fa8600 1100 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
AnnaBridge 157:e7ca05fa8600 1101 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
AnnaBridge 157:e7ca05fa8600 1102 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
AnnaBridge 157:e7ca05fa8600 1103 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
AnnaBridge 157:e7ca05fa8600 1104
AnnaBridge 157:e7ca05fa8600 1105 /*HASH Algorithm Selection*/
AnnaBridge 157:e7ca05fa8600 1106
AnnaBridge 157:e7ca05fa8600 1107 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
AnnaBridge 157:e7ca05fa8600 1108 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
AnnaBridge 157:e7ca05fa8600 1109 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
AnnaBridge 157:e7ca05fa8600 1110 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
AnnaBridge 157:e7ca05fa8600 1111
AnnaBridge 157:e7ca05fa8600 1112 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
AnnaBridge 157:e7ca05fa8600 1113 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
AnnaBridge 157:e7ca05fa8600 1114
AnnaBridge 157:e7ca05fa8600 1115 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
AnnaBridge 157:e7ca05fa8600 1116 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
AnnaBridge 157:e7ca05fa8600 1117 /**
AnnaBridge 157:e7ca05fa8600 1118 * @}
AnnaBridge 157:e7ca05fa8600 1119 */
AnnaBridge 157:e7ca05fa8600 1120
AnnaBridge 157:e7ca05fa8600 1121 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1122 * @{
AnnaBridge 157:e7ca05fa8600 1123 */
AnnaBridge 157:e7ca05fa8600 1124 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
AnnaBridge 157:e7ca05fa8600 1125 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
AnnaBridge 157:e7ca05fa8600 1126 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
AnnaBridge 157:e7ca05fa8600 1127 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
AnnaBridge 157:e7ca05fa8600 1128 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
AnnaBridge 157:e7ca05fa8600 1129 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
AnnaBridge 157:e7ca05fa8600 1130 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
AnnaBridge 157:e7ca05fa8600 1131 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
AnnaBridge 157:e7ca05fa8600 1132 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
AnnaBridge 157:e7ca05fa8600 1133 #if defined(STM32L0)
AnnaBridge 157:e7ca05fa8600 1134 #else
AnnaBridge 157:e7ca05fa8600 1135 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
AnnaBridge 157:e7ca05fa8600 1136 #endif
AnnaBridge 157:e7ca05fa8600 1137 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
AnnaBridge 157:e7ca05fa8600 1138 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
AnnaBridge 157:e7ca05fa8600 1139 /**
AnnaBridge 157:e7ca05fa8600 1140 * @}
AnnaBridge 157:e7ca05fa8600 1141 */
AnnaBridge 157:e7ca05fa8600 1142
AnnaBridge 157:e7ca05fa8600 1143 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1144 * @{
AnnaBridge 157:e7ca05fa8600 1145 */
AnnaBridge 157:e7ca05fa8600 1146 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
AnnaBridge 157:e7ca05fa8600 1147 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
AnnaBridge 157:e7ca05fa8600 1148 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
AnnaBridge 157:e7ca05fa8600 1149 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
AnnaBridge 157:e7ca05fa8600 1150 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
AnnaBridge 157:e7ca05fa8600 1151 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
AnnaBridge 157:e7ca05fa8600 1152 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
AnnaBridge 157:e7ca05fa8600 1153
AnnaBridge 157:e7ca05fa8600 1154 /**
AnnaBridge 157:e7ca05fa8600 1155 * @}
AnnaBridge 157:e7ca05fa8600 1156 */
AnnaBridge 157:e7ca05fa8600 1157
AnnaBridge 157:e7ca05fa8600 1158 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1159 * @{
AnnaBridge 157:e7ca05fa8600 1160 */
AnnaBridge 157:e7ca05fa8600 1161 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
AnnaBridge 157:e7ca05fa8600 1162 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
AnnaBridge 157:e7ca05fa8600 1163 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
AnnaBridge 157:e7ca05fa8600 1164 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
AnnaBridge 157:e7ca05fa8600 1165
AnnaBridge 157:e7ca05fa8600 1166 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
AnnaBridge 157:e7ca05fa8600 1167 /**
AnnaBridge 157:e7ca05fa8600 1168 * @}
AnnaBridge 157:e7ca05fa8600 1169 */
AnnaBridge 157:e7ca05fa8600 1170
AnnaBridge 157:e7ca05fa8600 1171 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1172 * @{
AnnaBridge 157:e7ca05fa8600 1173 */
AnnaBridge 157:e7ca05fa8600 1174 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
AnnaBridge 157:e7ca05fa8600 1175 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
AnnaBridge 157:e7ca05fa8600 1176 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
AnnaBridge 157:e7ca05fa8600 1177 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
AnnaBridge 157:e7ca05fa8600 1178 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
AnnaBridge 157:e7ca05fa8600 1179 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
AnnaBridge 157:e7ca05fa8600 1180 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
AnnaBridge 157:e7ca05fa8600 1181 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
AnnaBridge 157:e7ca05fa8600 1182 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
AnnaBridge 157:e7ca05fa8600 1183 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
AnnaBridge 157:e7ca05fa8600 1184 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
AnnaBridge 157:e7ca05fa8600 1185 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
AnnaBridge 157:e7ca05fa8600 1186 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
AnnaBridge 157:e7ca05fa8600 1187 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
AnnaBridge 157:e7ca05fa8600 1188 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
AnnaBridge 157:e7ca05fa8600 1189 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
AnnaBridge 157:e7ca05fa8600 1190
AnnaBridge 157:e7ca05fa8600 1191 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
AnnaBridge 157:e7ca05fa8600 1192 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
AnnaBridge 157:e7ca05fa8600 1193 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
AnnaBridge 157:e7ca05fa8600 1194 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
AnnaBridge 157:e7ca05fa8600 1195 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
AnnaBridge 157:e7ca05fa8600 1196 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
AnnaBridge 157:e7ca05fa8600 1197 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
AnnaBridge 157:e7ca05fa8600 1198
AnnaBridge 157:e7ca05fa8600 1199 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
AnnaBridge 157:e7ca05fa8600 1200 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
AnnaBridge 157:e7ca05fa8600 1201
AnnaBridge 157:e7ca05fa8600 1202 #define DBP_BitNumber DBP_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1203 #define PVDE_BitNumber PVDE_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1204 #define PMODE_BitNumber PMODE_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1205 #define EWUP_BitNumber EWUP_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1206 #define FPDS_BitNumber FPDS_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1207 #define ODEN_BitNumber ODEN_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1208 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1209 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1210 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1211 #define BRE_BitNumber BRE_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1212
AnnaBridge 157:e7ca05fa8600 1213 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
AnnaBridge 157:e7ca05fa8600 1214
AnnaBridge 157:e7ca05fa8600 1215 /**
AnnaBridge 157:e7ca05fa8600 1216 * @}
AnnaBridge 157:e7ca05fa8600 1217 */
AnnaBridge 157:e7ca05fa8600 1218
AnnaBridge 157:e7ca05fa8600 1219 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1220 * @{
AnnaBridge 157:e7ca05fa8600 1221 */
AnnaBridge 157:e7ca05fa8600 1222 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
AnnaBridge 157:e7ca05fa8600 1223 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
AnnaBridge 157:e7ca05fa8600 1224 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
AnnaBridge 157:e7ca05fa8600 1225 /**
AnnaBridge 157:e7ca05fa8600 1226 * @}
AnnaBridge 157:e7ca05fa8600 1227 */
AnnaBridge 157:e7ca05fa8600 1228
AnnaBridge 157:e7ca05fa8600 1229 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1230 * @{
AnnaBridge 157:e7ca05fa8600 1231 */
AnnaBridge 157:e7ca05fa8600 1232 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
AnnaBridge 157:e7ca05fa8600 1233 /**
AnnaBridge 157:e7ca05fa8600 1234 * @}
AnnaBridge 157:e7ca05fa8600 1235 */
AnnaBridge 157:e7ca05fa8600 1236
AnnaBridge 157:e7ca05fa8600 1237 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1238 * @{
AnnaBridge 157:e7ca05fa8600 1239 */
AnnaBridge 157:e7ca05fa8600 1240 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
AnnaBridge 157:e7ca05fa8600 1241 #define HAL_TIM_DMAError TIM_DMAError
AnnaBridge 157:e7ca05fa8600 1242 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
AnnaBridge 157:e7ca05fa8600 1243 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
AnnaBridge 157:e7ca05fa8600 1244 /**
AnnaBridge 157:e7ca05fa8600 1245 * @}
AnnaBridge 157:e7ca05fa8600 1246 */
AnnaBridge 157:e7ca05fa8600 1247
AnnaBridge 157:e7ca05fa8600 1248 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1249 * @{
AnnaBridge 157:e7ca05fa8600 1250 */
AnnaBridge 157:e7ca05fa8600 1251 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
AnnaBridge 157:e7ca05fa8600 1252 /**
AnnaBridge 157:e7ca05fa8600 1253 * @}
AnnaBridge 157:e7ca05fa8600 1254 */
AnnaBridge 157:e7ca05fa8600 1255
AnnaBridge 157:e7ca05fa8600 1256 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1257 * @{
AnnaBridge 157:e7ca05fa8600 1258 */
AnnaBridge 157:e7ca05fa8600 1259 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
AnnaBridge 157:e7ca05fa8600 1260 /**
AnnaBridge 157:e7ca05fa8600 1261 * @}
AnnaBridge 157:e7ca05fa8600 1262 */
AnnaBridge 157:e7ca05fa8600 1263
AnnaBridge 157:e7ca05fa8600 1264
AnnaBridge 157:e7ca05fa8600 1265 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1266 * @{
AnnaBridge 157:e7ca05fa8600 1267 */
AnnaBridge 157:e7ca05fa8600 1268
AnnaBridge 157:e7ca05fa8600 1269 /**
AnnaBridge 157:e7ca05fa8600 1270 * @}
AnnaBridge 157:e7ca05fa8600 1271 */
AnnaBridge 157:e7ca05fa8600 1272
AnnaBridge 157:e7ca05fa8600 1273 /* Exported macros ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 1274
AnnaBridge 157:e7ca05fa8600 1275 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1276 * @{
AnnaBridge 157:e7ca05fa8600 1277 */
AnnaBridge 157:e7ca05fa8600 1278 #define AES_IT_CC CRYP_IT_CC
AnnaBridge 157:e7ca05fa8600 1279 #define AES_IT_ERR CRYP_IT_ERR
AnnaBridge 157:e7ca05fa8600 1280 #define AES_FLAG_CCF CRYP_FLAG_CCF
AnnaBridge 157:e7ca05fa8600 1281 /**
AnnaBridge 157:e7ca05fa8600 1282 * @}
AnnaBridge 157:e7ca05fa8600 1283 */
AnnaBridge 157:e7ca05fa8600 1284
AnnaBridge 157:e7ca05fa8600 1285 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1286 * @{
AnnaBridge 157:e7ca05fa8600 1287 */
AnnaBridge 157:e7ca05fa8600 1288 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
AnnaBridge 157:e7ca05fa8600 1289 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
AnnaBridge 157:e7ca05fa8600 1290 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
AnnaBridge 157:e7ca05fa8600 1291 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
AnnaBridge 157:e7ca05fa8600 1292 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
AnnaBridge 157:e7ca05fa8600 1293 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
AnnaBridge 157:e7ca05fa8600 1294 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
AnnaBridge 157:e7ca05fa8600 1295 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
AnnaBridge 157:e7ca05fa8600 1296 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
AnnaBridge 157:e7ca05fa8600 1297 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
AnnaBridge 157:e7ca05fa8600 1298 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 1299 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
AnnaBridge 157:e7ca05fa8600 1300 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
AnnaBridge 157:e7ca05fa8600 1301
AnnaBridge 157:e7ca05fa8600 1302 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
AnnaBridge 157:e7ca05fa8600 1303 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
AnnaBridge 157:e7ca05fa8600 1304 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
AnnaBridge 157:e7ca05fa8600 1305 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1306 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 1307
AnnaBridge 157:e7ca05fa8600 1308 /**
AnnaBridge 157:e7ca05fa8600 1309 * @}
AnnaBridge 157:e7ca05fa8600 1310 */
AnnaBridge 157:e7ca05fa8600 1311
AnnaBridge 157:e7ca05fa8600 1312
AnnaBridge 157:e7ca05fa8600 1313 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1314 * @{
AnnaBridge 157:e7ca05fa8600 1315 */
AnnaBridge 157:e7ca05fa8600 1316 #define __ADC_ENABLE __HAL_ADC_ENABLE
AnnaBridge 157:e7ca05fa8600 1317 #define __ADC_DISABLE __HAL_ADC_DISABLE
AnnaBridge 157:e7ca05fa8600 1318 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
AnnaBridge 157:e7ca05fa8600 1319 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
AnnaBridge 157:e7ca05fa8600 1320 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge 157:e7ca05fa8600 1321 #define __ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge 157:e7ca05fa8600 1322 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
AnnaBridge 157:e7ca05fa8600 1323 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
AnnaBridge 157:e7ca05fa8600 1324 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
AnnaBridge 157:e7ca05fa8600 1325 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
AnnaBridge 157:e7ca05fa8600 1326 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
AnnaBridge 157:e7ca05fa8600 1327 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
AnnaBridge 157:e7ca05fa8600 1328 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
AnnaBridge 157:e7ca05fa8600 1329
AnnaBridge 157:e7ca05fa8600 1330 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge 157:e7ca05fa8600 1331 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
AnnaBridge 157:e7ca05fa8600 1332 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
AnnaBridge 157:e7ca05fa8600 1333 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
AnnaBridge 157:e7ca05fa8600 1334 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
AnnaBridge 157:e7ca05fa8600 1335 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
AnnaBridge 157:e7ca05fa8600 1336 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
AnnaBridge 157:e7ca05fa8600 1337 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
AnnaBridge 157:e7ca05fa8600 1338 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
AnnaBridge 157:e7ca05fa8600 1339 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
AnnaBridge 157:e7ca05fa8600 1340 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
AnnaBridge 157:e7ca05fa8600 1341 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
AnnaBridge 157:e7ca05fa8600 1342 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
AnnaBridge 157:e7ca05fa8600 1343 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
AnnaBridge 157:e7ca05fa8600 1344 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
AnnaBridge 157:e7ca05fa8600 1345 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
AnnaBridge 157:e7ca05fa8600 1346 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
AnnaBridge 157:e7ca05fa8600 1347 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
AnnaBridge 157:e7ca05fa8600 1348 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
AnnaBridge 157:e7ca05fa8600 1349 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
AnnaBridge 157:e7ca05fa8600 1350
AnnaBridge 157:e7ca05fa8600 1351 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
AnnaBridge 157:e7ca05fa8600 1352 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
AnnaBridge 157:e7ca05fa8600 1353 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
AnnaBridge 157:e7ca05fa8600 1354 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
AnnaBridge 157:e7ca05fa8600 1355 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
AnnaBridge 157:e7ca05fa8600 1356 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge 157:e7ca05fa8600 1357 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge 157:e7ca05fa8600 1358 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
AnnaBridge 157:e7ca05fa8600 1359 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
AnnaBridge 157:e7ca05fa8600 1360 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
AnnaBridge 157:e7ca05fa8600 1361
AnnaBridge 157:e7ca05fa8600 1362 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
AnnaBridge 157:e7ca05fa8600 1363 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
AnnaBridge 157:e7ca05fa8600 1364 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
AnnaBridge 157:e7ca05fa8600 1365 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
AnnaBridge 157:e7ca05fa8600 1366 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
AnnaBridge 157:e7ca05fa8600 1367 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
AnnaBridge 157:e7ca05fa8600 1368 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
AnnaBridge 157:e7ca05fa8600 1369 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
AnnaBridge 157:e7ca05fa8600 1370
AnnaBridge 157:e7ca05fa8600 1371 #define __HAL_ADC_SQR1 ADC_SQR1
AnnaBridge 157:e7ca05fa8600 1372 #define __HAL_ADC_SMPR1 ADC_SMPR1
AnnaBridge 157:e7ca05fa8600 1373 #define __HAL_ADC_SMPR2 ADC_SMPR2
AnnaBridge 157:e7ca05fa8600 1374 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
AnnaBridge 157:e7ca05fa8600 1375 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
AnnaBridge 157:e7ca05fa8600 1376 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
AnnaBridge 157:e7ca05fa8600 1377 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
AnnaBridge 157:e7ca05fa8600 1378 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
AnnaBridge 157:e7ca05fa8600 1379 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
AnnaBridge 157:e7ca05fa8600 1380 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
AnnaBridge 157:e7ca05fa8600 1381 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
AnnaBridge 157:e7ca05fa8600 1382 #define __HAL_ADC_JSQR ADC_JSQR
AnnaBridge 157:e7ca05fa8600 1383
AnnaBridge 157:e7ca05fa8600 1384 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
AnnaBridge 157:e7ca05fa8600 1385 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
AnnaBridge 157:e7ca05fa8600 1386 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
AnnaBridge 157:e7ca05fa8600 1387 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
AnnaBridge 157:e7ca05fa8600 1388 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
AnnaBridge 157:e7ca05fa8600 1389 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
AnnaBridge 157:e7ca05fa8600 1390 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
AnnaBridge 157:e7ca05fa8600 1391 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
AnnaBridge 157:e7ca05fa8600 1392
AnnaBridge 157:e7ca05fa8600 1393 /**
AnnaBridge 157:e7ca05fa8600 1394 * @}
AnnaBridge 157:e7ca05fa8600 1395 */
AnnaBridge 157:e7ca05fa8600 1396
AnnaBridge 157:e7ca05fa8600 1397 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1398 * @{
AnnaBridge 157:e7ca05fa8600 1399 */
AnnaBridge 157:e7ca05fa8600 1400 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
AnnaBridge 157:e7ca05fa8600 1401 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
AnnaBridge 157:e7ca05fa8600 1402 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
AnnaBridge 157:e7ca05fa8600 1403 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
AnnaBridge 157:e7ca05fa8600 1404
AnnaBridge 157:e7ca05fa8600 1405 /**
AnnaBridge 157:e7ca05fa8600 1406 * @}
AnnaBridge 157:e7ca05fa8600 1407 */
AnnaBridge 157:e7ca05fa8600 1408
AnnaBridge 157:e7ca05fa8600 1409 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1410 * @{
AnnaBridge 157:e7ca05fa8600 1411 */
AnnaBridge 157:e7ca05fa8600 1412 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
AnnaBridge 157:e7ca05fa8600 1413 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
AnnaBridge 157:e7ca05fa8600 1414 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
AnnaBridge 157:e7ca05fa8600 1415 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
AnnaBridge 157:e7ca05fa8600 1416 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
AnnaBridge 157:e7ca05fa8600 1417 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
AnnaBridge 157:e7ca05fa8600 1418 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
AnnaBridge 157:e7ca05fa8600 1419 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
AnnaBridge 157:e7ca05fa8600 1420 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
AnnaBridge 157:e7ca05fa8600 1421 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
AnnaBridge 157:e7ca05fa8600 1422 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
AnnaBridge 157:e7ca05fa8600 1423 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
AnnaBridge 157:e7ca05fa8600 1424 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
AnnaBridge 157:e7ca05fa8600 1425 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
AnnaBridge 157:e7ca05fa8600 1426 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
AnnaBridge 157:e7ca05fa8600 1427 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
AnnaBridge 157:e7ca05fa8600 1428
AnnaBridge 157:e7ca05fa8600 1429 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
AnnaBridge 157:e7ca05fa8600 1430 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
AnnaBridge 157:e7ca05fa8600 1431 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
AnnaBridge 157:e7ca05fa8600 1432 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
AnnaBridge 157:e7ca05fa8600 1433 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
AnnaBridge 157:e7ca05fa8600 1434 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
AnnaBridge 157:e7ca05fa8600 1435 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
AnnaBridge 157:e7ca05fa8600 1436 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
AnnaBridge 157:e7ca05fa8600 1437 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
AnnaBridge 157:e7ca05fa8600 1438 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
AnnaBridge 157:e7ca05fa8600 1439 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
AnnaBridge 157:e7ca05fa8600 1440 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
AnnaBridge 157:e7ca05fa8600 1441 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
AnnaBridge 157:e7ca05fa8600 1442 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
AnnaBridge 157:e7ca05fa8600 1443
AnnaBridge 157:e7ca05fa8600 1444
AnnaBridge 157:e7ca05fa8600 1445 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
AnnaBridge 157:e7ca05fa8600 1446 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
AnnaBridge 157:e7ca05fa8600 1447 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
AnnaBridge 157:e7ca05fa8600 1448 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
AnnaBridge 157:e7ca05fa8600 1449 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
AnnaBridge 157:e7ca05fa8600 1450 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
AnnaBridge 157:e7ca05fa8600 1451 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
AnnaBridge 157:e7ca05fa8600 1452 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
AnnaBridge 157:e7ca05fa8600 1453 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
AnnaBridge 157:e7ca05fa8600 1454 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
AnnaBridge 157:e7ca05fa8600 1455 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
AnnaBridge 157:e7ca05fa8600 1456 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
AnnaBridge 157:e7ca05fa8600 1457 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1458 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1459 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1460 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1461 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1462 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
AnnaBridge 157:e7ca05fa8600 1463 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
AnnaBridge 157:e7ca05fa8600 1464 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
AnnaBridge 157:e7ca05fa8600 1465 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
AnnaBridge 157:e7ca05fa8600 1466 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
AnnaBridge 157:e7ca05fa8600 1467 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
AnnaBridge 157:e7ca05fa8600 1468 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
AnnaBridge 157:e7ca05fa8600 1469
AnnaBridge 157:e7ca05fa8600 1470 /**
AnnaBridge 157:e7ca05fa8600 1471 * @}
AnnaBridge 157:e7ca05fa8600 1472 */
AnnaBridge 157:e7ca05fa8600 1473
AnnaBridge 157:e7ca05fa8600 1474 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1475 * @{
AnnaBridge 157:e7ca05fa8600 1476 */
AnnaBridge 157:e7ca05fa8600 1477 #if defined(STM32F3)
AnnaBridge 157:e7ca05fa8600 1478 #define COMP_START __HAL_COMP_ENABLE
AnnaBridge 157:e7ca05fa8600 1479 #define COMP_STOP __HAL_COMP_DISABLE
AnnaBridge 157:e7ca05fa8600 1480 #define COMP_LOCK __HAL_COMP_LOCK
AnnaBridge 157:e7ca05fa8600 1481
AnnaBridge 157:e7ca05fa8600 1482 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 157:e7ca05fa8600 1483 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1484 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1485 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1486 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1488 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1489 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1490 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1491 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1492 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1494 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1495 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1496 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1497 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge 157:e7ca05fa8600 1498 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1500 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge 157:e7ca05fa8600 1501 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1502 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1503 __HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge 157:e7ca05fa8600 1504 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1505 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1506 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge 157:e7ca05fa8600 1507 # endif
AnnaBridge 157:e7ca05fa8600 1508 # if defined(STM32F302xE) || defined(STM32F302xC)
AnnaBridge 157:e7ca05fa8600 1509 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1510 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1511 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1512 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1513 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1514 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1515 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1516 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1517 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1518 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1519 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1520 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1521 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1522 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1523 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1524 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1525 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1526 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1527 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1528 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge 157:e7ca05fa8600 1529 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1530 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1531 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1532 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge 157:e7ca05fa8600 1533 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1534 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1535 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1536 __HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge 157:e7ca05fa8600 1537 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1538 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1539 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1540 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge 157:e7ca05fa8600 1541 # endif
AnnaBridge 157:e7ca05fa8600 1542 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 157:e7ca05fa8600 1543 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1544 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1545 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1546 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1547 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1548 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1549 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1550 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1551 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1552 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1553 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1554 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1555 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1556 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1557 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1558 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1559 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1560 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1561 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1562 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1563 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1564 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1565 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1566 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1567 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1568 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1569 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1570 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1571 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1572 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1573 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1574 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1575 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1576 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1577 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
AnnaBridge 157:e7ca05fa8600 1578 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1579 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1580 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1581 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1582 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1583 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1584 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
AnnaBridge 157:e7ca05fa8600 1585 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1586 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1587 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1588 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1589 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1590 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1591 __HAL_COMP_COMP7_EXTI_GET_FLAG())
AnnaBridge 157:e7ca05fa8600 1592 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1593 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1594 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1595 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1596 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1597 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1598 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
AnnaBridge 157:e7ca05fa8600 1599 # endif
AnnaBridge 157:e7ca05fa8600 1600 # if defined(STM32F373xC) ||defined(STM32F378xx)
AnnaBridge 157:e7ca05fa8600 1601 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1602 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1603 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1604 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1605 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1606 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1607 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1608 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1609 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1610 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge 157:e7ca05fa8600 1611 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1612 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge 157:e7ca05fa8600 1613 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1614 __HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge 157:e7ca05fa8600 1615 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1616 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge 157:e7ca05fa8600 1617 # endif
AnnaBridge 157:e7ca05fa8600 1618 #else
AnnaBridge 157:e7ca05fa8600 1619 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1620 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1621 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1622 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 157:e7ca05fa8600 1623 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1624 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1625 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 157:e7ca05fa8600 1626 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 157:e7ca05fa8600 1627 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1628 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge 157:e7ca05fa8600 1629 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 1630 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge 157:e7ca05fa8600 1631 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1632 __HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge 157:e7ca05fa8600 1633 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 1634 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge 157:e7ca05fa8600 1635 #endif
AnnaBridge 157:e7ca05fa8600 1636
AnnaBridge 157:e7ca05fa8600 1637 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
AnnaBridge 157:e7ca05fa8600 1638
AnnaBridge 157:e7ca05fa8600 1639 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 1640 /* Note: On these STM32 families, the only argument of this macro */
AnnaBridge 157:e7ca05fa8600 1641 /* is COMP_FLAG_LOCK. */
AnnaBridge 157:e7ca05fa8600 1642 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
AnnaBridge 157:e7ca05fa8600 1643 /* argument. */
AnnaBridge 157:e7ca05fa8600 1644 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
AnnaBridge 157:e7ca05fa8600 1645 #endif
AnnaBridge 157:e7ca05fa8600 1646 /**
AnnaBridge 157:e7ca05fa8600 1647 * @}
AnnaBridge 157:e7ca05fa8600 1648 */
AnnaBridge 157:e7ca05fa8600 1649
AnnaBridge 157:e7ca05fa8600 1650 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 1651 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1652 * @{
AnnaBridge 157:e7ca05fa8600 1653 */
AnnaBridge 157:e7ca05fa8600 1654 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge 157:e7ca05fa8600 1655 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge 157:e7ca05fa8600 1656 /**
AnnaBridge 157:e7ca05fa8600 1657 * @}
AnnaBridge 157:e7ca05fa8600 1658 */
AnnaBridge 157:e7ca05fa8600 1659 #endif
AnnaBridge 157:e7ca05fa8600 1660
AnnaBridge 157:e7ca05fa8600 1661 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1662 * @{
AnnaBridge 157:e7ca05fa8600 1663 */
AnnaBridge 157:e7ca05fa8600 1664
AnnaBridge 157:e7ca05fa8600 1665 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
AnnaBridge 157:e7ca05fa8600 1666 ((WAVE) == DAC_WAVE_NOISE)|| \
AnnaBridge 157:e7ca05fa8600 1667 ((WAVE) == DAC_WAVE_TRIANGLE))
AnnaBridge 157:e7ca05fa8600 1668
AnnaBridge 157:e7ca05fa8600 1669 /**
AnnaBridge 157:e7ca05fa8600 1670 * @}
AnnaBridge 157:e7ca05fa8600 1671 */
AnnaBridge 157:e7ca05fa8600 1672
AnnaBridge 157:e7ca05fa8600 1673 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1674 * @{
AnnaBridge 157:e7ca05fa8600 1675 */
AnnaBridge 157:e7ca05fa8600 1676
AnnaBridge 157:e7ca05fa8600 1677 #define IS_WRPAREA IS_OB_WRPAREA
AnnaBridge 157:e7ca05fa8600 1678 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
AnnaBridge 157:e7ca05fa8600 1679 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
AnnaBridge 157:e7ca05fa8600 1680 #define IS_TYPEERASE IS_FLASH_TYPEERASE
AnnaBridge 157:e7ca05fa8600 1681 #define IS_NBSECTORS IS_FLASH_NBSECTORS
AnnaBridge 157:e7ca05fa8600 1682 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
AnnaBridge 157:e7ca05fa8600 1683
AnnaBridge 157:e7ca05fa8600 1684 /**
AnnaBridge 157:e7ca05fa8600 1685 * @}
AnnaBridge 157:e7ca05fa8600 1686 */
AnnaBridge 157:e7ca05fa8600 1687
AnnaBridge 157:e7ca05fa8600 1688 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1689 * @{
AnnaBridge 157:e7ca05fa8600 1690 */
AnnaBridge 157:e7ca05fa8600 1691
AnnaBridge 157:e7ca05fa8600 1692 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
AnnaBridge 157:e7ca05fa8600 1693 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
AnnaBridge 157:e7ca05fa8600 1694 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
AnnaBridge 157:e7ca05fa8600 1695 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
AnnaBridge 157:e7ca05fa8600 1696 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
AnnaBridge 157:e7ca05fa8600 1697 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
AnnaBridge 157:e7ca05fa8600 1698 #define __HAL_I2C_SPEED I2C_SPEED
AnnaBridge 157:e7ca05fa8600 1699 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
AnnaBridge 157:e7ca05fa8600 1700 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
AnnaBridge 157:e7ca05fa8600 1701 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
AnnaBridge 157:e7ca05fa8600 1702 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
AnnaBridge 157:e7ca05fa8600 1703 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
AnnaBridge 157:e7ca05fa8600 1704 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
AnnaBridge 157:e7ca05fa8600 1705 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
AnnaBridge 157:e7ca05fa8600 1706 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
AnnaBridge 157:e7ca05fa8600 1707 /**
AnnaBridge 157:e7ca05fa8600 1708 * @}
AnnaBridge 157:e7ca05fa8600 1709 */
AnnaBridge 157:e7ca05fa8600 1710
AnnaBridge 157:e7ca05fa8600 1711 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1712 * @{
AnnaBridge 157:e7ca05fa8600 1713 */
AnnaBridge 157:e7ca05fa8600 1714
AnnaBridge 157:e7ca05fa8600 1715 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
AnnaBridge 157:e7ca05fa8600 1716 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
AnnaBridge 157:e7ca05fa8600 1717
AnnaBridge 157:e7ca05fa8600 1718 /**
AnnaBridge 157:e7ca05fa8600 1719 * @}
AnnaBridge 157:e7ca05fa8600 1720 */
AnnaBridge 157:e7ca05fa8600 1721
AnnaBridge 157:e7ca05fa8600 1722 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1723 * @{
AnnaBridge 157:e7ca05fa8600 1724 */
AnnaBridge 157:e7ca05fa8600 1725
AnnaBridge 157:e7ca05fa8600 1726 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
AnnaBridge 157:e7ca05fa8600 1727 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
AnnaBridge 157:e7ca05fa8600 1728
AnnaBridge 157:e7ca05fa8600 1729 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 1730 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge 157:e7ca05fa8600 1731 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 1732 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge 157:e7ca05fa8600 1733
AnnaBridge 157:e7ca05fa8600 1734 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
AnnaBridge 157:e7ca05fa8600 1735
AnnaBridge 157:e7ca05fa8600 1736
AnnaBridge 157:e7ca05fa8600 1737 /**
AnnaBridge 157:e7ca05fa8600 1738 * @}
AnnaBridge 157:e7ca05fa8600 1739 */
AnnaBridge 157:e7ca05fa8600 1740
AnnaBridge 157:e7ca05fa8600 1741
AnnaBridge 157:e7ca05fa8600 1742 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1743 * @{
AnnaBridge 157:e7ca05fa8600 1744 */
AnnaBridge 157:e7ca05fa8600 1745 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
AnnaBridge 157:e7ca05fa8600 1746 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
AnnaBridge 157:e7ca05fa8600 1747 /**
AnnaBridge 157:e7ca05fa8600 1748 * @}
AnnaBridge 157:e7ca05fa8600 1749 */
AnnaBridge 157:e7ca05fa8600 1750
AnnaBridge 157:e7ca05fa8600 1751
AnnaBridge 157:e7ca05fa8600 1752 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1753 * @{
AnnaBridge 157:e7ca05fa8600 1754 */
AnnaBridge 157:e7ca05fa8600 1755
AnnaBridge 157:e7ca05fa8600 1756 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 1757 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 1758 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
AnnaBridge 157:e7ca05fa8600 1759
AnnaBridge 157:e7ca05fa8600 1760 /**
AnnaBridge 157:e7ca05fa8600 1761 * @}
AnnaBridge 157:e7ca05fa8600 1762 */
AnnaBridge 157:e7ca05fa8600 1763
AnnaBridge 157:e7ca05fa8600 1764
AnnaBridge 157:e7ca05fa8600 1765 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1766 * @{
AnnaBridge 157:e7ca05fa8600 1767 */
AnnaBridge 157:e7ca05fa8600 1768 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
AnnaBridge 157:e7ca05fa8600 1769 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
AnnaBridge 157:e7ca05fa8600 1770 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
AnnaBridge 157:e7ca05fa8600 1771 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
AnnaBridge 157:e7ca05fa8600 1772 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
AnnaBridge 157:e7ca05fa8600 1773 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
AnnaBridge 157:e7ca05fa8600 1774 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
AnnaBridge 157:e7ca05fa8600 1775 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
AnnaBridge 157:e7ca05fa8600 1776 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
AnnaBridge 157:e7ca05fa8600 1777 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
AnnaBridge 157:e7ca05fa8600 1778 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
AnnaBridge 157:e7ca05fa8600 1779 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
AnnaBridge 157:e7ca05fa8600 1780 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
AnnaBridge 157:e7ca05fa8600 1781
AnnaBridge 157:e7ca05fa8600 1782 /**
AnnaBridge 157:e7ca05fa8600 1783 * @}
AnnaBridge 157:e7ca05fa8600 1784 */
AnnaBridge 157:e7ca05fa8600 1785
AnnaBridge 157:e7ca05fa8600 1786
AnnaBridge 157:e7ca05fa8600 1787 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1788 * @{
AnnaBridge 157:e7ca05fa8600 1789 */
AnnaBridge 157:e7ca05fa8600 1790 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge 157:e7ca05fa8600 1791 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge 157:e7ca05fa8600 1792 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1793 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1794 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 1795 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 1796 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
AnnaBridge 157:e7ca05fa8600 1797 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
AnnaBridge 157:e7ca05fa8600 1798 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
AnnaBridge 157:e7ca05fa8600 1799 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
AnnaBridge 157:e7ca05fa8600 1800 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
AnnaBridge 157:e7ca05fa8600 1801 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
AnnaBridge 157:e7ca05fa8600 1802 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
AnnaBridge 157:e7ca05fa8600 1803 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
AnnaBridge 157:e7ca05fa8600 1804 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
AnnaBridge 157:e7ca05fa8600 1805 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
AnnaBridge 157:e7ca05fa8600 1806 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
AnnaBridge 157:e7ca05fa8600 1807 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge 157:e7ca05fa8600 1808 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge 157:e7ca05fa8600 1809 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1810 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1811 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 1812 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 1813 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1814 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 1815 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
AnnaBridge 157:e7ca05fa8600 1816 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
AnnaBridge 157:e7ca05fa8600 1817 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
AnnaBridge 157:e7ca05fa8600 1818 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
AnnaBridge 157:e7ca05fa8600 1819 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
AnnaBridge 157:e7ca05fa8600 1820 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
AnnaBridge 157:e7ca05fa8600 1821 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1822 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 1823 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
AnnaBridge 157:e7ca05fa8600 1824 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
AnnaBridge 157:e7ca05fa8600 1825
AnnaBridge 157:e7ca05fa8600 1826 #if defined (STM32F4)
AnnaBridge 157:e7ca05fa8600 1827 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
AnnaBridge 157:e7ca05fa8600 1828 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
AnnaBridge 157:e7ca05fa8600 1829 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
AnnaBridge 157:e7ca05fa8600 1830 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
AnnaBridge 157:e7ca05fa8600 1831 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
AnnaBridge 157:e7ca05fa8600 1832 #else
AnnaBridge 157:e7ca05fa8600 1833 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 1834 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 1835 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 1836 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
AnnaBridge 157:e7ca05fa8600 1837 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
AnnaBridge 157:e7ca05fa8600 1838 #endif /* STM32F4 */
AnnaBridge 157:e7ca05fa8600 1839 /**
AnnaBridge 157:e7ca05fa8600 1840 * @}
AnnaBridge 157:e7ca05fa8600 1841 */
AnnaBridge 157:e7ca05fa8600 1842
AnnaBridge 157:e7ca05fa8600 1843
AnnaBridge 157:e7ca05fa8600 1844 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 1845 * @{
AnnaBridge 157:e7ca05fa8600 1846 */
AnnaBridge 157:e7ca05fa8600 1847
AnnaBridge 157:e7ca05fa8600 1848 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge 157:e7ca05fa8600 1849 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge 157:e7ca05fa8600 1850
AnnaBridge 157:e7ca05fa8600 1851 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
AnnaBridge 157:e7ca05fa8600 1852 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
AnnaBridge 157:e7ca05fa8600 1853
AnnaBridge 167:84c0a372a020 1854 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
AnnaBridge 167:84c0a372a020 1855 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
AnnaBridge 167:84c0a372a020 1856 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
AnnaBridge 167:84c0a372a020 1857 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
AnnaBridge 167:84c0a372a020 1858 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
AnnaBridge 167:84c0a372a020 1859 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
AnnaBridge 167:84c0a372a020 1860 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
AnnaBridge 167:84c0a372a020 1861 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
AnnaBridge 167:84c0a372a020 1862 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
AnnaBridge 167:84c0a372a020 1863 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
AnnaBridge 167:84c0a372a020 1864 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
AnnaBridge 167:84c0a372a020 1865 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
AnnaBridge 167:84c0a372a020 1866 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
AnnaBridge 167:84c0a372a020 1867 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1868 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1869 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1870 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1871 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1872 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1873 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1874 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1875 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1876 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1877 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1878 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1879 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1880 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1881 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1882 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1883 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
AnnaBridge 167:84c0a372a020 1884 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1885 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1886 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1887 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1888 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1889 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1890 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1891 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1892 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1893 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1894 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1895 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1896 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1897 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1898 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1899 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1900 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1901 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1902 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1903 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1904 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1905 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1906 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1907 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1908 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1909 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1910 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1911 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1912 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1913 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1914 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1915 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1916 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1917 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1918 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1919 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1920 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1921 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1922 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1923 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1924 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1925 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1926 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1927 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1928 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1929 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1930 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1931 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1932 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1933 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1934 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1935 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1936 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1937 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1938 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1939 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1940 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1941 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1942 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1943 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1944 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1945 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1946 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1947 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1948 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1949 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1950 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1951 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1952 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1953 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1954 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1955 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1956 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1957 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1958 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1959 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1960 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1961 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1962 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1963 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1964 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1965 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1966 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1967 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1968 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1969 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1970 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1971 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1972 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1973 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1974 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1975 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1976 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1977 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1978 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1979 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1980 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1981 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1982 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1983 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1984 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1985 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1986 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1987 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1988 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1989 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1990 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1991 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1992 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 1993 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 1994 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 1995 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 1996 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1997 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 1998 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 1999 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2000 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2001 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2002 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2003 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2004 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2005 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2006 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2007 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2008 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2009 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2010 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2011 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2012 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2013 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2014 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2015 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2016 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2017 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2018 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2019 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2020 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2021 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2022 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2023 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2024 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2025 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2026 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2027 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2028 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2029 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2030 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2031 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2032 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2033 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2034 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2035 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2036 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2037 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2038 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2039 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2040 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2041 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2042 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2043 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2044 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2045 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2046 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2047 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2048 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2049 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2050 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2051 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2052 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2053 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2054 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2055 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2056 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2057 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2058 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2059 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2060 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2061 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2062 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2063 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2064 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2065 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2066 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2067 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2068 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2069 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2070 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2071 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2072 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2073 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2074 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2075 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2076 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2077 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2078 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2079 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2080 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2081 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2082 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2083 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2084 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2085 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2086 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2087 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2088 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2089 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2090 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2091 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2092 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2093 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2094 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2095 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2096 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2097 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2098 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2099 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2100 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2101 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2102 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2103 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2104 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2105 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2106 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2107 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2108 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2109 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2110 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2111 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2112 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2113 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2114 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2115 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2116 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2117 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2118 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2119 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2120 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2121 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2122 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2123 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2124 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2125 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2126 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2127 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2128 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2129 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2130 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2131 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2132 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2133 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2134 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2135 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2136 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2137 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2138 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2139 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2140 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2141 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2142 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2143 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2144 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2145 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2146 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2147 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2148 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2149 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2150 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2151 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2152 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2153 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2154 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2155 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2156 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2157 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2158 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2159 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2160 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2161 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2162 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2163 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2164 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2165 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2166 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2167 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2168 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2169 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2170 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2171 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2172 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2173 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2174 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2175 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2176 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2177 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2178 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2179 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2180 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2181 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2182 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2183 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2184 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2185 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2186 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2187 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2188 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2189 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2190 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2191 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2192 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2193 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2194 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2195 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2196 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2197 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2198 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2199 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2200 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2201 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2202 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2203 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2204 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2205 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2206 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2207 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2208 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2209 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2210 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2211 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2212 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2213 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2214 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2215 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2216 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2217 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2218 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2219 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2220 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2221 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2222 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2223 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2224 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2225 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2226 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2227 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2228 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2229 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2230 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2231 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2232 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2233 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2234 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2235 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2236 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2237 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2238 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2239 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2240 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2241 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2242 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2243 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2244 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2245 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2246 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2247 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2248 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2249 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2250 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2251 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2252 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2253 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2254 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2255 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2256 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2257 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2258 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2259 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2260 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2261 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2262 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2263 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2264 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2265 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2266 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2267 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2268 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2269 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2270 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2271 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2272 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2273 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2274 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2275 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2276 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2277 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2278 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2279 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2280 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2281 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2282 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2283 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2284 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2285 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2286 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2287 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2288 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2289 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2290 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2291 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2292 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2293 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2294 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2295 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2296 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2297 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2298 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2299 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
AnnaBridge 167:84c0a372a020 2300 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge 167:84c0a372a020 2301 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge 167:84c0a372a020 2302 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge 167:84c0a372a020 2303 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge 167:84c0a372a020 2304 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge 167:84c0a372a020 2305 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge 167:84c0a372a020 2306 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge 167:84c0a372a020 2307 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge 167:84c0a372a020 2308 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge 167:84c0a372a020 2309 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge 167:84c0a372a020 2310 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge 167:84c0a372a020 2311 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge 167:84c0a372a020 2312 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge 167:84c0a372a020 2313 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge 167:84c0a372a020 2314 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge 167:84c0a372a020 2315 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge 167:84c0a372a020 2316 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge 167:84c0a372a020 2317 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge 167:84c0a372a020 2318 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge 167:84c0a372a020 2319 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2320 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2321 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2322 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2323 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2324 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2325 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2326 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2327 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2328 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2329 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2330 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2331 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2332 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2333 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2334 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2335 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2336 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2337 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2338 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2339 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2340 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2341 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2342 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2343 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2344 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2345 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2346 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2347 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2348 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2349 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2350 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2351 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2352 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
AnnaBridge 157:e7ca05fa8600 2353 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
AnnaBridge 157:e7ca05fa8600 2354
AnnaBridge 157:e7ca05fa8600 2355 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2356 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2357 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2358 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2359 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2360 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2361 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2362 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2363 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2364 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2365 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2366 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2367 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2368 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2369 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2370 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2371 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2372 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2373 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2374 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2375 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2376 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2377 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2378 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2379 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2380 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2381 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2382 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2383 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2384 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2385 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2386 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2387 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2388 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2389 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2390 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2391 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2392 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2393 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2394 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2395 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2396 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2397 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2398 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2399 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2400 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2401 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2402 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2403 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2404 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2405 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2406 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2407 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2408 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2409 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2410 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2411 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2412 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2413 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2414 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2415 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2416 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2417 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2418 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2419 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2420 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2421 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2422 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2423 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2424 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2425 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2426 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2427 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2428 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2429 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2430 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2431 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2432 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2433 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2434 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2435 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2436 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2437 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2438 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2439 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2440 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2441 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2442 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2443 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2444 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2445 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2446 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2447 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2448 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2449 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2450 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2451 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2452 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2453 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2454 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2455 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2456 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2457 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2458 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2459 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2460 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2461 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2462 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2463 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2464 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2465 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2466 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2467 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2468 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2469 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2470 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2471 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
AnnaBridge 157:e7ca05fa8600 2472 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
AnnaBridge 157:e7ca05fa8600 2473 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2474 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2475 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2476 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2477 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
AnnaBridge 157:e7ca05fa8600 2478 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
AnnaBridge 157:e7ca05fa8600 2479 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2480 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2481 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2482 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2483 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2484 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2485 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2486 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2487 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2488 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2489 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2490 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2491 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2492 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2493 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2494 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2495 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2496 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2497 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2498 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2499 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2500 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2501 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2502
AnnaBridge 157:e7ca05fa8600 2503 /* alias define maintained for legacy */
AnnaBridge 157:e7ca05fa8600 2504 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2505 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2506
AnnaBridge 157:e7ca05fa8600 2507 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2508 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2509 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2510 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2511 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2512 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2513 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2514 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2515 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2516 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2517 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2518 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2519 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2520 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2521 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2522 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2523 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2524 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2525 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2526 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2527
AnnaBridge 157:e7ca05fa8600 2528 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2529 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2530 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2531 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2532 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2533 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2534 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2535 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2536 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2537 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2538 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2539 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2540 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2541 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2542 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2543 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2544 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2545 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2546 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2547 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2548
AnnaBridge 157:e7ca05fa8600 2549 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2550 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2551 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2552 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2553 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2554 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2555 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2556 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2557 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2558 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2559 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2560 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2561 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2562 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2563 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2564 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2565 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2566 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2567 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2568 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2569 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2570 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2571 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2572 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2573 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2574 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2575 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2576 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2577 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2578 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2579 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2580 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2581 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2582 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2583 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2584 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2585 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2586 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2587 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2588 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2589 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2590 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2591 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2592 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2593 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2594 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2595 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2596 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2597 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2598 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2599 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2600 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2601 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2602 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2603 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2604 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2605 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2606 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2607 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2608 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2609 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2610 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2611 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2612 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2613 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2614 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2615 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2616 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2617 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2618 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2619 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2620 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2621 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2622 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2623 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2624 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2625 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2626 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2627 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2628 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2629 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2630 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2631 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2632 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2633 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2634 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2635 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2636 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2637 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2638 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2639 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2640 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2641 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2642 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2643 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2644 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2645 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2646 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2647 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2648 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2649 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2650 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2651 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2652 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2653 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2654 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2655 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2656 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2657 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2658 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2659 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2660 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2661 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2662 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2663 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2664 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2665
AnnaBridge 157:e7ca05fa8600 2666 #if defined(STM32F4)
AnnaBridge 157:e7ca05fa8600 2667 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2668 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2669 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2670 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2671 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2672 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2673 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2674 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2675 #define Sdmmc1ClockSelection SdioClockSelection
AnnaBridge 157:e7ca05fa8600 2676 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
AnnaBridge 157:e7ca05fa8600 2677 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
AnnaBridge 157:e7ca05fa8600 2678 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
AnnaBridge 157:e7ca05fa8600 2679 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
AnnaBridge 157:e7ca05fa8600 2680 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
AnnaBridge 157:e7ca05fa8600 2681 #endif
AnnaBridge 157:e7ca05fa8600 2682
AnnaBridge 157:e7ca05fa8600 2683 #if defined(STM32F7) || defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 2684 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2685 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2686 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2687 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2688 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2689 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2690 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2691 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2692 #define SdioClockSelection Sdmmc1ClockSelection
AnnaBridge 157:e7ca05fa8600 2693 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
AnnaBridge 157:e7ca05fa8600 2694 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
AnnaBridge 157:e7ca05fa8600 2695 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
AnnaBridge 157:e7ca05fa8600 2696 #endif
AnnaBridge 157:e7ca05fa8600 2697
AnnaBridge 157:e7ca05fa8600 2698 #if defined(STM32F7)
AnnaBridge 157:e7ca05fa8600 2699 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
AnnaBridge 157:e7ca05fa8600 2700 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
AnnaBridge 157:e7ca05fa8600 2701 #endif
AnnaBridge 157:e7ca05fa8600 2702
AnnaBridge 157:e7ca05fa8600 2703 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
AnnaBridge 157:e7ca05fa8600 2704 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
AnnaBridge 157:e7ca05fa8600 2705
AnnaBridge 157:e7ca05fa8600 2706 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
AnnaBridge 157:e7ca05fa8600 2707
AnnaBridge 157:e7ca05fa8600 2708 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
AnnaBridge 157:e7ca05fa8600 2709 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
AnnaBridge 157:e7ca05fa8600 2710 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
AnnaBridge 157:e7ca05fa8600 2711 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
AnnaBridge 157:e7ca05fa8600 2712 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
AnnaBridge 157:e7ca05fa8600 2713
AnnaBridge 157:e7ca05fa8600 2714 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
AnnaBridge 157:e7ca05fa8600 2715
AnnaBridge 167:84c0a372a020 2716 #define RCC_IT_CSSLSE RCC_IT_LSECSS
AnnaBridge 167:84c0a372a020 2717 #define RCC_IT_CSSHSE RCC_IT_CSS
AnnaBridge 167:84c0a372a020 2718
AnnaBridge 167:84c0a372a020 2719 #define RCC_PLLMUL_3 RCC_PLL_MUL3
AnnaBridge 167:84c0a372a020 2720 #define RCC_PLLMUL_4 RCC_PLL_MUL4
AnnaBridge 167:84c0a372a020 2721 #define RCC_PLLMUL_6 RCC_PLL_MUL6
AnnaBridge 167:84c0a372a020 2722 #define RCC_PLLMUL_8 RCC_PLL_MUL8
AnnaBridge 167:84c0a372a020 2723 #define RCC_PLLMUL_12 RCC_PLL_MUL12
AnnaBridge 167:84c0a372a020 2724 #define RCC_PLLMUL_16 RCC_PLL_MUL16
AnnaBridge 167:84c0a372a020 2725 #define RCC_PLLMUL_24 RCC_PLL_MUL24
AnnaBridge 167:84c0a372a020 2726 #define RCC_PLLMUL_32 RCC_PLL_MUL32
AnnaBridge 167:84c0a372a020 2727 #define RCC_PLLMUL_48 RCC_PLL_MUL48
AnnaBridge 167:84c0a372a020 2728
AnnaBridge 167:84c0a372a020 2729 #define RCC_PLLDIV_2 RCC_PLL_DIV2
AnnaBridge 167:84c0a372a020 2730 #define RCC_PLLDIV_3 RCC_PLL_DIV3
AnnaBridge 167:84c0a372a020 2731 #define RCC_PLLDIV_4 RCC_PLL_DIV4
AnnaBridge 157:e7ca05fa8600 2732
AnnaBridge 157:e7ca05fa8600 2733 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
AnnaBridge 157:e7ca05fa8600 2734 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
AnnaBridge 157:e7ca05fa8600 2735 #define RCC_MCO_NODIV RCC_MCODIV_1
AnnaBridge 157:e7ca05fa8600 2736 #define RCC_MCO_DIV1 RCC_MCODIV_1
AnnaBridge 157:e7ca05fa8600 2737 #define RCC_MCO_DIV2 RCC_MCODIV_2
AnnaBridge 157:e7ca05fa8600 2738 #define RCC_MCO_DIV4 RCC_MCODIV_4
AnnaBridge 157:e7ca05fa8600 2739 #define RCC_MCO_DIV8 RCC_MCODIV_8
AnnaBridge 157:e7ca05fa8600 2740 #define RCC_MCO_DIV16 RCC_MCODIV_16
AnnaBridge 157:e7ca05fa8600 2741 #define RCC_MCO_DIV32 RCC_MCODIV_32
AnnaBridge 157:e7ca05fa8600 2742 #define RCC_MCO_DIV64 RCC_MCODIV_64
AnnaBridge 157:e7ca05fa8600 2743 #define RCC_MCO_DIV128 RCC_MCODIV_128
AnnaBridge 157:e7ca05fa8600 2744 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
AnnaBridge 157:e7ca05fa8600 2745 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
AnnaBridge 157:e7ca05fa8600 2746 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
AnnaBridge 157:e7ca05fa8600 2747 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
AnnaBridge 157:e7ca05fa8600 2748 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
AnnaBridge 157:e7ca05fa8600 2749 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
AnnaBridge 157:e7ca05fa8600 2750 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
AnnaBridge 157:e7ca05fa8600 2751 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
AnnaBridge 157:e7ca05fa8600 2752 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
AnnaBridge 157:e7ca05fa8600 2753 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
AnnaBridge 157:e7ca05fa8600 2754 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
AnnaBridge 157:e7ca05fa8600 2755
AnnaBridge 167:84c0a372a020 2756 #if defined(STM32WB) || defined(STM32G0)
AnnaBridge 167:84c0a372a020 2757 #else
AnnaBridge 157:e7ca05fa8600 2758 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
AnnaBridge 167:84c0a372a020 2759 #endif
AnnaBridge 157:e7ca05fa8600 2760
AnnaBridge 157:e7ca05fa8600 2761 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
AnnaBridge 157:e7ca05fa8600 2762 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
AnnaBridge 157:e7ca05fa8600 2763 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
AnnaBridge 157:e7ca05fa8600 2764 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
AnnaBridge 157:e7ca05fa8600 2765 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
AnnaBridge 157:e7ca05fa8600 2766 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
AnnaBridge 157:e7ca05fa8600 2767 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
AnnaBridge 157:e7ca05fa8600 2768 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
AnnaBridge 157:e7ca05fa8600 2769
AnnaBridge 157:e7ca05fa8600 2770 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2771 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2772 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2773 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2774 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2775 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2776 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2777 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2778 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2779 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2780 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2781 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2782 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2783 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2784 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2785 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2786 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2787 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2788 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2789 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2790 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2791 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2792 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2793 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2794 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2795 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
AnnaBridge 157:e7ca05fa8600 2796 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
AnnaBridge 157:e7ca05fa8600 2797 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
AnnaBridge 157:e7ca05fa8600 2798 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
AnnaBridge 157:e7ca05fa8600 2799 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
AnnaBridge 157:e7ca05fa8600 2800 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
AnnaBridge 157:e7ca05fa8600 2801 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
AnnaBridge 157:e7ca05fa8600 2802
AnnaBridge 157:e7ca05fa8600 2803 #define CR_HSION_BB RCC_CR_HSION_BB
AnnaBridge 157:e7ca05fa8600 2804 #define CR_CSSON_BB RCC_CR_CSSON_BB
AnnaBridge 157:e7ca05fa8600 2805 #define CR_PLLON_BB RCC_CR_PLLON_BB
AnnaBridge 157:e7ca05fa8600 2806 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
AnnaBridge 157:e7ca05fa8600 2807 #define CR_MSION_BB RCC_CR_MSION_BB
AnnaBridge 157:e7ca05fa8600 2808 #define CSR_LSION_BB RCC_CSR_LSION_BB
AnnaBridge 157:e7ca05fa8600 2809 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
AnnaBridge 157:e7ca05fa8600 2810 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
AnnaBridge 157:e7ca05fa8600 2811 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
AnnaBridge 157:e7ca05fa8600 2812 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
AnnaBridge 157:e7ca05fa8600 2813 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
AnnaBridge 157:e7ca05fa8600 2814 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
AnnaBridge 157:e7ca05fa8600 2815 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
AnnaBridge 157:e7ca05fa8600 2816 #define CR_HSEON_BB RCC_CR_HSEON_BB
AnnaBridge 157:e7ca05fa8600 2817 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
AnnaBridge 157:e7ca05fa8600 2818 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
AnnaBridge 157:e7ca05fa8600 2819 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
AnnaBridge 157:e7ca05fa8600 2820
AnnaBridge 157:e7ca05fa8600 2821 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
AnnaBridge 157:e7ca05fa8600 2822 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
AnnaBridge 157:e7ca05fa8600 2823 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
AnnaBridge 157:e7ca05fa8600 2824 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
AnnaBridge 157:e7ca05fa8600 2825 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
AnnaBridge 157:e7ca05fa8600 2826
AnnaBridge 157:e7ca05fa8600 2827 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
AnnaBridge 157:e7ca05fa8600 2828
AnnaBridge 157:e7ca05fa8600 2829 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
AnnaBridge 157:e7ca05fa8600 2830 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
AnnaBridge 157:e7ca05fa8600 2831
AnnaBridge 157:e7ca05fa8600 2832 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
AnnaBridge 157:e7ca05fa8600 2833 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
AnnaBridge 157:e7ca05fa8600 2834 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
AnnaBridge 157:e7ca05fa8600 2835 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
AnnaBridge 157:e7ca05fa8600 2836 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
AnnaBridge 157:e7ca05fa8600 2837 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
AnnaBridge 157:e7ca05fa8600 2838
AnnaBridge 157:e7ca05fa8600 2839 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
AnnaBridge 157:e7ca05fa8600 2840 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
AnnaBridge 157:e7ca05fa8600 2841 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
AnnaBridge 157:e7ca05fa8600 2842 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
AnnaBridge 157:e7ca05fa8600 2843 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
AnnaBridge 157:e7ca05fa8600 2844 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
AnnaBridge 157:e7ca05fa8600 2845 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
AnnaBridge 157:e7ca05fa8600 2846 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
AnnaBridge 157:e7ca05fa8600 2847 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
AnnaBridge 157:e7ca05fa8600 2848 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
AnnaBridge 157:e7ca05fa8600 2849 #define DfsdmClockSelection Dfsdm1ClockSelection
AnnaBridge 157:e7ca05fa8600 2850 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
AnnaBridge 157:e7ca05fa8600 2851 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
AnnaBridge 157:e7ca05fa8600 2852 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
AnnaBridge 157:e7ca05fa8600 2853 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
AnnaBridge 157:e7ca05fa8600 2854 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
AnnaBridge 157:e7ca05fa8600 2855 /**
AnnaBridge 157:e7ca05fa8600 2856 * @}
AnnaBridge 157:e7ca05fa8600 2857 */
AnnaBridge 157:e7ca05fa8600 2858
AnnaBridge 157:e7ca05fa8600 2859 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 2860 * @{
AnnaBridge 157:e7ca05fa8600 2861 */
AnnaBridge 157:e7ca05fa8600 2862 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
AnnaBridge 157:e7ca05fa8600 2863
AnnaBridge 157:e7ca05fa8600 2864 /**
AnnaBridge 157:e7ca05fa8600 2865 * @}
AnnaBridge 157:e7ca05fa8600 2866 */
AnnaBridge 157:e7ca05fa8600 2867
AnnaBridge 157:e7ca05fa8600 2868 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 2869 * @{
AnnaBridge 157:e7ca05fa8600 2870 */
AnnaBridge 167:84c0a372a020 2871 #if defined (STM32G0)
AnnaBridge 167:84c0a372a020 2872 #else
AnnaBridge 157:e7ca05fa8600 2873 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
AnnaBridge 167:84c0a372a020 2874 #endif
AnnaBridge 157:e7ca05fa8600 2875 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 2876 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 2877
AnnaBridge 157:e7ca05fa8600 2878 #if defined (STM32F1)
AnnaBridge 157:e7ca05fa8600 2879 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
AnnaBridge 157:e7ca05fa8600 2880
AnnaBridge 157:e7ca05fa8600 2881 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
AnnaBridge 157:e7ca05fa8600 2882
AnnaBridge 157:e7ca05fa8600 2883 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
AnnaBridge 157:e7ca05fa8600 2884
AnnaBridge 157:e7ca05fa8600 2885 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
AnnaBridge 157:e7ca05fa8600 2886
AnnaBridge 157:e7ca05fa8600 2887 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
AnnaBridge 157:e7ca05fa8600 2888 #else
AnnaBridge 157:e7ca05fa8600 2889 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 2890 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
AnnaBridge 157:e7ca05fa8600 2891 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
AnnaBridge 157:e7ca05fa8600 2892 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 2893 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 2894 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
AnnaBridge 157:e7ca05fa8600 2895 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 2896 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
AnnaBridge 157:e7ca05fa8600 2897 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
AnnaBridge 157:e7ca05fa8600 2898 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 2899 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
AnnaBridge 157:e7ca05fa8600 2900 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
AnnaBridge 157:e7ca05fa8600 2901 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
AnnaBridge 157:e7ca05fa8600 2902 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
AnnaBridge 157:e7ca05fa8600 2903 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
AnnaBridge 157:e7ca05fa8600 2904 #endif /* STM32F1 */
AnnaBridge 157:e7ca05fa8600 2905
AnnaBridge 157:e7ca05fa8600 2906 #define IS_ALARM IS_RTC_ALARM
AnnaBridge 157:e7ca05fa8600 2907 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
AnnaBridge 157:e7ca05fa8600 2908 #define IS_TAMPER IS_RTC_TAMPER
AnnaBridge 157:e7ca05fa8600 2909 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
AnnaBridge 157:e7ca05fa8600 2910 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
AnnaBridge 157:e7ca05fa8600 2911 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
AnnaBridge 157:e7ca05fa8600 2912 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
AnnaBridge 157:e7ca05fa8600 2913 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
AnnaBridge 157:e7ca05fa8600 2914 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
AnnaBridge 157:e7ca05fa8600 2915 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
AnnaBridge 157:e7ca05fa8600 2916 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
AnnaBridge 157:e7ca05fa8600 2917 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
AnnaBridge 157:e7ca05fa8600 2918 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
AnnaBridge 157:e7ca05fa8600 2919 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
AnnaBridge 157:e7ca05fa8600 2920
AnnaBridge 157:e7ca05fa8600 2921 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
AnnaBridge 157:e7ca05fa8600 2922 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
AnnaBridge 157:e7ca05fa8600 2923
AnnaBridge 157:e7ca05fa8600 2924 /**
AnnaBridge 157:e7ca05fa8600 2925 * @}
AnnaBridge 157:e7ca05fa8600 2926 */
AnnaBridge 157:e7ca05fa8600 2927
AnnaBridge 157:e7ca05fa8600 2928 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 2929 * @{
AnnaBridge 157:e7ca05fa8600 2930 */
AnnaBridge 157:e7ca05fa8600 2931
AnnaBridge 157:e7ca05fa8600 2932 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
AnnaBridge 157:e7ca05fa8600 2933 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
AnnaBridge 157:e7ca05fa8600 2934
AnnaBridge 157:e7ca05fa8600 2935 #if defined(STM32F4)
AnnaBridge 157:e7ca05fa8600 2936 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
AnnaBridge 157:e7ca05fa8600 2937 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
AnnaBridge 157:e7ca05fa8600 2938 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
AnnaBridge 157:e7ca05fa8600 2939 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
AnnaBridge 157:e7ca05fa8600 2940 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
AnnaBridge 157:e7ca05fa8600 2941 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
AnnaBridge 157:e7ca05fa8600 2942 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
AnnaBridge 157:e7ca05fa8600 2943 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
AnnaBridge 157:e7ca05fa8600 2944 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
AnnaBridge 157:e7ca05fa8600 2945 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
AnnaBridge 157:e7ca05fa8600 2946 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
AnnaBridge 157:e7ca05fa8600 2947 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 2948 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 2949 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
AnnaBridge 157:e7ca05fa8600 2950 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 2951 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
AnnaBridge 157:e7ca05fa8600 2952 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
AnnaBridge 157:e7ca05fa8600 2953 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
AnnaBridge 157:e7ca05fa8600 2954 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
AnnaBridge 157:e7ca05fa8600 2955 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
AnnaBridge 157:e7ca05fa8600 2956 /* alias CMSIS */
AnnaBridge 157:e7ca05fa8600 2957 #define SDMMC1_IRQn SDIO_IRQn
AnnaBridge 157:e7ca05fa8600 2958 #define SDMMC1_IRQHandler SDIO_IRQHandler
AnnaBridge 157:e7ca05fa8600 2959 #endif
AnnaBridge 157:e7ca05fa8600 2960
AnnaBridge 157:e7ca05fa8600 2961 #if defined(STM32F7) || defined(STM32L4)
AnnaBridge 157:e7ca05fa8600 2962 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
AnnaBridge 157:e7ca05fa8600 2963 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
AnnaBridge 157:e7ca05fa8600 2964 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
AnnaBridge 157:e7ca05fa8600 2965 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
AnnaBridge 157:e7ca05fa8600 2966 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
AnnaBridge 157:e7ca05fa8600 2967 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
AnnaBridge 157:e7ca05fa8600 2968 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
AnnaBridge 157:e7ca05fa8600 2969 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
AnnaBridge 157:e7ca05fa8600 2970 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
AnnaBridge 157:e7ca05fa8600 2971 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
AnnaBridge 157:e7ca05fa8600 2972 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
AnnaBridge 157:e7ca05fa8600 2973 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 2974 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 2975 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
AnnaBridge 157:e7ca05fa8600 2976 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 2977 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
AnnaBridge 157:e7ca05fa8600 2978 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
AnnaBridge 157:e7ca05fa8600 2979 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
AnnaBridge 157:e7ca05fa8600 2980 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
AnnaBridge 157:e7ca05fa8600 2981 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
AnnaBridge 157:e7ca05fa8600 2982 /* alias CMSIS for compatibilities */
AnnaBridge 157:e7ca05fa8600 2983 #define SDIO_IRQn SDMMC1_IRQn
AnnaBridge 157:e7ca05fa8600 2984 #define SDIO_IRQHandler SDMMC1_IRQHandler
AnnaBridge 157:e7ca05fa8600 2985 #endif
AnnaBridge 157:e7ca05fa8600 2986 /**
AnnaBridge 157:e7ca05fa8600 2987 * @}
AnnaBridge 157:e7ca05fa8600 2988 */
AnnaBridge 157:e7ca05fa8600 2989
AnnaBridge 157:e7ca05fa8600 2990 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 2991 * @{
AnnaBridge 157:e7ca05fa8600 2992 */
AnnaBridge 157:e7ca05fa8600 2993
AnnaBridge 157:e7ca05fa8600 2994 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 2995 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 2996 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
AnnaBridge 157:e7ca05fa8600 2997 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
AnnaBridge 157:e7ca05fa8600 2998 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
AnnaBridge 157:e7ca05fa8600 2999 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
AnnaBridge 157:e7ca05fa8600 3000
AnnaBridge 157:e7ca05fa8600 3001 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3002 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3003
AnnaBridge 157:e7ca05fa8600 3004 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
AnnaBridge 157:e7ca05fa8600 3005
AnnaBridge 157:e7ca05fa8600 3006 /**
AnnaBridge 157:e7ca05fa8600 3007 * @}
AnnaBridge 157:e7ca05fa8600 3008 */
AnnaBridge 157:e7ca05fa8600 3009
AnnaBridge 157:e7ca05fa8600 3010 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3011 * @{
AnnaBridge 157:e7ca05fa8600 3012 */
AnnaBridge 157:e7ca05fa8600 3013 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
AnnaBridge 157:e7ca05fa8600 3014 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
AnnaBridge 157:e7ca05fa8600 3015 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
AnnaBridge 157:e7ca05fa8600 3016 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
AnnaBridge 157:e7ca05fa8600 3017 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
AnnaBridge 157:e7ca05fa8600 3018 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
AnnaBridge 157:e7ca05fa8600 3019 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
AnnaBridge 157:e7ca05fa8600 3020 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
AnnaBridge 157:e7ca05fa8600 3021 /**
AnnaBridge 157:e7ca05fa8600 3022 * @}
AnnaBridge 157:e7ca05fa8600 3023 */
AnnaBridge 157:e7ca05fa8600 3024
AnnaBridge 157:e7ca05fa8600 3025 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3026 * @{
AnnaBridge 157:e7ca05fa8600 3027 */
AnnaBridge 157:e7ca05fa8600 3028
AnnaBridge 157:e7ca05fa8600 3029 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
AnnaBridge 157:e7ca05fa8600 3030 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
AnnaBridge 157:e7ca05fa8600 3031 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
AnnaBridge 157:e7ca05fa8600 3032
AnnaBridge 157:e7ca05fa8600 3033 /**
AnnaBridge 157:e7ca05fa8600 3034 * @}
AnnaBridge 157:e7ca05fa8600 3035 */
AnnaBridge 157:e7ca05fa8600 3036
AnnaBridge 157:e7ca05fa8600 3037 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3038 * @{
AnnaBridge 157:e7ca05fa8600 3039 */
AnnaBridge 157:e7ca05fa8600 3040
AnnaBridge 157:e7ca05fa8600 3041 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3042 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge 157:e7ca05fa8600 3043 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3044 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge 157:e7ca05fa8600 3045
AnnaBridge 157:e7ca05fa8600 3046 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
AnnaBridge 157:e7ca05fa8600 3047
AnnaBridge 157:e7ca05fa8600 3048 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
AnnaBridge 157:e7ca05fa8600 3049 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
AnnaBridge 157:e7ca05fa8600 3050
AnnaBridge 157:e7ca05fa8600 3051 /**
AnnaBridge 157:e7ca05fa8600 3052 * @}
AnnaBridge 157:e7ca05fa8600 3053 */
AnnaBridge 157:e7ca05fa8600 3054
AnnaBridge 157:e7ca05fa8600 3055
AnnaBridge 157:e7ca05fa8600 3056 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3057 * @{
AnnaBridge 157:e7ca05fa8600 3058 */
AnnaBridge 157:e7ca05fa8600 3059
AnnaBridge 157:e7ca05fa8600 3060 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 3061 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 3062 #define __USART_ENABLE __HAL_USART_ENABLE
AnnaBridge 157:e7ca05fa8600 3063 #define __USART_DISABLE __HAL_USART_DISABLE
AnnaBridge 157:e7ca05fa8600 3064
AnnaBridge 157:e7ca05fa8600 3065 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3066 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge 157:e7ca05fa8600 3067
AnnaBridge 157:e7ca05fa8600 3068 /**
AnnaBridge 157:e7ca05fa8600 3069 * @}
AnnaBridge 157:e7ca05fa8600 3070 */
AnnaBridge 157:e7ca05fa8600 3071
AnnaBridge 157:e7ca05fa8600 3072 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3073 * @{
AnnaBridge 157:e7ca05fa8600 3074 */
AnnaBridge 157:e7ca05fa8600 3075 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
AnnaBridge 157:e7ca05fa8600 3076
AnnaBridge 157:e7ca05fa8600 3077 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 3078 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3079 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3080 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
AnnaBridge 157:e7ca05fa8600 3081
AnnaBridge 157:e7ca05fa8600 3082 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 3083 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3084 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3085 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
AnnaBridge 157:e7ca05fa8600 3086
AnnaBridge 157:e7ca05fa8600 3087 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 3088 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 3089 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
AnnaBridge 157:e7ca05fa8600 3090 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 3091 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 3092 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3093 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3094
AnnaBridge 157:e7ca05fa8600 3095 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 3096 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 3097 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
AnnaBridge 157:e7ca05fa8600 3098 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 3099 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 3100 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3101 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3102 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge 157:e7ca05fa8600 3103
AnnaBridge 157:e7ca05fa8600 3104 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 3105 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 3106 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
AnnaBridge 157:e7ca05fa8600 3107 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 3108 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 157:e7ca05fa8600 3109 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3110 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 157:e7ca05fa8600 3111 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge 157:e7ca05fa8600 3112
AnnaBridge 157:e7ca05fa8600 3113 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
AnnaBridge 157:e7ca05fa8600 3114 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
AnnaBridge 157:e7ca05fa8600 3115
AnnaBridge 157:e7ca05fa8600 3116 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
AnnaBridge 157:e7ca05fa8600 3117 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
AnnaBridge 157:e7ca05fa8600 3118 /**
AnnaBridge 157:e7ca05fa8600 3119 * @}
AnnaBridge 157:e7ca05fa8600 3120 */
AnnaBridge 157:e7ca05fa8600 3121
AnnaBridge 157:e7ca05fa8600 3122 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3123 * @{
AnnaBridge 157:e7ca05fa8600 3124 */
AnnaBridge 157:e7ca05fa8600 3125 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
AnnaBridge 157:e7ca05fa8600 3126 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
AnnaBridge 157:e7ca05fa8600 3127
AnnaBridge 157:e7ca05fa8600 3128 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge 157:e7ca05fa8600 3129 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
AnnaBridge 157:e7ca05fa8600 3130
AnnaBridge 157:e7ca05fa8600 3131 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge 157:e7ca05fa8600 3132
AnnaBridge 157:e7ca05fa8600 3133 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
AnnaBridge 157:e7ca05fa8600 3134 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
AnnaBridge 157:e7ca05fa8600 3135 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
AnnaBridge 157:e7ca05fa8600 3136 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
AnnaBridge 157:e7ca05fa8600 3137 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
AnnaBridge 157:e7ca05fa8600 3138 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
AnnaBridge 157:e7ca05fa8600 3139 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
AnnaBridge 157:e7ca05fa8600 3140 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
AnnaBridge 157:e7ca05fa8600 3141 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
AnnaBridge 157:e7ca05fa8600 3142 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
AnnaBridge 157:e7ca05fa8600 3143 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
AnnaBridge 157:e7ca05fa8600 3144 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
AnnaBridge 157:e7ca05fa8600 3145
AnnaBridge 157:e7ca05fa8600 3146 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
AnnaBridge 157:e7ca05fa8600 3147 /**
AnnaBridge 157:e7ca05fa8600 3148 * @}
AnnaBridge 157:e7ca05fa8600 3149 */
AnnaBridge 157:e7ca05fa8600 3150
AnnaBridge 157:e7ca05fa8600 3151 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3152 * @{
AnnaBridge 157:e7ca05fa8600 3153 */
AnnaBridge 157:e7ca05fa8600 3154
AnnaBridge 157:e7ca05fa8600 3155 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 157:e7ca05fa8600 3156 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 157:e7ca05fa8600 3157 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
AnnaBridge 157:e7ca05fa8600 3158 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 157:e7ca05fa8600 3159 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
AnnaBridge 157:e7ca05fa8600 3160 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
AnnaBridge 157:e7ca05fa8600 3161 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
AnnaBridge 157:e7ca05fa8600 3162
AnnaBridge 157:e7ca05fa8600 3163 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
AnnaBridge 157:e7ca05fa8600 3164 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
AnnaBridge 157:e7ca05fa8600 3165 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
AnnaBridge 157:e7ca05fa8600 3166 /**
AnnaBridge 157:e7ca05fa8600 3167 * @}
AnnaBridge 157:e7ca05fa8600 3168 */
AnnaBridge 157:e7ca05fa8600 3169
AnnaBridge 157:e7ca05fa8600 3170 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3171 * @{
AnnaBridge 157:e7ca05fa8600 3172 */
AnnaBridge 157:e7ca05fa8600 3173 #define __HAL_LTDC_LAYER LTDC_LAYER
AnnaBridge 157:e7ca05fa8600 3174 /**
AnnaBridge 157:e7ca05fa8600 3175 * @}
AnnaBridge 157:e7ca05fa8600 3176 */
AnnaBridge 157:e7ca05fa8600 3177
AnnaBridge 157:e7ca05fa8600 3178 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3179 * @{
AnnaBridge 157:e7ca05fa8600 3180 */
AnnaBridge 157:e7ca05fa8600 3181 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
AnnaBridge 157:e7ca05fa8600 3182 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
AnnaBridge 157:e7ca05fa8600 3183 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
AnnaBridge 157:e7ca05fa8600 3184 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
AnnaBridge 157:e7ca05fa8600 3185 #define SAI_STREOMODE SAI_STEREOMODE
AnnaBridge 157:e7ca05fa8600 3186 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
AnnaBridge 157:e7ca05fa8600 3187 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
AnnaBridge 157:e7ca05fa8600 3188 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
AnnaBridge 157:e7ca05fa8600 3189 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
AnnaBridge 157:e7ca05fa8600 3190 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
AnnaBridge 157:e7ca05fa8600 3191 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
AnnaBridge 157:e7ca05fa8600 3192 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
AnnaBridge 157:e7ca05fa8600 3193 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
AnnaBridge 157:e7ca05fa8600 3194 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
AnnaBridge 157:e7ca05fa8600 3195 /**
AnnaBridge 157:e7ca05fa8600 3196 * @}
AnnaBridge 157:e7ca05fa8600 3197 */
AnnaBridge 157:e7ca05fa8600 3198
AnnaBridge 157:e7ca05fa8600 3199
AnnaBridge 157:e7ca05fa8600 3200 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
AnnaBridge 157:e7ca05fa8600 3201 * @{
AnnaBridge 157:e7ca05fa8600 3202 */
AnnaBridge 157:e7ca05fa8600 3203
AnnaBridge 157:e7ca05fa8600 3204 /**
AnnaBridge 157:e7ca05fa8600 3205 * @}
AnnaBridge 157:e7ca05fa8600 3206 */
AnnaBridge 157:e7ca05fa8600 3207
AnnaBridge 157:e7ca05fa8600 3208 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 3209 }
AnnaBridge 157:e7ca05fa8600 3210 #endif
AnnaBridge 157:e7ca05fa8600 3211
AnnaBridge 157:e7ca05fa8600 3212 #endif /* ___STM32_HAL_LEGACY */
AnnaBridge 157:e7ca05fa8600 3213
AnnaBridge 157:e7ca05fa8600 3214 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 157:e7ca05fa8600 3215