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TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/stm32f7xx_hal_nor.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_hal_nor.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of NOR HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_HAL_NOR_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_HAL_NOR_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx_ll_fmc.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 49 * @{
AnnaBridge 171:3a7713b1edbc 50 */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /** @addtogroup NOR
AnnaBridge 171:3a7713b1edbc 53 * @{
AnnaBridge 171:3a7713b1edbc 54 */
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 57 /** @defgroup NOR_Exported_Types NOR Exported Types
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief HAL SRAM State structures definition
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 typedef enum
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 67 HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 68 HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
AnnaBridge 171:3a7713b1edbc 69 HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
AnnaBridge 171:3a7713b1edbc 70 HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
AnnaBridge 171:3a7713b1edbc 71 }HAL_NOR_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @brief FMC NOR Status typedef
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef enum
AnnaBridge 171:3a7713b1edbc 77 {
AnnaBridge 171:3a7713b1edbc 78 HAL_NOR_STATUS_SUCCESS = 0U,
AnnaBridge 171:3a7713b1edbc 79 HAL_NOR_STATUS_ONGOING,
AnnaBridge 171:3a7713b1edbc 80 HAL_NOR_STATUS_ERROR,
AnnaBridge 171:3a7713b1edbc 81 HAL_NOR_STATUS_TIMEOUT
AnnaBridge 171:3a7713b1edbc 82 }HAL_NOR_StatusTypeDef;
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /**
AnnaBridge 171:3a7713b1edbc 85 * @brief FMC NOR ID typedef
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87 typedef struct
AnnaBridge 171:3a7713b1edbc 88 {
AnnaBridge 171:3a7713b1edbc 89 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 uint16_t Device_Code1;
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 uint16_t Device_Code2;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
AnnaBridge 171:3a7713b1edbc 96 These codes can be accessed by performing read operations with specific
AnnaBridge 171:3a7713b1edbc 97 control signals and addresses set.They can also be accessed by issuing
AnnaBridge 171:3a7713b1edbc 98 an Auto Select command */
AnnaBridge 171:3a7713b1edbc 99 }NOR_IDTypeDef;
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /**
AnnaBridge 171:3a7713b1edbc 102 * @brief FMC NOR CFI typedef
AnnaBridge 171:3a7713b1edbc 103 */
AnnaBridge 171:3a7713b1edbc 104 typedef struct
AnnaBridge 171:3a7713b1edbc 105 {
AnnaBridge 171:3a7713b1edbc 106 /*!< Defines the information stored in the memory's Common flash interface
AnnaBridge 171:3a7713b1edbc 107 which contains a description of various electrical and timing parameters,
AnnaBridge 171:3a7713b1edbc 108 density information and functions supported by the memory */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 uint16_t CFI_1;
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 uint16_t CFI_2;
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 uint16_t CFI_3;
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 uint16_t CFI_4;
AnnaBridge 171:3a7713b1edbc 117 }NOR_CFITypeDef;
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /**
AnnaBridge 171:3a7713b1edbc 120 * @brief NOR handle Structure definition
AnnaBridge 171:3a7713b1edbc 121 */
AnnaBridge 171:3a7713b1edbc 122 typedef struct
AnnaBridge 171:3a7713b1edbc 123 {
AnnaBridge 171:3a7713b1edbc 124 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 HAL_LockTypeDef Lock; /*!< NOR locking object */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 }NOR_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 135 /**
AnnaBridge 171:3a7713b1edbc 136 * @}
AnnaBridge 171:3a7713b1edbc 137 */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 140 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 141 /** @defgroup NOR_Exported_Macros NOR Exported Macros
AnnaBridge 171:3a7713b1edbc 142 * @{
AnnaBridge 171:3a7713b1edbc 143 */
AnnaBridge 171:3a7713b1edbc 144 /** @brief Reset NOR handle state
AnnaBridge 171:3a7713b1edbc 145 * @param __HANDLE__ specifies the NOR handle.
AnnaBridge 171:3a7713b1edbc 146 * @retval None
AnnaBridge 171:3a7713b1edbc 147 */
AnnaBridge 171:3a7713b1edbc 148 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 149 /**
AnnaBridge 171:3a7713b1edbc 150 * @}
AnnaBridge 171:3a7713b1edbc 151 */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 154 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
AnnaBridge 171:3a7713b1edbc 155 * @{
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 159 * @{
AnnaBridge 171:3a7713b1edbc 160 */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 /* Initialization/de-initialization functions ********************************/
AnnaBridge 171:3a7713b1edbc 163 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 171:3a7713b1edbc 164 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 165 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 166 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 167 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 168 /**
AnnaBridge 171:3a7713b1edbc 169 * @}
AnnaBridge 171:3a7713b1edbc 170 */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
AnnaBridge 171:3a7713b1edbc 173 * @{
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /* I/O operation functions ***************************************************/
AnnaBridge 171:3a7713b1edbc 177 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
AnnaBridge 171:3a7713b1edbc 178 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 179 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 171:3a7713b1edbc 180 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 171:3a7713b1edbc 183 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
AnnaBridge 171:3a7713b1edbc 186 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
AnnaBridge 171:3a7713b1edbc 187 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
AnnaBridge 171:3a7713b1edbc 188 /**
AnnaBridge 171:3a7713b1edbc 189 * @}
AnnaBridge 171:3a7713b1edbc 190 */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
AnnaBridge 171:3a7713b1edbc 193 * @{
AnnaBridge 171:3a7713b1edbc 194 */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /* NOR Control functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 197 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 198 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 199 /**
AnnaBridge 171:3a7713b1edbc 200 * @}
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
AnnaBridge 171:3a7713b1edbc 204 * @{
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /* NOR State functions ********************************************************/
AnnaBridge 171:3a7713b1edbc 208 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
AnnaBridge 171:3a7713b1edbc 209 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 210 /**
AnnaBridge 171:3a7713b1edbc 211 * @}
AnnaBridge 171:3a7713b1edbc 212 */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /**
AnnaBridge 171:3a7713b1edbc 215 * @}
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 219 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 220 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 221 /** @defgroup NOR_Private_Constants NOR Private Constants
AnnaBridge 171:3a7713b1edbc 222 * @{
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 /* NOR device IDs addresses */
AnnaBridge 171:3a7713b1edbc 225 #define MC_ADDRESS ((uint16_t)0x0000U)
AnnaBridge 171:3a7713b1edbc 226 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
AnnaBridge 171:3a7713b1edbc 227 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
AnnaBridge 171:3a7713b1edbc 228 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /* NOR CFI IDs addresses */
AnnaBridge 171:3a7713b1edbc 231 #define CFI1_ADDRESS ((uint16_t)0x61U)
AnnaBridge 171:3a7713b1edbc 232 #define CFI2_ADDRESS ((uint16_t)0x62U)
AnnaBridge 171:3a7713b1edbc 233 #define CFI3_ADDRESS ((uint16_t)0x63U)
AnnaBridge 171:3a7713b1edbc 234 #define CFI4_ADDRESS ((uint16_t)0x64U)
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /* NOR operation wait timeout */
AnnaBridge 171:3a7713b1edbc 237 #define NOR_TMEOUT ((uint16_t)0xFFFFU)
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /* NOR memory data width */
AnnaBridge 171:3a7713b1edbc 240 #define NOR_MEMORY_8B ((uint8_t)0x0U)
AnnaBridge 171:3a7713b1edbc 241 #define NOR_MEMORY_16B ((uint8_t)0x1U)
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /* NOR memory device read/write start address */
AnnaBridge 171:3a7713b1edbc 244 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
AnnaBridge 171:3a7713b1edbc 245 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
AnnaBridge 171:3a7713b1edbc 246 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
AnnaBridge 171:3a7713b1edbc 247 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 * @}
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 253 /** @defgroup NOR_Private_Macros NOR Private Macros
AnnaBridge 171:3a7713b1edbc 254 * @{
AnnaBridge 171:3a7713b1edbc 255 */
AnnaBridge 171:3a7713b1edbc 256 /**
AnnaBridge 171:3a7713b1edbc 257 * @brief NOR memory address shifting.
AnnaBridge 171:3a7713b1edbc 258 * @param __NOR_ADDRESS NOR base address
AnnaBridge 171:3a7713b1edbc 259 * @param __NOR_MEMORY_WIDTH_ NOR memory width
AnnaBridge 171:3a7713b1edbc 260 * @param __ADDRESS__ NOR memory address
AnnaBridge 171:3a7713b1edbc 261 * @retval NOR shifted address value
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
AnnaBridge 171:3a7713b1edbc 264 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
AnnaBridge 171:3a7713b1edbc 265 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
AnnaBridge 171:3a7713b1edbc 266 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /**
AnnaBridge 171:3a7713b1edbc 269 * @brief NOR memory write data to specified address.
AnnaBridge 171:3a7713b1edbc 270 * @param __ADDRESS__ NOR memory address
AnnaBridge 171:3a7713b1edbc 271 * @param __DATA__ Data to write
AnnaBridge 171:3a7713b1edbc 272 * @retval None
AnnaBridge 171:3a7713b1edbc 273 */
AnnaBridge 171:3a7713b1edbc 274 #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
AnnaBridge 171:3a7713b1edbc 275 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
AnnaBridge 171:3a7713b1edbc 276 __DSB(); \
AnnaBridge 171:3a7713b1edbc 277 } while(0)
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /**
AnnaBridge 171:3a7713b1edbc 280 * @}
AnnaBridge 171:3a7713b1edbc 281 */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /**
AnnaBridge 171:3a7713b1edbc 284 * @}
AnnaBridge 171:3a7713b1edbc 285 */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /**
AnnaBridge 171:3a7713b1edbc 288 * @}
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 292 }
AnnaBridge 171:3a7713b1edbc 293 #endif
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 #endif /* __STM32F7xx_HAL_NOR_H */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/