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TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/stm32f7xx_hal_dma2d.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_dma2d.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DMA2D HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_DMA2D_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_DMA2D_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | #if defined (DMA2D) |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 50 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /** @addtogroup DMA2D DMA2D |
| AnnaBridge | 171:3a7713b1edbc | 54 | * @brief DMA2D HAL module driver |
| AnnaBridge | 171:3a7713b1edbc | 55 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 56 | */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | |
| AnnaBridge | 171:3a7713b1edbc | 58 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup DMA2D_Exported_Types DMA2D Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 61 | */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #define MAX_DMA2D_LAYER 2 |
| AnnaBridge | 171:3a7713b1edbc | 63 | |
| AnnaBridge | 171:3a7713b1edbc | 64 | /** |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @brief DMA2D color Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 66 | */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 68 | { |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t Blue; /*!< Configures the blue value. |
| AnnaBridge | 171:3a7713b1edbc | 70 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t Green; /*!< Configures the green value. |
| AnnaBridge | 171:3a7713b1edbc | 73 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | |
| AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t Red; /*!< Configures the red value. |
| AnnaBridge | 171:3a7713b1edbc | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | } DMA2D_ColorTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /** |
| AnnaBridge | 171:3a7713b1edbc | 80 | * @brief DMA2D CLUT Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 81 | */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 83 | { |
| AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ |
| AnnaBridge | 171:3a7713b1edbc | 85 | |
| AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. |
| AnnaBridge | 171:3a7713b1edbc | 87 | This parameter can be one value of @ref DMA2D_CLUT_CM. */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t Size; /*!< Configures the DMA2D CLUT size. |
| AnnaBridge | 171:3a7713b1edbc | 90 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ |
| AnnaBridge | 171:3a7713b1edbc | 91 | } DMA2D_CLUTCfgTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 92 | |
| AnnaBridge | 171:3a7713b1edbc | 93 | /** |
| AnnaBridge | 171:3a7713b1edbc | 94 | * @brief DMA2D Init structure definition |
| AnnaBridge | 171:3a7713b1edbc | 95 | */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 97 | { |
| AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t Mode; /*!< Configures the DMA2D transfer mode. |
| AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be one value of @ref DMA2D_Mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | |
| AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t ColorMode; /*!< Configures the color format of the output image. |
| AnnaBridge | 171:3a7713b1edbc | 102 | This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | |
| AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t OutputOffset; /*!< Specifies the Offset value. |
| AnnaBridge | 171:3a7713b1edbc | 105 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #if defined (DMA2D_OPFCCR_AI) |
| AnnaBridge | 171:3a7713b1edbc | 107 | uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. |
| AnnaBridge | 171:3a7713b1edbc | 108 | This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #endif /* DMA2D_OPFCCR_AI */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | #if defined (DMA2D_OPFCCR_RBS) |
| AnnaBridge | 171:3a7713b1edbc | 112 | uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) |
| AnnaBridge | 171:3a7713b1edbc | 113 | for the output pixel format converter. |
| AnnaBridge | 171:3a7713b1edbc | 114 | This parameter can be one value of @ref DMA2D_RB_Swap. */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #endif /* DMA2D_OPFCCR_RBS */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | |
| AnnaBridge | 171:3a7713b1edbc | 117 | } DMA2D_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 118 | |
| AnnaBridge | 171:3a7713b1edbc | 119 | |
| AnnaBridge | 171:3a7713b1edbc | 120 | /** |
| AnnaBridge | 171:3a7713b1edbc | 121 | * @brief DMA2D Layer structure definition |
| AnnaBridge | 171:3a7713b1edbc | 122 | */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 124 | { |
| AnnaBridge | 171:3a7713b1edbc | 125 | uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. |
| AnnaBridge | 171:3a7713b1edbc | 126 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | |
| AnnaBridge | 171:3a7713b1edbc | 128 | uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. |
| AnnaBridge | 171:3a7713b1edbc | 129 | This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | |
| AnnaBridge | 171:3a7713b1edbc | 131 | uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. |
| AnnaBridge | 171:3a7713b1edbc | 132 | This parameter can be one value of @ref DMA2D_Alpha_Mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | |
| AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. |
| AnnaBridge | 171:3a7713b1edbc | 135 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. |
| AnnaBridge | 171:3a7713b1edbc | 136 | @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between |
| AnnaBridge | 171:3a7713b1edbc | 137 | Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where |
| AnnaBridge | 171:3a7713b1edbc | 138 | - InputAlpha[24:31] is the alpha value ALPHA[0:7] |
| AnnaBridge | 171:3a7713b1edbc | 139 | - InputAlpha[16:23] is the red value RED[0:7] |
| AnnaBridge | 171:3a7713b1edbc | 140 | - InputAlpha[8:15] is the green value GREEN[0:7] |
| AnnaBridge | 171:3a7713b1edbc | 141 | - InputAlpha[0:7] is the blue value BLUE[0:7]. */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | |
| AnnaBridge | 171:3a7713b1edbc | 143 | #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) |
| AnnaBridge | 171:3a7713b1edbc | 144 | uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. |
| AnnaBridge | 171:3a7713b1edbc | 145 | This parameter can be one value of @ref DMA2D_Alpha_Inverted. |
| AnnaBridge | 171:3a7713b1edbc | 146 | This feature is only available on devices : |
| AnnaBridge | 171:3a7713b1edbc | 147 | STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/ |
| AnnaBridge | 171:3a7713b1edbc | 148 | |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) |
| AnnaBridge | 171:3a7713b1edbc | 152 | uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). |
| AnnaBridge | 171:3a7713b1edbc | 153 | This parameter can be one value of @ref DMA2D_RB_Swap |
| AnnaBridge | 171:3a7713b1edbc | 154 | This feature is only available on devices : |
| AnnaBridge | 171:3a7713b1edbc | 155 | STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/ |
| AnnaBridge | 171:3a7713b1edbc | 156 | |
| AnnaBridge | 171:3a7713b1edbc | 157 | #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | |
| AnnaBridge | 171:3a7713b1edbc | 159 | } DMA2D_LayerCfgTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 160 | |
| AnnaBridge | 171:3a7713b1edbc | 161 | /** |
| AnnaBridge | 171:3a7713b1edbc | 162 | * @brief HAL DMA2D State structures definition |
| AnnaBridge | 171:3a7713b1edbc | 163 | */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | typedef enum |
| AnnaBridge | 171:3a7713b1edbc | 165 | { |
| AnnaBridge | 171:3a7713b1edbc | 166 | HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | }HAL_DMA2D_StateTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 173 | |
| AnnaBridge | 171:3a7713b1edbc | 174 | /** |
| AnnaBridge | 171:3a7713b1edbc | 175 | * @brief DMA2D handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 176 | */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | typedef struct __DMA2D_HandleTypeDef |
| AnnaBridge | 171:3a7713b1edbc | 178 | { |
| AnnaBridge | 171:3a7713b1edbc | 179 | DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | |
| AnnaBridge | 171:3a7713b1edbc | 181 | DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | |
| AnnaBridge | 171:3a7713b1edbc | 183 | void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | |
| AnnaBridge | 171:3a7713b1edbc | 185 | void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | |
| AnnaBridge | 171:3a7713b1edbc | 187 | DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | |
| AnnaBridge | 171:3a7713b1edbc | 189 | HAL_LockTypeDef Lock; /*!< DMA2D lock. */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | |
| AnnaBridge | 171:3a7713b1edbc | 193 | __IO uint32_t ErrorCode; /*!< DMA2D error code. */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | } DMA2D_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 195 | /** |
| AnnaBridge | 171:3a7713b1edbc | 196 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 197 | */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | |
| AnnaBridge | 171:3a7713b1edbc | 199 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 200 | /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 201 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 202 | */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | |
| AnnaBridge | 171:3a7713b1edbc | 204 | /** @defgroup DMA2D_Error_Code DMA2D Error Code |
| AnnaBridge | 171:3a7713b1edbc | 205 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 206 | */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | /** |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 214 | */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | |
| AnnaBridge | 171:3a7713b1edbc | 216 | /** @defgroup DMA2D_Mode DMA2D Mode |
| AnnaBridge | 171:3a7713b1edbc | 217 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 218 | */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | /** |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 225 | */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | |
| AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 229 | */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | /** |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | |
| AnnaBridge | 171:3a7713b1edbc | 239 | /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode |
| AnnaBridge | 171:3a7713b1edbc | 240 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 241 | */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | /** |
| AnnaBridge | 171:3a7713b1edbc | 254 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 255 | */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | |
| AnnaBridge | 171:3a7713b1edbc | 257 | /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode |
| AnnaBridge | 171:3a7713b1edbc | 258 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 259 | */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value |
| AnnaBridge | 171:3a7713b1edbc | 263 | with original alpha channel value */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | /** |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 266 | */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 276 | */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) |
| AnnaBridge | 171:3a7713b1edbc | 280 | /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 282 | */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | /** |
| AnnaBridge | 171:3a7713b1edbc | 286 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 287 | */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | |
| AnnaBridge | 171:3a7713b1edbc | 290 | /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode |
| AnnaBridge | 171:3a7713b1edbc | 291 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 292 | */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | /** |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 297 | */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | |
| AnnaBridge | 171:3a7713b1edbc | 299 | |
| AnnaBridge | 171:3a7713b1edbc | 300 | /** @defgroup DMA2D_Interrupts DMA2D Interrupts |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 302 | */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup DMA2D_Flags DMA2D Flags |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | /** |
| AnnaBridge | 171:3a7713b1edbc | 323 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 324 | */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | |
| AnnaBridge | 171:3a7713b1edbc | 326 | /** @defgroup DMA2D_Aliases DMA2D API Aliases |
| AnnaBridge | 171:3a7713b1edbc | 327 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 328 | */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | /** |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 332 | */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | |
| AnnaBridge | 171:3a7713b1edbc | 334 | |
| AnnaBridge | 171:3a7713b1edbc | 335 | /** |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 337 | */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | /* Exported macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 339 | /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 340 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 341 | */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | |
| AnnaBridge | 171:3a7713b1edbc | 343 | /** @brief Reset DMA2D handle state |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @param __HANDLE__ specifies the DMA2D handle. |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 346 | */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 348 | |
| AnnaBridge | 171:3a7713b1edbc | 349 | /** |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @brief Enable the DMA2D. |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 353 | */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) |
| AnnaBridge | 171:3a7713b1edbc | 355 | |
| AnnaBridge | 171:3a7713b1edbc | 356 | |
| AnnaBridge | 171:3a7713b1edbc | 357 | /* Interrupt & Flag management */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | /** |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @brief Get the DMA2D pending flags. |
| AnnaBridge | 171:3a7713b1edbc | 360 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 361 | * @param __FLAG__ flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 362 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
| AnnaBridge | 171:3a7713b1edbc | 365 | * @arg DMA2D_FLAG_CAE: CLUT access error flag |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| AnnaBridge | 171:3a7713b1edbc | 367 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @retval The state of FLAG. |
| AnnaBridge | 171:3a7713b1edbc | 370 | */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 372 | |
| AnnaBridge | 171:3a7713b1edbc | 373 | /** |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @brief Clear the DMA2D pending flags. |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @param __FLAG__ specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 377 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @arg DMA2D_FLAG_CAE: CLUT access error flag |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| AnnaBridge | 171:3a7713b1edbc | 382 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| AnnaBridge | 171:3a7713b1edbc | 384 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 385 | */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 387 | |
| AnnaBridge | 171:3a7713b1edbc | 388 | /** |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @brief Enable the specified DMA2D interrupts. |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. |
| AnnaBridge | 171:3a7713b1edbc | 392 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 398 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 399 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 400 | */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 402 | |
| AnnaBridge | 171:3a7713b1edbc | 403 | /** |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @brief Disable the specified DMA2D interrupts. |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. |
| AnnaBridge | 171:3a7713b1edbc | 407 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 408 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 412 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 413 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 414 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 415 | */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 417 | |
| AnnaBridge | 171:3a7713b1edbc | 418 | /** |
| AnnaBridge | 171:3a7713b1edbc | 419 | * @brief Check whether the specified DMA2D interrupt source is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @param __HANDLE__ DMA2D handle |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. |
| AnnaBridge | 171:3a7713b1edbc | 422 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @retval The state of INTERRUPT source. |
| AnnaBridge | 171:3a7713b1edbc | 430 | */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 432 | |
| AnnaBridge | 171:3a7713b1edbc | 433 | /** |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 435 | */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | |
| AnnaBridge | 171:3a7713b1edbc | 437 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 438 | /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 439 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 440 | */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | |
| AnnaBridge | 171:3a7713b1edbc | 442 | /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 171:3a7713b1edbc | 443 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 444 | */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | |
| AnnaBridge | 171:3a7713b1edbc | 446 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 171:3a7713b1edbc | 447 | HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 448 | HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 449 | void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 450 | void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | /** |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 454 | */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | |
| AnnaBridge | 171:3a7713b1edbc | 457 | /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 459 | */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | |
| AnnaBridge | 171:3a7713b1edbc | 461 | /* IO operation functions *******************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 462 | HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 171:3a7713b1edbc | 463 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 171:3a7713b1edbc | 464 | HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 171:3a7713b1edbc | 465 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 171:3a7713b1edbc | 466 | HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 467 | HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 468 | HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 469 | HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 470 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 471 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 472 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 473 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 474 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 475 | HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 476 | void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 477 | void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 478 | void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 479 | |
| AnnaBridge | 171:3a7713b1edbc | 480 | /** |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 482 | */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | |
| AnnaBridge | 171:3a7713b1edbc | 484 | /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions |
| AnnaBridge | 171:3a7713b1edbc | 485 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 486 | */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | |
| AnnaBridge | 171:3a7713b1edbc | 488 | /* Peripheral Control functions *************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 489 | HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 490 | HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 171:3a7713b1edbc | 491 | HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); |
| AnnaBridge | 171:3a7713b1edbc | 492 | HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 493 | HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 494 | HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); |
| AnnaBridge | 171:3a7713b1edbc | 495 | |
| AnnaBridge | 171:3a7713b1edbc | 496 | /** |
| AnnaBridge | 171:3a7713b1edbc | 497 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 498 | */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | |
| AnnaBridge | 171:3a7713b1edbc | 500 | /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 502 | */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | |
| AnnaBridge | 171:3a7713b1edbc | 504 | /* Peripheral State functions ***************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 505 | HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 506 | uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 171:3a7713b1edbc | 507 | |
| AnnaBridge | 171:3a7713b1edbc | 508 | /** |
| AnnaBridge | 171:3a7713b1edbc | 509 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 510 | */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | |
| AnnaBridge | 171:3a7713b1edbc | 512 | /** |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 514 | */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | |
| AnnaBridge | 171:3a7713b1edbc | 516 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 517 | |
| AnnaBridge | 171:3a7713b1edbc | 518 | /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 520 | */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | |
| AnnaBridge | 171:3a7713b1edbc | 522 | /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 524 | */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | /** |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 528 | */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | |
| AnnaBridge | 171:3a7713b1edbc | 530 | /** @defgroup DMA2D_Color_Value DMA2D Color Value |
| AnnaBridge | 171:3a7713b1edbc | 531 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 532 | */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | /** |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 536 | */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | |
| AnnaBridge | 171:3a7713b1edbc | 538 | /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 540 | */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | /** |
| AnnaBridge | 171:3a7713b1edbc | 543 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 544 | */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | /** @defgroup DMA2D_Offset DMA2D Offset |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 548 | */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | /** |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 552 | */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | |
| AnnaBridge | 171:3a7713b1edbc | 554 | /** @defgroup DMA2D_Size DMA2D Size |
| AnnaBridge | 171:3a7713b1edbc | 555 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 556 | */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | /** |
| AnnaBridge | 171:3a7713b1edbc | 560 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 561 | */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | |
| AnnaBridge | 171:3a7713b1edbc | 563 | /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size |
| AnnaBridge | 171:3a7713b1edbc | 564 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 565 | */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | /** |
| AnnaBridge | 171:3a7713b1edbc | 568 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 569 | */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | |
| AnnaBridge | 171:3a7713b1edbc | 571 | /** |
| AnnaBridge | 171:3a7713b1edbc | 572 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 573 | */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | |
| AnnaBridge | 171:3a7713b1edbc | 575 | |
| AnnaBridge | 171:3a7713b1edbc | 576 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 577 | /** @defgroup DMA2D_Private_Macros DMA2D Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 579 | */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 582 | ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ |
| AnnaBridge | 171:3a7713b1edbc | 584 | ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ |
| AnnaBridge | 171:3a7713b1edbc | 585 | ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ |
| AnnaBridge | 171:3a7713b1edbc | 591 | ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ |
| AnnaBridge | 171:3a7713b1edbc | 592 | ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 593 | ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ |
| AnnaBridge | 171:3a7713b1edbc | 594 | ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 595 | ((INPUT_CM) == DMA2D_INPUT_A4)) |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ |
| AnnaBridge | 171:3a7713b1edbc | 597 | ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ |
| AnnaBridge | 171:3a7713b1edbc | 598 | ((AlphaMode) == DMA2D_COMBINE_ALPHA)) |
| AnnaBridge | 171:3a7713b1edbc | 599 | |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ |
| AnnaBridge | 171:3a7713b1edbc | 601 | ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) |
| AnnaBridge | 171:3a7713b1edbc | 602 | |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ |
| AnnaBridge | 171:3a7713b1edbc | 604 | ((RB_Swap) == DMA2D_RB_SWAP)) |
| AnnaBridge | 171:3a7713b1edbc | 605 | |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 610 | ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 611 | ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 613 | ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 614 | ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) |
| AnnaBridge | 171:3a7713b1edbc | 615 | /** |
| AnnaBridge | 171:3a7713b1edbc | 616 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 617 | */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | |
| AnnaBridge | 171:3a7713b1edbc | 619 | /** |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 621 | */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | |
| AnnaBridge | 171:3a7713b1edbc | 623 | /** |
| AnnaBridge | 171:3a7713b1edbc | 624 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 625 | */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | |
| AnnaBridge | 171:3a7713b1edbc | 627 | #endif /* DMA2D */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | |
| AnnaBridge | 171:3a7713b1edbc | 629 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 630 | } |
| AnnaBridge | 171:3a7713b1edbc | 631 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 632 | |
| AnnaBridge | 171:3a7713b1edbc | 633 | #endif /* __STM32F7xx_HAL_DMA2D_H */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | |
| AnnaBridge | 171:3a7713b1edbc | 635 | |
| AnnaBridge | 171:3a7713b1edbc | 636 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
