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TARGET_NUCLEO_F413ZH/TOOLCHAIN_GCC_ARM/stm32f4xx_ll_fsmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@163:e59c8e839560

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/**
AnnaBridge	161:aa5281ff4a02	2	******************************************************************************
AnnaBridge	161:aa5281ff4a02	3	* @file stm32f4xx_ll_fsmc.h
AnnaBridge	161:aa5281ff4a02	4	* @author MCD Application Team
AnnaBridge	161:aa5281ff4a02	5	* @brief Header file of FSMC HAL module.
AnnaBridge	161:aa5281ff4a02	6	******************************************************************************
AnnaBridge	161:aa5281ff4a02	7	* @attention
AnnaBridge	161:aa5281ff4a02	8	*
AnnaBridge	161:aa5281ff4a02	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	161:aa5281ff4a02	10	*
AnnaBridge	161:aa5281ff4a02	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	161:aa5281ff4a02	12	* are permitted provided that the following conditions are met:
AnnaBridge	161:aa5281ff4a02	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	161:aa5281ff4a02	14	* this list of conditions and the following disclaimer.
AnnaBridge	161:aa5281ff4a02	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	161:aa5281ff4a02	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	161:aa5281ff4a02	17	* and/or other materials provided with the distribution.
AnnaBridge	161:aa5281ff4a02	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	161:aa5281ff4a02	19	* may be used to endorse or promote products derived from this software
AnnaBridge	161:aa5281ff4a02	20	* without specific prior written permission.
AnnaBridge	161:aa5281ff4a02	21	*
AnnaBridge	161:aa5281ff4a02	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	161:aa5281ff4a02	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	161:aa5281ff4a02	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	161:aa5281ff4a02	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	161:aa5281ff4a02	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	161:aa5281ff4a02	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	161:aa5281ff4a02	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	161:aa5281ff4a02	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	161:aa5281ff4a02	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	161:aa5281ff4a02	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	161:aa5281ff4a02	32	*
AnnaBridge	161:aa5281ff4a02	33	******************************************************************************
AnnaBridge	161:aa5281ff4a02	34	*/
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	161:aa5281ff4a02	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	161:aa5281ff4a02	37	#ifndef __STM32F4xx_LL_FSMC_H
AnnaBridge	161:aa5281ff4a02	38	#define __STM32F4xx_LL_FSMC_H
AnnaBridge	161:aa5281ff4a02	39
AnnaBridge	161:aa5281ff4a02	40	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	41	extern "C" {
AnnaBridge	161:aa5281ff4a02	42	#endif
AnnaBridge	161:aa5281ff4a02	43
AnnaBridge	161:aa5281ff4a02	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	161:aa5281ff4a02	46
AnnaBridge	161:aa5281ff4a02	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	161:aa5281ff4a02	48	* @{
AnnaBridge	161:aa5281ff4a02	49	*/
AnnaBridge	161:aa5281ff4a02	50
AnnaBridge	161:aa5281ff4a02	51	/** @addtogroup FSMC_LL
AnnaBridge	161:aa5281ff4a02	52	* @{
AnnaBridge	161:aa5281ff4a02	53	*/
AnnaBridge	161:aa5281ff4a02	54
AnnaBridge	161:aa5281ff4a02	55	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	161:aa5281ff4a02	56	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	161:aa5281ff4a02	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	58	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
AnnaBridge	161:aa5281ff4a02	59	* @{
AnnaBridge	161:aa5281ff4a02	60	*/
AnnaBridge	161:aa5281ff4a02	61
AnnaBridge	161:aa5281ff4a02	62	/**
AnnaBridge	161:aa5281ff4a02	63	* @brief FSMC NORSRAM Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	64	*/
AnnaBridge	161:aa5281ff4a02	65	typedef struct
AnnaBridge	161:aa5281ff4a02	66	{
AnnaBridge	161:aa5281ff4a02	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	161:aa5281ff4a02	68	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
AnnaBridge	161:aa5281ff4a02	69
AnnaBridge	161:aa5281ff4a02	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	161:aa5281ff4a02	71	multiplexed on the data bus or not.
AnnaBridge	161:aa5281ff4a02	72	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
AnnaBridge	161:aa5281ff4a02	73
AnnaBridge	161:aa5281ff4a02	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	161:aa5281ff4a02	75	the corresponding memory device.
AnnaBridge	161:aa5281ff4a02	76	This parameter can be a value of @ref FSMC_Memory_Type */
AnnaBridge	161:aa5281ff4a02	77
AnnaBridge	161:aa5281ff4a02	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	161:aa5281ff4a02	79	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
AnnaBridge	161:aa5281ff4a02	80
AnnaBridge	161:aa5281ff4a02	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	161:aa5281ff4a02	82	valid only with synchronous burst Flash memories.
AnnaBridge	161:aa5281ff4a02	83	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
AnnaBridge	161:aa5281ff4a02	84
AnnaBridge	161:aa5281ff4a02	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	161:aa5281ff4a02	86	the Flash memory in burst mode.
AnnaBridge	161:aa5281ff4a02	87	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
AnnaBridge	161:aa5281ff4a02	88
AnnaBridge	161:aa5281ff4a02	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	161:aa5281ff4a02	90	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	161:aa5281ff4a02	91	This parameter can be a value of @ref FSMC_Wrap_Mode
AnnaBridge	161:aa5281ff4a02	92	This mode is available only for the STM32F405/407/4015/417xx devices */
AnnaBridge	161:aa5281ff4a02	93
AnnaBridge	161:aa5281ff4a02	94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	161:aa5281ff4a02	95	clock cycle before the wait state or during the wait state,
AnnaBridge	161:aa5281ff4a02	96	valid only when accessing memories in burst mode.
AnnaBridge	161:aa5281ff4a02	97	This parameter can be a value of @ref FSMC_Wait_Timing */
AnnaBridge	161:aa5281ff4a02	98
AnnaBridge	161:aa5281ff4a02	99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
AnnaBridge	161:aa5281ff4a02	100	This parameter can be a value of @ref FSMC_Write_Operation */
AnnaBridge	161:aa5281ff4a02	101
AnnaBridge	161:aa5281ff4a02	102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	161:aa5281ff4a02	103	signal, valid for Flash memory access in burst mode.
AnnaBridge	161:aa5281ff4a02	104	This parameter can be a value of @ref FSMC_Wait_Signal */
AnnaBridge	161:aa5281ff4a02	105
AnnaBridge	161:aa5281ff4a02	106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	161:aa5281ff4a02	107	This parameter can be a value of @ref FSMC_Extended_Mode */
AnnaBridge	161:aa5281ff4a02	108
AnnaBridge	161:aa5281ff4a02	109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	161:aa5281ff4a02	110	valid only with asynchronous Flash memories.
AnnaBridge	161:aa5281ff4a02	111	This parameter can be a value of @ref FSMC_AsynchronousWait */
AnnaBridge	161:aa5281ff4a02	112
AnnaBridge	161:aa5281ff4a02	113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	161:aa5281ff4a02	114	This parameter can be a value of @ref FSMC_Write_Burst */
AnnaBridge	161:aa5281ff4a02	115
AnnaBridge	161:aa5281ff4a02	116	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	161:aa5281ff4a02	117	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	161:aa5281ff4a02	118	through FMC_BCR2..4 registers.
AnnaBridge	161:aa5281ff4a02	119	This parameter can be a value of @ref FMC_Continous_Clock
AnnaBridge	161:aa5281ff4a02	120	This mode is available only for the STM32F412Vx/Zx/Rx devices */
AnnaBridge	161:aa5281ff4a02	121
AnnaBridge	161:aa5281ff4a02	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	161:aa5281ff4a02	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	161:aa5281ff4a02	124	through FMC_BCR2..4 registers.
AnnaBridge	161:aa5281ff4a02	125	This parameter can be a value of @ref FMC_Write_FIFO
AnnaBridge	161:aa5281ff4a02	126	This mode is available only for the STM32F412Vx/Vx devices */
AnnaBridge	161:aa5281ff4a02	127
AnnaBridge	161:aa5281ff4a02	128	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	161:aa5281ff4a02	129	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	161:aa5281ff4a02	130	}FSMC_NORSRAM_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	131
AnnaBridge	161:aa5281ff4a02	132	/**
AnnaBridge	161:aa5281ff4a02	133	* @brief FSMC NORSRAM Timing parameters structure definition
AnnaBridge	161:aa5281ff4a02	134	*/
AnnaBridge	161:aa5281ff4a02	135	typedef struct
AnnaBridge	161:aa5281ff4a02	136	{
AnnaBridge	161:aa5281ff4a02	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	138	the duration of the address setup time.
AnnaBridge	161:aa5281ff4a02	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	140	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	141
AnnaBridge	161:aa5281ff4a02	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	143	the duration of the address hold time.
AnnaBridge	161:aa5281ff4a02	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	145	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	146
AnnaBridge	161:aa5281ff4a02	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	148	the duration of the data setup time.
AnnaBridge	161:aa5281ff4a02	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	161:aa5281ff4a02	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	161:aa5281ff4a02	151	NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	152
AnnaBridge	161:aa5281ff4a02	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	154	the duration of the bus turnaround.
AnnaBridge	161:aa5281ff4a02	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	156	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	157
AnnaBridge	161:aa5281ff4a02	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	161:aa5281ff4a02	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	161:aa5281ff4a02	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	161:aa5281ff4a02	161	accesses. */
AnnaBridge	161:aa5281ff4a02	162
AnnaBridge	161:aa5281ff4a02	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	161:aa5281ff4a02	164	to the memory before getting the first data.
AnnaBridge	161:aa5281ff4a02	165	The parameter value depends on the memory type as shown below:
AnnaBridge	161:aa5281ff4a02	166	- It must be set to 0 in case of a CRAM
AnnaBridge	161:aa5281ff4a02	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	161:aa5281ff4a02	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	161:aa5281ff4a02	169	with synchronous burst mode enable */
AnnaBridge	161:aa5281ff4a02	170
AnnaBridge	161:aa5281ff4a02	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	161:aa5281ff4a02	172	This parameter can be a value of @ref FSMC_Access_Mode */
AnnaBridge	161:aa5281ff4a02	173
AnnaBridge	161:aa5281ff4a02	174	}FSMC_NORSRAM_TimingTypeDef;
AnnaBridge	161:aa5281ff4a02	175
AnnaBridge	161:aa5281ff4a02	176	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	177	/**
AnnaBridge	161:aa5281ff4a02	178	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	179	*/
AnnaBridge	161:aa5281ff4a02	180	typedef struct
AnnaBridge	161:aa5281ff4a02	181	{
AnnaBridge	161:aa5281ff4a02	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	161:aa5281ff4a02	183	This parameter can be a value of @ref FSMC_NAND_Bank */
AnnaBridge	161:aa5281ff4a02	184
AnnaBridge	161:aa5281ff4a02	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	161:aa5281ff4a02	186	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	161:aa5281ff4a02	187
AnnaBridge	161:aa5281ff4a02	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	161:aa5281ff4a02	189	This parameter can be any value of @ref FSMC_NAND_Data_Width */
AnnaBridge	161:aa5281ff4a02	190
AnnaBridge	161:aa5281ff4a02	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	161:aa5281ff4a02	192	This parameter can be any value of @ref FSMC_ECC */
AnnaBridge	161:aa5281ff4a02	193
AnnaBridge	161:aa5281ff4a02	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	161:aa5281ff4a02	195	This parameter can be any value of @ref FSMC_ECC_Page_Size */
AnnaBridge	161:aa5281ff4a02	196
AnnaBridge	161:aa5281ff4a02	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	198	delay between CLE low and RE low.
AnnaBridge	161:aa5281ff4a02	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	200
AnnaBridge	161:aa5281ff4a02	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	202	delay between ALE low and RE low.
AnnaBridge	161:aa5281ff4a02	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	204
AnnaBridge	161:aa5281ff4a02	205	}FSMC_NAND_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	206
AnnaBridge	161:aa5281ff4a02	207	/**
AnnaBridge	161:aa5281ff4a02	208	* @brief FSMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	161:aa5281ff4a02	209	*/
AnnaBridge	161:aa5281ff4a02	210	typedef struct
AnnaBridge	161:aa5281ff4a02	211	{
AnnaBridge	161:aa5281ff4a02	212	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	161:aa5281ff4a02	213	the command assertion for NAND-Flash read or write access
AnnaBridge	161:aa5281ff4a02	214	to common/Attribute or I/O memory space (depending on
AnnaBridge	161:aa5281ff4a02	215	the memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	216	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	217
AnnaBridge	161:aa5281ff4a02	218	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	161:aa5281ff4a02	219	command for NAND-Flash read or write access to
AnnaBridge	161:aa5281ff4a02	220	common/Attribute or I/O memory space (depending on the
AnnaBridge	161:aa5281ff4a02	221	memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	223
AnnaBridge	161:aa5281ff4a02	224	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	161:aa5281ff4a02	225	(and data for write access) after the command de-assertion
AnnaBridge	161:aa5281ff4a02	226	for NAND-Flash read or write access to common/Attribute
AnnaBridge	161:aa5281ff4a02	227	or I/O memory space (depending on the memory space timing
AnnaBridge	161:aa5281ff4a02	228	to be configured).
AnnaBridge	161:aa5281ff4a02	229	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	230
AnnaBridge	161:aa5281ff4a02	231	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	161:aa5281ff4a02	232	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	161:aa5281ff4a02	233	write access to common/Attribute or I/O memory space (depending
AnnaBridge	161:aa5281ff4a02	234	on the memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	235	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	236
AnnaBridge	161:aa5281ff4a02	237	}FSMC_NAND_PCC_TimingTypeDef;
AnnaBridge	161:aa5281ff4a02	238
AnnaBridge	161:aa5281ff4a02	239	/**
AnnaBridge	161:aa5281ff4a02	240	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	241	*/
AnnaBridge	161:aa5281ff4a02	242	typedef struct
AnnaBridge	161:aa5281ff4a02	243	{
AnnaBridge	161:aa5281ff4a02	244	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	161:aa5281ff4a02	245	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	161:aa5281ff4a02	246
AnnaBridge	161:aa5281ff4a02	247	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	248	delay between CLE low and RE low.
AnnaBridge	161:aa5281ff4a02	249	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	250
AnnaBridge	161:aa5281ff4a02	251	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	252	delay between ALE low and RE low.
AnnaBridge	161:aa5281ff4a02	253	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	254
AnnaBridge	161:aa5281ff4a02	255	}FSMC_PCCARD_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	256	/**
AnnaBridge	161:aa5281ff4a02	257	* @}
AnnaBridge	161:aa5281ff4a02	258	*/
AnnaBridge	161:aa5281ff4a02	259	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	260
AnnaBridge	161:aa5281ff4a02	261	/* Private constants ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	262	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
AnnaBridge	161:aa5281ff4a02	263	* @{
AnnaBridge	161:aa5281ff4a02	264	*/
AnnaBridge	161:aa5281ff4a02	265
AnnaBridge	161:aa5281ff4a02	266	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
AnnaBridge	161:aa5281ff4a02	267	* @{
AnnaBridge	161:aa5281ff4a02	268	*/
AnnaBridge	161:aa5281ff4a02	269	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
AnnaBridge	161:aa5281ff4a02	270	* @{
AnnaBridge	161:aa5281ff4a02	271	*/
AnnaBridge	161:aa5281ff4a02	272	#define FSMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	161:aa5281ff4a02	273	#define FSMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	161:aa5281ff4a02	274	#define FSMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	161:aa5281ff4a02	275	#define FSMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	161:aa5281ff4a02	276	/**
AnnaBridge	161:aa5281ff4a02	277	* @}
AnnaBridge	161:aa5281ff4a02	278	*/
AnnaBridge	161:aa5281ff4a02	279
AnnaBridge	161:aa5281ff4a02	280	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
AnnaBridge	161:aa5281ff4a02	281	* @{
AnnaBridge	161:aa5281ff4a02	282	*/
AnnaBridge	161:aa5281ff4a02	283	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	284	#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	285	/**
AnnaBridge	161:aa5281ff4a02	286	* @}
AnnaBridge	161:aa5281ff4a02	287	*/
AnnaBridge	161:aa5281ff4a02	288
AnnaBridge	161:aa5281ff4a02	289	/** @defgroup FSMC_Memory_Type FSMC Memory Type
AnnaBridge	161:aa5281ff4a02	290	* @{
AnnaBridge	161:aa5281ff4a02	291	*/
AnnaBridge	161:aa5281ff4a02	292	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	161:aa5281ff4a02	293	#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge	161:aa5281ff4a02	294	#define FSMC_MEMORY_TYPE_NOR 0x00000008U
AnnaBridge	161:aa5281ff4a02	295	/**
AnnaBridge	161:aa5281ff4a02	296	* @}
AnnaBridge	161:aa5281ff4a02	297	*/
AnnaBridge	161:aa5281ff4a02	298
AnnaBridge	161:aa5281ff4a02	299	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
AnnaBridge	161:aa5281ff4a02	300	* @{
AnnaBridge	161:aa5281ff4a02	301	*/
AnnaBridge	161:aa5281ff4a02	302	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	303	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	161:aa5281ff4a02	304	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	161:aa5281ff4a02	305	/**
AnnaBridge	161:aa5281ff4a02	306	* @}
AnnaBridge	161:aa5281ff4a02	307	*/
AnnaBridge	161:aa5281ff4a02	308
AnnaBridge	161:aa5281ff4a02	309	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
AnnaBridge	161:aa5281ff4a02	310	* @{
AnnaBridge	161:aa5281ff4a02	311	*/
AnnaBridge	161:aa5281ff4a02	312	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge	161:aa5281ff4a02	313	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	314	/**
AnnaBridge	161:aa5281ff4a02	315	* @}
AnnaBridge	161:aa5281ff4a02	316	*/
AnnaBridge	161:aa5281ff4a02	317
AnnaBridge	161:aa5281ff4a02	318	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
AnnaBridge	161:aa5281ff4a02	319	* @{
AnnaBridge	161:aa5281ff4a02	320	*/
AnnaBridge	161:aa5281ff4a02	321	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	322	#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
AnnaBridge	161:aa5281ff4a02	323	/**
AnnaBridge	161:aa5281ff4a02	324	* @}
AnnaBridge	161:aa5281ff4a02	325	*/
AnnaBridge	161:aa5281ff4a02	326
AnnaBridge	161:aa5281ff4a02	327	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
AnnaBridge	161:aa5281ff4a02	328	* @{
AnnaBridge	161:aa5281ff4a02	329	*/
AnnaBridge	161:aa5281ff4a02	330	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	161:aa5281ff4a02	331	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
AnnaBridge	161:aa5281ff4a02	332	/**
AnnaBridge	161:aa5281ff4a02	333	* @}
AnnaBridge	161:aa5281ff4a02	334	*/
AnnaBridge	161:aa5281ff4a02	335
AnnaBridge	161:aa5281ff4a02	336	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
AnnaBridge	161:aa5281ff4a02	337	* @note These values are available only for the STM32F405/415/407/417xx devices.
AnnaBridge	161:aa5281ff4a02	338	* @{
AnnaBridge	161:aa5281ff4a02	339	*/
AnnaBridge	161:aa5281ff4a02	340	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	341	#define FSMC_WRAP_MODE_ENABLE 0x00000400U
AnnaBridge	161:aa5281ff4a02	342	/**
AnnaBridge	161:aa5281ff4a02	343	* @}
AnnaBridge	161:aa5281ff4a02	344	*/
AnnaBridge	161:aa5281ff4a02	345
AnnaBridge	161:aa5281ff4a02	346	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
AnnaBridge	161:aa5281ff4a02	347	* @{
AnnaBridge	161:aa5281ff4a02	348	*/
AnnaBridge	161:aa5281ff4a02	349	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	161:aa5281ff4a02	350	#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
AnnaBridge	161:aa5281ff4a02	351	/**
AnnaBridge	161:aa5281ff4a02	352	* @}
AnnaBridge	161:aa5281ff4a02	353	*/
AnnaBridge	161:aa5281ff4a02	354
AnnaBridge	161:aa5281ff4a02	355	/** @defgroup FSMC_Write_Operation FSMC Write Operation
AnnaBridge	161:aa5281ff4a02	356	* @{
AnnaBridge	161:aa5281ff4a02	357	*/
AnnaBridge	161:aa5281ff4a02	358	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	359	#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
AnnaBridge	161:aa5281ff4a02	360	/**
AnnaBridge	161:aa5281ff4a02	361	* @}
AnnaBridge	161:aa5281ff4a02	362	*/
AnnaBridge	161:aa5281ff4a02	363
AnnaBridge	161:aa5281ff4a02	364	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
AnnaBridge	161:aa5281ff4a02	365	* @{
AnnaBridge	161:aa5281ff4a02	366	*/
AnnaBridge	161:aa5281ff4a02	367	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	368	#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
AnnaBridge	161:aa5281ff4a02	369	/**
AnnaBridge	161:aa5281ff4a02	370	* @}
AnnaBridge	161:aa5281ff4a02	371	*/
AnnaBridge	161:aa5281ff4a02	372
AnnaBridge	161:aa5281ff4a02	373	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
AnnaBridge	161:aa5281ff4a02	374	* @{
AnnaBridge	161:aa5281ff4a02	375	*/
AnnaBridge	161:aa5281ff4a02	376	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	377	#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
AnnaBridge	161:aa5281ff4a02	378	/**
AnnaBridge	161:aa5281ff4a02	379	* @}
AnnaBridge	161:aa5281ff4a02	380	*/
AnnaBridge	161:aa5281ff4a02	381
AnnaBridge	161:aa5281ff4a02	382	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
AnnaBridge	161:aa5281ff4a02	383	* @{
AnnaBridge	161:aa5281ff4a02	384	*/
AnnaBridge	161:aa5281ff4a02	385	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	386	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
AnnaBridge	161:aa5281ff4a02	387	/**
AnnaBridge	161:aa5281ff4a02	388	* @}
AnnaBridge	161:aa5281ff4a02	389	*/
AnnaBridge	161:aa5281ff4a02	390
AnnaBridge	161:aa5281ff4a02	391	/** @defgroup FSMC_Page_Size FSMC Page Size
AnnaBridge	161:aa5281ff4a02	392	* @{
AnnaBridge	161:aa5281ff4a02	393	*/
AnnaBridge	161:aa5281ff4a02	394	#define FSMC_PAGE_SIZE_NONE 0x00000000U
AnnaBridge	161:aa5281ff4a02	395	#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
AnnaBridge	161:aa5281ff4a02	396	#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
AnnaBridge	161:aa5281ff4a02	397	#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 \| FSMC_BCR1_CPSIZE_1))
AnnaBridge	161:aa5281ff4a02	398	#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
AnnaBridge	161:aa5281ff4a02	399	/**
AnnaBridge	161:aa5281ff4a02	400	* @}
AnnaBridge	161:aa5281ff4a02	401	*/
AnnaBridge	161:aa5281ff4a02	402
AnnaBridge	161:aa5281ff4a02	403	/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
AnnaBridge	161:aa5281ff4a02	404	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
AnnaBridge	161:aa5281ff4a02	405	* @{
AnnaBridge	161:aa5281ff4a02	406	*/
AnnaBridge	161:aa5281ff4a02	407	#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
AnnaBridge	161:aa5281ff4a02	408	#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	409	/**
AnnaBridge	161:aa5281ff4a02	410	* @}
AnnaBridge	161:aa5281ff4a02	411	*/
AnnaBridge	161:aa5281ff4a02	412
AnnaBridge	161:aa5281ff4a02	413	/** @defgroup FSMC_Write_Burst FSMC Write Burst
AnnaBridge	161:aa5281ff4a02	414	* @{
AnnaBridge	161:aa5281ff4a02	415	*/
AnnaBridge	161:aa5281ff4a02	416	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	417	#define FSMC_WRITE_BURST_ENABLE 0x00080000U
AnnaBridge	161:aa5281ff4a02	418	/**
AnnaBridge	161:aa5281ff4a02	419	* @}
AnnaBridge	161:aa5281ff4a02	420	*/
AnnaBridge	161:aa5281ff4a02	421
AnnaBridge	161:aa5281ff4a02	422	/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
AnnaBridge	161:aa5281ff4a02	423	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
AnnaBridge	161:aa5281ff4a02	424	* @{
AnnaBridge	161:aa5281ff4a02	425	*/
AnnaBridge	161:aa5281ff4a02	426	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge	161:aa5281ff4a02	427	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
AnnaBridge	161:aa5281ff4a02	428	/**
AnnaBridge	161:aa5281ff4a02	429	* @}
AnnaBridge	161:aa5281ff4a02	430	*/
AnnaBridge	161:aa5281ff4a02	431
AnnaBridge	161:aa5281ff4a02	432	/** @defgroup FSMC_Access_Mode FSMC Access Mode
AnnaBridge	161:aa5281ff4a02	433	* @{
AnnaBridge	161:aa5281ff4a02	434	*/
AnnaBridge	161:aa5281ff4a02	435	#define FSMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	161:aa5281ff4a02	436	#define FSMC_ACCESS_MODE_B 0x10000000U
AnnaBridge	161:aa5281ff4a02	437	#define FSMC_ACCESS_MODE_C 0x20000000U
AnnaBridge	161:aa5281ff4a02	438	#define FSMC_ACCESS_MODE_D 0x30000000U
AnnaBridge	161:aa5281ff4a02	439	/**
AnnaBridge	161:aa5281ff4a02	440	* @}
AnnaBridge	161:aa5281ff4a02	441	*/
AnnaBridge	161:aa5281ff4a02	442	/**
AnnaBridge	161:aa5281ff4a02	443	* @}
AnnaBridge	161:aa5281ff4a02	444	*/
AnnaBridge	161:aa5281ff4a02	445
AnnaBridge	161:aa5281ff4a02	446	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	447	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
AnnaBridge	161:aa5281ff4a02	448	* @{
AnnaBridge	161:aa5281ff4a02	449	*/
AnnaBridge	161:aa5281ff4a02	450	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
AnnaBridge	161:aa5281ff4a02	451	* @{
AnnaBridge	161:aa5281ff4a02	452	*/
AnnaBridge	161:aa5281ff4a02	453	#define FSMC_NAND_BANK2 0x00000010U
AnnaBridge	161:aa5281ff4a02	454	#define FSMC_NAND_BANK3 0x00000100U
AnnaBridge	161:aa5281ff4a02	455	/**
AnnaBridge	161:aa5281ff4a02	456	* @}
AnnaBridge	161:aa5281ff4a02	457	*/
AnnaBridge	161:aa5281ff4a02	458
AnnaBridge	161:aa5281ff4a02	459	/** @defgroup FSMC_Wait_feature FSMC Wait feature
AnnaBridge	161:aa5281ff4a02	460	* @{
AnnaBridge	161:aa5281ff4a02	461	*/
AnnaBridge	161:aa5281ff4a02	462	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	463	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	464	/**
AnnaBridge	161:aa5281ff4a02	465	* @}
AnnaBridge	161:aa5281ff4a02	466	*/
AnnaBridge	161:aa5281ff4a02	467
AnnaBridge	161:aa5281ff4a02	468	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
AnnaBridge	161:aa5281ff4a02	469	* @{
AnnaBridge	161:aa5281ff4a02	470	*/
AnnaBridge	161:aa5281ff4a02	471	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	161:aa5281ff4a02	472	#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
AnnaBridge	161:aa5281ff4a02	473	/**
AnnaBridge	161:aa5281ff4a02	474	* @}
AnnaBridge	161:aa5281ff4a02	475	*/
AnnaBridge	161:aa5281ff4a02	476
AnnaBridge	161:aa5281ff4a02	477	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
AnnaBridge	161:aa5281ff4a02	478	* @{
AnnaBridge	161:aa5281ff4a02	479	*/
AnnaBridge	161:aa5281ff4a02	480	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	481	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	161:aa5281ff4a02	482	/**
AnnaBridge	161:aa5281ff4a02	483	* @}
AnnaBridge	161:aa5281ff4a02	484	*/
AnnaBridge	161:aa5281ff4a02	485
AnnaBridge	161:aa5281ff4a02	486	/** @defgroup FSMC_ECC FSMC ECC
AnnaBridge	161:aa5281ff4a02	487	* @{
AnnaBridge	161:aa5281ff4a02	488	*/
AnnaBridge	161:aa5281ff4a02	489	#define FSMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	490	#define FSMC_NAND_ECC_ENABLE 0x00000040U
AnnaBridge	161:aa5281ff4a02	491	/**
AnnaBridge	161:aa5281ff4a02	492	* @}
AnnaBridge	161:aa5281ff4a02	493	*/
AnnaBridge	161:aa5281ff4a02	494
AnnaBridge	161:aa5281ff4a02	495	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
AnnaBridge	161:aa5281ff4a02	496	* @{
AnnaBridge	161:aa5281ff4a02	497	*/
AnnaBridge	161:aa5281ff4a02	498	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	161:aa5281ff4a02	499	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge	161:aa5281ff4a02	500	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge	161:aa5281ff4a02	501	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge	161:aa5281ff4a02	502	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge	161:aa5281ff4a02	503	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
AnnaBridge	161:aa5281ff4a02	504	/**
AnnaBridge	161:aa5281ff4a02	505	* @}
AnnaBridge	161:aa5281ff4a02	506	*/
AnnaBridge	161:aa5281ff4a02	507	/**
AnnaBridge	161:aa5281ff4a02	508	* @}
AnnaBridge	161:aa5281ff4a02	509	*/
AnnaBridge	161:aa5281ff4a02	510	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	511
AnnaBridge	161:aa5281ff4a02	512	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
AnnaBridge	161:aa5281ff4a02	513	* @{
AnnaBridge	161:aa5281ff4a02	514	*/
AnnaBridge	161:aa5281ff4a02	515	#define FSMC_IT_RISING_EDGE 0x00000008U
AnnaBridge	161:aa5281ff4a02	516	#define FSMC_IT_LEVEL 0x00000010U
AnnaBridge	161:aa5281ff4a02	517	#define FSMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge	161:aa5281ff4a02	518	#define FSMC_IT_REFRESH_ERROR 0x00004000U
AnnaBridge	161:aa5281ff4a02	519	/**
AnnaBridge	161:aa5281ff4a02	520	* @}
AnnaBridge	161:aa5281ff4a02	521	*/
AnnaBridge	161:aa5281ff4a02	522
AnnaBridge	161:aa5281ff4a02	523	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
AnnaBridge	161:aa5281ff4a02	524	* @{
AnnaBridge	161:aa5281ff4a02	525	*/
AnnaBridge	161:aa5281ff4a02	526	#define FSMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge	161:aa5281ff4a02	527	#define FSMC_FLAG_LEVEL 0x00000002U
AnnaBridge	161:aa5281ff4a02	528	#define FSMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge	161:aa5281ff4a02	529	#define FSMC_FLAG_FEMPT 0x00000040U
AnnaBridge	161:aa5281ff4a02	530	/**
AnnaBridge	161:aa5281ff4a02	531	* @}
AnnaBridge	161:aa5281ff4a02	532	*/
AnnaBridge	161:aa5281ff4a02	533
AnnaBridge	161:aa5281ff4a02	534	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
AnnaBridge	161:aa5281ff4a02	535	* @{
AnnaBridge	161:aa5281ff4a02	536	*/
AnnaBridge	161:aa5281ff4a02	537	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
AnnaBridge	161:aa5281ff4a02	538	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
AnnaBridge	161:aa5281ff4a02	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	540	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
AnnaBridge	161:aa5281ff4a02	541	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
AnnaBridge	161:aa5281ff4a02	542	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	543
AnnaBridge	161:aa5281ff4a02	544	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
AnnaBridge	161:aa5281ff4a02	545	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
AnnaBridge	161:aa5281ff4a02	546	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	547	#define FSMC_NAND_DEVICE FSMC_Bank2_3
AnnaBridge	161:aa5281ff4a02	548	#define FSMC_PCCARD_DEVICE FSMC_Bank4
AnnaBridge	161:aa5281ff4a02	549	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	550
AnnaBridge	161:aa5281ff4a02	551	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
AnnaBridge	161:aa5281ff4a02	552	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
AnnaBridge	161:aa5281ff4a02	553	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
AnnaBridge	161:aa5281ff4a02	554
AnnaBridge	161:aa5281ff4a02	555	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
AnnaBridge	161:aa5281ff4a02	556	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	161:aa5281ff4a02	557	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
AnnaBridge	161:aa5281ff4a02	558	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
AnnaBridge	161:aa5281ff4a02	559
AnnaBridge	161:aa5281ff4a02	560	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
AnnaBridge	161:aa5281ff4a02	561	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
AnnaBridge	161:aa5281ff4a02	562	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
AnnaBridge	161:aa5281ff4a02	563	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
AnnaBridge	161:aa5281ff4a02	564	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
AnnaBridge	161:aa5281ff4a02	565	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
AnnaBridge	161:aa5281ff4a02	566
AnnaBridge	161:aa5281ff4a02	567	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
AnnaBridge	161:aa5281ff4a02	568	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
AnnaBridge	161:aa5281ff4a02	569
AnnaBridge	161:aa5281ff4a02	570	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	571	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
AnnaBridge	161:aa5281ff4a02	572	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
AnnaBridge	161:aa5281ff4a02	573	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
AnnaBridge	161:aa5281ff4a02	574
AnnaBridge	161:aa5281ff4a02	575	#define FMC_NAND_Init FSMC_NAND_Init
AnnaBridge	161:aa5281ff4a02	576	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
AnnaBridge	161:aa5281ff4a02	577	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
AnnaBridge	161:aa5281ff4a02	578	#define FMC_NAND_DeInit FSMC_NAND_DeInit
AnnaBridge	161:aa5281ff4a02	579	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
AnnaBridge	161:aa5281ff4a02	580	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
AnnaBridge	161:aa5281ff4a02	581	#define FMC_NAND_GetECC FSMC_NAND_GetECC
AnnaBridge	161:aa5281ff4a02	582	#define FMC_PCCARD_Init FSMC_PCCARD_Init
AnnaBridge	161:aa5281ff4a02	583	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
AnnaBridge	161:aa5281ff4a02	584	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
AnnaBridge	161:aa5281ff4a02	585	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
AnnaBridge	161:aa5281ff4a02	586	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
AnnaBridge	161:aa5281ff4a02	587
AnnaBridge	161:aa5281ff4a02	588	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
AnnaBridge	161:aa5281ff4a02	589	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
AnnaBridge	161:aa5281ff4a02	590	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
AnnaBridge	161:aa5281ff4a02	591	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
AnnaBridge	161:aa5281ff4a02	592	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
AnnaBridge	161:aa5281ff4a02	593	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
AnnaBridge	161:aa5281ff4a02	594	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
AnnaBridge	161:aa5281ff4a02	595	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
AnnaBridge	161:aa5281ff4a02	596	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
AnnaBridge	161:aa5281ff4a02	597	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
AnnaBridge	161:aa5281ff4a02	598	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
AnnaBridge	161:aa5281ff4a02	599	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
AnnaBridge	161:aa5281ff4a02	600	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	601
AnnaBridge	161:aa5281ff4a02	602	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
AnnaBridge	161:aa5281ff4a02	603	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	161:aa5281ff4a02	604	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	605	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
AnnaBridge	161:aa5281ff4a02	606	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
AnnaBridge	161:aa5281ff4a02	607	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	608
AnnaBridge	161:aa5281ff4a02	609	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
AnnaBridge	161:aa5281ff4a02	610	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
AnnaBridge	161:aa5281ff4a02	611	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	612	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
AnnaBridge	161:aa5281ff4a02	613	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
AnnaBridge	161:aa5281ff4a02	614
AnnaBridge	161:aa5281ff4a02	615	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
AnnaBridge	161:aa5281ff4a02	616	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	617
AnnaBridge	161:aa5281ff4a02	618	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
AnnaBridge	161:aa5281ff4a02	619	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
AnnaBridge	161:aa5281ff4a02	620	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
AnnaBridge	161:aa5281ff4a02	621
AnnaBridge	161:aa5281ff4a02	622	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
AnnaBridge	161:aa5281ff4a02	623	#define FMC_IT_LEVEL FSMC_IT_LEVEL
AnnaBridge	161:aa5281ff4a02	624	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
AnnaBridge	161:aa5281ff4a02	625	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
AnnaBridge	161:aa5281ff4a02	626
AnnaBridge	161:aa5281ff4a02	627	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
AnnaBridge	161:aa5281ff4a02	628	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
AnnaBridge	161:aa5281ff4a02	629	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
AnnaBridge	161:aa5281ff4a02	630	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
AnnaBridge	161:aa5281ff4a02	631	/**
AnnaBridge	161:aa5281ff4a02	632	* @}
AnnaBridge	161:aa5281ff4a02	633	*/
AnnaBridge	161:aa5281ff4a02	634
AnnaBridge	161:aa5281ff4a02	635	/**
AnnaBridge	161:aa5281ff4a02	636	* @}
AnnaBridge	161:aa5281ff4a02	637	*/
AnnaBridge	161:aa5281ff4a02	638
AnnaBridge	161:aa5281ff4a02	639	/* Private macro -------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	640	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
AnnaBridge	161:aa5281ff4a02	641	* @{
AnnaBridge	161:aa5281ff4a02	642	*/
AnnaBridge	161:aa5281ff4a02	643
AnnaBridge	161:aa5281ff4a02	644	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
AnnaBridge	161:aa5281ff4a02	645	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	161:aa5281ff4a02	646	* @{
AnnaBridge	161:aa5281ff4a02	647	*/
AnnaBridge	161:aa5281ff4a02	648	/**
AnnaBridge	161:aa5281ff4a02	649	* @brief Enable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	650	* @param __INSTANCE__ FSMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	651	* @param __BANK__ FSMC_NORSRAM Bank
AnnaBridge	161:aa5281ff4a02	652	* @retval none
AnnaBridge	161:aa5281ff4a02	653	*/
AnnaBridge	161:aa5281ff4a02	654	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
AnnaBridge	161:aa5281ff4a02	655
AnnaBridge	161:aa5281ff4a02	656	/**
AnnaBridge	161:aa5281ff4a02	657	* @brief Disable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	658	* @param __INSTANCE__ FSMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	659	* @param __BANK__ FSMC_NORSRAM Bank
AnnaBridge	161:aa5281ff4a02	660	* @retval none
AnnaBridge	161:aa5281ff4a02	661	*/
AnnaBridge	161:aa5281ff4a02	662	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
AnnaBridge	161:aa5281ff4a02	663	/**
AnnaBridge	161:aa5281ff4a02	664	* @}
AnnaBridge	161:aa5281ff4a02	665	*/
AnnaBridge	161:aa5281ff4a02	666
AnnaBridge	161:aa5281ff4a02	667	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
AnnaBridge	161:aa5281ff4a02	668	* @brief macros to handle NAND device enable/disable
AnnaBridge	161:aa5281ff4a02	669	* @{
AnnaBridge	161:aa5281ff4a02	670	*/
AnnaBridge	161:aa5281ff4a02	671	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	672	/**
AnnaBridge	161:aa5281ff4a02	673	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	674	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	675	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	676	* @retval none
AnnaBridge	161:aa5281ff4a02	677	*/
AnnaBridge	161:aa5281ff4a02	678	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
AnnaBridge	161:aa5281ff4a02	679	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
AnnaBridge	161:aa5281ff4a02	680
AnnaBridge	161:aa5281ff4a02	681	/**
AnnaBridge	161:aa5281ff4a02	682	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	683	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	684	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	685	* @retval none
AnnaBridge	161:aa5281ff4a02	686	*/
AnnaBridge	161:aa5281ff4a02	687	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
AnnaBridge	161:aa5281ff4a02	688	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
AnnaBridge	161:aa5281ff4a02	689	/**
AnnaBridge	161:aa5281ff4a02	690	* @}
AnnaBridge	161:aa5281ff4a02	691	*/
AnnaBridge	161:aa5281ff4a02	692
AnnaBridge	161:aa5281ff4a02	693	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
AnnaBridge	161:aa5281ff4a02	694	* @brief macros to handle SRAM read/write operations
AnnaBridge	161:aa5281ff4a02	695	* @{
AnnaBridge	161:aa5281ff4a02	696	*/
AnnaBridge	161:aa5281ff4a02	697	/**
AnnaBridge	161:aa5281ff4a02	698	* @brief Enable the PCCARD device access.
AnnaBridge	163:e59c8e839560	699	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	161:aa5281ff4a02	700	* @retval none
AnnaBridge	161:aa5281ff4a02	701	*/
AnnaBridge	161:aa5281ff4a02	702	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
AnnaBridge	161:aa5281ff4a02	703
AnnaBridge	161:aa5281ff4a02	704	/**
AnnaBridge	161:aa5281ff4a02	705	* @brief Disable the PCCARD device access.
AnnaBridge	163:e59c8e839560	706	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	161:aa5281ff4a02	707	* @retval none
AnnaBridge	161:aa5281ff4a02	708	*/
AnnaBridge	161:aa5281ff4a02	709	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
AnnaBridge	161:aa5281ff4a02	710	/**
AnnaBridge	161:aa5281ff4a02	711	* @}
AnnaBridge	161:aa5281ff4a02	712	*/
AnnaBridge	161:aa5281ff4a02	713
AnnaBridge	161:aa5281ff4a02	714	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
AnnaBridge	161:aa5281ff4a02	715	* @brief macros to handle FSMC flags and interrupts
AnnaBridge	161:aa5281ff4a02	716	* @{
AnnaBridge	161:aa5281ff4a02	717	*/
AnnaBridge	161:aa5281ff4a02	718	/**
AnnaBridge	161:aa5281ff4a02	719	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	720	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	721	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	722	* @param __INTERRUPT__ FSMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	723	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	724	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	725	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	726	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	727	* @retval None
AnnaBridge	161:aa5281ff4a02	728	*/
AnnaBridge	161:aa5281ff4a02	729	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
AnnaBridge	161:aa5281ff4a02	730	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
AnnaBridge	161:aa5281ff4a02	731
AnnaBridge	161:aa5281ff4a02	732	/**
AnnaBridge	161:aa5281ff4a02	733	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	734	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	735	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	736	* @param __INTERRUPT__ FSMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	737	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	738	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	739	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	740	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	741	* @retval None
AnnaBridge	161:aa5281ff4a02	742	*/
AnnaBridge	161:aa5281ff4a02	743	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
AnnaBridge	161:aa5281ff4a02	744	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
AnnaBridge	161:aa5281ff4a02	745
AnnaBridge	161:aa5281ff4a02	746	/**
AnnaBridge	161:aa5281ff4a02	747	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	748	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	749	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	750	* @param __FLAG__ FSMC_NAND flag
AnnaBridge	161:aa5281ff4a02	751	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	752	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	753	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	754	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	755	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	756	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	757	*/
AnnaBridge	161:aa5281ff4a02	758	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	161:aa5281ff4a02	759	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	161:aa5281ff4a02	760
AnnaBridge	161:aa5281ff4a02	761	/**
AnnaBridge	161:aa5281ff4a02	762	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	763	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	764	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	765	* @param __FLAG__ FSMC_NAND flag
AnnaBridge	161:aa5281ff4a02	766	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	767	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	768	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	769	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	770	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	771	* @retval None
AnnaBridge	161:aa5281ff4a02	772	*/
AnnaBridge	161:aa5281ff4a02	773	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
AnnaBridge	161:aa5281ff4a02	774	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
AnnaBridge	161:aa5281ff4a02	775
AnnaBridge	161:aa5281ff4a02	776	/**
AnnaBridge	161:aa5281ff4a02	777	* @brief Enable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	778	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	779	* @param __INTERRUPT__ FSMC_PCCARD interrupt
AnnaBridge	161:aa5281ff4a02	780	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	781	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	782	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	783	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	784	* @retval None
AnnaBridge	161:aa5281ff4a02	785	*/
AnnaBridge	161:aa5281ff4a02	786	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	787
AnnaBridge	161:aa5281ff4a02	788	/**
AnnaBridge	161:aa5281ff4a02	789	* @brief Disable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	790	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	791	* @param __INTERRUPT__ FSMC_PCCARD interrupt
AnnaBridge	161:aa5281ff4a02	792	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	793	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	794	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	795	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	796	* @retval None
AnnaBridge	161:aa5281ff4a02	797	*/
AnnaBridge	161:aa5281ff4a02	798	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	799
AnnaBridge	161:aa5281ff4a02	800	/**
AnnaBridge	161:aa5281ff4a02	801	* @brief Get flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	802	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	803	* @param __FLAG__ FSMC_PCCARD flag
AnnaBridge	161:aa5281ff4a02	804	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	805	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	806	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	807	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	808	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	809	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	810	*/
AnnaBridge	161:aa5281ff4a02	811	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	812
AnnaBridge	161:aa5281ff4a02	813	/**
AnnaBridge	161:aa5281ff4a02	814	* @brief Clear flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	815	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	816	* @param __FLAG__ FSMC_PCCARD flag
AnnaBridge	161:aa5281ff4a02	817	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	818	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	819	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	820	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	821	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	822	* @retval None
AnnaBridge	161:aa5281ff4a02	823	*/
AnnaBridge	161:aa5281ff4a02	824	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
AnnaBridge	161:aa5281ff4a02	825	/**
AnnaBridge	161:aa5281ff4a02	826	* @}
AnnaBridge	161:aa5281ff4a02	827	*/
AnnaBridge	161:aa5281ff4a02	828	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	829
AnnaBridge	161:aa5281ff4a02	830	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
AnnaBridge	161:aa5281ff4a02	831	* @{
AnnaBridge	161:aa5281ff4a02	832	*/
AnnaBridge	161:aa5281ff4a02	833	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
AnnaBridge	161:aa5281ff4a02	834	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
AnnaBridge	161:aa5281ff4a02	835	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
AnnaBridge	161:aa5281ff4a02	836	((__BANK__) == FSMC_NORSRAM_BANK4))
AnnaBridge	161:aa5281ff4a02	837
AnnaBridge	161:aa5281ff4a02	838	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	839	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	161:aa5281ff4a02	840
AnnaBridge	161:aa5281ff4a02	841	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	161:aa5281ff4a02	842	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	161:aa5281ff4a02	843	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
AnnaBridge	161:aa5281ff4a02	844
AnnaBridge	161:aa5281ff4a02	845	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	161:aa5281ff4a02	846	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	161:aa5281ff4a02	847	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	161:aa5281ff4a02	848
AnnaBridge	161:aa5281ff4a02	849	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
AnnaBridge	161:aa5281ff4a02	850	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
AnnaBridge	161:aa5281ff4a02	851	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
AnnaBridge	161:aa5281ff4a02	852	((__MODE__) == FSMC_ACCESS_MODE_D))
AnnaBridge	161:aa5281ff4a02	853
AnnaBridge	161:aa5281ff4a02	854	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
AnnaBridge	161:aa5281ff4a02	855	((BANK) == FSMC_NAND_BANK3))
AnnaBridge	161:aa5281ff4a02	856
AnnaBridge	161:aa5281ff4a02	857	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	858	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	161:aa5281ff4a02	859
AnnaBridge	161:aa5281ff4a02	860	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	161:aa5281ff4a02	861	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	161:aa5281ff4a02	862
AnnaBridge	161:aa5281ff4a02	863	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	864	((STATE) == FSMC_NAND_ECC_ENABLE))
AnnaBridge	161:aa5281ff4a02	865
AnnaBridge	161:aa5281ff4a02	866	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	867	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	868	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	869	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	870	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	871	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	161:aa5281ff4a02	872
AnnaBridge	161:aa5281ff4a02	873	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	874
AnnaBridge	161:aa5281ff4a02	875	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	876
AnnaBridge	161:aa5281ff4a02	877	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	878
AnnaBridge	161:aa5281ff4a02	879	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	880
AnnaBridge	161:aa5281ff4a02	881	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	882
AnnaBridge	161:aa5281ff4a02	883	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	884
AnnaBridge	161:aa5281ff4a02	885	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
AnnaBridge	161:aa5281ff4a02	886
AnnaBridge	161:aa5281ff4a02	887	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	161:aa5281ff4a02	888
AnnaBridge	161:aa5281ff4a02	889	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
AnnaBridge	161:aa5281ff4a02	890
AnnaBridge	161:aa5281ff4a02	891	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
AnnaBridge	161:aa5281ff4a02	892
AnnaBridge	161:aa5281ff4a02	893	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	894	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	895
AnnaBridge	161:aa5281ff4a02	896	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	161:aa5281ff4a02	897	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	161:aa5281ff4a02	898
AnnaBridge	161:aa5281ff4a02	899	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	900	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	901
AnnaBridge	161:aa5281ff4a02	902	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	161:aa5281ff4a02	903	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
AnnaBridge	161:aa5281ff4a02	904
AnnaBridge	161:aa5281ff4a02	905	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	906	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
AnnaBridge	161:aa5281ff4a02	907
AnnaBridge	161:aa5281ff4a02	908	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	909	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	161:aa5281ff4a02	910
AnnaBridge	161:aa5281ff4a02	911	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	912	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	913
AnnaBridge	161:aa5281ff4a02	914	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	915	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	161:aa5281ff4a02	916
AnnaBridge	161:aa5281ff4a02	917	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	161:aa5281ff4a02	918
AnnaBridge	161:aa5281ff4a02	919	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	920	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
AnnaBridge	161:aa5281ff4a02	921
AnnaBridge	161:aa5281ff4a02	922	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	161:aa5281ff4a02	923
AnnaBridge	161:aa5281ff4a02	924	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	161:aa5281ff4a02	925
AnnaBridge	161:aa5281ff4a02	926	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	161:aa5281ff4a02	927
AnnaBridge	161:aa5281ff4a02	928	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	161:aa5281ff4a02	929
AnnaBridge	161:aa5281ff4a02	930	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	161:aa5281ff4a02	931	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	161:aa5281ff4a02	932
AnnaBridge	161:aa5281ff4a02	933	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
AnnaBridge	161:aa5281ff4a02	934
AnnaBridge	161:aa5281ff4a02	935	#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	936	((SIZE) == FSMC_PAGE_SIZE_128) \|\| \
AnnaBridge	161:aa5281ff4a02	937	((SIZE) == FSMC_PAGE_SIZE_256) \|\| \
AnnaBridge	161:aa5281ff4a02	938	((SIZE) == FSMC_PAGE_SIZE_512) \|\| \
AnnaBridge	161:aa5281ff4a02	939	((SIZE) == FSMC_PAGE_SIZE_1024))
AnnaBridge	161:aa5281ff4a02	940
AnnaBridge	161:aa5281ff4a02	941	#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	942	((FIFO) == FSMC_WRITE_FIFO_ENABLE))
AnnaBridge	161:aa5281ff4a02	943
AnnaBridge	161:aa5281ff4a02	944	/**
AnnaBridge	161:aa5281ff4a02	945	* @}
AnnaBridge	161:aa5281ff4a02	946	*/
AnnaBridge	161:aa5281ff4a02	947	/**
AnnaBridge	161:aa5281ff4a02	948	* @}
AnnaBridge	161:aa5281ff4a02	949	*/
AnnaBridge	161:aa5281ff4a02	950
AnnaBridge	161:aa5281ff4a02	951	/* Private functions ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	952	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
AnnaBridge	161:aa5281ff4a02	953	* @{
AnnaBridge	161:aa5281ff4a02	954	*/
AnnaBridge	161:aa5281ff4a02	955
AnnaBridge	161:aa5281ff4a02	956	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
AnnaBridge	161:aa5281ff4a02	957	* @{
AnnaBridge	161:aa5281ff4a02	958	*/
AnnaBridge	161:aa5281ff4a02	959
AnnaBridge	161:aa5281ff4a02	960	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	961	* @{
AnnaBridge	161:aa5281ff4a02	962	*/
AnnaBridge	161:aa5281ff4a02	963	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	964	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	965	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	161:aa5281ff4a02	966	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	967	/**
AnnaBridge	161:aa5281ff4a02	968	* @}
AnnaBridge	161:aa5281ff4a02	969	*/
AnnaBridge	161:aa5281ff4a02	970
AnnaBridge	161:aa5281ff4a02	971	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	161:aa5281ff4a02	972	* @{
AnnaBridge	161:aa5281ff4a02	973	*/
AnnaBridge	161:aa5281ff4a02	974	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	975	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	976	/**
AnnaBridge	161:aa5281ff4a02	977	* @}
AnnaBridge	161:aa5281ff4a02	978	*/
AnnaBridge	161:aa5281ff4a02	979	/**
AnnaBridge	161:aa5281ff4a02	980	* @}
AnnaBridge	161:aa5281ff4a02	981	*/
AnnaBridge	161:aa5281ff4a02	982
AnnaBridge	161:aa5281ff4a02	983	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	161:aa5281ff4a02	984	/** @defgroup FSMC_LL_NAND NAND
AnnaBridge	161:aa5281ff4a02	985	* @{
AnnaBridge	161:aa5281ff4a02	986	*/
AnnaBridge	161:aa5281ff4a02	987	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	988	* @{
AnnaBridge	161:aa5281ff4a02	989	*/
AnnaBridge	161:aa5281ff4a02	990	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	991	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	992	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	993	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	994	/**
AnnaBridge	161:aa5281ff4a02	995	* @}
AnnaBridge	161:aa5281ff4a02	996	*/
AnnaBridge	161:aa5281ff4a02	997
AnnaBridge	161:aa5281ff4a02	998	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	161:aa5281ff4a02	999	* @{
AnnaBridge	161:aa5281ff4a02	1000	*/
AnnaBridge	161:aa5281ff4a02	1001	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1002	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1003	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	1004	/**
AnnaBridge	161:aa5281ff4a02	1005	* @}
AnnaBridge	161:aa5281ff4a02	1006	*/
AnnaBridge	161:aa5281ff4a02	1007	/**
AnnaBridge	161:aa5281ff4a02	1008	* @}
AnnaBridge	161:aa5281ff4a02	1009	*/
AnnaBridge	161:aa5281ff4a02	1010
AnnaBridge	161:aa5281ff4a02	1011	/** @defgroup FSMC_LL_PCCARD PCCARD
AnnaBridge	161:aa5281ff4a02	1012	* @{
AnnaBridge	161:aa5281ff4a02	1013	*/
AnnaBridge	161:aa5281ff4a02	1014	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	1015	* @{
AnnaBridge	161:aa5281ff4a02	1016	*/
AnnaBridge	161:aa5281ff4a02	1017	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	1018	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1019	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1020	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1021	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
AnnaBridge	161:aa5281ff4a02	1022	/**
AnnaBridge	161:aa5281ff4a02	1023	* @}
AnnaBridge	161:aa5281ff4a02	1024	*/
AnnaBridge	161:aa5281ff4a02	1025	/**
AnnaBridge	161:aa5281ff4a02	1026	* @}
AnnaBridge	161:aa5281ff4a02	1027	*/
AnnaBridge	161:aa5281ff4a02	1028	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	161:aa5281ff4a02	1029
AnnaBridge	161:aa5281ff4a02	1030	/**
AnnaBridge	161:aa5281ff4a02	1031	* @}
AnnaBridge	161:aa5281ff4a02	1032	*/
AnnaBridge	161:aa5281ff4a02	1033	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	161:aa5281ff4a02	1034
AnnaBridge	161:aa5281ff4a02	1035	/**
AnnaBridge	161:aa5281ff4a02	1036	* @}
AnnaBridge	161:aa5281ff4a02	1037	*/
AnnaBridge	161:aa5281ff4a02	1038
AnnaBridge	161:aa5281ff4a02	1039	/**
AnnaBridge	161:aa5281ff4a02	1040	* @}
AnnaBridge	161:aa5281ff4a02	1041	*/
AnnaBridge	161:aa5281ff4a02	1042
AnnaBridge	161:aa5281ff4a02	1043	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	1044	}
AnnaBridge	161:aa5281ff4a02	1045	#endif
AnnaBridge	161:aa5281ff4a02	1046
AnnaBridge	161:aa5281ff4a02	1047	#endif /* __STM32F4xx_LL_FSMC_H */
AnnaBridge	161:aa5281ff4a02	1048
AnnaBridge	161:aa5281ff4a02	1049	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/