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TARGET_NUCLEO_F413ZH/TOOLCHAIN_ARM_MICRO/stm32f413xx.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_F413ZH/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f413xx.h@163:e59c8e839560 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 146:22da6e220af6 1 /**
AnnaBridge 146:22da6e220af6 2 ******************************************************************************
AnnaBridge 146:22da6e220af6 3 * @file stm32f413xx.h
AnnaBridge 146:22da6e220af6 4 * @author MCD Application Team
AnnaBridge 146:22da6e220af6 5 * @brief CMSIS STM32F413xx Device Peripheral Access Layer Header File.
AnnaBridge 146:22da6e220af6 6 *
AnnaBridge 146:22da6e220af6 7 * This file contains:
AnnaBridge 146:22da6e220af6 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 146:22da6e220af6 9 * - peripherals registers declarations and bits definition
AnnaBridge 163:e59c8e839560 10 * - Macros to access peripheral's registers hardware
AnnaBridge 146:22da6e220af6 11 *
AnnaBridge 146:22da6e220af6 12 ******************************************************************************
AnnaBridge 146:22da6e220af6 13 * @attention
AnnaBridge 146:22da6e220af6 14 *
AnnaBridge 146:22da6e220af6 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 146:22da6e220af6 16 *
AnnaBridge 146:22da6e220af6 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 146:22da6e220af6 18 * are permitted provided that the following conditions are met:
AnnaBridge 146:22da6e220af6 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 146:22da6e220af6 20 * this list of conditions and the following disclaimer.
AnnaBridge 146:22da6e220af6 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 146:22da6e220af6 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 146:22da6e220af6 23 * and/or other materials provided with the distribution.
AnnaBridge 146:22da6e220af6 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 146:22da6e220af6 25 * may be used to endorse or promote products derived from this software
AnnaBridge 146:22da6e220af6 26 * without specific prior written permission.
AnnaBridge 146:22da6e220af6 27 *
AnnaBridge 146:22da6e220af6 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 146:22da6e220af6 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 146:22da6e220af6 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 146:22da6e220af6 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 146:22da6e220af6 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 146:22da6e220af6 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 146:22da6e220af6 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 146:22da6e220af6 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 146:22da6e220af6 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 146:22da6e220af6 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 146:22da6e220af6 38 *
AnnaBridge 146:22da6e220af6 39 ******************************************************************************
AnnaBridge 146:22da6e220af6 40 */
AnnaBridge 146:22da6e220af6 41
AnnaBridge 146:22da6e220af6 42 /** @addtogroup CMSIS_Device
AnnaBridge 146:22da6e220af6 43 * @{
AnnaBridge 146:22da6e220af6 44 */
AnnaBridge 146:22da6e220af6 45
AnnaBridge 146:22da6e220af6 46 /** @addtogroup stm32f413xx
AnnaBridge 146:22da6e220af6 47 * @{
AnnaBridge 146:22da6e220af6 48 */
AnnaBridge 146:22da6e220af6 49
AnnaBridge 146:22da6e220af6 50 #ifndef __STM32F413xx_H
AnnaBridge 146:22da6e220af6 51 #define __STM32F413xx_H
AnnaBridge 146:22da6e220af6 52
AnnaBridge 146:22da6e220af6 53 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 54 extern "C" {
AnnaBridge 146:22da6e220af6 55 #endif /* __cplusplus */
AnnaBridge 146:22da6e220af6 56
AnnaBridge 146:22da6e220af6 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 146:22da6e220af6 58 * @{
AnnaBridge 146:22da6e220af6 59 */
AnnaBridge 146:22da6e220af6 60
AnnaBridge 146:22da6e220af6 61 /**
AnnaBridge 146:22da6e220af6 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 146:22da6e220af6 63 */
AnnaBridge 146:22da6e220af6 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 146:22da6e220af6 65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
AnnaBridge 146:22da6e220af6 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
AnnaBridge 146:22da6e220af6 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 163:e59c8e839560 68 /* MBED */
AnnaBridge 146:22da6e220af6 69 #ifndef __FPU_PRESENT
AnnaBridge 146:22da6e220af6 70 #define __FPU_PRESENT 1U /*!< FPU present */
AnnaBridge 146:22da6e220af6 71 #endif
AnnaBridge 163:e59c8e839560 72 /* MBED */
AnnaBridge 146:22da6e220af6 73
AnnaBridge 146:22da6e220af6 74 /**
AnnaBridge 146:22da6e220af6 75 * @}
AnnaBridge 146:22da6e220af6 76 */
AnnaBridge 146:22da6e220af6 77
AnnaBridge 146:22da6e220af6 78 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 146:22da6e220af6 79 * @{
AnnaBridge 146:22da6e220af6 80 */
AnnaBridge 146:22da6e220af6 81
AnnaBridge 146:22da6e220af6 82 /**
AnnaBridge 146:22da6e220af6 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
AnnaBridge 146:22da6e220af6 84 * in @ref Library_configuration_section
AnnaBridge 146:22da6e220af6 85 */
AnnaBridge 146:22da6e220af6 86 typedef enum
AnnaBridge 146:22da6e220af6 87 {
AnnaBridge 146:22da6e220af6 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 146:22da6e220af6 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 146:22da6e220af6 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 146:22da6e220af6 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 146:22da6e220af6 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 146:22da6e220af6 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 146:22da6e220af6 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 146:22da6e220af6 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 146:22da6e220af6 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 146:22da6e220af6 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 146:22da6e220af6 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 146:22da6e220af6 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 146:22da6e220af6 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 146:22da6e220af6 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 146:22da6e220af6 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 146:22da6e220af6 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 146:22da6e220af6 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 146:22da6e220af6 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 146:22da6e220af6 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 146:22da6e220af6 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 146:22da6e220af6 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 146:22da6e220af6 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 146:22da6e220af6 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 146:22da6e220af6 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 146:22da6e220af6 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 146:22da6e220af6 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 146:22da6e220af6 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 146:22da6e220af6 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 146:22da6e220af6 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 146:22da6e220af6 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 146:22da6e220af6 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 146:22da6e220af6 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 146:22da6e220af6 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 146:22da6e220af6 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 146:22da6e220af6 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 146:22da6e220af6 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 146:22da6e220af6 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 146:22da6e220af6 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 146:22da6e220af6 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 146:22da6e220af6 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 146:22da6e220af6 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 146:22da6e220af6 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 146:22da6e220af6 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 146:22da6e220af6 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 146:22da6e220af6 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 146:22da6e220af6 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 146:22da6e220af6 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 146:22da6e220af6 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 146:22da6e220af6 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 146:22da6e220af6 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 146:22da6e220af6 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 146:22da6e220af6 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 146:22da6e220af6 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 146:22da6e220af6 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 146:22da6e220af6 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 146:22da6e220af6 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 146:22da6e220af6 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
AnnaBridge 146:22da6e220af6 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 146:22da6e220af6 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
AnnaBridge 146:22da6e220af6 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 146:22da6e220af6 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 146:22da6e220af6 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 146:22da6e220af6 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 146:22da6e220af6 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 146:22da6e220af6 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 146:22da6e220af6 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 146:22da6e220af6 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 146:22da6e220af6 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 146:22da6e220af6 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 146:22da6e220af6 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 146:22da6e220af6 158 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
AnnaBridge 146:22da6e220af6 159 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
AnnaBridge 146:22da6e220af6 160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
AnnaBridge 146:22da6e220af6 161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
AnnaBridge 146:22da6e220af6 162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
AnnaBridge 146:22da6e220af6 163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
AnnaBridge 146:22da6e220af6 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 146:22da6e220af6 165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 146:22da6e220af6 166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 146:22da6e220af6 167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 146:22da6e220af6 168 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 146:22da6e220af6 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 146:22da6e220af6 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 146:22da6e220af6 171 CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
AnnaBridge 146:22da6e220af6 172 CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
AnnaBridge 146:22da6e220af6 173 CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
AnnaBridge 146:22da6e220af6 174 CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
AnnaBridge 146:22da6e220af6 175 RNG_IRQn = 80, /*!< RNG global Interrupt */
AnnaBridge 146:22da6e220af6 176 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 146:22da6e220af6 177 UART7_IRQn = 82, /*!< UART7 global interrupt */
AnnaBridge 146:22da6e220af6 178 UART8_IRQn = 83, /*!< UART8 global interrupt */
AnnaBridge 146:22da6e220af6 179 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
AnnaBridge 146:22da6e220af6 180 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 146:22da6e220af6 181 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
AnnaBridge 146:22da6e220af6 182 UART9_IRQn = 88, /*!< UART9 global Interrupt */
AnnaBridge 146:22da6e220af6 183 UART10_IRQn = 89, /*!< UART10 global Interrupt */
AnnaBridge 146:22da6e220af6 184 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
AnnaBridge 146:22da6e220af6 185 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
AnnaBridge 146:22da6e220af6 186 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
AnnaBridge 146:22da6e220af6 187 LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
AnnaBridge 146:22da6e220af6 188 DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
AnnaBridge 146:22da6e220af6 189 DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
AnnaBridge 146:22da6e220af6 190 DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
AnnaBridge 146:22da6e220af6 191 DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
AnnaBridge 146:22da6e220af6 192 } IRQn_Type;
AnnaBridge 146:22da6e220af6 193
AnnaBridge 146:22da6e220af6 194 /**
AnnaBridge 146:22da6e220af6 195 * @}
AnnaBridge 146:22da6e220af6 196 */
AnnaBridge 146:22da6e220af6 197
AnnaBridge 146:22da6e220af6 198 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 146:22da6e220af6 199 #include "system_stm32f4xx.h"
AnnaBridge 146:22da6e220af6 200 #include <stdint.h>
AnnaBridge 146:22da6e220af6 201
AnnaBridge 146:22da6e220af6 202 /** @addtogroup Peripheral_registers_structures
AnnaBridge 146:22da6e220af6 203 * @{
AnnaBridge 146:22da6e220af6 204 */
AnnaBridge 146:22da6e220af6 205
AnnaBridge 146:22da6e220af6 206 /**
AnnaBridge 146:22da6e220af6 207 * @brief Analog to Digital Converter
AnnaBridge 146:22da6e220af6 208 */
AnnaBridge 146:22da6e220af6 209
AnnaBridge 146:22da6e220af6 210 typedef struct
AnnaBridge 146:22da6e220af6 211 {
AnnaBridge 146:22da6e220af6 212 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 213 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 214 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 215 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 216 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 217 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 218 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 219 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 220 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 221 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 222 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 223 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 224 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 225 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 226 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 146:22da6e220af6 227 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 146:22da6e220af6 228 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 146:22da6e220af6 229 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 146:22da6e220af6 230 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 146:22da6e220af6 231 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 146:22da6e220af6 232 } ADC_TypeDef;
AnnaBridge 146:22da6e220af6 233
AnnaBridge 146:22da6e220af6 234 typedef struct
AnnaBridge 146:22da6e220af6 235 {
AnnaBridge 146:22da6e220af6 236 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 146:22da6e220af6 237 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 146:22da6e220af6 238 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 146:22da6e220af6 239 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 146:22da6e220af6 240 } ADC_Common_TypeDef;
AnnaBridge 146:22da6e220af6 241
AnnaBridge 146:22da6e220af6 242
AnnaBridge 146:22da6e220af6 243 /**
AnnaBridge 146:22da6e220af6 244 * @brief Controller Area Network TxMailBox
AnnaBridge 146:22da6e220af6 245 */
AnnaBridge 146:22da6e220af6 246
AnnaBridge 146:22da6e220af6 247 typedef struct
AnnaBridge 146:22da6e220af6 248 {
AnnaBridge 146:22da6e220af6 249 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 146:22da6e220af6 250 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 146:22da6e220af6 251 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 146:22da6e220af6 252 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 146:22da6e220af6 253 } CAN_TxMailBox_TypeDef;
AnnaBridge 146:22da6e220af6 254
AnnaBridge 146:22da6e220af6 255 /**
AnnaBridge 146:22da6e220af6 256 * @brief Controller Area Network FIFOMailBox
AnnaBridge 146:22da6e220af6 257 */
AnnaBridge 146:22da6e220af6 258
AnnaBridge 146:22da6e220af6 259 typedef struct
AnnaBridge 146:22da6e220af6 260 {
AnnaBridge 146:22da6e220af6 261 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 146:22da6e220af6 262 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 146:22da6e220af6 263 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 146:22da6e220af6 264 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 146:22da6e220af6 265 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 146:22da6e220af6 266
AnnaBridge 146:22da6e220af6 267 /**
AnnaBridge 146:22da6e220af6 268 * @brief Controller Area Network FilterRegister
AnnaBridge 146:22da6e220af6 269 */
AnnaBridge 146:22da6e220af6 270
AnnaBridge 146:22da6e220af6 271 typedef struct
AnnaBridge 146:22da6e220af6 272 {
AnnaBridge 146:22da6e220af6 273 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 146:22da6e220af6 274 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 146:22da6e220af6 275 } CAN_FilterRegister_TypeDef;
AnnaBridge 146:22da6e220af6 276
AnnaBridge 146:22da6e220af6 277 /**
AnnaBridge 146:22da6e220af6 278 * @brief Controller Area Network
AnnaBridge 146:22da6e220af6 279 */
AnnaBridge 146:22da6e220af6 280
AnnaBridge 146:22da6e220af6 281 typedef struct
AnnaBridge 146:22da6e220af6 282 {
AnnaBridge 146:22da6e220af6 283 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 284 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 285 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 286 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 287 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 288 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 289 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 290 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 291 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 146:22da6e220af6 292 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 146:22da6e220af6 293 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 146:22da6e220af6 294 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 146:22da6e220af6 295 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 146:22da6e220af6 296 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 146:22da6e220af6 297 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 146:22da6e220af6 298 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 146:22da6e220af6 299 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 146:22da6e220af6 300 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 146:22da6e220af6 301 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 146:22da6e220af6 302 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 146:22da6e220af6 303 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 146:22da6e220af6 304 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 146:22da6e220af6 305 } CAN_TypeDef;
AnnaBridge 146:22da6e220af6 306
AnnaBridge 146:22da6e220af6 307 /**
AnnaBridge 146:22da6e220af6 308 * @brief CRC calculation unit
AnnaBridge 146:22da6e220af6 309 */
AnnaBridge 146:22da6e220af6 310
AnnaBridge 146:22da6e220af6 311 typedef struct
AnnaBridge 146:22da6e220af6 312 {
AnnaBridge 146:22da6e220af6 313 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 314 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 315 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 146:22da6e220af6 316 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 146:22da6e220af6 317 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 318 } CRC_TypeDef;
AnnaBridge 146:22da6e220af6 319
AnnaBridge 146:22da6e220af6 320 /**
AnnaBridge 146:22da6e220af6 321 * @brief DFSDM module registers
AnnaBridge 146:22da6e220af6 322 */
AnnaBridge 146:22da6e220af6 323 typedef struct
AnnaBridge 146:22da6e220af6 324 {
AnnaBridge 146:22da6e220af6 325 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
AnnaBridge 146:22da6e220af6 326 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
AnnaBridge 146:22da6e220af6 327 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
AnnaBridge 146:22da6e220af6 328 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
AnnaBridge 146:22da6e220af6 329 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
AnnaBridge 146:22da6e220af6 330 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
AnnaBridge 146:22da6e220af6 331 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
AnnaBridge 146:22da6e220af6 332 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
AnnaBridge 146:22da6e220af6 333 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
AnnaBridge 146:22da6e220af6 334 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
AnnaBridge 146:22da6e220af6 335 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
AnnaBridge 146:22da6e220af6 336 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
AnnaBridge 146:22da6e220af6 337 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
AnnaBridge 146:22da6e220af6 338 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
AnnaBridge 146:22da6e220af6 339 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
AnnaBridge 146:22da6e220af6 340 } DFSDM_Filter_TypeDef;
AnnaBridge 146:22da6e220af6 341
AnnaBridge 146:22da6e220af6 342 /**
AnnaBridge 146:22da6e220af6 343 * @brief DFSDM channel configuration registers
AnnaBridge 146:22da6e220af6 344 */
AnnaBridge 146:22da6e220af6 345 typedef struct
AnnaBridge 146:22da6e220af6 346 {
AnnaBridge 146:22da6e220af6 347 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 348 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 349 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
AnnaBridge 146:22da6e220af6 350 short circuit detector register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 351 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 352 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 353 } DFSDM_Channel_TypeDef;
AnnaBridge 146:22da6e220af6 354
AnnaBridge 146:22da6e220af6 355 /**
AnnaBridge 146:22da6e220af6 356 * @brief Digital to Analog Converter
AnnaBridge 146:22da6e220af6 357 */
AnnaBridge 146:22da6e220af6 358
AnnaBridge 146:22da6e220af6 359 typedef struct
AnnaBridge 146:22da6e220af6 360 {
AnnaBridge 146:22da6e220af6 361 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 362 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 363 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 364 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 365 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 366 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 367 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 368 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 369 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 370 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 371 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 372 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 373 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 374 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 375 } DAC_TypeDef;
AnnaBridge 146:22da6e220af6 376
AnnaBridge 146:22da6e220af6 377 /**
AnnaBridge 146:22da6e220af6 378 * @brief Debug MCU
AnnaBridge 146:22da6e220af6 379 */
AnnaBridge 146:22da6e220af6 380
AnnaBridge 146:22da6e220af6 381 typedef struct
AnnaBridge 146:22da6e220af6 382 {
AnnaBridge 146:22da6e220af6 383 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 384 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 385 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 386 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 387 }DBGMCU_TypeDef;
AnnaBridge 146:22da6e220af6 388
AnnaBridge 146:22da6e220af6 389
AnnaBridge 146:22da6e220af6 390 /**
AnnaBridge 146:22da6e220af6 391 * @brief DMA Controller
AnnaBridge 146:22da6e220af6 392 */
AnnaBridge 146:22da6e220af6 393
AnnaBridge 146:22da6e220af6 394 typedef struct
AnnaBridge 146:22da6e220af6 395 {
AnnaBridge 146:22da6e220af6 396 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 146:22da6e220af6 397 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 146:22da6e220af6 398 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 146:22da6e220af6 399 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 146:22da6e220af6 400 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 146:22da6e220af6 401 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 146:22da6e220af6 402 } DMA_Stream_TypeDef;
AnnaBridge 146:22da6e220af6 403
AnnaBridge 146:22da6e220af6 404 typedef struct
AnnaBridge 146:22da6e220af6 405 {
AnnaBridge 146:22da6e220af6 406 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 407 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 408 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 409 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 410 } DMA_TypeDef;
AnnaBridge 146:22da6e220af6 411
AnnaBridge 146:22da6e220af6 412 /**
AnnaBridge 146:22da6e220af6 413 * @brief External Interrupt/Event Controller
AnnaBridge 146:22da6e220af6 414 */
AnnaBridge 146:22da6e220af6 415
AnnaBridge 146:22da6e220af6 416 typedef struct
AnnaBridge 146:22da6e220af6 417 {
AnnaBridge 146:22da6e220af6 418 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 419 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 420 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 421 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 422 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 423 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 424 } EXTI_TypeDef;
AnnaBridge 146:22da6e220af6 425
AnnaBridge 146:22da6e220af6 426 /**
AnnaBridge 146:22da6e220af6 427 * @brief FLASH Registers
AnnaBridge 146:22da6e220af6 428 */
AnnaBridge 146:22da6e220af6 429
AnnaBridge 146:22da6e220af6 430 typedef struct
AnnaBridge 146:22da6e220af6 431 {
AnnaBridge 146:22da6e220af6 432 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 433 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 434 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 435 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 436 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 437 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 438 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 439 } FLASH_TypeDef;
AnnaBridge 146:22da6e220af6 440
AnnaBridge 146:22da6e220af6 441
AnnaBridge 146:22da6e220af6 442
AnnaBridge 146:22da6e220af6 443 /**
AnnaBridge 146:22da6e220af6 444 * @brief Flexible Static Memory Controller
AnnaBridge 146:22da6e220af6 445 */
AnnaBridge 146:22da6e220af6 446
AnnaBridge 146:22da6e220af6 447 typedef struct
AnnaBridge 146:22da6e220af6 448 {
AnnaBridge 146:22da6e220af6 449 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 146:22da6e220af6 450 } FSMC_Bank1_TypeDef;
AnnaBridge 146:22da6e220af6 451
AnnaBridge 146:22da6e220af6 452 /**
AnnaBridge 146:22da6e220af6 453 * @brief Flexible Static Memory Controller Bank1E
AnnaBridge 146:22da6e220af6 454 */
AnnaBridge 146:22da6e220af6 455
AnnaBridge 146:22da6e220af6 456 typedef struct
AnnaBridge 146:22da6e220af6 457 {
AnnaBridge 146:22da6e220af6 458 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 146:22da6e220af6 459 } FSMC_Bank1E_TypeDef;
AnnaBridge 146:22da6e220af6 460 /**
AnnaBridge 146:22da6e220af6 461 * @brief General Purpose I/O
AnnaBridge 146:22da6e220af6 462 */
AnnaBridge 146:22da6e220af6 463
AnnaBridge 146:22da6e220af6 464 typedef struct
AnnaBridge 146:22da6e220af6 465 {
AnnaBridge 146:22da6e220af6 466 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 467 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 468 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 469 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 470 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 471 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 472 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 473 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 474 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 146:22da6e220af6 475 } GPIO_TypeDef;
AnnaBridge 146:22da6e220af6 476
AnnaBridge 146:22da6e220af6 477 /**
AnnaBridge 146:22da6e220af6 478 * @brief System configuration controller
AnnaBridge 146:22da6e220af6 479 */
AnnaBridge 146:22da6e220af6 480
AnnaBridge 146:22da6e220af6 481 typedef struct
AnnaBridge 146:22da6e220af6 482 {
AnnaBridge 146:22da6e220af6 483 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 484 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 485 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 146:22da6e220af6 486 uint32_t RESERVED; /*!< Reserved, 0x18 */
AnnaBridge 146:22da6e220af6 487 __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 488 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 489 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
AnnaBridge 146:22da6e220af6 490 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 491 __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 492 } SYSCFG_TypeDef;
AnnaBridge 146:22da6e220af6 493
AnnaBridge 146:22da6e220af6 494 /**
AnnaBridge 146:22da6e220af6 495 * @brief Inter-integrated Circuit Interface
AnnaBridge 146:22da6e220af6 496 */
AnnaBridge 146:22da6e220af6 497
AnnaBridge 146:22da6e220af6 498 typedef struct
AnnaBridge 146:22da6e220af6 499 {
AnnaBridge 146:22da6e220af6 500 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 501 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 502 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 503 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 504 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 505 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 506 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 507 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 508 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 509 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 510 } I2C_TypeDef;
AnnaBridge 146:22da6e220af6 511
AnnaBridge 146:22da6e220af6 512 /**
AnnaBridge 146:22da6e220af6 513 * @brief Inter-integrated Circuit Interface
AnnaBridge 146:22da6e220af6 514 */
AnnaBridge 146:22da6e220af6 515
AnnaBridge 146:22da6e220af6 516 typedef struct
AnnaBridge 146:22da6e220af6 517 {
AnnaBridge 146:22da6e220af6 518 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 519 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 520 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 521 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 522 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 523 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 524 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 525 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 526 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 527 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 528 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 529 } FMPI2C_TypeDef;
AnnaBridge 146:22da6e220af6 530
AnnaBridge 146:22da6e220af6 531 /**
AnnaBridge 146:22da6e220af6 532 * @brief Independent WATCHDOG
AnnaBridge 146:22da6e220af6 533 */
AnnaBridge 146:22da6e220af6 534
AnnaBridge 146:22da6e220af6 535 typedef struct
AnnaBridge 146:22da6e220af6 536 {
AnnaBridge 146:22da6e220af6 537 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 538 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 539 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 540 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 541 } IWDG_TypeDef;
AnnaBridge 146:22da6e220af6 542
AnnaBridge 146:22da6e220af6 543
AnnaBridge 146:22da6e220af6 544 /**
AnnaBridge 146:22da6e220af6 545 * @brief Power Control
AnnaBridge 146:22da6e220af6 546 */
AnnaBridge 146:22da6e220af6 547
AnnaBridge 146:22da6e220af6 548 typedef struct
AnnaBridge 146:22da6e220af6 549 {
AnnaBridge 146:22da6e220af6 550 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 551 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 552 } PWR_TypeDef;
AnnaBridge 146:22da6e220af6 553
AnnaBridge 146:22da6e220af6 554 /**
AnnaBridge 146:22da6e220af6 555 * @brief Reset and Clock Control
AnnaBridge 146:22da6e220af6 556 */
AnnaBridge 146:22da6e220af6 557
AnnaBridge 146:22da6e220af6 558 typedef struct
AnnaBridge 146:22da6e220af6 559 {
AnnaBridge 146:22da6e220af6 560 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 561 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 562 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 563 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 564 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 565 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 566 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 567 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 146:22da6e220af6 568 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 569 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 570 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 146:22da6e220af6 571 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 572 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 573 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 146:22da6e220af6 574 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 146:22da6e220af6 575 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 146:22da6e220af6 576 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 146:22da6e220af6 577 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 146:22da6e220af6 578 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 146:22da6e220af6 579 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 146:22da6e220af6 580 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 146:22da6e220af6 581 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 146:22da6e220af6 582 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 146:22da6e220af6 583 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 146:22da6e220af6 584 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 146:22da6e220af6 585 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 146:22da6e220af6 586 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 146:22da6e220af6 587 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 146:22da6e220af6 588 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 146:22da6e220af6 589 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 146:22da6e220af6 590 uint32_t RESERVED7; /*!< Reserved, 0x84 */
AnnaBridge 146:22da6e220af6 591 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
AnnaBridge 146:22da6e220af6 592 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
AnnaBridge 146:22da6e220af6 593 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
AnnaBridge 146:22da6e220af6 594 } RCC_TypeDef;
AnnaBridge 146:22da6e220af6 595
AnnaBridge 146:22da6e220af6 596 /**
AnnaBridge 146:22da6e220af6 597 * @brief Real-Time Clock
AnnaBridge 146:22da6e220af6 598 */
AnnaBridge 146:22da6e220af6 599
AnnaBridge 146:22da6e220af6 600 typedef struct
AnnaBridge 146:22da6e220af6 601 {
AnnaBridge 146:22da6e220af6 602 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 603 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 604 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 605 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 606 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 607 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 608 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 609 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 610 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 611 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 612 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 613 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 614 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 615 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 616 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 146:22da6e220af6 617 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 146:22da6e220af6 618 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 146:22da6e220af6 619 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 146:22da6e220af6 620 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 146:22da6e220af6 621 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 146:22da6e220af6 622 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
AnnaBridge 146:22da6e220af6 623 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 146:22da6e220af6 624 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 146:22da6e220af6 625 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 146:22da6e220af6 626 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 146:22da6e220af6 627 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 146:22da6e220af6 628 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 146:22da6e220af6 629 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 146:22da6e220af6 630 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 146:22da6e220af6 631 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 146:22da6e220af6 632 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 146:22da6e220af6 633 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 146:22da6e220af6 634 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 146:22da6e220af6 635 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 146:22da6e220af6 636 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 146:22da6e220af6 637 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 146:22da6e220af6 638 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 146:22da6e220af6 639 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 146:22da6e220af6 640 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 146:22da6e220af6 641 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 146:22da6e220af6 642 } RTC_TypeDef;
AnnaBridge 146:22da6e220af6 643
AnnaBridge 146:22da6e220af6 644 /**
AnnaBridge 146:22da6e220af6 645 * @brief Serial Audio Interface
AnnaBridge 146:22da6e220af6 646 */
AnnaBridge 146:22da6e220af6 647
AnnaBridge 146:22da6e220af6 648 typedef struct
AnnaBridge 146:22da6e220af6 649 {
AnnaBridge 146:22da6e220af6 650 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 651 } SAI_TypeDef;
AnnaBridge 146:22da6e220af6 652
AnnaBridge 146:22da6e220af6 653 typedef struct
AnnaBridge 146:22da6e220af6 654 {
AnnaBridge 146:22da6e220af6 655 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 656 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 657 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 658 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 659 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 660 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 661 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 662 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 663 } SAI_Block_TypeDef;
AnnaBridge 146:22da6e220af6 664
AnnaBridge 146:22da6e220af6 665 /**
AnnaBridge 146:22da6e220af6 666 * @brief SD host Interface
AnnaBridge 146:22da6e220af6 667 */
AnnaBridge 146:22da6e220af6 668
AnnaBridge 146:22da6e220af6 669 typedef struct
AnnaBridge 146:22da6e220af6 670 {
AnnaBridge 146:22da6e220af6 671 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 672 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 673 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 674 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 675 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 676 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 677 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 678 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 679 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 680 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 681 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 682 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 683 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 684 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 685 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 146:22da6e220af6 686 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 146:22da6e220af6 687 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 146:22da6e220af6 688 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 146:22da6e220af6 689 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 146:22da6e220af6 690 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
AnnaBridge 146:22da6e220af6 691 } SDIO_TypeDef;
AnnaBridge 146:22da6e220af6 692
AnnaBridge 146:22da6e220af6 693 /**
AnnaBridge 146:22da6e220af6 694 * @brief Serial Peripheral Interface
AnnaBridge 146:22da6e220af6 695 */
AnnaBridge 146:22da6e220af6 696
AnnaBridge 146:22da6e220af6 697 typedef struct
AnnaBridge 146:22da6e220af6 698 {
AnnaBridge 146:22da6e220af6 699 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 700 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 701 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 702 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 703 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 704 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 705 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 706 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 707 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 708 } SPI_TypeDef;
AnnaBridge 146:22da6e220af6 709
AnnaBridge 146:22da6e220af6 710 /**
AnnaBridge 146:22da6e220af6 711 * @brief QUAD Serial Peripheral Interface
AnnaBridge 146:22da6e220af6 712 */
AnnaBridge 146:22da6e220af6 713
AnnaBridge 146:22da6e220af6 714 typedef struct
AnnaBridge 146:22da6e220af6 715 {
AnnaBridge 146:22da6e220af6 716 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 717 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 718 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 719 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 720 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 721 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 722 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 723 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 724 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 725 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 726 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 727 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 728 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 729 } QUADSPI_TypeDef;
AnnaBridge 146:22da6e220af6 730
AnnaBridge 146:22da6e220af6 731 /**
AnnaBridge 146:22da6e220af6 732 * @brief TIM
AnnaBridge 146:22da6e220af6 733 */
AnnaBridge 146:22da6e220af6 734
AnnaBridge 146:22da6e220af6 735 typedef struct
AnnaBridge 146:22da6e220af6 736 {
AnnaBridge 146:22da6e220af6 737 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 738 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 739 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 740 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 741 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 742 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 743 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 744 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 745 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 746 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 146:22da6e220af6 747 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 146:22da6e220af6 748 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 146:22da6e220af6 749 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 146:22da6e220af6 750 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 146:22da6e220af6 751 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 146:22da6e220af6 752 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 146:22da6e220af6 753 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 146:22da6e220af6 754 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 146:22da6e220af6 755 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 146:22da6e220af6 756 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 146:22da6e220af6 757 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 146:22da6e220af6 758 } TIM_TypeDef;
AnnaBridge 146:22da6e220af6 759
AnnaBridge 146:22da6e220af6 760 /**
AnnaBridge 146:22da6e220af6 761 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 146:22da6e220af6 762 */
AnnaBridge 146:22da6e220af6 763
AnnaBridge 146:22da6e220af6 764 typedef struct
AnnaBridge 146:22da6e220af6 765 {
AnnaBridge 146:22da6e220af6 766 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 767 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 768 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 769 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 770 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 771 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 772 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 773 } USART_TypeDef;
AnnaBridge 146:22da6e220af6 774
AnnaBridge 146:22da6e220af6 775 /**
AnnaBridge 146:22da6e220af6 776 * @brief Window WATCHDOG
AnnaBridge 146:22da6e220af6 777 */
AnnaBridge 146:22da6e220af6 778
AnnaBridge 146:22da6e220af6 779 typedef struct
AnnaBridge 146:22da6e220af6 780 {
AnnaBridge 146:22da6e220af6 781 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 782 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 783 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 784 } WWDG_TypeDef;
AnnaBridge 146:22da6e220af6 785
AnnaBridge 146:22da6e220af6 786 /**
AnnaBridge 146:22da6e220af6 787 * @brief RNG
AnnaBridge 146:22da6e220af6 788 */
AnnaBridge 146:22da6e220af6 789
AnnaBridge 146:22da6e220af6 790 typedef struct
AnnaBridge 146:22da6e220af6 791 {
AnnaBridge 146:22da6e220af6 792 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 793 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 794 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 795 } RNG_TypeDef;
AnnaBridge 146:22da6e220af6 796
AnnaBridge 146:22da6e220af6 797 /**
AnnaBridge 146:22da6e220af6 798 * @brief USB_OTG_Core_Registers
AnnaBridge 146:22da6e220af6 799 */
AnnaBridge 146:22da6e220af6 800 typedef struct
AnnaBridge 146:22da6e220af6 801 {
AnnaBridge 146:22da6e220af6 802 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 146:22da6e220af6 803 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 146:22da6e220af6 804 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 146:22da6e220af6 805 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 146:22da6e220af6 806 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 146:22da6e220af6 807 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 146:22da6e220af6 808 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 146:22da6e220af6 809 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 146:22da6e220af6 810 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 146:22da6e220af6 811 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 146:22da6e220af6 812 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 146:22da6e220af6 813 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 146:22da6e220af6 814 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 146:22da6e220af6 815 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 146:22da6e220af6 816 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 146:22da6e220af6 817 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
AnnaBridge 146:22da6e220af6 818 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
AnnaBridge 146:22da6e220af6 819 uint32_t Reserved6; /*!< Reserved 050h */
AnnaBridge 146:22da6e220af6 820 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
AnnaBridge 146:22da6e220af6 821 uint32_t Reserved; /*!< Reserved 058h */
AnnaBridge 146:22da6e220af6 822 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
AnnaBridge 146:22da6e220af6 823 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
AnnaBridge 146:22da6e220af6 824 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 146:22da6e220af6 825 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 146:22da6e220af6 826 } USB_OTG_GlobalTypeDef;
AnnaBridge 146:22da6e220af6 827
AnnaBridge 146:22da6e220af6 828 /**
AnnaBridge 146:22da6e220af6 829 * @brief USB_OTG_device_Registers
AnnaBridge 146:22da6e220af6 830 */
AnnaBridge 146:22da6e220af6 831 typedef struct
AnnaBridge 146:22da6e220af6 832 {
AnnaBridge 146:22da6e220af6 833 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 146:22da6e220af6 834 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 146:22da6e220af6 835 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 146:22da6e220af6 836 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 146:22da6e220af6 837 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 146:22da6e220af6 838 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 146:22da6e220af6 839 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 146:22da6e220af6 840 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 146:22da6e220af6 841 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 146:22da6e220af6 842 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 146:22da6e220af6 843 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 146:22da6e220af6 844 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 146:22da6e220af6 845 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 146:22da6e220af6 846 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 146:22da6e220af6 847 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 146:22da6e220af6 848 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 146:22da6e220af6 849 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 146:22da6e220af6 850 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 146:22da6e220af6 851 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 146:22da6e220af6 852 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 146:22da6e220af6 853 } USB_OTG_DeviceTypeDef;
AnnaBridge 146:22da6e220af6 854
AnnaBridge 146:22da6e220af6 855 /**
AnnaBridge 146:22da6e220af6 856 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 146:22da6e220af6 857 */
AnnaBridge 146:22da6e220af6 858 typedef struct
AnnaBridge 146:22da6e220af6 859 {
AnnaBridge 146:22da6e220af6 860 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 146:22da6e220af6 861 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 146:22da6e220af6 862 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 146:22da6e220af6 863 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 146:22da6e220af6 864 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 146:22da6e220af6 865 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 146:22da6e220af6 866 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 146:22da6e220af6 867 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 146:22da6e220af6 868 } USB_OTG_INEndpointTypeDef;
AnnaBridge 146:22da6e220af6 869
AnnaBridge 146:22da6e220af6 870 /**
AnnaBridge 146:22da6e220af6 871 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 146:22da6e220af6 872 */
AnnaBridge 146:22da6e220af6 873 typedef struct
AnnaBridge 146:22da6e220af6 874 {
AnnaBridge 146:22da6e220af6 875 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 146:22da6e220af6 876 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 146:22da6e220af6 877 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 146:22da6e220af6 878 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 146:22da6e220af6 879 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 146:22da6e220af6 880 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 146:22da6e220af6 881 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 146:22da6e220af6 882 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 146:22da6e220af6 883
AnnaBridge 146:22da6e220af6 884 /**
AnnaBridge 146:22da6e220af6 885 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 146:22da6e220af6 886 */
AnnaBridge 146:22da6e220af6 887 typedef struct
AnnaBridge 146:22da6e220af6 888 {
AnnaBridge 146:22da6e220af6 889 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 146:22da6e220af6 890 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 146:22da6e220af6 891 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 146:22da6e220af6 892 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 146:22da6e220af6 893 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 146:22da6e220af6 894 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 146:22da6e220af6 895 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 146:22da6e220af6 896 } USB_OTG_HostTypeDef;
AnnaBridge 146:22da6e220af6 897
AnnaBridge 146:22da6e220af6 898 /**
AnnaBridge 146:22da6e220af6 899 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 146:22da6e220af6 900 */
AnnaBridge 146:22da6e220af6 901 typedef struct
AnnaBridge 146:22da6e220af6 902 {
AnnaBridge 146:22da6e220af6 903 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 146:22da6e220af6 904 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 146:22da6e220af6 905 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 146:22da6e220af6 906 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 146:22da6e220af6 907 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 146:22da6e220af6 908 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 146:22da6e220af6 909 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 146:22da6e220af6 910 } USB_OTG_HostChannelTypeDef;
AnnaBridge 146:22da6e220af6 911
AnnaBridge 146:22da6e220af6 912 /**
AnnaBridge 146:22da6e220af6 913 * @brief LPTIMER
AnnaBridge 146:22da6e220af6 914 */
AnnaBridge 146:22da6e220af6 915 typedef struct
AnnaBridge 146:22da6e220af6 916 {
AnnaBridge 146:22da6e220af6 917 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 146:22da6e220af6 918 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 146:22da6e220af6 919 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 146:22da6e220af6 920 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 146:22da6e220af6 921 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 146:22da6e220af6 922 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 146:22da6e220af6 923 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 146:22da6e220af6 924 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 146:22da6e220af6 925 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
AnnaBridge 146:22da6e220af6 926 } LPTIM_TypeDef;
AnnaBridge 146:22da6e220af6 927
AnnaBridge 146:22da6e220af6 928 /**
AnnaBridge 146:22da6e220af6 929 * @}
AnnaBridge 146:22da6e220af6 930 */
AnnaBridge 146:22da6e220af6 931
AnnaBridge 146:22da6e220af6 932 /** @addtogroup Peripheral_memory_map
AnnaBridge 146:22da6e220af6 933 * @{
AnnaBridge 146:22da6e220af6 934 */
AnnaBridge 146:22da6e220af6 935 #define FLASH_BASE 0x08000000U /*!< FLASH (up to 1.5 MB) base address in the alias region */
AnnaBridge 146:22da6e220af6 936 #define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
AnnaBridge 146:22da6e220af6 937 #define SRAM2_BASE 0x20040000U /*!< SRAM2(64 KB) base address in the alias region */
AnnaBridge 146:22da6e220af6 938 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
AnnaBridge 146:22da6e220af6 939 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
AnnaBridge 146:22da6e220af6 940 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
AnnaBridge 146:22da6e220af6 941 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
AnnaBridge 146:22da6e220af6 942 #define SRAM2_BB_BASE 0x22800000U /*!< SRAM2(64 KB) base address in the bit-band region */
AnnaBridge 146:22da6e220af6 943 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 146:22da6e220af6 944 #define FLASH_END 0x0817FFFFU /*!< FLASH end address */
AnnaBridge 146:22da6e220af6 945 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 146:22da6e220af6 946 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 146:22da6e220af6 947
AnnaBridge 146:22da6e220af6 948 /* Legacy defines */
AnnaBridge 146:22da6e220af6 949 #define SRAM_BASE SRAM1_BASE
AnnaBridge 146:22da6e220af6 950 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 146:22da6e220af6 951
AnnaBridge 146:22da6e220af6 952 /*!< Peripheral memory map */
AnnaBridge 146:22da6e220af6 953 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 146:22da6e220af6 954 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 146:22da6e220af6 955 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 146:22da6e220af6 956 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 146:22da6e220af6 957
AnnaBridge 146:22da6e220af6 958 /*!< APB1 peripherals */
AnnaBridge 146:22da6e220af6 959 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 146:22da6e220af6 960 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 146:22da6e220af6 961 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 146:22da6e220af6 962 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 146:22da6e220af6 963 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 146:22da6e220af6 964 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 146:22da6e220af6 965 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
AnnaBridge 146:22da6e220af6 966 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
AnnaBridge 146:22da6e220af6 967 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
AnnaBridge 146:22da6e220af6 968 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
AnnaBridge 146:22da6e220af6 969 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 146:22da6e220af6 970 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 146:22da6e220af6 971 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 146:22da6e220af6 972 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 146:22da6e220af6 973 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 146:22da6e220af6 974 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 146:22da6e220af6 975 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 146:22da6e220af6 976 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 146:22da6e220af6 977 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
AnnaBridge 146:22da6e220af6 978 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
AnnaBridge 146:22da6e220af6 979 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
AnnaBridge 146:22da6e220af6 980 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 146:22da6e220af6 981 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 146:22da6e220af6 982 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 146:22da6e220af6 983 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
AnnaBridge 146:22da6e220af6 984 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 146:22da6e220af6 985 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
AnnaBridge 146:22da6e220af6 986 #define CAN3_BASE (APB1PERIPH_BASE + 0x6C00U)
AnnaBridge 146:22da6e220af6 987 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 146:22da6e220af6 988 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 146:22da6e220af6 989 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 146:22da6e220af6 990 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
AnnaBridge 146:22da6e220af6 991
AnnaBridge 146:22da6e220af6 992 /*!< APB2 peripherals */
AnnaBridge 146:22da6e220af6 993 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 146:22da6e220af6 994 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 146:22da6e220af6 995 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 146:22da6e220af6 996 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 146:22da6e220af6 997 #define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
AnnaBridge 146:22da6e220af6 998 #define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
AnnaBridge 146:22da6e220af6 999 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 146:22da6e220af6 1000 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 146:22da6e220af6 1001 /* Legacy define */
AnnaBridge 146:22da6e220af6 1002 #define ADC_BASE ADC1_COMMON_BASE
AnnaBridge 146:22da6e220af6 1003 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 146:22da6e220af6 1004 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 146:22da6e220af6 1005 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
AnnaBridge 146:22da6e220af6 1006 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 146:22da6e220af6 1007 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 146:22da6e220af6 1008 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 146:22da6e220af6 1009 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 146:22da6e220af6 1010 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 146:22da6e220af6 1011 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
AnnaBridge 146:22da6e220af6 1012 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
AnnaBridge 146:22da6e220af6 1013 #define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
AnnaBridge 146:22da6e220af6 1014 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
AnnaBridge 146:22da6e220af6 1015 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
AnnaBridge 146:22da6e220af6 1016 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
AnnaBridge 146:22da6e220af6 1017 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
AnnaBridge 146:22da6e220af6 1018 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
AnnaBridge 146:22da6e220af6 1019 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
AnnaBridge 146:22da6e220af6 1020 #define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
AnnaBridge 146:22da6e220af6 1021 #define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
AnnaBridge 146:22da6e220af6 1022 #define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
AnnaBridge 146:22da6e220af6 1023 #define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
AnnaBridge 146:22da6e220af6 1024 #define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
AnnaBridge 146:22da6e220af6 1025 #define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
AnnaBridge 146:22da6e220af6 1026 #define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
AnnaBridge 146:22da6e220af6 1027 #define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
AnnaBridge 146:22da6e220af6 1028 #define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
AnnaBridge 146:22da6e220af6 1029 #define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
AnnaBridge 146:22da6e220af6 1030 #define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
AnnaBridge 146:22da6e220af6 1031 #define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
AnnaBridge 146:22da6e220af6 1032 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
AnnaBridge 146:22da6e220af6 1033 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
AnnaBridge 146:22da6e220af6 1034 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
AnnaBridge 146:22da6e220af6 1035
AnnaBridge 146:22da6e220af6 1036 /*!< AHB1 peripherals */
AnnaBridge 146:22da6e220af6 1037 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 146:22da6e220af6 1038 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 146:22da6e220af6 1039 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 146:22da6e220af6 1040 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 146:22da6e220af6 1041 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 146:22da6e220af6 1042 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
AnnaBridge 146:22da6e220af6 1043 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
AnnaBridge 146:22da6e220af6 1044 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 146:22da6e220af6 1045 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 146:22da6e220af6 1046 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 146:22da6e220af6 1047 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 146:22da6e220af6 1048 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 146:22da6e220af6 1049 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 146:22da6e220af6 1050 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 146:22da6e220af6 1051 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 146:22da6e220af6 1052 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 146:22da6e220af6 1053 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 146:22da6e220af6 1054 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 146:22da6e220af6 1055 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 146:22da6e220af6 1056 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 146:22da6e220af6 1057 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 146:22da6e220af6 1058 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 146:22da6e220af6 1059 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 146:22da6e220af6 1060 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 146:22da6e220af6 1061 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 146:22da6e220af6 1062 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 146:22da6e220af6 1063 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 146:22da6e220af6 1064 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 146:22da6e220af6 1065 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 146:22da6e220af6 1066
AnnaBridge 146:22da6e220af6 1067 /*!< AHB2 peripherals */
AnnaBridge 146:22da6e220af6 1068 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
AnnaBridge 146:22da6e220af6 1069
AnnaBridge 146:22da6e220af6 1070
AnnaBridge 146:22da6e220af6 1071 /*!< FSMC Bankx registers base address */
AnnaBridge 146:22da6e220af6 1072 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
AnnaBridge 146:22da6e220af6 1073 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
AnnaBridge 146:22da6e220af6 1074
AnnaBridge 146:22da6e220af6 1075 /*!< Debug MCU registers base address */
AnnaBridge 146:22da6e220af6 1076 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 146:22da6e220af6 1077 /*!< USB registers base address */
AnnaBridge 146:22da6e220af6 1078 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 146:22da6e220af6 1079
AnnaBridge 146:22da6e220af6 1080 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 146:22da6e220af6 1081 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 146:22da6e220af6 1082 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 146:22da6e220af6 1083 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 146:22da6e220af6 1084 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 146:22da6e220af6 1085 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 146:22da6e220af6 1086 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 146:22da6e220af6 1087 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 146:22da6e220af6 1088 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 146:22da6e220af6 1089 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 146:22da6e220af6 1090 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 146:22da6e220af6 1091 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 146:22da6e220af6 1092
AnnaBridge 146:22da6e220af6 1093 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 146:22da6e220af6 1094 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 146:22da6e220af6 1095 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 146:22da6e220af6 1096 /**
AnnaBridge 146:22da6e220af6 1097 * @}
AnnaBridge 146:22da6e220af6 1098 */
AnnaBridge 146:22da6e220af6 1099
AnnaBridge 146:22da6e220af6 1100 /** @addtogroup Peripheral_declaration
AnnaBridge 146:22da6e220af6 1101 * @{
AnnaBridge 146:22da6e220af6 1102 */
AnnaBridge 146:22da6e220af6 1103 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 146:22da6e220af6 1104 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 146:22da6e220af6 1105 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 146:22da6e220af6 1106 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 146:22da6e220af6 1107 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 146:22da6e220af6 1108 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 146:22da6e220af6 1109 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 146:22da6e220af6 1110 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 146:22da6e220af6 1111 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 146:22da6e220af6 1112 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 146:22da6e220af6 1113 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 146:22da6e220af6 1114 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 146:22da6e220af6 1115 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 146:22da6e220af6 1116 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
AnnaBridge 146:22da6e220af6 1117 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 146:22da6e220af6 1118 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 146:22da6e220af6 1119 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
AnnaBridge 146:22da6e220af6 1120 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 146:22da6e220af6 1121 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 146:22da6e220af6 1122 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 146:22da6e220af6 1123 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 146:22da6e220af6 1124 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 146:22da6e220af6 1125 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 146:22da6e220af6 1126 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 146:22da6e220af6 1127 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
AnnaBridge 146:22da6e220af6 1128 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 146:22da6e220af6 1129 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
AnnaBridge 146:22da6e220af6 1130 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
AnnaBridge 146:22da6e220af6 1131 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 146:22da6e220af6 1132 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 146:22da6e220af6 1133 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
AnnaBridge 146:22da6e220af6 1134 #define UART7 ((USART_TypeDef *) UART7_BASE)
AnnaBridge 146:22da6e220af6 1135 #define UART8 ((USART_TypeDef *) UART8_BASE)
AnnaBridge 146:22da6e220af6 1136 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 146:22da6e220af6 1137 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 146:22da6e220af6 1138 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 146:22da6e220af6 1139 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 146:22da6e220af6 1140 #define UART9 ((USART_TypeDef *) UART9_BASE)
AnnaBridge 146:22da6e220af6 1141 #define UART10 ((USART_TypeDef *) UART10_BASE)
AnnaBridge 146:22da6e220af6 1142 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 146:22da6e220af6 1143 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
AnnaBridge 146:22da6e220af6 1144 /* Legacy define */
AnnaBridge 146:22da6e220af6 1145 #define ADC ADC1_COMMON
AnnaBridge 146:22da6e220af6 1146 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
AnnaBridge 146:22da6e220af6 1147 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 146:22da6e220af6 1148 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 146:22da6e220af6 1149 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 146:22da6e220af6 1150 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 146:22da6e220af6 1151 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 146:22da6e220af6 1152 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 146:22da6e220af6 1153 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 146:22da6e220af6 1154 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 146:22da6e220af6 1155 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
AnnaBridge 146:22da6e220af6 1156 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
AnnaBridge 146:22da6e220af6 1157 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
AnnaBridge 146:22da6e220af6 1158 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
AnnaBridge 146:22da6e220af6 1159 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
AnnaBridge 146:22da6e220af6 1160 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
AnnaBridge 146:22da6e220af6 1161 #define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
AnnaBridge 146:22da6e220af6 1162 #define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
AnnaBridge 146:22da6e220af6 1163 #define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
AnnaBridge 146:22da6e220af6 1164 #define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
AnnaBridge 146:22da6e220af6 1165 #define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
AnnaBridge 146:22da6e220af6 1166 #define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
AnnaBridge 146:22da6e220af6 1167 #define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
AnnaBridge 146:22da6e220af6 1168 #define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
AnnaBridge 146:22da6e220af6 1169 #define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
AnnaBridge 146:22da6e220af6 1170 #define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
AnnaBridge 146:22da6e220af6 1171 #define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
AnnaBridge 146:22da6e220af6 1172 #define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
AnnaBridge 146:22da6e220af6 1173 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 146:22da6e220af6 1174 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 146:22da6e220af6 1175 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 146:22da6e220af6 1176 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 146:22da6e220af6 1177 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 146:22da6e220af6 1178 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 146:22da6e220af6 1179 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 146:22da6e220af6 1180 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 146:22da6e220af6 1181 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 146:22da6e220af6 1182 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 146:22da6e220af6 1183 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 146:22da6e220af6 1184 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 146:22da6e220af6 1185 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 146:22da6e220af6 1186 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 146:22da6e220af6 1187 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 146:22da6e220af6 1188 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 146:22da6e220af6 1189 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 146:22da6e220af6 1190 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 146:22da6e220af6 1191 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 146:22da6e220af6 1192 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 146:22da6e220af6 1193 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 146:22da6e220af6 1194 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 146:22da6e220af6 1195 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 146:22da6e220af6 1196 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 146:22da6e220af6 1197 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 146:22da6e220af6 1198 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 146:22da6e220af6 1199 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 146:22da6e220af6 1200 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 146:22da6e220af6 1201 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 146:22da6e220af6 1202 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 146:22da6e220af6 1203 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 146:22da6e220af6 1204 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 146:22da6e220af6 1205 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 146:22da6e220af6 1206 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
AnnaBridge 146:22da6e220af6 1207 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
AnnaBridge 146:22da6e220af6 1208 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
AnnaBridge 146:22da6e220af6 1209 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 146:22da6e220af6 1210 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 146:22da6e220af6 1211
AnnaBridge 146:22da6e220af6 1212 /**
AnnaBridge 146:22da6e220af6 1213 * @}
AnnaBridge 146:22da6e220af6 1214 */
AnnaBridge 146:22da6e220af6 1215
AnnaBridge 146:22da6e220af6 1216 /** @addtogroup Exported_constants
AnnaBridge 146:22da6e220af6 1217 * @{
AnnaBridge 146:22da6e220af6 1218 */
AnnaBridge 146:22da6e220af6 1219
AnnaBridge 146:22da6e220af6 1220 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 146:22da6e220af6 1221 * @{
AnnaBridge 146:22da6e220af6 1222 */
AnnaBridge 146:22da6e220af6 1223
AnnaBridge 146:22da6e220af6 1224 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1225 /* Peripheral Registers_Bits_Definition */
AnnaBridge 146:22da6e220af6 1226 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1227
AnnaBridge 146:22da6e220af6 1228 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1229 /* */
AnnaBridge 146:22da6e220af6 1230 /* Analog to Digital Converter */
AnnaBridge 146:22da6e220af6 1231 /* */
AnnaBridge 146:22da6e220af6 1232 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1233
AnnaBridge 146:22da6e220af6 1234 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 146:22da6e220af6 1235 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 146:22da6e220af6 1236 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1237 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 146:22da6e220af6 1238 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 146:22da6e220af6 1239 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1240 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 146:22da6e220af6 1241 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 146:22da6e220af6 1242 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1243 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 146:22da6e220af6 1244 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 146:22da6e220af6 1245 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1246 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 146:22da6e220af6 1247 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 146:22da6e220af6 1248 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1249 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 146:22da6e220af6 1250 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 146:22da6e220af6 1251 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1252 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 146:22da6e220af6 1253
AnnaBridge 146:22da6e220af6 1254 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 146:22da6e220af6 1255 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 146:22da6e220af6 1256 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1257 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 146:22da6e220af6 1258 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1259 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1260 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1261 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1262 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1263 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 146:22da6e220af6 1264 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1265 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 146:22da6e220af6 1266 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 146:22da6e220af6 1267 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1268 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 146:22da6e220af6 1269 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 146:22da6e220af6 1270 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1271 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 146:22da6e220af6 1272 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 146:22da6e220af6 1273 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1274 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 146:22da6e220af6 1275 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 146:22da6e220af6 1276 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1277 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 146:22da6e220af6 1278 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 146:22da6e220af6 1279 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1280 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 146:22da6e220af6 1281 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 146:22da6e220af6 1282 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1283 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 146:22da6e220af6 1284 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 146:22da6e220af6 1285 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1286 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 146:22da6e220af6 1287 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 146:22da6e220af6 1288 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 146:22da6e220af6 1289 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 146:22da6e220af6 1290 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1291 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1292 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1293 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 146:22da6e220af6 1294 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1295 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 146:22da6e220af6 1296 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 146:22da6e220af6 1297 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1298 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 146:22da6e220af6 1299 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 146:22da6e220af6 1300 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 1301 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 146:22da6e220af6 1302 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1303 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1304 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 146:22da6e220af6 1305 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1306 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 146:22da6e220af6 1307
AnnaBridge 146:22da6e220af6 1308 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 146:22da6e220af6 1309 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 146:22da6e220af6 1310 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1311 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 146:22da6e220af6 1312 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 146:22da6e220af6 1313 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1314 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 146:22da6e220af6 1315 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 146:22da6e220af6 1316 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1317 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 146:22da6e220af6 1318 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 146:22da6e220af6 1319 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1320 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 146:22da6e220af6 1321 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 146:22da6e220af6 1322 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1323 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 146:22da6e220af6 1324 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 146:22da6e220af6 1325 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1326 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 146:22da6e220af6 1327 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 146:22da6e220af6 1328 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 1329 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 146:22da6e220af6 1330 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1331 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1332 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1333 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1334 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 146:22da6e220af6 1335 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 1336 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 146:22da6e220af6 1337 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1338 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1339 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 146:22da6e220af6 1340 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1341 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 146:22da6e220af6 1342 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 146:22da6e220af6 1343 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 1344 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 146:22da6e220af6 1345 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1346 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1347 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1348 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 1349 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 146:22da6e220af6 1350 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 1351 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 146:22da6e220af6 1352 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 1353 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 1354 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 146:22da6e220af6 1355 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 1356 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 146:22da6e220af6 1357
AnnaBridge 146:22da6e220af6 1358 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 146:22da6e220af6 1359 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 146:22da6e220af6 1360 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 1361 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 146:22da6e220af6 1362 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1363 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1364 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1365 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 146:22da6e220af6 1366 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 146:22da6e220af6 1367 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 146:22da6e220af6 1368 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1369 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1370 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1371 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 146:22da6e220af6 1372 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 146:22da6e220af6 1373 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 146:22da6e220af6 1374 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1375 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1376 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1377 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 146:22da6e220af6 1378 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 146:22da6e220af6 1379 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 146:22da6e220af6 1380 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1381 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1382 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1383 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 146:22da6e220af6 1384 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 1385 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 146:22da6e220af6 1386 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1387 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1388 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1389 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 146:22da6e220af6 1390 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 146:22da6e220af6 1391 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 146:22da6e220af6 1392 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1393 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1394 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1395 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 146:22da6e220af6 1396 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 146:22da6e220af6 1397 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 146:22da6e220af6 1398 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1399 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1400 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1401 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 146:22da6e220af6 1402 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 146:22da6e220af6 1403 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 146:22da6e220af6 1404 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1405 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1406 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1407 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 146:22da6e220af6 1408 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 146:22da6e220af6 1409 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 146:22da6e220af6 1410 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1411 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1412 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1413
AnnaBridge 146:22da6e220af6 1414 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 146:22da6e220af6 1415 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 146:22da6e220af6 1416 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 1417 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 146:22da6e220af6 1418 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1419 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1420 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1421 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 146:22da6e220af6 1422 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 146:22da6e220af6 1423 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 146:22da6e220af6 1424 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1425 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1426 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1427 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 146:22da6e220af6 1428 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 146:22da6e220af6 1429 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 146:22da6e220af6 1430 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1431 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1432 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1433 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 146:22da6e220af6 1434 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 146:22da6e220af6 1435 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 146:22da6e220af6 1436 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1437 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1438 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1439 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 146:22da6e220af6 1440 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 1441 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 146:22da6e220af6 1442 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1443 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1444 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1445 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 146:22da6e220af6 1446 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 146:22da6e220af6 1447 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 146:22da6e220af6 1448 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1449 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1450 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1451 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 146:22da6e220af6 1452 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 146:22da6e220af6 1453 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 146:22da6e220af6 1454 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1455 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1456 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1457 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 146:22da6e220af6 1458 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 146:22da6e220af6 1459 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 146:22da6e220af6 1460 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1461 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1462 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1463 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 146:22da6e220af6 1464 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 146:22da6e220af6 1465 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 146:22da6e220af6 1466 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1467 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1468 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1469 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 146:22da6e220af6 1470 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 146:22da6e220af6 1471 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 146:22da6e220af6 1472 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 1473 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 1474 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 1475
AnnaBridge 146:22da6e220af6 1476 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 146:22da6e220af6 1477 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 146:22da6e220af6 1478 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1479 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 146:22da6e220af6 1480
AnnaBridge 146:22da6e220af6 1481 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 146:22da6e220af6 1482 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 146:22da6e220af6 1483 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1484 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 146:22da6e220af6 1485
AnnaBridge 146:22da6e220af6 1486 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 146:22da6e220af6 1487 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 146:22da6e220af6 1488 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1489 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 146:22da6e220af6 1490
AnnaBridge 146:22da6e220af6 1491 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 146:22da6e220af6 1492 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 146:22da6e220af6 1493 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1494 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 146:22da6e220af6 1495
AnnaBridge 146:22da6e220af6 1496 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 146:22da6e220af6 1497 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 146:22da6e220af6 1498 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1499 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 146:22da6e220af6 1500
AnnaBridge 146:22da6e220af6 1501 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 146:22da6e220af6 1502 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 146:22da6e220af6 1503 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 1504 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 146:22da6e220af6 1505
AnnaBridge 146:22da6e220af6 1506 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 146:22da6e220af6 1507 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 146:22da6e220af6 1508 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1509 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1510 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1511 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1512 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1513 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1514 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1515 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 146:22da6e220af6 1516 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 146:22da6e220af6 1517 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1518 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1519 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1520 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1521 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1522 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1523 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 146:22da6e220af6 1524 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 146:22da6e220af6 1525 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1526 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1527 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1528 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1529 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1530 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1531 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 146:22da6e220af6 1532 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 146:22da6e220af6 1533 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1534 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1535 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1536 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1537 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1538 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1539 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 146:22da6e220af6 1540 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 1541 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 146:22da6e220af6 1542 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1543 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1544 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1545 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1546
AnnaBridge 146:22da6e220af6 1547 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 146:22da6e220af6 1548 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 146:22da6e220af6 1549 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1550 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1551 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1552 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1553 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1554 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1555 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1556 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 146:22da6e220af6 1557 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 146:22da6e220af6 1558 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1559 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1560 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1561 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1562 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1563 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1564 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 146:22da6e220af6 1565 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 146:22da6e220af6 1566 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1567 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1568 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1569 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1570 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1571 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1572 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 146:22da6e220af6 1573 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 146:22da6e220af6 1574 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1575 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1576 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1577 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1578 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1579 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1580 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 146:22da6e220af6 1581 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 146:22da6e220af6 1582 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1583 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1584 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1585 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1586 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1587 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1588 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 146:22da6e220af6 1589 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 146:22da6e220af6 1590 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1591 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1592 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1593 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 1594 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 1595 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 1596
AnnaBridge 146:22da6e220af6 1597 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 146:22da6e220af6 1598 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 146:22da6e220af6 1599 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1600 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1601 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1602 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1603 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1604 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1605 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1606 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 146:22da6e220af6 1607 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 146:22da6e220af6 1608 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1609 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1610 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1611 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1612 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1613 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1614 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 146:22da6e220af6 1615 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 146:22da6e220af6 1616 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1617 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1618 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1619 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1620 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1621 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1622 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 146:22da6e220af6 1623 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 146:22da6e220af6 1624 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1625 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1626 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1627 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1628 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1629 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1630 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 146:22da6e220af6 1631 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 146:22da6e220af6 1632 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1633 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1634 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1635 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1636 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1637 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 1638 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 146:22da6e220af6 1639 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 146:22da6e220af6 1640 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 146:22da6e220af6 1641 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 1642 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1643 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 1644 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 1645 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 1646
AnnaBridge 146:22da6e220af6 1647 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 146:22da6e220af6 1648 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 146:22da6e220af6 1649 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1650 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 146:22da6e220af6 1651 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1652 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1653 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1654 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1655 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1656 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 146:22da6e220af6 1657 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 146:22da6e220af6 1658 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 146:22da6e220af6 1659 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1660 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1661 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1662 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1663 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1664 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 146:22da6e220af6 1665 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 146:22da6e220af6 1666 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 146:22da6e220af6 1667 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1668 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1669 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 1670 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1671 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1672 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 146:22da6e220af6 1673 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 146:22da6e220af6 1674 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 146:22da6e220af6 1675 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1676 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1677 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1678 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1679 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1680 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 146:22da6e220af6 1681 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 1682 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 146:22da6e220af6 1683 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 1684 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 1685
AnnaBridge 146:22da6e220af6 1686 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 146:22da6e220af6 1687 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 1688 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1689 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
AnnaBridge 146:22da6e220af6 1690
AnnaBridge 146:22da6e220af6 1691 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 146:22da6e220af6 1692 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 1693 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1694 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
AnnaBridge 146:22da6e220af6 1695
AnnaBridge 146:22da6e220af6 1696 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 146:22da6e220af6 1697 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 1698 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1699 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
AnnaBridge 146:22da6e220af6 1700
AnnaBridge 146:22da6e220af6 1701 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 146:22da6e220af6 1702 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 1703 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1704 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
AnnaBridge 146:22da6e220af6 1705
AnnaBridge 146:22da6e220af6 1706 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 146:22da6e220af6 1707 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 146:22da6e220af6 1708 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1709 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 146:22da6e220af6 1710 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 146:22da6e220af6 1711 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 1712 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 146:22da6e220af6 1713
AnnaBridge 146:22da6e220af6 1714 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 146:22da6e220af6 1715 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 146:22da6e220af6 1716 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1717 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 146:22da6e220af6 1718 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 146:22da6e220af6 1719 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1720 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 146:22da6e220af6 1721 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 146:22da6e220af6 1722 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1723 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 146:22da6e220af6 1724 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 146:22da6e220af6 1725 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1726 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 146:22da6e220af6 1727 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 146:22da6e220af6 1728 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1729 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 146:22da6e220af6 1730 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 146:22da6e220af6 1731 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1732 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 146:22da6e220af6 1733
AnnaBridge 146:22da6e220af6 1734 /* Legacy defines */
AnnaBridge 146:22da6e220af6 1735 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 146:22da6e220af6 1736
AnnaBridge 146:22da6e220af6 1737 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 146:22da6e220af6 1738 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 146:22da6e220af6 1739 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 1740 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 146:22da6e220af6 1741 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1742 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1743 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1744 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1745 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1746 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 146:22da6e220af6 1747 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 1748 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 146:22da6e220af6 1749 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1750 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1751 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1752 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1753 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 146:22da6e220af6 1754 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 1755 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 146:22da6e220af6 1756 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 146:22da6e220af6 1757 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 1758 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 146:22da6e220af6 1759 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 1760 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1761 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 146:22da6e220af6 1762 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 1763 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 146:22da6e220af6 1764 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1765 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1766 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 146:22da6e220af6 1767 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 1768 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 146:22da6e220af6 1769 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 146:22da6e220af6 1770 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1771 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 146:22da6e220af6 1772
AnnaBridge 146:22da6e220af6 1773 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 146:22da6e220af6 1774 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 146:22da6e220af6 1775 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 1776 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 146:22da6e220af6 1777 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 1778 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 1779 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 146:22da6e220af6 1780
AnnaBridge 146:22da6e220af6 1781 /* Legacy defines */
AnnaBridge 146:22da6e220af6 1782 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 146:22da6e220af6 1783 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 146:22da6e220af6 1784
AnnaBridge 146:22da6e220af6 1785 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1786 /* */
AnnaBridge 146:22da6e220af6 1787 /* Controller Area Network */
AnnaBridge 146:22da6e220af6 1788 /* */
AnnaBridge 146:22da6e220af6 1789 /******************************************************************************/
AnnaBridge 146:22da6e220af6 1790 /*!<CAN control and status registers */
AnnaBridge 146:22da6e220af6 1791 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 146:22da6e220af6 1792 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 146:22da6e220af6 1793 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1794 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 146:22da6e220af6 1795 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 146:22da6e220af6 1796 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1797 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 146:22da6e220af6 1798 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 146:22da6e220af6 1799 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1800 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 146:22da6e220af6 1801 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 146:22da6e220af6 1802 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1803 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 146:22da6e220af6 1804 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 146:22da6e220af6 1805 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1806 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 146:22da6e220af6 1807 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 146:22da6e220af6 1808 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1809 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 146:22da6e220af6 1810 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 146:22da6e220af6 1811 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1812 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 146:22da6e220af6 1813 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 146:22da6e220af6 1814 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1815 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 146:22da6e220af6 1816 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 146:22da6e220af6 1817 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1818 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 146:22da6e220af6 1819 #define CAN_MCR_DBF_Pos (16U)
AnnaBridge 146:22da6e220af6 1820 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1821 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
AnnaBridge 146:22da6e220af6 1822 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 146:22da6e220af6 1823 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 146:22da6e220af6 1824 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1825 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 146:22da6e220af6 1826 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 146:22da6e220af6 1827 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1828 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 146:22da6e220af6 1829 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 146:22da6e220af6 1830 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1831 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 146:22da6e220af6 1832 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 146:22da6e220af6 1833 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1834 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 146:22da6e220af6 1835 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 146:22da6e220af6 1836 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1837 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 146:22da6e220af6 1838 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 146:22da6e220af6 1839 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1840 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 146:22da6e220af6 1841 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 146:22da6e220af6 1842 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1843 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 146:22da6e220af6 1844 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 146:22da6e220af6 1845 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1846 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 146:22da6e220af6 1847 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 146:22da6e220af6 1848 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1849 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 146:22da6e220af6 1850
AnnaBridge 146:22da6e220af6 1851 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 146:22da6e220af6 1852 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 146:22da6e220af6 1853 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1854 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 146:22da6e220af6 1855 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 146:22da6e220af6 1856 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1857 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 146:22da6e220af6 1858 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 146:22da6e220af6 1859 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1860 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 146:22da6e220af6 1861 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 146:22da6e220af6 1862 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1863 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 146:22da6e220af6 1864 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 146:22da6e220af6 1865 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 1866 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 146:22da6e220af6 1867 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 146:22da6e220af6 1868 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1869 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 146:22da6e220af6 1870 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 146:22da6e220af6 1871 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1872 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 146:22da6e220af6 1873 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 146:22da6e220af6 1874 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1875 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 146:22da6e220af6 1876 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 146:22da6e220af6 1877 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1878 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 146:22da6e220af6 1879 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 146:22da6e220af6 1880 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1881 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 146:22da6e220af6 1882 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 146:22da6e220af6 1883 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1884 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 146:22da6e220af6 1885 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 146:22da6e220af6 1886 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1887 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 146:22da6e220af6 1888 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 146:22da6e220af6 1889 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 1890 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 146:22da6e220af6 1891 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 146:22da6e220af6 1892 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 1893 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 146:22da6e220af6 1894 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 146:22da6e220af6 1895 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 1896 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 146:22da6e220af6 1897 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 146:22da6e220af6 1898 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 1899 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 146:22da6e220af6 1900
AnnaBridge 146:22da6e220af6 1901 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 146:22da6e220af6 1902 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 146:22da6e220af6 1903 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 146:22da6e220af6 1904 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 146:22da6e220af6 1905 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 1906 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 146:22da6e220af6 1907 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 146:22da6e220af6 1908 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 1909 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 146:22da6e220af6 1910 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 146:22da6e220af6 1911 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 1912 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 146:22da6e220af6 1913
AnnaBridge 146:22da6e220af6 1914 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 146:22da6e220af6 1915 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 146:22da6e220af6 1916 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 146:22da6e220af6 1917 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 146:22da6e220af6 1918 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 1919 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 146:22da6e220af6 1920 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 146:22da6e220af6 1921 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 1922 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 146:22da6e220af6 1923 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 146:22da6e220af6 1924 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 1925 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 146:22da6e220af6 1926
AnnaBridge 146:22da6e220af6 1927 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 146:22da6e220af6 1928 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 146:22da6e220af6 1929 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 1930 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 146:22da6e220af6 1931 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 146:22da6e220af6 1932 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1933 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 146:22da6e220af6 1934 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 146:22da6e220af6 1935 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1936 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 146:22da6e220af6 1937 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 146:22da6e220af6 1938 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1939 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 146:22da6e220af6 1940
AnnaBridge 146:22da6e220af6 1941 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 146:22da6e220af6 1942 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 146:22da6e220af6 1943 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 1944 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 146:22da6e220af6 1945 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 146:22da6e220af6 1946 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1947 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 146:22da6e220af6 1948 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 146:22da6e220af6 1949 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1950 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 146:22da6e220af6 1951 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 146:22da6e220af6 1952 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1953 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 146:22da6e220af6 1954
AnnaBridge 146:22da6e220af6 1955 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 146:22da6e220af6 1956 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 146:22da6e220af6 1957 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 1958 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 146:22da6e220af6 1959 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 146:22da6e220af6 1960 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 1961 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 146:22da6e220af6 1962 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 146:22da6e220af6 1963 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 1964 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 146:22da6e220af6 1965 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 146:22da6e220af6 1966 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 1967 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 146:22da6e220af6 1968 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 146:22da6e220af6 1969 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 1970 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 146:22da6e220af6 1971 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 146:22da6e220af6 1972 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 1973 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 146:22da6e220af6 1974 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 146:22da6e220af6 1975 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 1976 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 146:22da6e220af6 1977 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 146:22da6e220af6 1978 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 1979 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 146:22da6e220af6 1980 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 146:22da6e220af6 1981 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 1982 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 146:22da6e220af6 1983 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 146:22da6e220af6 1984 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 1985 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 146:22da6e220af6 1986 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 146:22da6e220af6 1987 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 1988 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 146:22da6e220af6 1989 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 146:22da6e220af6 1990 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 1991 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 1992 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 146:22da6e220af6 1993 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 1994 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 146:22da6e220af6 1995 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 146:22da6e220af6 1996 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 1997 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 146:22da6e220af6 1998 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 146:22da6e220af6 1999
AnnaBridge 146:22da6e220af6 2000 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 146:22da6e220af6 2001 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 146:22da6e220af6 2002 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2003 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 146:22da6e220af6 2004 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 146:22da6e220af6 2005 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2006 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 146:22da6e220af6 2007 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 146:22da6e220af6 2008 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2009 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 146:22da6e220af6 2010
AnnaBridge 146:22da6e220af6 2011 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 146:22da6e220af6 2012 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 2013 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 146:22da6e220af6 2014 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2015 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2016 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2017
AnnaBridge 146:22da6e220af6 2018 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 146:22da6e220af6 2019 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2020 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 146:22da6e220af6 2021 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 146:22da6e220af6 2022 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2023 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 146:22da6e220af6 2024
AnnaBridge 146:22da6e220af6 2025 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 146:22da6e220af6 2026 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 146:22da6e220af6 2027 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 146:22da6e220af6 2028 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 146:22da6e220af6 2029 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 146:22da6e220af6 2030 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 2031 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 146:22da6e220af6 2032 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2033 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2034 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2035 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2036 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 146:22da6e220af6 2037 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 146:22da6e220af6 2038 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 146:22da6e220af6 2039 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2040 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2041 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2042 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 146:22da6e220af6 2043 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 2044 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 146:22da6e220af6 2045 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2046 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2047 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 146:22da6e220af6 2048 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 2049 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 146:22da6e220af6 2050 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 146:22da6e220af6 2051 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 2052 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 146:22da6e220af6 2053
AnnaBridge 146:22da6e220af6 2054
AnnaBridge 146:22da6e220af6 2055 /*!<Mailbox registers */
AnnaBridge 146:22da6e220af6 2056 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 146:22da6e220af6 2057 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 146:22da6e220af6 2058 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2059 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 146:22da6e220af6 2060 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 146:22da6e220af6 2061 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2062 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 146:22da6e220af6 2063 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 146:22da6e220af6 2064 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2065 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 146:22da6e220af6 2066 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 146:22da6e220af6 2067 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 146:22da6e220af6 2068 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 146:22da6e220af6 2069 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 146:22da6e220af6 2070 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 146:22da6e220af6 2071 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 146:22da6e220af6 2072
AnnaBridge 146:22da6e220af6 2073 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 146:22da6e220af6 2074 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 146:22da6e220af6 2075 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 2076 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 146:22da6e220af6 2077 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 146:22da6e220af6 2078 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2079 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 146:22da6e220af6 2080 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 146:22da6e220af6 2081 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 2082 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 146:22da6e220af6 2083
AnnaBridge 146:22da6e220af6 2084 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 146:22da6e220af6 2085 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2086 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2087 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 146:22da6e220af6 2088 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 146:22da6e220af6 2089 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2090 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 146:22da6e220af6 2091 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 2092 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2093 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 146:22da6e220af6 2094 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 146:22da6e220af6 2095 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2096 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 146:22da6e220af6 2097
AnnaBridge 146:22da6e220af6 2098 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 146:22da6e220af6 2099 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 146:22da6e220af6 2100 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2101 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 146:22da6e220af6 2102 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 146:22da6e220af6 2103 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2104 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 146:22da6e220af6 2105 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 146:22da6e220af6 2106 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2107 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 146:22da6e220af6 2108 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 146:22da6e220af6 2109 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2110 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 146:22da6e220af6 2111
AnnaBridge 146:22da6e220af6 2112 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 146:22da6e220af6 2113 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 146:22da6e220af6 2114 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2115 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 146:22da6e220af6 2116 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 146:22da6e220af6 2117 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2118 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 146:22da6e220af6 2119 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 146:22da6e220af6 2120 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2121 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 146:22da6e220af6 2122 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 146:22da6e220af6 2123 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 146:22da6e220af6 2124 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 146:22da6e220af6 2125 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 146:22da6e220af6 2126 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 146:22da6e220af6 2127 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 146:22da6e220af6 2128
AnnaBridge 146:22da6e220af6 2129 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 146:22da6e220af6 2130 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 146:22da6e220af6 2131 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 2132 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 146:22da6e220af6 2133 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 146:22da6e220af6 2134 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2135 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 146:22da6e220af6 2136 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 146:22da6e220af6 2137 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 2138 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 146:22da6e220af6 2139
AnnaBridge 146:22da6e220af6 2140 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 146:22da6e220af6 2141 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2142 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2143 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 146:22da6e220af6 2144 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 146:22da6e220af6 2145 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2146 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 146:22da6e220af6 2147 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 2148 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2149 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 146:22da6e220af6 2150 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 146:22da6e220af6 2151 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2152 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 146:22da6e220af6 2153
AnnaBridge 146:22da6e220af6 2154 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 146:22da6e220af6 2155 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 146:22da6e220af6 2156 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2157 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 146:22da6e220af6 2158 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 146:22da6e220af6 2159 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2160 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 146:22da6e220af6 2161 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 146:22da6e220af6 2162 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2163 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 146:22da6e220af6 2164 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 146:22da6e220af6 2165 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2166 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 146:22da6e220af6 2167
AnnaBridge 146:22da6e220af6 2168 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 146:22da6e220af6 2169 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 146:22da6e220af6 2170 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2171 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 146:22da6e220af6 2172 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 146:22da6e220af6 2173 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2174 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 146:22da6e220af6 2175 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 146:22da6e220af6 2176 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2177 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 146:22da6e220af6 2178 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 146:22da6e220af6 2179 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 146:22da6e220af6 2180 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 146:22da6e220af6 2181 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 146:22da6e220af6 2182 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 146:22da6e220af6 2183 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 146:22da6e220af6 2184
AnnaBridge 146:22da6e220af6 2185 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 146:22da6e220af6 2186 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 146:22da6e220af6 2187 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 2188 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 146:22da6e220af6 2189 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 146:22da6e220af6 2190 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2191 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 146:22da6e220af6 2192 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 146:22da6e220af6 2193 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 2194 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 146:22da6e220af6 2195
AnnaBridge 146:22da6e220af6 2196 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 146:22da6e220af6 2197 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2198 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2199 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 146:22da6e220af6 2200 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 146:22da6e220af6 2201 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2202 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 146:22da6e220af6 2203 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 2204 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2205 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 146:22da6e220af6 2206 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 146:22da6e220af6 2207 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2208 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 146:22da6e220af6 2209
AnnaBridge 146:22da6e220af6 2210 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 146:22da6e220af6 2211 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 146:22da6e220af6 2212 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2213 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 146:22da6e220af6 2214 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 146:22da6e220af6 2215 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2216 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 146:22da6e220af6 2217 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 146:22da6e220af6 2218 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2219 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 146:22da6e220af6 2220 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 146:22da6e220af6 2221 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2222 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 146:22da6e220af6 2223
AnnaBridge 146:22da6e220af6 2224 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 146:22da6e220af6 2225 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 146:22da6e220af6 2226 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2227 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 146:22da6e220af6 2228 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 146:22da6e220af6 2229 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2230 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 146:22da6e220af6 2231 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 146:22da6e220af6 2232 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 146:22da6e220af6 2233 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 146:22da6e220af6 2234 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 146:22da6e220af6 2235 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 146:22da6e220af6 2236 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 146:22da6e220af6 2237
AnnaBridge 146:22da6e220af6 2238 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 146:22da6e220af6 2239 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 146:22da6e220af6 2240 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 2241 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 146:22da6e220af6 2242 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 146:22da6e220af6 2243 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2244 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 146:22da6e220af6 2245 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 146:22da6e220af6 2246 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 2247 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 146:22da6e220af6 2248
AnnaBridge 146:22da6e220af6 2249 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 146:22da6e220af6 2250 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2251 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2252 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 146:22da6e220af6 2253 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 146:22da6e220af6 2254 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2255 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 146:22da6e220af6 2256 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 2257 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2258 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 146:22da6e220af6 2259 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 146:22da6e220af6 2260 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2261 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 146:22da6e220af6 2262
AnnaBridge 146:22da6e220af6 2263 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 146:22da6e220af6 2264 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 146:22da6e220af6 2265 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2266 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 146:22da6e220af6 2267 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 146:22da6e220af6 2268 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2269 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 146:22da6e220af6 2270 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 146:22da6e220af6 2271 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2272 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 146:22da6e220af6 2273 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 146:22da6e220af6 2274 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2275 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 146:22da6e220af6 2276
AnnaBridge 146:22da6e220af6 2277 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 146:22da6e220af6 2278 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 146:22da6e220af6 2279 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2280 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 146:22da6e220af6 2281 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 146:22da6e220af6 2282 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2283 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 146:22da6e220af6 2284 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 146:22da6e220af6 2285 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 146:22da6e220af6 2286 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 146:22da6e220af6 2287 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 146:22da6e220af6 2288 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 146:22da6e220af6 2289 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 146:22da6e220af6 2290
AnnaBridge 146:22da6e220af6 2291 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 146:22da6e220af6 2292 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 146:22da6e220af6 2293 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 2294 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 146:22da6e220af6 2295 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 146:22da6e220af6 2296 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2297 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 146:22da6e220af6 2298 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 146:22da6e220af6 2299 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 2300 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 146:22da6e220af6 2301
AnnaBridge 146:22da6e220af6 2302 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 146:22da6e220af6 2303 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2304 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2305 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 146:22da6e220af6 2306 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 146:22da6e220af6 2307 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2308 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 146:22da6e220af6 2309 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 146:22da6e220af6 2310 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2311 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 146:22da6e220af6 2312 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 146:22da6e220af6 2313 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2314 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 146:22da6e220af6 2315
AnnaBridge 146:22da6e220af6 2316 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 146:22da6e220af6 2317 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 146:22da6e220af6 2318 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 2319 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 146:22da6e220af6 2320 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 146:22da6e220af6 2321 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 2322 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 146:22da6e220af6 2323 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 146:22da6e220af6 2324 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 2325 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 146:22da6e220af6 2326 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 146:22da6e220af6 2327 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 2328 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 146:22da6e220af6 2329
AnnaBridge 146:22da6e220af6 2330 /*!<CAN filter registers */
AnnaBridge 146:22da6e220af6 2331 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 146:22da6e220af6 2332 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 146:22da6e220af6 2333 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2334 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 146:22da6e220af6 2335 #define CAN_FMR_CAN2SB_Pos (8U)
AnnaBridge 146:22da6e220af6 2336 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
AnnaBridge 146:22da6e220af6 2337 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
AnnaBridge 146:22da6e220af6 2338
AnnaBridge 146:22da6e220af6 2339 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 146:22da6e220af6 2340 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 146:22da6e220af6 2341 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 146:22da6e220af6 2342 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 146:22da6e220af6 2343 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 146:22da6e220af6 2344 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2345 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 146:22da6e220af6 2346 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 146:22da6e220af6 2347 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2348 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 146:22da6e220af6 2349 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 146:22da6e220af6 2350 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2351 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 146:22da6e220af6 2352 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 146:22da6e220af6 2353 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2354 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 146:22da6e220af6 2355 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 146:22da6e220af6 2356 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2357 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 146:22da6e220af6 2358 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 146:22da6e220af6 2359 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2360 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 146:22da6e220af6 2361 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 146:22da6e220af6 2362 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2363 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 146:22da6e220af6 2364 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 146:22da6e220af6 2365 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2366 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 146:22da6e220af6 2367 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 146:22da6e220af6 2368 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2369 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 146:22da6e220af6 2370 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 146:22da6e220af6 2371 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2372 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 146:22da6e220af6 2373 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 146:22da6e220af6 2374 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2375 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 146:22da6e220af6 2376 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 146:22da6e220af6 2377 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2378 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 146:22da6e220af6 2379 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 146:22da6e220af6 2380 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2381 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 146:22da6e220af6 2382 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 146:22da6e220af6 2383 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2384 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 146:22da6e220af6 2385 #define CAN_FM1R_FBM14_Pos (14U)
AnnaBridge 146:22da6e220af6 2386 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2387 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
AnnaBridge 146:22da6e220af6 2388 #define CAN_FM1R_FBM15_Pos (15U)
AnnaBridge 146:22da6e220af6 2389 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2390 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
AnnaBridge 146:22da6e220af6 2391 #define CAN_FM1R_FBM16_Pos (16U)
AnnaBridge 146:22da6e220af6 2392 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2393 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
AnnaBridge 146:22da6e220af6 2394 #define CAN_FM1R_FBM17_Pos (17U)
AnnaBridge 146:22da6e220af6 2395 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2396 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
AnnaBridge 146:22da6e220af6 2397 #define CAN_FM1R_FBM18_Pos (18U)
AnnaBridge 146:22da6e220af6 2398 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2399 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
AnnaBridge 146:22da6e220af6 2400 #define CAN_FM1R_FBM19_Pos (19U)
AnnaBridge 146:22da6e220af6 2401 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2402 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
AnnaBridge 146:22da6e220af6 2403 #define CAN_FM1R_FBM20_Pos (20U)
AnnaBridge 146:22da6e220af6 2404 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2405 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
AnnaBridge 146:22da6e220af6 2406 #define CAN_FM1R_FBM21_Pos (21U)
AnnaBridge 146:22da6e220af6 2407 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2408 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
AnnaBridge 146:22da6e220af6 2409 #define CAN_FM1R_FBM22_Pos (22U)
AnnaBridge 146:22da6e220af6 2410 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2411 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
AnnaBridge 146:22da6e220af6 2412 #define CAN_FM1R_FBM23_Pos (23U)
AnnaBridge 146:22da6e220af6 2413 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2414 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
AnnaBridge 146:22da6e220af6 2415 #define CAN_FM1R_FBM24_Pos (24U)
AnnaBridge 146:22da6e220af6 2416 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2417 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
AnnaBridge 146:22da6e220af6 2418 #define CAN_FM1R_FBM25_Pos (25U)
AnnaBridge 146:22da6e220af6 2419 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2420 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
AnnaBridge 146:22da6e220af6 2421 #define CAN_FM1R_FBM26_Pos (26U)
AnnaBridge 146:22da6e220af6 2422 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2423 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
AnnaBridge 146:22da6e220af6 2424 #define CAN_FM1R_FBM27_Pos (27U)
AnnaBridge 146:22da6e220af6 2425 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2426 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
AnnaBridge 146:22da6e220af6 2427
AnnaBridge 146:22da6e220af6 2428 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 146:22da6e220af6 2429 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 146:22da6e220af6 2430 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 146:22da6e220af6 2431 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 146:22da6e220af6 2432 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 146:22da6e220af6 2433 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2434 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 146:22da6e220af6 2435 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 146:22da6e220af6 2436 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2437 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 146:22da6e220af6 2438 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 146:22da6e220af6 2439 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2440 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 146:22da6e220af6 2441 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 146:22da6e220af6 2442 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2443 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 146:22da6e220af6 2444 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 146:22da6e220af6 2445 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2446 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 146:22da6e220af6 2447 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 146:22da6e220af6 2448 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2449 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 146:22da6e220af6 2450 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 146:22da6e220af6 2451 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2452 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 146:22da6e220af6 2453 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 146:22da6e220af6 2454 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2455 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 146:22da6e220af6 2456 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 146:22da6e220af6 2457 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2458 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 146:22da6e220af6 2459 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 146:22da6e220af6 2460 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2461 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 146:22da6e220af6 2462 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 146:22da6e220af6 2463 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2464 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 146:22da6e220af6 2465 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 146:22da6e220af6 2466 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2467 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 146:22da6e220af6 2468 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 146:22da6e220af6 2469 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2470 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 146:22da6e220af6 2471 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 146:22da6e220af6 2472 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2473 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 146:22da6e220af6 2474 #define CAN_FS1R_FSC14_Pos (14U)
AnnaBridge 146:22da6e220af6 2475 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2476 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
AnnaBridge 146:22da6e220af6 2477 #define CAN_FS1R_FSC15_Pos (15U)
AnnaBridge 146:22da6e220af6 2478 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2479 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
AnnaBridge 146:22da6e220af6 2480 #define CAN_FS1R_FSC16_Pos (16U)
AnnaBridge 146:22da6e220af6 2481 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2482 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
AnnaBridge 146:22da6e220af6 2483 #define CAN_FS1R_FSC17_Pos (17U)
AnnaBridge 146:22da6e220af6 2484 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2485 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
AnnaBridge 146:22da6e220af6 2486 #define CAN_FS1R_FSC18_Pos (18U)
AnnaBridge 146:22da6e220af6 2487 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2488 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
AnnaBridge 146:22da6e220af6 2489 #define CAN_FS1R_FSC19_Pos (19U)
AnnaBridge 146:22da6e220af6 2490 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2491 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
AnnaBridge 146:22da6e220af6 2492 #define CAN_FS1R_FSC20_Pos (20U)
AnnaBridge 146:22da6e220af6 2493 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2494 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
AnnaBridge 146:22da6e220af6 2495 #define CAN_FS1R_FSC21_Pos (21U)
AnnaBridge 146:22da6e220af6 2496 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2497 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
AnnaBridge 146:22da6e220af6 2498 #define CAN_FS1R_FSC22_Pos (22U)
AnnaBridge 146:22da6e220af6 2499 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2500 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
AnnaBridge 146:22da6e220af6 2501 #define CAN_FS1R_FSC23_Pos (23U)
AnnaBridge 146:22da6e220af6 2502 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2503 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
AnnaBridge 146:22da6e220af6 2504 #define CAN_FS1R_FSC24_Pos (24U)
AnnaBridge 146:22da6e220af6 2505 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2506 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
AnnaBridge 146:22da6e220af6 2507 #define CAN_FS1R_FSC25_Pos (25U)
AnnaBridge 146:22da6e220af6 2508 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2509 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
AnnaBridge 146:22da6e220af6 2510 #define CAN_FS1R_FSC26_Pos (26U)
AnnaBridge 146:22da6e220af6 2511 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2512 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
AnnaBridge 146:22da6e220af6 2513 #define CAN_FS1R_FSC27_Pos (27U)
AnnaBridge 146:22da6e220af6 2514 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2515 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
AnnaBridge 146:22da6e220af6 2516
AnnaBridge 146:22da6e220af6 2517 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 146:22da6e220af6 2518 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 146:22da6e220af6 2519 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 146:22da6e220af6 2520 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 146:22da6e220af6 2521 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 146:22da6e220af6 2522 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2523 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
AnnaBridge 146:22da6e220af6 2524 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 146:22da6e220af6 2525 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2526 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
AnnaBridge 146:22da6e220af6 2527 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 146:22da6e220af6 2528 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2529 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
AnnaBridge 146:22da6e220af6 2530 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 146:22da6e220af6 2531 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2532 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
AnnaBridge 146:22da6e220af6 2533 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 146:22da6e220af6 2534 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2535 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
AnnaBridge 146:22da6e220af6 2536 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 146:22da6e220af6 2537 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2538 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
AnnaBridge 146:22da6e220af6 2539 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 146:22da6e220af6 2540 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2541 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
AnnaBridge 146:22da6e220af6 2542 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 146:22da6e220af6 2543 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2544 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
AnnaBridge 146:22da6e220af6 2545 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 146:22da6e220af6 2546 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2547 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
AnnaBridge 146:22da6e220af6 2548 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 146:22da6e220af6 2549 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2550 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
AnnaBridge 146:22da6e220af6 2551 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 146:22da6e220af6 2552 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2553 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
AnnaBridge 146:22da6e220af6 2554 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 146:22da6e220af6 2555 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2556 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
AnnaBridge 146:22da6e220af6 2557 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 146:22da6e220af6 2558 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2559 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
AnnaBridge 146:22da6e220af6 2560 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 146:22da6e220af6 2561 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2562 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
AnnaBridge 146:22da6e220af6 2563 #define CAN_FFA1R_FFA14_Pos (14U)
AnnaBridge 146:22da6e220af6 2564 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2565 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
AnnaBridge 146:22da6e220af6 2566 #define CAN_FFA1R_FFA15_Pos (15U)
AnnaBridge 146:22da6e220af6 2567 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2568 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
AnnaBridge 146:22da6e220af6 2569 #define CAN_FFA1R_FFA16_Pos (16U)
AnnaBridge 146:22da6e220af6 2570 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2571 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
AnnaBridge 146:22da6e220af6 2572 #define CAN_FFA1R_FFA17_Pos (17U)
AnnaBridge 146:22da6e220af6 2573 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2574 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
AnnaBridge 146:22da6e220af6 2575 #define CAN_FFA1R_FFA18_Pos (18U)
AnnaBridge 146:22da6e220af6 2576 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2577 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
AnnaBridge 146:22da6e220af6 2578 #define CAN_FFA1R_FFA19_Pos (19U)
AnnaBridge 146:22da6e220af6 2579 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2580 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
AnnaBridge 146:22da6e220af6 2581 #define CAN_FFA1R_FFA20_Pos (20U)
AnnaBridge 146:22da6e220af6 2582 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2583 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
AnnaBridge 146:22da6e220af6 2584 #define CAN_FFA1R_FFA21_Pos (21U)
AnnaBridge 146:22da6e220af6 2585 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2586 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
AnnaBridge 146:22da6e220af6 2587 #define CAN_FFA1R_FFA22_Pos (22U)
AnnaBridge 146:22da6e220af6 2588 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2589 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
AnnaBridge 146:22da6e220af6 2590 #define CAN_FFA1R_FFA23_Pos (23U)
AnnaBridge 146:22da6e220af6 2591 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2592 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
AnnaBridge 146:22da6e220af6 2593 #define CAN_FFA1R_FFA24_Pos (24U)
AnnaBridge 146:22da6e220af6 2594 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2595 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
AnnaBridge 146:22da6e220af6 2596 #define CAN_FFA1R_FFA25_Pos (25U)
AnnaBridge 146:22da6e220af6 2597 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2598 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
AnnaBridge 146:22da6e220af6 2599 #define CAN_FFA1R_FFA26_Pos (26U)
AnnaBridge 146:22da6e220af6 2600 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2601 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
AnnaBridge 146:22da6e220af6 2602 #define CAN_FFA1R_FFA27_Pos (27U)
AnnaBridge 146:22da6e220af6 2603 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2604 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
AnnaBridge 146:22da6e220af6 2605
AnnaBridge 146:22da6e220af6 2606 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 146:22da6e220af6 2607 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 146:22da6e220af6 2608 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 146:22da6e220af6 2609 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 146:22da6e220af6 2610 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 146:22da6e220af6 2611 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2612 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
AnnaBridge 146:22da6e220af6 2613 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 146:22da6e220af6 2614 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2615 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
AnnaBridge 146:22da6e220af6 2616 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 146:22da6e220af6 2617 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2618 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
AnnaBridge 146:22da6e220af6 2619 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 146:22da6e220af6 2620 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2621 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
AnnaBridge 146:22da6e220af6 2622 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 146:22da6e220af6 2623 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2624 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
AnnaBridge 146:22da6e220af6 2625 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 146:22da6e220af6 2626 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2627 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
AnnaBridge 146:22da6e220af6 2628 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 146:22da6e220af6 2629 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2630 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
AnnaBridge 146:22da6e220af6 2631 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 146:22da6e220af6 2632 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2633 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
AnnaBridge 146:22da6e220af6 2634 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 146:22da6e220af6 2635 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2636 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
AnnaBridge 146:22da6e220af6 2637 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 146:22da6e220af6 2638 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2639 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
AnnaBridge 146:22da6e220af6 2640 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 146:22da6e220af6 2641 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2642 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
AnnaBridge 146:22da6e220af6 2643 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 146:22da6e220af6 2644 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2645 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
AnnaBridge 146:22da6e220af6 2646 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 146:22da6e220af6 2647 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2648 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
AnnaBridge 146:22da6e220af6 2649 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 146:22da6e220af6 2650 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2651 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
AnnaBridge 146:22da6e220af6 2652 #define CAN_FA1R_FACT14_Pos (14U)
AnnaBridge 146:22da6e220af6 2653 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2654 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
AnnaBridge 146:22da6e220af6 2655 #define CAN_FA1R_FACT15_Pos (15U)
AnnaBridge 146:22da6e220af6 2656 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2657 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
AnnaBridge 146:22da6e220af6 2658 #define CAN_FA1R_FACT16_Pos (16U)
AnnaBridge 146:22da6e220af6 2659 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2660 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
AnnaBridge 146:22da6e220af6 2661 #define CAN_FA1R_FACT17_Pos (17U)
AnnaBridge 146:22da6e220af6 2662 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2663 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
AnnaBridge 146:22da6e220af6 2664 #define CAN_FA1R_FACT18_Pos (18U)
AnnaBridge 146:22da6e220af6 2665 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2666 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
AnnaBridge 146:22da6e220af6 2667 #define CAN_FA1R_FACT19_Pos (19U)
AnnaBridge 146:22da6e220af6 2668 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2669 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
AnnaBridge 146:22da6e220af6 2670 #define CAN_FA1R_FACT20_Pos (20U)
AnnaBridge 146:22da6e220af6 2671 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2672 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
AnnaBridge 146:22da6e220af6 2673 #define CAN_FA1R_FACT21_Pos (21U)
AnnaBridge 146:22da6e220af6 2674 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2675 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
AnnaBridge 146:22da6e220af6 2676 #define CAN_FA1R_FACT22_Pos (22U)
AnnaBridge 146:22da6e220af6 2677 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2678 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
AnnaBridge 146:22da6e220af6 2679 #define CAN_FA1R_FACT23_Pos (23U)
AnnaBridge 146:22da6e220af6 2680 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2681 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
AnnaBridge 146:22da6e220af6 2682 #define CAN_FA1R_FACT24_Pos (24U)
AnnaBridge 146:22da6e220af6 2683 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2684 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
AnnaBridge 146:22da6e220af6 2685 #define CAN_FA1R_FACT25_Pos (25U)
AnnaBridge 146:22da6e220af6 2686 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2687 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
AnnaBridge 146:22da6e220af6 2688 #define CAN_FA1R_FACT26_Pos (26U)
AnnaBridge 146:22da6e220af6 2689 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2690 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
AnnaBridge 146:22da6e220af6 2691 #define CAN_FA1R_FACT27_Pos (27U)
AnnaBridge 146:22da6e220af6 2692 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2693 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
AnnaBridge 146:22da6e220af6 2694
AnnaBridge 146:22da6e220af6 2695
AnnaBridge 146:22da6e220af6 2696 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 146:22da6e220af6 2697 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 2698 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2699 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 2700 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 2701 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2702 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 2703 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 2704 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2705 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 2706 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 2707 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2708 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 2709 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 2710 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2711 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 2712 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 2713 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2714 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 2715 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 2716 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2717 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 2718 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 2719 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2720 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 2721 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 2722 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2723 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 2724 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 2725 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2726 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 2727 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 2728 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2729 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 2730 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 2731 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2732 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 2733 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 2734 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2735 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 2736 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 2737 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2738 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 2739 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 2740 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2741 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 2742 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 2743 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2744 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 2745 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 2746 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2747 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 2748 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 2749 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2750 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 2751 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 2752 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2753 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 2754 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 2755 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2756 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 2757 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 2758 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2759 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 2760 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 2761 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2762 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 2763 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 2764 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2765 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 2766 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 2767 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2768 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 2769 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 2770 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2771 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 2772 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 2773 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2774 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 2775 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 2776 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2777 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 2778 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 2779 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2780 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 2781 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 2782 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 2783 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 2784 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 2785 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 2786 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 2787 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 2788 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 2789 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 2790 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 2791 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 2792 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 2793
AnnaBridge 146:22da6e220af6 2794 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 146:22da6e220af6 2795 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 2796 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2797 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 2798 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 2799 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2800 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 2801 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 2802 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2803 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 2804 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 2805 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2806 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 2807 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 2808 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2809 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 2810 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 2811 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2812 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 2813 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 2814 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2815 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 2816 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 2817 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2818 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 2819 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 2820 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2821 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 2822 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 2823 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2824 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 2825 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 2826 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2827 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 2828 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 2829 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2830 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 2831 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 2832 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2833 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 2834 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 2835 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2836 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 2837 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 2838 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2839 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 2840 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 2841 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2842 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 2843 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 2844 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2845 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 2846 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 2847 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2848 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 2849 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 2850 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2851 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 2852 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 2853 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2854 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 2855 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 2856 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2857 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 2858 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 2859 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2860 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 2861 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 2862 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2863 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 2864 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 2865 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2866 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 2867 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 2868 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2869 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 2870 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 2871 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2872 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 2873 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 2874 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2875 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 2876 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 2877 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2878 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 2879 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 2880 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 2881 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 2882 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 2883 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 2884 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 2885 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 2886 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 2887 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 2888 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 2889 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 2890 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 2891
AnnaBridge 146:22da6e220af6 2892 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 146:22da6e220af6 2893 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 2894 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2895 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 2896 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 2897 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2898 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 2899 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 2900 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2901 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 2902 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 2903 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 2904 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 2905 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 2906 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 2907 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 2908 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 2909 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 2910 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 2911 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 2912 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 2913 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 2914 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 2915 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 2916 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 2917 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 2918 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 2919 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 2920 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 2921 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 2922 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 2923 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 2924 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 2925 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 2926 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 2927 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 2928 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 2929 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 2930 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 2931 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 2932 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 2933 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 2934 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 2935 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 2936 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 2937 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 2938 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 2939 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 2940 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 2941 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 2942 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 2943 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 2944 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 2945 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 2946 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 2947 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 2948 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 2949 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 2950 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 2951 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 2952 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 2953 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 2954 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 2955 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 2956 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 2957 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 2958 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 2959 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 2960 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 2961 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 2962 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 2963 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 2964 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 2965 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 2966 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 2967 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 2968 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 2969 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 2970 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 2971 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 2972 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 2973 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 2974 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 2975 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 2976 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 2977 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 2978 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 2979 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 2980 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 2981 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 2982 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 2983 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 2984 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 2985 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 2986 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 2987 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 2988 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 2989
AnnaBridge 146:22da6e220af6 2990 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 146:22da6e220af6 2991 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 2992 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 2993 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 2994 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 2995 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 2996 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 2997 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 2998 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 2999 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3000 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3001 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3002 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3003 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3004 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3005 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3006 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3007 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3008 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3009 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3010 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3011 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3012 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3013 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3014 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3015 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3016 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3017 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3018 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3019 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3020 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3021 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3022 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3023 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3024 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3025 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3026 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3027 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3028 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3029 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3030 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3031 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3032 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3033 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3034 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3035 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3036 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3037 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3038 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3039 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3040 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3041 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3042 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3043 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3044 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3045 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3046 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3047 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3048 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3049 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3050 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3051 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3052 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3053 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3054 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3055 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3056 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3057 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3058 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3059 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3060 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3061 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3062 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3063 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3064 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3065 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3066 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3067 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3068 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3069 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3070 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3071 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3072 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3073 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3074 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3075 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3076 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3077 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3078 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3079 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3080 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3081 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3082 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3083 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3084 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3085 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3086 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3087
AnnaBridge 146:22da6e220af6 3088 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 146:22da6e220af6 3089 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3090 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3091 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3092 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3093 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3094 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3095 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3096 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3097 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3098 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3099 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3100 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3101 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3102 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3103 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3104 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3105 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3106 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3107 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3108 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3109 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3110 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3111 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3112 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3113 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3114 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3115 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3116 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3117 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3118 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3119 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3120 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3121 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3122 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3123 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3124 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3125 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3126 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3127 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3128 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3129 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3130 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3131 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3132 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3133 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3134 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3135 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3136 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3137 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3138 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3139 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3140 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3141 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3142 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3143 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3144 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3145 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3146 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3147 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3148 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3149 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3150 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3151 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3152 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3153 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3154 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3155 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3156 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3157 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3158 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3159 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3160 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3161 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3162 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3163 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3164 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3165 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3166 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3167 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3168 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3169 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3170 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3171 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3172 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3173 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3174 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3175 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3176 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3177 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3178 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3179 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3180 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3181 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3182 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3183 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3184 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3185
AnnaBridge 146:22da6e220af6 3186 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 146:22da6e220af6 3187 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3188 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3189 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3190 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3191 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3192 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3193 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3194 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3195 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3196 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3197 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3198 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3199 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3200 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3201 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3202 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3203 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3204 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3205 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3206 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3207 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3208 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3209 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3210 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3211 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3212 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3213 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3214 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3215 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3216 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3217 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3218 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3219 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3220 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3221 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3222 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3223 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3224 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3225 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3226 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3227 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3228 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3229 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3230 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3231 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3232 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3233 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3234 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3235 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3236 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3237 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3238 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3239 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3240 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3241 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3242 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3243 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3244 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3245 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3246 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3247 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3248 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3249 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3250 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3251 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3252 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3253 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3254 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3255 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3256 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3257 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3258 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3259 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3260 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3261 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3262 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3263 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3264 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3265 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3266 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3267 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3268 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3269 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3270 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3271 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3272 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3273 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3274 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3275 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3276 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3277 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3278 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3279 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3280 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3281 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3282 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3283
AnnaBridge 146:22da6e220af6 3284 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 146:22da6e220af6 3285 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3286 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3287 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3288 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3289 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3290 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3291 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3292 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3293 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3294 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3295 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3296 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3297 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3298 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3299 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3300 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3301 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3302 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3303 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3304 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3305 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3306 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3307 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3308 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3309 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3310 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3311 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3312 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3313 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3314 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3315 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3316 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3317 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3318 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3319 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3320 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3321 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3322 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3323 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3324 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3325 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3326 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3327 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3328 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3329 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3330 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3331 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3332 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3333 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3334 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3335 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3336 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3337 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3338 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3339 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3340 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3341 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3342 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3343 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3344 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3345 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3346 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3347 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3348 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3349 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3350 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3351 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3352 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3353 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3354 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3355 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3356 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3357 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3358 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3359 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3360 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3361 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3362 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3363 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3364 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3365 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3366 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3367 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3368 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3369 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3370 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3371 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3372 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3373 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3374 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3375 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3376 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3377 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3378 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3379 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3380 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3381
AnnaBridge 146:22da6e220af6 3382 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 146:22da6e220af6 3383 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3384 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3385 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3386 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3387 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3388 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3389 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3390 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3391 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3392 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3393 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3394 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3395 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3396 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3397 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3398 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3399 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3400 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3401 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3402 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3403 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3404 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3405 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3406 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3407 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3408 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3409 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3410 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3411 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3412 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3413 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3414 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3415 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3416 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3417 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3418 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3419 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3420 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3421 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3422 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3423 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3424 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3425 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3426 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3427 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3428 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3429 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3430 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3431 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3432 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3433 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3434 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3435 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3436 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3437 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3438 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3439 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3440 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3441 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3442 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3443 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3444 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3445 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3446 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3447 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3448 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3449 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3450 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3451 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3452 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3453 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3454 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3455 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3456 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3457 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3458 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3459 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3460 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3461 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3462 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3463 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3464 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3465 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3466 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3467 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3468 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3469 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3470 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3471 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3472 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3473 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3474 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3475 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3476 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3477 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3478 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3479
AnnaBridge 146:22da6e220af6 3480 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 146:22da6e220af6 3481 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3482 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3483 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3484 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3485 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3486 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3487 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3488 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3489 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3490 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3491 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3492 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3493 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3494 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3495 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3496 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3497 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3498 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3499 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3500 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3501 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3502 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3503 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3504 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3505 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3506 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3507 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3508 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3509 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3510 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3511 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3512 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3513 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3514 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3515 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3516 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3517 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3518 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3519 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3520 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3521 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3522 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3523 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3524 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3525 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3526 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3527 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3528 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3529 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3530 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3531 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3532 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3533 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3534 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3535 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3536 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3537 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3538 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3539 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3540 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3541 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3542 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3543 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3544 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3545 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3546 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3547 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3548 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3549 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3550 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3551 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3552 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3553 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3554 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3555 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3556 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3557 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3558 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3559 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3560 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3561 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3562 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3563 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3564 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3565 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3566 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3567 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3568 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3569 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3570 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3571 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3572 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3573 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3574 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3575 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3576 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3577
AnnaBridge 146:22da6e220af6 3578 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 146:22da6e220af6 3579 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3580 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3581 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3582 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3583 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3584 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3585 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3586 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3587 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3588 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3589 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3590 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3591 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3592 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3593 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3594 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3595 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3596 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3597 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3598 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3599 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3600 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3601 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3602 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3603 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3604 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3605 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3606 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3607 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3608 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3609 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3610 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3611 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3612 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3613 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3614 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3615 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3616 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3617 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3618 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3619 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3620 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3621 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3622 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3623 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3624 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3625 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3626 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3627 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3628 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3629 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3630 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3631 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3632 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3633 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3634 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3635 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3636 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3637 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3638 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3639 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3640 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3641 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3642 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3643 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3644 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3645 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3646 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3647 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3648 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3649 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3650 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3651 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3652 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3653 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3654 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3655 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3656 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3657 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3658 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3659 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3660 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3661 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3662 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3663 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3664 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3665 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3666 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3667 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3668 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3669 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3670 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3671 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3672 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3673 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3674 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3675
AnnaBridge 146:22da6e220af6 3676 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 146:22da6e220af6 3677 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3678 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3679 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3680 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3681 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3682 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3683 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3684 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3685 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3686 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3687 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3688 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3689 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3690 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3691 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3692 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3693 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3694 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3695 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3696 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3697 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3698 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3699 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3700 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3701 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3702 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3703 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3704 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3705 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3706 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3707 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3708 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3709 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3710 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3711 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3712 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3713 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3714 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3715 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3716 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3717 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3718 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3719 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3720 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3721 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3722 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3723 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3724 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3725 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3726 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3727 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3728 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3729 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3730 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3731 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3732 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3733 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3734 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3735 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3736 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3737 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3738 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3739 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3740 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3741 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3742 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3743 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3744 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3745 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3746 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3747 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3748 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3749 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3750 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3751 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3752 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3753 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3754 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3755 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3756 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3757 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3758 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3759 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3760 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3761 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3762 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3763 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3764 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3765 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3766 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3767 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3768 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3769 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3770 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3771 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3772 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3773
AnnaBridge 146:22da6e220af6 3774 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 146:22da6e220af6 3775 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3776 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3777 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3778 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3779 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3780 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3781 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3782 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3783 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3784 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3785 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3786 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3787 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3788 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3789 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3790 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3791 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3792 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3793 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3794 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3795 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3796 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3797 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3798 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3799 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3800 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3801 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3802 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3803 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3804 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3805 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3806 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3807 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3808 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3809 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3810 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3811 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3812 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3813 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3814 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3815 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3816 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3817 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3818 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3819 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3820 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3821 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3822 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3823 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3824 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3825 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3826 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3827 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3828 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3829 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3830 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3831 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3832 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3833 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3834 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3835 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3836 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3837 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3838 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3839 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3840 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3841 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3842 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3843 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3844 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3845 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3846 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3847 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3848 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3849 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3850 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3851 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3852 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3853 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3854 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3855 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3856 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3857 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3858 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3859 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3860 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3861 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3862 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3863 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3864 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3865 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3866 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3867 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3868 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3869 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3870 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3871
AnnaBridge 146:22da6e220af6 3872 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 146:22da6e220af6 3873 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3874 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3875 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3876 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3877 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3878 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3879 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3880 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3881 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3882 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3883 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3884 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3885 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3886 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3887 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3888 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3889 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3890 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3891 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3892 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3893 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3894 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3895 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3896 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3897 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3898 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3899 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3900 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3901 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 3902 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 3903 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 3904 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 3905 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 3906 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 3907 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 3908 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 3909 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 3910 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 3911 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 3912 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 3913 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 3914 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 3915 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 3916 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 3917 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 3918 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 3919 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 3920 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 3921 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 3922 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 3923 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 3924 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 3925 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 3926 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 3927 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 3928 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 3929 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 3930 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 3931 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 3932 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 3933 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 3934 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 3935 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 3936 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 3937 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 3938 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 3939 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 3940 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 3941 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 3942 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 3943 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 3944 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 3945 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 3946 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 3947 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 3948 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 3949 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 3950 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 3951 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 3952 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 3953 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 3954 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 3955 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 3956 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 3957 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 3958 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 3959 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 3960 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 3961 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 3962 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 3963 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 3964 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 3965 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 3966 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 3967 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 3968 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 3969
AnnaBridge 146:22da6e220af6 3970 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 146:22da6e220af6 3971 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 3972 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 3973 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 3974 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 3975 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 3976 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 3977 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 3978 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 3979 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 3980 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 3981 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 3982 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 3983 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 3984 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 3985 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 3986 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 3987 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 3988 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 3989 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 3990 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 3991 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 3992 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 3993 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 3994 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 3995 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 3996 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 3997 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 3998 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 3999 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4000 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4001 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4002 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4003 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4004 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4005 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4006 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4007 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4008 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4009 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4010 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4011 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4012 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4013 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4014 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4015 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4016 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4017 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4018 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4019 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4020 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4021 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4022 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4023 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4024 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4025 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4026 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4027 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4028 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4029 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4030 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4031 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4032 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4033 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4034 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4035 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4036 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4037 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4038 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4039 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4040 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4041 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4042 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4043 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4044 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4045 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4046 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4047 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4048 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4049 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4050 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4051 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4052 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4053 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4054 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4055 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4056 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4057 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4058 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4059 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4060 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4061 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4062 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4063 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4064 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4065 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4066 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4067
AnnaBridge 146:22da6e220af6 4068 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 146:22da6e220af6 4069 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4070 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4071 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4072 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4073 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4074 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4075 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4076 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4077 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4078 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4079 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4080 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4081 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4082 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4083 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4084 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4085 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4086 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4087 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4088 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4089 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4090 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4091 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4092 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4093 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4094 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4095 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4096 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4097 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4098 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4099 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4100 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4101 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4102 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4103 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4104 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4105 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4106 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4107 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4108 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4109 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4110 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4111 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4112 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4113 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4114 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4115 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4116 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4117 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4118 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4119 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4120 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4121 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4122 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4123 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4124 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4125 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4126 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4127 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4128 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4129 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4130 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4131 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4132 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4133 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4134 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4135 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4136 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4137 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4138 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4139 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4140 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4141 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4142 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4143 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4144 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4145 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4146 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4147 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4148 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4149 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4150 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4151 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4152 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4153 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4154 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4155 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4156 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4157 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4158 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4159 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4160 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4161 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4162 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4163 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4164 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4165
AnnaBridge 146:22da6e220af6 4166 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 146:22da6e220af6 4167 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4168 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4169 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4170 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4171 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4172 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4173 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4174 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4175 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4176 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4177 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4178 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4179 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4180 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4181 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4182 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4183 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4184 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4185 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4186 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4187 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4188 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4189 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4190 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4191 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4192 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4193 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4194 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4195 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4196 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4197 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4198 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4199 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4200 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4201 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4202 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4203 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4204 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4205 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4206 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4207 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4208 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4209 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4210 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4211 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4212 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4213 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4214 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4215 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4216 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4217 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4218 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4219 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4220 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4221 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4222 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4223 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4224 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4225 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4226 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4227 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4228 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4229 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4230 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4231 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4232 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4233 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4234 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4235 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4236 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4237 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4238 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4239 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4240 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4241 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4242 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4243 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4244 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4245 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4246 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4247 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4248 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4249 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4250 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4251 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4252 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4253 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4254 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4255 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4256 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4257 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4258 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4259 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4260 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4261 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4262 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4263
AnnaBridge 146:22da6e220af6 4264 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 146:22da6e220af6 4265 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4266 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4267 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4268 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4269 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4270 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4271 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4272 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4273 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4274 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4275 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4276 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4277 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4278 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4279 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4280 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4281 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4282 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4283 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4284 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4285 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4286 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4287 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4288 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4289 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4290 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4291 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4292 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4293 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4294 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4295 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4296 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4297 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4298 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4299 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4300 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4301 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4302 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4303 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4304 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4305 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4306 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4307 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4308 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4309 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4310 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4311 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4312 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4313 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4314 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4315 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4316 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4317 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4318 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4319 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4320 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4321 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4322 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4323 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4324 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4325 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4326 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4327 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4328 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4329 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4330 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4331 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4332 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4333 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4334 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4335 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4336 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4337 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4338 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4339 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4340 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4341 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4342 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4343 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4344 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4345 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4346 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4347 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4348 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4349 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4350 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4351 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4352 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4353 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4354 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4355 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4356 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4357 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4358 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4359 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4360 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4361
AnnaBridge 146:22da6e220af6 4362 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 146:22da6e220af6 4363 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4364 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4365 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4366 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4367 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4368 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4369 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4370 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4371 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4372 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4373 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4374 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4375 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4376 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4377 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4378 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4379 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4380 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4381 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4382 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4383 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4384 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4385 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4386 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4387 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4388 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4389 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4390 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4391 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4392 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4393 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4394 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4395 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4396 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4397 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4398 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4399 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4400 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4401 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4402 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4403 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4404 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4405 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4406 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4407 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4408 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4409 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4410 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4411 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4412 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4413 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4414 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4415 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4416 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4417 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4418 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4419 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4420 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4421 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4422 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4423 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4424 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4425 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4426 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4427 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4428 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4429 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4430 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4431 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4432 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4433 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4434 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4435 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4436 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4437 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4438 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4439 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4440 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4441 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4442 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4443 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4444 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4445 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4446 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4447 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4448 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4449 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4450 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4451 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4452 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4453 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4454 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4455 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4456 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4457 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4458 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4459
AnnaBridge 146:22da6e220af6 4460 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 146:22da6e220af6 4461 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4462 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4463 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4464 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4465 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4466 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4467 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4468 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4469 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4470 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4471 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4472 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4473 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4474 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4475 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4476 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4477 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4478 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4479 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4480 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4481 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4482 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4483 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4484 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4485 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4486 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4487 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4488 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4489 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4490 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4491 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4492 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4493 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4494 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4495 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4496 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4497 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4498 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4499 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4500 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4501 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4502 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4503 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4504 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4505 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4506 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4507 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4508 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4509 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4510 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4511 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4512 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4513 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4514 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4515 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4516 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4517 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4518 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4519 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4520 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4521 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4522 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4523 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4524 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4525 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4526 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4527 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4528 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4529 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4530 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4531 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4532 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4533 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4534 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4535 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4536 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4537 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4538 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4539 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4540 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4541 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4542 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4543 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4544 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4545 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4546 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4547 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4548 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4549 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4550 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4551 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4552 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4553 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4554 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4555 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4556 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4557
AnnaBridge 146:22da6e220af6 4558 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 146:22da6e220af6 4559 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4560 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4561 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4562 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4563 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4564 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4565 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4566 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4567 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4568 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4569 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4570 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4571 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4572 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4573 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4574 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4575 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4576 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4577 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4578 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4579 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4580 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4581 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4582 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4583 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4584 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4585 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4586 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4587 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4588 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4589 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4590 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4591 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4592 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4593 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4594 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4595 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4596 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4597 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4598 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4599 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4600 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4601 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4602 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4603 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4604 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4605 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4606 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4607 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4608 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4609 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4610 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4611 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4612 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4613 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4614 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4615 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4616 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4617 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4618 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4619 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4620 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4621 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4622 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4623 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4624 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4625 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4626 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4627 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4628 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4629 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4630 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4631 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4632 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4633 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4634 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4635 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4636 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4637 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4638 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4639 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4640 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4641 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4642 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4643 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4644 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4645 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4646 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4647 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4648 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4649 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4650 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4651 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4652 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4653 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4654 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4655
AnnaBridge 146:22da6e220af6 4656 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 146:22da6e220af6 4657 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4658 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4659 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4660 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4661 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4662 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4663 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4664 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4665 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4666 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4667 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4668 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4669 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4670 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4671 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4672 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4673 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4674 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4675 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4676 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4677 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4678 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4679 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4680 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4681 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4682 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4683 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4684 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4685 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4686 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4687 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4688 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4689 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4690 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4691 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4692 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4693 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4694 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4695 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4696 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4697 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4698 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4699 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4700 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4701 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4702 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4703 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4704 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4705 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4706 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4707 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4708 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4709 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4710 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4711 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4712 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4713 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4714 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4715 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4716 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4717 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4718 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4719 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4720 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4721 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4722 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4723 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4724 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4725 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4726 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4727 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4728 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4729 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4730 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4731 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4732 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4733 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4734 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4735 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4736 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4737 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4738 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4739 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4740 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4741 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4742 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4743 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4744 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4745 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4746 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4747 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4748 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4749 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4750 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4751 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4752 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4753
AnnaBridge 146:22da6e220af6 4754 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 146:22da6e220af6 4755 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4756 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4757 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4758 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4759 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4760 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4761 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4762 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4763 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4764 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4765 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4766 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4767 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4768 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4769 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4770 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4771 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4772 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4773 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4774 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4775 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4776 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4777 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4778 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4779 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4780 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4781 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4782 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4783 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4784 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4785 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4786 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4787 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4788 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4789 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4790 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4791 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4792 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4793 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4794 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4795 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4796 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4797 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4798 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4799 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4800 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4801 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4802 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4803 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4804 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4805 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4806 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4807 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4808 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4809 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4810 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4811 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4812 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4813 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4814 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4815 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4816 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4817 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4818 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4819 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4820 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4821 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4822 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4823 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4824 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4825 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4826 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4827 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4828 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4829 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4830 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4831 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4832 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4833 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4834 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4835 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4836 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4837 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4838 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4839 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4840 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4841 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4842 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4843 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4844 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4845 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4846 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4847 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4848 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4849 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4850 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4851
AnnaBridge 146:22da6e220af6 4852 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 146:22da6e220af6 4853 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4854 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4855 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4856 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4857 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4858 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4859 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4860 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4861 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4862 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4863 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4864 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4865 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4866 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4867 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4868 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4869 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4870 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4871 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4872 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4873 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4874 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4875 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4876 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4877 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4878 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4879 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4880 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4881 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4882 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4883 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4884 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4885 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4886 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4887 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4888 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4889 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4890 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4891 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4892 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4893 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4894 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4895 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4896 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4897 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4898 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4899 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4900 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4901 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 4902 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 4903 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 4904 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 4905 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 4906 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 4907 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 4908 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 4909 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 4910 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 4911 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 4912 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 4913 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 4914 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 4915 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 4916 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 4917 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 4918 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 4919 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 4920 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 4921 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 4922 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 4923 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 4924 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 4925 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 4926 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 4927 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 4928 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 4929 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 4930 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 4931 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 4932 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 4933 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 4934 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 4935 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 4936 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 4937 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 4938 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 4939 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 4940 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 4941 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 4942 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 4943 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 4944 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 4945 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 4946 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 4947 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 4948 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 4949
AnnaBridge 146:22da6e220af6 4950 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 146:22da6e220af6 4951 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 4952 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 4953 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 4954 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 4955 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 4956 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 4957 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 4958 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 4959 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 4960 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 4961 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 4962 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 4963 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 4964 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 4965 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 4966 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 4967 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 4968 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 4969 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 4970 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 4971 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 4972 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 4973 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 4974 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 4975 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 4976 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 4977 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 4978 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 4979 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 4980 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 4981 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 4982 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 4983 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 4984 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 4985 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 4986 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 4987 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 4988 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 4989 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 4990 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 4991 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 4992 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 4993 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 4994 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 4995 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 4996 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 4997 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 4998 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 4999 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 5000 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5001 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 5002 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 5003 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5004 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 5005 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 5006 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5007 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 5008 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 5009 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5010 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 5011 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 5012 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5013 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 5014 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 5015 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5016 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 5017 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 5018 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5019 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 5020 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 5021 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5022 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 5023 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 5024 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5025 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 5026 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 5027 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5028 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 5029 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 5030 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5031 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 5032 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 5033 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5034 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 5035 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 5036 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5037 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 5038 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 5039 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5040 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 5041 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 5042 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5043 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 5044 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 5045 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5046 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 5047
AnnaBridge 146:22da6e220af6 5048 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 146:22da6e220af6 5049 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 5050 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5051 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 5052 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 5053 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5054 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 5055 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 5056 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5057 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 5058 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 5059 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5060 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 5061 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 5062 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5063 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 5064 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 5065 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5066 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 5067 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 5068 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5069 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 5070 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 5071 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5072 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 5073 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 5074 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5075 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 5076 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 5077 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5078 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 5079 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 5080 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5081 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 5082 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 5083 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5084 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 5085 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 5086 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5087 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 5088 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 5089 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5090 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 5091 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 5092 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5093 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 5094 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 5095 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5096 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 5097 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 5098 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5099 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 5100 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 5101 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5102 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 5103 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 5104 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5105 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 5106 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 5107 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5108 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 5109 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 5110 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5111 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 5112 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 5113 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5114 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 5115 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 5116 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5117 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 5118 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 5119 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5120 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 5121 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 5122 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5123 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 5124 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 5125 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5126 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 5127 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 5128 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5129 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 5130 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 5131 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5132 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 5133 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 5134 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5135 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 5136 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 5137 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5138 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 5139 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 5140 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5141 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 5142 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 5143 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5144 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 5145
AnnaBridge 146:22da6e220af6 5146 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 146:22da6e220af6 5147 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 5148 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5149 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 5150 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 5151 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5152 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 5153 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 5154 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5155 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 5156 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 5157 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5158 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 5159 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 5160 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5161 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 5162 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 5163 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5164 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 5165 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 5166 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5167 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 5168 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 5169 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5170 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 5171 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 5172 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5173 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 5174 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 5175 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5176 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 5177 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 5178 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5179 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 5180 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 5181 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5182 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 5183 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 5184 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5185 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 5186 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 5187 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5188 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 5189 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 5190 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5191 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 5192 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 5193 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5194 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 5195 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 5196 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5197 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 5198 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 5199 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5200 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 5201 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 5202 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5203 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 5204 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 5205 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5206 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 5207 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 5208 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5209 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 5210 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 5211 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5212 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 5213 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 5214 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5215 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 5216 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 5217 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5218 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 5219 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 5220 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5221 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 5222 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 5223 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5224 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 5225 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 5226 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5227 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 5228 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 5229 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5230 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 5231 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 5232 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5233 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 5234 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 5235 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5236 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 5237 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 5238 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5239 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 5240 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 5241 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5242 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 5243
AnnaBridge 146:22da6e220af6 5244 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 146:22da6e220af6 5245 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 5246 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5247 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 5248 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 5249 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5250 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 5251 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 5252 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5253 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 5254 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 5255 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5256 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 5257 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 5258 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5259 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 5260 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 5261 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5262 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 5263 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 5264 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5265 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 5266 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 5267 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5268 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 5269 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 5270 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5271 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 5272 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 5273 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5274 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 5275 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 5276 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5277 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 5278 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 5279 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5280 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 5281 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 5282 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5283 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 5284 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 5285 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5286 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 5287 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 5288 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5289 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 5290 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 5291 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5292 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 5293 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 5294 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5295 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 5296 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 5297 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5298 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 5299 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 5300 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5301 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 5302 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 5303 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5304 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 5305 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 5306 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5307 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 5308 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 5309 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5310 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 5311 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 5312 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5313 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 5314 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 5315 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5316 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 5317 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 5318 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5319 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 5320 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 5321 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5322 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 5323 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 5324 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5325 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 5326 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 5327 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5328 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 5329 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 5330 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5331 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 5332 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 5333 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5334 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 5335 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 5336 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5337 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 5338 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 5339 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5340 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 5341
AnnaBridge 146:22da6e220af6 5342 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 146:22da6e220af6 5343 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 146:22da6e220af6 5344 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5345 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 146:22da6e220af6 5346 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 146:22da6e220af6 5347 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5348 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 146:22da6e220af6 5349 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 146:22da6e220af6 5350 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5351 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 146:22da6e220af6 5352 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 146:22da6e220af6 5353 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5354 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 146:22da6e220af6 5355 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 146:22da6e220af6 5356 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5357 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 146:22da6e220af6 5358 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 146:22da6e220af6 5359 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5360 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 146:22da6e220af6 5361 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 146:22da6e220af6 5362 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5363 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 146:22da6e220af6 5364 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 146:22da6e220af6 5365 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5366 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 146:22da6e220af6 5367 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 146:22da6e220af6 5368 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5369 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 146:22da6e220af6 5370 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 146:22da6e220af6 5371 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5372 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 146:22da6e220af6 5373 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 146:22da6e220af6 5374 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5375 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 146:22da6e220af6 5376 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 146:22da6e220af6 5377 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5378 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 146:22da6e220af6 5379 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 146:22da6e220af6 5380 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5381 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 146:22da6e220af6 5382 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 146:22da6e220af6 5383 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5384 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 146:22da6e220af6 5385 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 146:22da6e220af6 5386 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5387 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 146:22da6e220af6 5388 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 146:22da6e220af6 5389 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5390 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 146:22da6e220af6 5391 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 146:22da6e220af6 5392 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5393 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 146:22da6e220af6 5394 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 146:22da6e220af6 5395 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5396 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 146:22da6e220af6 5397 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 146:22da6e220af6 5398 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5399 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 146:22da6e220af6 5400 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 146:22da6e220af6 5401 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5402 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 146:22da6e220af6 5403 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 146:22da6e220af6 5404 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5405 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 146:22da6e220af6 5406 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 146:22da6e220af6 5407 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5408 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 146:22da6e220af6 5409 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 146:22da6e220af6 5410 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5411 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 146:22da6e220af6 5412 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 146:22da6e220af6 5413 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5414 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 146:22da6e220af6 5415 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 146:22da6e220af6 5416 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5417 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 146:22da6e220af6 5418 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 146:22da6e220af6 5419 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5420 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 146:22da6e220af6 5421 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 146:22da6e220af6 5422 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5423 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 146:22da6e220af6 5424 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 146:22da6e220af6 5425 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5426 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 146:22da6e220af6 5427 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 146:22da6e220af6 5428 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5429 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 146:22da6e220af6 5430 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 146:22da6e220af6 5431 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5432 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 146:22da6e220af6 5433 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 146:22da6e220af6 5434 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5435 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 146:22da6e220af6 5436 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 146:22da6e220af6 5437 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5438 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 146:22da6e220af6 5439
AnnaBridge 146:22da6e220af6 5440 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5441 /* */
AnnaBridge 146:22da6e220af6 5442 /* CRC calculation unit */
AnnaBridge 146:22da6e220af6 5443 /* */
AnnaBridge 146:22da6e220af6 5444 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5445 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 146:22da6e220af6 5446 #define CRC_DR_DR_Pos (0U)
AnnaBridge 146:22da6e220af6 5447 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 5448 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 146:22da6e220af6 5449
AnnaBridge 146:22da6e220af6 5450
AnnaBridge 146:22da6e220af6 5451 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 146:22da6e220af6 5452 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 146:22da6e220af6 5453 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5454 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 146:22da6e220af6 5455
AnnaBridge 146:22da6e220af6 5456
AnnaBridge 146:22da6e220af6 5457 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 146:22da6e220af6 5458 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 146:22da6e220af6 5459 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5460 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 146:22da6e220af6 5461
AnnaBridge 146:22da6e220af6 5462 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5463 /* */
AnnaBridge 146:22da6e220af6 5464 /* Digital to Analog Converter */
AnnaBridge 146:22da6e220af6 5465 /* */
AnnaBridge 146:22da6e220af6 5466 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5467 /*
AnnaBridge 146:22da6e220af6 5468 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 5469 */
AnnaBridge 146:22da6e220af6 5470 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
AnnaBridge 146:22da6e220af6 5471 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 146:22da6e220af6 5472 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 146:22da6e220af6 5473 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5474 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 146:22da6e220af6 5475 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 146:22da6e220af6 5476 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5477 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 146:22da6e220af6 5478 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 146:22da6e220af6 5479 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5480 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 146:22da6e220af6 5481
AnnaBridge 146:22da6e220af6 5482 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 146:22da6e220af6 5483 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 146:22da6e220af6 5484 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 146:22da6e220af6 5485 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5486 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5487 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5488
AnnaBridge 146:22da6e220af6 5489 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 146:22da6e220af6 5490 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 5491 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 146:22da6e220af6 5492 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5493 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5494
AnnaBridge 146:22da6e220af6 5495 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 146:22da6e220af6 5496 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 5497 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 146:22da6e220af6 5498 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5499 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5500 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5501 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5502
AnnaBridge 146:22da6e220af6 5503 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 146:22da6e220af6 5504 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5505 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 146:22da6e220af6 5506 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 146:22da6e220af6 5507 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5508 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
AnnaBridge 146:22da6e220af6 5509 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 146:22da6e220af6 5510 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5511 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 146:22da6e220af6 5512 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 146:22da6e220af6 5513 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5514 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 146:22da6e220af6 5515 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 146:22da6e220af6 5516 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5517 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 146:22da6e220af6 5518
AnnaBridge 146:22da6e220af6 5519 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 146:22da6e220af6 5520 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 146:22da6e220af6 5521 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 146:22da6e220af6 5522 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5523 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 5524 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5525
AnnaBridge 146:22da6e220af6 5526 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 146:22da6e220af6 5527 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 5528 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 146:22da6e220af6 5529 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5530 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5531
AnnaBridge 146:22da6e220af6 5532 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 146:22da6e220af6 5533 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 5534 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 146:22da6e220af6 5535 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5536 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 5537 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 5538 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 5539
AnnaBridge 146:22da6e220af6 5540 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 146:22da6e220af6 5541 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 5542 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 146:22da6e220af6 5543 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 146:22da6e220af6 5544 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5545 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
AnnaBridge 146:22da6e220af6 5546
AnnaBridge 146:22da6e220af6 5547 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 146:22da6e220af6 5548 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 146:22da6e220af6 5549 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5550 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 146:22da6e220af6 5551 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 146:22da6e220af6 5552 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5553 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 146:22da6e220af6 5554
AnnaBridge 146:22da6e220af6 5555 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 146:22da6e220af6 5556 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5557 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 5558 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5559
AnnaBridge 146:22da6e220af6 5560 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 146:22da6e220af6 5561 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 146:22da6e220af6 5562 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 146:22da6e220af6 5563 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 146:22da6e220af6 5564
AnnaBridge 146:22da6e220af6 5565 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 146:22da6e220af6 5566 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5567 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5568 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5569
AnnaBridge 146:22da6e220af6 5570 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 146:22da6e220af6 5571 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5572 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 5573 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5574
AnnaBridge 146:22da6e220af6 5575 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 146:22da6e220af6 5576 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 146:22da6e220af6 5577 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 146:22da6e220af6 5578 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 146:22da6e220af6 5579
AnnaBridge 146:22da6e220af6 5580 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 146:22da6e220af6 5581 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5582 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5583 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5584
AnnaBridge 146:22da6e220af6 5585 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 146:22da6e220af6 5586 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5587 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 5588 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5589 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 146:22da6e220af6 5590 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 146:22da6e220af6 5591 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5592
AnnaBridge 146:22da6e220af6 5593 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 146:22da6e220af6 5594 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 146:22da6e220af6 5595 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 146:22da6e220af6 5596 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 146:22da6e220af6 5597 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 146:22da6e220af6 5598 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 146:22da6e220af6 5599 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 146:22da6e220af6 5600
AnnaBridge 146:22da6e220af6 5601 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 146:22da6e220af6 5602 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 146:22da6e220af6 5603 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5604 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5605 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 146:22da6e220af6 5606 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 5607 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 146:22da6e220af6 5608
AnnaBridge 146:22da6e220af6 5609 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 146:22da6e220af6 5610 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 146:22da6e220af6 5611 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 5612 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 146:22da6e220af6 5613
AnnaBridge 146:22da6e220af6 5614 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 146:22da6e220af6 5615 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 146:22da6e220af6 5616 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 5617 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 146:22da6e220af6 5618
AnnaBridge 146:22da6e220af6 5619 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 146:22da6e220af6 5620 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 146:22da6e220af6 5621 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5622 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 146:22da6e220af6 5623 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 146:22da6e220af6 5624 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5625 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 146:22da6e220af6 5626
AnnaBridge 146:22da6e220af6 5627 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5628 /* */
AnnaBridge 146:22da6e220af6 5629 /* Digital Filter for Sigma Delta Modulators */
AnnaBridge 146:22da6e220af6 5630 /* */
AnnaBridge 146:22da6e220af6 5631 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5632
AnnaBridge 146:22da6e220af6 5633 /**************** DFSDM channel configuration registers ********************/
AnnaBridge 146:22da6e220af6 5634
AnnaBridge 146:22da6e220af6 5635 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
AnnaBridge 146:22da6e220af6 5636 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
AnnaBridge 146:22da6e220af6 5637 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5638 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
AnnaBridge 146:22da6e220af6 5639 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
AnnaBridge 146:22da6e220af6 5640 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5641 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
AnnaBridge 146:22da6e220af6 5642 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
AnnaBridge 146:22da6e220af6 5643 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 5644 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
AnnaBridge 146:22da6e220af6 5645 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
AnnaBridge 146:22da6e220af6 5646 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 5647 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
AnnaBridge 146:22da6e220af6 5648 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5649 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5650 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
AnnaBridge 146:22da6e220af6 5651 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 5652 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
AnnaBridge 146:22da6e220af6 5653 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5654 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5655 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
AnnaBridge 146:22da6e220af6 5656 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5657 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
AnnaBridge 146:22da6e220af6 5658 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
AnnaBridge 146:22da6e220af6 5659 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5660 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
AnnaBridge 146:22da6e220af6 5661 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
AnnaBridge 146:22da6e220af6 5662 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5663 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
AnnaBridge 146:22da6e220af6 5664 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
AnnaBridge 146:22da6e220af6 5665 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5666 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
AnnaBridge 146:22da6e220af6 5667 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
AnnaBridge 146:22da6e220af6 5668 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 5669 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
AnnaBridge 146:22da6e220af6 5670 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5671 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5672 #define DFSDM_CHCFGR1_SITP_Pos (0U)
AnnaBridge 146:22da6e220af6 5673 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 5674 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
AnnaBridge 146:22da6e220af6 5675 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5676 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5677
AnnaBridge 146:22da6e220af6 5678 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
AnnaBridge 146:22da6e220af6 5679 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
AnnaBridge 146:22da6e220af6 5680 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5681 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
AnnaBridge 146:22da6e220af6 5682 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
AnnaBridge 146:22da6e220af6 5683 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
AnnaBridge 146:22da6e220af6 5684 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
AnnaBridge 146:22da6e220af6 5685
AnnaBridge 146:22da6e220af6 5686 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
AnnaBridge 146:22da6e220af6 5687 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
AnnaBridge 146:22da6e220af6 5688 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 5689 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
AnnaBridge 146:22da6e220af6 5690 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5691 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5692 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
AnnaBridge 146:22da6e220af6 5693 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
AnnaBridge 146:22da6e220af6 5694 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
AnnaBridge 146:22da6e220af6 5695 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
AnnaBridge 146:22da6e220af6 5696 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 5697 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
AnnaBridge 146:22da6e220af6 5698 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
AnnaBridge 146:22da6e220af6 5699 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5700 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
AnnaBridge 146:22da6e220af6 5701
AnnaBridge 146:22da6e220af6 5702 /**************** Bit definition for DFSDM_CHWDATR register *******************/
AnnaBridge 146:22da6e220af6 5703 #define DFSDM_CHWDATR_WDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 5704 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 5705 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
AnnaBridge 146:22da6e220af6 5706
AnnaBridge 146:22da6e220af6 5707 /**************** Bit definition for DFSDM_CHDATINR register *****************/
AnnaBridge 146:22da6e220af6 5708 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
AnnaBridge 146:22da6e220af6 5709 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 5710 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
AnnaBridge 146:22da6e220af6 5711 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
AnnaBridge 146:22da6e220af6 5712 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 5713 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
AnnaBridge 146:22da6e220af6 5714
AnnaBridge 146:22da6e220af6 5715 /************************ DFSDM module registers ****************************/
AnnaBridge 146:22da6e220af6 5716
AnnaBridge 146:22da6e220af6 5717 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
AnnaBridge 146:22da6e220af6 5718 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
AnnaBridge 146:22da6e220af6 5719 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5720 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
AnnaBridge 146:22da6e220af6 5721 #define DFSDM_FLTCR1_FAST_Pos (29U)
AnnaBridge 146:22da6e220af6 5722 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5723 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
AnnaBridge 146:22da6e220af6 5724 #define DFSDM_FLTCR1_RCH_Pos (24U)
AnnaBridge 146:22da6e220af6 5725 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
AnnaBridge 146:22da6e220af6 5726 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
AnnaBridge 146:22da6e220af6 5727 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
AnnaBridge 146:22da6e220af6 5728 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5729 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
AnnaBridge 146:22da6e220af6 5730 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
AnnaBridge 146:22da6e220af6 5731 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5732 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
AnnaBridge 146:22da6e220af6 5733 #define DFSDM_FLTCR1_RCONT_Pos (18U)
AnnaBridge 146:22da6e220af6 5734 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5735 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
AnnaBridge 146:22da6e220af6 5736 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
AnnaBridge 146:22da6e220af6 5737 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5738 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
AnnaBridge 146:22da6e220af6 5739 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
AnnaBridge 146:22da6e220af6 5740 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
AnnaBridge 146:22da6e220af6 5741 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
AnnaBridge 146:22da6e220af6 5742 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5743 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5744 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
AnnaBridge 146:22da6e220af6 5745 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
AnnaBridge 146:22da6e220af6 5746 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
AnnaBridge 146:22da6e220af6 5747 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5748 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5749 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5750 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
AnnaBridge 146:22da6e220af6 5751 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5752 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
AnnaBridge 146:22da6e220af6 5753 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
AnnaBridge 146:22da6e220af6 5754 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5755 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
AnnaBridge 146:22da6e220af6 5756 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
AnnaBridge 146:22da6e220af6 5757 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5758 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
AnnaBridge 146:22da6e220af6 5759 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
AnnaBridge 146:22da6e220af6 5760 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5761 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
AnnaBridge 146:22da6e220af6 5762 #define DFSDM_FLTCR1_DFEN_Pos (0U)
AnnaBridge 146:22da6e220af6 5763 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5764 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
AnnaBridge 146:22da6e220af6 5765
AnnaBridge 146:22da6e220af6 5766 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
AnnaBridge 146:22da6e220af6 5767 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
AnnaBridge 146:22da6e220af6 5768 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 5769 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
AnnaBridge 146:22da6e220af6 5770 #define DFSDM_FLTCR2_EXCH_Pos (8U)
AnnaBridge 146:22da6e220af6 5771 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 5772 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
AnnaBridge 146:22da6e220af6 5773 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
AnnaBridge 146:22da6e220af6 5774 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5775 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
AnnaBridge 146:22da6e220af6 5776 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
AnnaBridge 146:22da6e220af6 5777 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5778 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
AnnaBridge 146:22da6e220af6 5779 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
AnnaBridge 146:22da6e220af6 5780 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5781 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
AnnaBridge 146:22da6e220af6 5782 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
AnnaBridge 146:22da6e220af6 5783 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5784 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
AnnaBridge 146:22da6e220af6 5785 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
AnnaBridge 146:22da6e220af6 5786 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5787 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
AnnaBridge 146:22da6e220af6 5788 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
AnnaBridge 146:22da6e220af6 5789 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5790 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
AnnaBridge 146:22da6e220af6 5791 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
AnnaBridge 146:22da6e220af6 5792 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5793 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
AnnaBridge 146:22da6e220af6 5794
AnnaBridge 146:22da6e220af6 5795 /***************** Bit definition for DFSDM_FLTISR register *******************/
AnnaBridge 146:22da6e220af6 5796 #define DFSDM_FLTISR_SCDF_Pos (24U)
AnnaBridge 146:22da6e220af6 5797 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 5798 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
AnnaBridge 146:22da6e220af6 5799 #define DFSDM_FLTISR_CKABF_Pos (16U)
AnnaBridge 146:22da6e220af6 5800 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 5801 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
AnnaBridge 146:22da6e220af6 5802 #define DFSDM_FLTISR_RCIP_Pos (14U)
AnnaBridge 146:22da6e220af6 5803 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5804 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
AnnaBridge 146:22da6e220af6 5805 #define DFSDM_FLTISR_JCIP_Pos (13U)
AnnaBridge 146:22da6e220af6 5806 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5807 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
AnnaBridge 146:22da6e220af6 5808 #define DFSDM_FLTISR_AWDF_Pos (4U)
AnnaBridge 146:22da6e220af6 5809 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5810 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
AnnaBridge 146:22da6e220af6 5811 #define DFSDM_FLTISR_ROVRF_Pos (3U)
AnnaBridge 146:22da6e220af6 5812 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5813 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
AnnaBridge 146:22da6e220af6 5814 #define DFSDM_FLTISR_JOVRF_Pos (2U)
AnnaBridge 146:22da6e220af6 5815 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5816 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
AnnaBridge 146:22da6e220af6 5817 #define DFSDM_FLTISR_REOCF_Pos (1U)
AnnaBridge 146:22da6e220af6 5818 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 5819 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
AnnaBridge 146:22da6e220af6 5820 #define DFSDM_FLTISR_JEOCF_Pos (0U)
AnnaBridge 146:22da6e220af6 5821 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 5822 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
AnnaBridge 146:22da6e220af6 5823
AnnaBridge 146:22da6e220af6 5824 /***************** Bit definition for DFSDM_FLTICR register *******************/
AnnaBridge 146:22da6e220af6 5825 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
AnnaBridge 146:22da6e220af6 5826 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 5827 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
AnnaBridge 146:22da6e220af6 5828 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
AnnaBridge 146:22da6e220af6 5829 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 5830 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
AnnaBridge 146:22da6e220af6 5831 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
AnnaBridge 146:22da6e220af6 5832 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5833 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
AnnaBridge 146:22da6e220af6 5834 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
AnnaBridge 146:22da6e220af6 5835 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 5836 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
AnnaBridge 146:22da6e220af6 5837
AnnaBridge 146:22da6e220af6 5838 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
AnnaBridge 146:22da6e220af6 5839 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
AnnaBridge 146:22da6e220af6 5840 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5841 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
AnnaBridge 146:22da6e220af6 5842
AnnaBridge 146:22da6e220af6 5843 /***************** Bit definition for DFSDM_FLTFCR register *******************/
AnnaBridge 146:22da6e220af6 5844 #define DFSDM_FLTFCR_FORD_Pos (29U)
AnnaBridge 146:22da6e220af6 5845 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
AnnaBridge 146:22da6e220af6 5846 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
AnnaBridge 146:22da6e220af6 5847 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 5848 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 5849 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 5850 #define DFSDM_FLTFCR_FOSR_Pos (16U)
AnnaBridge 146:22da6e220af6 5851 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
AnnaBridge 146:22da6e220af6 5852 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
AnnaBridge 146:22da6e220af6 5853 #define DFSDM_FLTFCR_IOSR_Pos (0U)
AnnaBridge 146:22da6e220af6 5854 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5855 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
AnnaBridge 146:22da6e220af6 5856
AnnaBridge 146:22da6e220af6 5857 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
AnnaBridge 146:22da6e220af6 5858 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
AnnaBridge 146:22da6e220af6 5859 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5860 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
AnnaBridge 146:22da6e220af6 5861 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
AnnaBridge 146:22da6e220af6 5862 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 5863 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
AnnaBridge 146:22da6e220af6 5864
AnnaBridge 146:22da6e220af6 5865 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
AnnaBridge 146:22da6e220af6 5866 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
AnnaBridge 146:22da6e220af6 5867 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5868 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
AnnaBridge 146:22da6e220af6 5869 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
AnnaBridge 146:22da6e220af6 5870 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5871 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
AnnaBridge 146:22da6e220af6 5872 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
AnnaBridge 146:22da6e220af6 5873 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 5874 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
AnnaBridge 146:22da6e220af6 5875
AnnaBridge 146:22da6e220af6 5876 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
AnnaBridge 146:22da6e220af6 5877 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
AnnaBridge 146:22da6e220af6 5878 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5879 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
AnnaBridge 146:22da6e220af6 5880 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
AnnaBridge 146:22da6e220af6 5881 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 5882 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
AnnaBridge 146:22da6e220af6 5883
AnnaBridge 146:22da6e220af6 5884 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
AnnaBridge 146:22da6e220af6 5885 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
AnnaBridge 146:22da6e220af6 5886 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5887 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
AnnaBridge 146:22da6e220af6 5888 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
AnnaBridge 146:22da6e220af6 5889 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 5890 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
AnnaBridge 146:22da6e220af6 5891
AnnaBridge 146:22da6e220af6 5892 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
AnnaBridge 146:22da6e220af6 5893 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
AnnaBridge 146:22da6e220af6 5894 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 5895 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
AnnaBridge 146:22da6e220af6 5896 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
AnnaBridge 146:22da6e220af6 5897 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5898 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
AnnaBridge 146:22da6e220af6 5899
AnnaBridge 146:22da6e220af6 5900
AnnaBridge 146:22da6e220af6 5901 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
AnnaBridge 146:22da6e220af6 5902 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
AnnaBridge 146:22da6e220af6 5903 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 5904 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
AnnaBridge 146:22da6e220af6 5905 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
AnnaBridge 146:22da6e220af6 5906 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 5907 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
AnnaBridge 146:22da6e220af6 5908
AnnaBridge 146:22da6e220af6 5909 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
AnnaBridge 146:22da6e220af6 5910 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
AnnaBridge 146:22da6e220af6 5911 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5912 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
AnnaBridge 146:22da6e220af6 5913 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
AnnaBridge 146:22da6e220af6 5914 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 5915 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
AnnaBridge 146:22da6e220af6 5916
AnnaBridge 146:22da6e220af6 5917 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
AnnaBridge 146:22da6e220af6 5918 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
AnnaBridge 146:22da6e220af6 5919 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 146:22da6e220af6 5920 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
AnnaBridge 146:22da6e220af6 5921 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
AnnaBridge 146:22da6e220af6 5922 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 5923 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
AnnaBridge 146:22da6e220af6 5924
AnnaBridge 146:22da6e220af6 5925 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
AnnaBridge 146:22da6e220af6 5926 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
AnnaBridge 146:22da6e220af6 5927 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
AnnaBridge 146:22da6e220af6 5928 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
AnnaBridge 146:22da6e220af6 5929
AnnaBridge 146:22da6e220af6 5930 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5931 /* */
AnnaBridge 146:22da6e220af6 5932 /* DMA Controller */
AnnaBridge 146:22da6e220af6 5933 /* */
AnnaBridge 146:22da6e220af6 5934 /******************************************************************************/
AnnaBridge 146:22da6e220af6 5935 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 146:22da6e220af6 5936 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 146:22da6e220af6 5937 #define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
AnnaBridge 146:22da6e220af6 5938 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 146:22da6e220af6 5939 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 146:22da6e220af6 5940 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 146:22da6e220af6 5941 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 146:22da6e220af6 5942 #define DMA_SxCR_CHSEL_3 0x10000000U
AnnaBridge 146:22da6e220af6 5943 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 146:22da6e220af6 5944 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 146:22da6e220af6 5945 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 146:22da6e220af6 5946 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 5947 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 5948 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 146:22da6e220af6 5949 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 146:22da6e220af6 5950 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 146:22da6e220af6 5951 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 5952 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 5953 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 146:22da6e220af6 5954 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 5955 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 146:22da6e220af6 5956 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 146:22da6e220af6 5957 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 5958 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 146:22da6e220af6 5959 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 146:22da6e220af6 5960 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 5961 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 146:22da6e220af6 5962 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 5963 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 5964 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 146:22da6e220af6 5965 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 5966 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 146:22da6e220af6 5967 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 146:22da6e220af6 5968 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 146:22da6e220af6 5969 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 146:22da6e220af6 5970 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 5971 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 5972 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 146:22da6e220af6 5973 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 146:22da6e220af6 5974 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 146:22da6e220af6 5975 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 5976 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 5977 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 146:22da6e220af6 5978 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 5979 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 146:22da6e220af6 5980 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 146:22da6e220af6 5981 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 5982 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 146:22da6e220af6 5983 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 146:22da6e220af6 5984 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 5985 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 146:22da6e220af6 5986 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 146:22da6e220af6 5987 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 5988 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 146:22da6e220af6 5989 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 5990 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 5991 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 146:22da6e220af6 5992 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 5993 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 146:22da6e220af6 5994 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 146:22da6e220af6 5995 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 5996 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 146:22da6e220af6 5997 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 146:22da6e220af6 5998 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 5999 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 146:22da6e220af6 6000 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 146:22da6e220af6 6001 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6002 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 146:22da6e220af6 6003 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 146:22da6e220af6 6004 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6005 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 146:22da6e220af6 6006 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 146:22da6e220af6 6007 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6008 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 146:22da6e220af6 6009
AnnaBridge 146:22da6e220af6 6010 /* Legacy defines */
AnnaBridge 146:22da6e220af6 6011 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 146:22da6e220af6 6012 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6013 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
AnnaBridge 146:22da6e220af6 6014
AnnaBridge 146:22da6e220af6 6015 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 146:22da6e220af6 6016 #define DMA_SxNDT_Pos (0U)
AnnaBridge 146:22da6e220af6 6017 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 6018 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 146:22da6e220af6 6019 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6020 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6021 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6022 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6023 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6024 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6025 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6026 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6027 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6028 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6029 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6030 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6031 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6032 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6033 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6034 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6035
AnnaBridge 146:22da6e220af6 6036 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 146:22da6e220af6 6037 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 146:22da6e220af6 6038 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6039 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 146:22da6e220af6 6040 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 146:22da6e220af6 6041 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 146:22da6e220af6 6042 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 146:22da6e220af6 6043 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6044 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6045 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6046 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 146:22da6e220af6 6047 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6048 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 146:22da6e220af6 6049 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 146:22da6e220af6 6050 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 6051 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 146:22da6e220af6 6052 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6053 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6054
AnnaBridge 146:22da6e220af6 6055 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 146:22da6e220af6 6056 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 146:22da6e220af6 6057 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 6058 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 146:22da6e220af6 6059 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 146:22da6e220af6 6060 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 6061 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 146:22da6e220af6 6062 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 146:22da6e220af6 6063 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 6064 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 146:22da6e220af6 6065 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 146:22da6e220af6 6066 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6067 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 146:22da6e220af6 6068 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 146:22da6e220af6 6069 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6070 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 146:22da6e220af6 6071 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 146:22da6e220af6 6072 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6073 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 146:22da6e220af6 6074 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 146:22da6e220af6 6075 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6076 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 146:22da6e220af6 6077 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 146:22da6e220af6 6078 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6079 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 146:22da6e220af6 6080 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 146:22da6e220af6 6081 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6082 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 146:22da6e220af6 6083 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 146:22da6e220af6 6084 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6085 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 146:22da6e220af6 6086 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 146:22da6e220af6 6087 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6088 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 146:22da6e220af6 6089 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 146:22da6e220af6 6090 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6091 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 146:22da6e220af6 6092 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 146:22da6e220af6 6093 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6094 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 146:22da6e220af6 6095 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 146:22da6e220af6 6096 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6097 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 146:22da6e220af6 6098 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 146:22da6e220af6 6099 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6100 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 146:22da6e220af6 6101 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 146:22da6e220af6 6102 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6103 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 146:22da6e220af6 6104 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 146:22da6e220af6 6105 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6106 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 146:22da6e220af6 6107 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 146:22da6e220af6 6108 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6109 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 146:22da6e220af6 6110 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 146:22da6e220af6 6111 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6112 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 146:22da6e220af6 6113 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 146:22da6e220af6 6114 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6115 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 146:22da6e220af6 6116
AnnaBridge 146:22da6e220af6 6117 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 146:22da6e220af6 6118 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 146:22da6e220af6 6119 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 6120 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 146:22da6e220af6 6121 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 146:22da6e220af6 6122 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 6123 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 146:22da6e220af6 6124 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 146:22da6e220af6 6125 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 6126 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 146:22da6e220af6 6127 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 146:22da6e220af6 6128 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6129 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 146:22da6e220af6 6130 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 146:22da6e220af6 6131 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6132 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 146:22da6e220af6 6133 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 146:22da6e220af6 6134 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6135 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 146:22da6e220af6 6136 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 146:22da6e220af6 6137 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6138 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 146:22da6e220af6 6139 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 146:22da6e220af6 6140 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6141 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 146:22da6e220af6 6142 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 146:22da6e220af6 6143 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6144 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 146:22da6e220af6 6145 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 146:22da6e220af6 6146 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6147 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 146:22da6e220af6 6148 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 146:22da6e220af6 6149 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6150 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 146:22da6e220af6 6151 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 146:22da6e220af6 6152 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6153 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 146:22da6e220af6 6154 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 146:22da6e220af6 6155 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6156 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 146:22da6e220af6 6157 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 146:22da6e220af6 6158 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6159 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 146:22da6e220af6 6160 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 146:22da6e220af6 6161 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6162 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 146:22da6e220af6 6163 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 146:22da6e220af6 6164 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6165 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 146:22da6e220af6 6166 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 146:22da6e220af6 6167 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6168 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 146:22da6e220af6 6169 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 146:22da6e220af6 6170 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6171 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 146:22da6e220af6 6172 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 146:22da6e220af6 6173 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6174 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 146:22da6e220af6 6175 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 146:22da6e220af6 6176 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6177 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 146:22da6e220af6 6178
AnnaBridge 146:22da6e220af6 6179 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 146:22da6e220af6 6180 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 146:22da6e220af6 6181 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 6182 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 146:22da6e220af6 6183 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 146:22da6e220af6 6184 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 6185 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 146:22da6e220af6 6186 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 146:22da6e220af6 6187 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 6188 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 146:22da6e220af6 6189 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 146:22da6e220af6 6190 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6191 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 146:22da6e220af6 6192 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 146:22da6e220af6 6193 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6194 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 146:22da6e220af6 6195 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 146:22da6e220af6 6196 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6197 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 146:22da6e220af6 6198 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 146:22da6e220af6 6199 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6200 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 146:22da6e220af6 6201 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 146:22da6e220af6 6202 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6203 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 146:22da6e220af6 6204 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 146:22da6e220af6 6205 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6206 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 146:22da6e220af6 6207 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 146:22da6e220af6 6208 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6209 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 146:22da6e220af6 6210 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 146:22da6e220af6 6211 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6212 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 146:22da6e220af6 6213 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 146:22da6e220af6 6214 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6215 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 146:22da6e220af6 6216 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 146:22da6e220af6 6217 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6218 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 146:22da6e220af6 6219 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 146:22da6e220af6 6220 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6221 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 146:22da6e220af6 6222 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 146:22da6e220af6 6223 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6224 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 146:22da6e220af6 6225 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 146:22da6e220af6 6226 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6227 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 146:22da6e220af6 6228 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 146:22da6e220af6 6229 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6230 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 146:22da6e220af6 6231 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 146:22da6e220af6 6232 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6233 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 146:22da6e220af6 6234 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 146:22da6e220af6 6235 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6236 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 146:22da6e220af6 6237 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 146:22da6e220af6 6238 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6239 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 146:22da6e220af6 6240
AnnaBridge 146:22da6e220af6 6241 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 146:22da6e220af6 6242 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 146:22da6e220af6 6243 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 6244 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 146:22da6e220af6 6245 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 146:22da6e220af6 6246 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 6247 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 146:22da6e220af6 6248 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 146:22da6e220af6 6249 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 6250 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 146:22da6e220af6 6251 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 146:22da6e220af6 6252 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6253 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 146:22da6e220af6 6254 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 146:22da6e220af6 6255 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6256 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 146:22da6e220af6 6257 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 146:22da6e220af6 6258 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6259 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 146:22da6e220af6 6260 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 146:22da6e220af6 6261 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6262 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 146:22da6e220af6 6263 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 146:22da6e220af6 6264 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6265 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 146:22da6e220af6 6266 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 146:22da6e220af6 6267 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6268 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 146:22da6e220af6 6269 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 146:22da6e220af6 6270 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6271 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 146:22da6e220af6 6272 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 146:22da6e220af6 6273 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6274 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 146:22da6e220af6 6275 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 146:22da6e220af6 6276 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6277 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 146:22da6e220af6 6278 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 146:22da6e220af6 6279 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6280 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 146:22da6e220af6 6281 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 146:22da6e220af6 6282 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6283 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 146:22da6e220af6 6284 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 146:22da6e220af6 6285 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6286 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 146:22da6e220af6 6287 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 146:22da6e220af6 6288 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6289 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 146:22da6e220af6 6290 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 146:22da6e220af6 6291 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6292 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 146:22da6e220af6 6293 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 146:22da6e220af6 6294 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6295 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 146:22da6e220af6 6296 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 146:22da6e220af6 6297 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6298 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 146:22da6e220af6 6299 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 146:22da6e220af6 6300 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6301 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 146:22da6e220af6 6302
AnnaBridge 146:22da6e220af6 6303 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 146:22da6e220af6 6304 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 146:22da6e220af6 6305 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 6306 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 146:22da6e220af6 6307
AnnaBridge 146:22da6e220af6 6308 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 146:22da6e220af6 6309 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 146:22da6e220af6 6310 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 6311 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 146:22da6e220af6 6312
AnnaBridge 146:22da6e220af6 6313 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 146:22da6e220af6 6314 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 146:22da6e220af6 6315 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 6316 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 146:22da6e220af6 6317
AnnaBridge 146:22da6e220af6 6318
AnnaBridge 146:22da6e220af6 6319 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6320 /* */
AnnaBridge 146:22da6e220af6 6321 /* External Interrupt/Event Controller */
AnnaBridge 146:22da6e220af6 6322 /* */
AnnaBridge 146:22da6e220af6 6323 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6324 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 146:22da6e220af6 6325 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 146:22da6e220af6 6326 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6327 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 146:22da6e220af6 6328 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 146:22da6e220af6 6329 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6330 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 146:22da6e220af6 6331 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 146:22da6e220af6 6332 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6333 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 146:22da6e220af6 6334 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 146:22da6e220af6 6335 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6336 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 146:22da6e220af6 6337 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 146:22da6e220af6 6338 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6339 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 146:22da6e220af6 6340 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 146:22da6e220af6 6341 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6342 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 146:22da6e220af6 6343 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 146:22da6e220af6 6344 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6345 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 146:22da6e220af6 6346 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 146:22da6e220af6 6347 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6348 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 146:22da6e220af6 6349 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 146:22da6e220af6 6350 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6351 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 146:22da6e220af6 6352 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 146:22da6e220af6 6353 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6354 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 146:22da6e220af6 6355 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 146:22da6e220af6 6356 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6357 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 146:22da6e220af6 6358 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 146:22da6e220af6 6359 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6360 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 146:22da6e220af6 6361 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 146:22da6e220af6 6362 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6363 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 146:22da6e220af6 6364 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 146:22da6e220af6 6365 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6366 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 146:22da6e220af6 6367 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 146:22da6e220af6 6368 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6369 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 146:22da6e220af6 6370 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 146:22da6e220af6 6371 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6372 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 146:22da6e220af6 6373 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 146:22da6e220af6 6374 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6375 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 146:22da6e220af6 6376 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 146:22da6e220af6 6377 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6378 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 146:22da6e220af6 6379 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 146:22da6e220af6 6380 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6381 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 146:22da6e220af6 6382 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 146:22da6e220af6 6383 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6384 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 146:22da6e220af6 6385 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 146:22da6e220af6 6386 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6387 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 146:22da6e220af6 6388 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 146:22da6e220af6 6389 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6390 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 146:22da6e220af6 6391 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 146:22da6e220af6 6392 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6393 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 146:22da6e220af6 6394 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 146:22da6e220af6 6395 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6396 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 146:22da6e220af6 6397
AnnaBridge 146:22da6e220af6 6398 /* Reference Defines */
AnnaBridge 146:22da6e220af6 6399 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 146:22da6e220af6 6400 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 146:22da6e220af6 6401 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 146:22da6e220af6 6402 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 146:22da6e220af6 6403 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 146:22da6e220af6 6404 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 146:22da6e220af6 6405 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 146:22da6e220af6 6406 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 146:22da6e220af6 6407 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 146:22da6e220af6 6408 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 146:22da6e220af6 6409 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 146:22da6e220af6 6410 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 146:22da6e220af6 6411 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 146:22da6e220af6 6412 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 146:22da6e220af6 6413 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 146:22da6e220af6 6414 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 146:22da6e220af6 6415 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 146:22da6e220af6 6416 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 146:22da6e220af6 6417 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 146:22da6e220af6 6418 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 146:22da6e220af6 6419 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 146:22da6e220af6 6420 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 146:22da6e220af6 6421 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 146:22da6e220af6 6422 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 146:22da6e220af6 6423 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 146:22da6e220af6 6424 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
AnnaBridge 146:22da6e220af6 6425 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 146:22da6e220af6 6426
AnnaBridge 146:22da6e220af6 6427 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 146:22da6e220af6 6428 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 146:22da6e220af6 6429 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6430 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 146:22da6e220af6 6431 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 146:22da6e220af6 6432 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6433 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 146:22da6e220af6 6434 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 146:22da6e220af6 6435 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6436 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 146:22da6e220af6 6437 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 146:22da6e220af6 6438 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6439 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 146:22da6e220af6 6440 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 146:22da6e220af6 6441 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6442 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 146:22da6e220af6 6443 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 146:22da6e220af6 6444 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6445 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 146:22da6e220af6 6446 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 146:22da6e220af6 6447 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6448 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 146:22da6e220af6 6449 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 146:22da6e220af6 6450 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6451 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 146:22da6e220af6 6452 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 146:22da6e220af6 6453 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6454 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 146:22da6e220af6 6455 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 146:22da6e220af6 6456 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6457 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 146:22da6e220af6 6458 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 146:22da6e220af6 6459 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6460 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 146:22da6e220af6 6461 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 146:22da6e220af6 6462 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6463 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 146:22da6e220af6 6464 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 146:22da6e220af6 6465 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6466 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 146:22da6e220af6 6467 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 146:22da6e220af6 6468 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6469 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 146:22da6e220af6 6470 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 146:22da6e220af6 6471 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6472 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 146:22da6e220af6 6473 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 146:22da6e220af6 6474 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6475 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 146:22da6e220af6 6476 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 146:22da6e220af6 6477 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6478 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 146:22da6e220af6 6479 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 146:22da6e220af6 6480 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6481 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 146:22da6e220af6 6482 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 146:22da6e220af6 6483 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6484 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 146:22da6e220af6 6485 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 146:22da6e220af6 6486 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6487 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 146:22da6e220af6 6488 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 146:22da6e220af6 6489 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6490 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 146:22da6e220af6 6491 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 146:22da6e220af6 6492 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6493 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 146:22da6e220af6 6494 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 146:22da6e220af6 6495 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6496 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 146:22da6e220af6 6497 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 146:22da6e220af6 6498 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6499 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 146:22da6e220af6 6500
AnnaBridge 146:22da6e220af6 6501 /* Reference Defines */
AnnaBridge 146:22da6e220af6 6502 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 146:22da6e220af6 6503 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 146:22da6e220af6 6504 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 146:22da6e220af6 6505 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 146:22da6e220af6 6506 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 146:22da6e220af6 6507 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 146:22da6e220af6 6508 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 146:22da6e220af6 6509 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 146:22da6e220af6 6510 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 146:22da6e220af6 6511 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 146:22da6e220af6 6512 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 146:22da6e220af6 6513 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 146:22da6e220af6 6514 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 146:22da6e220af6 6515 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 146:22da6e220af6 6516 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 146:22da6e220af6 6517 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 146:22da6e220af6 6518 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 146:22da6e220af6 6519 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 146:22da6e220af6 6520 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 146:22da6e220af6 6521 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 146:22da6e220af6 6522 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 146:22da6e220af6 6523 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 146:22da6e220af6 6524 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 146:22da6e220af6 6525 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 146:22da6e220af6 6526
AnnaBridge 146:22da6e220af6 6527 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 146:22da6e220af6 6528 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 146:22da6e220af6 6529 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6530 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 146:22da6e220af6 6531 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 146:22da6e220af6 6532 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6533 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 146:22da6e220af6 6534 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 146:22da6e220af6 6535 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6536 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 146:22da6e220af6 6537 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 146:22da6e220af6 6538 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6539 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 146:22da6e220af6 6540 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 146:22da6e220af6 6541 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6542 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 146:22da6e220af6 6543 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 146:22da6e220af6 6544 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6545 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 146:22da6e220af6 6546 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 146:22da6e220af6 6547 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6548 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 146:22da6e220af6 6549 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 146:22da6e220af6 6550 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6551 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 146:22da6e220af6 6552 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 146:22da6e220af6 6553 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6554 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 146:22da6e220af6 6555 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 146:22da6e220af6 6556 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6557 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 146:22da6e220af6 6558 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 146:22da6e220af6 6559 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6560 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 146:22da6e220af6 6561 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 146:22da6e220af6 6562 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6563 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 146:22da6e220af6 6564 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 146:22da6e220af6 6565 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6566 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 146:22da6e220af6 6567 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 146:22da6e220af6 6568 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6569 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 146:22da6e220af6 6570 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 146:22da6e220af6 6571 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6572 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 146:22da6e220af6 6573 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 146:22da6e220af6 6574 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6575 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 146:22da6e220af6 6576 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 146:22da6e220af6 6577 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6578 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 146:22da6e220af6 6579 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 146:22da6e220af6 6580 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6581 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 146:22da6e220af6 6582 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 146:22da6e220af6 6583 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6584 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 146:22da6e220af6 6585 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 146:22da6e220af6 6586 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6587 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 146:22da6e220af6 6588 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 146:22da6e220af6 6589 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6590 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 146:22da6e220af6 6591 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 146:22da6e220af6 6592 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6593 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 146:22da6e220af6 6594 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 146:22da6e220af6 6595 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6596 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 146:22da6e220af6 6597 #define EXTI_RTSR_TR23_Pos (23U)
AnnaBridge 146:22da6e220af6 6598 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6599 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
AnnaBridge 146:22da6e220af6 6600
AnnaBridge 146:22da6e220af6 6601 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 146:22da6e220af6 6602 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 146:22da6e220af6 6603 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6604 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 146:22da6e220af6 6605 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 146:22da6e220af6 6606 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6607 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 146:22da6e220af6 6608 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 146:22da6e220af6 6609 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6610 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 146:22da6e220af6 6611 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 146:22da6e220af6 6612 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6613 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 146:22da6e220af6 6614 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 146:22da6e220af6 6615 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6616 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 146:22da6e220af6 6617 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 146:22da6e220af6 6618 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6619 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 146:22da6e220af6 6620 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 146:22da6e220af6 6621 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6622 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 146:22da6e220af6 6623 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 146:22da6e220af6 6624 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6625 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 146:22da6e220af6 6626 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 146:22da6e220af6 6627 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6628 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 146:22da6e220af6 6629 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 146:22da6e220af6 6630 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6631 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 146:22da6e220af6 6632 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 146:22da6e220af6 6633 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6634 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 146:22da6e220af6 6635 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 146:22da6e220af6 6636 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6637 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 146:22da6e220af6 6638 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 146:22da6e220af6 6639 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6640 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 146:22da6e220af6 6641 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 146:22da6e220af6 6642 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6643 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 146:22da6e220af6 6644 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 146:22da6e220af6 6645 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6646 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 146:22da6e220af6 6647 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 146:22da6e220af6 6648 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6649 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 146:22da6e220af6 6650 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 146:22da6e220af6 6651 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6652 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 146:22da6e220af6 6653 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 146:22da6e220af6 6654 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6655 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 146:22da6e220af6 6656 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 146:22da6e220af6 6657 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6658 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 146:22da6e220af6 6659 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 146:22da6e220af6 6660 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6661 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 146:22da6e220af6 6662 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 146:22da6e220af6 6663 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6664 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 146:22da6e220af6 6665 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 146:22da6e220af6 6666 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6667 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 146:22da6e220af6 6668 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 146:22da6e220af6 6669 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6670 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 146:22da6e220af6 6671 #define EXTI_FTSR_TR23_Pos (23U)
AnnaBridge 146:22da6e220af6 6672 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6673 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
AnnaBridge 146:22da6e220af6 6674
AnnaBridge 146:22da6e220af6 6675 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 146:22da6e220af6 6676 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 146:22da6e220af6 6677 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6678 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 146:22da6e220af6 6679 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 146:22da6e220af6 6680 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6681 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 146:22da6e220af6 6682 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 146:22da6e220af6 6683 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6684 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 146:22da6e220af6 6685 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 146:22da6e220af6 6686 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6687 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 146:22da6e220af6 6688 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 146:22da6e220af6 6689 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6690 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 146:22da6e220af6 6691 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 146:22da6e220af6 6692 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6693 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 146:22da6e220af6 6694 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 146:22da6e220af6 6695 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6696 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 146:22da6e220af6 6697 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 146:22da6e220af6 6698 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6699 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 146:22da6e220af6 6700 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 146:22da6e220af6 6701 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6702 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 146:22da6e220af6 6703 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 146:22da6e220af6 6704 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6705 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 146:22da6e220af6 6706 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 146:22da6e220af6 6707 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6708 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 146:22da6e220af6 6709 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 146:22da6e220af6 6710 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6711 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 146:22da6e220af6 6712 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 146:22da6e220af6 6713 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6714 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 146:22da6e220af6 6715 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 146:22da6e220af6 6716 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6717 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 146:22da6e220af6 6718 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 146:22da6e220af6 6719 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6720 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 146:22da6e220af6 6721 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 146:22da6e220af6 6722 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6723 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 146:22da6e220af6 6724 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 146:22da6e220af6 6725 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6726 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 146:22da6e220af6 6727 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 146:22da6e220af6 6728 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6729 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 146:22da6e220af6 6730 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 146:22da6e220af6 6731 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6732 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 146:22da6e220af6 6733 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 146:22da6e220af6 6734 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6735 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 146:22da6e220af6 6736 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 146:22da6e220af6 6737 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6738 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 146:22da6e220af6 6739 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 146:22da6e220af6 6740 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6741 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 146:22da6e220af6 6742 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 146:22da6e220af6 6743 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6744 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 146:22da6e220af6 6745 #define EXTI_SWIER_SWIER23_Pos (23U)
AnnaBridge 146:22da6e220af6 6746 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6747 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
AnnaBridge 146:22da6e220af6 6748
AnnaBridge 146:22da6e220af6 6749 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 146:22da6e220af6 6750 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 146:22da6e220af6 6751 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6752 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 146:22da6e220af6 6753 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 146:22da6e220af6 6754 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6755 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 146:22da6e220af6 6756 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 146:22da6e220af6 6757 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6758 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 146:22da6e220af6 6759 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 146:22da6e220af6 6760 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6761 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 146:22da6e220af6 6762 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 146:22da6e220af6 6763 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6764 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 146:22da6e220af6 6765 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 146:22da6e220af6 6766 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6767 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 146:22da6e220af6 6768 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 146:22da6e220af6 6769 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6770 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 146:22da6e220af6 6771 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 146:22da6e220af6 6772 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6773 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 146:22da6e220af6 6774 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 146:22da6e220af6 6775 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6776 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 146:22da6e220af6 6777 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 146:22da6e220af6 6778 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6779 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 146:22da6e220af6 6780 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 146:22da6e220af6 6781 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6782 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 146:22da6e220af6 6783 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 146:22da6e220af6 6784 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6785 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 146:22da6e220af6 6786 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 146:22da6e220af6 6787 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6788 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 146:22da6e220af6 6789 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 146:22da6e220af6 6790 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6791 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 146:22da6e220af6 6792 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 146:22da6e220af6 6793 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6794 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 146:22da6e220af6 6795 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 146:22da6e220af6 6796 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6797 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 146:22da6e220af6 6798 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 146:22da6e220af6 6799 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6800 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 146:22da6e220af6 6801 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 146:22da6e220af6 6802 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6803 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 146:22da6e220af6 6804 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 146:22da6e220af6 6805 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6806 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 146:22da6e220af6 6807 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 146:22da6e220af6 6808 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6809 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 146:22da6e220af6 6810 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 146:22da6e220af6 6811 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6812 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 146:22da6e220af6 6813 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 146:22da6e220af6 6814 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6815 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 146:22da6e220af6 6816 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 146:22da6e220af6 6817 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6818 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 146:22da6e220af6 6819 #define EXTI_PR_PR23_Pos (23U)
AnnaBridge 146:22da6e220af6 6820 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6821 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
AnnaBridge 146:22da6e220af6 6822
AnnaBridge 146:22da6e220af6 6823 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6824 /* */
AnnaBridge 146:22da6e220af6 6825 /* FLASH */
AnnaBridge 146:22da6e220af6 6826 /* */
AnnaBridge 146:22da6e220af6 6827 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6828 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 146:22da6e220af6 6829 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 146:22da6e220af6 6830 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 6831 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 146:22da6e220af6 6832 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 146:22da6e220af6 6833 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 146:22da6e220af6 6834 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 146:22da6e220af6 6835 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 146:22da6e220af6 6836 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 146:22da6e220af6 6837 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 146:22da6e220af6 6838 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 146:22da6e220af6 6839 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 146:22da6e220af6 6840
AnnaBridge 146:22da6e220af6 6841 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 146:22da6e220af6 6842 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6843 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 146:22da6e220af6 6844 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 146:22da6e220af6 6845 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6846 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 146:22da6e220af6 6847 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 146:22da6e220af6 6848 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6849 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 146:22da6e220af6 6850 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 146:22da6e220af6 6851 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6852 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 146:22da6e220af6 6853 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 146:22da6e220af6 6854 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6855 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 146:22da6e220af6 6856 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 146:22da6e220af6 6857 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 146:22da6e220af6 6858 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 146:22da6e220af6 6859 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 146:22da6e220af6 6860 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 146:22da6e220af6 6861 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
AnnaBridge 146:22da6e220af6 6862
AnnaBridge 146:22da6e220af6 6863 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 146:22da6e220af6 6864 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 146:22da6e220af6 6865 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6866 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 146:22da6e220af6 6867 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 146:22da6e220af6 6868 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6869 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 146:22da6e220af6 6870 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 146:22da6e220af6 6871 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6872 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 146:22da6e220af6 6873 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 146:22da6e220af6 6874 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6875 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 146:22da6e220af6 6876 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 146:22da6e220af6 6877 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6878 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 146:22da6e220af6 6879 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 146:22da6e220af6 6880 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6881 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 146:22da6e220af6 6882 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 146:22da6e220af6 6883 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6884 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 146:22da6e220af6 6885 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 146:22da6e220af6 6886 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6887 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 146:22da6e220af6 6888
AnnaBridge 146:22da6e220af6 6889 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 146:22da6e220af6 6890 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 146:22da6e220af6 6891 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6892 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 146:22da6e220af6 6893 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 146:22da6e220af6 6894 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6895 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 146:22da6e220af6 6896 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 146:22da6e220af6 6897 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 6898 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 146:22da6e220af6 6899 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 146:22da6e220af6 6900 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 146:22da6e220af6 6901 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 146:22da6e220af6 6902 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 6903 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 6904 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6905 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6906 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6907 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 146:22da6e220af6 6908 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 6909 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 146:22da6e220af6 6910 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6911 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6912 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 146:22da6e220af6 6913 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6914 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 146:22da6e220af6 6915 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 146:22da6e220af6 6916 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6917 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 146:22da6e220af6 6918 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 146:22da6e220af6 6919 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 6920 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 146:22da6e220af6 6921
AnnaBridge 146:22da6e220af6 6922 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 146:22da6e220af6 6923 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 146:22da6e220af6 6924 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 6925 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 146:22da6e220af6 6926 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 146:22da6e220af6 6927 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 6928 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 146:22da6e220af6 6929
AnnaBridge 146:22da6e220af6 6930 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 146:22da6e220af6 6931 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 146:22da6e220af6 6932 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 146:22da6e220af6 6933 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 6934 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 146:22da6e220af6 6935 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 146:22da6e220af6 6936 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 6937 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 146:22da6e220af6 6938 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 146:22da6e220af6 6939 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 6940 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 146:22da6e220af6 6941 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 146:22da6e220af6 6942 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 6943 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 146:22da6e220af6 6944 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 146:22da6e220af6 6945 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 6946 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 146:22da6e220af6 6947 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 6948 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 6949 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 6950 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 6951 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 6952 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 6953 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 6954 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 6955 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 146:22da6e220af6 6956 #define FLASH_OPTCR_nWRP_Msk (0x7FFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x7FFF0000 */
AnnaBridge 146:22da6e220af6 6957 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 146:22da6e220af6 6958 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 146:22da6e220af6 6959 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 146:22da6e220af6 6960 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 146:22da6e220af6 6961 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 146:22da6e220af6 6962 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 146:22da6e220af6 6963 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 146:22da6e220af6 6964 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 146:22da6e220af6 6965 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 146:22da6e220af6 6966 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 146:22da6e220af6 6967 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 146:22da6e220af6 6968 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 146:22da6e220af6 6969 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 146:22da6e220af6 6970 #define FLASH_OPTCR_nWRP_12 0x10000000U
AnnaBridge 146:22da6e220af6 6971 #define FLASH_OPTCR_nWRP_13 0x20000000U
AnnaBridge 146:22da6e220af6 6972 #define FLASH_OPTCR_nWRP_14 0x40000000U
AnnaBridge 146:22da6e220af6 6973 #define FLASH_OPTCR_nWRP_15 0x40000000U
AnnaBridge 146:22da6e220af6 6974
AnnaBridge 146:22da6e220af6 6975 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 146:22da6e220af6 6976 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 146:22da6e220af6 6977 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 146:22da6e220af6 6978 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 146:22da6e220af6 6979 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 6980 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 6981 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 6982 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 6983 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 6984 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 6985 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 6986 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 6987 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 6988 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 6989 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 6990 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 6991
AnnaBridge 146:22da6e220af6 6992 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6993 /* */
AnnaBridge 146:22da6e220af6 6994 /* Flexible Static Memory Controller */
AnnaBridge 146:22da6e220af6 6995 /* */
AnnaBridge 146:22da6e220af6 6996 /******************************************************************************/
AnnaBridge 146:22da6e220af6 6997 /****************** Bit definition for FSMC_BCR1 register *******************/
AnnaBridge 146:22da6e220af6 6998 #define FSMC_BCR1_MBKEN_Pos (0U)
AnnaBridge 146:22da6e220af6 6999 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7000 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 146:22da6e220af6 7001 #define FSMC_BCR1_MUXEN_Pos (1U)
AnnaBridge 146:22da6e220af6 7002 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7003 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 146:22da6e220af6 7004
AnnaBridge 146:22da6e220af6 7005 #define FSMC_BCR1_MTYP_Pos (2U)
AnnaBridge 146:22da6e220af6 7006 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7007 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 146:22da6e220af6 7008 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7009 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7010
AnnaBridge 146:22da6e220af6 7011 #define FSMC_BCR1_MWID_Pos (4U)
AnnaBridge 146:22da6e220af6 7012 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7013 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 146:22da6e220af6 7014 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7015 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7016
AnnaBridge 146:22da6e220af6 7017 #define FSMC_BCR1_FACCEN_Pos (6U)
AnnaBridge 146:22da6e220af6 7018 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7019 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 146:22da6e220af6 7020 #define FSMC_BCR1_BURSTEN_Pos (8U)
AnnaBridge 146:22da6e220af6 7021 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7022 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 146:22da6e220af6 7023 #define FSMC_BCR1_WAITPOL_Pos (9U)
AnnaBridge 146:22da6e220af6 7024 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7025 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 146:22da6e220af6 7026 #define FSMC_BCR1_WAITCFG_Pos (11U)
AnnaBridge 146:22da6e220af6 7027 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7028 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 146:22da6e220af6 7029 #define FSMC_BCR1_WREN_Pos (12U)
AnnaBridge 146:22da6e220af6 7030 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7031 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
AnnaBridge 146:22da6e220af6 7032 #define FSMC_BCR1_WAITEN_Pos (13U)
AnnaBridge 146:22da6e220af6 7033 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7034 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 146:22da6e220af6 7035 #define FSMC_BCR1_EXTMOD_Pos (14U)
AnnaBridge 146:22da6e220af6 7036 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7037 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 146:22da6e220af6 7038 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
AnnaBridge 146:22da6e220af6 7039 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7040 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 146:22da6e220af6 7041 #define FSMC_BCR1_CPSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 7042 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 146:22da6e220af6 7043 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 146:22da6e220af6 7044 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7045 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7046 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7047 #define FSMC_BCR1_CBURSTRW_Pos (19U)
AnnaBridge 146:22da6e220af6 7048 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7049 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 146:22da6e220af6 7050 #define FSMC_BCR1_CCLKEN_Pos (20U)
AnnaBridge 146:22da6e220af6 7051 #define FSMC_BCR1_CCLKEN_Msk (0x1U << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7052 #define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
AnnaBridge 146:22da6e220af6 7053 #define FSMC_BCR1_WFDIS_Pos (21U)
AnnaBridge 146:22da6e220af6 7054 #define FSMC_BCR1_WFDIS_Msk (0x1U << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7055 #define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
AnnaBridge 146:22da6e220af6 7056
AnnaBridge 146:22da6e220af6 7057 /****************** Bit definition for FSMC_BCR2 register *******************/
AnnaBridge 146:22da6e220af6 7058 #define FSMC_BCR2_MBKEN_Pos (0U)
AnnaBridge 146:22da6e220af6 7059 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7060 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 146:22da6e220af6 7061 #define FSMC_BCR2_MUXEN_Pos (1U)
AnnaBridge 146:22da6e220af6 7062 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7063 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 146:22da6e220af6 7064
AnnaBridge 146:22da6e220af6 7065 #define FSMC_BCR2_MTYP_Pos (2U)
AnnaBridge 146:22da6e220af6 7066 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7067 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 146:22da6e220af6 7068 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7069 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7070
AnnaBridge 146:22da6e220af6 7071 #define FSMC_BCR2_MWID_Pos (4U)
AnnaBridge 146:22da6e220af6 7072 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7073 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 146:22da6e220af6 7074 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7075 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7076
AnnaBridge 146:22da6e220af6 7077 #define FSMC_BCR2_FACCEN_Pos (6U)
AnnaBridge 146:22da6e220af6 7078 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7079 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 146:22da6e220af6 7080 #define FSMC_BCR2_BURSTEN_Pos (8U)
AnnaBridge 146:22da6e220af6 7081 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7082 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 146:22da6e220af6 7083 #define FSMC_BCR2_WAITPOL_Pos (9U)
AnnaBridge 146:22da6e220af6 7084 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7085 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 146:22da6e220af6 7086 #define FSMC_BCR2_WAITCFG_Pos (11U)
AnnaBridge 146:22da6e220af6 7087 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7088 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 146:22da6e220af6 7089 #define FSMC_BCR2_WREN_Pos (12U)
AnnaBridge 146:22da6e220af6 7090 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7091 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
AnnaBridge 146:22da6e220af6 7092 #define FSMC_BCR2_WAITEN_Pos (13U)
AnnaBridge 146:22da6e220af6 7093 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7094 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 146:22da6e220af6 7095 #define FSMC_BCR2_EXTMOD_Pos (14U)
AnnaBridge 146:22da6e220af6 7096 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7097 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 146:22da6e220af6 7098 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
AnnaBridge 146:22da6e220af6 7099 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7100 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 146:22da6e220af6 7101 #define FSMC_BCR2_CPSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 7102 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 146:22da6e220af6 7103 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 146:22da6e220af6 7104 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7105 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7106 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7107 #define FSMC_BCR2_CBURSTRW_Pos (19U)
AnnaBridge 146:22da6e220af6 7108 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7109 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 146:22da6e220af6 7110
AnnaBridge 146:22da6e220af6 7111 /****************** Bit definition for FSMC_BCR3 register *******************/
AnnaBridge 146:22da6e220af6 7112 #define FSMC_BCR3_MBKEN_Pos (0U)
AnnaBridge 146:22da6e220af6 7113 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7114 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 146:22da6e220af6 7115 #define FSMC_BCR3_MUXEN_Pos (1U)
AnnaBridge 146:22da6e220af6 7116 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7117 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 146:22da6e220af6 7118
AnnaBridge 146:22da6e220af6 7119 #define FSMC_BCR3_MTYP_Pos (2U)
AnnaBridge 146:22da6e220af6 7120 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7121 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 146:22da6e220af6 7122 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7123 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7124
AnnaBridge 146:22da6e220af6 7125 #define FSMC_BCR3_MWID_Pos (4U)
AnnaBridge 146:22da6e220af6 7126 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7127 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 146:22da6e220af6 7128 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7129 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7130
AnnaBridge 146:22da6e220af6 7131 #define FSMC_BCR3_FACCEN_Pos (6U)
AnnaBridge 146:22da6e220af6 7132 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7133 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 146:22da6e220af6 7134 #define FSMC_BCR3_BURSTEN_Pos (8U)
AnnaBridge 146:22da6e220af6 7135 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7136 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 146:22da6e220af6 7137 #define FSMC_BCR3_WAITPOL_Pos (9U)
AnnaBridge 146:22da6e220af6 7138 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7139 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 146:22da6e220af6 7140 #define FSMC_BCR3_WAITCFG_Pos (11U)
AnnaBridge 146:22da6e220af6 7141 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7142 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 146:22da6e220af6 7143 #define FSMC_BCR3_WREN_Pos (12U)
AnnaBridge 146:22da6e220af6 7144 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7145 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
AnnaBridge 146:22da6e220af6 7146 #define FSMC_BCR3_WAITEN_Pos (13U)
AnnaBridge 146:22da6e220af6 7147 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7148 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 146:22da6e220af6 7149 #define FSMC_BCR3_EXTMOD_Pos (14U)
AnnaBridge 146:22da6e220af6 7150 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7151 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 146:22da6e220af6 7152 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
AnnaBridge 146:22da6e220af6 7153 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7154 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 146:22da6e220af6 7155 #define FSMC_BCR3_CPSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 7156 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 146:22da6e220af6 7157 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 146:22da6e220af6 7158 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7159 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7160 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7161 #define FSMC_BCR3_CBURSTRW_Pos (19U)
AnnaBridge 146:22da6e220af6 7162 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7163 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 146:22da6e220af6 7164
AnnaBridge 146:22da6e220af6 7165 /****************** Bit definition for FSMC_BCR4 register *******************/
AnnaBridge 146:22da6e220af6 7166 #define FSMC_BCR4_MBKEN_Pos (0U)
AnnaBridge 146:22da6e220af6 7167 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7168 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 146:22da6e220af6 7169 #define FSMC_BCR4_MUXEN_Pos (1U)
AnnaBridge 146:22da6e220af6 7170 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7171 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 146:22da6e220af6 7172
AnnaBridge 146:22da6e220af6 7173 #define FSMC_BCR4_MTYP_Pos (2U)
AnnaBridge 146:22da6e220af6 7174 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7175 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 146:22da6e220af6 7176 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7177 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7178
AnnaBridge 146:22da6e220af6 7179 #define FSMC_BCR4_MWID_Pos (4U)
AnnaBridge 146:22da6e220af6 7180 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7181 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 146:22da6e220af6 7182 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7183 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7184
AnnaBridge 146:22da6e220af6 7185 #define FSMC_BCR4_FACCEN_Pos (6U)
AnnaBridge 146:22da6e220af6 7186 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7187 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 146:22da6e220af6 7188 #define FSMC_BCR4_BURSTEN_Pos (8U)
AnnaBridge 146:22da6e220af6 7189 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7190 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 146:22da6e220af6 7191 #define FSMC_BCR4_WAITPOL_Pos (9U)
AnnaBridge 146:22da6e220af6 7192 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7193 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 146:22da6e220af6 7194 #define FSMC_BCR4_WAITCFG_Pos (11U)
AnnaBridge 146:22da6e220af6 7195 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7196 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 146:22da6e220af6 7197 #define FSMC_BCR4_WREN_Pos (12U)
AnnaBridge 146:22da6e220af6 7198 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7199 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
AnnaBridge 146:22da6e220af6 7200 #define FSMC_BCR4_WAITEN_Pos (13U)
AnnaBridge 146:22da6e220af6 7201 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7202 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 146:22da6e220af6 7203 #define FSMC_BCR4_EXTMOD_Pos (14U)
AnnaBridge 146:22da6e220af6 7204 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7205 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 146:22da6e220af6 7206 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
AnnaBridge 146:22da6e220af6 7207 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7208 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 146:22da6e220af6 7209 #define FSMC_BCR4_CPSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 7210 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 146:22da6e220af6 7211 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 146:22da6e220af6 7212 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7213 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7214 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7215 #define FSMC_BCR4_CBURSTRW_Pos (19U)
AnnaBridge 146:22da6e220af6 7216 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7217 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 146:22da6e220af6 7218
AnnaBridge 146:22da6e220af6 7219 /****************** Bit definition for FSMC_BTR1 register ******************/
AnnaBridge 146:22da6e220af6 7220 #define FSMC_BTR1_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7221 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7222 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7223 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7224 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7225 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7226 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7227
AnnaBridge 146:22da6e220af6 7228 #define FSMC_BTR1_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7229 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7230 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7231 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7232 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7233 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7234 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7235
AnnaBridge 146:22da6e220af6 7236 #define FSMC_BTR1_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7237 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7238 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7239 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7240 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7241 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7242 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7243 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7244 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7245 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7246 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7247
AnnaBridge 146:22da6e220af6 7248 #define FSMC_BTR1_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7249 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7250 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 146:22da6e220af6 7251 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7252 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7253 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7254 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7255
AnnaBridge 146:22da6e220af6 7256 #define FSMC_BTR1_CLKDIV_Pos (20U)
AnnaBridge 146:22da6e220af6 7257 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 7258 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 146:22da6e220af6 7259 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7260 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7261 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7262 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7263
AnnaBridge 146:22da6e220af6 7264 #define FSMC_BTR1_DATLAT_Pos (24U)
AnnaBridge 146:22da6e220af6 7265 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 7266 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 146:22da6e220af6 7267 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7268 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7269 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7270 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7271
AnnaBridge 146:22da6e220af6 7272 #define FSMC_BTR1_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7273 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7274 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7275 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7276 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7277
AnnaBridge 146:22da6e220af6 7278 /****************** Bit definition for FSMC_BTR2 register *******************/
AnnaBridge 146:22da6e220af6 7279 #define FSMC_BTR2_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7280 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7281 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7282 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7283 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7284 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7285 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7286
AnnaBridge 146:22da6e220af6 7287 #define FSMC_BTR2_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7288 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7289 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7290 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7291 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7292 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7293 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7294
AnnaBridge 146:22da6e220af6 7295 #define FSMC_BTR2_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7296 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7297 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7298 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7299 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7300 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7301 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7302 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7303 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7304 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7305 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7306
AnnaBridge 146:22da6e220af6 7307 #define FSMC_BTR2_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7308 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7309 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 146:22da6e220af6 7310 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7311 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7312 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7313 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7314
AnnaBridge 146:22da6e220af6 7315 #define FSMC_BTR2_CLKDIV_Pos (20U)
AnnaBridge 146:22da6e220af6 7316 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 7317 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 146:22da6e220af6 7318 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7319 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7320 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7321 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7322
AnnaBridge 146:22da6e220af6 7323 #define FSMC_BTR2_DATLAT_Pos (24U)
AnnaBridge 146:22da6e220af6 7324 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 7325 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 146:22da6e220af6 7326 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7327 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7328 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7329 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7330
AnnaBridge 146:22da6e220af6 7331 #define FSMC_BTR2_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7332 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7333 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7334 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7335 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7336
AnnaBridge 146:22da6e220af6 7337 /******************* Bit definition for FSMC_BTR3 register *******************/
AnnaBridge 146:22da6e220af6 7338 #define FSMC_BTR3_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7339 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7340 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7341 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7342 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7343 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7344 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7345
AnnaBridge 146:22da6e220af6 7346 #define FSMC_BTR3_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7347 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7348 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7349 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7350 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7351 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7352 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7353
AnnaBridge 146:22da6e220af6 7354 #define FSMC_BTR3_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7355 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7356 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7357 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7358 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7359 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7360 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7361 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7362 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7363 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7364 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7365
AnnaBridge 146:22da6e220af6 7366 #define FSMC_BTR3_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7367 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7368 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 146:22da6e220af6 7369 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7370 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7371 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7372 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7373
AnnaBridge 146:22da6e220af6 7374 #define FSMC_BTR3_CLKDIV_Pos (20U)
AnnaBridge 146:22da6e220af6 7375 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 7376 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 146:22da6e220af6 7377 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7378 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7379 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7380 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7381
AnnaBridge 146:22da6e220af6 7382 #define FSMC_BTR3_DATLAT_Pos (24U)
AnnaBridge 146:22da6e220af6 7383 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 7384 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 146:22da6e220af6 7385 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7386 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7387 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7388 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7389
AnnaBridge 146:22da6e220af6 7390 #define FSMC_BTR3_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7391 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7392 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7393 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7394 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7395
AnnaBridge 146:22da6e220af6 7396 /****************** Bit definition for FSMC_BTR4 register *******************/
AnnaBridge 146:22da6e220af6 7397 #define FSMC_BTR4_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7398 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7399 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7400 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7401 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7402 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7403 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7404
AnnaBridge 146:22da6e220af6 7405 #define FSMC_BTR4_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7406 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7407 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7408 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7409 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7410 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7411 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7412
AnnaBridge 146:22da6e220af6 7413 #define FSMC_BTR4_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7414 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7415 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7416 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7417 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7418 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7419 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7420 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7421 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7422 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7423 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7424
AnnaBridge 146:22da6e220af6 7425 #define FSMC_BTR4_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7426 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7427 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 146:22da6e220af6 7428 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7429 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7430 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7431 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7432
AnnaBridge 146:22da6e220af6 7433 #define FSMC_BTR4_CLKDIV_Pos (20U)
AnnaBridge 146:22da6e220af6 7434 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 7435 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 146:22da6e220af6 7436 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7437 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7438 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7439 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7440
AnnaBridge 146:22da6e220af6 7441 #define FSMC_BTR4_DATLAT_Pos (24U)
AnnaBridge 146:22da6e220af6 7442 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 7443 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 146:22da6e220af6 7444 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7445 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7446 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7447 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7448
AnnaBridge 146:22da6e220af6 7449 #define FSMC_BTR4_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7450 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7451 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7452 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7453 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7454
AnnaBridge 146:22da6e220af6 7455 /****************** Bit definition for FSMC_BWTR1 register ******************/
AnnaBridge 146:22da6e220af6 7456 #define FSMC_BWTR1_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7457 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7458 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7459 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7460 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7461 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7462 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7463
AnnaBridge 146:22da6e220af6 7464 #define FSMC_BWTR1_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7465 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7466 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7467 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7468 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7469 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7470 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7471
AnnaBridge 146:22da6e220af6 7472 #define FSMC_BWTR1_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7473 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7474 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7475 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7476 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7477 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7478 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7479 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7480 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7481 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7482 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7483
AnnaBridge 146:22da6e220af6 7484 #define FSMC_BWTR1_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7485 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7486 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 146:22da6e220af6 7487 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7488 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7489 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7490 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7491
AnnaBridge 146:22da6e220af6 7492 #define FSMC_BWTR1_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7493 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7494 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7495 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7496 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7497
AnnaBridge 146:22da6e220af6 7498 /****************** Bit definition for FSMC_BWTR2 register ******************/
AnnaBridge 146:22da6e220af6 7499 #define FSMC_BWTR2_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7500 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7501 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7502 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7503 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7504 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7505 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7506
AnnaBridge 146:22da6e220af6 7507 #define FSMC_BWTR2_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7508 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7509 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7510 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7511 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7512 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7513 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7514
AnnaBridge 146:22da6e220af6 7515 #define FSMC_BWTR2_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7516 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7517 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7518 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7519 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7520 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7521 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7522 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7523 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7524 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7525 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7526
AnnaBridge 146:22da6e220af6 7527 #define FSMC_BWTR2_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7528 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7529 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 146:22da6e220af6 7530 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7531 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7532 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7533 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7534
AnnaBridge 146:22da6e220af6 7535 #define FSMC_BWTR2_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7536 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7537 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7538 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7539 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7540
AnnaBridge 146:22da6e220af6 7541 /****************** Bit definition for FSMC_BWTR3 register ******************/
AnnaBridge 146:22da6e220af6 7542 #define FSMC_BWTR3_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7543 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7544 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7545 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7546 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7547 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7548 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7549
AnnaBridge 146:22da6e220af6 7550 #define FSMC_BWTR3_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7551 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7552 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7553 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7554 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7555 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7556 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7557
AnnaBridge 146:22da6e220af6 7558 #define FSMC_BWTR3_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7559 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7560 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7561 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7562 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7563 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7564 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7565 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7566 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7567 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7568 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7569
AnnaBridge 146:22da6e220af6 7570 #define FSMC_BWTR3_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7571 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7572 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 146:22da6e220af6 7573 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7574 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7575 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7576 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7577
AnnaBridge 146:22da6e220af6 7578 #define FSMC_BWTR3_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7579 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7580 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7581 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7582 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7583
AnnaBridge 146:22da6e220af6 7584 /****************** Bit definition for FSMC_BWTR4 register ******************/
AnnaBridge 146:22da6e220af6 7585 #define FSMC_BWTR4_ADDSET_Pos (0U)
AnnaBridge 146:22da6e220af6 7586 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 7587 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 146:22da6e220af6 7588 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7589 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7590 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7591 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7592
AnnaBridge 146:22da6e220af6 7593 #define FSMC_BWTR4_ADDHLD_Pos (4U)
AnnaBridge 146:22da6e220af6 7594 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 7595 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 146:22da6e220af6 7596 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7597 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7598 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7599 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7600
AnnaBridge 146:22da6e220af6 7601 #define FSMC_BWTR4_DATAST_Pos (8U)
AnnaBridge 146:22da6e220af6 7602 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 7603 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 146:22da6e220af6 7604 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 146:22da6e220af6 7605 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 146:22da6e220af6 7606 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 146:22da6e220af6 7607 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 146:22da6e220af6 7608 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 146:22da6e220af6 7609 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 146:22da6e220af6 7610 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 146:22da6e220af6 7611 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 146:22da6e220af6 7612
AnnaBridge 146:22da6e220af6 7613 #define FSMC_BWTR4_BUSTURN_Pos (16U)
AnnaBridge 146:22da6e220af6 7614 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 7615 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 146:22da6e220af6 7616 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7617 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7618 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7619 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7620
AnnaBridge 146:22da6e220af6 7621 #define FSMC_BWTR4_ACCMOD_Pos (28U)
AnnaBridge 146:22da6e220af6 7622 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7623 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 146:22da6e220af6 7624 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7625 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7626
AnnaBridge 146:22da6e220af6 7627 /******************************************************************************/
AnnaBridge 146:22da6e220af6 7628 /* */
AnnaBridge 146:22da6e220af6 7629 /* General Purpose I/O */
AnnaBridge 146:22da6e220af6 7630 /* */
AnnaBridge 146:22da6e220af6 7631 /******************************************************************************/
AnnaBridge 146:22da6e220af6 7632 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 146:22da6e220af6 7633 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 146:22da6e220af6 7634 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 7635 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 146:22da6e220af6 7636 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7637 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7638 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 146:22da6e220af6 7639 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7640 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 146:22da6e220af6 7641 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7642 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7643 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 146:22da6e220af6 7644 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7645 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 146:22da6e220af6 7646 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7647 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7648 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 146:22da6e220af6 7649 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 7650 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 146:22da6e220af6 7651 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7652 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7653 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 146:22da6e220af6 7654 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 7655 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 146:22da6e220af6 7656 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7657 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7658 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 146:22da6e220af6 7659 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 7660 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 146:22da6e220af6 7661 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7662 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7663 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 146:22da6e220af6 7664 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 7665 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 146:22da6e220af6 7666 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7667 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7668 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 146:22da6e220af6 7669 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 7670 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 146:22da6e220af6 7671 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7672 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7673 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 146:22da6e220af6 7674 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 7675 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 146:22da6e220af6 7676 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7677 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7678 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 146:22da6e220af6 7679 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 7680 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 146:22da6e220af6 7681 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7682 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7683 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 146:22da6e220af6 7684 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 7685 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 146:22da6e220af6 7686 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7687 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7688 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 146:22da6e220af6 7689 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 7690 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 146:22da6e220af6 7691 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7692 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7693 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 146:22da6e220af6 7694 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 7695 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 146:22da6e220af6 7696 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7697 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7698 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 146:22da6e220af6 7699 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 146:22da6e220af6 7700 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 146:22da6e220af6 7701 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7702 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7703 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 146:22da6e220af6 7704 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7705 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 146:22da6e220af6 7706 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7707 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7708 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 146:22da6e220af6 7709 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 146:22da6e220af6 7710 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 146:22da6e220af6 7711 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 7712 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 7713
AnnaBridge 146:22da6e220af6 7714 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 146:22da6e220af6 7715 #define GPIO_OTYPER_OT_0 0x00000001U
AnnaBridge 146:22da6e220af6 7716 #define GPIO_OTYPER_OT_1 0x00000002U
AnnaBridge 146:22da6e220af6 7717 #define GPIO_OTYPER_OT_2 0x00000004U
AnnaBridge 146:22da6e220af6 7718 #define GPIO_OTYPER_OT_3 0x00000008U
AnnaBridge 146:22da6e220af6 7719 #define GPIO_OTYPER_OT_4 0x00000010U
AnnaBridge 146:22da6e220af6 7720 #define GPIO_OTYPER_OT_5 0x00000020U
AnnaBridge 146:22da6e220af6 7721 #define GPIO_OTYPER_OT_6 0x00000040U
AnnaBridge 146:22da6e220af6 7722 #define GPIO_OTYPER_OT_7 0x00000080U
AnnaBridge 146:22da6e220af6 7723 #define GPIO_OTYPER_OT_8 0x00000100U
AnnaBridge 146:22da6e220af6 7724 #define GPIO_OTYPER_OT_9 0x00000200U
AnnaBridge 146:22da6e220af6 7725 #define GPIO_OTYPER_OT_10 0x00000400U
AnnaBridge 146:22da6e220af6 7726 #define GPIO_OTYPER_OT_11 0x00000800U
AnnaBridge 146:22da6e220af6 7727 #define GPIO_OTYPER_OT_12 0x00001000U
AnnaBridge 146:22da6e220af6 7728 #define GPIO_OTYPER_OT_13 0x00002000U
AnnaBridge 146:22da6e220af6 7729 #define GPIO_OTYPER_OT_14 0x00004000U
AnnaBridge 146:22da6e220af6 7730 #define GPIO_OTYPER_OT_15 0x00008000U
AnnaBridge 146:22da6e220af6 7731
AnnaBridge 146:22da6e220af6 7732 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 146:22da6e220af6 7733 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
AnnaBridge 146:22da6e220af6 7734 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 7735 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
AnnaBridge 146:22da6e220af6 7736 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7737 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7738
AnnaBridge 146:22da6e220af6 7739 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
AnnaBridge 146:22da6e220af6 7740 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7741 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
AnnaBridge 146:22da6e220af6 7742 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7743 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7744
AnnaBridge 146:22da6e220af6 7745 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
AnnaBridge 146:22da6e220af6 7746 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7747 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
AnnaBridge 146:22da6e220af6 7748 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7749 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7750
AnnaBridge 146:22da6e220af6 7751 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
AnnaBridge 146:22da6e220af6 7752 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 7753 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
AnnaBridge 146:22da6e220af6 7754 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7755 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7756
AnnaBridge 146:22da6e220af6 7757 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
AnnaBridge 146:22da6e220af6 7758 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 7759 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
AnnaBridge 146:22da6e220af6 7760 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7761 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7762
AnnaBridge 146:22da6e220af6 7763 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
AnnaBridge 146:22da6e220af6 7764 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 7765 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
AnnaBridge 146:22da6e220af6 7766 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7767 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7768
AnnaBridge 146:22da6e220af6 7769 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
AnnaBridge 146:22da6e220af6 7770 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 7771 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
AnnaBridge 146:22da6e220af6 7772 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7773 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7774
AnnaBridge 146:22da6e220af6 7775 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
AnnaBridge 146:22da6e220af6 7776 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 7777 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
AnnaBridge 146:22da6e220af6 7778 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7779 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7780
AnnaBridge 146:22da6e220af6 7781 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
AnnaBridge 146:22da6e220af6 7782 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 7783 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
AnnaBridge 146:22da6e220af6 7784 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7785 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7786
AnnaBridge 146:22da6e220af6 7787 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
AnnaBridge 146:22da6e220af6 7788 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 7789 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
AnnaBridge 146:22da6e220af6 7790 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7791 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7792
AnnaBridge 146:22da6e220af6 7793 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
AnnaBridge 146:22da6e220af6 7794 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 7795 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
AnnaBridge 146:22da6e220af6 7796 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7797 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7798
AnnaBridge 146:22da6e220af6 7799 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
AnnaBridge 146:22da6e220af6 7800 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 7801 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
AnnaBridge 146:22da6e220af6 7802 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7803 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7804
AnnaBridge 146:22da6e220af6 7805 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
AnnaBridge 146:22da6e220af6 7806 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 7807 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
AnnaBridge 146:22da6e220af6 7808 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7809 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7810
AnnaBridge 146:22da6e220af6 7811 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
AnnaBridge 146:22da6e220af6 7812 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 146:22da6e220af6 7813 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
AnnaBridge 146:22da6e220af6 7814 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7815 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7816
AnnaBridge 146:22da6e220af6 7817 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
AnnaBridge 146:22da6e220af6 7818 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7819 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
AnnaBridge 146:22da6e220af6 7820 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7821 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7822
AnnaBridge 146:22da6e220af6 7823 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
AnnaBridge 146:22da6e220af6 7824 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 146:22da6e220af6 7825 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
AnnaBridge 146:22da6e220af6 7826 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 7827 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 7828
AnnaBridge 146:22da6e220af6 7829 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 146:22da6e220af6 7830 #define GPIO_PUPDR_PUPDR0_Pos (0U)
AnnaBridge 146:22da6e220af6 7831 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 7832 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
AnnaBridge 146:22da6e220af6 7833 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7834 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 7835
AnnaBridge 146:22da6e220af6 7836 #define GPIO_PUPDR_PUPDR1_Pos (2U)
AnnaBridge 146:22da6e220af6 7837 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 7838 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
AnnaBridge 146:22da6e220af6 7839 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 7840 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 7841
AnnaBridge 146:22da6e220af6 7842 #define GPIO_PUPDR_PUPDR2_Pos (4U)
AnnaBridge 146:22da6e220af6 7843 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 7844 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
AnnaBridge 146:22da6e220af6 7845 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 7846 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 7847
AnnaBridge 146:22da6e220af6 7848 #define GPIO_PUPDR_PUPDR3_Pos (6U)
AnnaBridge 146:22da6e220af6 7849 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 7850 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
AnnaBridge 146:22da6e220af6 7851 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 7852 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 7853
AnnaBridge 146:22da6e220af6 7854 #define GPIO_PUPDR_PUPDR4_Pos (8U)
AnnaBridge 146:22da6e220af6 7855 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 7856 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
AnnaBridge 146:22da6e220af6 7857 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 7858 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 7859
AnnaBridge 146:22da6e220af6 7860 #define GPIO_PUPDR_PUPDR5_Pos (10U)
AnnaBridge 146:22da6e220af6 7861 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 7862 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
AnnaBridge 146:22da6e220af6 7863 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 7864 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 7865
AnnaBridge 146:22da6e220af6 7866 #define GPIO_PUPDR_PUPDR6_Pos (12U)
AnnaBridge 146:22da6e220af6 7867 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 7868 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
AnnaBridge 146:22da6e220af6 7869 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 7870 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 7871
AnnaBridge 146:22da6e220af6 7872 #define GPIO_PUPDR_PUPDR7_Pos (14U)
AnnaBridge 146:22da6e220af6 7873 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 7874 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
AnnaBridge 146:22da6e220af6 7875 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 7876 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 7877
AnnaBridge 146:22da6e220af6 7878 #define GPIO_PUPDR_PUPDR8_Pos (16U)
AnnaBridge 146:22da6e220af6 7879 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 7880 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
AnnaBridge 146:22da6e220af6 7881 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 7882 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 7883
AnnaBridge 146:22da6e220af6 7884 #define GPIO_PUPDR_PUPDR9_Pos (18U)
AnnaBridge 146:22da6e220af6 7885 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 7886 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
AnnaBridge 146:22da6e220af6 7887 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 7888 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 7889
AnnaBridge 146:22da6e220af6 7890 #define GPIO_PUPDR_PUPDR10_Pos (20U)
AnnaBridge 146:22da6e220af6 7891 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 7892 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
AnnaBridge 146:22da6e220af6 7893 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 7894 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 7895
AnnaBridge 146:22da6e220af6 7896 #define GPIO_PUPDR_PUPDR11_Pos (22U)
AnnaBridge 146:22da6e220af6 7897 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 7898 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
AnnaBridge 146:22da6e220af6 7899 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 7900 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 7901
AnnaBridge 146:22da6e220af6 7902 #define GPIO_PUPDR_PUPDR12_Pos (24U)
AnnaBridge 146:22da6e220af6 7903 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 7904 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
AnnaBridge 146:22da6e220af6 7905 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 7906 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 7907
AnnaBridge 146:22da6e220af6 7908 #define GPIO_PUPDR_PUPDR13_Pos (26U)
AnnaBridge 146:22da6e220af6 7909 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 146:22da6e220af6 7910 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
AnnaBridge 146:22da6e220af6 7911 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 7912 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 7913
AnnaBridge 146:22da6e220af6 7914 #define GPIO_PUPDR_PUPDR14_Pos (28U)
AnnaBridge 146:22da6e220af6 7915 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 7916 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
AnnaBridge 146:22da6e220af6 7917 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 7918 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 7919
AnnaBridge 146:22da6e220af6 7920 #define GPIO_PUPDR_PUPDR15_Pos (30U)
AnnaBridge 146:22da6e220af6 7921 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 146:22da6e220af6 7922 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
AnnaBridge 146:22da6e220af6 7923 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 7924 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 7925
AnnaBridge 146:22da6e220af6 7926 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 146:22da6e220af6 7927 #define GPIO_IDR_IDR_0 0x00000001U
AnnaBridge 146:22da6e220af6 7928 #define GPIO_IDR_IDR_1 0x00000002U
AnnaBridge 146:22da6e220af6 7929 #define GPIO_IDR_IDR_2 0x00000004U
AnnaBridge 146:22da6e220af6 7930 #define GPIO_IDR_IDR_3 0x00000008U
AnnaBridge 146:22da6e220af6 7931 #define GPIO_IDR_IDR_4 0x00000010U
AnnaBridge 146:22da6e220af6 7932 #define GPIO_IDR_IDR_5 0x00000020U
AnnaBridge 146:22da6e220af6 7933 #define GPIO_IDR_IDR_6 0x00000040U
AnnaBridge 146:22da6e220af6 7934 #define GPIO_IDR_IDR_7 0x00000080U
AnnaBridge 146:22da6e220af6 7935 #define GPIO_IDR_IDR_8 0x00000100U
AnnaBridge 146:22da6e220af6 7936 #define GPIO_IDR_IDR_9 0x00000200U
AnnaBridge 146:22da6e220af6 7937 #define GPIO_IDR_IDR_10 0x00000400U
AnnaBridge 146:22da6e220af6 7938 #define GPIO_IDR_IDR_11 0x00000800U
AnnaBridge 146:22da6e220af6 7939 #define GPIO_IDR_IDR_12 0x00001000U
AnnaBridge 146:22da6e220af6 7940 #define GPIO_IDR_IDR_13 0x00002000U
AnnaBridge 146:22da6e220af6 7941 #define GPIO_IDR_IDR_14 0x00004000U
AnnaBridge 146:22da6e220af6 7942 #define GPIO_IDR_IDR_15 0x00008000U
AnnaBridge 146:22da6e220af6 7943
AnnaBridge 146:22da6e220af6 7944 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 146:22da6e220af6 7945 #define GPIO_ODR_ODR_0 0x00000001U
AnnaBridge 146:22da6e220af6 7946 #define GPIO_ODR_ODR_1 0x00000002U
AnnaBridge 146:22da6e220af6 7947 #define GPIO_ODR_ODR_2 0x00000004U
AnnaBridge 146:22da6e220af6 7948 #define GPIO_ODR_ODR_3 0x00000008U
AnnaBridge 146:22da6e220af6 7949 #define GPIO_ODR_ODR_4 0x00000010U
AnnaBridge 146:22da6e220af6 7950 #define GPIO_ODR_ODR_5 0x00000020U
AnnaBridge 146:22da6e220af6 7951 #define GPIO_ODR_ODR_6 0x00000040U
AnnaBridge 146:22da6e220af6 7952 #define GPIO_ODR_ODR_7 0x00000080U
AnnaBridge 146:22da6e220af6 7953 #define GPIO_ODR_ODR_8 0x00000100U
AnnaBridge 146:22da6e220af6 7954 #define GPIO_ODR_ODR_9 0x00000200U
AnnaBridge 146:22da6e220af6 7955 #define GPIO_ODR_ODR_10 0x00000400U
AnnaBridge 146:22da6e220af6 7956 #define GPIO_ODR_ODR_11 0x00000800U
AnnaBridge 146:22da6e220af6 7957 #define GPIO_ODR_ODR_12 0x00001000U
AnnaBridge 146:22da6e220af6 7958 #define GPIO_ODR_ODR_13 0x00002000U
AnnaBridge 146:22da6e220af6 7959 #define GPIO_ODR_ODR_14 0x00004000U
AnnaBridge 146:22da6e220af6 7960 #define GPIO_ODR_ODR_15 0x00008000U
AnnaBridge 146:22da6e220af6 7961
AnnaBridge 146:22da6e220af6 7962 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 146:22da6e220af6 7963 #define GPIO_BSRR_BS_0 0x00000001U
AnnaBridge 146:22da6e220af6 7964 #define GPIO_BSRR_BS_1 0x00000002U
AnnaBridge 146:22da6e220af6 7965 #define GPIO_BSRR_BS_2 0x00000004U
AnnaBridge 146:22da6e220af6 7966 #define GPIO_BSRR_BS_3 0x00000008U
AnnaBridge 146:22da6e220af6 7967 #define GPIO_BSRR_BS_4 0x00000010U
AnnaBridge 146:22da6e220af6 7968 #define GPIO_BSRR_BS_5 0x00000020U
AnnaBridge 146:22da6e220af6 7969 #define GPIO_BSRR_BS_6 0x00000040U
AnnaBridge 146:22da6e220af6 7970 #define GPIO_BSRR_BS_7 0x00000080U
AnnaBridge 146:22da6e220af6 7971 #define GPIO_BSRR_BS_8 0x00000100U
AnnaBridge 146:22da6e220af6 7972 #define GPIO_BSRR_BS_9 0x00000200U
AnnaBridge 146:22da6e220af6 7973 #define GPIO_BSRR_BS_10 0x00000400U
AnnaBridge 146:22da6e220af6 7974 #define GPIO_BSRR_BS_11 0x00000800U
AnnaBridge 146:22da6e220af6 7975 #define GPIO_BSRR_BS_12 0x00001000U
AnnaBridge 146:22da6e220af6 7976 #define GPIO_BSRR_BS_13 0x00002000U
AnnaBridge 146:22da6e220af6 7977 #define GPIO_BSRR_BS_14 0x00004000U
AnnaBridge 146:22da6e220af6 7978 #define GPIO_BSRR_BS_15 0x00008000U
AnnaBridge 146:22da6e220af6 7979 #define GPIO_BSRR_BR_0 0x00010000U
AnnaBridge 146:22da6e220af6 7980 #define GPIO_BSRR_BR_1 0x00020000U
AnnaBridge 146:22da6e220af6 7981 #define GPIO_BSRR_BR_2 0x00040000U
AnnaBridge 146:22da6e220af6 7982 #define GPIO_BSRR_BR_3 0x00080000U
AnnaBridge 146:22da6e220af6 7983 #define GPIO_BSRR_BR_4 0x00100000U
AnnaBridge 146:22da6e220af6 7984 #define GPIO_BSRR_BR_5 0x00200000U
AnnaBridge 146:22da6e220af6 7985 #define GPIO_BSRR_BR_6 0x00400000U
AnnaBridge 146:22da6e220af6 7986 #define GPIO_BSRR_BR_7 0x00800000U
AnnaBridge 146:22da6e220af6 7987 #define GPIO_BSRR_BR_8 0x01000000U
AnnaBridge 146:22da6e220af6 7988 #define GPIO_BSRR_BR_9 0x02000000U
AnnaBridge 146:22da6e220af6 7989 #define GPIO_BSRR_BR_10 0x04000000U
AnnaBridge 146:22da6e220af6 7990 #define GPIO_BSRR_BR_11 0x08000000U
AnnaBridge 146:22da6e220af6 7991 #define GPIO_BSRR_BR_12 0x10000000U
AnnaBridge 146:22da6e220af6 7992 #define GPIO_BSRR_BR_13 0x20000000U
AnnaBridge 146:22da6e220af6 7993 #define GPIO_BSRR_BR_14 0x40000000U
AnnaBridge 146:22da6e220af6 7994 #define GPIO_BSRR_BR_15 0x80000000U
AnnaBridge 146:22da6e220af6 7995 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 146:22da6e220af6 7996 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 146:22da6e220af6 7997 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 7998 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 146:22da6e220af6 7999 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 146:22da6e220af6 8000 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8001 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 146:22da6e220af6 8002 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 146:22da6e220af6 8003 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8004 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 146:22da6e220af6 8005 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 146:22da6e220af6 8006 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8007 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 146:22da6e220af6 8008 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 146:22da6e220af6 8009 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8010 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 146:22da6e220af6 8011 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 146:22da6e220af6 8012 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8013 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 146:22da6e220af6 8014 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 146:22da6e220af6 8015 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8016 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 146:22da6e220af6 8017 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 146:22da6e220af6 8018 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8019 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 146:22da6e220af6 8020 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 146:22da6e220af6 8021 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8022 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 146:22da6e220af6 8023 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 146:22da6e220af6 8024 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8025 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 146:22da6e220af6 8026 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 146:22da6e220af6 8027 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8028 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 146:22da6e220af6 8029 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 146:22da6e220af6 8030 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8031 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 146:22da6e220af6 8032 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 146:22da6e220af6 8033 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8034 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 146:22da6e220af6 8035 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 146:22da6e220af6 8036 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8037 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 146:22da6e220af6 8038 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 146:22da6e220af6 8039 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8040 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 146:22da6e220af6 8041 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 146:22da6e220af6 8042 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8043 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 146:22da6e220af6 8044 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 146:22da6e220af6 8045 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8046 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 146:22da6e220af6 8047 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 146:22da6e220af6 8048 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 146:22da6e220af6 8049 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 8050 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 146:22da6e220af6 8051 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8052 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8053 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8054 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8055 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 146:22da6e220af6 8056 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 8057 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 146:22da6e220af6 8058 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8059 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8060 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8061 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8062 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 146:22da6e220af6 8063 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 8064 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 146:22da6e220af6 8065 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8066 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8067 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8068 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8069 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 146:22da6e220af6 8070 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 8071 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 146:22da6e220af6 8072 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8073 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8074 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8075 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8076 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 146:22da6e220af6 8077 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 8078 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 146:22da6e220af6 8079 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8080 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 8081 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 8082 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 8083 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 146:22da6e220af6 8084 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 8085 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 146:22da6e220af6 8086 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8087 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 8088 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 8089 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 8090 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 146:22da6e220af6 8091 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 8092 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 146:22da6e220af6 8093 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 8094 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 8095 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 8096 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 8097 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 146:22da6e220af6 8098 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 146:22da6e220af6 8099 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 146:22da6e220af6 8100 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 8101 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 8102 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 8103 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 8104
AnnaBridge 146:22da6e220af6 8105 /* Legacy defines */
AnnaBridge 146:22da6e220af6 8106 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 146:22da6e220af6 8107 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 146:22da6e220af6 8108 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 146:22da6e220af6 8109 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 146:22da6e220af6 8110 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 146:22da6e220af6 8111 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 146:22da6e220af6 8112 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 146:22da6e220af6 8113 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 146:22da6e220af6 8114 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 146:22da6e220af6 8115 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 146:22da6e220af6 8116 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 146:22da6e220af6 8117 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 146:22da6e220af6 8118 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 146:22da6e220af6 8119 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 146:22da6e220af6 8120 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 146:22da6e220af6 8121 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 146:22da6e220af6 8122 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 146:22da6e220af6 8123 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 146:22da6e220af6 8124 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 146:22da6e220af6 8125 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 146:22da6e220af6 8126 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 146:22da6e220af6 8127 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 146:22da6e220af6 8128 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 146:22da6e220af6 8129 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 146:22da6e220af6 8130 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 146:22da6e220af6 8131 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 146:22da6e220af6 8132 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 146:22da6e220af6 8133 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 146:22da6e220af6 8134 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 146:22da6e220af6 8135 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 146:22da6e220af6 8136 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 146:22da6e220af6 8137 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 146:22da6e220af6 8138 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 146:22da6e220af6 8139 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 146:22da6e220af6 8140 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 146:22da6e220af6 8141 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 146:22da6e220af6 8142 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 146:22da6e220af6 8143 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 146:22da6e220af6 8144 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 146:22da6e220af6 8145 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 146:22da6e220af6 8146
AnnaBridge 146:22da6e220af6 8147 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 146:22da6e220af6 8148 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 146:22da6e220af6 8149 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 8150 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 146:22da6e220af6 8151 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8152 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8153 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8154 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8155 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 146:22da6e220af6 8156 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 8157 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 146:22da6e220af6 8158 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8159 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8160 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8161 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8162 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 146:22da6e220af6 8163 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 8164 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 146:22da6e220af6 8165 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8166 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8167 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8168 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8169 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 146:22da6e220af6 8170 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 8171 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 146:22da6e220af6 8172 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8173 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8174 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8175 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8176 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 146:22da6e220af6 8177 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 8178 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 146:22da6e220af6 8179 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8180 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 8181 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 8182 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 8183 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 146:22da6e220af6 8184 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 8185 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 146:22da6e220af6 8186 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8187 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 8188 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 8189 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 8190 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 146:22da6e220af6 8191 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 8192 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 146:22da6e220af6 8193 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 8194 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 8195 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 8196 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 8197 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 146:22da6e220af6 8198 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 146:22da6e220af6 8199 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 146:22da6e220af6 8200 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 8201 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 8202 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 8203 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 8204
AnnaBridge 146:22da6e220af6 8205 /* Legacy defines */
AnnaBridge 146:22da6e220af6 8206 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 146:22da6e220af6 8207 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 146:22da6e220af6 8208 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 146:22da6e220af6 8209 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 146:22da6e220af6 8210 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 146:22da6e220af6 8211 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 146:22da6e220af6 8212 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 146:22da6e220af6 8213 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 146:22da6e220af6 8214 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 146:22da6e220af6 8215 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 146:22da6e220af6 8216 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 146:22da6e220af6 8217 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 146:22da6e220af6 8218 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 146:22da6e220af6 8219 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 146:22da6e220af6 8220 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 146:22da6e220af6 8221 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 146:22da6e220af6 8222 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 146:22da6e220af6 8223 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 146:22da6e220af6 8224 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 146:22da6e220af6 8225 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 146:22da6e220af6 8226 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 146:22da6e220af6 8227 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 146:22da6e220af6 8228 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 146:22da6e220af6 8229 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 146:22da6e220af6 8230 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 146:22da6e220af6 8231 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 146:22da6e220af6 8232 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 146:22da6e220af6 8233 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 146:22da6e220af6 8234 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 146:22da6e220af6 8235 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 146:22da6e220af6 8236 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 146:22da6e220af6 8237 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 146:22da6e220af6 8238 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 146:22da6e220af6 8239 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 146:22da6e220af6 8240 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 146:22da6e220af6 8241 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 146:22da6e220af6 8242 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 146:22da6e220af6 8243 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 146:22da6e220af6 8244 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 146:22da6e220af6 8245 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 146:22da6e220af6 8246
AnnaBridge 146:22da6e220af6 8247 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 146:22da6e220af6 8248 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 146:22da6e220af6 8249 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8250 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 146:22da6e220af6 8251 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 146:22da6e220af6 8252 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8253 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 146:22da6e220af6 8254 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 146:22da6e220af6 8255 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8256 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 146:22da6e220af6 8257 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 146:22da6e220af6 8258 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8259 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 146:22da6e220af6 8260 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 146:22da6e220af6 8261 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8262 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 146:22da6e220af6 8263 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 146:22da6e220af6 8264 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8265 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 146:22da6e220af6 8266 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 146:22da6e220af6 8267 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8268 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 146:22da6e220af6 8269 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 146:22da6e220af6 8270 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8271 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 146:22da6e220af6 8272 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 146:22da6e220af6 8273 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8274 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 146:22da6e220af6 8275 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 146:22da6e220af6 8276 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8277 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 146:22da6e220af6 8278 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 146:22da6e220af6 8279 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8280 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 146:22da6e220af6 8281 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 146:22da6e220af6 8282 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8283 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 146:22da6e220af6 8284 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 146:22da6e220af6 8285 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8286 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 146:22da6e220af6 8287 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 146:22da6e220af6 8288 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8289 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 146:22da6e220af6 8290 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 146:22da6e220af6 8291 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8292 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 146:22da6e220af6 8293 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 146:22da6e220af6 8294 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8295 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 146:22da6e220af6 8296
AnnaBridge 146:22da6e220af6 8297
AnnaBridge 146:22da6e220af6 8298 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8299 /* */
AnnaBridge 146:22da6e220af6 8300 /* Inter-integrated Circuit Interface */
AnnaBridge 146:22da6e220af6 8301 /* */
AnnaBridge 146:22da6e220af6 8302 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8303 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 146:22da6e220af6 8304 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 146:22da6e220af6 8305 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8306 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 146:22da6e220af6 8307 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 146:22da6e220af6 8308 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8309 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 146:22da6e220af6 8310 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 146:22da6e220af6 8311 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8312 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 146:22da6e220af6 8313 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 146:22da6e220af6 8314 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8315 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 146:22da6e220af6 8316 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 146:22da6e220af6 8317 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8318 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 146:22da6e220af6 8319 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 146:22da6e220af6 8320 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8321 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 146:22da6e220af6 8322 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 146:22da6e220af6 8323 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8324 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 146:22da6e220af6 8325 #define I2C_CR1_START_Pos (8U)
AnnaBridge 146:22da6e220af6 8326 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8327 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 146:22da6e220af6 8328 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 146:22da6e220af6 8329 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8330 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 146:22da6e220af6 8331 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 146:22da6e220af6 8332 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8333 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 146:22da6e220af6 8334 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 146:22da6e220af6 8335 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8336 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 146:22da6e220af6 8337 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 146:22da6e220af6 8338 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8339 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 146:22da6e220af6 8340 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 146:22da6e220af6 8341 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8342 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 146:22da6e220af6 8343 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 146:22da6e220af6 8344 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8345 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
AnnaBridge 146:22da6e220af6 8346
AnnaBridge 146:22da6e220af6 8347 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 146:22da6e220af6 8348 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 146:22da6e220af6 8349 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 8350 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 146:22da6e220af6 8351 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8352 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8353 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8354 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8355 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8356 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8357
AnnaBridge 146:22da6e220af6 8358 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 146:22da6e220af6 8359 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8360 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 8361 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 146:22da6e220af6 8362 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8363 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 146:22da6e220af6 8364 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 146:22da6e220af6 8365 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8366 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 146:22da6e220af6 8367 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 146:22da6e220af6 8368 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8369 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 146:22da6e220af6 8370 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 146:22da6e220af6 8371 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8372 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
AnnaBridge 146:22da6e220af6 8373
AnnaBridge 146:22da6e220af6 8374 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 146:22da6e220af6 8375 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 146:22da6e220af6 8376 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 146:22da6e220af6 8377
AnnaBridge 146:22da6e220af6 8378 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 146:22da6e220af6 8379 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8380 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 146:22da6e220af6 8381 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 146:22da6e220af6 8382 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8383 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 146:22da6e220af6 8384 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 146:22da6e220af6 8385 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8386 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 146:22da6e220af6 8387 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 146:22da6e220af6 8388 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8389 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 146:22da6e220af6 8390 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 146:22da6e220af6 8391 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8392 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 146:22da6e220af6 8393 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 146:22da6e220af6 8394 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8395 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 146:22da6e220af6 8396 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 146:22da6e220af6 8397 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8398 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 146:22da6e220af6 8399 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 146:22da6e220af6 8400 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8401 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 146:22da6e220af6 8402 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 146:22da6e220af6 8403 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8404 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 146:22da6e220af6 8405 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 146:22da6e220af6 8406 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8407 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 146:22da6e220af6 8408
AnnaBridge 146:22da6e220af6 8409 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 146:22da6e220af6 8410 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8411 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
AnnaBridge 146:22da6e220af6 8412
AnnaBridge 146:22da6e220af6 8413 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 146:22da6e220af6 8414 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 146:22da6e220af6 8415 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8416 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 146:22da6e220af6 8417 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 146:22da6e220af6 8418 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 146:22da6e220af6 8419 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
AnnaBridge 146:22da6e220af6 8420
AnnaBridge 146:22da6e220af6 8421 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 146:22da6e220af6 8422 #define I2C_DR_DR_Pos (0U)
AnnaBridge 146:22da6e220af6 8423 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 8424 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
AnnaBridge 146:22da6e220af6 8425
AnnaBridge 146:22da6e220af6 8426 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 146:22da6e220af6 8427 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 146:22da6e220af6 8428 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8429 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 146:22da6e220af6 8430 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 146:22da6e220af6 8431 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8432 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 146:22da6e220af6 8433 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 146:22da6e220af6 8434 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8435 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 146:22da6e220af6 8436 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 146:22da6e220af6 8437 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8438 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 146:22da6e220af6 8439 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 146:22da6e220af6 8440 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8441 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 146:22da6e220af6 8442 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 146:22da6e220af6 8443 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8444 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 146:22da6e220af6 8445 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 146:22da6e220af6 8446 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8447 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 146:22da6e220af6 8448 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 146:22da6e220af6 8449 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8450 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 146:22da6e220af6 8451 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 146:22da6e220af6 8452 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8453 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 146:22da6e220af6 8454 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 146:22da6e220af6 8455 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8456 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 146:22da6e220af6 8457 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 146:22da6e220af6 8458 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8459 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 146:22da6e220af6 8460 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 146:22da6e220af6 8461 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8462 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 146:22da6e220af6 8463 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 146:22da6e220af6 8464 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8465 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 146:22da6e220af6 8466 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 146:22da6e220af6 8467 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8468 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
AnnaBridge 146:22da6e220af6 8469
AnnaBridge 146:22da6e220af6 8470 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 146:22da6e220af6 8471 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 146:22da6e220af6 8472 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8473 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 146:22da6e220af6 8474 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 146:22da6e220af6 8475 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8476 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 146:22da6e220af6 8477 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 146:22da6e220af6 8478 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8479 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 146:22da6e220af6 8480 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 146:22da6e220af6 8481 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8482 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 146:22da6e220af6 8483 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 146:22da6e220af6 8484 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8485 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 146:22da6e220af6 8486 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 146:22da6e220af6 8487 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8488 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 146:22da6e220af6 8489 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 146:22da6e220af6 8490 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8491 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 146:22da6e220af6 8492 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 146:22da6e220af6 8493 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 8494 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
AnnaBridge 146:22da6e220af6 8495
AnnaBridge 146:22da6e220af6 8496 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 146:22da6e220af6 8497 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 146:22da6e220af6 8498 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 8499 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 146:22da6e220af6 8500 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 146:22da6e220af6 8501 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8502 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 146:22da6e220af6 8503 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 146:22da6e220af6 8504 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8505 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
AnnaBridge 146:22da6e220af6 8506
AnnaBridge 146:22da6e220af6 8507 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 146:22da6e220af6 8508 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 146:22da6e220af6 8509 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 8510 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 146:22da6e220af6 8511
AnnaBridge 146:22da6e220af6 8512 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 146:22da6e220af6 8513 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 146:22da6e220af6 8514 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 8515 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 146:22da6e220af6 8516 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 146:22da6e220af6 8517 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8518 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
AnnaBridge 146:22da6e220af6 8519
AnnaBridge 146:22da6e220af6 8520 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8521 /* */
AnnaBridge 146:22da6e220af6 8522 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
AnnaBridge 146:22da6e220af6 8523 /* */
AnnaBridge 146:22da6e220af6 8524 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8525 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 146:22da6e220af6 8526 #define FMPI2C_CR1_PE_Pos (0U)
AnnaBridge 146:22da6e220af6 8527 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8528 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 146:22da6e220af6 8529 #define FMPI2C_CR1_TXIE_Pos (1U)
AnnaBridge 146:22da6e220af6 8530 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8531 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 146:22da6e220af6 8532 #define FMPI2C_CR1_RXIE_Pos (2U)
AnnaBridge 146:22da6e220af6 8533 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8534 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 146:22da6e220af6 8535 #define FMPI2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 146:22da6e220af6 8536 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8537 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 146:22da6e220af6 8538 #define FMPI2C_CR1_NACKIE_Pos (4U)
AnnaBridge 146:22da6e220af6 8539 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8540 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 146:22da6e220af6 8541 #define FMPI2C_CR1_STOPIE_Pos (5U)
AnnaBridge 146:22da6e220af6 8542 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8543 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 146:22da6e220af6 8544 #define FMPI2C_CR1_TCIE_Pos (6U)
AnnaBridge 146:22da6e220af6 8545 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8546 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 146:22da6e220af6 8547 #define FMPI2C_CR1_ERRIE_Pos (7U)
AnnaBridge 146:22da6e220af6 8548 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8549 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 146:22da6e220af6 8550 #define FMPI2C_CR1_DFN_Pos (8U)
AnnaBridge 146:22da6e220af6 8551 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 8552 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
AnnaBridge 146:22da6e220af6 8553 #define FMPI2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 146:22da6e220af6 8554 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8555 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 146:22da6e220af6 8556 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 146:22da6e220af6 8557 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8558 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 146:22da6e220af6 8559 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 146:22da6e220af6 8560 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8561 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 146:22da6e220af6 8562 #define FMPI2C_CR1_SBC_Pos (16U)
AnnaBridge 146:22da6e220af6 8563 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8564 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 146:22da6e220af6 8565 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 146:22da6e220af6 8566 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 8567 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 146:22da6e220af6 8568 #define FMPI2C_CR1_GCEN_Pos (19U)
AnnaBridge 146:22da6e220af6 8569 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 8570 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 146:22da6e220af6 8571 #define FMPI2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 146:22da6e220af6 8572 #define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8573 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 146:22da6e220af6 8574 #define FMPI2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 146:22da6e220af6 8575 #define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 8576 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 146:22da6e220af6 8577 #define FMPI2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 146:22da6e220af6 8578 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 8579 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 146:22da6e220af6 8580 #define FMPI2C_CR1_PECEN_Pos (23U)
AnnaBridge 146:22da6e220af6 8581 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 8582 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 146:22da6e220af6 8583
AnnaBridge 146:22da6e220af6 8584 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 146:22da6e220af6 8585 #define FMPI2C_CR2_SADD_Pos (0U)
AnnaBridge 146:22da6e220af6 8586 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 146:22da6e220af6 8587 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 146:22da6e220af6 8588 #define FMPI2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 146:22da6e220af6 8589 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8590 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 146:22da6e220af6 8591 #define FMPI2C_CR2_ADD10_Pos (11U)
AnnaBridge 146:22da6e220af6 8592 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8593 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 146:22da6e220af6 8594 #define FMPI2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 146:22da6e220af6 8595 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8596 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 146:22da6e220af6 8597 #define FMPI2C_CR2_START_Pos (13U)
AnnaBridge 146:22da6e220af6 8598 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8599 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
AnnaBridge 146:22da6e220af6 8600 #define FMPI2C_CR2_STOP_Pos (14U)
AnnaBridge 146:22da6e220af6 8601 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8602 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 146:22da6e220af6 8603 #define FMPI2C_CR2_NACK_Pos (15U)
AnnaBridge 146:22da6e220af6 8604 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8605 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 146:22da6e220af6 8606 #define FMPI2C_CR2_NBYTES_Pos (16U)
AnnaBridge 146:22da6e220af6 8607 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 8608 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 146:22da6e220af6 8609 #define FMPI2C_CR2_RELOAD_Pos (24U)
AnnaBridge 146:22da6e220af6 8610 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 8611 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 146:22da6e220af6 8612 #define FMPI2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 146:22da6e220af6 8613 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 8614 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 146:22da6e220af6 8615 #define FMPI2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 146:22da6e220af6 8616 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 8617 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 146:22da6e220af6 8618
AnnaBridge 146:22da6e220af6 8619 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 146:22da6e220af6 8620 #define FMPI2C_OAR1_OA1_Pos (0U)
AnnaBridge 146:22da6e220af6 8621 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 146:22da6e220af6 8622 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 146:22da6e220af6 8623 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 146:22da6e220af6 8624 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8625 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 146:22da6e220af6 8626 #define FMPI2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 146:22da6e220af6 8627 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8628 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 146:22da6e220af6 8629
AnnaBridge 146:22da6e220af6 8630 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 146:22da6e220af6 8631 #define FMPI2C_OAR2_OA2_Pos (1U)
AnnaBridge 146:22da6e220af6 8632 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 146:22da6e220af6 8633 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 146:22da6e220af6 8634 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 146:22da6e220af6 8635 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 146:22da6e220af6 8636 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 146:22da6e220af6 8637 #define FMPI2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 146:22da6e220af6 8638 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8639 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 146:22da6e220af6 8640
AnnaBridge 146:22da6e220af6 8641 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 146:22da6e220af6 8642 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 146:22da6e220af6 8643 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 8644 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 146:22da6e220af6 8645 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 146:22da6e220af6 8646 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 8647 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 146:22da6e220af6 8648 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 146:22da6e220af6 8649 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 8650 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 146:22da6e220af6 8651 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 146:22da6e220af6 8652 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 8653 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 146:22da6e220af6 8654 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 146:22da6e220af6 8655 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 146:22da6e220af6 8656 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 146:22da6e220af6 8657
AnnaBridge 146:22da6e220af6 8658 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 146:22da6e220af6 8659 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 146:22da6e220af6 8660 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 8661 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 146:22da6e220af6 8662 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 146:22da6e220af6 8663 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8664 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 146:22da6e220af6 8665 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 146:22da6e220af6 8666 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8667 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 146:22da6e220af6 8668 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 146:22da6e220af6 8669 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 146:22da6e220af6 8670 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
AnnaBridge 146:22da6e220af6 8671 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 146:22da6e220af6 8672 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 8673 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 146:22da6e220af6 8674
AnnaBridge 146:22da6e220af6 8675 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 146:22da6e220af6 8676 #define FMPI2C_ISR_TXE_Pos (0U)
AnnaBridge 146:22da6e220af6 8677 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8678 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 146:22da6e220af6 8679 #define FMPI2C_ISR_TXIS_Pos (1U)
AnnaBridge 146:22da6e220af6 8680 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8681 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 146:22da6e220af6 8682 #define FMPI2C_ISR_RXNE_Pos (2U)
AnnaBridge 146:22da6e220af6 8683 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8684 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 146:22da6e220af6 8685 #define FMPI2C_ISR_ADDR_Pos (3U)
AnnaBridge 146:22da6e220af6 8686 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8687 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
AnnaBridge 146:22da6e220af6 8688 #define FMPI2C_ISR_NACKF_Pos (4U)
AnnaBridge 146:22da6e220af6 8689 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8690 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 146:22da6e220af6 8691 #define FMPI2C_ISR_STOPF_Pos (5U)
AnnaBridge 146:22da6e220af6 8692 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8693 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 146:22da6e220af6 8694 #define FMPI2C_ISR_TC_Pos (6U)
AnnaBridge 146:22da6e220af6 8695 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8696 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 146:22da6e220af6 8697 #define FMPI2C_ISR_TCR_Pos (7U)
AnnaBridge 146:22da6e220af6 8698 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8699 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 146:22da6e220af6 8700 #define FMPI2C_ISR_BERR_Pos (8U)
AnnaBridge 146:22da6e220af6 8701 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8702 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 146:22da6e220af6 8703 #define FMPI2C_ISR_ARLO_Pos (9U)
AnnaBridge 146:22da6e220af6 8704 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8705 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 146:22da6e220af6 8706 #define FMPI2C_ISR_OVR_Pos (10U)
AnnaBridge 146:22da6e220af6 8707 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8708 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 146:22da6e220af6 8709 #define FMPI2C_ISR_PECERR_Pos (11U)
AnnaBridge 146:22da6e220af6 8710 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8711 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 146:22da6e220af6 8712 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 146:22da6e220af6 8713 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8714 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 146:22da6e220af6 8715 #define FMPI2C_ISR_ALERT_Pos (13U)
AnnaBridge 146:22da6e220af6 8716 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8717 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 146:22da6e220af6 8718 #define FMPI2C_ISR_BUSY_Pos (15U)
AnnaBridge 146:22da6e220af6 8719 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 8720 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 146:22da6e220af6 8721 #define FMPI2C_ISR_DIR_Pos (16U)
AnnaBridge 146:22da6e220af6 8722 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8723 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 146:22da6e220af6 8724 #define FMPI2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 146:22da6e220af6 8725 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 146:22da6e220af6 8726 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 146:22da6e220af6 8727
AnnaBridge 146:22da6e220af6 8728 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 146:22da6e220af6 8729 #define FMPI2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 146:22da6e220af6 8730 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8731 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 146:22da6e220af6 8732 #define FMPI2C_ICR_NACKCF_Pos (4U)
AnnaBridge 146:22da6e220af6 8733 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8734 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 146:22da6e220af6 8735 #define FMPI2C_ICR_STOPCF_Pos (5U)
AnnaBridge 146:22da6e220af6 8736 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8737 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 146:22da6e220af6 8738 #define FMPI2C_ICR_BERRCF_Pos (8U)
AnnaBridge 146:22da6e220af6 8739 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8740 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 146:22da6e220af6 8741 #define FMPI2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 146:22da6e220af6 8742 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8743 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 146:22da6e220af6 8744 #define FMPI2C_ICR_OVRCF_Pos (10U)
AnnaBridge 146:22da6e220af6 8745 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8746 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 146:22da6e220af6 8747 #define FMPI2C_ICR_PECCF_Pos (11U)
AnnaBridge 146:22da6e220af6 8748 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8749 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 146:22da6e220af6 8750 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 146:22da6e220af6 8751 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8752 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 146:22da6e220af6 8753 #define FMPI2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 146:22da6e220af6 8754 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8755 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 146:22da6e220af6 8756
AnnaBridge 146:22da6e220af6 8757 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 146:22da6e220af6 8758 #define FMPI2C_PECR_PEC_Pos (0U)
AnnaBridge 146:22da6e220af6 8759 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 8760 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 146:22da6e220af6 8761
AnnaBridge 146:22da6e220af6 8762 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 146:22da6e220af6 8763 #define FMPI2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 8764 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 8765 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 146:22da6e220af6 8766
AnnaBridge 146:22da6e220af6 8767 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 146:22da6e220af6 8768 #define FMPI2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 146:22da6e220af6 8769 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 8770 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 146:22da6e220af6 8771
AnnaBridge 146:22da6e220af6 8772
AnnaBridge 146:22da6e220af6 8773
AnnaBridge 146:22da6e220af6 8774 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8775 /* */
AnnaBridge 146:22da6e220af6 8776 /* Independent WATCHDOG */
AnnaBridge 146:22da6e220af6 8777 /* */
AnnaBridge 146:22da6e220af6 8778 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8779 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 146:22da6e220af6 8780 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 146:22da6e220af6 8781 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 8782 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 146:22da6e220af6 8783
AnnaBridge 146:22da6e220af6 8784 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 146:22da6e220af6 8785 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 146:22da6e220af6 8786 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 8787 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 146:22da6e220af6 8788 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 146:22da6e220af6 8789 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 146:22da6e220af6 8790 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 146:22da6e220af6 8791
AnnaBridge 146:22da6e220af6 8792 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 146:22da6e220af6 8793 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 146:22da6e220af6 8794 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 8795 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 146:22da6e220af6 8796
AnnaBridge 146:22da6e220af6 8797 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 146:22da6e220af6 8798 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 146:22da6e220af6 8799 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8800 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 146:22da6e220af6 8801 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 146:22da6e220af6 8802 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8803 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 146:22da6e220af6 8804
AnnaBridge 146:22da6e220af6 8805
AnnaBridge 146:22da6e220af6 8806
AnnaBridge 146:22da6e220af6 8807 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8808 /* */
AnnaBridge 146:22da6e220af6 8809 /* Power Control */
AnnaBridge 146:22da6e220af6 8810 /* */
AnnaBridge 146:22da6e220af6 8811 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8812 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 146:22da6e220af6 8813 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 146:22da6e220af6 8814 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8815 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 146:22da6e220af6 8816 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 146:22da6e220af6 8817 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8818 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 146:22da6e220af6 8819 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 146:22da6e220af6 8820 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8821 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 146:22da6e220af6 8822 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 146:22da6e220af6 8823 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8824 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 146:22da6e220af6 8825 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 146:22da6e220af6 8826 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8827 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 146:22da6e220af6 8828
AnnaBridge 146:22da6e220af6 8829 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 146:22da6e220af6 8830 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 146:22da6e220af6 8831 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 146:22da6e220af6 8832 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 8833 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8834 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8835
AnnaBridge 146:22da6e220af6 8836 /*!< PVD level configuration */
AnnaBridge 146:22da6e220af6 8837 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 146:22da6e220af6 8838 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 146:22da6e220af6 8839 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 146:22da6e220af6 8840 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 146:22da6e220af6 8841 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 146:22da6e220af6 8842 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 146:22da6e220af6 8843 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 146:22da6e220af6 8844 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 146:22da6e220af6 8845 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 146:22da6e220af6 8846 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8847 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 146:22da6e220af6 8848 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 146:22da6e220af6 8849 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8850 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 146:22da6e220af6 8851 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 146:22da6e220af6 8852 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8853 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 146:22da6e220af6 8854 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 146:22da6e220af6 8855 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8856 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 146:22da6e220af6 8857 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 146:22da6e220af6 8858 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 8859 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 146:22da6e220af6 8860 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 146:22da6e220af6 8861 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 8862 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 146:22da6e220af6 8863 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 146:22da6e220af6 8864 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 146:22da6e220af6 8865 #define PWR_CR_FMSSR_Pos (20U)
AnnaBridge 146:22da6e220af6 8866 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8867 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
AnnaBridge 146:22da6e220af6 8868 #define PWR_CR_FISSR_Pos (21U)
AnnaBridge 146:22da6e220af6 8869 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 8870 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
AnnaBridge 146:22da6e220af6 8871
AnnaBridge 146:22da6e220af6 8872
AnnaBridge 146:22da6e220af6 8873 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 146:22da6e220af6 8874 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 146:22da6e220af6 8875 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8876 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 146:22da6e220af6 8877 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 146:22da6e220af6 8878 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8879 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 146:22da6e220af6 8880 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 146:22da6e220af6 8881 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8882 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 146:22da6e220af6 8883 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 146:22da6e220af6 8884 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8885 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 163:e59c8e839560 8886 #define PWR_CSR_EWUP3_Pos (6U)
AnnaBridge 163:e59c8e839560 8887 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
AnnaBridge 163:e59c8e839560 8888 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
AnnaBridge 163:e59c8e839560 8889 #define PWR_CSR_EWUP2_Pos (7U)
AnnaBridge 163:e59c8e839560 8890 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
AnnaBridge 163:e59c8e839560 8891 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 163:e59c8e839560 8892 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 163:e59c8e839560 8893 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 163:e59c8e839560 8894 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 146:22da6e220af6 8895 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 146:22da6e220af6 8896 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8897 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 146:22da6e220af6 8898 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 146:22da6e220af6 8899 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 8900 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 146:22da6e220af6 8901
AnnaBridge 146:22da6e220af6 8902
AnnaBridge 146:22da6e220af6 8903 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8904 /* */
AnnaBridge 146:22da6e220af6 8905 /* QUADSPI */
AnnaBridge 146:22da6e220af6 8906 /* */
AnnaBridge 146:22da6e220af6 8907 /******************************************************************************/
AnnaBridge 146:22da6e220af6 8908 /***************** Bit definition for QUADSPI_CR register *******************/
AnnaBridge 146:22da6e220af6 8909 #define QUADSPI_CR_EN_Pos (0U)
AnnaBridge 146:22da6e220af6 8910 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8911 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
AnnaBridge 146:22da6e220af6 8912 #define QUADSPI_CR_ABORT_Pos (1U)
AnnaBridge 146:22da6e220af6 8913 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8914 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
AnnaBridge 146:22da6e220af6 8915 #define QUADSPI_CR_DMAEN_Pos (2U)
AnnaBridge 146:22da6e220af6 8916 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8917 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
AnnaBridge 146:22da6e220af6 8918 #define QUADSPI_CR_TCEN_Pos (3U)
AnnaBridge 146:22da6e220af6 8919 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 8920 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
AnnaBridge 146:22da6e220af6 8921 #define QUADSPI_CR_SSHIFT_Pos (4U)
AnnaBridge 146:22da6e220af6 8922 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 8923 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
AnnaBridge 146:22da6e220af6 8924 #define QUADSPI_CR_DFM_Pos (6U)
AnnaBridge 146:22da6e220af6 8925 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 8926 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
AnnaBridge 146:22da6e220af6 8927 #define QUADSPI_CR_FSEL_Pos (7U)
AnnaBridge 146:22da6e220af6 8928 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 8929 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
AnnaBridge 146:22da6e220af6 8930 #define QUADSPI_CR_FTHRES_Pos (8U)
AnnaBridge 146:22da6e220af6 8931 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
AnnaBridge 146:22da6e220af6 8932 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
AnnaBridge 146:22da6e220af6 8933 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8934 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8935 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8936 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 8937 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 8938 #define QUADSPI_CR_TEIE_Pos (16U)
AnnaBridge 146:22da6e220af6 8939 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8940 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 8941 #define QUADSPI_CR_TCIE_Pos (17U)
AnnaBridge 146:22da6e220af6 8942 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 8943 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 146:22da6e220af6 8944 #define QUADSPI_CR_FTIE_Pos (18U)
AnnaBridge 146:22da6e220af6 8945 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 8946 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
AnnaBridge 146:22da6e220af6 8947 #define QUADSPI_CR_SMIE_Pos (19U)
AnnaBridge 146:22da6e220af6 8948 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 8949 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
AnnaBridge 146:22da6e220af6 8950 #define QUADSPI_CR_TOIE_Pos (20U)
AnnaBridge 146:22da6e220af6 8951 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8952 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
AnnaBridge 146:22da6e220af6 8953 #define QUADSPI_CR_APMS_Pos (22U)
AnnaBridge 146:22da6e220af6 8954 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 8955 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
AnnaBridge 146:22da6e220af6 8956 #define QUADSPI_CR_PMM_Pos (23U)
AnnaBridge 146:22da6e220af6 8957 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 8958 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
AnnaBridge 146:22da6e220af6 8959 #define QUADSPI_CR_PRESCALER_Pos (24U)
AnnaBridge 146:22da6e220af6 8960 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 8961 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
AnnaBridge 146:22da6e220af6 8962 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 8963 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 8964 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 8965 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 8966 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 8967 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 8968 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 8969 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 8970
AnnaBridge 146:22da6e220af6 8971 /***************** Bit definition for QUADSPI_DCR register ******************/
AnnaBridge 146:22da6e220af6 8972 #define QUADSPI_DCR_CKMODE_Pos (0U)
AnnaBridge 146:22da6e220af6 8973 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8974 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
AnnaBridge 146:22da6e220af6 8975 #define QUADSPI_DCR_CSHT_Pos (8U)
AnnaBridge 146:22da6e220af6 8976 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
AnnaBridge 146:22da6e220af6 8977 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
AnnaBridge 146:22da6e220af6 8978 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 8979 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 8980 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 8981 #define QUADSPI_DCR_FSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 8982 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
AnnaBridge 146:22da6e220af6 8983 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
AnnaBridge 146:22da6e220af6 8984 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 8985 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 8986 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 8987 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 8988 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 8989
AnnaBridge 146:22da6e220af6 8990 /****************** Bit definition for QUADSPI_SR register *******************/
AnnaBridge 146:22da6e220af6 8991 #define QUADSPI_SR_TEF_Pos (0U)
AnnaBridge 146:22da6e220af6 8992 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 8993 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
AnnaBridge 146:22da6e220af6 8994 #define QUADSPI_SR_TCF_Pos (1U)
AnnaBridge 146:22da6e220af6 8995 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 8996 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
AnnaBridge 146:22da6e220af6 8997 #define QUADSPI_SR_FTF_Pos (2U)
AnnaBridge 146:22da6e220af6 8998 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 8999 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 146:22da6e220af6 9000 #define QUADSPI_SR_SMF_Pos (3U)
AnnaBridge 146:22da6e220af6 9001 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9002 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
AnnaBridge 146:22da6e220af6 9003 #define QUADSPI_SR_TOF_Pos (4U)
AnnaBridge 146:22da6e220af6 9004 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9005 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
AnnaBridge 146:22da6e220af6 9006 #define QUADSPI_SR_BUSY_Pos (5U)
AnnaBridge 146:22da6e220af6 9007 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9008 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
AnnaBridge 146:22da6e220af6 9009 #define QUADSPI_SR_FLEVEL_Pos (8U)
AnnaBridge 146:22da6e220af6 9010 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
AnnaBridge 146:22da6e220af6 9011 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 146:22da6e220af6 9012 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9013 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9014 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9015 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9016 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9017 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9018
AnnaBridge 146:22da6e220af6 9019 /****************** Bit definition for QUADSPI_FCR register ******************/
AnnaBridge 146:22da6e220af6 9020 #define QUADSPI_FCR_CTEF_Pos (0U)
AnnaBridge 146:22da6e220af6 9021 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9022 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
AnnaBridge 146:22da6e220af6 9023 #define QUADSPI_FCR_CTCF_Pos (1U)
AnnaBridge 146:22da6e220af6 9024 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9025 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
AnnaBridge 146:22da6e220af6 9026 #define QUADSPI_FCR_CSMF_Pos (3U)
AnnaBridge 146:22da6e220af6 9027 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9028 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
AnnaBridge 146:22da6e220af6 9029 #define QUADSPI_FCR_CTOF_Pos (4U)
AnnaBridge 146:22da6e220af6 9030 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9031 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
AnnaBridge 146:22da6e220af6 9032
AnnaBridge 146:22da6e220af6 9033 /****************** Bit definition for QUADSPI_DLR register ******************/
AnnaBridge 146:22da6e220af6 9034 #define QUADSPI_DLR_DL_Pos (0U)
AnnaBridge 146:22da6e220af6 9035 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9036 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
AnnaBridge 146:22da6e220af6 9037
AnnaBridge 146:22da6e220af6 9038 /****************** Bit definition for QUADSPI_CCR register ******************/
AnnaBridge 146:22da6e220af6 9039 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
AnnaBridge 146:22da6e220af6 9040 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 9041 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
AnnaBridge 146:22da6e220af6 9042 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9043 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9044 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9045 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9046 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9047 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9048 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9049 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9050 #define QUADSPI_CCR_IMODE_Pos (8U)
AnnaBridge 146:22da6e220af6 9051 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 9052 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
AnnaBridge 146:22da6e220af6 9053 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9054 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9055 #define QUADSPI_CCR_ADMODE_Pos (10U)
AnnaBridge 146:22da6e220af6 9056 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 9057 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
AnnaBridge 146:22da6e220af6 9058 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9059 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9060 #define QUADSPI_CCR_ADSIZE_Pos (12U)
AnnaBridge 146:22da6e220af6 9061 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 9062 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
AnnaBridge 146:22da6e220af6 9063 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9064 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9065 #define QUADSPI_CCR_ABMODE_Pos (14U)
AnnaBridge 146:22da6e220af6 9066 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 9067 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
AnnaBridge 146:22da6e220af6 9068 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9069 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9070 #define QUADSPI_CCR_ABSIZE_Pos (16U)
AnnaBridge 146:22da6e220af6 9071 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 9072 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
AnnaBridge 146:22da6e220af6 9073 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9074 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9075 #define QUADSPI_CCR_DCYC_Pos (18U)
AnnaBridge 146:22da6e220af6 9076 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
AnnaBridge 146:22da6e220af6 9077 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
AnnaBridge 146:22da6e220af6 9078 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9079 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9080 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9081 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9082 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9083 #define QUADSPI_CCR_DMODE_Pos (24U)
AnnaBridge 146:22da6e220af6 9084 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 9085 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
AnnaBridge 146:22da6e220af6 9086 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9087 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9088 #define QUADSPI_CCR_FMODE_Pos (26U)
AnnaBridge 146:22da6e220af6 9089 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
AnnaBridge 146:22da6e220af6 9090 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
AnnaBridge 146:22da6e220af6 9091 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9092 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9093 #define QUADSPI_CCR_SIOO_Pos (28U)
AnnaBridge 146:22da6e220af6 9094 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9095 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
AnnaBridge 146:22da6e220af6 9096 #define QUADSPI_CCR_DHHC_Pos (30U)
AnnaBridge 146:22da6e220af6 9097 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9098 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
AnnaBridge 146:22da6e220af6 9099 #define QUADSPI_CCR_DDRM_Pos (31U)
AnnaBridge 146:22da6e220af6 9100 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 9101 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
AnnaBridge 146:22da6e220af6 9102 /****************** Bit definition for QUADSPI_AR register *******************/
AnnaBridge 146:22da6e220af6 9103 #define QUADSPI_AR_ADDRESS_Pos (0U)
AnnaBridge 146:22da6e220af6 9104 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9105 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
AnnaBridge 146:22da6e220af6 9106
AnnaBridge 146:22da6e220af6 9107 /****************** Bit definition for QUADSPI_ABR register ******************/
AnnaBridge 146:22da6e220af6 9108 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
AnnaBridge 146:22da6e220af6 9109 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9110 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
AnnaBridge 146:22da6e220af6 9111
AnnaBridge 146:22da6e220af6 9112 /****************** Bit definition for QUADSPI_DR register *******************/
AnnaBridge 146:22da6e220af6 9113 #define QUADSPI_DR_DATA_Pos (0U)
AnnaBridge 146:22da6e220af6 9114 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9115 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
AnnaBridge 146:22da6e220af6 9116
AnnaBridge 146:22da6e220af6 9117 /****************** Bit definition for QUADSPI_PSMKR register ****************/
AnnaBridge 146:22da6e220af6 9118 #define QUADSPI_PSMKR_MASK_Pos (0U)
AnnaBridge 146:22da6e220af6 9119 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9120 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
AnnaBridge 146:22da6e220af6 9121
AnnaBridge 146:22da6e220af6 9122 /****************** Bit definition for QUADSPI_PSMAR register ****************/
AnnaBridge 146:22da6e220af6 9123 #define QUADSPI_PSMAR_MATCH_Pos (0U)
AnnaBridge 146:22da6e220af6 9124 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 9125 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
AnnaBridge 146:22da6e220af6 9126
AnnaBridge 146:22da6e220af6 9127 /****************** Bit definition for QUADSPI_PIR register *****************/
AnnaBridge 146:22da6e220af6 9128 #define QUADSPI_PIR_INTERVAL_Pos (0U)
AnnaBridge 146:22da6e220af6 9129 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 9130 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
AnnaBridge 146:22da6e220af6 9131
AnnaBridge 146:22da6e220af6 9132 /****************** Bit definition for QUADSPI_LPTR register *****************/
AnnaBridge 146:22da6e220af6 9133 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
AnnaBridge 146:22da6e220af6 9134 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 9135 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
AnnaBridge 146:22da6e220af6 9136
AnnaBridge 146:22da6e220af6 9137 /******************************************************************************/
AnnaBridge 146:22da6e220af6 9138 /* */
AnnaBridge 146:22da6e220af6 9139 /* Reset and Clock Control */
AnnaBridge 146:22da6e220af6 9140 /* */
AnnaBridge 146:22da6e220af6 9141 /******************************************************************************/
AnnaBridge 146:22da6e220af6 9142 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 146:22da6e220af6 9143 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 146:22da6e220af6 9144 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9145 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 146:22da6e220af6 9146 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 146:22da6e220af6 9147 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9148 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 146:22da6e220af6 9149
AnnaBridge 146:22da6e220af6 9150 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 146:22da6e220af6 9151 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 146:22da6e220af6 9152 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 146:22da6e220af6 9153 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9154 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9155 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9156 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9157 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9158
AnnaBridge 146:22da6e220af6 9159 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 146:22da6e220af6 9160 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 9161 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 146:22da6e220af6 9162 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9163 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9164 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9165 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9166 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9167 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9168 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9169 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9170
AnnaBridge 146:22da6e220af6 9171 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 146:22da6e220af6 9172 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9173 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 146:22da6e220af6 9174 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 146:22da6e220af6 9175 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9176 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 146:22da6e220af6 9177 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 146:22da6e220af6 9178 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9179 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 146:22da6e220af6 9180 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 146:22da6e220af6 9181 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9182 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 146:22da6e220af6 9183 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 146:22da6e220af6 9184 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9185 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 146:22da6e220af6 9186 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 146:22da6e220af6 9187 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9188 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 146:22da6e220af6 9189 /*
AnnaBridge 146:22da6e220af6 9190 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 9191 */
AnnaBridge 146:22da6e220af6 9192 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 146:22da6e220af6 9193
AnnaBridge 146:22da6e220af6 9194 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 146:22da6e220af6 9195 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9196 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 146:22da6e220af6 9197 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 146:22da6e220af6 9198 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9199 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 146:22da6e220af6 9200
AnnaBridge 146:22da6e220af6 9201 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 146:22da6e220af6 9202 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 146:22da6e220af6 9203 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 9204 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 146:22da6e220af6 9205 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9206 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9207 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9208 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9209 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9210 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9211
AnnaBridge 146:22da6e220af6 9212 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 146:22da6e220af6 9213 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 146:22da6e220af6 9214 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 146:22da6e220af6 9215 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9216 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9217 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9218 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9219 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9220 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9221 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9222 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9223 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9224
AnnaBridge 146:22da6e220af6 9225 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 146:22da6e220af6 9226 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 146:22da6e220af6 9227 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 146:22da6e220af6 9228 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9229 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9230
AnnaBridge 146:22da6e220af6 9231 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 146:22da6e220af6 9232 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9233 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 146:22da6e220af6 9234 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 146:22da6e220af6 9235 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9236 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 146:22da6e220af6 9237 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 146:22da6e220af6 9238
AnnaBridge 146:22da6e220af6 9239 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 146:22da6e220af6 9240 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 9241 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 146:22da6e220af6 9242 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9243 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9244 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9245 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9246 /*
AnnaBridge 146:22da6e220af6 9247 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 9248 */
AnnaBridge 146:22da6e220af6 9249 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
AnnaBridge 146:22da6e220af6 9250
AnnaBridge 146:22da6e220af6 9251 #define RCC_PLLCFGR_PLLR_Pos (28U)
AnnaBridge 146:22da6e220af6 9252 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
AnnaBridge 146:22da6e220af6 9253 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
AnnaBridge 146:22da6e220af6 9254 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9255 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 9256 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9257
AnnaBridge 146:22da6e220af6 9258 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 146:22da6e220af6 9259 /*!< SW configuration */
AnnaBridge 146:22da6e220af6 9260 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 146:22da6e220af6 9261 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 9262 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 146:22da6e220af6 9263 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9264 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9265
AnnaBridge 146:22da6e220af6 9266 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 146:22da6e220af6 9267 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 146:22da6e220af6 9268 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 146:22da6e220af6 9269
AnnaBridge 146:22da6e220af6 9270 /*!< SWS configuration */
AnnaBridge 146:22da6e220af6 9271 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 146:22da6e220af6 9272 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 9273 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 146:22da6e220af6 9274 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9275 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9276
AnnaBridge 146:22da6e220af6 9277 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 146:22da6e220af6 9278 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 146:22da6e220af6 9279 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 146:22da6e220af6 9280
AnnaBridge 146:22da6e220af6 9281 /*!< HPRE configuration */
AnnaBridge 146:22da6e220af6 9282 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 146:22da6e220af6 9283 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 9284 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 146:22da6e220af6 9285 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9286 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9287 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9288 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9289
AnnaBridge 146:22da6e220af6 9290 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 146:22da6e220af6 9291 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 146:22da6e220af6 9292 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 146:22da6e220af6 9293 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 146:22da6e220af6 9294 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 146:22da6e220af6 9295 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 146:22da6e220af6 9296 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 146:22da6e220af6 9297 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 146:22da6e220af6 9298 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 146:22da6e220af6 9299
AnnaBridge 146:22da6e220af6 9300 /*!< PPRE1 configuration */
AnnaBridge 146:22da6e220af6 9301 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 146:22da6e220af6 9302 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 146:22da6e220af6 9303 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 146:22da6e220af6 9304 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9305 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9306 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9307
AnnaBridge 146:22da6e220af6 9308 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 146:22da6e220af6 9309 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 146:22da6e220af6 9310 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 146:22da6e220af6 9311 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 146:22da6e220af6 9312 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 146:22da6e220af6 9313
AnnaBridge 146:22da6e220af6 9314 /*!< PPRE2 configuration */
AnnaBridge 146:22da6e220af6 9315 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 146:22da6e220af6 9316 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 146:22da6e220af6 9317 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 146:22da6e220af6 9318 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9319 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9320 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9321
AnnaBridge 146:22da6e220af6 9322 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 146:22da6e220af6 9323 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 146:22da6e220af6 9324 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 146:22da6e220af6 9325 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 146:22da6e220af6 9326 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 146:22da6e220af6 9327
AnnaBridge 146:22da6e220af6 9328 /*!< RTCPRE configuration */
AnnaBridge 146:22da6e220af6 9329 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 146:22da6e220af6 9330 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 146:22da6e220af6 9331 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 146:22da6e220af6 9332 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9333 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9334 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9335 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9336 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9337
AnnaBridge 146:22da6e220af6 9338 /*!< MCO1 configuration */
AnnaBridge 146:22da6e220af6 9339 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 146:22da6e220af6 9340 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 146:22da6e220af6 9341 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 146:22da6e220af6 9342 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9343 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9344
AnnaBridge 146:22da6e220af6 9345
AnnaBridge 146:22da6e220af6 9346 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 146:22da6e220af6 9347 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 146:22da6e220af6 9348 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 146:22da6e220af6 9349 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9350 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9351 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9352
AnnaBridge 146:22da6e220af6 9353 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 146:22da6e220af6 9354 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 146:22da6e220af6 9355 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 146:22da6e220af6 9356 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9357 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9358 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 9359
AnnaBridge 146:22da6e220af6 9360 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 146:22da6e220af6 9361 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 146:22da6e220af6 9362 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 146:22da6e220af6 9363 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9364 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 9365
AnnaBridge 146:22da6e220af6 9366 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 146:22da6e220af6 9367 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 146:22da6e220af6 9368 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9369 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 146:22da6e220af6 9370 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 146:22da6e220af6 9371 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9372 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 146:22da6e220af6 9373 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 146:22da6e220af6 9374 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9375 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 146:22da6e220af6 9376 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 146:22da6e220af6 9377 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9378 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 146:22da6e220af6 9379 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 146:22da6e220af6 9380 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9381 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 146:22da6e220af6 9382 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 146:22da6e220af6 9383 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9384 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 146:22da6e220af6 9385
AnnaBridge 146:22da6e220af6 9386 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 146:22da6e220af6 9387 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9388 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 146:22da6e220af6 9389 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 146:22da6e220af6 9390 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9391 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 146:22da6e220af6 9392 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 146:22da6e220af6 9393 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9394 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 146:22da6e220af6 9395 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 146:22da6e220af6 9396 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9397 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 146:22da6e220af6 9398 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 146:22da6e220af6 9399 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9400 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 146:22da6e220af6 9401 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 146:22da6e220af6 9402 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9403 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 146:22da6e220af6 9404 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 146:22da6e220af6 9405 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9406 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 146:22da6e220af6 9407
AnnaBridge 146:22da6e220af6 9408 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 146:22da6e220af6 9409 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9410 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 146:22da6e220af6 9411 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 146:22da6e220af6 9412 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9413 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 146:22da6e220af6 9414 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 146:22da6e220af6 9415 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9416 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 146:22da6e220af6 9417 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 146:22da6e220af6 9418 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9419 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 146:22da6e220af6 9420 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 146:22da6e220af6 9421 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9422 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 146:22da6e220af6 9423 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 146:22da6e220af6 9424 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9425 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 146:22da6e220af6 9426
AnnaBridge 146:22da6e220af6 9427 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 146:22da6e220af6 9428 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 9429 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 146:22da6e220af6 9430
AnnaBridge 146:22da6e220af6 9431 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 146:22da6e220af6 9432 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 146:22da6e220af6 9433 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9434 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 146:22da6e220af6 9435 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 146:22da6e220af6 9436 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9437 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 146:22da6e220af6 9438 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 146:22da6e220af6 9439 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9440 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 146:22da6e220af6 9441 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 146:22da6e220af6 9442 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9443 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 146:22da6e220af6 9444 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 146:22da6e220af6 9445 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9446 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 146:22da6e220af6 9447 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
AnnaBridge 146:22da6e220af6 9448 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9449 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
AnnaBridge 146:22da6e220af6 9450 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
AnnaBridge 146:22da6e220af6 9451 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9452 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
AnnaBridge 146:22da6e220af6 9453 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 146:22da6e220af6 9454 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9455 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 146:22da6e220af6 9456 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 146:22da6e220af6 9457 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9458 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 146:22da6e220af6 9459 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 146:22da6e220af6 9460 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9461 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 146:22da6e220af6 9462 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 146:22da6e220af6 9463 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9464 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 146:22da6e220af6 9465
AnnaBridge 146:22da6e220af6 9466 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 146:22da6e220af6 9467 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 146:22da6e220af6 9468 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9469 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 146:22da6e220af6 9470 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 146:22da6e220af6 9471 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9472 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
AnnaBridge 146:22da6e220af6 9473 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 146:22da6e220af6 9474 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
AnnaBridge 146:22da6e220af6 9475 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9476 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
AnnaBridge 146:22da6e220af6 9477 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
AnnaBridge 146:22da6e220af6 9478 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9479 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
AnnaBridge 146:22da6e220af6 9480
AnnaBridge 146:22da6e220af6 9481
AnnaBridge 146:22da6e220af6 9482 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 146:22da6e220af6 9483 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 146:22da6e220af6 9484 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9485 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 146:22da6e220af6 9486 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 146:22da6e220af6 9487 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9488 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 146:22da6e220af6 9489 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 146:22da6e220af6 9490 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9491 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 146:22da6e220af6 9492 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 146:22da6e220af6 9493 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9494 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 146:22da6e220af6 9495 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 146:22da6e220af6 9496 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9497 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 146:22da6e220af6 9498 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 146:22da6e220af6 9499 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9500 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
AnnaBridge 146:22da6e220af6 9501 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
AnnaBridge 146:22da6e220af6 9502 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9503 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
AnnaBridge 146:22da6e220af6 9504 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
AnnaBridge 146:22da6e220af6 9505 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9506 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
AnnaBridge 146:22da6e220af6 9507 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 146:22da6e220af6 9508 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9509 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
AnnaBridge 146:22da6e220af6 9510 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
AnnaBridge 146:22da6e220af6 9511 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9512 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
AnnaBridge 146:22da6e220af6 9513 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 146:22da6e220af6 9514 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9515 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 146:22da6e220af6 9516 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 146:22da6e220af6 9517 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9518 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 146:22da6e220af6 9519 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 146:22da6e220af6 9520 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9521 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 146:22da6e220af6 9522 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 146:22da6e220af6 9523 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9524 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 146:22da6e220af6 9525 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 146:22da6e220af6 9526 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9527 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
AnnaBridge 146:22da6e220af6 9528 #define RCC_APB1RSTR_UART4RST_Pos (19U)
AnnaBridge 146:22da6e220af6 9529 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9530 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
AnnaBridge 146:22da6e220af6 9531 #define RCC_APB1RSTR_UART5RST_Pos (20U)
AnnaBridge 146:22da6e220af6 9532 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9533 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
AnnaBridge 146:22da6e220af6 9534 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 146:22da6e220af6 9535 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9536 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 146:22da6e220af6 9537 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 146:22da6e220af6 9538 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9539 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 146:22da6e220af6 9540 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 146:22da6e220af6 9541 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 9542 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 146:22da6e220af6 9543 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
AnnaBridge 146:22da6e220af6 9544 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9545 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
AnnaBridge 146:22da6e220af6 9546 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
AnnaBridge 146:22da6e220af6 9547 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9548 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
AnnaBridge 146:22da6e220af6 9549 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
AnnaBridge 146:22da6e220af6 9550 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9551 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
AnnaBridge 146:22da6e220af6 9552 #define RCC_APB1RSTR_CAN3RST_Pos (27U)
AnnaBridge 146:22da6e220af6 9553 #define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9554 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
AnnaBridge 146:22da6e220af6 9555 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 146:22da6e220af6 9556 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9557 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 146:22da6e220af6 9558 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 146:22da6e220af6 9559 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 9560 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 146:22da6e220af6 9561 #define RCC_APB1RSTR_UART7RST_Pos (30U)
AnnaBridge 146:22da6e220af6 9562 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9563 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
AnnaBridge 146:22da6e220af6 9564 #define RCC_APB1RSTR_UART8RST_Pos (31U)
AnnaBridge 146:22da6e220af6 9565 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 9566 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
AnnaBridge 146:22da6e220af6 9567
AnnaBridge 146:22da6e220af6 9568 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 146:22da6e220af6 9569 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 146:22da6e220af6 9570 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9571 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 146:22da6e220af6 9572 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 146:22da6e220af6 9573 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9574 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 146:22da6e220af6 9575 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 146:22da6e220af6 9576 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9577 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 146:22da6e220af6 9578 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 146:22da6e220af6 9579 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9580 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 146:22da6e220af6 9581 #define RCC_APB2RSTR_UART9RST_Pos (6U)
AnnaBridge 146:22da6e220af6 9582 #define RCC_APB2RSTR_UART9RST_Msk (0x1U << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9583 #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
AnnaBridge 146:22da6e220af6 9584 #define RCC_APB2RSTR_UART10RST_Pos (7U)
AnnaBridge 146:22da6e220af6 9585 #define RCC_APB2RSTR_UART10RST_Msk (0x1U << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9586 #define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
AnnaBridge 146:22da6e220af6 9587 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 146:22da6e220af6 9588 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9589 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 146:22da6e220af6 9590 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 146:22da6e220af6 9591 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9592 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 146:22da6e220af6 9593 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 146:22da6e220af6 9594 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9595 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 146:22da6e220af6 9596 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 146:22da6e220af6 9597 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9598 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 146:22da6e220af6 9599 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 146:22da6e220af6 9600 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9601 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 146:22da6e220af6 9602 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 146:22da6e220af6 9603 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9604 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 146:22da6e220af6 9605 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 146:22da6e220af6 9606 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9607 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 146:22da6e220af6 9608 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 146:22da6e220af6 9609 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9610 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 146:22da6e220af6 9611 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 146:22da6e220af6 9612 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9613 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 146:22da6e220af6 9614 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
AnnaBridge 146:22da6e220af6 9615 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9616 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 146:22da6e220af6 9617 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
AnnaBridge 146:22da6e220af6 9618 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9619 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
AnnaBridge 146:22da6e220af6 9620 #define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
AnnaBridge 146:22da6e220af6 9621 #define RCC_APB2RSTR_DFSDM2RST_Msk (0x1U << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9622 #define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
AnnaBridge 146:22da6e220af6 9623
AnnaBridge 146:22da6e220af6 9624 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 146:22da6e220af6 9625 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9626 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9627 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 146:22da6e220af6 9628 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9629 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9630 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 146:22da6e220af6 9631 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 146:22da6e220af6 9632 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9633 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 146:22da6e220af6 9634 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 146:22da6e220af6 9635 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9636 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 146:22da6e220af6 9637 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 146:22da6e220af6 9638 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9639 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 146:22da6e220af6 9640 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
AnnaBridge 146:22da6e220af6 9641 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9642 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
AnnaBridge 146:22da6e220af6 9643 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9644 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9645 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
AnnaBridge 146:22da6e220af6 9646 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9647 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9648 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 146:22da6e220af6 9649 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 146:22da6e220af6 9650 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9651 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 146:22da6e220af6 9652 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 146:22da6e220af6 9653 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9654 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 146:22da6e220af6 9655 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 146:22da6e220af6 9656 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9657 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 146:22da6e220af6 9658 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 146:22da6e220af6 9659 /*
AnnaBridge 146:22da6e220af6 9660 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 9661 */
AnnaBridge 146:22da6e220af6 9662 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 146:22da6e220af6 9663
AnnaBridge 146:22da6e220af6 9664 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9665 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9666 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 146:22da6e220af6 9667 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9668 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9669 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
AnnaBridge 146:22da6e220af6 9670
AnnaBridge 146:22da6e220af6 9671 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 146:22da6e220af6 9672 /*
AnnaBridge 146:22da6e220af6 9673 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 9674 */
AnnaBridge 146:22da6e220af6 9675 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
AnnaBridge 146:22da6e220af6 9676
AnnaBridge 146:22da6e220af6 9677 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9678 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9679 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
AnnaBridge 146:22da6e220af6 9680 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9681 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9682 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
AnnaBridge 146:22da6e220af6 9683
AnnaBridge 146:22da6e220af6 9684 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 146:22da6e220af6 9685 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 146:22da6e220af6 9686 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9687 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 146:22da6e220af6 9688 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 146:22da6e220af6 9689 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9690 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 146:22da6e220af6 9691 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 146:22da6e220af6 9692 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9693 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 146:22da6e220af6 9694 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 146:22da6e220af6 9695 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9696 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 146:22da6e220af6 9697 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 146:22da6e220af6 9698 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9699 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 146:22da6e220af6 9700 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 146:22da6e220af6 9701 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9702 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
AnnaBridge 146:22da6e220af6 9703 #define RCC_APB1ENR_TIM12EN_Pos (6U)
AnnaBridge 146:22da6e220af6 9704 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9705 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
AnnaBridge 146:22da6e220af6 9706 #define RCC_APB1ENR_TIM13EN_Pos (7U)
AnnaBridge 146:22da6e220af6 9707 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9708 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
AnnaBridge 146:22da6e220af6 9709 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 146:22da6e220af6 9710 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9711 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
AnnaBridge 146:22da6e220af6 9712 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
AnnaBridge 146:22da6e220af6 9713 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9714 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
AnnaBridge 146:22da6e220af6 9715 #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
AnnaBridge 146:22da6e220af6 9716 #define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9717 #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
AnnaBridge 146:22da6e220af6 9718 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 146:22da6e220af6 9719 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9720 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 146:22da6e220af6 9721 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 146:22da6e220af6 9722 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9723 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 146:22da6e220af6 9724 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 146:22da6e220af6 9725 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9726 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 146:22da6e220af6 9727 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 146:22da6e220af6 9728 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9729 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 146:22da6e220af6 9730 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 146:22da6e220af6 9731 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9732 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
AnnaBridge 146:22da6e220af6 9733 #define RCC_APB1ENR_UART4EN_Pos (19U)
AnnaBridge 146:22da6e220af6 9734 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9735 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
AnnaBridge 146:22da6e220af6 9736 #define RCC_APB1ENR_UART5EN_Pos (20U)
AnnaBridge 146:22da6e220af6 9737 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9738 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
AnnaBridge 146:22da6e220af6 9739 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 146:22da6e220af6 9740 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9741 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 146:22da6e220af6 9742 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 146:22da6e220af6 9743 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9744 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 146:22da6e220af6 9745 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 146:22da6e220af6 9746 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 9747 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 146:22da6e220af6 9748 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
AnnaBridge 146:22da6e220af6 9749 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9750 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
AnnaBridge 146:22da6e220af6 9751 #define RCC_APB1ENR_CAN1EN_Pos (25U)
AnnaBridge 146:22da6e220af6 9752 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9753 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
AnnaBridge 146:22da6e220af6 9754 #define RCC_APB1ENR_CAN2EN_Pos (26U)
AnnaBridge 146:22da6e220af6 9755 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9756 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
AnnaBridge 146:22da6e220af6 9757 #define RCC_APB1ENR_CAN3EN_Pos (27U)
AnnaBridge 146:22da6e220af6 9758 #define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9759 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
AnnaBridge 146:22da6e220af6 9760 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 146:22da6e220af6 9761 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9762 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 146:22da6e220af6 9763 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 146:22da6e220af6 9764 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 9765 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 146:22da6e220af6 9766 #define RCC_APB1ENR_UART7EN_Pos (30U)
AnnaBridge 146:22da6e220af6 9767 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9768 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
AnnaBridge 146:22da6e220af6 9769 #define RCC_APB1ENR_UART8EN_Pos (31U)
AnnaBridge 146:22da6e220af6 9770 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 9771 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
AnnaBridge 146:22da6e220af6 9772
AnnaBridge 146:22da6e220af6 9773 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 146:22da6e220af6 9774 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 146:22da6e220af6 9775 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9776 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 146:22da6e220af6 9777 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 146:22da6e220af6 9778 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9779 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 146:22da6e220af6 9780 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 146:22da6e220af6 9781 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9782 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 146:22da6e220af6 9783 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 146:22da6e220af6 9784 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9785 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 146:22da6e220af6 9786 #define RCC_APB2ENR_UART9EN_Pos (6U)
AnnaBridge 146:22da6e220af6 9787 #define RCC_APB2ENR_UART9EN_Msk (0x1U << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9788 #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
AnnaBridge 146:22da6e220af6 9789 #define RCC_APB2ENR_UART10EN_Pos (7U)
AnnaBridge 146:22da6e220af6 9790 #define RCC_APB2ENR_UART10EN_Msk (0x1U << RCC_APB2ENR_UART10EN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9791 #define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
AnnaBridge 146:22da6e220af6 9792 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 146:22da6e220af6 9793 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9794 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 146:22da6e220af6 9795 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 146:22da6e220af6 9796 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9797 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 146:22da6e220af6 9798 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 146:22da6e220af6 9799 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9800 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 146:22da6e220af6 9801 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 146:22da6e220af6 9802 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 9803 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 146:22da6e220af6 9804 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 146:22da6e220af6 9805 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9806 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 146:22da6e220af6 9807 #define RCC_APB2ENR_EXTITEN_Pos (15U)
AnnaBridge 146:22da6e220af6 9808 #define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9809 #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
AnnaBridge 146:22da6e220af6 9810 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 146:22da6e220af6 9811 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9812 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 146:22da6e220af6 9813 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 146:22da6e220af6 9814 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9815 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 146:22da6e220af6 9816 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 146:22da6e220af6 9817 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9818 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 146:22da6e220af6 9819 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 146:22da6e220af6 9820 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9821 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 146:22da6e220af6 9822 #define RCC_APB2ENR_SAI1EN_Pos (22U)
AnnaBridge 146:22da6e220af6 9823 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9824 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 146:22da6e220af6 9825 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
AnnaBridge 146:22da6e220af6 9826 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9827 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
AnnaBridge 146:22da6e220af6 9828 #define RCC_APB2ENR_DFSDM2EN_Pos (25U)
AnnaBridge 146:22da6e220af6 9829 #define RCC_APB2ENR_DFSDM2EN_Msk (0x1U << RCC_APB2ENR_DFSDM2EN_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9830 #define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
AnnaBridge 146:22da6e220af6 9831
AnnaBridge 146:22da6e220af6 9832 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 146:22da6e220af6 9833 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9834 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9835 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 146:22da6e220af6 9836 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9837 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9838 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 146:22da6e220af6 9839 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 146:22da6e220af6 9840 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9841 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 146:22da6e220af6 9842 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 146:22da6e220af6 9843 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9844 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 146:22da6e220af6 9845 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 146:22da6e220af6 9846 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9847 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 146:22da6e220af6 9848 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 146:22da6e220af6 9849 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9850 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
AnnaBridge 146:22da6e220af6 9851 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9852 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9853 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
AnnaBridge 146:22da6e220af6 9854 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9855 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9856 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 146:22da6e220af6 9857 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 146:22da6e220af6 9858 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 9859 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 146:22da6e220af6 9860 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 146:22da6e220af6 9861 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9862 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 146:22da6e220af6 9863 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 146:22da6e220af6 9864 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 9865 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 146:22da6e220af6 9866 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
AnnaBridge 146:22da6e220af6 9867 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9868 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
AnnaBridge 146:22da6e220af6 9869 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 146:22da6e220af6 9870 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9871 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 146:22da6e220af6 9872 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 146:22da6e220af6 9873 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9874 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 146:22da6e220af6 9875
AnnaBridge 146:22da6e220af6 9876
AnnaBridge 146:22da6e220af6 9877 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 146:22da6e220af6 9878 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9879 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9880 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 146:22da6e220af6 9881 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9882 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9883 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
AnnaBridge 146:22da6e220af6 9884
AnnaBridge 146:22da6e220af6 9885 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 146:22da6e220af6 9886 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9887 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9888 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
AnnaBridge 146:22da6e220af6 9889 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9890 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9891 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
AnnaBridge 146:22da6e220af6 9892
AnnaBridge 146:22da6e220af6 9893 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 146:22da6e220af6 9894 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9895 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9896 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 146:22da6e220af6 9897 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9898 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9899 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 146:22da6e220af6 9900 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 146:22da6e220af6 9901 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 9902 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 146:22da6e220af6 9903 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 146:22da6e220af6 9904 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 9905 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 146:22da6e220af6 9906 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 146:22da6e220af6 9907 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9908 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 146:22da6e220af6 9909 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 146:22da6e220af6 9910 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9911 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
AnnaBridge 146:22da6e220af6 9912 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9913 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9914 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
AnnaBridge 146:22da6e220af6 9915 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9916 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 9917 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
AnnaBridge 146:22da6e220af6 9918 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
AnnaBridge 146:22da6e220af6 9919 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 9920 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
AnnaBridge 146:22da6e220af6 9921 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
AnnaBridge 146:22da6e220af6 9922 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 9923 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
AnnaBridge 146:22da6e220af6 9924 #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
AnnaBridge 146:22da6e220af6 9925 #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 9926 #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
AnnaBridge 146:22da6e220af6 9927 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 146:22da6e220af6 9928 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 9929 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 146:22da6e220af6 9930 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 146:22da6e220af6 9931 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 9932 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 146:22da6e220af6 9933 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 146:22da6e220af6 9934 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 9935 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 146:22da6e220af6 9936 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 146:22da6e220af6 9937 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 9938 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 146:22da6e220af6 9939 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 146:22da6e220af6 9940 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 9941 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
AnnaBridge 146:22da6e220af6 9942 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
AnnaBridge 146:22da6e220af6 9943 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 9944 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
AnnaBridge 146:22da6e220af6 9945 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
AnnaBridge 146:22da6e220af6 9946 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 9947 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
AnnaBridge 146:22da6e220af6 9948 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 146:22da6e220af6 9949 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 9950 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 146:22da6e220af6 9951 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 146:22da6e220af6 9952 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 9953 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 146:22da6e220af6 9954 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 146:22da6e220af6 9955 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 9956 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 146:22da6e220af6 9957 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
AnnaBridge 146:22da6e220af6 9958 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 9959 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
AnnaBridge 146:22da6e220af6 9960 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
AnnaBridge 146:22da6e220af6 9961 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 9962 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
AnnaBridge 146:22da6e220af6 9963 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
AnnaBridge 146:22da6e220af6 9964 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 9965 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
AnnaBridge 146:22da6e220af6 9966 #define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
AnnaBridge 146:22da6e220af6 9967 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 9968 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
AnnaBridge 146:22da6e220af6 9969 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 146:22da6e220af6 9970 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 9971 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 146:22da6e220af6 9972 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 146:22da6e220af6 9973 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 9974 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 146:22da6e220af6 9975 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
AnnaBridge 146:22da6e220af6 9976 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 9977 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
AnnaBridge 146:22da6e220af6 9978 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
AnnaBridge 146:22da6e220af6 9979 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 9980 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
AnnaBridge 146:22da6e220af6 9981
AnnaBridge 146:22da6e220af6 9982 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 146:22da6e220af6 9983 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 146:22da6e220af6 9984 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 9985 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 146:22da6e220af6 9986 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 146:22da6e220af6 9987 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 9988 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 146:22da6e220af6 9989 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 146:22da6e220af6 9990 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 9991 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 146:22da6e220af6 9992 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 146:22da6e220af6 9993 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 9994 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 146:22da6e220af6 9995 #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
AnnaBridge 146:22da6e220af6 9996 #define RCC_APB2LPENR_UART9LPEN_Msk (0x1U << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 9997 #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
AnnaBridge 146:22da6e220af6 9998 #define RCC_APB2LPENR_UART10LPEN_Pos (7U)
AnnaBridge 146:22da6e220af6 9999 #define RCC_APB2LPENR_UART10LPEN_Msk (0x1U << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10000 #define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
AnnaBridge 146:22da6e220af6 10001 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 146:22da6e220af6 10002 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10003 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 146:22da6e220af6 10004 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 146:22da6e220af6 10005 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10006 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 146:22da6e220af6 10007 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 146:22da6e220af6 10008 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10009 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 146:22da6e220af6 10010 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 146:22da6e220af6 10011 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10012 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 146:22da6e220af6 10013 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 146:22da6e220af6 10014 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10015 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 146:22da6e220af6 10016 #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
AnnaBridge 146:22da6e220af6 10017 #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10018 #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
AnnaBridge 146:22da6e220af6 10019 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 146:22da6e220af6 10020 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10021 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 146:22da6e220af6 10022 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 146:22da6e220af6 10023 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10024 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 146:22da6e220af6 10025 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 146:22da6e220af6 10026 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10027 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 146:22da6e220af6 10028 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 146:22da6e220af6 10029 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10030 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 146:22da6e220af6 10031 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
AnnaBridge 146:22da6e220af6 10032 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10033 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
AnnaBridge 146:22da6e220af6 10034 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
AnnaBridge 146:22da6e220af6 10035 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10036 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
AnnaBridge 146:22da6e220af6 10037 #define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
AnnaBridge 146:22da6e220af6 10038 #define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10039 #define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
AnnaBridge 146:22da6e220af6 10040
AnnaBridge 146:22da6e220af6 10041 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 146:22da6e220af6 10042 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 146:22da6e220af6 10043 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10044 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 146:22da6e220af6 10045 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 146:22da6e220af6 10046 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10047 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 146:22da6e220af6 10048 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 146:22da6e220af6 10049 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10050 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 146:22da6e220af6 10051 #define RCC_BDCR_LSEMOD_Pos (3U)
AnnaBridge 146:22da6e220af6 10052 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10053 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
AnnaBridge 146:22da6e220af6 10054
AnnaBridge 146:22da6e220af6 10055 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 146:22da6e220af6 10056 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 10057 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 146:22da6e220af6 10058 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10059 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10060
AnnaBridge 146:22da6e220af6 10061 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 146:22da6e220af6 10062 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10063 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 146:22da6e220af6 10064 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 146:22da6e220af6 10065 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10066 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 146:22da6e220af6 10067
AnnaBridge 146:22da6e220af6 10068 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 146:22da6e220af6 10069 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 146:22da6e220af6 10070 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10071 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 146:22da6e220af6 10072 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 146:22da6e220af6 10073 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10074 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 146:22da6e220af6 10075 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 146:22da6e220af6 10076 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10077 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 146:22da6e220af6 10078 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 146:22da6e220af6 10079 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10080 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 146:22da6e220af6 10081 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 146:22da6e220af6 10082 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10083 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 146:22da6e220af6 10084 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 146:22da6e220af6 10085 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10086 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 146:22da6e220af6 10087 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 146:22da6e220af6 10088 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 10089 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 146:22da6e220af6 10090 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 146:22da6e220af6 10091 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10092 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 146:22da6e220af6 10093 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 146:22da6e220af6 10094 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10095 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 146:22da6e220af6 10096 /* Legacy defines */
AnnaBridge 146:22da6e220af6 10097 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 146:22da6e220af6 10098 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
AnnaBridge 146:22da6e220af6 10099
AnnaBridge 146:22da6e220af6 10100 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 146:22da6e220af6 10101 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 146:22da6e220af6 10102 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 146:22da6e220af6 10103 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 146:22da6e220af6 10104 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 146:22da6e220af6 10105 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 146:22da6e220af6 10106 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 146:22da6e220af6 10107 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 146:22da6e220af6 10108 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10109 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 146:22da6e220af6 10110 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 146:22da6e220af6 10111 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10112 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 146:22da6e220af6 10113
AnnaBridge 146:22da6e220af6 10114 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 146:22da6e220af6 10115 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
AnnaBridge 146:22da6e220af6 10116 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 10117 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
AnnaBridge 146:22da6e220af6 10118 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10119 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10120 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10121 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10122 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10123 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10124
AnnaBridge 146:22da6e220af6 10125 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 146:22da6e220af6 10126 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 146:22da6e220af6 10127 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 146:22da6e220af6 10128 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10129 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10130 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10131 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10132 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10133 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10134 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10135 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10136 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10137
AnnaBridge 146:22da6e220af6 10138 #define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
AnnaBridge 146:22da6e220af6 10139 #define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10140 #define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
AnnaBridge 146:22da6e220af6 10141 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
AnnaBridge 146:22da6e220af6 10142 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 10143 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
AnnaBridge 146:22da6e220af6 10144 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10145 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10146 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10147 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10148 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 146:22da6e220af6 10149 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 146:22da6e220af6 10150 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 146:22da6e220af6 10151 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10152 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 10153 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10154
AnnaBridge 146:22da6e220af6 10155
AnnaBridge 146:22da6e220af6 10156
AnnaBridge 146:22da6e220af6 10157 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 146:22da6e220af6 10158 #define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
AnnaBridge 146:22da6e220af6 10159 #define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 10160 #define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
AnnaBridge 146:22da6e220af6 10161 #define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10162 #define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10163 #define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10164 #define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10165 #define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10166
AnnaBridge 146:22da6e220af6 10167 #define RCC_DCKCFGR_PLLDIVR_Pos (8U)
AnnaBridge 146:22da6e220af6 10168 #define RCC_DCKCFGR_PLLDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */
AnnaBridge 146:22da6e220af6 10169 #define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
AnnaBridge 146:22da6e220af6 10170 #define RCC_DCKCFGR_PLLDIVR_0 (0x01U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10171 #define RCC_DCKCFGR_PLLDIVR_1 (0x02U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10172 #define RCC_DCKCFGR_PLLDIVR_2 (0x04U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10173 #define RCC_DCKCFGR_PLLDIVR_3 (0x08U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10174 #define RCC_DCKCFGR_PLLDIVR_4 (0x10U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10175
AnnaBridge 146:22da6e220af6 10176 #define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
AnnaBridge 146:22da6e220af6 10177 #define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10178 #define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
AnnaBridge 146:22da6e220af6 10179 #define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
AnnaBridge 146:22da6e220af6 10180 #define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10181 #define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
AnnaBridge 146:22da6e220af6 10182
AnnaBridge 146:22da6e220af6 10183 /*
AnnaBridge 146:22da6e220af6 10184 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 146:22da6e220af6 10185 */
AnnaBridge 146:22da6e220af6 10186 #define RCC_SAI1A_PLLSOURCE_SUPPORT /*!< SAI1 block A PLL Main source clock support */
AnnaBridge 146:22da6e220af6 10187 #define RCC_SAI1B_PLLSOURCE_SUPPORT /*!< SAI1 block B PLL Main source clock support */
AnnaBridge 146:22da6e220af6 10188
AnnaBridge 146:22da6e220af6 10189 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
AnnaBridge 146:22da6e220af6 10190 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 10191 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
AnnaBridge 146:22da6e220af6 10192 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10193 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10194 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
AnnaBridge 146:22da6e220af6 10195 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 10196 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
AnnaBridge 146:22da6e220af6 10197 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10198 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10199 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 146:22da6e220af6 10200 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10201 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
AnnaBridge 146:22da6e220af6 10202 #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
AnnaBridge 146:22da6e220af6 10203 #define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
AnnaBridge 146:22da6e220af6 10204 #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
AnnaBridge 146:22da6e220af6 10205 #define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10206 #define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10207
AnnaBridge 146:22da6e220af6 10208 #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
AnnaBridge 146:22da6e220af6 10209 #define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
AnnaBridge 146:22da6e220af6 10210 #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
AnnaBridge 146:22da6e220af6 10211 #define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10212 #define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10213 #define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
AnnaBridge 146:22da6e220af6 10214 #define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10215 #define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
AnnaBridge 146:22da6e220af6 10216
AnnaBridge 146:22da6e220af6 10217 /******************** Bit definition for RCC_CKGATENR register ***************/
AnnaBridge 146:22da6e220af6 10218 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
AnnaBridge 146:22da6e220af6 10219 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10220 #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
AnnaBridge 146:22da6e220af6 10221 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
AnnaBridge 146:22da6e220af6 10222 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10223 #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
AnnaBridge 146:22da6e220af6 10224 #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
AnnaBridge 146:22da6e220af6 10225 #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10226 #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
AnnaBridge 146:22da6e220af6 10227 #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
AnnaBridge 146:22da6e220af6 10228 #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10229 #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
AnnaBridge 146:22da6e220af6 10230 #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
AnnaBridge 146:22da6e220af6 10231 #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10232 #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
AnnaBridge 146:22da6e220af6 10233 #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
AnnaBridge 146:22da6e220af6 10234 #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10235 #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
AnnaBridge 146:22da6e220af6 10236 #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
AnnaBridge 146:22da6e220af6 10237 #define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10238 #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
AnnaBridge 146:22da6e220af6 10239 #define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
AnnaBridge 146:22da6e220af6 10240 #define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10241 #define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
AnnaBridge 146:22da6e220af6 10242
AnnaBridge 146:22da6e220af6 10243 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
AnnaBridge 146:22da6e220af6 10244 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
AnnaBridge 146:22da6e220af6 10245 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
AnnaBridge 146:22da6e220af6 10246 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
AnnaBridge 146:22da6e220af6 10247 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10248 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10249 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
AnnaBridge 146:22da6e220af6 10250 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10251 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
AnnaBridge 146:22da6e220af6 10252 #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
AnnaBridge 146:22da6e220af6 10253 #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10254 #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
AnnaBridge 146:22da6e220af6 10255 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
AnnaBridge 146:22da6e220af6 10256 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
AnnaBridge 146:22da6e220af6 10257 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
AnnaBridge 146:22da6e220af6 10258 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10259 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10260
AnnaBridge 146:22da6e220af6 10261
AnnaBridge 146:22da6e220af6 10262 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10263 /* */
AnnaBridge 146:22da6e220af6 10264 /* RNG */
AnnaBridge 146:22da6e220af6 10265 /* */
AnnaBridge 146:22da6e220af6 10266 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10267 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 146:22da6e220af6 10268 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 146:22da6e220af6 10269 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10270 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 146:22da6e220af6 10271 #define RNG_CR_IE_Pos (3U)
AnnaBridge 146:22da6e220af6 10272 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10273 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 146:22da6e220af6 10274
AnnaBridge 146:22da6e220af6 10275 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 146:22da6e220af6 10276 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 146:22da6e220af6 10277 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10278 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 146:22da6e220af6 10279 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 146:22da6e220af6 10280 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10281 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 146:22da6e220af6 10282 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 146:22da6e220af6 10283 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10284 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 146:22da6e220af6 10285 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 146:22da6e220af6 10286 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10287 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 146:22da6e220af6 10288 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 146:22da6e220af6 10289 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10290 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 146:22da6e220af6 10291
AnnaBridge 146:22da6e220af6 10292 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10293 /* */
AnnaBridge 146:22da6e220af6 10294 /* Real-Time Clock (RTC) */
AnnaBridge 146:22da6e220af6 10295 /* */
AnnaBridge 146:22da6e220af6 10296 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10297 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 146:22da6e220af6 10298 #define RTC_TR_PM_Pos (22U)
AnnaBridge 146:22da6e220af6 10299 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10300 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 146:22da6e220af6 10301 #define RTC_TR_HT_Pos (20U)
AnnaBridge 146:22da6e220af6 10302 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 10303 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 146:22da6e220af6 10304 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10305 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10306 #define RTC_TR_HU_Pos (16U)
AnnaBridge 146:22da6e220af6 10307 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 10308 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 146:22da6e220af6 10309 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10310 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10311 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10312 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10313 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 146:22da6e220af6 10314 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 10315 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 146:22da6e220af6 10316 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10317 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10318 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10319 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 146:22da6e220af6 10320 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10321 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 146:22da6e220af6 10322 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10323 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10324 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10325 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10326 #define RTC_TR_ST_Pos (4U)
AnnaBridge 146:22da6e220af6 10327 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 10328 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 146:22da6e220af6 10329 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10330 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10331 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10332 #define RTC_TR_SU_Pos (0U)
AnnaBridge 146:22da6e220af6 10333 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10334 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 146:22da6e220af6 10335 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10336 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10337 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10338 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10339
AnnaBridge 146:22da6e220af6 10340 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 146:22da6e220af6 10341 #define RTC_DR_YT_Pos (20U)
AnnaBridge 146:22da6e220af6 10342 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 10343 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 146:22da6e220af6 10344 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10345 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10346 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10347 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10348 #define RTC_DR_YU_Pos (16U)
AnnaBridge 146:22da6e220af6 10349 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 10350 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 146:22da6e220af6 10351 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10352 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10353 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10354 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10355 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 146:22da6e220af6 10356 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 146:22da6e220af6 10357 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 146:22da6e220af6 10358 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10359 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10360 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10361 #define RTC_DR_MT_Pos (12U)
AnnaBridge 146:22da6e220af6 10362 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10363 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 146:22da6e220af6 10364 #define RTC_DR_MU_Pos (8U)
AnnaBridge 146:22da6e220af6 10365 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10366 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 146:22da6e220af6 10367 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10368 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10369 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10370 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10371 #define RTC_DR_DT_Pos (4U)
AnnaBridge 146:22da6e220af6 10372 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 10373 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 146:22da6e220af6 10374 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10375 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10376 #define RTC_DR_DU_Pos (0U)
AnnaBridge 146:22da6e220af6 10377 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10378 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 146:22da6e220af6 10379 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10380 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10381 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10382 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10383
AnnaBridge 146:22da6e220af6 10384 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 146:22da6e220af6 10385 #define RTC_CR_COE_Pos (23U)
AnnaBridge 146:22da6e220af6 10386 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10387 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 146:22da6e220af6 10388 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 146:22da6e220af6 10389 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 146:22da6e220af6 10390 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 146:22da6e220af6 10391 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10392 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10393 #define RTC_CR_POL_Pos (20U)
AnnaBridge 146:22da6e220af6 10394 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10395 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 146:22da6e220af6 10396 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 146:22da6e220af6 10397 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10398 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 146:22da6e220af6 10399 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 146:22da6e220af6 10400 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10401 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 146:22da6e220af6 10402 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 146:22da6e220af6 10403 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10404 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 146:22da6e220af6 10405 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 146:22da6e220af6 10406 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10407 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 146:22da6e220af6 10408 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 146:22da6e220af6 10409 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10410 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 146:22da6e220af6 10411 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 146:22da6e220af6 10412 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10413 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 146:22da6e220af6 10414 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 146:22da6e220af6 10415 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10416 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 146:22da6e220af6 10417 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 146:22da6e220af6 10418 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10419 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 146:22da6e220af6 10420 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 146:22da6e220af6 10421 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10422 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 146:22da6e220af6 10423 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 146:22da6e220af6 10424 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10425 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 146:22da6e220af6 10426 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 146:22da6e220af6 10427 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10428 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 146:22da6e220af6 10429 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 146:22da6e220af6 10430 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10431 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 146:22da6e220af6 10432 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 146:22da6e220af6 10433 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10434 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 146:22da6e220af6 10435 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 146:22da6e220af6 10436 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10437 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 146:22da6e220af6 10438 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 146:22da6e220af6 10439 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10440 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 146:22da6e220af6 10441 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 146:22da6e220af6 10442 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10443 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 146:22da6e220af6 10444 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 146:22da6e220af6 10445 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10446 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 146:22da6e220af6 10447 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 146:22da6e220af6 10448 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 10449 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 146:22da6e220af6 10450 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10451 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10452 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10453
AnnaBridge 146:22da6e220af6 10454 /* Legacy defines */
AnnaBridge 146:22da6e220af6 10455 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 146:22da6e220af6 10456
AnnaBridge 146:22da6e220af6 10457 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 146:22da6e220af6 10458 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 146:22da6e220af6 10459 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10460 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 146:22da6e220af6 10461 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 146:22da6e220af6 10462 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10463 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 146:22da6e220af6 10464 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 146:22da6e220af6 10465 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10466 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 146:22da6e220af6 10467 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 146:22da6e220af6 10468 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10469 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 146:22da6e220af6 10470 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 146:22da6e220af6 10471 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10472 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 146:22da6e220af6 10473 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 146:22da6e220af6 10474 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10475 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 146:22da6e220af6 10476 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 146:22da6e220af6 10477 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10478 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 146:22da6e220af6 10479 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 146:22da6e220af6 10480 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10481 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 146:22da6e220af6 10482 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 146:22da6e220af6 10483 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10484 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 146:22da6e220af6 10485 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 146:22da6e220af6 10486 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10487 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 146:22da6e220af6 10488 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 146:22da6e220af6 10489 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10490 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 146:22da6e220af6 10491 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 146:22da6e220af6 10492 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10493 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 146:22da6e220af6 10494 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 146:22da6e220af6 10495 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10496 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 146:22da6e220af6 10497 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 146:22da6e220af6 10498 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10499 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 146:22da6e220af6 10500 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 146:22da6e220af6 10501 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10502 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 146:22da6e220af6 10503 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 146:22da6e220af6 10504 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10505 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 146:22da6e220af6 10506
AnnaBridge 146:22da6e220af6 10507 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 146:22da6e220af6 10508 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 146:22da6e220af6 10509 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 146:22da6e220af6 10510 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 146:22da6e220af6 10511 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 146:22da6e220af6 10512 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 146:22da6e220af6 10513 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 146:22da6e220af6 10514
AnnaBridge 146:22da6e220af6 10515 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 146:22da6e220af6 10516 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 146:22da6e220af6 10517 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 10518 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 146:22da6e220af6 10519
AnnaBridge 146:22da6e220af6 10520 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 146:22da6e220af6 10521 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 146:22da6e220af6 10522 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10523 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 146:22da6e220af6 10524 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 146:22da6e220af6 10525 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 10526 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 146:22da6e220af6 10527
AnnaBridge 146:22da6e220af6 10528 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 146:22da6e220af6 10529 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 146:22da6e220af6 10530 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10531 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 146:22da6e220af6 10532 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 146:22da6e220af6 10533 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10534 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 146:22da6e220af6 10535 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 146:22da6e220af6 10536 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 10537 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 146:22da6e220af6 10538 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10539 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 10540 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 146:22da6e220af6 10541 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 10542 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 146:22da6e220af6 10543 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10544 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10545 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10546 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10547 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 146:22da6e220af6 10548 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10549 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 146:22da6e220af6 10550 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 146:22da6e220af6 10551 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10552 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 146:22da6e220af6 10553 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 146:22da6e220af6 10554 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 10555 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 146:22da6e220af6 10556 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10557 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10558 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 146:22da6e220af6 10559 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 10560 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 146:22da6e220af6 10561 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10562 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10563 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10564 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10565 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 146:22da6e220af6 10566 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10567 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 146:22da6e220af6 10568 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 146:22da6e220af6 10569 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 10570 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 146:22da6e220af6 10571 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10572 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10573 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10574 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 146:22da6e220af6 10575 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10576 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 146:22da6e220af6 10577 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10578 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10579 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10580 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10581 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 146:22da6e220af6 10582 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10583 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 146:22da6e220af6 10584 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 146:22da6e220af6 10585 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 10586 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 146:22da6e220af6 10587 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10588 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10589 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10590 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 146:22da6e220af6 10591 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10592 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 146:22da6e220af6 10593 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10594 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10595 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10596 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10597
AnnaBridge 146:22da6e220af6 10598 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 146:22da6e220af6 10599 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 146:22da6e220af6 10600 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10601 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 146:22da6e220af6 10602 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 146:22da6e220af6 10603 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 10604 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 146:22da6e220af6 10605 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 146:22da6e220af6 10606 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 146:22da6e220af6 10607 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 146:22da6e220af6 10608 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 10609 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 10610 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 146:22da6e220af6 10611 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 10612 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 146:22da6e220af6 10613 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10614 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10615 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10616 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10617 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 146:22da6e220af6 10618 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 10619 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 146:22da6e220af6 10620 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 146:22da6e220af6 10621 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10622 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 146:22da6e220af6 10623 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 146:22da6e220af6 10624 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 10625 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 146:22da6e220af6 10626 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10627 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10628 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 146:22da6e220af6 10629 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 10630 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 146:22da6e220af6 10631 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10632 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10633 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10634 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10635 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 146:22da6e220af6 10636 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10637 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 146:22da6e220af6 10638 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 146:22da6e220af6 10639 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 10640 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 146:22da6e220af6 10641 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10642 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10643 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10644 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 146:22da6e220af6 10645 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10646 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 146:22da6e220af6 10647 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10648 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10649 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10650 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10651 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 146:22da6e220af6 10652 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10653 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 146:22da6e220af6 10654 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 146:22da6e220af6 10655 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 10656 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 146:22da6e220af6 10657 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10658 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10659 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10660 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 146:22da6e220af6 10661 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10662 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 146:22da6e220af6 10663 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10664 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10665 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10666 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10667
AnnaBridge 146:22da6e220af6 10668 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 146:22da6e220af6 10669 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 146:22da6e220af6 10670 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 10671 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 146:22da6e220af6 10672
AnnaBridge 146:22da6e220af6 10673 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 146:22da6e220af6 10674 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 146:22da6e220af6 10675 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 10676 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 146:22da6e220af6 10677
AnnaBridge 146:22da6e220af6 10678 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 146:22da6e220af6 10679 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 146:22da6e220af6 10680 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 146:22da6e220af6 10681 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 146:22da6e220af6 10682 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 146:22da6e220af6 10683 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 10684 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 146:22da6e220af6 10685
AnnaBridge 146:22da6e220af6 10686 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 146:22da6e220af6 10687 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 146:22da6e220af6 10688 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 10689 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 146:22da6e220af6 10690 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 146:22da6e220af6 10691 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 10692 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 146:22da6e220af6 10693 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 10694 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 10695 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 146:22da6e220af6 10696 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 146:22da6e220af6 10697 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 146:22da6e220af6 10698 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10699 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10700 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10701 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 10702 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 146:22da6e220af6 10703 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 10704 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 146:22da6e220af6 10705 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10706 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10707 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10708 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 146:22da6e220af6 10709 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10710 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 146:22da6e220af6 10711 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10712 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10713 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10714 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10715 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 146:22da6e220af6 10716 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 10717 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 146:22da6e220af6 10718 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10719 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10720 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10721 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 146:22da6e220af6 10722 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10723 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 146:22da6e220af6 10724 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10725 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10726 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10727 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10728
AnnaBridge 146:22da6e220af6 10729 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 146:22da6e220af6 10730 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 146:22da6e220af6 10731 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 146:22da6e220af6 10732 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 146:22da6e220af6 10733 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10734 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10735 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10736 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 146:22da6e220af6 10737 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10738 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 146:22da6e220af6 10739 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 146:22da6e220af6 10740 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 10741 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 146:22da6e220af6 10742 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10743 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10744 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10745 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10746 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 146:22da6e220af6 10747 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 10748 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 146:22da6e220af6 10749 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10750 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10751 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 146:22da6e220af6 10752 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 10753 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 146:22da6e220af6 10754 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10755 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10756 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10757 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10758
AnnaBridge 146:22da6e220af6 10759 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 146:22da6e220af6 10760 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 146:22da6e220af6 10761 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 10762 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 146:22da6e220af6 10763
AnnaBridge 146:22da6e220af6 10764 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 146:22da6e220af6 10765 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 146:22da6e220af6 10766 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10767 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 146:22da6e220af6 10768 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 146:22da6e220af6 10769 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10770 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 146:22da6e220af6 10771 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 146:22da6e220af6 10772 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10773 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 146:22da6e220af6 10774 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 146:22da6e220af6 10775 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 146:22da6e220af6 10776 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 146:22da6e220af6 10777 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10778 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10779 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10780 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10781 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10782 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10783 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 10784 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10785 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10786
AnnaBridge 146:22da6e220af6 10787 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 146:22da6e220af6 10788 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 146:22da6e220af6 10789 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 10790 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 146:22da6e220af6 10791 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 146:22da6e220af6 10792 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 10793 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 146:22da6e220af6 10794 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 146:22da6e220af6 10795 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 10796 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 146:22da6e220af6 10797 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 146:22da6e220af6 10798 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 10799 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 146:22da6e220af6 10800 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 146:22da6e220af6 10801 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 146:22da6e220af6 10802 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 146:22da6e220af6 10803 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 10804 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 10805 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 146:22da6e220af6 10806 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 146:22da6e220af6 10807 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 146:22da6e220af6 10808 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 10809 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 10810 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 146:22da6e220af6 10811 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 146:22da6e220af6 10812 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 146:22da6e220af6 10813 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 10814 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 10815 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 10816 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 146:22da6e220af6 10817 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 10818 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 146:22da6e220af6 10819 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 146:22da6e220af6 10820 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10821 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 146:22da6e220af6 10822 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 146:22da6e220af6 10823 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10824 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 146:22da6e220af6 10825 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 146:22da6e220af6 10826 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10827 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 146:22da6e220af6 10828 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 146:22da6e220af6 10829 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10830 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 146:22da6e220af6 10831 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 146:22da6e220af6 10832 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10833 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 146:22da6e220af6 10834
AnnaBridge 146:22da6e220af6 10835 /* Legacy defines */
AnnaBridge 146:22da6e220af6 10836 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
AnnaBridge 146:22da6e220af6 10837
AnnaBridge 146:22da6e220af6 10838 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 146:22da6e220af6 10839 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 146:22da6e220af6 10840 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 10841 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 146:22da6e220af6 10842 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10843 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10844 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10845 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10846 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 146:22da6e220af6 10847 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 146:22da6e220af6 10848 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 146:22da6e220af6 10849
AnnaBridge 146:22da6e220af6 10850 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 146:22da6e220af6 10851 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 146:22da6e220af6 10852 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 146:22da6e220af6 10853 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 146:22da6e220af6 10854 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 10855 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 10856 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 10857 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 10858 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 146:22da6e220af6 10859 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 146:22da6e220af6 10860 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 146:22da6e220af6 10861
AnnaBridge 146:22da6e220af6 10862 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 146:22da6e220af6 10863 #define RTC_BKP0R_Pos (0U)
AnnaBridge 146:22da6e220af6 10864 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10865 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 146:22da6e220af6 10866
AnnaBridge 146:22da6e220af6 10867 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 146:22da6e220af6 10868 #define RTC_BKP1R_Pos (0U)
AnnaBridge 146:22da6e220af6 10869 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10870 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 146:22da6e220af6 10871
AnnaBridge 146:22da6e220af6 10872 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 146:22da6e220af6 10873 #define RTC_BKP2R_Pos (0U)
AnnaBridge 146:22da6e220af6 10874 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10875 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 146:22da6e220af6 10876
AnnaBridge 146:22da6e220af6 10877 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 146:22da6e220af6 10878 #define RTC_BKP3R_Pos (0U)
AnnaBridge 146:22da6e220af6 10879 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10880 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 146:22da6e220af6 10881
AnnaBridge 146:22da6e220af6 10882 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 146:22da6e220af6 10883 #define RTC_BKP4R_Pos (0U)
AnnaBridge 146:22da6e220af6 10884 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10885 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 146:22da6e220af6 10886
AnnaBridge 146:22da6e220af6 10887 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 146:22da6e220af6 10888 #define RTC_BKP5R_Pos (0U)
AnnaBridge 146:22da6e220af6 10889 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10890 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 146:22da6e220af6 10891
AnnaBridge 146:22da6e220af6 10892 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 146:22da6e220af6 10893 #define RTC_BKP6R_Pos (0U)
AnnaBridge 146:22da6e220af6 10894 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10895 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 146:22da6e220af6 10896
AnnaBridge 146:22da6e220af6 10897 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 146:22da6e220af6 10898 #define RTC_BKP7R_Pos (0U)
AnnaBridge 146:22da6e220af6 10899 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10900 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 146:22da6e220af6 10901
AnnaBridge 146:22da6e220af6 10902 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 146:22da6e220af6 10903 #define RTC_BKP8R_Pos (0U)
AnnaBridge 146:22da6e220af6 10904 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10905 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 146:22da6e220af6 10906
AnnaBridge 146:22da6e220af6 10907 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 146:22da6e220af6 10908 #define RTC_BKP9R_Pos (0U)
AnnaBridge 146:22da6e220af6 10909 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10910 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 146:22da6e220af6 10911
AnnaBridge 146:22da6e220af6 10912 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 146:22da6e220af6 10913 #define RTC_BKP10R_Pos (0U)
AnnaBridge 146:22da6e220af6 10914 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10915 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 146:22da6e220af6 10916
AnnaBridge 146:22da6e220af6 10917 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 146:22da6e220af6 10918 #define RTC_BKP11R_Pos (0U)
AnnaBridge 146:22da6e220af6 10919 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10920 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 146:22da6e220af6 10921
AnnaBridge 146:22da6e220af6 10922 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 146:22da6e220af6 10923 #define RTC_BKP12R_Pos (0U)
AnnaBridge 146:22da6e220af6 10924 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10925 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 146:22da6e220af6 10926
AnnaBridge 146:22da6e220af6 10927 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 146:22da6e220af6 10928 #define RTC_BKP13R_Pos (0U)
AnnaBridge 146:22da6e220af6 10929 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10930 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 146:22da6e220af6 10931
AnnaBridge 146:22da6e220af6 10932 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 146:22da6e220af6 10933 #define RTC_BKP14R_Pos (0U)
AnnaBridge 146:22da6e220af6 10934 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10935 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 146:22da6e220af6 10936
AnnaBridge 146:22da6e220af6 10937 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 146:22da6e220af6 10938 #define RTC_BKP15R_Pos (0U)
AnnaBridge 146:22da6e220af6 10939 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10940 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 146:22da6e220af6 10941
AnnaBridge 146:22da6e220af6 10942 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 146:22da6e220af6 10943 #define RTC_BKP16R_Pos (0U)
AnnaBridge 146:22da6e220af6 10944 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10945 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 146:22da6e220af6 10946
AnnaBridge 146:22da6e220af6 10947 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 146:22da6e220af6 10948 #define RTC_BKP17R_Pos (0U)
AnnaBridge 146:22da6e220af6 10949 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10950 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 146:22da6e220af6 10951
AnnaBridge 146:22da6e220af6 10952 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 146:22da6e220af6 10953 #define RTC_BKP18R_Pos (0U)
AnnaBridge 146:22da6e220af6 10954 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10955 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 146:22da6e220af6 10956
AnnaBridge 146:22da6e220af6 10957 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 146:22da6e220af6 10958 #define RTC_BKP19R_Pos (0U)
AnnaBridge 146:22da6e220af6 10959 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 10960 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 146:22da6e220af6 10961
AnnaBridge 146:22da6e220af6 10962 /******************** Number of backup registers ******************************/
AnnaBridge 146:22da6e220af6 10963 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 146:22da6e220af6 10964
AnnaBridge 146:22da6e220af6 10965 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10966 /* */
AnnaBridge 146:22da6e220af6 10967 /* Serial Audio Interface */
AnnaBridge 146:22da6e220af6 10968 /* */
AnnaBridge 146:22da6e220af6 10969 /******************************************************************************/
AnnaBridge 146:22da6e220af6 10970 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 146:22da6e220af6 10971 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 146:22da6e220af6 10972 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 10973 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 146:22da6e220af6 10974 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10975 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10976
AnnaBridge 146:22da6e220af6 10977 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 146:22da6e220af6 10978 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 10979 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 146:22da6e220af6 10980 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 10981 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 10982
AnnaBridge 146:22da6e220af6 10983 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 146:22da6e220af6 10984 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 146:22da6e220af6 10985 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 10986 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 146:22da6e220af6 10987 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 10988 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 10989
AnnaBridge 146:22da6e220af6 10990 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 146:22da6e220af6 10991 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 10992 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 146:22da6e220af6 10993 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 10994 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 10995
AnnaBridge 146:22da6e220af6 10996 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 146:22da6e220af6 10997 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 146:22da6e220af6 10998 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 146:22da6e220af6 10999 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11000 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11001 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11002
AnnaBridge 146:22da6e220af6 11003 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 146:22da6e220af6 11004 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11005 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 146:22da6e220af6 11006 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 146:22da6e220af6 11007 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11008 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 146:22da6e220af6 11009
AnnaBridge 146:22da6e220af6 11010 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 146:22da6e220af6 11011 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 11012 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 146:22da6e220af6 11013 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11014 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11015
AnnaBridge 146:22da6e220af6 11016 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 146:22da6e220af6 11017 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11018 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 146:22da6e220af6 11019 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 146:22da6e220af6 11020 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11021 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 146:22da6e220af6 11022 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 146:22da6e220af6 11023 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11024 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 146:22da6e220af6 11025 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 146:22da6e220af6 11026 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 11027 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 146:22da6e220af6 11028 #define SAI_xCR1_NODIV_Pos (19U)
AnnaBridge 146:22da6e220af6 11029 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 11030 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
AnnaBridge 146:22da6e220af6 11031
AnnaBridge 146:22da6e220af6 11032 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 146:22da6e220af6 11033 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 146:22da6e220af6 11034 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 146:22da6e220af6 11035 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 11036 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 11037 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 11038 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 11039
AnnaBridge 146:22da6e220af6 11040 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 146:22da6e220af6 11041 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 146:22da6e220af6 11042 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 11043 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 146:22da6e220af6 11044 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11045 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11046 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11047
AnnaBridge 146:22da6e220af6 11048 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 146:22da6e220af6 11049 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11050 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 146:22da6e220af6 11051 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 146:22da6e220af6 11052 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11053 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 146:22da6e220af6 11054 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 146:22da6e220af6 11055 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11056 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 146:22da6e220af6 11057 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 146:22da6e220af6 11058 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11059 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 146:22da6e220af6 11060
AnnaBridge 146:22da6e220af6 11061 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 146:22da6e220af6 11062 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 146:22da6e220af6 11063 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 146:22da6e220af6 11064 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11065 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11066 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11067 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11068 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11069 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11070
AnnaBridge 146:22da6e220af6 11071 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 146:22da6e220af6 11072 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11073 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
AnnaBridge 146:22da6e220af6 11074
AnnaBridge 146:22da6e220af6 11075 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 146:22da6e220af6 11076 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 11077 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 146:22da6e220af6 11078 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11079 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 11080
AnnaBridge 146:22da6e220af6 11081 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 146:22da6e220af6 11082 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 146:22da6e220af6 11083 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 11084 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
AnnaBridge 146:22da6e220af6 11085 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11086 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11087 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11088 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11089 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11090 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11091 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11092 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11093
AnnaBridge 146:22da6e220af6 11094 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 146:22da6e220af6 11095 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 146:22da6e220af6 11096 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
AnnaBridge 146:22da6e220af6 11097 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11098 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11099 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11100 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11101 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11102 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11103 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11104
AnnaBridge 146:22da6e220af6 11105 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 146:22da6e220af6 11106 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11107 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
AnnaBridge 146:22da6e220af6 11108 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 146:22da6e220af6 11109 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 11110 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 146:22da6e220af6 11111 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 146:22da6e220af6 11112 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 11113 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
AnnaBridge 146:22da6e220af6 11114 /* Legacy defines */
AnnaBridge 146:22da6e220af6 11115 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
AnnaBridge 146:22da6e220af6 11116
AnnaBridge 146:22da6e220af6 11117 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 146:22da6e220af6 11118 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 146:22da6e220af6 11119 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 11120 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 146:22da6e220af6 11121 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11122 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11123 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11124 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11125 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11126
AnnaBridge 146:22da6e220af6 11127 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 146:22da6e220af6 11128 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 11129 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 146:22da6e220af6 11130 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11131 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11132
AnnaBridge 146:22da6e220af6 11133 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 146:22da6e220af6 11134 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 11135 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 146:22da6e220af6 11136 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11137 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11138 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11139 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11140
AnnaBridge 146:22da6e220af6 11141 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 146:22da6e220af6 11142 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 11143 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 146:22da6e220af6 11144
AnnaBridge 146:22da6e220af6 11145 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 146:22da6e220af6 11146 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 146:22da6e220af6 11147 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11148 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 146:22da6e220af6 11149 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 146:22da6e220af6 11150 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11151 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 146:22da6e220af6 11152 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 146:22da6e220af6 11153 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11154 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 146:22da6e220af6 11155 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 146:22da6e220af6 11156 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11157 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 146:22da6e220af6 11158 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 146:22da6e220af6 11159 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11160 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 146:22da6e220af6 11161 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 146:22da6e220af6 11162 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11163 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 146:22da6e220af6 11164 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 146:22da6e220af6 11165 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11166 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 146:22da6e220af6 11167
AnnaBridge 146:22da6e220af6 11168 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 146:22da6e220af6 11169 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 146:22da6e220af6 11170 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11171 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 146:22da6e220af6 11172 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 146:22da6e220af6 11173 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11174 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 146:22da6e220af6 11175 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 146:22da6e220af6 11176 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11177 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 146:22da6e220af6 11178 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 146:22da6e220af6 11179 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11180 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 146:22da6e220af6 11181 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 146:22da6e220af6 11182 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11183 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 146:22da6e220af6 11184 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 146:22da6e220af6 11185 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11186 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 146:22da6e220af6 11187 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 146:22da6e220af6 11188 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11189 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 146:22da6e220af6 11190
AnnaBridge 146:22da6e220af6 11191 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 146:22da6e220af6 11192 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 146:22da6e220af6 11193 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 146:22da6e220af6 11194 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11195 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 11196 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 11197
AnnaBridge 146:22da6e220af6 11198 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 146:22da6e220af6 11199 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 146:22da6e220af6 11200 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11201 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 146:22da6e220af6 11202 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 146:22da6e220af6 11203 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11204 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 146:22da6e220af6 11205 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 146:22da6e220af6 11206 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11207 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 146:22da6e220af6 11208 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 146:22da6e220af6 11209 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11210 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 146:22da6e220af6 11211 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 146:22da6e220af6 11212 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11213 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 146:22da6e220af6 11214 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 146:22da6e220af6 11215 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11216 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 146:22da6e220af6 11217 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 146:22da6e220af6 11218 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11219 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
AnnaBridge 146:22da6e220af6 11220
AnnaBridge 146:22da6e220af6 11221 /****************** Bit definition for SAI_xDR register ******************/
AnnaBridge 146:22da6e220af6 11222 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 146:22da6e220af6 11223 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11224 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
AnnaBridge 146:22da6e220af6 11225
AnnaBridge 146:22da6e220af6 11226
AnnaBridge 146:22da6e220af6 11227 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11228 /* */
AnnaBridge 146:22da6e220af6 11229 /* SD host Interface */
AnnaBridge 146:22da6e220af6 11230 /* */
AnnaBridge 146:22da6e220af6 11231 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11232 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 146:22da6e220af6 11233 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 146:22da6e220af6 11234 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 11235 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 146:22da6e220af6 11236 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 146:22da6e220af6 11237 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
AnnaBridge 146:22da6e220af6 11238
AnnaBridge 146:22da6e220af6 11239 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 146:22da6e220af6 11240 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 146:22da6e220af6 11241 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 11242 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 146:22da6e220af6 11243 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 146:22da6e220af6 11244 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11245 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 146:22da6e220af6 11246 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 146:22da6e220af6 11247 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11248 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 146:22da6e220af6 11249 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 146:22da6e220af6 11250 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11251 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 146:22da6e220af6 11252
AnnaBridge 146:22da6e220af6 11253 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 146:22da6e220af6 11254 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 146:22da6e220af6 11255 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 146:22da6e220af6 11256 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 11257 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 11258
AnnaBridge 146:22da6e220af6 11259 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 146:22da6e220af6 11260 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11261 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 146:22da6e220af6 11262 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 146:22da6e220af6 11263 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11264 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 146:22da6e220af6 11265
AnnaBridge 146:22da6e220af6 11266 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 146:22da6e220af6 11267 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 146:22da6e220af6 11268 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11269 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 146:22da6e220af6 11270
AnnaBridge 146:22da6e220af6 11271 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 146:22da6e220af6 11272 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 146:22da6e220af6 11273 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 11274 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 146:22da6e220af6 11275
AnnaBridge 146:22da6e220af6 11276 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 146:22da6e220af6 11277 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 11278 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 146:22da6e220af6 11279 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 11280 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 11281
AnnaBridge 146:22da6e220af6 11282 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 146:22da6e220af6 11283 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11284 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 146:22da6e220af6 11285 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 146:22da6e220af6 11286 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11287 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 146:22da6e220af6 11288 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 146:22da6e220af6 11289 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11290 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 146:22da6e220af6 11291 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 146:22da6e220af6 11292 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11293 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 146:22da6e220af6 11294
AnnaBridge 146:22da6e220af6 11295 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 146:22da6e220af6 11296 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 146:22da6e220af6 11297 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 146:22da6e220af6 11298 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 146:22da6e220af6 11299
AnnaBridge 146:22da6e220af6 11300 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 146:22da6e220af6 11301 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 146:22da6e220af6 11302 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11303 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 146:22da6e220af6 11304
AnnaBridge 146:22da6e220af6 11305 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 146:22da6e220af6 11306 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 146:22da6e220af6 11307 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11308 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 146:22da6e220af6 11309
AnnaBridge 146:22da6e220af6 11310 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 146:22da6e220af6 11311 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 146:22da6e220af6 11312 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11313 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 146:22da6e220af6 11314
AnnaBridge 146:22da6e220af6 11315 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 146:22da6e220af6 11316 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 146:22da6e220af6 11317 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11318 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 146:22da6e220af6 11319
AnnaBridge 146:22da6e220af6 11320 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 146:22da6e220af6 11321 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 146:22da6e220af6 11322 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11323 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 146:22da6e220af6 11324
AnnaBridge 146:22da6e220af6 11325 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 146:22da6e220af6 11326 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 146:22da6e220af6 11327 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11328 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 146:22da6e220af6 11329
AnnaBridge 146:22da6e220af6 11330 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 146:22da6e220af6 11331 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 146:22da6e220af6 11332 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 146:22da6e220af6 11333 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 146:22da6e220af6 11334
AnnaBridge 146:22da6e220af6 11335 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 146:22da6e220af6 11336 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 146:22da6e220af6 11337 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11338 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 146:22da6e220af6 11339 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 146:22da6e220af6 11340 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11341 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 146:22da6e220af6 11342 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 146:22da6e220af6 11343 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11344 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 146:22da6e220af6 11345 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 146:22da6e220af6 11346 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11347 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 146:22da6e220af6 11348
AnnaBridge 146:22da6e220af6 11349 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 146:22da6e220af6 11350 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 11351 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 146:22da6e220af6 11352 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 11353 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 11354 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 11355 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 11356
AnnaBridge 146:22da6e220af6 11357 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 146:22da6e220af6 11358 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11359 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 146:22da6e220af6 11360 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 146:22da6e220af6 11361 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11362 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 146:22da6e220af6 11363 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 146:22da6e220af6 11364 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11365 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 146:22da6e220af6 11366 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 146:22da6e220af6 11367 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11368 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 146:22da6e220af6 11369
AnnaBridge 146:22da6e220af6 11370 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 146:22da6e220af6 11371 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 146:22da6e220af6 11372 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 146:22da6e220af6 11373 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 146:22da6e220af6 11374
AnnaBridge 146:22da6e220af6 11375 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 146:22da6e220af6 11376 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 146:22da6e220af6 11377 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11378 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 146:22da6e220af6 11379 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 146:22da6e220af6 11380 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11381 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 146:22da6e220af6 11382 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 146:22da6e220af6 11383 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11384 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 146:22da6e220af6 11385 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 146:22da6e220af6 11386 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11387 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 146:22da6e220af6 11388 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 146:22da6e220af6 11389 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11390 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 146:22da6e220af6 11391 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 146:22da6e220af6 11392 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11393 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 146:22da6e220af6 11394 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 146:22da6e220af6 11395 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11396 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 146:22da6e220af6 11397 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 146:22da6e220af6 11398 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11399 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 146:22da6e220af6 11400 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 146:22da6e220af6 11401 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11402 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 146:22da6e220af6 11403 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 146:22da6e220af6 11404 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11405 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 146:22da6e220af6 11406 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 146:22da6e220af6 11407 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11408 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 146:22da6e220af6 11409 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 146:22da6e220af6 11410 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11411 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 146:22da6e220af6 11412 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 146:22da6e220af6 11413 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11414 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 146:22da6e220af6 11415 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 146:22da6e220af6 11416 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11417 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 146:22da6e220af6 11418 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 146:22da6e220af6 11419 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 11420 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 146:22da6e220af6 11421 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 146:22da6e220af6 11422 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11423 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 146:22da6e220af6 11424 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 146:22da6e220af6 11425 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 11426 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 146:22da6e220af6 11427 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 146:22da6e220af6 11428 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 11429 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 146:22da6e220af6 11430 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 146:22da6e220af6 11431 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 11432 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 146:22da6e220af6 11433 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 146:22da6e220af6 11434 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 11435 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 146:22da6e220af6 11436 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 146:22da6e220af6 11437 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 11438 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 146:22da6e220af6 11439 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 146:22da6e220af6 11440 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 11441 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 146:22da6e220af6 11442
AnnaBridge 146:22da6e220af6 11443 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 146:22da6e220af6 11444 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 146:22da6e220af6 11445 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11446 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 146:22da6e220af6 11447 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 146:22da6e220af6 11448 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11449 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 146:22da6e220af6 11450 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 146:22da6e220af6 11451 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11452 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 146:22da6e220af6 11453 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 146:22da6e220af6 11454 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11455 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 146:22da6e220af6 11456 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 146:22da6e220af6 11457 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11458 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 146:22da6e220af6 11459 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 146:22da6e220af6 11460 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11461 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 146:22da6e220af6 11462 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 146:22da6e220af6 11463 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11464 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 146:22da6e220af6 11465 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 146:22da6e220af6 11466 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11467 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 146:22da6e220af6 11468 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 146:22da6e220af6 11469 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11470 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 146:22da6e220af6 11471 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 146:22da6e220af6 11472 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11473 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 146:22da6e220af6 11474 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 146:22da6e220af6 11475 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 11476 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 146:22da6e220af6 11477
AnnaBridge 146:22da6e220af6 11478 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 146:22da6e220af6 11479 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 146:22da6e220af6 11480 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11481 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 146:22da6e220af6 11482 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 146:22da6e220af6 11483 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11484 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 146:22da6e220af6 11485 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 146:22da6e220af6 11486 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11487 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 146:22da6e220af6 11488 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 146:22da6e220af6 11489 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11490 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 146:22da6e220af6 11491 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 146:22da6e220af6 11492 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11493 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 11494 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 146:22da6e220af6 11495 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11496 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 11497 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 146:22da6e220af6 11498 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11499 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 146:22da6e220af6 11500 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 146:22da6e220af6 11501 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11502 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 146:22da6e220af6 11503 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 146:22da6e220af6 11504 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11505 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 146:22da6e220af6 11506 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 146:22da6e220af6 11507 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11508 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 146:22da6e220af6 11509 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 146:22da6e220af6 11510 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11511 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 146:22da6e220af6 11512 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 146:22da6e220af6 11513 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11514 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 146:22da6e220af6 11515 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 146:22da6e220af6 11516 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11517 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 146:22da6e220af6 11518 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 146:22da6e220af6 11519 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11520 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 146:22da6e220af6 11521 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 146:22da6e220af6 11522 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 11523 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 146:22da6e220af6 11524 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 146:22da6e220af6 11525 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11526 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 146:22da6e220af6 11527 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 146:22da6e220af6 11528 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 11529 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 146:22da6e220af6 11530 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 146:22da6e220af6 11531 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 11532 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 146:22da6e220af6 11533 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 146:22da6e220af6 11534 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 11535 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 146:22da6e220af6 11536 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 146:22da6e220af6 11537 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 11538 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 146:22da6e220af6 11539 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 146:22da6e220af6 11540 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 11541 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 146:22da6e220af6 11542 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 146:22da6e220af6 11543 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 11544 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 146:22da6e220af6 11545
AnnaBridge 146:22da6e220af6 11546 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 146:22da6e220af6 11547 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 146:22da6e220af6 11548 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 146:22da6e220af6 11549 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 146:22da6e220af6 11550
AnnaBridge 146:22da6e220af6 11551 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 146:22da6e220af6 11552 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 146:22da6e220af6 11553 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 11554 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 146:22da6e220af6 11555
AnnaBridge 146:22da6e220af6 11556 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11557 /* */
AnnaBridge 146:22da6e220af6 11558 /* Serial Peripheral Interface */
AnnaBridge 146:22da6e220af6 11559 /* */
AnnaBridge 146:22da6e220af6 11560 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11561 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 146:22da6e220af6 11562 #define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
AnnaBridge 146:22da6e220af6 11563
AnnaBridge 146:22da6e220af6 11564 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 146:22da6e220af6 11565 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 146:22da6e220af6 11566 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11567 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 146:22da6e220af6 11568 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 146:22da6e220af6 11569 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11570 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 146:22da6e220af6 11571 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 146:22da6e220af6 11572 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11573 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 146:22da6e220af6 11574
AnnaBridge 146:22da6e220af6 11575 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 146:22da6e220af6 11576 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 146:22da6e220af6 11577 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 146:22da6e220af6 11578 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11579 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11580 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11581
AnnaBridge 146:22da6e220af6 11582 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 146:22da6e220af6 11583 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11584 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 146:22da6e220af6 11585 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 146:22da6e220af6 11586 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11587 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 146:22da6e220af6 11588 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 146:22da6e220af6 11589 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11590 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 146:22da6e220af6 11591 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 146:22da6e220af6 11592 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11593 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 146:22da6e220af6 11594 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 146:22da6e220af6 11595 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11596 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 146:22da6e220af6 11597 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 146:22da6e220af6 11598 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11599 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 146:22da6e220af6 11600 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 146:22da6e220af6 11601 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11602 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 146:22da6e220af6 11603 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 146:22da6e220af6 11604 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 11605 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 146:22da6e220af6 11606 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 146:22da6e220af6 11607 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 11608 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 146:22da6e220af6 11609 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 146:22da6e220af6 11610 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 11611 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 146:22da6e220af6 11612
AnnaBridge 146:22da6e220af6 11613 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 146:22da6e220af6 11614 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 146:22da6e220af6 11615 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11616 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 146:22da6e220af6 11617 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 146:22da6e220af6 11618 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11619 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 146:22da6e220af6 11620 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 146:22da6e220af6 11621 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11622 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 146:22da6e220af6 11623 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 146:22da6e220af6 11624 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11625 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 146:22da6e220af6 11626 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 146:22da6e220af6 11627 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11628 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 11629 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 146:22da6e220af6 11630 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11631 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 146:22da6e220af6 11632 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 146:22da6e220af6 11633 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11634 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
AnnaBridge 146:22da6e220af6 11635
AnnaBridge 146:22da6e220af6 11636 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 146:22da6e220af6 11637 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 146:22da6e220af6 11638 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11639 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 146:22da6e220af6 11640 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 146:22da6e220af6 11641 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11642 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 146:22da6e220af6 11643 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 146:22da6e220af6 11644 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11645 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 146:22da6e220af6 11646 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 146:22da6e220af6 11647 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11648 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 146:22da6e220af6 11649 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 146:22da6e220af6 11650 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11651 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 146:22da6e220af6 11652 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 146:22da6e220af6 11653 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11654 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 146:22da6e220af6 11655 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 146:22da6e220af6 11656 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 11657 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 146:22da6e220af6 11658 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 146:22da6e220af6 11659 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11660 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 146:22da6e220af6 11661 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 146:22da6e220af6 11662 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11663 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 146:22da6e220af6 11664
AnnaBridge 146:22da6e220af6 11665 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 146:22da6e220af6 11666 #define SPI_DR_DR_Pos (0U)
AnnaBridge 146:22da6e220af6 11667 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 11668 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 146:22da6e220af6 11669
AnnaBridge 146:22da6e220af6 11670 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 146:22da6e220af6 11671 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 146:22da6e220af6 11672 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 11673 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 146:22da6e220af6 11674
AnnaBridge 146:22da6e220af6 11675 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 146:22da6e220af6 11676 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 146:22da6e220af6 11677 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 11678 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 146:22da6e220af6 11679
AnnaBridge 146:22da6e220af6 11680 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 146:22da6e220af6 11681 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 146:22da6e220af6 11682 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 11683 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 146:22da6e220af6 11684
AnnaBridge 146:22da6e220af6 11685 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 146:22da6e220af6 11686 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 146:22da6e220af6 11687 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11688 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 146:22da6e220af6 11689
AnnaBridge 146:22da6e220af6 11690 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 146:22da6e220af6 11691 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 146:22da6e220af6 11692 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 146:22da6e220af6 11693 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11694 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 11695
AnnaBridge 146:22da6e220af6 11696 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 146:22da6e220af6 11697 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 11698 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 146:22da6e220af6 11699
AnnaBridge 146:22da6e220af6 11700 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 146:22da6e220af6 11701 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 146:22da6e220af6 11702 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 146:22da6e220af6 11703 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 11704 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 11705
AnnaBridge 146:22da6e220af6 11706 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 146:22da6e220af6 11707 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 11708 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 146:22da6e220af6 11709
AnnaBridge 146:22da6e220af6 11710 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 146:22da6e220af6 11711 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 11712 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 146:22da6e220af6 11713 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11714 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11715
AnnaBridge 146:22da6e220af6 11716 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 146:22da6e220af6 11717 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 11718 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 146:22da6e220af6 11719 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 146:22da6e220af6 11720 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 11721 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 146:22da6e220af6 11722 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
AnnaBridge 146:22da6e220af6 11723 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 11724 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
AnnaBridge 146:22da6e220af6 11725
AnnaBridge 146:22da6e220af6 11726 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 146:22da6e220af6 11727 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 146:22da6e220af6 11728 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 11729 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 146:22da6e220af6 11730 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 146:22da6e220af6 11731 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 11732 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 146:22da6e220af6 11733 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 146:22da6e220af6 11734 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 11735 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 146:22da6e220af6 11736
AnnaBridge 146:22da6e220af6 11737 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11738 /* */
AnnaBridge 146:22da6e220af6 11739 /* SYSCFG */
AnnaBridge 146:22da6e220af6 11740 /* */
AnnaBridge 146:22da6e220af6 11741 /******************************************************************************/
AnnaBridge 146:22da6e220af6 11742 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 146:22da6e220af6 11743 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 146:22da6e220af6 11744 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 11745 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 146:22da6e220af6 11746 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 11747 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 11748 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 146:22da6e220af6 11749 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 146:22da6e220af6 11750 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 11751 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 146:22da6e220af6 11752
AnnaBridge 146:22da6e220af6 11753 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 146:22da6e220af6 11754 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 146:22da6e220af6 11755 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 11756 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 146:22da6e220af6 11757 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 146:22da6e220af6 11758 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 11759 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 146:22da6e220af6 11760 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 146:22da6e220af6 11761 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 11762 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 146:22da6e220af6 11763 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 146:22da6e220af6 11764 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 11765 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 146:22da6e220af6 11766 /**
AnnaBridge 146:22da6e220af6 11767 * @brief EXTI0 configuration
AnnaBridge 146:22da6e220af6 11768 */
AnnaBridge 146:22da6e220af6 11769 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 146:22da6e220af6 11770 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 146:22da6e220af6 11771 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 146:22da6e220af6 11772 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 146:22da6e220af6 11773 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 146:22da6e220af6 11774 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 146:22da6e220af6 11775 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 146:22da6e220af6 11776 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 146:22da6e220af6 11777
AnnaBridge 146:22da6e220af6 11778 /**
AnnaBridge 146:22da6e220af6 11779 * @brief EXTI1 configuration
AnnaBridge 146:22da6e220af6 11780 */
AnnaBridge 146:22da6e220af6 11781 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 146:22da6e220af6 11782 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 146:22da6e220af6 11783 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 146:22da6e220af6 11784 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 146:22da6e220af6 11785 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 146:22da6e220af6 11786 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 146:22da6e220af6 11787 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 146:22da6e220af6 11788 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 146:22da6e220af6 11789
AnnaBridge 146:22da6e220af6 11790 /**
AnnaBridge 146:22da6e220af6 11791 * @brief EXTI2 configuration
AnnaBridge 146:22da6e220af6 11792 */
AnnaBridge 146:22da6e220af6 11793 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 146:22da6e220af6 11794 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 146:22da6e220af6 11795 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 146:22da6e220af6 11796 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 146:22da6e220af6 11797 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 146:22da6e220af6 11798 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 146:22da6e220af6 11799 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 146:22da6e220af6 11800 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 146:22da6e220af6 11801
AnnaBridge 146:22da6e220af6 11802 /**
AnnaBridge 146:22da6e220af6 11803 * @brief EXTI3 configuration
AnnaBridge 146:22da6e220af6 11804 */
AnnaBridge 146:22da6e220af6 11805 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 146:22da6e220af6 11806 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 146:22da6e220af6 11807 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 146:22da6e220af6 11808 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 146:22da6e220af6 11809 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 146:22da6e220af6 11810 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 146:22da6e220af6 11811 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 146:22da6e220af6 11812 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 146:22da6e220af6 11813
AnnaBridge 146:22da6e220af6 11814 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 146:22da6e220af6 11815 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 146:22da6e220af6 11816 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 11817 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 146:22da6e220af6 11818 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 146:22da6e220af6 11819 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 11820 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 146:22da6e220af6 11821 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 146:22da6e220af6 11822 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 11823 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 146:22da6e220af6 11824 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 146:22da6e220af6 11825 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 11826 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 146:22da6e220af6 11827
AnnaBridge 146:22da6e220af6 11828 /**
AnnaBridge 146:22da6e220af6 11829 * @brief EXTI4 configuration
AnnaBridge 146:22da6e220af6 11830 */
AnnaBridge 146:22da6e220af6 11831 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 146:22da6e220af6 11832 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 146:22da6e220af6 11833 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 146:22da6e220af6 11834 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 146:22da6e220af6 11835 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 146:22da6e220af6 11836 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 146:22da6e220af6 11837 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 146:22da6e220af6 11838 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 146:22da6e220af6 11839
AnnaBridge 146:22da6e220af6 11840 /**
AnnaBridge 146:22da6e220af6 11841 * @brief EXTI5 configuration
AnnaBridge 146:22da6e220af6 11842 */
AnnaBridge 146:22da6e220af6 11843 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 146:22da6e220af6 11844 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 146:22da6e220af6 11845 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 146:22da6e220af6 11846 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 146:22da6e220af6 11847 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 146:22da6e220af6 11848 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 146:22da6e220af6 11849 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 146:22da6e220af6 11850 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 146:22da6e220af6 11851
AnnaBridge 146:22da6e220af6 11852 /**
AnnaBridge 146:22da6e220af6 11853 * @brief EXTI6 configuration
AnnaBridge 146:22da6e220af6 11854 */
AnnaBridge 146:22da6e220af6 11855 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 146:22da6e220af6 11856 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 146:22da6e220af6 11857 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 146:22da6e220af6 11858 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 146:22da6e220af6 11859 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 146:22da6e220af6 11860 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 146:22da6e220af6 11861 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 146:22da6e220af6 11862 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 146:22da6e220af6 11863
AnnaBridge 146:22da6e220af6 11864 /**
AnnaBridge 146:22da6e220af6 11865 * @brief EXTI7 configuration
AnnaBridge 146:22da6e220af6 11866 */
AnnaBridge 146:22da6e220af6 11867 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 146:22da6e220af6 11868 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 146:22da6e220af6 11869 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 146:22da6e220af6 11870 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 146:22da6e220af6 11871 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 146:22da6e220af6 11872 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 146:22da6e220af6 11873 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 146:22da6e220af6 11874 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 146:22da6e220af6 11875
AnnaBridge 146:22da6e220af6 11876 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 146:22da6e220af6 11877 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 146:22da6e220af6 11878 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 11879 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 146:22da6e220af6 11880 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 146:22da6e220af6 11881 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 11882 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 146:22da6e220af6 11883 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 146:22da6e220af6 11884 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 11885 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 146:22da6e220af6 11886 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 146:22da6e220af6 11887 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 11888 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 146:22da6e220af6 11889
AnnaBridge 146:22da6e220af6 11890 /**
AnnaBridge 146:22da6e220af6 11891 * @brief EXTI8 configuration
AnnaBridge 146:22da6e220af6 11892 */
AnnaBridge 146:22da6e220af6 11893 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 146:22da6e220af6 11894 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 146:22da6e220af6 11895 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 146:22da6e220af6 11896 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 146:22da6e220af6 11897 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 146:22da6e220af6 11898 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 146:22da6e220af6 11899 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 146:22da6e220af6 11900 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 146:22da6e220af6 11901
AnnaBridge 146:22da6e220af6 11902 /**
AnnaBridge 146:22da6e220af6 11903 * @brief EXTI9 configuration
AnnaBridge 146:22da6e220af6 11904 */
AnnaBridge 146:22da6e220af6 11905 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 146:22da6e220af6 11906 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 146:22da6e220af6 11907 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 146:22da6e220af6 11908 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 146:22da6e220af6 11909 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 146:22da6e220af6 11910 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 146:22da6e220af6 11911 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 146:22da6e220af6 11912 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 146:22da6e220af6 11913
AnnaBridge 146:22da6e220af6 11914 /**
AnnaBridge 146:22da6e220af6 11915 * @brief EXTI10 configuration
AnnaBridge 146:22da6e220af6 11916 */
AnnaBridge 146:22da6e220af6 11917 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 146:22da6e220af6 11918 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 146:22da6e220af6 11919 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 146:22da6e220af6 11920 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 146:22da6e220af6 11921 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 146:22da6e220af6 11922 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 146:22da6e220af6 11923 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 146:22da6e220af6 11924 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 146:22da6e220af6 11925
AnnaBridge 146:22da6e220af6 11926 /**
AnnaBridge 146:22da6e220af6 11927 * @brief EXTI11 configuration
AnnaBridge 146:22da6e220af6 11928 */
AnnaBridge 146:22da6e220af6 11929 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 146:22da6e220af6 11930 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 146:22da6e220af6 11931 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 146:22da6e220af6 11932 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 146:22da6e220af6 11933 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 146:22da6e220af6 11934 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 146:22da6e220af6 11935 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 146:22da6e220af6 11936 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 146:22da6e220af6 11937
AnnaBridge 146:22da6e220af6 11938 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 146:22da6e220af6 11939 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 146:22da6e220af6 11940 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 11941 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 146:22da6e220af6 11942 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 146:22da6e220af6 11943 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 11944 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 146:22da6e220af6 11945 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 146:22da6e220af6 11946 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 11947 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 146:22da6e220af6 11948 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 146:22da6e220af6 11949 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 11950 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 146:22da6e220af6 11951
AnnaBridge 146:22da6e220af6 11952 /**
AnnaBridge 146:22da6e220af6 11953 * @brief EXTI12 configuration
AnnaBridge 146:22da6e220af6 11954 */
AnnaBridge 146:22da6e220af6 11955 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 146:22da6e220af6 11956 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 146:22da6e220af6 11957 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 146:22da6e220af6 11958 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 146:22da6e220af6 11959 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 146:22da6e220af6 11960 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 146:22da6e220af6 11961 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 146:22da6e220af6 11962 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 146:22da6e220af6 11963
AnnaBridge 146:22da6e220af6 11964 /**
AnnaBridge 146:22da6e220af6 11965 * @brief EXTI13 configuration
AnnaBridge 146:22da6e220af6 11966 */
AnnaBridge 146:22da6e220af6 11967 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 146:22da6e220af6 11968 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 146:22da6e220af6 11969 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 146:22da6e220af6 11970 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 146:22da6e220af6 11971 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 146:22da6e220af6 11972 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 146:22da6e220af6 11973 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 146:22da6e220af6 11974 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 146:22da6e220af6 11975
AnnaBridge 146:22da6e220af6 11976 /**
AnnaBridge 146:22da6e220af6 11977 * @brief EXTI14 configuration
AnnaBridge 146:22da6e220af6 11978 */
AnnaBridge 146:22da6e220af6 11979 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 146:22da6e220af6 11980 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 146:22da6e220af6 11981 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 146:22da6e220af6 11982 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 146:22da6e220af6 11983 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 146:22da6e220af6 11984 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 146:22da6e220af6 11985 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 146:22da6e220af6 11986 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 146:22da6e220af6 11987
AnnaBridge 146:22da6e220af6 11988 /**
AnnaBridge 146:22da6e220af6 11989 * @brief EXTI15 configuration
AnnaBridge 146:22da6e220af6 11990 */
AnnaBridge 146:22da6e220af6 11991 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 146:22da6e220af6 11992 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 146:22da6e220af6 11993 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 146:22da6e220af6 11994 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 146:22da6e220af6 11995 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 146:22da6e220af6 11996 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 146:22da6e220af6 11997 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 146:22da6e220af6 11998 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 146:22da6e220af6 11999
AnnaBridge 146:22da6e220af6 12000 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 146:22da6e220af6 12001 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 146:22da6e220af6 12002 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12003 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 146:22da6e220af6 12004 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 146:22da6e220af6 12005 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12006 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
AnnaBridge 146:22da6e220af6 12007 /****************** Bit definition for SYSCFG_CFGR register *****************/
AnnaBridge 146:22da6e220af6 12008 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
AnnaBridge 146:22da6e220af6 12009 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12010 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
AnnaBridge 146:22da6e220af6 12011 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
AnnaBridge 146:22da6e220af6 12012 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12013 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
AnnaBridge 146:22da6e220af6 12014
AnnaBridge 146:22da6e220af6 12015 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
AnnaBridge 146:22da6e220af6 12016 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
AnnaBridge 146:22da6e220af6 12017 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12018 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
AnnaBridge 146:22da6e220af6 12019 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
AnnaBridge 146:22da6e220af6 12020 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12021 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
AnnaBridge 146:22da6e220af6 12022 /****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
AnnaBridge 146:22da6e220af6 12023 #define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
AnnaBridge 146:22da6e220af6 12024 #define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1U << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12025 #define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk /*!<Bitstream clock source selection */
AnnaBridge 146:22da6e220af6 12026 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
AnnaBridge 146:22da6e220af6 12027 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12028 #define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk /*!<MCHDLY clock enable for DFSDM1 */
AnnaBridge 146:22da6e220af6 12029 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
AnnaBridge 146:22da6e220af6 12030 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12031 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM1 */
AnnaBridge 146:22da6e220af6 12032 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
AnnaBridge 146:22da6e220af6 12033 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12034 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM1 */
AnnaBridge 146:22da6e220af6 12035 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
AnnaBridge 146:22da6e220af6 12036 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12037 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */
AnnaBridge 146:22da6e220af6 12038 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
AnnaBridge 146:22da6e220af6 12039 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12040 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */
AnnaBridge 146:22da6e220af6 12041 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
AnnaBridge 146:22da6e220af6 12042 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12043 #define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk /*!<Source selection for DFSDM1 */
AnnaBridge 146:22da6e220af6 12044 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
AnnaBridge 146:22da6e220af6 12045 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12046 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk /*!<Source selection for 1_CKOUT */
AnnaBridge 146:22da6e220af6 12047 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
AnnaBridge 146:22da6e220af6 12048 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12049 #define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk /*!<MCHDLY clock enable for DFSDM2 */
AnnaBridge 146:22da6e220af6 12050 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
AnnaBridge 146:22da6e220af6 12051 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12052 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM2 */
AnnaBridge 146:22da6e220af6 12053 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
AnnaBridge 146:22da6e220af6 12054 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12055 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM2 */
AnnaBridge 146:22da6e220af6 12056 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
AnnaBridge 146:22da6e220af6 12057 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12058 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk /*!<Source selection for DatIn4 for DFSDM2 */
AnnaBridge 146:22da6e220af6 12059 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
AnnaBridge 146:22da6e220af6 12060 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12061 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk /*!<Source selection for DatIn6 for DFSDM2 */
AnnaBridge 146:22da6e220af6 12062 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
AnnaBridge 146:22da6e220af6 12063 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12064 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */
AnnaBridge 146:22da6e220af6 12065 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
AnnaBridge 146:22da6e220af6 12066 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12067 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */
AnnaBridge 146:22da6e220af6 12068 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
AnnaBridge 146:22da6e220af6 12069 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12070 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2 */
AnnaBridge 146:22da6e220af6 12071 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
AnnaBridge 146:22da6e220af6 12072 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 12073 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */
AnnaBridge 146:22da6e220af6 12074 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
AnnaBridge 146:22da6e220af6 12075 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 12076 #define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk /*!<Source selection for DFSDM2 */
AnnaBridge 146:22da6e220af6 12077 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
AnnaBridge 146:22da6e220af6 12078 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 12079 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk /*!<Source selection for 2_CKOUT */
AnnaBridge 146:22da6e220af6 12080
AnnaBridge 146:22da6e220af6 12081 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12082 /* */
AnnaBridge 146:22da6e220af6 12083 /* TIM */
AnnaBridge 146:22da6e220af6 12084 /* */
AnnaBridge 146:22da6e220af6 12085 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12086 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 146:22da6e220af6 12087 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 146:22da6e220af6 12088 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12089 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 146:22da6e220af6 12090 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 146:22da6e220af6 12091 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12092 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 146:22da6e220af6 12093 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 146:22da6e220af6 12094 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12095 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 146:22da6e220af6 12096 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 146:22da6e220af6 12097 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12098 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 146:22da6e220af6 12099 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 146:22da6e220af6 12100 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12101 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 146:22da6e220af6 12102
AnnaBridge 146:22da6e220af6 12103 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 146:22da6e220af6 12104 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 146:22da6e220af6 12105 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 146:22da6e220af6 12106 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12107 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12108
AnnaBridge 146:22da6e220af6 12109 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 146:22da6e220af6 12110 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12111 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 146:22da6e220af6 12112
AnnaBridge 146:22da6e220af6 12113 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 146:22da6e220af6 12114 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 12115 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 146:22da6e220af6 12116 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12117 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12118
AnnaBridge 146:22da6e220af6 12119 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 146:22da6e220af6 12120 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 146:22da6e220af6 12121 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12122 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 146:22da6e220af6 12123 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 146:22da6e220af6 12124 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12125 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 146:22da6e220af6 12126 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 146:22da6e220af6 12127 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12128 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 146:22da6e220af6 12129
AnnaBridge 146:22da6e220af6 12130 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 146:22da6e220af6 12131 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 12132 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 146:22da6e220af6 12133 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12134 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12135 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12136
AnnaBridge 146:22da6e220af6 12137 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 146:22da6e220af6 12138 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12139 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 146:22da6e220af6 12140 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 146:22da6e220af6 12141 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12142 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 146:22da6e220af6 12143 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 146:22da6e220af6 12144 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12145 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 146:22da6e220af6 12146 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 146:22da6e220af6 12147 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12148 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 146:22da6e220af6 12149 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 146:22da6e220af6 12150 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12151 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 146:22da6e220af6 12152 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 146:22da6e220af6 12153 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12154 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 146:22da6e220af6 12155 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 146:22da6e220af6 12156 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12157 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 146:22da6e220af6 12158 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 146:22da6e220af6 12159 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12160 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 146:22da6e220af6 12161
AnnaBridge 146:22da6e220af6 12162 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 146:22da6e220af6 12163 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 146:22da6e220af6 12164 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 12165 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 146:22da6e220af6 12166 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12167 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12168 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12169
AnnaBridge 146:22da6e220af6 12170 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 146:22da6e220af6 12171 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 12172 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 146:22da6e220af6 12173 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12174 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12175 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12176
AnnaBridge 146:22da6e220af6 12177 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 146:22da6e220af6 12178 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12179 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 146:22da6e220af6 12180
AnnaBridge 146:22da6e220af6 12181 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 146:22da6e220af6 12182 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 12183 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 146:22da6e220af6 12184 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12185 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12186 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 146:22da6e220af6 12187 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 12188
AnnaBridge 146:22da6e220af6 12189 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 146:22da6e220af6 12190 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 12191 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 146:22da6e220af6 12192 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12193 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12194
AnnaBridge 146:22da6e220af6 12195 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 146:22da6e220af6 12196 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12197 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 146:22da6e220af6 12198 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 146:22da6e220af6 12199 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12200 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 146:22da6e220af6 12201
AnnaBridge 146:22da6e220af6 12202 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 146:22da6e220af6 12203 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 146:22da6e220af6 12204 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12205 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 146:22da6e220af6 12206 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 146:22da6e220af6 12207 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12208 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 146:22da6e220af6 12209 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 146:22da6e220af6 12210 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12211 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 146:22da6e220af6 12212 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 146:22da6e220af6 12213 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12214 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 146:22da6e220af6 12215 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 146:22da6e220af6 12216 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12217 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 146:22da6e220af6 12218 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 146:22da6e220af6 12219 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12220 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 146:22da6e220af6 12221 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 146:22da6e220af6 12222 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12223 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 146:22da6e220af6 12224 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 146:22da6e220af6 12225 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12226 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 146:22da6e220af6 12227 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 146:22da6e220af6 12228 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12229 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 146:22da6e220af6 12230 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 146:22da6e220af6 12231 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12232 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 146:22da6e220af6 12233 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 146:22da6e220af6 12234 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12235 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 146:22da6e220af6 12236 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 146:22da6e220af6 12237 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12238 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 146:22da6e220af6 12239 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 146:22da6e220af6 12240 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12241 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 146:22da6e220af6 12242 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 146:22da6e220af6 12243 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12244 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 146:22da6e220af6 12245 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 146:22da6e220af6 12246 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12247 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 146:22da6e220af6 12248
AnnaBridge 146:22da6e220af6 12249 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 146:22da6e220af6 12250 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 146:22da6e220af6 12251 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12252 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 146:22da6e220af6 12253 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 146:22da6e220af6 12254 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12255 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 146:22da6e220af6 12256 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 146:22da6e220af6 12257 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12258 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 146:22da6e220af6 12259 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 146:22da6e220af6 12260 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12261 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 146:22da6e220af6 12262 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 146:22da6e220af6 12263 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12264 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 146:22da6e220af6 12265 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 146:22da6e220af6 12266 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12267 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 146:22da6e220af6 12268 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 146:22da6e220af6 12269 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12270 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 146:22da6e220af6 12271 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 146:22da6e220af6 12272 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12273 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 146:22da6e220af6 12274 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 146:22da6e220af6 12275 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12276 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 146:22da6e220af6 12277 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 146:22da6e220af6 12278 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12279 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 146:22da6e220af6 12280 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 146:22da6e220af6 12281 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12282 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 146:22da6e220af6 12283 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 146:22da6e220af6 12284 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12285 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 146:22da6e220af6 12286
AnnaBridge 146:22da6e220af6 12287 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 146:22da6e220af6 12288 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 146:22da6e220af6 12289 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12290 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 146:22da6e220af6 12291 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 146:22da6e220af6 12292 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12293 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 146:22da6e220af6 12294 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 146:22da6e220af6 12295 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12296 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 146:22da6e220af6 12297 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 146:22da6e220af6 12298 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12299 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 146:22da6e220af6 12300 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 146:22da6e220af6 12301 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12302 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 146:22da6e220af6 12303 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 146:22da6e220af6 12304 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12305 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 146:22da6e220af6 12306 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 146:22da6e220af6 12307 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12308 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 146:22da6e220af6 12309 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 146:22da6e220af6 12310 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12311 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 146:22da6e220af6 12312
AnnaBridge 146:22da6e220af6 12313 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 146:22da6e220af6 12314 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 146:22da6e220af6 12315 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 12316 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 146:22da6e220af6 12317 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12318 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12319
AnnaBridge 146:22da6e220af6 12320 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 146:22da6e220af6 12321 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12322 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 146:22da6e220af6 12323 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 146:22da6e220af6 12324 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12325 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 146:22da6e220af6 12326
AnnaBridge 146:22da6e220af6 12327 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 146:22da6e220af6 12328 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 12329 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 146:22da6e220af6 12330 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12331 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12332 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12333
AnnaBridge 146:22da6e220af6 12334 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 146:22da6e220af6 12335 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12336 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 146:22da6e220af6 12337
AnnaBridge 146:22da6e220af6 12338 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 146:22da6e220af6 12339 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 12340 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 146:22da6e220af6 12341 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12342 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12343
AnnaBridge 146:22da6e220af6 12344 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 146:22da6e220af6 12345 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12346 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 146:22da6e220af6 12347 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 146:22da6e220af6 12348 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12349 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 146:22da6e220af6 12350
AnnaBridge 146:22da6e220af6 12351 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 146:22da6e220af6 12352 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 12353 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 146:22da6e220af6 12354 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12355 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12356 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 146:22da6e220af6 12357
AnnaBridge 146:22da6e220af6 12358 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 146:22da6e220af6 12359 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12360 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 146:22da6e220af6 12361
AnnaBridge 146:22da6e220af6 12362 /*----------------------------------------------------------------------------*/
AnnaBridge 146:22da6e220af6 12363
AnnaBridge 146:22da6e220af6 12364 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 146:22da6e220af6 12365 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 12366 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 146:22da6e220af6 12367 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12368 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 12369
AnnaBridge 146:22da6e220af6 12370 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 146:22da6e220af6 12371 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 12372 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 146:22da6e220af6 12373 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12374 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12375 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12376 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 12377
AnnaBridge 146:22da6e220af6 12378 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 146:22da6e220af6 12379 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 12380 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 146:22da6e220af6 12381 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 146:22da6e220af6 12382 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 12383
AnnaBridge 146:22da6e220af6 12384 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 146:22da6e220af6 12385 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 12386 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 146:22da6e220af6 12387 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12388 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12389 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 146:22da6e220af6 12390 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 146:22da6e220af6 12391
AnnaBridge 146:22da6e220af6 12392 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 146:22da6e220af6 12393 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 146:22da6e220af6 12394 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 12395 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 146:22da6e220af6 12396 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12397 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12398
AnnaBridge 146:22da6e220af6 12399 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 146:22da6e220af6 12400 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12401 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 146:22da6e220af6 12402 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 146:22da6e220af6 12403 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12404 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 146:22da6e220af6 12405
AnnaBridge 146:22da6e220af6 12406 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 146:22da6e220af6 12407 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 12408 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 146:22da6e220af6 12409 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12410 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12411 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12412
AnnaBridge 146:22da6e220af6 12413 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 146:22da6e220af6 12414 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12415 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 146:22da6e220af6 12416
AnnaBridge 146:22da6e220af6 12417 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 146:22da6e220af6 12418 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 12419 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 146:22da6e220af6 12420 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12421 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12422
AnnaBridge 146:22da6e220af6 12423 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 146:22da6e220af6 12424 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12425 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 146:22da6e220af6 12426 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 146:22da6e220af6 12427 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12428 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 146:22da6e220af6 12429
AnnaBridge 146:22da6e220af6 12430 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 146:22da6e220af6 12431 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 146:22da6e220af6 12432 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 146:22da6e220af6 12433 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12434 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12435 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 146:22da6e220af6 12436
AnnaBridge 146:22da6e220af6 12437 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 146:22da6e220af6 12438 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12439 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 146:22da6e220af6 12440
AnnaBridge 146:22da6e220af6 12441 /*----------------------------------------------------------------------------*/
AnnaBridge 146:22da6e220af6 12442
AnnaBridge 146:22da6e220af6 12443 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 146:22da6e220af6 12444 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 146:22da6e220af6 12445 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 146:22da6e220af6 12446 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12447 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 12448
AnnaBridge 146:22da6e220af6 12449 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 146:22da6e220af6 12450 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 146:22da6e220af6 12451 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 146:22da6e220af6 12452 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12453 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12454 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12455 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 12456
AnnaBridge 146:22da6e220af6 12457 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 146:22da6e220af6 12458 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 12459 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 146:22da6e220af6 12460 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 146:22da6e220af6 12461 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 12462
AnnaBridge 146:22da6e220af6 12463 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 146:22da6e220af6 12464 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 146:22da6e220af6 12465 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 146:22da6e220af6 12466 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12467 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12468 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 146:22da6e220af6 12469 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 146:22da6e220af6 12470
AnnaBridge 146:22da6e220af6 12471 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 146:22da6e220af6 12472 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 146:22da6e220af6 12473 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12474 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 146:22da6e220af6 12475 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 146:22da6e220af6 12476 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12477 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 146:22da6e220af6 12478 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 146:22da6e220af6 12479 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12480 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 146:22da6e220af6 12481 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 146:22da6e220af6 12482 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12483 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 146:22da6e220af6 12484 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 146:22da6e220af6 12485 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12486 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 146:22da6e220af6 12487 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 146:22da6e220af6 12488 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12489 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 146:22da6e220af6 12490 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 146:22da6e220af6 12491 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12492 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 146:22da6e220af6 12493 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 146:22da6e220af6 12494 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12495 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 146:22da6e220af6 12496 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 146:22da6e220af6 12497 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12498 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 146:22da6e220af6 12499 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 146:22da6e220af6 12500 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12501 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 146:22da6e220af6 12502 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 146:22da6e220af6 12503 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12504 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 146:22da6e220af6 12505 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 146:22da6e220af6 12506 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12507 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 146:22da6e220af6 12508 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 146:22da6e220af6 12509 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12510 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 146:22da6e220af6 12511 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 146:22da6e220af6 12512 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12513 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 146:22da6e220af6 12514 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 146:22da6e220af6 12515 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12516 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 146:22da6e220af6 12517
AnnaBridge 146:22da6e220af6 12518 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 146:22da6e220af6 12519 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 146:22da6e220af6 12520 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 12521 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 146:22da6e220af6 12522
AnnaBridge 146:22da6e220af6 12523 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 146:22da6e220af6 12524 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 146:22da6e220af6 12525 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12526 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 146:22da6e220af6 12527
AnnaBridge 146:22da6e220af6 12528 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 146:22da6e220af6 12529 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 146:22da6e220af6 12530 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 12531 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 146:22da6e220af6 12532
AnnaBridge 146:22da6e220af6 12533 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 146:22da6e220af6 12534 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 146:22da6e220af6 12535 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 12536 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 146:22da6e220af6 12537
AnnaBridge 146:22da6e220af6 12538 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 146:22da6e220af6 12539 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 146:22da6e220af6 12540 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12541 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 146:22da6e220af6 12542
AnnaBridge 146:22da6e220af6 12543 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 146:22da6e220af6 12544 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 146:22da6e220af6 12545 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12546 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 146:22da6e220af6 12547
AnnaBridge 146:22da6e220af6 12548 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 146:22da6e220af6 12549 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 146:22da6e220af6 12550 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12551 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 146:22da6e220af6 12552
AnnaBridge 146:22da6e220af6 12553 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 146:22da6e220af6 12554 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 146:22da6e220af6 12555 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12556 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 146:22da6e220af6 12557
AnnaBridge 146:22da6e220af6 12558 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 146:22da6e220af6 12559 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 146:22da6e220af6 12560 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 12561 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 146:22da6e220af6 12562 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12563 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12564 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12565 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 12566 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12567 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 12568 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12569 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 12570
AnnaBridge 146:22da6e220af6 12571 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 146:22da6e220af6 12572 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 146:22da6e220af6 12573 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 146:22da6e220af6 12574 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12575 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12576
AnnaBridge 146:22da6e220af6 12577 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 146:22da6e220af6 12578 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12579 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 146:22da6e220af6 12580 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 146:22da6e220af6 12581 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12582 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 146:22da6e220af6 12583 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 146:22da6e220af6 12584 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12585 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 146:22da6e220af6 12586 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 146:22da6e220af6 12587 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12588 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 146:22da6e220af6 12589 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 146:22da6e220af6 12590 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12591 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 146:22da6e220af6 12592 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 146:22da6e220af6 12593 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12594 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 146:22da6e220af6 12595
AnnaBridge 146:22da6e220af6 12596 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 146:22da6e220af6 12597 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 146:22da6e220af6 12598 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 146:22da6e220af6 12599 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 146:22da6e220af6 12600 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12601 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12602 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12603 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 12604 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12605
AnnaBridge 146:22da6e220af6 12606 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 146:22da6e220af6 12607 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 146:22da6e220af6 12608 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 146:22da6e220af6 12609 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 12610 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 146:22da6e220af6 12611 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 146:22da6e220af6 12612 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 12613 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12614
AnnaBridge 146:22da6e220af6 12615 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 146:22da6e220af6 12616 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 146:22da6e220af6 12617 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12618 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 146:22da6e220af6 12619
AnnaBridge 146:22da6e220af6 12620 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 146:22da6e220af6 12621 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 146:22da6e220af6 12622 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 12623 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 146:22da6e220af6 12624 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12625 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12626
AnnaBridge 146:22da6e220af6 12627 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 146:22da6e220af6 12628 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 12629 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 146:22da6e220af6 12630 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 12631 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 12632 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 146:22da6e220af6 12633 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 12634 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 146:22da6e220af6 12635 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 146:22da6e220af6 12636 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
AnnaBridge 146:22da6e220af6 12637
AnnaBridge 146:22da6e220af6 12638 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12639 /* */
AnnaBridge 146:22da6e220af6 12640 /* Low Power Timer (LPTIM) */
AnnaBridge 146:22da6e220af6 12641 /* */
AnnaBridge 146:22da6e220af6 12642 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12643 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 146:22da6e220af6 12644 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 146:22da6e220af6 12645 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12646 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 146:22da6e220af6 12647 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 146:22da6e220af6 12648 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12649 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 146:22da6e220af6 12650 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 146:22da6e220af6 12651 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12652 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 146:22da6e220af6 12653 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 146:22da6e220af6 12654 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12655 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 146:22da6e220af6 12656 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 146:22da6e220af6 12657 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12658 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 146:22da6e220af6 12659 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 146:22da6e220af6 12660 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12661 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 146:22da6e220af6 12662 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 146:22da6e220af6 12663 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12664 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 146:22da6e220af6 12665
AnnaBridge 146:22da6e220af6 12666 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 146:22da6e220af6 12667 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 146:22da6e220af6 12668 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12669 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 146:22da6e220af6 12670 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 146:22da6e220af6 12671 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12672 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 146:22da6e220af6 12673 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 146:22da6e220af6 12674 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12675 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 146:22da6e220af6 12676 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 146:22da6e220af6 12677 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12678 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 146:22da6e220af6 12679 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 146:22da6e220af6 12680 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12681 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 146:22da6e220af6 12682 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 146:22da6e220af6 12683 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12684 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 146:22da6e220af6 12685 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 146:22da6e220af6 12686 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12687 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 146:22da6e220af6 12688
AnnaBridge 146:22da6e220af6 12689 /****************** Bit definition for LPTIM_IER register ********************/
AnnaBridge 146:22da6e220af6 12690 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 146:22da6e220af6 12691 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12692 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 146:22da6e220af6 12693 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 146:22da6e220af6 12694 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12695 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 146:22da6e220af6 12696 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 146:22da6e220af6 12697 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12698 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 146:22da6e220af6 12699 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 146:22da6e220af6 12700 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12701 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 146:22da6e220af6 12702 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 146:22da6e220af6 12703 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12704 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 146:22da6e220af6 12705 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 146:22da6e220af6 12706 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12707 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 146:22da6e220af6 12708 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 146:22da6e220af6 12709 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12710 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 146:22da6e220af6 12711
AnnaBridge 146:22da6e220af6 12712 /****************** Bit definition for LPTIM_CFGR register *******************/
AnnaBridge 146:22da6e220af6 12713 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 146:22da6e220af6 12714 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12715 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 146:22da6e220af6 12716
AnnaBridge 146:22da6e220af6 12717 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 146:22da6e220af6 12718 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 146:22da6e220af6 12719 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 146:22da6e220af6 12720 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12721 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12722
AnnaBridge 146:22da6e220af6 12723 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 146:22da6e220af6 12724 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 146:22da6e220af6 12725 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 146:22da6e220af6 12726 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12727 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12728
AnnaBridge 146:22da6e220af6 12729 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 146:22da6e220af6 12730 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 12731 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 146:22da6e220af6 12732 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12733 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12734
AnnaBridge 146:22da6e220af6 12735 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 146:22da6e220af6 12736 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 146:22da6e220af6 12737 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 146:22da6e220af6 12738 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12739 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12740 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12741
AnnaBridge 146:22da6e220af6 12742 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 146:22da6e220af6 12743 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 146:22da6e220af6 12744 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 146:22da6e220af6 12745 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12746 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12747 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12748
AnnaBridge 146:22da6e220af6 12749 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 146:22da6e220af6 12750 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 146:22da6e220af6 12751 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 146:22da6e220af6 12752 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 12753 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 12754
AnnaBridge 146:22da6e220af6 12755 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 146:22da6e220af6 12756 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 12757 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 146:22da6e220af6 12758 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 146:22da6e220af6 12759 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 12760 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 146:22da6e220af6 12761 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 146:22da6e220af6 12762 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 12763 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 146:22da6e220af6 12764 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 146:22da6e220af6 12765 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 12766 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 146:22da6e220af6 12767 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 146:22da6e220af6 12768 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 12769 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 146:22da6e220af6 12770 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 146:22da6e220af6 12771 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 12772 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 146:22da6e220af6 12773
AnnaBridge 146:22da6e220af6 12774 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 146:22da6e220af6 12775 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 146:22da6e220af6 12776 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12777 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 146:22da6e220af6 12778 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 146:22da6e220af6 12779 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12780 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 146:22da6e220af6 12781 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 146:22da6e220af6 12782 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12783 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 146:22da6e220af6 12784
AnnaBridge 146:22da6e220af6 12785 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 146:22da6e220af6 12786 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 146:22da6e220af6 12787 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12788 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 146:22da6e220af6 12789
AnnaBridge 146:22da6e220af6 12790 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 146:22da6e220af6 12791 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 146:22da6e220af6 12792 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12793 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 146:22da6e220af6 12794
AnnaBridge 146:22da6e220af6 12795 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 146:22da6e220af6 12796 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 146:22da6e220af6 12797 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 12798 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 146:22da6e220af6 12799
AnnaBridge 146:22da6e220af6 12800 /****************** Bit definition for LPTIM_OR register *******************/
AnnaBridge 146:22da6e220af6 12801 #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
AnnaBridge 146:22da6e220af6 12802 #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 12803 #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
AnnaBridge 146:22da6e220af6 12804 #define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12805 #define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12806 #define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
AnnaBridge 146:22da6e220af6 12807 #define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1U << LPTIM_OR_TIM1_ITR2_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12808 #define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk /*!< Bit 2 */
AnnaBridge 146:22da6e220af6 12809 #define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
AnnaBridge 146:22da6e220af6 12810 #define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM5_ITR1_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12811 #define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk /*!< Bit 3 */
AnnaBridge 146:22da6e220af6 12812 #define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
AnnaBridge 146:22da6e220af6 12813 #define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM9_ITR1_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12814 #define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk /*!< Bit 4 */
AnnaBridge 146:22da6e220af6 12815
AnnaBridge 146:22da6e220af6 12816 /* Legacy Defines */
AnnaBridge 146:22da6e220af6 12817 #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
AnnaBridge 146:22da6e220af6 12818 #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
AnnaBridge 146:22da6e220af6 12819 #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
AnnaBridge 146:22da6e220af6 12820
AnnaBridge 146:22da6e220af6 12821
AnnaBridge 146:22da6e220af6 12822 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12823 /* */
AnnaBridge 146:22da6e220af6 12824 /* Universal Synchronous Asynchronous Receiver Transmitter */
AnnaBridge 146:22da6e220af6 12825 /* */
AnnaBridge 146:22da6e220af6 12826 /******************************************************************************/
AnnaBridge 146:22da6e220af6 12827 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 146:22da6e220af6 12828 #define USART_SR_PE_Pos (0U)
AnnaBridge 146:22da6e220af6 12829 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12830 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 146:22da6e220af6 12831 #define USART_SR_FE_Pos (1U)
AnnaBridge 146:22da6e220af6 12832 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12833 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 146:22da6e220af6 12834 #define USART_SR_NE_Pos (2U)
AnnaBridge 146:22da6e220af6 12835 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12836 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 146:22da6e220af6 12837 #define USART_SR_ORE_Pos (3U)
AnnaBridge 146:22da6e220af6 12838 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12839 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 146:22da6e220af6 12840 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 146:22da6e220af6 12841 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12842 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 146:22da6e220af6 12843 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 146:22da6e220af6 12844 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12845 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 146:22da6e220af6 12846 #define USART_SR_TC_Pos (6U)
AnnaBridge 146:22da6e220af6 12847 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12848 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 146:22da6e220af6 12849 #define USART_SR_TXE_Pos (7U)
AnnaBridge 146:22da6e220af6 12850 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12851 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 146:22da6e220af6 12852 #define USART_SR_LBD_Pos (8U)
AnnaBridge 146:22da6e220af6 12853 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12854 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 146:22da6e220af6 12855 #define USART_SR_CTS_Pos (9U)
AnnaBridge 146:22da6e220af6 12856 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12857 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
AnnaBridge 146:22da6e220af6 12858
AnnaBridge 146:22da6e220af6 12859 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 146:22da6e220af6 12860 #define USART_DR_DR_Pos (0U)
AnnaBridge 146:22da6e220af6 12861 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 146:22da6e220af6 12862 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
AnnaBridge 146:22da6e220af6 12863
AnnaBridge 146:22da6e220af6 12864 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 146:22da6e220af6 12865 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 146:22da6e220af6 12866 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 12867 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 146:22da6e220af6 12868 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 146:22da6e220af6 12869 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 146:22da6e220af6 12870 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
AnnaBridge 146:22da6e220af6 12871
AnnaBridge 146:22da6e220af6 12872 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 146:22da6e220af6 12873 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 146:22da6e220af6 12874 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12875 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 146:22da6e220af6 12876 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 146:22da6e220af6 12877 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12878 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 146:22da6e220af6 12879 #define USART_CR1_RE_Pos (2U)
AnnaBridge 146:22da6e220af6 12880 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12881 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 146:22da6e220af6 12882 #define USART_CR1_TE_Pos (3U)
AnnaBridge 146:22da6e220af6 12883 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12884 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 146:22da6e220af6 12885 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 146:22da6e220af6 12886 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12887 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 146:22da6e220af6 12888 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 146:22da6e220af6 12889 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12890 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 146:22da6e220af6 12891 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 146:22da6e220af6 12892 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12893 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 146:22da6e220af6 12894 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 146:22da6e220af6 12895 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 163:e59c8e839560 12896 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
AnnaBridge 146:22da6e220af6 12897 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 146:22da6e220af6 12898 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12899 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 146:22da6e220af6 12900 #define USART_CR1_PS_Pos (9U)
AnnaBridge 146:22da6e220af6 12901 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12902 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 146:22da6e220af6 12903 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 146:22da6e220af6 12904 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12905 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 146:22da6e220af6 12906 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 146:22da6e220af6 12907 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12908 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 146:22da6e220af6 12909 #define USART_CR1_M_Pos (12U)
AnnaBridge 146:22da6e220af6 12910 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 12911 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 146:22da6e220af6 12912 #define USART_CR1_UE_Pos (13U)
AnnaBridge 146:22da6e220af6 12913 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 12914 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 146:22da6e220af6 12915 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 146:22da6e220af6 12916 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 12917 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
AnnaBridge 146:22da6e220af6 12918
AnnaBridge 146:22da6e220af6 12919 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 146:22da6e220af6 12920 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 146:22da6e220af6 12921 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 12922 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 146:22da6e220af6 12923 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 146:22da6e220af6 12924 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12925 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 146:22da6e220af6 12926 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 146:22da6e220af6 12927 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12928 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 146:22da6e220af6 12929 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 146:22da6e220af6 12930 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12931 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 146:22da6e220af6 12932 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 146:22da6e220af6 12933 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12934 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 146:22da6e220af6 12935 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 146:22da6e220af6 12936 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12937 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 146:22da6e220af6 12938 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 146:22da6e220af6 12939 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12940 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 146:22da6e220af6 12941
AnnaBridge 146:22da6e220af6 12942 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 146:22da6e220af6 12943 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 146:22da6e220af6 12944 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 146:22da6e220af6 12945 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 146:22da6e220af6 12946 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 146:22da6e220af6 12947
AnnaBridge 146:22da6e220af6 12948 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 146:22da6e220af6 12949 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 12950 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
AnnaBridge 146:22da6e220af6 12951
AnnaBridge 146:22da6e220af6 12952 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 146:22da6e220af6 12953 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 146:22da6e220af6 12954 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 12955 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 146:22da6e220af6 12956 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 146:22da6e220af6 12957 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 12958 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 146:22da6e220af6 12959 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 146:22da6e220af6 12960 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 12961 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 146:22da6e220af6 12962 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 146:22da6e220af6 12963 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 12964 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 146:22da6e220af6 12965 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 146:22da6e220af6 12966 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 12967 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 146:22da6e220af6 12968 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 146:22da6e220af6 12969 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 12970 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 146:22da6e220af6 12971 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 146:22da6e220af6 12972 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 12973 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 146:22da6e220af6 12974 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 146:22da6e220af6 12975 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 12976 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 146:22da6e220af6 12977 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 146:22da6e220af6 12978 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 12979 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 146:22da6e220af6 12980 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 146:22da6e220af6 12981 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 12982 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 146:22da6e220af6 12983 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 146:22da6e220af6 12984 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 12985 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 146:22da6e220af6 12986 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 146:22da6e220af6 12987 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 12988 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
AnnaBridge 146:22da6e220af6 12989
AnnaBridge 146:22da6e220af6 12990 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 146:22da6e220af6 12991 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 146:22da6e220af6 12992 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 146:22da6e220af6 12993 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 146:22da6e220af6 12994 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 12995 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 12996 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 12997 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 12998 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 12999 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 13000 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 13001 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 13002
AnnaBridge 146:22da6e220af6 13003 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 146:22da6e220af6 13004 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 146:22da6e220af6 13005 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
AnnaBridge 146:22da6e220af6 13006
AnnaBridge 146:22da6e220af6 13007 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13008 /* */
AnnaBridge 146:22da6e220af6 13009 /* Window WATCHDOG */
AnnaBridge 146:22da6e220af6 13010 /* */
AnnaBridge 146:22da6e220af6 13011 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13012 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 146:22da6e220af6 13013 #define WWDG_CR_T_Pos (0U)
AnnaBridge 146:22da6e220af6 13014 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 146:22da6e220af6 13015 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 146:22da6e220af6 13016 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 146:22da6e220af6 13017 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 146:22da6e220af6 13018 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 146:22da6e220af6 13019 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 146:22da6e220af6 13020 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 146:22da6e220af6 13021 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 146:22da6e220af6 13022 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 146:22da6e220af6 13023 /* Legacy defines */
AnnaBridge 146:22da6e220af6 13024 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 146:22da6e220af6 13025 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 146:22da6e220af6 13026 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 146:22da6e220af6 13027 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 146:22da6e220af6 13028 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 146:22da6e220af6 13029 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 146:22da6e220af6 13030 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 146:22da6e220af6 13031
AnnaBridge 146:22da6e220af6 13032 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 146:22da6e220af6 13033 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13034 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 146:22da6e220af6 13035
AnnaBridge 146:22da6e220af6 13036 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 146:22da6e220af6 13037 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 146:22da6e220af6 13038 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 146:22da6e220af6 13039 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 146:22da6e220af6 13040 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 146:22da6e220af6 13041 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 146:22da6e220af6 13042 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 146:22da6e220af6 13043 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 146:22da6e220af6 13044 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 146:22da6e220af6 13045 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 146:22da6e220af6 13046 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 146:22da6e220af6 13047 /* Legacy defines */
AnnaBridge 146:22da6e220af6 13048 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 146:22da6e220af6 13049 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 146:22da6e220af6 13050 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 146:22da6e220af6 13051 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 146:22da6e220af6 13052 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 146:22da6e220af6 13053 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 146:22da6e220af6 13054 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 146:22da6e220af6 13055
AnnaBridge 146:22da6e220af6 13056 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 146:22da6e220af6 13057 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 146:22da6e220af6 13058 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 146:22da6e220af6 13059 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 146:22da6e220af6 13060 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 146:22da6e220af6 13061 /* Legacy defines */
AnnaBridge 146:22da6e220af6 13062 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 146:22da6e220af6 13063 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 146:22da6e220af6 13064
AnnaBridge 146:22da6e220af6 13065 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 146:22da6e220af6 13066 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13067 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 146:22da6e220af6 13068
AnnaBridge 146:22da6e220af6 13069 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 146:22da6e220af6 13070 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 146:22da6e220af6 13071 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13072 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 146:22da6e220af6 13073
AnnaBridge 146:22da6e220af6 13074
AnnaBridge 146:22da6e220af6 13075 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13076 /* */
AnnaBridge 146:22da6e220af6 13077 /* DBG */
AnnaBridge 146:22da6e220af6 13078 /* */
AnnaBridge 146:22da6e220af6 13079 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13080 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 146:22da6e220af6 13081 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 146:22da6e220af6 13082 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 13083 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 146:22da6e220af6 13084 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 146:22da6e220af6 13085 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13086 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 146:22da6e220af6 13087
AnnaBridge 146:22da6e220af6 13088 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 146:22da6e220af6 13089 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 146:22da6e220af6 13090 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13091 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 146:22da6e220af6 13092 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 146:22da6e220af6 13093 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13094 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 146:22da6e220af6 13095 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 146:22da6e220af6 13096 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13097 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 146:22da6e220af6 13098 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 146:22da6e220af6 13099 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13100 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 146:22da6e220af6 13101
AnnaBridge 146:22da6e220af6 13102 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 146:22da6e220af6 13103 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 146:22da6e220af6 13104 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 146:22da6e220af6 13105 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13106 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13107
AnnaBridge 146:22da6e220af6 13108 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 146:22da6e220af6 13109 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 146:22da6e220af6 13110 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13111 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 146:22da6e220af6 13112 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 146:22da6e220af6 13113 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13114 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 146:22da6e220af6 13115 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 146:22da6e220af6 13116 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13117 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 146:22da6e220af6 13118 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 146:22da6e220af6 13119 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13120 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 146:22da6e220af6 13121 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 146:22da6e220af6 13122 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13123 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 146:22da6e220af6 13124 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 146:22da6e220af6 13125 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13126 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 146:22da6e220af6 13127 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
AnnaBridge 146:22da6e220af6 13128 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13129 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
AnnaBridge 146:22da6e220af6 13130 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
AnnaBridge 146:22da6e220af6 13131 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13132 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
AnnaBridge 146:22da6e220af6 13133 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 146:22da6e220af6 13134 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13135 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
AnnaBridge 146:22da6e220af6 13136 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
AnnaBridge 146:22da6e220af6 13137 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13138 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
AnnaBridge 146:22da6e220af6 13139 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 146:22da6e220af6 13140 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13141 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 146:22da6e220af6 13142 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 146:22da6e220af6 13143 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13144 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 146:22da6e220af6 13145 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 146:22da6e220af6 13146 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13147 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 146:22da6e220af6 13148 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 146:22da6e220af6 13149 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13150 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 146:22da6e220af6 13151 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 146:22da6e220af6 13152 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13153 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 146:22da6e220af6 13154 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 146:22da6e220af6 13155 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13156 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 146:22da6e220af6 13157 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
AnnaBridge 146:22da6e220af6 13158 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13159 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
AnnaBridge 146:22da6e220af6 13160 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 146:22da6e220af6 13161 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13162 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 146:22da6e220af6 13163 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 146:22da6e220af6 13164 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 13165 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
AnnaBridge 146:22da6e220af6 13166 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
AnnaBridge 146:22da6e220af6 13167 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13168 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
AnnaBridge 146:22da6e220af6 13169
AnnaBridge 146:22da6e220af6 13170 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 146:22da6e220af6 13171 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 146:22da6e220af6 13172 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13173 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 146:22da6e220af6 13174 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
AnnaBridge 146:22da6e220af6 13175 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13176 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
AnnaBridge 146:22da6e220af6 13177 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 146:22da6e220af6 13178 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13179 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 146:22da6e220af6 13180 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 146:22da6e220af6 13181 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13182 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 146:22da6e220af6 13183 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 146:22da6e220af6 13184 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13185 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 146:22da6e220af6 13186
AnnaBridge 146:22da6e220af6 13187 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13188 /* */
AnnaBridge 146:22da6e220af6 13189 /* USB_OTG */
AnnaBridge 146:22da6e220af6 13190 /* */
AnnaBridge 146:22da6e220af6 13191 /******************************************************************************/
AnnaBridge 146:22da6e220af6 13192 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 146:22da6e220af6 13193 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 146:22da6e220af6 13194 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13195 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 146:22da6e220af6 13196 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 146:22da6e220af6 13197 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13198 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 146:22da6e220af6 13199 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
AnnaBridge 146:22da6e220af6 13200 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13201 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
AnnaBridge 146:22da6e220af6 13202 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
AnnaBridge 146:22da6e220af6 13203 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13204 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
AnnaBridge 146:22da6e220af6 13205 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
AnnaBridge 146:22da6e220af6 13206 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13207 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
AnnaBridge 146:22da6e220af6 13208 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
AnnaBridge 146:22da6e220af6 13209 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13210 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
AnnaBridge 146:22da6e220af6 13211 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
AnnaBridge 146:22da6e220af6 13212 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13213 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
AnnaBridge 146:22da6e220af6 13214 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
AnnaBridge 146:22da6e220af6 13215 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13216 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
AnnaBridge 146:22da6e220af6 13217 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 146:22da6e220af6 13218 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13219 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 146:22da6e220af6 13220 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 146:22da6e220af6 13221 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13222 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 146:22da6e220af6 13223 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 146:22da6e220af6 13224 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13225 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 146:22da6e220af6 13226 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 146:22da6e220af6 13227 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13228 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 146:22da6e220af6 13229 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
AnnaBridge 146:22da6e220af6 13230 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13231 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
AnnaBridge 146:22da6e220af6 13232 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 146:22da6e220af6 13233 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13234 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 146:22da6e220af6 13235 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 146:22da6e220af6 13236 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13237 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 146:22da6e220af6 13238 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 146:22da6e220af6 13239 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13240 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 146:22da6e220af6 13241 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
AnnaBridge 146:22da6e220af6 13242 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13243 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
AnnaBridge 146:22da6e220af6 13244 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
AnnaBridge 146:22da6e220af6 13245 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13246 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
AnnaBridge 146:22da6e220af6 13247
AnnaBridge 146:22da6e220af6 13248 /******************** Bit definition forUSB_OTG_HCFG register ********************/
AnnaBridge 146:22da6e220af6 13249
AnnaBridge 146:22da6e220af6 13250 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 146:22da6e220af6 13251 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 13252 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 146:22da6e220af6 13253 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13254 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13255 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 146:22da6e220af6 13256 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13257 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 146:22da6e220af6 13258
AnnaBridge 146:22da6e220af6 13259 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 146:22da6e220af6 13260
AnnaBridge 146:22da6e220af6 13261 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 146:22da6e220af6 13262 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 146:22da6e220af6 13263 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 146:22da6e220af6 13264 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13265 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13266 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 146:22da6e220af6 13267 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13268 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 146:22da6e220af6 13269
AnnaBridge 146:22da6e220af6 13270 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 146:22da6e220af6 13271 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 146:22da6e220af6 13272 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 146:22da6e220af6 13273 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13274 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13275 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13276 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13277 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13278 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13279 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13280
AnnaBridge 146:22da6e220af6 13281 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 146:22da6e220af6 13282 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 146:22da6e220af6 13283 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 146:22da6e220af6 13284 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13285 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13286
AnnaBridge 146:22da6e220af6 13287 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 146:22da6e220af6 13288 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 146:22da6e220af6 13289 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 146:22da6e220af6 13290 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13291 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13292
AnnaBridge 146:22da6e220af6 13293 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 146:22da6e220af6 13294 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 146:22da6e220af6 13295 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13296 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 146:22da6e220af6 13297 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 146:22da6e220af6 13298 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13299 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 146:22da6e220af6 13300 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 146:22da6e220af6 13301 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13302 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 146:22da6e220af6 13303
AnnaBridge 146:22da6e220af6 13304 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 146:22da6e220af6 13305 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 146:22da6e220af6 13306 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13307 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 146:22da6e220af6 13308 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 146:22da6e220af6 13309 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13310 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 146:22da6e220af6 13311 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 146:22da6e220af6 13312 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13313 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 146:22da6e220af6 13314 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 146:22da6e220af6 13315 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13316 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 146:22da6e220af6 13317 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 146:22da6e220af6 13318 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13319 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 146:22da6e220af6 13320 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 146:22da6e220af6 13321 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13322 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 146:22da6e220af6 13323 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
AnnaBridge 146:22da6e220af6 13324 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13325 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
AnnaBridge 146:22da6e220af6 13326
AnnaBridge 146:22da6e220af6 13327 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 146:22da6e220af6 13328 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 146:22da6e220af6 13329 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13330 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 146:22da6e220af6 13331 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 146:22da6e220af6 13332 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13333 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 146:22da6e220af6 13334 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 146:22da6e220af6 13335 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13336 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 146:22da6e220af6 13337 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 146:22da6e220af6 13338 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13339 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 146:22da6e220af6 13340
AnnaBridge 146:22da6e220af6 13341 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 146:22da6e220af6 13342 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 146:22da6e220af6 13343 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 146:22da6e220af6 13344 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13345 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13346 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13347 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 146:22da6e220af6 13348 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13349 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 146:22da6e220af6 13350 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 146:22da6e220af6 13351 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13352 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 146:22da6e220af6 13353 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 146:22da6e220af6 13354 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13355 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 146:22da6e220af6 13356 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 146:22da6e220af6 13357 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13358 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 146:22da6e220af6 13359 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 146:22da6e220af6 13360 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13361 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 146:22da6e220af6 13362
AnnaBridge 146:22da6e220af6 13363 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 146:22da6e220af6 13364 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 146:22da6e220af6 13365 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13366 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 146:22da6e220af6 13367
AnnaBridge 146:22da6e220af6 13368 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 146:22da6e220af6 13369 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 146:22da6e220af6 13370 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13371 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 146:22da6e220af6 13372 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 146:22da6e220af6 13373 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13374 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 146:22da6e220af6 13375
AnnaBridge 146:22da6e220af6 13376 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 146:22da6e220af6 13377 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 146:22da6e220af6 13378 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13379 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 146:22da6e220af6 13380
AnnaBridge 146:22da6e220af6 13381 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 146:22da6e220af6 13382 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 146:22da6e220af6 13383 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 146:22da6e220af6 13384 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13385 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13386 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 146:22da6e220af6 13387 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13388 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 146:22da6e220af6 13389 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 146:22da6e220af6 13390 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 146:22da6e220af6 13391 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 146:22da6e220af6 13392
AnnaBridge 146:22da6e220af6 13393 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 146:22da6e220af6 13394 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 146:22da6e220af6 13395 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13396 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 146:22da6e220af6 13397 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 146:22da6e220af6 13398 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 146:22da6e220af6 13399 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 146:22da6e220af6 13400 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 146:22da6e220af6 13401 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 146:22da6e220af6 13402 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 146:22da6e220af6 13403 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 146:22da6e220af6 13404 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 146:22da6e220af6 13405 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 146:22da6e220af6 13406 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13407 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 146:22da6e220af6 13408 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 146:22da6e220af6 13409 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13410 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 146:22da6e220af6 13411 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 146:22da6e220af6 13412 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13413 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 146:22da6e220af6 13414
AnnaBridge 146:22da6e220af6 13415 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 146:22da6e220af6 13416
AnnaBridge 146:22da6e220af6 13417 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 146:22da6e220af6 13418 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 146:22da6e220af6 13419 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 146:22da6e220af6 13420 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13421 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13422 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13423 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 146:22da6e220af6 13424 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13425 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 146:22da6e220af6 13426 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 146:22da6e220af6 13427 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13428 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 146:22da6e220af6 13429 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 146:22da6e220af6 13430 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13431 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 146:22da6e220af6 13432 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 146:22da6e220af6 13433 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 146:22da6e220af6 13434 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 146:22da6e220af6 13435 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13436 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13437 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13438 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 13439 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 146:22da6e220af6 13440 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 13441 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 146:22da6e220af6 13442 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 146:22da6e220af6 13443 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13444 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 146:22da6e220af6 13445 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 146:22da6e220af6 13446 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13447 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 146:22da6e220af6 13448 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 146:22da6e220af6 13449 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13450 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 146:22da6e220af6 13451 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 146:22da6e220af6 13452 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13453 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 146:22da6e220af6 13454 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 146:22da6e220af6 13455 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13456 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 146:22da6e220af6 13457 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 146:22da6e220af6 13458 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13459 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 146:22da6e220af6 13460 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 146:22da6e220af6 13461 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13462 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 146:22da6e220af6 13463 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 146:22da6e220af6 13464 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13465 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 146:22da6e220af6 13466 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 146:22da6e220af6 13467 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13468 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 146:22da6e220af6 13469 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 146:22da6e220af6 13470 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 13471 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 146:22da6e220af6 13472 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 146:22da6e220af6 13473 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13474 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 146:22da6e220af6 13475 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 146:22da6e220af6 13476 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 13477 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 146:22da6e220af6 13478
AnnaBridge 146:22da6e220af6 13479 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 146:22da6e220af6 13480 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 146:22da6e220af6 13481 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13482 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 146:22da6e220af6 13483 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 146:22da6e220af6 13484 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13485 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 146:22da6e220af6 13486 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 146:22da6e220af6 13487 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13488 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 146:22da6e220af6 13489 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 146:22da6e220af6 13490 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13491 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 146:22da6e220af6 13492 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 146:22da6e220af6 13493 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13494 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 146:22da6e220af6 13495
AnnaBridge 146:22da6e220af6 13496
AnnaBridge 146:22da6e220af6 13497 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 146:22da6e220af6 13498 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 146:22da6e220af6 13499 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 146:22da6e220af6 13500 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13501 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13502 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13503 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13504 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13505 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 146:22da6e220af6 13506 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13507 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 146:22da6e220af6 13508 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 146:22da6e220af6 13509 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 13510 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 146:22da6e220af6 13511
AnnaBridge 146:22da6e220af6 13512 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 146:22da6e220af6 13513 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 146:22da6e220af6 13514 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13515 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 146:22da6e220af6 13516 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 146:22da6e220af6 13517 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13518 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 146:22da6e220af6 13519 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 146:22da6e220af6 13520 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13521 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 146:22da6e220af6 13522 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 146:22da6e220af6 13523 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13524 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 146:22da6e220af6 13525 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 146:22da6e220af6 13526 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13527 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 146:22da6e220af6 13528 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 146:22da6e220af6 13529 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13530 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 146:22da6e220af6 13531 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 146:22da6e220af6 13532 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13533 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 146:22da6e220af6 13534 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 146:22da6e220af6 13535 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13536 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 146:22da6e220af6 13537
AnnaBridge 146:22da6e220af6 13538 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 146:22da6e220af6 13539 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 146:22da6e220af6 13540 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13541 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 146:22da6e220af6 13542 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 146:22da6e220af6 13543 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 13544 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 146:22da6e220af6 13545 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13546 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13547 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13548 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13549 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13550 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13551 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13552 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13553
AnnaBridge 146:22da6e220af6 13554 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 146:22da6e220af6 13555 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 146:22da6e220af6 13556 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 146:22da6e220af6 13557 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13558 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13559 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 13560 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13561 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 13562 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 13563 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13564 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 13565
AnnaBridge 146:22da6e220af6 13566 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 146:22da6e220af6 13567 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 146:22da6e220af6 13568 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13569 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 146:22da6e220af6 13570
AnnaBridge 146:22da6e220af6 13571 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 146:22da6e220af6 13572 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 146:22da6e220af6 13573 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13574 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 146:22da6e220af6 13575 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 146:22da6e220af6 13576 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13577 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 146:22da6e220af6 13578 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 146:22da6e220af6 13579 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13580 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 146:22da6e220af6 13581 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 146:22da6e220af6 13582 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13583 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 146:22da6e220af6 13584 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
AnnaBridge 146:22da6e220af6 13585 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13586 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
AnnaBridge 146:22da6e220af6 13587 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 146:22da6e220af6 13588 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13589 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 146:22da6e220af6 13590 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 146:22da6e220af6 13591 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13592 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 146:22da6e220af6 13593 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 146:22da6e220af6 13594 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13595 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 146:22da6e220af6 13596
AnnaBridge 146:22da6e220af6 13597 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 146:22da6e220af6 13598 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 146:22da6e220af6 13599 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13600 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 146:22da6e220af6 13601 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 146:22da6e220af6 13602 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13603 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 146:22da6e220af6 13604 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 146:22da6e220af6 13605 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13606 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 146:22da6e220af6 13607 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 146:22da6e220af6 13608 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13609 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 146:22da6e220af6 13610 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 146:22da6e220af6 13611 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13612 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 146:22da6e220af6 13613 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 146:22da6e220af6 13614 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13615 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 146:22da6e220af6 13616 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 146:22da6e220af6 13617 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13618 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 146:22da6e220af6 13619 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 146:22da6e220af6 13620 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13621 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 146:22da6e220af6 13622 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 146:22da6e220af6 13623 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13624 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 146:22da6e220af6 13625 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 146:22da6e220af6 13626 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13627 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 146:22da6e220af6 13628 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 146:22da6e220af6 13629 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13630 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 146:22da6e220af6 13631 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 146:22da6e220af6 13632 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 13633 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 146:22da6e220af6 13634 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 146:22da6e220af6 13635 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 13636 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 146:22da6e220af6 13637 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 146:22da6e220af6 13638 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 13639 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 146:22da6e220af6 13640 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 146:22da6e220af6 13641 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13642 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 146:22da6e220af6 13643 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 146:22da6e220af6 13644 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13645 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 146:22da6e220af6 13646 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 146:22da6e220af6 13647 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13648 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 146:22da6e220af6 13649 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 146:22da6e220af6 13650 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13651 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 146:22da6e220af6 13652 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 146:22da6e220af6 13653 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13654 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 146:22da6e220af6 13655 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
AnnaBridge 146:22da6e220af6 13656 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13657 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
AnnaBridge 146:22da6e220af6 13658 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 146:22da6e220af6 13659 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13660 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 146:22da6e220af6 13661 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 146:22da6e220af6 13662 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13663 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 146:22da6e220af6 13664 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 146:22da6e220af6 13665 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 13666 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 146:22da6e220af6 13667 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
AnnaBridge 146:22da6e220af6 13668 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13669 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
AnnaBridge 146:22da6e220af6 13670 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 146:22da6e220af6 13671 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 13672 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 146:22da6e220af6 13673 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 146:22da6e220af6 13674 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 13675 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 146:22da6e220af6 13676 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 146:22da6e220af6 13677 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13678 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 146:22da6e220af6 13679 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 146:22da6e220af6 13680 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 13681 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 146:22da6e220af6 13682
AnnaBridge 146:22da6e220af6 13683 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 146:22da6e220af6 13684 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 146:22da6e220af6 13685 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13686 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 146:22da6e220af6 13687 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 146:22da6e220af6 13688 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13689 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 146:22da6e220af6 13690 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 146:22da6e220af6 13691 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13692 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 146:22da6e220af6 13693 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 146:22da6e220af6 13694 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13695 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 146:22da6e220af6 13696 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 146:22da6e220af6 13697 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13698 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 146:22da6e220af6 13699 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 146:22da6e220af6 13700 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13701 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 146:22da6e220af6 13702 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 146:22da6e220af6 13703 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13704 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 146:22da6e220af6 13705 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 146:22da6e220af6 13706 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13707 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 146:22da6e220af6 13708 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 146:22da6e220af6 13709 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 13710 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 146:22da6e220af6 13711 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 146:22da6e220af6 13712 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13713 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 146:22da6e220af6 13714 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 146:22da6e220af6 13715 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 13716 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 146:22da6e220af6 13717 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 146:22da6e220af6 13718 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 13719 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 146:22da6e220af6 13720 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 146:22da6e220af6 13721 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 13722 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 146:22da6e220af6 13723 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 146:22da6e220af6 13724 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13725 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 146:22da6e220af6 13726 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 146:22da6e220af6 13727 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13728 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 146:22da6e220af6 13729 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 146:22da6e220af6 13730 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13731 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 146:22da6e220af6 13732 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 146:22da6e220af6 13733 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13734 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 146:22da6e220af6 13735 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 146:22da6e220af6 13736 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13737 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 146:22da6e220af6 13738 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 146:22da6e220af6 13739 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13740 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 146:22da6e220af6 13741 #define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
AnnaBridge 146:22da6e220af6 13742 #define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13743 #define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
AnnaBridge 146:22da6e220af6 13744 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 146:22da6e220af6 13745 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13746 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 146:22da6e220af6 13747 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 146:22da6e220af6 13748 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13749 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 146:22da6e220af6 13750 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 146:22da6e220af6 13751 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 13752 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 146:22da6e220af6 13753 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
AnnaBridge 146:22da6e220af6 13754 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13755 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
AnnaBridge 146:22da6e220af6 13756 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 146:22da6e220af6 13757 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 13758 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 146:22da6e220af6 13759 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 146:22da6e220af6 13760 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 13761 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 146:22da6e220af6 13762 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 146:22da6e220af6 13763 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13764 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 146:22da6e220af6 13765 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 146:22da6e220af6 13766 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 13767 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 146:22da6e220af6 13768
AnnaBridge 146:22da6e220af6 13769 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 146:22da6e220af6 13770 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 146:22da6e220af6 13771 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13772 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 146:22da6e220af6 13773 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 146:22da6e220af6 13774 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13775 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 146:22da6e220af6 13776
AnnaBridge 146:22da6e220af6 13777 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 146:22da6e220af6 13778 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 146:22da6e220af6 13779 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13780 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 146:22da6e220af6 13781
AnnaBridge 146:22da6e220af6 13782 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 146:22da6e220af6 13783 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 146:22da6e220af6 13784 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 146:22da6e220af6 13785 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13786 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 146:22da6e220af6 13787 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 146:22da6e220af6 13788 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13789 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 146:22da6e220af6 13790 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 146:22da6e220af6 13791 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13792 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 146:22da6e220af6 13793 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 146:22da6e220af6 13794 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13795
AnnaBridge 146:22da6e220af6 13796 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 146:22da6e220af6 13797 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 146:22da6e220af6 13798 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13799 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13800 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 146:22da6e220af6 13801 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13802 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 146:22da6e220af6 13803
AnnaBridge 146:22da6e220af6 13804 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 146:22da6e220af6 13805 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 146:22da6e220af6 13806 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13807 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 146:22da6e220af6 13808
AnnaBridge 146:22da6e220af6 13809 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 146:22da6e220af6 13810 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 146:22da6e220af6 13811 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13812 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 146:22da6e220af6 13813
AnnaBridge 146:22da6e220af6 13814 /******************** Bit definition for OTG register ********************/
AnnaBridge 146:22da6e220af6 13815 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 146:22da6e220af6 13816 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13817 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 146:22da6e220af6 13818 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 146:22da6e220af6 13819 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13820 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 146:22da6e220af6 13821 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 146:22da6e220af6 13822 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13823 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 146:22da6e220af6 13824 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 146:22da6e220af6 13825 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 13826 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 146:22da6e220af6 13827
AnnaBridge 146:22da6e220af6 13828 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 146:22da6e220af6 13829 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 146:22da6e220af6 13830 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 146:22da6e220af6 13831 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 146:22da6e220af6 13832
AnnaBridge 146:22da6e220af6 13833 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 146:22da6e220af6 13834 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 146:22da6e220af6 13835 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13836 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 146:22da6e220af6 13837
AnnaBridge 146:22da6e220af6 13838 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 146:22da6e220af6 13839 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 146:22da6e220af6 13840 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 146:22da6e220af6 13841 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13842 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13843 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13844 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13845 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13846 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13847 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13848 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13849
AnnaBridge 146:22da6e220af6 13850 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 146:22da6e220af6 13851 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 146:22da6e220af6 13852 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 146:22da6e220af6 13853 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13854 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13855 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 13856 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13857 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 13858 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 13859 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 13860
AnnaBridge 146:22da6e220af6 13861 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 146:22da6e220af6 13862 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 146:22da6e220af6 13863 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13864 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 146:22da6e220af6 13865 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 146:22da6e220af6 13866 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13867 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 146:22da6e220af6 13868
AnnaBridge 146:22da6e220af6 13869 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 146:22da6e220af6 13870 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 146:22da6e220af6 13871 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 146:22da6e220af6 13872 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13873 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13874 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 13875 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 13876 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13877 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13878 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 13879 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 13880 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 13881 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 146:22da6e220af6 13882 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13883 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 146:22da6e220af6 13884
AnnaBridge 146:22da6e220af6 13885 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 146:22da6e220af6 13886 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 146:22da6e220af6 13887 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 146:22da6e220af6 13888 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13889 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13890 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13891 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13892 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13893 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 13894 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 13895 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13896 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 13897 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 146:22da6e220af6 13898 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 13899 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 146:22da6e220af6 13900
AnnaBridge 146:22da6e220af6 13901 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 146:22da6e220af6 13902 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 146:22da6e220af6 13903 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 13904 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 146:22da6e220af6 13905
AnnaBridge 146:22da6e220af6 13906 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 146:22da6e220af6 13907 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 146:22da6e220af6 13908 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13909 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 146:22da6e220af6 13910 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 146:22da6e220af6 13911 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13912 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 146:22da6e220af6 13913
AnnaBridge 146:22da6e220af6 13914 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 146:22da6e220af6 13915 #define USB_OTG_GCCFG_DCDET_Pos (0U)
AnnaBridge 146:22da6e220af6 13916 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13917 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
AnnaBridge 146:22da6e220af6 13918 #define USB_OTG_GCCFG_PDET_Pos (1U)
AnnaBridge 146:22da6e220af6 13919 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13920 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
AnnaBridge 146:22da6e220af6 13921 #define USB_OTG_GCCFG_SDET_Pos (2U)
AnnaBridge 146:22da6e220af6 13922 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 13923 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
AnnaBridge 146:22da6e220af6 13924 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
AnnaBridge 146:22da6e220af6 13925 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 13926 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
AnnaBridge 146:22da6e220af6 13927 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 146:22da6e220af6 13928 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13929 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 146:22da6e220af6 13930 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
AnnaBridge 146:22da6e220af6 13931 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13932 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
AnnaBridge 146:22da6e220af6 13933 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
AnnaBridge 146:22da6e220af6 13934 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 13935 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
AnnaBridge 146:22da6e220af6 13936 #define USB_OTG_GCCFG_PDEN_Pos (19U)
AnnaBridge 146:22da6e220af6 13937 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 13938 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
AnnaBridge 146:22da6e220af6 13939 #define USB_OTG_GCCFG_SDEN_Pos (20U)
AnnaBridge 146:22da6e220af6 13940 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 13941 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
AnnaBridge 146:22da6e220af6 13942 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
AnnaBridge 146:22da6e220af6 13943 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 13944 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
AnnaBridge 146:22da6e220af6 13945
AnnaBridge 146:22da6e220af6 13946 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 146:22da6e220af6 13947 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 146:22da6e220af6 13948 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13949 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 146:22da6e220af6 13950 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 146:22da6e220af6 13951 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 13952 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 146:22da6e220af6 13953
AnnaBridge 146:22da6e220af6 13954 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 146:22da6e220af6 13955 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 146:22da6e220af6 13956 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 13957 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 146:22da6e220af6 13958
AnnaBridge 146:22da6e220af6 13959 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
AnnaBridge 146:22da6e220af6 13960 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
AnnaBridge 146:22da6e220af6 13961 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 13962 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
AnnaBridge 146:22da6e220af6 13963 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
AnnaBridge 146:22da6e220af6 13964 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 13965 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
AnnaBridge 146:22da6e220af6 13966 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
AnnaBridge 146:22da6e220af6 13967 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
AnnaBridge 146:22da6e220af6 13968 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 146:22da6e220af6 13969 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
AnnaBridge 146:22da6e220af6 13970 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 13971 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 146:22da6e220af6 13972 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
AnnaBridge 146:22da6e220af6 13973 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 13974 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
AnnaBridge 146:22da6e220af6 13975 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
AnnaBridge 146:22da6e220af6 13976 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
AnnaBridge 146:22da6e220af6 13977 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
AnnaBridge 146:22da6e220af6 13978 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
AnnaBridge 146:22da6e220af6 13979 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 13980 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
AnnaBridge 146:22da6e220af6 13981 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
AnnaBridge 146:22da6e220af6 13982 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
AnnaBridge 146:22da6e220af6 13983 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
AnnaBridge 146:22da6e220af6 13984 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
AnnaBridge 146:22da6e220af6 13985 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 13986 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
AnnaBridge 146:22da6e220af6 13987 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
AnnaBridge 146:22da6e220af6 13988 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 13989 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
AnnaBridge 146:22da6e220af6 13990 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
AnnaBridge 146:22da6e220af6 13991 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
AnnaBridge 146:22da6e220af6 13992 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
AnnaBridge 146:22da6e220af6 13993 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
AnnaBridge 146:22da6e220af6 13994 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
AnnaBridge 146:22da6e220af6 13995 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
AnnaBridge 146:22da6e220af6 13996 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
AnnaBridge 146:22da6e220af6 13997 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 13998 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
AnnaBridge 146:22da6e220af6 13999 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
AnnaBridge 146:22da6e220af6 14000 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
AnnaBridge 146:22da6e220af6 14001 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
AnnaBridge 146:22da6e220af6 14002 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
AnnaBridge 146:22da6e220af6 14003 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 14004 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
AnnaBridge 146:22da6e220af6 14005
AnnaBridge 146:22da6e220af6 14006 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 146:22da6e220af6 14007 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 146:22da6e220af6 14008 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14009 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 146:22da6e220af6 14010 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 146:22da6e220af6 14011 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14012 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 146:22da6e220af6 14013 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 146:22da6e220af6 14014 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14015 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 146:22da6e220af6 14016 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 146:22da6e220af6 14017 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14018 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 146:22da6e220af6 14019 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 146:22da6e220af6 14020 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14021 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 146:22da6e220af6 14022 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 146:22da6e220af6 14023 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14024 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 146:22da6e220af6 14025 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 146:22da6e220af6 14026 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14027 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 146:22da6e220af6 14028 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 146:22da6e220af6 14029 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14030 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 146:22da6e220af6 14031 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 146:22da6e220af6 14032 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14033 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 146:22da6e220af6 14034
AnnaBridge 146:22da6e220af6 14035 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 146:22da6e220af6 14036 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 146:22da6e220af6 14037 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14038 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 146:22da6e220af6 14039 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 146:22da6e220af6 14040 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14041 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 146:22da6e220af6 14042 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 146:22da6e220af6 14043 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 14044 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 146:22da6e220af6 14045 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 146:22da6e220af6 14046 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14047 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 146:22da6e220af6 14048 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 146:22da6e220af6 14049 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14050 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 146:22da6e220af6 14051 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 146:22da6e220af6 14052 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14053 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 146:22da6e220af6 14054 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 146:22da6e220af6 14055 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14056 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 146:22da6e220af6 14057 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 146:22da6e220af6 14058 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 14059 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 146:22da6e220af6 14060 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 146:22da6e220af6 14061 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14062 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 146:22da6e220af6 14063
AnnaBridge 146:22da6e220af6 14064 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 146:22da6e220af6 14065 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 146:22da6e220af6 14066 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 146:22da6e220af6 14067 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 14068 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 14069 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 146:22da6e220af6 14070 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 14071 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 146:22da6e220af6 14072
AnnaBridge 146:22da6e220af6 14073 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 146:22da6e220af6 14074 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 146:22da6e220af6 14075 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 146:22da6e220af6 14076 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14077 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 14078 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 14079 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 14080
AnnaBridge 146:22da6e220af6 14081 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 146:22da6e220af6 14082 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 146:22da6e220af6 14083 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 146:22da6e220af6 14084 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 14085 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 14086
AnnaBridge 146:22da6e220af6 14087 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 146:22da6e220af6 14088 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 146:22da6e220af6 14089 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14090 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 146:22da6e220af6 14091 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 146:22da6e220af6 14092 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14093 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 146:22da6e220af6 14094 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 146:22da6e220af6 14095 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14096 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 146:22da6e220af6 14097 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 146:22da6e220af6 14098 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14099 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 146:22da6e220af6 14100 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 146:22da6e220af6 14101 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14102 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 146:22da6e220af6 14103 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 146:22da6e220af6 14104 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14105 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 146:22da6e220af6 14106 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 146:22da6e220af6 14107 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14108 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 146:22da6e220af6 14109 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 146:22da6e220af6 14110 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14111 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 146:22da6e220af6 14112 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 146:22da6e220af6 14113 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 14114 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 146:22da6e220af6 14115 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 146:22da6e220af6 14116 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14117 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 146:22da6e220af6 14118 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 146:22da6e220af6 14119 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 14120 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 146:22da6e220af6 14121
AnnaBridge 146:22da6e220af6 14122 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 146:22da6e220af6 14123 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 146:22da6e220af6 14124 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 14125 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 146:22da6e220af6 14126 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 146:22da6e220af6 14127 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 14128 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 146:22da6e220af6 14129
AnnaBridge 146:22da6e220af6 14130 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 146:22da6e220af6 14131 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14132 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 146:22da6e220af6 14133 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 146:22da6e220af6 14134 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 146:22da6e220af6 14135 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 14136 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 146:22da6e220af6 14137 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 146:22da6e220af6 14138 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 14139 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 146:22da6e220af6 14140 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 146:22da6e220af6 14141 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 14142 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 146:22da6e220af6 14143
AnnaBridge 146:22da6e220af6 14144 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 146:22da6e220af6 14145 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 14146 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 146:22da6e220af6 14147 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 14148 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 14149 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 146:22da6e220af6 14150 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 14151 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 146:22da6e220af6 14152
AnnaBridge 146:22da6e220af6 14153 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 146:22da6e220af6 14154 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 146:22da6e220af6 14155 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 146:22da6e220af6 14156 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 14157 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 14158 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 14159 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 14160 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 146:22da6e220af6 14161 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 14162 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 146:22da6e220af6 14163 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 146:22da6e220af6 14164 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 14165 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 146:22da6e220af6 14166 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 146:22da6e220af6 14167 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 14168 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 146:22da6e220af6 14169 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 146:22da6e220af6 14170 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 14171 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 146:22da6e220af6 14172 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 146:22da6e220af6 14173 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 14174 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 146:22da6e220af6 14175 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 146:22da6e220af6 14176 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 14177 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 146:22da6e220af6 14178
AnnaBridge 146:22da6e220af6 14179 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 146:22da6e220af6 14180 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14181 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 146:22da6e220af6 14182 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 146:22da6e220af6 14183
AnnaBridge 146:22da6e220af6 14184 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 146:22da6e220af6 14185 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 146:22da6e220af6 14186 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 146:22da6e220af6 14187 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 14188 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 14189 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14190 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 14191 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 146:22da6e220af6 14192 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 14193 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 146:22da6e220af6 14194 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 146:22da6e220af6 14195 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 14196 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 146:22da6e220af6 14197
AnnaBridge 146:22da6e220af6 14198 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 146:22da6e220af6 14199 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 14200 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 146:22da6e220af6 14201 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 14202 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 14203
AnnaBridge 146:22da6e220af6 14204 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 146:22da6e220af6 14205 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 146:22da6e220af6 14206 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 146:22da6e220af6 14207 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 14208 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 14209
AnnaBridge 146:22da6e220af6 14210 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 146:22da6e220af6 14211 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 146:22da6e220af6 14212 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 146:22da6e220af6 14213 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 146:22da6e220af6 14214 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 146:22da6e220af6 14215 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 14216 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 146:22da6e220af6 14217 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 14218 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 14219 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 14220 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 146:22da6e220af6 14221 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 14222 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 146:22da6e220af6 14223 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 146:22da6e220af6 14224 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 14225 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 146:22da6e220af6 14226 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 146:22da6e220af6 14227 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 14228 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 146:22da6e220af6 14229
AnnaBridge 146:22da6e220af6 14230 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 146:22da6e220af6 14231
AnnaBridge 146:22da6e220af6 14232 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 146:22da6e220af6 14233 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 146:22da6e220af6 14234 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 146:22da6e220af6 14235 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14236 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14237 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 14238 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14239 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14240 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14241 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14242
AnnaBridge 146:22da6e220af6 14243 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 146:22da6e220af6 14244 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 146:22da6e220af6 14245 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 146:22da6e220af6 14246 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 14247 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14248 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14249 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 14250 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 14251 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 14252 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14253
AnnaBridge 146:22da6e220af6 14254 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 146:22da6e220af6 14255 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 146:22da6e220af6 14256 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 146:22da6e220af6 14257 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 14258 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 14259 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 146:22da6e220af6 14260 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 146:22da6e220af6 14261 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 146:22da6e220af6 14262 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 146:22da6e220af6 14263 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 14264 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 146:22da6e220af6 14265
AnnaBridge 146:22da6e220af6 14266 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 146:22da6e220af6 14267 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 146:22da6e220af6 14268 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14269 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 146:22da6e220af6 14270 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 146:22da6e220af6 14271 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14272 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 146:22da6e220af6 14273 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 146:22da6e220af6 14274 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 14275 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 146:22da6e220af6 14276 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 146:22da6e220af6 14277 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14278 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 146:22da6e220af6 14279 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 146:22da6e220af6 14280 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14281 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 146:22da6e220af6 14282 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 146:22da6e220af6 14283 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14284 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 146:22da6e220af6 14285 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 146:22da6e220af6 14286 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14287 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 146:22da6e220af6 14288 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 146:22da6e220af6 14289 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 14290 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 146:22da6e220af6 14291 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 146:22da6e220af6 14292 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14293 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 146:22da6e220af6 14294 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 146:22da6e220af6 14295 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14296 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 146:22da6e220af6 14297 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 146:22da6e220af6 14298 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 14299 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 146:22da6e220af6 14300
AnnaBridge 146:22da6e220af6 14301 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 146:22da6e220af6 14302 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 146:22da6e220af6 14303 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14304 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 146:22da6e220af6 14305 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 146:22da6e220af6 14306 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14307 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 146:22da6e220af6 14308 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 146:22da6e220af6 14309 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14310 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 146:22da6e220af6 14311 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 146:22da6e220af6 14312 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14313 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 146:22da6e220af6 14314 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 146:22da6e220af6 14315 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14316 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 146:22da6e220af6 14317 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 146:22da6e220af6 14318 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 14319 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 146:22da6e220af6 14320 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 146:22da6e220af6 14321 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14322 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 146:22da6e220af6 14323 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 146:22da6e220af6 14324 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14325 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 146:22da6e220af6 14326 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 146:22da6e220af6 14327 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 146:22da6e220af6 14328 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 146:22da6e220af6 14329 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 146:22da6e220af6 14330 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 146:22da6e220af6 14331 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 146:22da6e220af6 14332 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 146:22da6e220af6 14333 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 146:22da6e220af6 14334 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 146:22da6e220af6 14335
AnnaBridge 146:22da6e220af6 14336 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 146:22da6e220af6 14337 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 146:22da6e220af6 14338 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14339 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 146:22da6e220af6 14340 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 146:22da6e220af6 14341 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14342 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 146:22da6e220af6 14343 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 146:22da6e220af6 14344 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 146:22da6e220af6 14345 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 146:22da6e220af6 14346 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 146:22da6e220af6 14347 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14348 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 146:22da6e220af6 14349 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 146:22da6e220af6 14350 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14351 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 146:22da6e220af6 14352 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 146:22da6e220af6 14353 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14354 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 146:22da6e220af6 14355 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 146:22da6e220af6 14356 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14357 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 146:22da6e220af6 14358 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 146:22da6e220af6 14359 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 146:22da6e220af6 14360 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 146:22da6e220af6 14361 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 146:22da6e220af6 14362 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 146:22da6e220af6 14363 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 146:22da6e220af6 14364 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 146:22da6e220af6 14365 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 146:22da6e220af6 14366 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 146:22da6e220af6 14367 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 146:22da6e220af6 14368 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 146:22da6e220af6 14369 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 146:22da6e220af6 14370
AnnaBridge 146:22da6e220af6 14371 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 146:22da6e220af6 14372
AnnaBridge 146:22da6e220af6 14373 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14374 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 146:22da6e220af6 14375 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 146:22da6e220af6 14376 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 146:22da6e220af6 14377 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 146:22da6e220af6 14378 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 146:22da6e220af6 14379 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 146:22da6e220af6 14380 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 146:22da6e220af6 14381 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 146:22da6e220af6 14382 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 146:22da6e220af6 14383 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14384 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 146:22da6e220af6 14385 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 146:22da6e220af6 14386 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 146:22da6e220af6 14387 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 146:22da6e220af6 14388 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 146:22da6e220af6 14389 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 146:22da6e220af6 14390 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 14391 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 146:22da6e220af6 14392 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 146:22da6e220af6 14393 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 146:22da6e220af6 14394 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 146:22da6e220af6 14395 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 14396 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 14397
AnnaBridge 146:22da6e220af6 14398 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 146:22da6e220af6 14399 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 146:22da6e220af6 14400 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 14401 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 146:22da6e220af6 14402
AnnaBridge 146:22da6e220af6 14403 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 146:22da6e220af6 14404 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 146:22da6e220af6 14405 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 146:22da6e220af6 14406 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 146:22da6e220af6 14407
AnnaBridge 146:22da6e220af6 14408 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 146:22da6e220af6 14409 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 146:22da6e220af6 14410 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 14411 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 146:22da6e220af6 14412
AnnaBridge 146:22da6e220af6 14413 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 146:22da6e220af6 14414 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 146:22da6e220af6 14415 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 146:22da6e220af6 14416 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 146:22da6e220af6 14417 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 146:22da6e220af6 14418 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 146:22da6e220af6 14419 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 146:22da6e220af6 14420
AnnaBridge 146:22da6e220af6 14421 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 146:22da6e220af6 14422
AnnaBridge 146:22da6e220af6 14423 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14424 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 146:22da6e220af6 14425 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 146:22da6e220af6 14426 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 146:22da6e220af6 14427 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 146:22da6e220af6 14428 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 146:22da6e220af6 14429 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 146:22da6e220af6 14430 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 146:22da6e220af6 14431 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 146:22da6e220af6 14432 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 146:22da6e220af6 14433 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 146:22da6e220af6 14434 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 146:22da6e220af6 14435 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 146:22da6e220af6 14436 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 14437 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 146:22da6e220af6 14438 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 146:22da6e220af6 14439 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 146:22da6e220af6 14440 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 146:22da6e220af6 14441 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 146:22da6e220af6 14442 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 146:22da6e220af6 14443 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 146:22da6e220af6 14444 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 146:22da6e220af6 14445 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 146:22da6e220af6 14446 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 146:22da6e220af6 14447 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 146:22da6e220af6 14448 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 146:22da6e220af6 14449 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 146:22da6e220af6 14450 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 146:22da6e220af6 14451 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 146:22da6e220af6 14452 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 146:22da6e220af6 14453 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 146:22da6e220af6 14454 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 146:22da6e220af6 14455 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 146:22da6e220af6 14456 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 14457 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 146:22da6e220af6 14458 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 146:22da6e220af6 14459 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 146:22da6e220af6 14460 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 146:22da6e220af6 14461
AnnaBridge 146:22da6e220af6 14462 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 146:22da6e220af6 14463 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 146:22da6e220af6 14464 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14465 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 146:22da6e220af6 14466 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 146:22da6e220af6 14467 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14468 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 146:22da6e220af6 14469 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 146:22da6e220af6 14470 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 146:22da6e220af6 14471 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 146:22da6e220af6 14472 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 146:22da6e220af6 14473 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14474 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 146:22da6e220af6 14475 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
AnnaBridge 146:22da6e220af6 14476 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
AnnaBridge 146:22da6e220af6 14477 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
AnnaBridge 146:22da6e220af6 14478 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 146:22da6e220af6 14479 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 146:22da6e220af6 14480 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 146:22da6e220af6 14481 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 146:22da6e220af6 14482 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 146:22da6e220af6 14483 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 146:22da6e220af6 14484
AnnaBridge 146:22da6e220af6 14485 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 146:22da6e220af6 14486
AnnaBridge 146:22da6e220af6 14487 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 146:22da6e220af6 14488 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 146:22da6e220af6 14489 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 146:22da6e220af6 14490 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 146:22da6e220af6 14491 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 146:22da6e220af6 14492 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 146:22da6e220af6 14493
AnnaBridge 146:22da6e220af6 14494 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 146:22da6e220af6 14495 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 146:22da6e220af6 14496 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 146:22da6e220af6 14497 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 146:22da6e220af6 14498 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 146:22da6e220af6 14499
AnnaBridge 146:22da6e220af6 14500 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 146:22da6e220af6 14501 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 146:22da6e220af6 14502 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 146:22da6e220af6 14503 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 146:22da6e220af6 14504 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 146:22da6e220af6 14505 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 146:22da6e220af6 14506 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 146:22da6e220af6 14507 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 146:22da6e220af6 14508 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 146:22da6e220af6 14509 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 146:22da6e220af6 14510
AnnaBridge 163:e59c8e839560 14511 /* Legacy define */
AnnaBridge 163:e59c8e839560 14512 /******************** Bit definition for OTG register ********************/
AnnaBridge 163:e59c8e839560 14513 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 163:e59c8e839560 14514 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 163:e59c8e839560 14515 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 163:e59c8e839560 14516 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 163:e59c8e839560 14517 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 163:e59c8e839560 14518 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 163:e59c8e839560 14519 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 163:e59c8e839560 14520 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 163:e59c8e839560 14521 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 163:e59c8e839560 14522 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 163:e59c8e839560 14523
AnnaBridge 163:e59c8e839560 14524 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 163:e59c8e839560 14525 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 163:e59c8e839560 14526 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 163:e59c8e839560 14527 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 163:e59c8e839560 14528 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 163:e59c8e839560 14529
AnnaBridge 163:e59c8e839560 14530 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 163:e59c8e839560 14531 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 163:e59c8e839560 14532 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 163:e59c8e839560 14533 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 163:e59c8e839560 14534 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 163:e59c8e839560 14535 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 163:e59c8e839560 14536 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 163:e59c8e839560 14537
AnnaBridge 163:e59c8e839560 14538 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 163:e59c8e839560 14539 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 163:e59c8e839560 14540 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 163:e59c8e839560 14541 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 163:e59c8e839560 14542 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 163:e59c8e839560 14543 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 163:e59c8e839560 14544 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 163:e59c8e839560 14545
AnnaBridge 163:e59c8e839560 14546 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 163:e59c8e839560 14547 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 163:e59c8e839560 14548 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 163:e59c8e839560 14549 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 163:e59c8e839560 14550 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 163:e59c8e839560 14551 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 163:e59c8e839560 14552 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 146:22da6e220af6 14553 /**
AnnaBridge 146:22da6e220af6 14554 * @}
AnnaBridge 146:22da6e220af6 14555 */
AnnaBridge 146:22da6e220af6 14556
AnnaBridge 146:22da6e220af6 14557 /**
AnnaBridge 146:22da6e220af6 14558 * @}
AnnaBridge 146:22da6e220af6 14559 */
AnnaBridge 146:22da6e220af6 14560
AnnaBridge 146:22da6e220af6 14561 /** @addtogroup Exported_macros
AnnaBridge 146:22da6e220af6 14562 * @{
AnnaBridge 146:22da6e220af6 14563 */
AnnaBridge 146:22da6e220af6 14564
AnnaBridge 146:22da6e220af6 14565 /******************************* ADC Instances ********************************/
AnnaBridge 146:22da6e220af6 14566 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 146:22da6e220af6 14567
AnnaBridge 146:22da6e220af6 14568 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 146:22da6e220af6 14569
AnnaBridge 146:22da6e220af6 14570 /******************************* CAN Instances ********************************/
AnnaBridge 146:22da6e220af6 14571 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
AnnaBridge 146:22da6e220af6 14572 ((INSTANCE) == CAN2) || \
AnnaBridge 146:22da6e220af6 14573 ((INSTANCE) == CAN3))
AnnaBridge 146:22da6e220af6 14574
AnnaBridge 146:22da6e220af6 14575 /****************************** DFSDM Instances *******************************/
AnnaBridge 146:22da6e220af6 14576 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
AnnaBridge 146:22da6e220af6 14577 ((INSTANCE) == DFSDM1_Filter1) || \
AnnaBridge 146:22da6e220af6 14578 ((INSTANCE) == DFSDM2_Filter0) || \
AnnaBridge 146:22da6e220af6 14579 ((INSTANCE) == DFSDM2_Filter1) || \
AnnaBridge 146:22da6e220af6 14580 ((INSTANCE) == DFSDM2_Filter2) || \
AnnaBridge 146:22da6e220af6 14581 ((INSTANCE) == DFSDM2_Filter3))
AnnaBridge 146:22da6e220af6 14582
AnnaBridge 146:22da6e220af6 14583 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
AnnaBridge 146:22da6e220af6 14584 ((INSTANCE) == DFSDM1_Channel1) || \
AnnaBridge 146:22da6e220af6 14585 ((INSTANCE) == DFSDM1_Channel2) || \
AnnaBridge 146:22da6e220af6 14586 ((INSTANCE) == DFSDM1_Channel3) || \
AnnaBridge 146:22da6e220af6 14587 ((INSTANCE) == DFSDM2_Channel0) || \
AnnaBridge 146:22da6e220af6 14588 ((INSTANCE) == DFSDM2_Channel1) || \
AnnaBridge 146:22da6e220af6 14589 ((INSTANCE) == DFSDM2_Channel2) || \
AnnaBridge 146:22da6e220af6 14590 ((INSTANCE) == DFSDM2_Channel3) || \
AnnaBridge 146:22da6e220af6 14591 ((INSTANCE) == DFSDM2_Channel4) || \
AnnaBridge 146:22da6e220af6 14592 ((INSTANCE) == DFSDM2_Channel5) || \
AnnaBridge 146:22da6e220af6 14593 ((INSTANCE) == DFSDM2_Channel6) || \
AnnaBridge 146:22da6e220af6 14594 ((INSTANCE) == DFSDM2_Channel7))
AnnaBridge 146:22da6e220af6 14595 /******************************* CRC Instances ********************************/
AnnaBridge 146:22da6e220af6 14596 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 146:22da6e220af6 14597
AnnaBridge 146:22da6e220af6 14598 /******************************* DAC Instances ********************************/
AnnaBridge 146:22da6e220af6 14599 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 146:22da6e220af6 14600
AnnaBridge 146:22da6e220af6 14601
AnnaBridge 146:22da6e220af6 14602 /******************************** DMA Instances *******************************/
AnnaBridge 146:22da6e220af6 14603 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 146:22da6e220af6 14604 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 146:22da6e220af6 14605 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 146:22da6e220af6 14606 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 146:22da6e220af6 14607 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 146:22da6e220af6 14608 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 146:22da6e220af6 14609 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 146:22da6e220af6 14610 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 146:22da6e220af6 14611 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 146:22da6e220af6 14612 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 146:22da6e220af6 14613 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 146:22da6e220af6 14614 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 146:22da6e220af6 14615 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 146:22da6e220af6 14616 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 146:22da6e220af6 14617 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 146:22da6e220af6 14618 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 146:22da6e220af6 14619
AnnaBridge 146:22da6e220af6 14620 /******************************* GPIO Instances *******************************/
AnnaBridge 146:22da6e220af6 14621 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 146:22da6e220af6 14622 ((INSTANCE) == GPIOB) || \
AnnaBridge 146:22da6e220af6 14623 ((INSTANCE) == GPIOC) || \
AnnaBridge 146:22da6e220af6 14624 ((INSTANCE) == GPIOD) || \
AnnaBridge 146:22da6e220af6 14625 ((INSTANCE) == GPIOE) || \
AnnaBridge 146:22da6e220af6 14626 ((INSTANCE) == GPIOF) || \
AnnaBridge 146:22da6e220af6 14627 ((INSTANCE) == GPIOG) || \
AnnaBridge 146:22da6e220af6 14628 ((INSTANCE) == GPIOH))
AnnaBridge 146:22da6e220af6 14629
AnnaBridge 146:22da6e220af6 14630 /******************************** I2C Instances *******************************/
AnnaBridge 146:22da6e220af6 14631 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 146:22da6e220af6 14632 ((INSTANCE) == I2C2) || \
AnnaBridge 146:22da6e220af6 14633 ((INSTANCE) == I2C3))
AnnaBridge 146:22da6e220af6 14634
AnnaBridge 146:22da6e220af6 14635
AnnaBridge 146:22da6e220af6 14636 /******************************** I2S Instances *******************************/
AnnaBridge 146:22da6e220af6 14637 #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 146:22da6e220af6 14638 ((INSTANCE) == SPI3))
AnnaBridge 146:22da6e220af6 14639
AnnaBridge 146:22da6e220af6 14640 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 146:22da6e220af6 14641 ((INSTANCE) == SPI2) || \
AnnaBridge 146:22da6e220af6 14642 ((INSTANCE) == SPI3) || \
AnnaBridge 146:22da6e220af6 14643 ((INSTANCE) == SPI4) || \
AnnaBridge 146:22da6e220af6 14644 ((INSTANCE) == SPI5))
AnnaBridge 146:22da6e220af6 14645
AnnaBridge 146:22da6e220af6 14646 /*************************** I2S Extended Instances ***************************/
AnnaBridge 146:22da6e220af6 14647 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 146:22da6e220af6 14648 ((INSTANCE) == I2S3ext))
AnnaBridge 146:22da6e220af6 14649 /* Legacy Defines */
AnnaBridge 146:22da6e220af6 14650 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
AnnaBridge 146:22da6e220af6 14651
AnnaBridge 146:22da6e220af6 14652 /******************************* LPTIM Instances ******************************/
AnnaBridge 146:22da6e220af6 14653 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
AnnaBridge 146:22da6e220af6 14654
AnnaBridge 146:22da6e220af6 14655 /******************************* RNG Instances ********************************/
AnnaBridge 146:22da6e220af6 14656 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 146:22da6e220af6 14657
AnnaBridge 146:22da6e220af6 14658 /****************************** RTC Instances *********************************/
AnnaBridge 146:22da6e220af6 14659 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 146:22da6e220af6 14660
AnnaBridge 146:22da6e220af6 14661
AnnaBridge 146:22da6e220af6 14662 /******************************** SPI Instances *******************************/
AnnaBridge 146:22da6e220af6 14663
AnnaBridge 146:22da6e220af6 14664 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 146:22da6e220af6 14665 ((INSTANCE) == SPI2) || \
AnnaBridge 146:22da6e220af6 14666 ((INSTANCE) == SPI3) || \
AnnaBridge 146:22da6e220af6 14667 ((INSTANCE) == SPI4) || \
AnnaBridge 146:22da6e220af6 14668 ((INSTANCE) == SPI5))
AnnaBridge 146:22da6e220af6 14669
AnnaBridge 146:22da6e220af6 14670
AnnaBridge 146:22da6e220af6 14671 /*************************** SPI Extended Instances ***************************/
AnnaBridge 146:22da6e220af6 14672 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 146:22da6e220af6 14673 ((INSTANCE) == SPI2) || \
AnnaBridge 146:22da6e220af6 14674 ((INSTANCE) == SPI3) || \
AnnaBridge 146:22da6e220af6 14675 ((INSTANCE) == SPI4) || \
AnnaBridge 146:22da6e220af6 14676 ((INSTANCE) == SPI5) || \
AnnaBridge 146:22da6e220af6 14677 ((INSTANCE) == I2S2ext) || \
AnnaBridge 146:22da6e220af6 14678 ((INSTANCE) == I2S3ext))
AnnaBridge 146:22da6e220af6 14679 /******************************* SAI Instances ********************************/
AnnaBridge 146:22da6e220af6 14680 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
AnnaBridge 146:22da6e220af6 14681 ((PERIPH) == SAI1_Block_B))
AnnaBridge 146:22da6e220af6 14682 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 146:22da6e220af6 14683 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14684 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14685 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14686 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14687 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14688 ((INSTANCE) == TIM6) || \
AnnaBridge 146:22da6e220af6 14689 ((INSTANCE) == TIM7) || \
AnnaBridge 146:22da6e220af6 14690 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14691 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14692 ((INSTANCE) == TIM10)|| \
AnnaBridge 146:22da6e220af6 14693 ((INSTANCE) == TIM11)|| \
AnnaBridge 146:22da6e220af6 14694 ((INSTANCE) == TIM12)|| \
AnnaBridge 146:22da6e220af6 14695 ((INSTANCE) == TIM13)|| \
AnnaBridge 146:22da6e220af6 14696 ((INSTANCE) == TIM14))
AnnaBridge 146:22da6e220af6 14697
AnnaBridge 146:22da6e220af6 14698 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 146:22da6e220af6 14699 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14700 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14701 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14702 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14703 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14704 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14705 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14706 ((INSTANCE) == TIM10) || \
AnnaBridge 146:22da6e220af6 14707 ((INSTANCE) == TIM11) || \
AnnaBridge 146:22da6e220af6 14708 ((INSTANCE) == TIM12) || \
AnnaBridge 146:22da6e220af6 14709 ((INSTANCE) == TIM13) || \
AnnaBridge 146:22da6e220af6 14710 ((INSTANCE) == TIM14))
AnnaBridge 146:22da6e220af6 14711
AnnaBridge 146:22da6e220af6 14712 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 146:22da6e220af6 14713 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14714 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14715 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14716 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14717 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14718 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14719 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14720 ((INSTANCE) == TIM12))
AnnaBridge 146:22da6e220af6 14721
AnnaBridge 146:22da6e220af6 14722 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 146:22da6e220af6 14723 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14724 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14725 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14726 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14727 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14728 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14729
AnnaBridge 146:22da6e220af6 14730 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 146:22da6e220af6 14731 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14732 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14733 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14734 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14735 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14736 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14737
AnnaBridge 146:22da6e220af6 14738 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 146:22da6e220af6 14739 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14740 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14741
AnnaBridge 146:22da6e220af6 14742 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 146:22da6e220af6 14743 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14744 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14745 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14746 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14747 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14748 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14749
AnnaBridge 146:22da6e220af6 14750 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 146:22da6e220af6 14751 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14752 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14753 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14754 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14755 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14756 ((INSTANCE) == TIM6) || \
AnnaBridge 146:22da6e220af6 14757 ((INSTANCE) == TIM7) || \
AnnaBridge 146:22da6e220af6 14758 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14759
AnnaBridge 146:22da6e220af6 14760 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 146:22da6e220af6 14761 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14762 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14763 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14764 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14765 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14766 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14767
AnnaBridge 146:22da6e220af6 14768 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 146:22da6e220af6 14769 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14770 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14771 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14772 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14773 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14774 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14775
AnnaBridge 146:22da6e220af6 14776 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 146:22da6e220af6 14777 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14778 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14779 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14780 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14781 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14782 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14783
AnnaBridge 146:22da6e220af6 14784 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 146:22da6e220af6 14785 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14786 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14787 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14788 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14789 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14790 ((INSTANCE) == TIM6) || \
AnnaBridge 146:22da6e220af6 14791 ((INSTANCE) == TIM7) || \
AnnaBridge 146:22da6e220af6 14792 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14793
AnnaBridge 146:22da6e220af6 14794 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 146:22da6e220af6 14795 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14796 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14797 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14798 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14799 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14800 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14801 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14802 ((INSTANCE) == TIM12))
AnnaBridge 146:22da6e220af6 14803
AnnaBridge 146:22da6e220af6 14804 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 146:22da6e220af6 14805 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14806 ((INSTANCE) == TIM5))
AnnaBridge 146:22da6e220af6 14807
AnnaBridge 146:22da6e220af6 14808 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 146:22da6e220af6 14809 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14810 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14811 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14812 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14813 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14814 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14815
AnnaBridge 146:22da6e220af6 14816 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 146:22da6e220af6 14817 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14818 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14819 ((INSTANCE) == TIM11))
AnnaBridge 146:22da6e220af6 14820
AnnaBridge 146:22da6e220af6 14821 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 146:22da6e220af6 14822 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 146:22da6e220af6 14823 ((((INSTANCE) == TIM1) && \
AnnaBridge 146:22da6e220af6 14824 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14825 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14826 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14827 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14828 || \
AnnaBridge 146:22da6e220af6 14829 (((INSTANCE) == TIM2) && \
AnnaBridge 146:22da6e220af6 14830 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14831 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14832 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14833 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14834 || \
AnnaBridge 146:22da6e220af6 14835 (((INSTANCE) == TIM3) && \
AnnaBridge 146:22da6e220af6 14836 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14837 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14838 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14839 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14840 || \
AnnaBridge 146:22da6e220af6 14841 (((INSTANCE) == TIM4) && \
AnnaBridge 146:22da6e220af6 14842 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14843 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14844 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14845 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14846 || \
AnnaBridge 146:22da6e220af6 14847 (((INSTANCE) == TIM5) && \
AnnaBridge 146:22da6e220af6 14848 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14849 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14850 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14851 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14852 || \
AnnaBridge 146:22da6e220af6 14853 (((INSTANCE) == TIM8) && \
AnnaBridge 146:22da6e220af6 14854 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14855 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14856 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 146:22da6e220af6 14857 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 146:22da6e220af6 14858 || \
AnnaBridge 146:22da6e220af6 14859 (((INSTANCE) == TIM9) && \
AnnaBridge 146:22da6e220af6 14860 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14861 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 146:22da6e220af6 14862 || \
AnnaBridge 146:22da6e220af6 14863 (((INSTANCE) == TIM10) && \
AnnaBridge 146:22da6e220af6 14864 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 146:22da6e220af6 14865 || \
AnnaBridge 146:22da6e220af6 14866 (((INSTANCE) == TIM11) && \
AnnaBridge 146:22da6e220af6 14867 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 146:22da6e220af6 14868 || \
AnnaBridge 146:22da6e220af6 14869 (((INSTANCE) == TIM12) && \
AnnaBridge 146:22da6e220af6 14870 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14871 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 146:22da6e220af6 14872 || \
AnnaBridge 146:22da6e220af6 14873 (((INSTANCE) == TIM13) && \
AnnaBridge 146:22da6e220af6 14874 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 146:22da6e220af6 14875 || \
AnnaBridge 146:22da6e220af6 14876 (((INSTANCE) == TIM14) && \
AnnaBridge 146:22da6e220af6 14877 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 146:22da6e220af6 14878
AnnaBridge 146:22da6e220af6 14879 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 146:22da6e220af6 14880 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 146:22da6e220af6 14881 ((((INSTANCE) == TIM1) && \
AnnaBridge 146:22da6e220af6 14882 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14883 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14884 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 146:22da6e220af6 14885 || \
AnnaBridge 146:22da6e220af6 14886 (((INSTANCE) == TIM8) && \
AnnaBridge 146:22da6e220af6 14887 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 146:22da6e220af6 14888 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 146:22da6e220af6 14889 ((CHANNEL) == TIM_CHANNEL_3))))
AnnaBridge 146:22da6e220af6 14890
AnnaBridge 146:22da6e220af6 14891 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 146:22da6e220af6 14892 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14893 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14894 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14895 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14896 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14897 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14898
AnnaBridge 146:22da6e220af6 14899 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 146:22da6e220af6 14900 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14901 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14902 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14903 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14904 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14905 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14906 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14907 ((INSTANCE) == TIM10)|| \
AnnaBridge 146:22da6e220af6 14908 ((INSTANCE) == TIM11)|| \
AnnaBridge 146:22da6e220af6 14909 ((INSTANCE) == TIM12)|| \
AnnaBridge 146:22da6e220af6 14910 ((INSTANCE) == TIM13)|| \
AnnaBridge 146:22da6e220af6 14911 ((INSTANCE) == TIM14))
AnnaBridge 146:22da6e220af6 14912
AnnaBridge 146:22da6e220af6 14913 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 146:22da6e220af6 14914 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 146:22da6e220af6 14915 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14916
AnnaBridge 146:22da6e220af6 14917
AnnaBridge 146:22da6e220af6 14918 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 146:22da6e220af6 14919 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14920 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14921 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14922 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14923 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14924 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14925
AnnaBridge 146:22da6e220af6 14926 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 146:22da6e220af6 14927 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14928 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14929 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14930 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14931 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14932 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14933 ((INSTANCE) == TIM9) || \
AnnaBridge 146:22da6e220af6 14934 ((INSTANCE) == TIM12))
AnnaBridge 146:22da6e220af6 14935
AnnaBridge 146:22da6e220af6 14936 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 146:22da6e220af6 14937 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14938 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14939 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14940 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14941 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14942 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14943
AnnaBridge 146:22da6e220af6 14944 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 146:22da6e220af6 14945 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14946 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14947
AnnaBridge 146:22da6e220af6 14948 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 146:22da6e220af6 14949 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14950 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14951 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14952 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14953 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14954 ((INSTANCE) == TIM8) || \
AnnaBridge 146:22da6e220af6 14955 ((INSTANCE) == TIM9))
AnnaBridge 146:22da6e220af6 14956 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 146:22da6e220af6 14957 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14958 ((INSTANCE) == TIM2) || \
AnnaBridge 146:22da6e220af6 14959 ((INSTANCE) == TIM3) || \
AnnaBridge 146:22da6e220af6 14960 ((INSTANCE) == TIM4) || \
AnnaBridge 146:22da6e220af6 14961 ((INSTANCE) == TIM5) || \
AnnaBridge 146:22da6e220af6 14962 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14963 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 146:22da6e220af6 14964 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 146:22da6e220af6 14965 ((INSTANCE) == TIM8))
AnnaBridge 146:22da6e220af6 14966
AnnaBridge 146:22da6e220af6 14967 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 146:22da6e220af6 14968 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 146:22da6e220af6 14969 ((INSTANCE) == USART2) || \
AnnaBridge 146:22da6e220af6 14970 ((INSTANCE) == USART3) || \
AnnaBridge 146:22da6e220af6 14971 ((INSTANCE) == USART6))
AnnaBridge 146:22da6e220af6 14972
AnnaBridge 146:22da6e220af6 14973 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 146:22da6e220af6 14974 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 146:22da6e220af6 14975 ((INSTANCE) == USART2) || \
AnnaBridge 146:22da6e220af6 14976 ((INSTANCE) == USART3) || \
AnnaBridge 146:22da6e220af6 14977 ((INSTANCE) == UART4) || \
AnnaBridge 146:22da6e220af6 14978 ((INSTANCE) == UART5) || \
AnnaBridge 146:22da6e220af6 14979 ((INSTANCE) == USART6) || \
AnnaBridge 146:22da6e220af6 14980 ((INSTANCE) == UART7) || \
AnnaBridge 146:22da6e220af6 14981 ((INSTANCE) == UART8) || \
AnnaBridge 146:22da6e220af6 14982 ((INSTANCE) == UART9) || \
AnnaBridge 146:22da6e220af6 14983 ((INSTANCE) == UART10))
AnnaBridge 146:22da6e220af6 14984
AnnaBridge 146:22da6e220af6 14985 /* Legacy defines */
AnnaBridge 146:22da6e220af6 14986 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 146:22da6e220af6 14987
AnnaBridge 146:22da6e220af6 14988 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 146:22da6e220af6 14989 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 146:22da6e220af6 14990 ((INSTANCE) == USART2) || \
AnnaBridge 146:22da6e220af6 14991 ((INSTANCE) == USART3) || \
AnnaBridge 146:22da6e220af6 14992 ((INSTANCE) == USART6))
AnnaBridge 146:22da6e220af6 14993 /******************** UART Instances : LIN mode **********************/
AnnaBridge 146:22da6e220af6 14994 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 146:22da6e220af6 14995
AnnaBridge 146:22da6e220af6 14996 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 146:22da6e220af6 14997 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 146:22da6e220af6 14998 ((INSTANCE) == USART2) || \
AnnaBridge 146:22da6e220af6 14999 ((INSTANCE) == USART3) || \
AnnaBridge 146:22da6e220af6 15000 ((INSTANCE) == USART6))
AnnaBridge 146:22da6e220af6 15001
AnnaBridge 146:22da6e220af6 15002 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 146:22da6e220af6 15003 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 146:22da6e220af6 15004 ((INSTANCE) == USART2) || \
AnnaBridge 146:22da6e220af6 15005 ((INSTANCE) == USART3) || \
AnnaBridge 146:22da6e220af6 15006 ((INSTANCE) == UART4) || \
AnnaBridge 146:22da6e220af6 15007 ((INSTANCE) == UART5) || \
AnnaBridge 146:22da6e220af6 15008 ((INSTANCE) == USART6) || \
AnnaBridge 146:22da6e220af6 15009 ((INSTANCE) == UART7) || \
AnnaBridge 146:22da6e220af6 15010 ((INSTANCE) == UART8) || \
AnnaBridge 146:22da6e220af6 15011 ((INSTANCE) == UART9) || \
AnnaBridge 146:22da6e220af6 15012 ((INSTANCE) == UART10))
AnnaBridge 146:22da6e220af6 15013
AnnaBridge 146:22da6e220af6 15014 /*********************** PCD Instances ****************************************/
AnnaBridge 146:22da6e220af6 15015 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
AnnaBridge 146:22da6e220af6 15016
AnnaBridge 146:22da6e220af6 15017 /*********************** HCD Instances ****************************************/
AnnaBridge 146:22da6e220af6 15018 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
AnnaBridge 146:22da6e220af6 15019
AnnaBridge 146:22da6e220af6 15020 /****************************** SDIO Instances ********************************/
AnnaBridge 146:22da6e220af6 15021 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
AnnaBridge 146:22da6e220af6 15022
AnnaBridge 146:22da6e220af6 15023 /****************************** IWDG Instances ********************************/
AnnaBridge 146:22da6e220af6 15024 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 146:22da6e220af6 15025
AnnaBridge 146:22da6e220af6 15026 /****************************** WWDG Instances ********************************/
AnnaBridge 146:22da6e220af6 15027 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 146:22da6e220af6 15028
AnnaBridge 146:22da6e220af6 15029
AnnaBridge 146:22da6e220af6 15030 /***************************** FMPI2C Instances *******************************/
AnnaBridge 146:22da6e220af6 15031 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
AnnaBridge 146:22da6e220af6 15032
AnnaBridge 146:22da6e220af6 15033 /****************************** QSPI Instances ********************************/
AnnaBridge 146:22da6e220af6 15034 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
AnnaBridge 146:22da6e220af6 15035 /****************************** USB Instances ********************************/
AnnaBridge 146:22da6e220af6 15036 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
AnnaBridge 146:22da6e220af6 15037 /****************************** USB Exported Constants ************************/
AnnaBridge 146:22da6e220af6 15038 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
AnnaBridge 146:22da6e220af6 15039 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 146:22da6e220af6 15040 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 146:22da6e220af6 15041 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
AnnaBridge 146:22da6e220af6 15042
AnnaBridge 146:22da6e220af6 15043 /*
AnnaBridge 146:22da6e220af6 15044 * @brief Specific devices reset values definitions
AnnaBridge 146:22da6e220af6 15045 */
AnnaBridge 146:22da6e220af6 15046 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 146:22da6e220af6 15047 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
AnnaBridge 146:22da6e220af6 15048
AnnaBridge 146:22da6e220af6 15049 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
AnnaBridge 146:22da6e220af6 15050 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
AnnaBridge 146:22da6e220af6 15051 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 146:22da6e220af6 15052 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 146:22da6e220af6 15053 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 146:22da6e220af6 15054 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 146:22da6e220af6 15055 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 146:22da6e220af6 15056 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 146:22da6e220af6 15057
AnnaBridge 146:22da6e220af6 15058 #define RCC_PLLN_MIN_VALUE 50U
AnnaBridge 146:22da6e220af6 15059 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 146:22da6e220af6 15060
AnnaBridge 146:22da6e220af6 15061 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 146:22da6e220af6 15062 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 146:22da6e220af6 15063 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 146:22da6e220af6 15064
AnnaBridge 146:22da6e220af6 15065 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 146:22da6e220af6 15066 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 146:22da6e220af6 15067
AnnaBridge 146:22da6e220af6 15068 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 146:22da6e220af6 15069 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 146:22da6e220af6 15070
AnnaBridge 146:22da6e220af6 15071
AnnaBridge 146:22da6e220af6 15072 /**
AnnaBridge 146:22da6e220af6 15073 * @}
AnnaBridge 146:22da6e220af6 15074 */
AnnaBridge 146:22da6e220af6 15075
AnnaBridge 146:22da6e220af6 15076 /**
AnnaBridge 146:22da6e220af6 15077 * @}
AnnaBridge 146:22da6e220af6 15078 */
AnnaBridge 146:22da6e220af6 15079
AnnaBridge 146:22da6e220af6 15080 /**
AnnaBridge 146:22da6e220af6 15081 * @}
AnnaBridge 146:22da6e220af6 15082 */
AnnaBridge 146:22da6e220af6 15083
AnnaBridge 146:22da6e220af6 15084 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 15085 }
AnnaBridge 146:22da6e220af6 15086 #endif /* __cplusplus */
AnnaBridge 146:22da6e220af6 15087
AnnaBridge 146:22da6e220af6 15088 #endif /* __STM32F413xx_H */
AnnaBridge 146:22da6e220af6 15089
AnnaBridge 146:22da6e220af6 15090
AnnaBridge 146:22da6e220af6 15091
AnnaBridge 146:22da6e220af6 15092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/