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TARGET_NUCLEO_F412ZG/TOOLCHAIN_IAR/pin_device.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/pin_device.h@170:e95d10626187
Child:
172:65be27845400
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /* mbed Microcontroller Library
AnnaBridge 161:aa5281ff4a02 2 *******************************************************************************
AnnaBridge 161:aa5281ff4a02 3 * Copyright (c) 2016, STMicroelectronics
AnnaBridge 161:aa5281ff4a02 4 * All rights reserved.
AnnaBridge 161:aa5281ff4a02 5 *
AnnaBridge 161:aa5281ff4a02 6 * Redistribution and use in source and binary forms, with or without
AnnaBridge 161:aa5281ff4a02 7 * modification, are permitted provided that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 8 *
AnnaBridge 161:aa5281ff4a02 9 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 161:aa5281ff4a02 10 * this list of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 161:aa5281ff4a02 12 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 161:aa5281ff4a02 13 * and/or other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 161:aa5281ff4a02 15 * may be used to endorse or promote products derived from this software
AnnaBridge 161:aa5281ff4a02 16 * without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 161:aa5281ff4a02 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 161:aa5281ff4a02 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 161:aa5281ff4a02 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 161:aa5281ff4a02 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 161:aa5281ff4a02 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 161:aa5281ff4a02 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 161:aa5281ff4a02 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 161:aa5281ff4a02 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 28 *******************************************************************************
AnnaBridge 161:aa5281ff4a02 29 */
AnnaBridge 161:aa5281ff4a02 30 #ifndef MBED_PIN_DEVICE_H
AnnaBridge 161:aa5281ff4a02 31 #define MBED_PIN_DEVICE_H
AnnaBridge 161:aa5281ff4a02 32
AnnaBridge 161:aa5281ff4a02 33 #include "cmsis.h"
AnnaBridge 161:aa5281ff4a02 34
AnnaBridge 161:aa5281ff4a02 35 // when LL is available, below include can be used
AnnaBridge 161:aa5281ff4a02 36 // #include "stm32f4xx_ll_gpio.h"
AnnaBridge 161:aa5281ff4a02 37 // until then let's define locally the required functions
AnnaBridge 161:aa5281ff4a02 38 #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
AnnaBridge 161:aa5281ff4a02 39 #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
AnnaBridge 161:aa5281ff4a02 40 #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
AnnaBridge 161:aa5281ff4a02 41 #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
AnnaBridge 161:aa5281ff4a02 42 #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
AnnaBridge 161:aa5281ff4a02 43 #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
AnnaBridge 161:aa5281ff4a02 44 #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
AnnaBridge 161:aa5281ff4a02 45 #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
AnnaBridge 161:aa5281ff4a02 46 #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
AnnaBridge 161:aa5281ff4a02 47 #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
AnnaBridge 161:aa5281ff4a02 48 #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
AnnaBridge 161:aa5281ff4a02 49 #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
AnnaBridge 161:aa5281ff4a02 50 #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
AnnaBridge 161:aa5281ff4a02 51 #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
AnnaBridge 161:aa5281ff4a02 52 #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
AnnaBridge 161:aa5281ff4a02 53 #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
AnnaBridge 161:aa5281ff4a02 54
AnnaBridge 161:aa5281ff4a02 55 #define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */
AnnaBridge 161:aa5281ff4a02 56 #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
AnnaBridge 161:aa5281ff4a02 57 #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
AnnaBridge 161:aa5281ff4a02 58 #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
AnnaBridge 161:aa5281ff4a02 59
AnnaBridge 161:aa5281ff4a02 60 #define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
AnnaBridge 161:aa5281ff4a02 61 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
AnnaBridge 161:aa5281ff4a02 62
AnnaBridge 161:aa5281ff4a02 63 #define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */
AnnaBridge 161:aa5281ff4a02 64 #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
AnnaBridge 161:aa5281ff4a02 65 #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
AnnaBridge 161:aa5281ff4a02 66
AnnaBridge 161:aa5281ff4a02 67 #define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */
AnnaBridge 161:aa5281ff4a02 68 #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
AnnaBridge 161:aa5281ff4a02 69 #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
AnnaBridge 161:aa5281ff4a02 70 #define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
AnnaBridge 161:aa5281ff4a02 71
AnnaBridge 161:aa5281ff4a02 72 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
AnnaBridge 161:aa5281ff4a02 73 {
AnnaBridge 170:e95d10626187 74 MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)),
AnnaBridge 170:e95d10626187 75 (Alternate << (POSITION_VAL(Pin) * 4U)));
AnnaBridge 161:aa5281ff4a02 76 }
AnnaBridge 161:aa5281ff4a02 77 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
AnnaBridge 161:aa5281ff4a02 78 {
AnnaBridge 170:e95d10626187 79 MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)),
AnnaBridge 170:e95d10626187 80 (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
AnnaBridge 161:aa5281ff4a02 81 }
AnnaBridge 161:aa5281ff4a02 82 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
AnnaBridge 161:aa5281ff4a02 83 {
AnnaBridge 170:e95d10626187 84 MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
AnnaBridge 161:aa5281ff4a02 85 }
AnnaBridge 161:aa5281ff4a02 86 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
AnnaBridge 161:aa5281ff4a02 87 {
AnnaBridge 170:e95d10626187 88 return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
AnnaBridge 161:aa5281ff4a02 89 }
AnnaBridge 161:aa5281ff4a02 90 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
AnnaBridge 161:aa5281ff4a02 91 {
AnnaBridge 170:e95d10626187 92 MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
AnnaBridge 161:aa5281ff4a02 93 }
AnnaBridge 161:aa5281ff4a02 94 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
AnnaBridge 161:aa5281ff4a02 95 {
AnnaBridge 170:e95d10626187 96 MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
AnnaBridge 161:aa5281ff4a02 97 }
AnnaBridge 161:aa5281ff4a02 98 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
AnnaBridge 161:aa5281ff4a02 99 {
AnnaBridge 170:e95d10626187 100 MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
AnnaBridge 170:e95d10626187 101 (Speed << (POSITION_VAL(Pin) * 2U)));
AnnaBridge 161:aa5281ff4a02 102 }
AnnaBridge 161:aa5281ff4a02 103 // Above lines shall be defined in LL when available
AnnaBridge 161:aa5281ff4a02 104
AnnaBridge 161:aa5281ff4a02 105 extern const uint32_t ll_pin_defines[16];
AnnaBridge 161:aa5281ff4a02 106
AnnaBridge 161:aa5281ff4a02 107 /* Family specific implementations */
AnnaBridge 161:aa5281ff4a02 108 static inline void stm_pin_DisconnectDebug(PinName pin)
AnnaBridge 161:aa5281ff4a02 109 {
AnnaBridge 161:aa5281ff4a02 110 /* empty for now */
AnnaBridge 161:aa5281ff4a02 111 }
AnnaBridge 161:aa5281ff4a02 112
AnnaBridge 161:aa5281ff4a02 113 static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
AnnaBridge 161:aa5281ff4a02 114 {
AnnaBridge 161:aa5281ff4a02 115 switch (pull_config) {
AnnaBridge 161:aa5281ff4a02 116 case GPIO_PULLUP:
AnnaBridge 161:aa5281ff4a02 117 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
AnnaBridge 161:aa5281ff4a02 118 break;
AnnaBridge 161:aa5281ff4a02 119 case GPIO_PULLDOWN:
AnnaBridge 161:aa5281ff4a02 120 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
AnnaBridge 161:aa5281ff4a02 121 break;
AnnaBridge 161:aa5281ff4a02 122 default:
AnnaBridge 161:aa5281ff4a02 123 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO);
AnnaBridge 161:aa5281ff4a02 124 break;
AnnaBridge 161:aa5281ff4a02 125 }
AnnaBridge 161:aa5281ff4a02 126 }
AnnaBridge 161:aa5281ff4a02 127
AnnaBridge 170:e95d10626187 128 static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
AnnaBridge 161:aa5281ff4a02 129 {
AnnaBridge 161:aa5281ff4a02 130 uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
AnnaBridge 161:aa5281ff4a02 131
AnnaBridge 170:e95d10626187 132 if (STM_PIN(pin) > 7) {
AnnaBridge 161:aa5281ff4a02 133 LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
AnnaBridge 170:e95d10626187 134 } else {
AnnaBridge 161:aa5281ff4a02 135 LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
AnnaBridge 170:e95d10626187 136 }
AnnaBridge 161:aa5281ff4a02 137 }
AnnaBridge 161:aa5281ff4a02 138
AnnaBridge 161:aa5281ff4a02 139 #endif