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TARGET_NUCLEO_F412ZG/TOOLCHAIN_GCC_ARM/stm32f4xx_hal_rcc_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_STEVAL_3DP001V1/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@163:e59c8e839560

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32f4xx_hal_rcc_ex.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	163:e59c8e839560	6	******************************************************************************
AnnaBridge	163:e59c8e839560	7	* @attention
AnnaBridge	163:e59c8e839560	8	*
AnnaBridge	163:e59c8e839560	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	10	*
AnnaBridge	163:e59c8e839560	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	12	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	14	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	17	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	19	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	20	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	21	*
AnnaBridge	163:e59c8e839560	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	32	*
AnnaBridge	163:e59c8e839560	33	******************************************************************************
AnnaBridge	163:e59c8e839560	34	*/
AnnaBridge	163:e59c8e839560	35
AnnaBridge	163:e59c8e839560	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	37	#ifndef __STM32F4xx_HAL_RCC_EX_H
AnnaBridge	163:e59c8e839560	38	#define __STM32F4xx_HAL_RCC_EX_H
AnnaBridge	163:e59c8e839560	39
AnnaBridge	163:e59c8e839560	40	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	41	extern "C" {
AnnaBridge	163:e59c8e839560	42	#endif
AnnaBridge	163:e59c8e839560	43
AnnaBridge	163:e59c8e839560	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	163:e59c8e839560	46
AnnaBridge	163:e59c8e839560	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	163:e59c8e839560	48	* @{
AnnaBridge	163:e59c8e839560	49	*/
AnnaBridge	163:e59c8e839560	50
AnnaBridge	163:e59c8e839560	51	/** @addtogroup RCCEx
AnnaBridge	163:e59c8e839560	52	* @{
AnnaBridge	163:e59c8e839560	53	*/
AnnaBridge	163:e59c8e839560	54
AnnaBridge	163:e59c8e839560	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	56	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	163:e59c8e839560	57	* @{
AnnaBridge	163:e59c8e839560	58	*/
AnnaBridge	163:e59c8e839560	59
AnnaBridge	163:e59c8e839560	60	/**
AnnaBridge	163:e59c8e839560	61	* @brief RCC PLL configuration structure definition
AnnaBridge	163:e59c8e839560	62	*/
AnnaBridge	163:e59c8e839560	63	typedef struct
AnnaBridge	163:e59c8e839560	64	{
AnnaBridge	163:e59c8e839560	65	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	163:e59c8e839560	66	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	163:e59c8e839560	67
AnnaBridge	163:e59c8e839560	68	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	163:e59c8e839560	69	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	163:e59c8e839560	70
AnnaBridge	163:e59c8e839560	71	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	163:e59c8e839560	72	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
AnnaBridge	163:e59c8e839560	73
AnnaBridge	163:e59c8e839560	74	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	163:e59c8e839560	75	This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	163:e59c8e839560	76	except for STM32F411xE devices where the Min_Data = 192 */
AnnaBridge	163:e59c8e839560	77
AnnaBridge	163:e59c8e839560	78	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
AnnaBridge	163:e59c8e839560	79	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	163:e59c8e839560	80
AnnaBridge	163:e59c8e839560	81	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	82	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
AnnaBridge	163:e59c8e839560	83	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	163:e59c8e839560	84	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	85	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	86	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
AnnaBridge	163:e59c8e839560	87	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
AnnaBridge	163:e59c8e839560	88	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
AnnaBridge	163:e59c8e839560	89	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
AnnaBridge	163:e59c8e839560	90	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	91	}RCC_PLLInitTypeDef;
AnnaBridge	163:e59c8e839560	92
AnnaBridge	163:e59c8e839560	93	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	94	/**
AnnaBridge	163:e59c8e839560	95	* @brief PLLI2S Clock structure definition
AnnaBridge	163:e59c8e839560	96	*/
AnnaBridge	163:e59c8e839560	97	typedef struct
AnnaBridge	163:e59c8e839560	98	{
AnnaBridge	163:e59c8e839560	99	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
AnnaBridge	163:e59c8e839560	100	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	163:e59c8e839560	101
AnnaBridge	163:e59c8e839560	102	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	103	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	163:e59c8e839560	104
AnnaBridge	163:e59c8e839560	105	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
AnnaBridge	163:e59c8e839560	106	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
AnnaBridge	163:e59c8e839560	107
AnnaBridge	163:e59c8e839560	108	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	163:e59c8e839560	109	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	110	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	111
AnnaBridge	163:e59c8e839560	112	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	163:e59c8e839560	113	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	114	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	163:e59c8e839560	115	}RCC_PLLI2SInitTypeDef;
AnnaBridge	163:e59c8e839560	116
AnnaBridge	163:e59c8e839560	117	/**
AnnaBridge	163:e59c8e839560	118	* @brief PLLSAI Clock structure definition
AnnaBridge	163:e59c8e839560	119	*/
AnnaBridge	163:e59c8e839560	120	typedef struct
AnnaBridge	163:e59c8e839560	121	{
AnnaBridge	163:e59c8e839560	122	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
AnnaBridge	163:e59c8e839560	123	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	163:e59c8e839560	124
AnnaBridge	163:e59c8e839560	125	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	126	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	163:e59c8e839560	127
AnnaBridge	163:e59c8e839560	128	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	129	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
AnnaBridge	163:e59c8e839560	130
AnnaBridge	163:e59c8e839560	131	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	163:e59c8e839560	132	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	133	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	134	}RCC_PLLSAIInitTypeDef;
AnnaBridge	163:e59c8e839560	135
AnnaBridge	163:e59c8e839560	136	/**
AnnaBridge	163:e59c8e839560	137	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	138	*/
AnnaBridge	163:e59c8e839560	139	typedef struct
AnnaBridge	163:e59c8e839560	140	{
AnnaBridge	163:e59c8e839560	141	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	142	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	143
AnnaBridge	163:e59c8e839560	144	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	163:e59c8e839560	145	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	146
AnnaBridge	163:e59c8e839560	147	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge	163:e59c8e839560	148	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge	163:e59c8e839560	149
AnnaBridge	163:e59c8e839560	150	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	151	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	152	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	153
AnnaBridge	163:e59c8e839560	154	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	155	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	156	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	157
AnnaBridge	163:e59c8e839560	158	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	159	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	163:e59c8e839560	160
AnnaBridge	163:e59c8e839560	161	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
AnnaBridge	163:e59c8e839560	162	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge	163:e59c8e839560	163
AnnaBridge	163:e59c8e839560	164	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	165	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
AnnaBridge	163:e59c8e839560	166
AnnaBridge	163:e59c8e839560	167	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
AnnaBridge	163:e59c8e839560	168	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
AnnaBridge	163:e59c8e839560	169
AnnaBridge	163:e59c8e839560	170	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	163:e59c8e839560	171	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	172
AnnaBridge	163:e59c8e839560	173	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	163:e59c8e839560	174	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	163:e59c8e839560	175
AnnaBridge	163:e59c8e839560	176	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
AnnaBridge	163:e59c8e839560	177	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	163:e59c8e839560	178
AnnaBridge	163:e59c8e839560	179	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	180	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	181
AnnaBridge	163:e59c8e839560	182	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
AnnaBridge	163:e59c8e839560	183	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
AnnaBridge	163:e59c8e839560	184
AnnaBridge	163:e59c8e839560	185	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	186	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	163:e59c8e839560	187
AnnaBridge	163:e59c8e839560	188	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	163:e59c8e839560	189	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	163:e59c8e839560	190	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	191	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	192
AnnaBridge	163:e59c8e839560	193	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	194	/**
AnnaBridge	163:e59c8e839560	195	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	196	*/
AnnaBridge	163:e59c8e839560	197	typedef struct
AnnaBridge	163:e59c8e839560	198	{
AnnaBridge	163:e59c8e839560	199	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	200	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	201
AnnaBridge	163:e59c8e839560	202	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	163:e59c8e839560	203	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
AnnaBridge	163:e59c8e839560	204
AnnaBridge	163:e59c8e839560	205	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	163:e59c8e839560	206	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	207
AnnaBridge	163:e59c8e839560	208	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	209	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	210
AnnaBridge	163:e59c8e839560	211	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	212	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	213
AnnaBridge	163:e59c8e839560	214	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	163:e59c8e839560	215	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	163:e59c8e839560	216	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	217	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	218
AnnaBridge	163:e59c8e839560	219	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	220	/**
AnnaBridge	163:e59c8e839560	221	* @brief PLLI2S Clock structure definition
AnnaBridge	163:e59c8e839560	222	*/
AnnaBridge	163:e59c8e839560	223	typedef struct
AnnaBridge	163:e59c8e839560	224	{
AnnaBridge	163:e59c8e839560	225	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
AnnaBridge	163:e59c8e839560	226	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	163:e59c8e839560	227
AnnaBridge	163:e59c8e839560	228	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	229	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	163:e59c8e839560	230
AnnaBridge	163:e59c8e839560	231	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	163:e59c8e839560	232	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	233	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	234
AnnaBridge	163:e59c8e839560	235	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	163:e59c8e839560	236	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	163:e59c8e839560	238	}RCC_PLLI2SInitTypeDef;
AnnaBridge	163:e59c8e839560	239
AnnaBridge	163:e59c8e839560	240	/**
AnnaBridge	163:e59c8e839560	241	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	242	*/
AnnaBridge	163:e59c8e839560	243	typedef struct
AnnaBridge	163:e59c8e839560	244	{
AnnaBridge	163:e59c8e839560	245	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	246	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	247
AnnaBridge	163:e59c8e839560	248	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	163:e59c8e839560	249	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	163:e59c8e839560	250
AnnaBridge	163:e59c8e839560	251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	252	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	253	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	254	This parameter will be used only when PLL is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	255
AnnaBridge	163:e59c8e839560	256	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	257	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	258	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	259	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	260
AnnaBridge	163:e59c8e839560	261	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	262	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
AnnaBridge	163:e59c8e839560	263
AnnaBridge	163:e59c8e839560	264	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
AnnaBridge	163:e59c8e839560	265	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
AnnaBridge	163:e59c8e839560	266
AnnaBridge	163:e59c8e839560	267	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	163:e59c8e839560	268	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	269
AnnaBridge	163:e59c8e839560	270	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	163:e59c8e839560	271	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	163:e59c8e839560	272
AnnaBridge	163:e59c8e839560	273	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	274	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	275
AnnaBridge	163:e59c8e839560	276	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	277	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	163:e59c8e839560	278
AnnaBridge	163:e59c8e839560	279	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
AnnaBridge	163:e59c8e839560	280	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
AnnaBridge	163:e59c8e839560	281
AnnaBridge	163:e59c8e839560	282	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
AnnaBridge	163:e59c8e839560	283	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
AnnaBridge	163:e59c8e839560	284
AnnaBridge	163:e59c8e839560	285	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	286	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
AnnaBridge	163:e59c8e839560	287	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
AnnaBridge	163:e59c8e839560	288
AnnaBridge	163:e59c8e839560	289	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
AnnaBridge	163:e59c8e839560	290	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
AnnaBridge	163:e59c8e839560	291
AnnaBridge	163:e59c8e839560	292	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
AnnaBridge	163:e59c8e839560	293	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	294
AnnaBridge	163:e59c8e839560	295	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	296	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
AnnaBridge	163:e59c8e839560	297
AnnaBridge	163:e59c8e839560	298	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	299	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
AnnaBridge	163:e59c8e839560	300	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	301
AnnaBridge	163:e59c8e839560	302	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
AnnaBridge	163:e59c8e839560	303	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	304
AnnaBridge	163:e59c8e839560	305	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	163:e59c8e839560	306	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	163:e59c8e839560	307	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	308	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	309
AnnaBridge	163:e59c8e839560	310	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	311
AnnaBridge	163:e59c8e839560	312	/**
AnnaBridge	163:e59c8e839560	313	* @brief PLLI2S Clock structure definition
AnnaBridge	163:e59c8e839560	314	*/
AnnaBridge	163:e59c8e839560	315	typedef struct
AnnaBridge	163:e59c8e839560	316	{
AnnaBridge	163:e59c8e839560	317	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	318	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	319	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	320
AnnaBridge	163:e59c8e839560	321	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	163:e59c8e839560	322	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	323	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	324
AnnaBridge	163:e59c8e839560	325	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	326	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	327	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	328	}RCC_PLLI2SInitTypeDef;
AnnaBridge	163:e59c8e839560	329
AnnaBridge	163:e59c8e839560	330	/**
AnnaBridge	163:e59c8e839560	331	* @brief PLLSAI Clock structure definition
AnnaBridge	163:e59c8e839560	332	*/
AnnaBridge	163:e59c8e839560	333	typedef struct
AnnaBridge	163:e59c8e839560	334	{
AnnaBridge	163:e59c8e839560	335	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	336	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	337	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge	163:e59c8e839560	338	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	339	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
AnnaBridge	163:e59c8e839560	340	This parameter is only available in STM32F469xx/STM32F479xx devices.
AnnaBridge	163:e59c8e839560	341	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
AnnaBridge	163:e59c8e839560	342	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	343
AnnaBridge	163:e59c8e839560	344	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	345	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	346	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge	163:e59c8e839560	347
AnnaBridge	163:e59c8e839560	348	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
AnnaBridge	163:e59c8e839560	349	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	350	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
AnnaBridge	163:e59c8e839560	351
AnnaBridge	163:e59c8e839560	352	}RCC_PLLSAIInitTypeDef;
AnnaBridge	163:e59c8e839560	353
AnnaBridge	163:e59c8e839560	354	/**
AnnaBridge	163:e59c8e839560	355	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	356	*/
AnnaBridge	163:e59c8e839560	357	typedef struct
AnnaBridge	163:e59c8e839560	358	{
AnnaBridge	163:e59c8e839560	359	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	360	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	361
AnnaBridge	163:e59c8e839560	362	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	163:e59c8e839560	363	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	364
AnnaBridge	163:e59c8e839560	365	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge	163:e59c8e839560	366	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge	163:e59c8e839560	367
AnnaBridge	163:e59c8e839560	368	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	369	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	370	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	371
AnnaBridge	163:e59c8e839560	372	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	373	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	163:e59c8e839560	374	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	163:e59c8e839560	375
AnnaBridge	163:e59c8e839560	376	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
AnnaBridge	163:e59c8e839560	377	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
AnnaBridge	163:e59c8e839560	378
AnnaBridge	163:e59c8e839560	379	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
AnnaBridge	163:e59c8e839560	380	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	381
AnnaBridge	163:e59c8e839560	382	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge	163:e59c8e839560	383	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	163:e59c8e839560	384	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	385	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	386	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	163:e59c8e839560	387
AnnaBridge	163:e59c8e839560	388	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	163:e59c8e839560	389	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	163:e59c8e839560	390	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	391	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	392
AnnaBridge	163:e59c8e839560	393	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	394
AnnaBridge	163:e59c8e839560	395	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	163:e59c8e839560	396	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	397	/**
AnnaBridge	163:e59c8e839560	398	* @brief PLLI2S Clock structure definition
AnnaBridge	163:e59c8e839560	399	*/
AnnaBridge	163:e59c8e839560	400	typedef struct
AnnaBridge	163:e59c8e839560	401	{
AnnaBridge	163:e59c8e839560	402	#if defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	403	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
AnnaBridge	163:e59c8e839560	404	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
AnnaBridge	163:e59c8e839560	405	#endif /* STM32F411xE */
AnnaBridge	163:e59c8e839560	406
AnnaBridge	163:e59c8e839560	407	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	408	This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	163:e59c8e839560	409	Except for STM32F411xE devices where the Min_Data = 192.
AnnaBridge	163:e59c8e839560	410	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	411
AnnaBridge	163:e59c8e839560	412	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	163:e59c8e839560	413	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	414	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	415
AnnaBridge	163:e59c8e839560	416	}RCC_PLLI2SInitTypeDef;
AnnaBridge	163:e59c8e839560	417
AnnaBridge	163:e59c8e839560	418	/**
AnnaBridge	163:e59c8e839560	419	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	420	*/
AnnaBridge	163:e59c8e839560	421	typedef struct
AnnaBridge	163:e59c8e839560	422	{
AnnaBridge	163:e59c8e839560	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	425
AnnaBridge	163:e59c8e839560	426	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	163:e59c8e839560	427	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	163:e59c8e839560	428
AnnaBridge	163:e59c8e839560	429	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
AnnaBridge	163:e59c8e839560	430	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	431	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	432	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	163:e59c8e839560	433	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	163:e59c8e839560	434	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	163:e59c8e839560	435	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	436	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	163:e59c8e839560	437	/**
AnnaBridge	163:e59c8e839560	438	* @}
AnnaBridge	163:e59c8e839560	439	*/
AnnaBridge	163:e59c8e839560	440
AnnaBridge	163:e59c8e839560	441	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	442	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	163:e59c8e839560	443	* @{
AnnaBridge	163:e59c8e839560	444	*/
AnnaBridge	163:e59c8e839560	445
AnnaBridge	163:e59c8e839560	446	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
AnnaBridge	163:e59c8e839560	447	* @{
AnnaBridge	163:e59c8e839560	448	*/
AnnaBridge	163:e59c8e839560	449	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
AnnaBridge	163:e59c8e839560	450	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	451	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	452	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	163:e59c8e839560	453	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	163:e59c8e839560	454	#define RCC_PERIPHCLK_TIM 0x00000004U
AnnaBridge	163:e59c8e839560	455	#define RCC_PERIPHCLK_RTC 0x00000008U
AnnaBridge	163:e59c8e839560	456	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
AnnaBridge	163:e59c8e839560	457	#define RCC_PERIPHCLK_CLK48 0x00000020U
AnnaBridge	163:e59c8e839560	458	#define RCC_PERIPHCLK_SDIO 0x00000040U
AnnaBridge	163:e59c8e839560	459	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
AnnaBridge	163:e59c8e839560	460	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
AnnaBridge	163:e59c8e839560	461	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
AnnaBridge	163:e59c8e839560	462	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	463	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	464	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
AnnaBridge	163:e59c8e839560	465	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
AnnaBridge	163:e59c8e839560	466	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
AnnaBridge	163:e59c8e839560	467	#define RCC_PERIPHCLK_SAIA 0x00002000U
AnnaBridge	163:e59c8e839560	468	#define RCC_PERIPHCLK_SAIB 0x00004000U
AnnaBridge	163:e59c8e839560	469	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	470	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	471
AnnaBridge	163:e59c8e839560	472	/------------------- Peripheral Clock source for STM32F410xx ----------------/
AnnaBridge	163:e59c8e839560	473	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	474	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	163:e59c8e839560	475	#define RCC_PERIPHCLK_TIM 0x00000002U
AnnaBridge	163:e59c8e839560	476	#define RCC_PERIPHCLK_RTC 0x00000004U
AnnaBridge	163:e59c8e839560	477	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
AnnaBridge	163:e59c8e839560	478	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
AnnaBridge	163:e59c8e839560	479	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	480	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	481
AnnaBridge	163:e59c8e839560	482	/------------------- Peripheral Clock source for STM32F446xx ----------------/
AnnaBridge	163:e59c8e839560	483	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	484	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	163:e59c8e839560	485	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	163:e59c8e839560	486	#define RCC_PERIPHCLK_SAI1 0x00000004U
AnnaBridge	163:e59c8e839560	487	#define RCC_PERIPHCLK_SAI2 0x00000008U
AnnaBridge	163:e59c8e839560	488	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	163:e59c8e839560	489	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	163:e59c8e839560	490	#define RCC_PERIPHCLK_CEC 0x00000040U
AnnaBridge	163:e59c8e839560	491	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
AnnaBridge	163:e59c8e839560	492	#define RCC_PERIPHCLK_CLK48 0x00000100U
AnnaBridge	163:e59c8e839560	493	#define RCC_PERIPHCLK_SDIO 0x00000200U
AnnaBridge	163:e59c8e839560	494	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
AnnaBridge	163:e59c8e839560	495	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
AnnaBridge	163:e59c8e839560	496	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	497	/-----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	498
AnnaBridge	163:e59c8e839560	499	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
AnnaBridge	163:e59c8e839560	500	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	501	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	163:e59c8e839560	502	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	163:e59c8e839560	503	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	163:e59c8e839560	504	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	163:e59c8e839560	505	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	163:e59c8e839560	506	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	163:e59c8e839560	507	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
AnnaBridge	163:e59c8e839560	508	#define RCC_PERIPHCLK_CLK48 0x00000080U
AnnaBridge	163:e59c8e839560	509	#define RCC_PERIPHCLK_SDIO 0x00000100U
AnnaBridge	163:e59c8e839560	510	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	511	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	512
AnnaBridge	163:e59c8e839560	513	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
AnnaBridge	163:e59c8e839560	514	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	163:e59c8e839560	515	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	163:e59c8e839560	516	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	163:e59c8e839560	517	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	163:e59c8e839560	518	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	163:e59c8e839560	519	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	163:e59c8e839560	520	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	163:e59c8e839560	521	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
AnnaBridge	163:e59c8e839560	522	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	163:e59c8e839560	523	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	524
AnnaBridge	163:e59c8e839560	525	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
AnnaBridge	163:e59c8e839560	526	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
AnnaBridge	163:e59c8e839560	527	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	528	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	163:e59c8e839560	529	#define RCC_PERIPHCLK_RTC 0x00000002U
AnnaBridge	163:e59c8e839560	530	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
AnnaBridge	163:e59c8e839560	531	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	163:e59c8e839560	532	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	533	#define RCC_PERIPHCLK_TIM 0x00000008U
AnnaBridge	163:e59c8e839560	534	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	163:e59c8e839560	535	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	536	/**
AnnaBridge	163:e59c8e839560	537	* @}
AnnaBridge	163:e59c8e839560	538	*/
AnnaBridge	163:e59c8e839560	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	540	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	541	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
AnnaBridge	163:e59c8e839560	542	defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	543	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
AnnaBridge	163:e59c8e839560	544	* @{
AnnaBridge	163:e59c8e839560	545	*/
AnnaBridge	163:e59c8e839560	546	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	163:e59c8e839560	547	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
AnnaBridge	163:e59c8e839560	548	/**
AnnaBridge	163:e59c8e839560	549	* @}
AnnaBridge	163:e59c8e839560	550	*/
AnnaBridge	163:e59c8e839560	551	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	552	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	553
AnnaBridge	163:e59c8e839560	554	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
AnnaBridge	163:e59c8e839560	555	* @{
AnnaBridge	163:e59c8e839560	556	*/
AnnaBridge	163:e59c8e839560	557	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	163:e59c8e839560	558	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	559	#define RCC_PLLSAIDIVR_2 0x00000000U
AnnaBridge	163:e59c8e839560	560	#define RCC_PLLSAIDIVR_4 0x00010000U
AnnaBridge	163:e59c8e839560	561	#define RCC_PLLSAIDIVR_8 0x00020000U
AnnaBridge	163:e59c8e839560	562	#define RCC_PLLSAIDIVR_16 0x00030000U
AnnaBridge	163:e59c8e839560	563	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	564	/**
AnnaBridge	163:e59c8e839560	565	* @}
AnnaBridge	163:e59c8e839560	566	*/
AnnaBridge	163:e59c8e839560	567
AnnaBridge	163:e59c8e839560	568	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
AnnaBridge	163:e59c8e839560	569	* @{
AnnaBridge	163:e59c8e839560	570	*/
AnnaBridge	163:e59c8e839560	571	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	572	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	163:e59c8e839560	573	#define RCC_PLLI2SP_DIV2 0x00000002U
AnnaBridge	163:e59c8e839560	574	#define RCC_PLLI2SP_DIV4 0x00000004U
AnnaBridge	163:e59c8e839560	575	#define RCC_PLLI2SP_DIV6 0x00000006U
AnnaBridge	163:e59c8e839560	576	#define RCC_PLLI2SP_DIV8 0x00000008U
AnnaBridge	163:e59c8e839560	577	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	578	/**
AnnaBridge	163:e59c8e839560	579	* @}
AnnaBridge	163:e59c8e839560	580	*/
AnnaBridge	163:e59c8e839560	581
AnnaBridge	163:e59c8e839560	582	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
AnnaBridge	163:e59c8e839560	583	* @{
AnnaBridge	163:e59c8e839560	584	*/
AnnaBridge	163:e59c8e839560	585	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	586	#define RCC_PLLSAIP_DIV2 0x00000002U
AnnaBridge	163:e59c8e839560	587	#define RCC_PLLSAIP_DIV4 0x00000004U
AnnaBridge	163:e59c8e839560	588	#define RCC_PLLSAIP_DIV6 0x00000006U
AnnaBridge	163:e59c8e839560	589	#define RCC_PLLSAIP_DIV8 0x00000008U
AnnaBridge	163:e59c8e839560	590	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	591	/**
AnnaBridge	163:e59c8e839560	592	* @}
AnnaBridge	163:e59c8e839560	593	*/
AnnaBridge	163:e59c8e839560	594
AnnaBridge	163:e59c8e839560	595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	596	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
AnnaBridge	163:e59c8e839560	597	* @{
AnnaBridge	163:e59c8e839560	598	*/
AnnaBridge	163:e59c8e839560	599	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	163:e59c8e839560	600	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
AnnaBridge	163:e59c8e839560	601	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
AnnaBridge	163:e59c8e839560	602	/**
AnnaBridge	163:e59c8e839560	603	* @}
AnnaBridge	163:e59c8e839560	604	*/
AnnaBridge	163:e59c8e839560	605
AnnaBridge	163:e59c8e839560	606	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
AnnaBridge	163:e59c8e839560	607	* @{
AnnaBridge	163:e59c8e839560	608	*/
AnnaBridge	163:e59c8e839560	609	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	163:e59c8e839560	610	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
AnnaBridge	163:e59c8e839560	611	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
AnnaBridge	163:e59c8e839560	612	/**
AnnaBridge	163:e59c8e839560	613	* @}
AnnaBridge	163:e59c8e839560	614	*/
AnnaBridge	163:e59c8e839560	615	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	616
AnnaBridge	163:e59c8e839560	617	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	618	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	163:e59c8e839560	619	* @{
AnnaBridge	163:e59c8e839560	620	*/
AnnaBridge	163:e59c8e839560	621	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	163:e59c8e839560	622	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
AnnaBridge	163:e59c8e839560	623	/**
AnnaBridge	163:e59c8e839560	624	* @}
AnnaBridge	163:e59c8e839560	625	*/
AnnaBridge	163:e59c8e839560	626
AnnaBridge	163:e59c8e839560	627	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	163:e59c8e839560	628	* @{
AnnaBridge	163:e59c8e839560	629	*/
AnnaBridge	163:e59c8e839560	630	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	163:e59c8e839560	631	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
AnnaBridge	163:e59c8e839560	632	/**
AnnaBridge	163:e59c8e839560	633	* @}
AnnaBridge	163:e59c8e839560	634	*/
AnnaBridge	163:e59c8e839560	635
AnnaBridge	163:e59c8e839560	636	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
AnnaBridge	163:e59c8e839560	637	* @{
AnnaBridge	163:e59c8e839560	638	*/
AnnaBridge	163:e59c8e839560	639	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
AnnaBridge	163:e59c8e839560	640	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
AnnaBridge	163:e59c8e839560	641	/**
AnnaBridge	163:e59c8e839560	642	* @}
AnnaBridge	163:e59c8e839560	643	*/
AnnaBridge	163:e59c8e839560	644	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	645
AnnaBridge	163:e59c8e839560	646	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	647	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
AnnaBridge	163:e59c8e839560	648	* @{
AnnaBridge	163:e59c8e839560	649	*/
AnnaBridge	163:e59c8e839560	650	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	163:e59c8e839560	651	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
AnnaBridge	163:e59c8e839560	652	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
AnnaBridge	163:e59c8e839560	653	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
AnnaBridge	163:e59c8e839560	654	/**
AnnaBridge	163:e59c8e839560	655	* @}
AnnaBridge	163:e59c8e839560	656	*/
AnnaBridge	163:e59c8e839560	657
AnnaBridge	163:e59c8e839560	658	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
AnnaBridge	163:e59c8e839560	659	* @{
AnnaBridge	163:e59c8e839560	660	*/
AnnaBridge	163:e59c8e839560	661	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	163:e59c8e839560	662	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
AnnaBridge	163:e59c8e839560	663	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
AnnaBridge	163:e59c8e839560	664	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
AnnaBridge	163:e59c8e839560	665	/**
AnnaBridge	163:e59c8e839560	666	* @}
AnnaBridge	163:e59c8e839560	667	*/
AnnaBridge	163:e59c8e839560	668
AnnaBridge	163:e59c8e839560	669	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
AnnaBridge	163:e59c8e839560	670	* @{
AnnaBridge	163:e59c8e839560	671	*/
AnnaBridge	163:e59c8e839560	672	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	163:e59c8e839560	673	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
AnnaBridge	163:e59c8e839560	674	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
AnnaBridge	163:e59c8e839560	675	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
AnnaBridge	163:e59c8e839560	676	/**
AnnaBridge	163:e59c8e839560	677	* @}
AnnaBridge	163:e59c8e839560	678	*/
AnnaBridge	163:e59c8e839560	679
AnnaBridge	163:e59c8e839560	680	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
AnnaBridge	163:e59c8e839560	681	* @{
AnnaBridge	163:e59c8e839560	682	*/
AnnaBridge	163:e59c8e839560	683	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	163:e59c8e839560	684	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
AnnaBridge	163:e59c8e839560	685	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
AnnaBridge	163:e59c8e839560	686	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
AnnaBridge	163:e59c8e839560	687	/**
AnnaBridge	163:e59c8e839560	688	* @}
AnnaBridge	163:e59c8e839560	689	*/
AnnaBridge	163:e59c8e839560	690
AnnaBridge	163:e59c8e839560	691	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	163:e59c8e839560	692	* @{
AnnaBridge	163:e59c8e839560	693	*/
AnnaBridge	163:e59c8e839560	694	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	163:e59c8e839560	695	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	163:e59c8e839560	696	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	163:e59c8e839560	697	/**
AnnaBridge	163:e59c8e839560	698	* @}
AnnaBridge	163:e59c8e839560	699	*/
AnnaBridge	163:e59c8e839560	700
AnnaBridge	163:e59c8e839560	701	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
AnnaBridge	163:e59c8e839560	702	* @{
AnnaBridge	163:e59c8e839560	703	*/
AnnaBridge	163:e59c8e839560	704	#define RCC_CECCLKSOURCE_HSI 0x00000000U
AnnaBridge	163:e59c8e839560	705	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
AnnaBridge	163:e59c8e839560	706	/**
AnnaBridge	163:e59c8e839560	707	* @}
AnnaBridge	163:e59c8e839560	708	*/
AnnaBridge	163:e59c8e839560	709
AnnaBridge	163:e59c8e839560	710	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	163:e59c8e839560	711	* @{
AnnaBridge	163:e59c8e839560	712	*/
AnnaBridge	163:e59c8e839560	713	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	163:e59c8e839560	714	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	163:e59c8e839560	715	/**
AnnaBridge	163:e59c8e839560	716	* @}
AnnaBridge	163:e59c8e839560	717	*/
AnnaBridge	163:e59c8e839560	718
AnnaBridge	163:e59c8e839560	719	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	163:e59c8e839560	720	* @{
AnnaBridge	163:e59c8e839560	721	*/
AnnaBridge	163:e59c8e839560	722	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	163:e59c8e839560	723	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	163:e59c8e839560	724	/**
AnnaBridge	163:e59c8e839560	725	* @}
AnnaBridge	163:e59c8e839560	726	*/
AnnaBridge	163:e59c8e839560	727
AnnaBridge	163:e59c8e839560	728	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
AnnaBridge	163:e59c8e839560	729	* @{
AnnaBridge	163:e59c8e839560	730	*/
AnnaBridge	163:e59c8e839560	731	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
AnnaBridge	163:e59c8e839560	732	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
AnnaBridge	163:e59c8e839560	733	/**
AnnaBridge	163:e59c8e839560	734	* @}
AnnaBridge	163:e59c8e839560	735	*/
AnnaBridge	163:e59c8e839560	736
AnnaBridge	163:e59c8e839560	737	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	738
AnnaBridge	163:e59c8e839560	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
AnnaBridge	163:e59c8e839560	741	* @{
AnnaBridge	163:e59c8e839560	742	*/
AnnaBridge	163:e59c8e839560	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	163:e59c8e839560	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
AnnaBridge	163:e59c8e839560	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	163:e59c8e839560	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	163:e59c8e839560	747	/**
AnnaBridge	163:e59c8e839560	748	* @}
AnnaBridge	163:e59c8e839560	749	*/
AnnaBridge	163:e59c8e839560	750
AnnaBridge	163:e59c8e839560	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
AnnaBridge	163:e59c8e839560	752	* @{
AnnaBridge	163:e59c8e839560	753	*/
AnnaBridge	163:e59c8e839560	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	163:e59c8e839560	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
AnnaBridge	163:e59c8e839560	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	163:e59c8e839560	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	163:e59c8e839560	758	/**
AnnaBridge	163:e59c8e839560	759	* @}
AnnaBridge	163:e59c8e839560	760	*/
AnnaBridge	163:e59c8e839560	761
AnnaBridge	163:e59c8e839560	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge	163:e59c8e839560	763	* @{
AnnaBridge	163:e59c8e839560	764	*/
AnnaBridge	163:e59c8e839560	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	163:e59c8e839560	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
AnnaBridge	163:e59c8e839560	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	163:e59c8e839560	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	163:e59c8e839560	769	/**
AnnaBridge	163:e59c8e839560	770	* @}
AnnaBridge	163:e59c8e839560	771	*/
AnnaBridge	163:e59c8e839560	772
AnnaBridge	163:e59c8e839560	773
AnnaBridge	163:e59c8e839560	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
AnnaBridge	163:e59c8e839560	775	* @{
AnnaBridge	163:e59c8e839560	776	*/
AnnaBridge	163:e59c8e839560	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	163:e59c8e839560	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
AnnaBridge	163:e59c8e839560	779	/**
AnnaBridge	163:e59c8e839560	780	* @}
AnnaBridge	163:e59c8e839560	781	*/
AnnaBridge	163:e59c8e839560	782
AnnaBridge	163:e59c8e839560	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
AnnaBridge	163:e59c8e839560	784	* @{
AnnaBridge	163:e59c8e839560	785	*/
AnnaBridge	163:e59c8e839560	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	163:e59c8e839560	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
AnnaBridge	163:e59c8e839560	788	/**
AnnaBridge	163:e59c8e839560	789	* @}
AnnaBridge	163:e59c8e839560	790	*/
AnnaBridge	163:e59c8e839560	791
AnnaBridge	163:e59c8e839560	792	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	793
AnnaBridge	163:e59c8e839560	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
AnnaBridge	163:e59c8e839560	796	* @{
AnnaBridge	163:e59c8e839560	797	*/
AnnaBridge	163:e59c8e839560	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
AnnaBridge	163:e59c8e839560	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
AnnaBridge	163:e59c8e839560	800	/**
AnnaBridge	163:e59c8e839560	801	* @}
AnnaBridge	163:e59c8e839560	802	*/
AnnaBridge	163:e59c8e839560	803
AnnaBridge	163:e59c8e839560	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
AnnaBridge	163:e59c8e839560	805	* @{
AnnaBridge	163:e59c8e839560	806	*/
AnnaBridge	163:e59c8e839560	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	163:e59c8e839560	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
AnnaBridge	163:e59c8e839560	809	/**
AnnaBridge	163:e59c8e839560	810	* @}
AnnaBridge	163:e59c8e839560	811	*/
AnnaBridge	163:e59c8e839560	812
AnnaBridge	163:e59c8e839560	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
AnnaBridge	163:e59c8e839560	814	* @{
AnnaBridge	163:e59c8e839560	815	*/
AnnaBridge	163:e59c8e839560	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	163:e59c8e839560	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
AnnaBridge	163:e59c8e839560	818	/**
AnnaBridge	163:e59c8e839560	819	* @}
AnnaBridge	163:e59c8e839560	820	*/
AnnaBridge	163:e59c8e839560	821
AnnaBridge	163:e59c8e839560	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
AnnaBridge	163:e59c8e839560	823	* @{
AnnaBridge	163:e59c8e839560	824	*/
AnnaBridge	163:e59c8e839560	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	163:e59c8e839560	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
AnnaBridge	163:e59c8e839560	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
AnnaBridge	163:e59c8e839560	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
AnnaBridge	163:e59c8e839560	829	/**
AnnaBridge	163:e59c8e839560	830	* @}
AnnaBridge	163:e59c8e839560	831	*/
AnnaBridge	163:e59c8e839560	832
AnnaBridge	163:e59c8e839560	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
AnnaBridge	163:e59c8e839560	834	* @{
AnnaBridge	163:e59c8e839560	835	*/
AnnaBridge	163:e59c8e839560	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	163:e59c8e839560	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
AnnaBridge	163:e59c8e839560	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
AnnaBridge	163:e59c8e839560	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
AnnaBridge	163:e59c8e839560	840	/**
AnnaBridge	163:e59c8e839560	841	* @}
AnnaBridge	163:e59c8e839560	842	*/
AnnaBridge	163:e59c8e839560	843
AnnaBridge	163:e59c8e839560	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	163:e59c8e839560	845	* @{
AnnaBridge	163:e59c8e839560	846	*/
AnnaBridge	163:e59c8e839560	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	163:e59c8e839560	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	163:e59c8e839560	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	163:e59c8e839560	850	/**
AnnaBridge	163:e59c8e839560	851	* @}
AnnaBridge	163:e59c8e839560	852	*/
AnnaBridge	163:e59c8e839560	853
AnnaBridge	163:e59c8e839560	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	163:e59c8e839560	855	* @{
AnnaBridge	163:e59c8e839560	856	*/
AnnaBridge	163:e59c8e839560	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	163:e59c8e839560	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	163:e59c8e839560	859	/**
AnnaBridge	163:e59c8e839560	860	* @}
AnnaBridge	163:e59c8e839560	861	*/
AnnaBridge	163:e59c8e839560	862
AnnaBridge	163:e59c8e839560	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	163:e59c8e839560	864	* @{
AnnaBridge	163:e59c8e839560	865	*/
AnnaBridge	163:e59c8e839560	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	163:e59c8e839560	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	163:e59c8e839560	868	/**
AnnaBridge	163:e59c8e839560	869	* @}
AnnaBridge	163:e59c8e839560	870	*/
AnnaBridge	163:e59c8e839560	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	872
AnnaBridge	163:e59c8e839560	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	874
AnnaBridge	163:e59c8e839560	875	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
AnnaBridge	163:e59c8e839560	876	* @{
AnnaBridge	163:e59c8e839560	877	*/
AnnaBridge	163:e59c8e839560	878	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
AnnaBridge	163:e59c8e839560	879	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
AnnaBridge	163:e59c8e839560	880	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
AnnaBridge	163:e59c8e839560	881	/**
AnnaBridge	163:e59c8e839560	882	* @}
AnnaBridge	163:e59c8e839560	883	*/
AnnaBridge	163:e59c8e839560	884
AnnaBridge	163:e59c8e839560	885	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	163:e59c8e839560	886	* @{
AnnaBridge	163:e59c8e839560	887	*/
AnnaBridge	163:e59c8e839560	888	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	163:e59c8e839560	889	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	163:e59c8e839560	890	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	163:e59c8e839560	891	/**
AnnaBridge	163:e59c8e839560	892	* @}
AnnaBridge	163:e59c8e839560	893	*/
AnnaBridge	163:e59c8e839560	894
AnnaBridge	163:e59c8e839560	895	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge	163:e59c8e839560	896	* @{
AnnaBridge	163:e59c8e839560	897	*/
AnnaBridge	163:e59c8e839560	898	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	163:e59c8e839560	899	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
AnnaBridge	163:e59c8e839560	900	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	163:e59c8e839560	901	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	163:e59c8e839560	902	/**
AnnaBridge	163:e59c8e839560	903	* @}
AnnaBridge	163:e59c8e839560	904	*/
AnnaBridge	163:e59c8e839560	905	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	906
AnnaBridge	163:e59c8e839560	907	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	908	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
AnnaBridge	163:e59c8e839560	909	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	163:e59c8e839560	910	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	163:e59c8e839560	911	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	912	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
AnnaBridge	163:e59c8e839560	913	* @{
AnnaBridge	163:e59c8e839560	914	*/
AnnaBridge	163:e59c8e839560	915	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
AnnaBridge	163:e59c8e839560	916	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
AnnaBridge	163:e59c8e839560	917	/**
AnnaBridge	163:e59c8e839560	918	* @}
AnnaBridge	163:e59c8e839560	919	*/
AnnaBridge	163:e59c8e839560	920	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
AnnaBridge	163:e59c8e839560	921	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	163:e59c8e839560	922	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	923
AnnaBridge	163:e59c8e839560	924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
AnnaBridge	163:e59c8e839560	925	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	163:e59c8e839560	926	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	163:e59c8e839560	927	defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	928	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
AnnaBridge	163:e59c8e839560	929	* @{
AnnaBridge	163:e59c8e839560	930	*/
AnnaBridge	163:e59c8e839560	931	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
AnnaBridge	163:e59c8e839560	932	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
AnnaBridge	163:e59c8e839560	933	/**
AnnaBridge	163:e59c8e839560	934	* @}
AnnaBridge	163:e59c8e839560	935	*/
AnnaBridge	163:e59c8e839560	936	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
AnnaBridge	163:e59c8e839560	937	STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	938
AnnaBridge	163:e59c8e839560	939	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	940	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	941	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	163:e59c8e839560	942	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	943	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	944	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
AnnaBridge	163:e59c8e839560	945	* @{
AnnaBridge	163:e59c8e839560	946	*/
AnnaBridge	163:e59c8e839560	947	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
AnnaBridge	163:e59c8e839560	948	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
AnnaBridge	163:e59c8e839560	949	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge	163:e59c8e839560	950	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge	163:e59c8e839560	951	/**
AnnaBridge	163:e59c8e839560	952	* @}
AnnaBridge	163:e59c8e839560	953	*/
AnnaBridge	163:e59c8e839560	954	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	955	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	163:e59c8e839560	956	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	163:e59c8e839560	957
AnnaBridge	163:e59c8e839560	958	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	959	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
AnnaBridge	163:e59c8e839560	960	* @{
AnnaBridge	163:e59c8e839560	961	*/
AnnaBridge	163:e59c8e839560	962	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
AnnaBridge	163:e59c8e839560	963	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
AnnaBridge	163:e59c8e839560	964	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge	163:e59c8e839560	965	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge	163:e59c8e839560	966	/**
AnnaBridge	163:e59c8e839560	967	* @}
AnnaBridge	163:e59c8e839560	968	*/
AnnaBridge	163:e59c8e839560	969	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	970
AnnaBridge	163:e59c8e839560	971	/**
AnnaBridge	163:e59c8e839560	972	* @}
AnnaBridge	163:e59c8e839560	973	*/
AnnaBridge	163:e59c8e839560	974
AnnaBridge	163:e59c8e839560	975	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	976	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	163:e59c8e839560	977	* @{
AnnaBridge	163:e59c8e839560	978	*/
AnnaBridge	163:e59c8e839560	979	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
AnnaBridge	163:e59c8e839560	980	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	981	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	982	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	983	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	984	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	985	* using it.
AnnaBridge	163:e59c8e839560	986	* @{
AnnaBridge	163:e59c8e839560	987	*/
AnnaBridge	163:e59c8e839560	988	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	989	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	990	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	991	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	992	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	993	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	994	} while(0U)
AnnaBridge	163:e59c8e839560	995	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	996	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	997	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	998	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	999	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	1000	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1001	} while(0U)
AnnaBridge	163:e59c8e839560	1002	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1003	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1004	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	1005	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1006	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	1007	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1008	} while(0U)
AnnaBridge	163:e59c8e839560	1009	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1010	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1011	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	1012	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1013	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	1014	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1015	} while(0U)
AnnaBridge	163:e59c8e839560	1016	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1017	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1018	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1019	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1020	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1021	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1022	} while(0U)
AnnaBridge	163:e59c8e839560	1023	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1024	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1025	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	163:e59c8e839560	1026	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1027	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	163:e59c8e839560	1028	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1029	} while(0U)
AnnaBridge	163:e59c8e839560	1030	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1031	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1032	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	1033	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1034	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	1035	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1036	} while(0U)
AnnaBridge	163:e59c8e839560	1037	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1038	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1039	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	1040	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1041	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	1042	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1043	} while(0U)
AnnaBridge	163:e59c8e839560	1044	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1045	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1046	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	163:e59c8e839560	1047	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1048	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	163:e59c8e839560	1049	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1050	} while(0U)
AnnaBridge	163:e59c8e839560	1051	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1052	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1053	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	163:e59c8e839560	1054	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1055	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	163:e59c8e839560	1056	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1057	} while(0U)
AnnaBridge	163:e59c8e839560	1058	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1059	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1060	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	163:e59c8e839560	1061	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1062	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	163:e59c8e839560	1063	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1064	} while(0U)
AnnaBridge	163:e59c8e839560	1065	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1066	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1067	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	163:e59c8e839560	1068	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1069	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	163:e59c8e839560	1070	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1071	} while(0U)
AnnaBridge	163:e59c8e839560	1072	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1073	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1074	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	163:e59c8e839560	1075	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1076	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	163:e59c8e839560	1077	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1078	} while(0U)
AnnaBridge	163:e59c8e839560	1079	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1080	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1081	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	163:e59c8e839560	1082	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1083	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	163:e59c8e839560	1084	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1085	} while(0U)
AnnaBridge	163:e59c8e839560	1086	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1087	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1088	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	163:e59c8e839560	1089	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1090	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	163:e59c8e839560	1091	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1092	} while(0U)
AnnaBridge	163:e59c8e839560	1093	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1094	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1095	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	1096	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1097	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	1098	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1099	} while(0U)
AnnaBridge	163:e59c8e839560	1100	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1101	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1102	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	1103	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1104	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	1105	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1106	} while(0U)
AnnaBridge	163:e59c8e839560	1107	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	1108	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	1109	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	163:e59c8e839560	1110	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	163:e59c8e839560	1111	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	163:e59c8e839560	1112	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
AnnaBridge	163:e59c8e839560	1113	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
AnnaBridge	163:e59c8e839560	1114	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
AnnaBridge	163:e59c8e839560	1115	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge	163:e59c8e839560	1116	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge	163:e59c8e839560	1117	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge	163:e59c8e839560	1118	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge	163:e59c8e839560	1119	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	163:e59c8e839560	1120	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	163:e59c8e839560	1121	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	163:e59c8e839560	1122	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	163:e59c8e839560	1123	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	1124
AnnaBridge	163:e59c8e839560	1125	/**
AnnaBridge	163:e59c8e839560	1126	* @brief Enable ETHERNET clock.
AnnaBridge	163:e59c8e839560	1127	*/
AnnaBridge	163:e59c8e839560	1128	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1129	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	1130	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	1131	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	1132	} while(0U)
AnnaBridge	163:e59c8e839560	1133	/**
AnnaBridge	163:e59c8e839560	1134	* @brief Disable ETHERNET clock.
AnnaBridge	163:e59c8e839560	1135	*/
AnnaBridge	163:e59c8e839560	1136	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	163:e59c8e839560	1137	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	1138	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	1139	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	1140	} while(0U)
AnnaBridge	163:e59c8e839560	1141	/**
AnnaBridge	163:e59c8e839560	1142	* @}
AnnaBridge	163:e59c8e839560	1143	*/
AnnaBridge	163:e59c8e839560	1144
AnnaBridge	163:e59c8e839560	1145	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	1146	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	1147	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1148	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1149	* using it.
AnnaBridge	163:e59c8e839560	1150	* @{
AnnaBridge	163:e59c8e839560	1151	*/
AnnaBridge	163:e59c8e839560	1152	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	1153	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	1154	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	163:e59c8e839560	1155	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	163:e59c8e839560	1156	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	163:e59c8e839560	1157	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
AnnaBridge	163:e59c8e839560	1158	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
AnnaBridge	163:e59c8e839560	1159	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
AnnaBridge	163:e59c8e839560	1160	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge	163:e59c8e839560	1161	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge	163:e59c8e839560	1162	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge	163:e59c8e839560	1163	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge	163:e59c8e839560	1164	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	163:e59c8e839560	1165	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	1166	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	1167	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	1168	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	1169	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge	163:e59c8e839560	1170	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge	163:e59c8e839560	1171	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge	163:e59c8e839560	1172
AnnaBridge	163:e59c8e839560	1173	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	1174	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	1175	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	163:e59c8e839560	1176	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	163:e59c8e839560	1177	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	163:e59c8e839560	1178	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
AnnaBridge	163:e59c8e839560	1179	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
AnnaBridge	163:e59c8e839560	1180	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
AnnaBridge	163:e59c8e839560	1181	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge	163:e59c8e839560	1182	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge	163:e59c8e839560	1183	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge	163:e59c8e839560	1184	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge	163:e59c8e839560	1185	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	163:e59c8e839560	1186	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	163:e59c8e839560	1187	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	1188	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	1189	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	1190	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge	163:e59c8e839560	1191	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge	163:e59c8e839560	1192	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
AnnaBridge	163:e59c8e839560	1193	/**
AnnaBridge	163:e59c8e839560	1194	* @}
AnnaBridge	163:e59c8e839560	1195	*/
AnnaBridge	163:e59c8e839560	1196
AnnaBridge	163:e59c8e839560	1197	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	1198	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	1199	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1200	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1201	* using it.
AnnaBridge	163:e59c8e839560	1202	* @{
AnnaBridge	163:e59c8e839560	1203	*/
AnnaBridge	163:e59c8e839560	1204	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1205	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1206	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	1207	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1208	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	1209	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1210	} while(0U)
AnnaBridge	163:e59c8e839560	1211	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	163:e59c8e839560	1212
AnnaBridge	163:e59c8e839560	1213	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1214	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1215	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1216	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	163:e59c8e839560	1217	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1218	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	163:e59c8e839560	1219	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1220	} while(0U)
AnnaBridge	163:e59c8e839560	1221	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1222	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1223	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	163:e59c8e839560	1224	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1225	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	163:e59c8e839560	1226	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1227	} while(0U)
AnnaBridge	163:e59c8e839560	1228
AnnaBridge	163:e59c8e839560	1229	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge	163:e59c8e839560	1230	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge	163:e59c8e839560	1231	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1232
AnnaBridge	163:e59c8e839560	1233	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	1234	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	1235	}while(0U)
AnnaBridge	163:e59c8e839560	1236
AnnaBridge	163:e59c8e839560	1237	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	1238
AnnaBridge	163:e59c8e839560	1239	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1240	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1241	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	1242	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1243	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	1244	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1245	} while(0U)
AnnaBridge	163:e59c8e839560	1246	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	163:e59c8e839560	1247	/**
AnnaBridge	163:e59c8e839560	1248	* @}
AnnaBridge	163:e59c8e839560	1249	*/
AnnaBridge	163:e59c8e839560	1250
AnnaBridge	163:e59c8e839560	1251	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	1252	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	1253	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1254	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1255	* using it.
AnnaBridge	163:e59c8e839560	1256	* @{
AnnaBridge	163:e59c8e839560	1257	*/
AnnaBridge	163:e59c8e839560	1258	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	163:e59c8e839560	1259	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	163:e59c8e839560	1260
AnnaBridge	163:e59c8e839560	1261	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1262	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge	163:e59c8e839560	1263	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge	163:e59c8e839560	1264
AnnaBridge	163:e59c8e839560	1265	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge	163:e59c8e839560	1266	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge	163:e59c8e839560	1267	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1268
AnnaBridge	163:e59c8e839560	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	1270	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	1271
AnnaBridge	163:e59c8e839560	1272	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	163:e59c8e839560	1273	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	163:e59c8e839560	1274	/**
AnnaBridge	163:e59c8e839560	1275	* @}
AnnaBridge	163:e59c8e839560	1276	*/
AnnaBridge	163:e59c8e839560	1277
AnnaBridge	163:e59c8e839560	1278	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	1279	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	1280	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1281	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1282	* using it.
AnnaBridge	163:e59c8e839560	1283	* @{
AnnaBridge	163:e59c8e839560	1284	*/
AnnaBridge	163:e59c8e839560	1285	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1286	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1287	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	163:e59c8e839560	1288	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1289	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	163:e59c8e839560	1290	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1291	} while(0U)
AnnaBridge	163:e59c8e839560	1292	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge	163:e59c8e839560	1293	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1294	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1295	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1296	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	1297	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1298	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	1299	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1300	} while(0U)
AnnaBridge	163:e59c8e839560	1301	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	163:e59c8e839560	1302	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1303	/**
AnnaBridge	163:e59c8e839560	1304	* @}
AnnaBridge	163:e59c8e839560	1305	*/
AnnaBridge	163:e59c8e839560	1306
AnnaBridge	163:e59c8e839560	1307
AnnaBridge	163:e59c8e839560	1308	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	1309	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	1310	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1311	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1312	* using it.
AnnaBridge	163:e59c8e839560	1313	* @{
AnnaBridge	163:e59c8e839560	1314	*/
AnnaBridge	163:e59c8e839560	1315	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge	163:e59c8e839560	1316	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge	163:e59c8e839560	1317	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1318	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	1319	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	163:e59c8e839560	1320	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1321	/**
AnnaBridge	163:e59c8e839560	1322	* @}
AnnaBridge	163:e59c8e839560	1323	*/
AnnaBridge	163:e59c8e839560	1324
AnnaBridge	163:e59c8e839560	1325	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	1326	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	1327	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1328	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1329	* using it.
AnnaBridge	163:e59c8e839560	1330	* @{
AnnaBridge	163:e59c8e839560	1331	*/
AnnaBridge	163:e59c8e839560	1332	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1333	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	1335	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	1337	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1338	} while(0U)
AnnaBridge	163:e59c8e839560	1339	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1340	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	1342	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	1344	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1345	} while(0U)
AnnaBridge	163:e59c8e839560	1346	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1347	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	1349	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	1351	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1352	} while(0U)
AnnaBridge	163:e59c8e839560	1353	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1354	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	1356	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	1358	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1359	} while(0U)
AnnaBridge	163:e59c8e839560	1360	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1361	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	1363	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	1365	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1366	} while(0U)
AnnaBridge	163:e59c8e839560	1367	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1368	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	1370	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	1372	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1373	} while(0U)
AnnaBridge	163:e59c8e839560	1374	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1375	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	1377	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	1379	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1380	} while(0U)
AnnaBridge	163:e59c8e839560	1381	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1382	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	1384	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	1386	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1387	} while(0U)
AnnaBridge	163:e59c8e839560	1388	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1389	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	1391	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	1393	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1394	} while(0U)
AnnaBridge	163:e59c8e839560	1395	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1396	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	1398	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	1400	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1401	} while(0U)
AnnaBridge	163:e59c8e839560	1402	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1403	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	1405	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	1407	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1408	} while(0U)
AnnaBridge	163:e59c8e839560	1409	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1410	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	1412	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	1414	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1415	} while(0U)
AnnaBridge	163:e59c8e839560	1416	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1417	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	163:e59c8e839560	1419	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	163:e59c8e839560	1421	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1422	} while(0U)
AnnaBridge	163:e59c8e839560	1423	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1424	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	163:e59c8e839560	1426	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	163:e59c8e839560	1428	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1429	} while(0U)
AnnaBridge	163:e59c8e839560	1430	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1431	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	1433	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	1435	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1436	} while(0U)
AnnaBridge	163:e59c8e839560	1437	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1438	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	1440	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	1442	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1443	} while(0U)
AnnaBridge	163:e59c8e839560	1444	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1445	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	1447	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	1449	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1450	} while(0U)
AnnaBridge	163:e59c8e839560	1451	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1452	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	1454	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	1456	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1457	} while(0U)
AnnaBridge	163:e59c8e839560	1458	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1459	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1460	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	1461	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1462	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	1463	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1464	} while(0U)
AnnaBridge	163:e59c8e839560	1465	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	1466	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	1467	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	1468	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	1469	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	1470	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	1471	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	163:e59c8e839560	1472	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	163:e59c8e839560	1473	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	163:e59c8e839560	1474	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	163:e59c8e839560	1475	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	163:e59c8e839560	1476	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	163:e59c8e839560	1477	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	163:e59c8e839560	1478	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	163:e59c8e839560	1479	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	163:e59c8e839560	1480	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	163:e59c8e839560	1481	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	163:e59c8e839560	1482	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	163:e59c8e839560	1483	/**
AnnaBridge	163:e59c8e839560	1484	* @}
AnnaBridge	163:e59c8e839560	1485	*/
AnnaBridge	163:e59c8e839560	1486
AnnaBridge	163:e59c8e839560	1487	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	1488	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	1489	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1490	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1491	* using it.
AnnaBridge	163:e59c8e839560	1492	* @{
AnnaBridge	163:e59c8e839560	1493	*/
AnnaBridge	163:e59c8e839560	1494	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	1495	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	1496	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	1497	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	1498	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	1499	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	1500	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	163:e59c8e839560	1501	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	163:e59c8e839560	1502	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	163:e59c8e839560	1503	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	163:e59c8e839560	1504	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	163:e59c8e839560	1505	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	163:e59c8e839560	1506	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	163:e59c8e839560	1507	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	163:e59c8e839560	1508	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	163:e59c8e839560	1509	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	163:e59c8e839560	1510	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	163:e59c8e839560	1511	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	163:e59c8e839560	1512
AnnaBridge	163:e59c8e839560	1513	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	1514	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	1515	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	1516	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	1517	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	1518	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	1519	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	163:e59c8e839560	1520	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	163:e59c8e839560	1521	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	163:e59c8e839560	1522	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	163:e59c8e839560	1523	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	163:e59c8e839560	1524	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	163:e59c8e839560	1525	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	163:e59c8e839560	1526	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	163:e59c8e839560	1527	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	163:e59c8e839560	1528	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	163:e59c8e839560	1529	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	163:e59c8e839560	1530	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	163:e59c8e839560	1531	/**
AnnaBridge	163:e59c8e839560	1532	* @}
AnnaBridge	163:e59c8e839560	1533	*/
AnnaBridge	163:e59c8e839560	1534
AnnaBridge	163:e59c8e839560	1535	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	1536	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	1537	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1538	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1539	* using it.
AnnaBridge	163:e59c8e839560	1540	* @{
AnnaBridge	163:e59c8e839560	1541	*/
AnnaBridge	163:e59c8e839560	1542	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1543	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1544	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	1545	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1546	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	1547	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1548	} while(0U)
AnnaBridge	163:e59c8e839560	1549	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1550	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1551	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	1552	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1553	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	1554	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1555	} while(0U)
AnnaBridge	163:e59c8e839560	1556	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1557	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1558	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	1559	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1560	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	1561	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1562	} while(0U)
AnnaBridge	163:e59c8e839560	1563	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1564	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1565	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	1566	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1567	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	1568	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1569	} while(0U)
AnnaBridge	163:e59c8e839560	1570	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1571	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1572	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	163:e59c8e839560	1573	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1574	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	163:e59c8e839560	1575	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1576	} while(0U)
AnnaBridge	163:e59c8e839560	1577	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1578	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1579	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	1580	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1581	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	1582	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1583	} while(0U)
AnnaBridge	163:e59c8e839560	1584	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1585	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1586	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	1587	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1588	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	1589	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1590	} while(0U)
AnnaBridge	163:e59c8e839560	1591	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1592	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1593	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	1594	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1595	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	1596	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1597	} while(0U)
AnnaBridge	163:e59c8e839560	1598	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1599	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1600	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	1601	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1602	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	1603	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1604	} while(0U)
AnnaBridge	163:e59c8e839560	1605	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	1606	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	1607	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	1608	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	163:e59c8e839560	1609	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	163:e59c8e839560	1610	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	163:e59c8e839560	1611	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	163:e59c8e839560	1612	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
AnnaBridge	163:e59c8e839560	1613	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	163:e59c8e839560	1614
AnnaBridge	163:e59c8e839560	1615	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1616	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1617	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1618	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	163:e59c8e839560	1619	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1620	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	163:e59c8e839560	1621	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1622	} while(0U)
AnnaBridge	163:e59c8e839560	1623
AnnaBridge	163:e59c8e839560	1624	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
AnnaBridge	163:e59c8e839560	1625	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1626
AnnaBridge	163:e59c8e839560	1627	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1628	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1629	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	1630	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	163:e59c8e839560	1631	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1632	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	163:e59c8e839560	1633	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1634	} while(0U)
AnnaBridge	163:e59c8e839560	1635
AnnaBridge	163:e59c8e839560	1636	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
AnnaBridge	163:e59c8e839560	1637	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1638	/**
AnnaBridge	163:e59c8e839560	1639	* @}
AnnaBridge	163:e59c8e839560	1640	*/
AnnaBridge	163:e59c8e839560	1641
AnnaBridge	163:e59c8e839560	1642	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	1643	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	1644	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1645	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1646	* using it.
AnnaBridge	163:e59c8e839560	1647	* @{
AnnaBridge	163:e59c8e839560	1648	*/
AnnaBridge	163:e59c8e839560	1649	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	163:e59c8e839560	1650	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	1651	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	163:e59c8e839560	1652	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	163:e59c8e839560	1653	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
AnnaBridge	163:e59c8e839560	1654	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	1655	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	1656	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	1657	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
AnnaBridge	163:e59c8e839560	1658
AnnaBridge	163:e59c8e839560	1659	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	1660	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	1661	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
AnnaBridge	163:e59c8e839560	1662	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	163:e59c8e839560	1663	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	1664	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	163:e59c8e839560	1665	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	163:e59c8e839560	1666	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
AnnaBridge	163:e59c8e839560	1667	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	1668
AnnaBridge	163:e59c8e839560	1669	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1670	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
AnnaBridge	163:e59c8e839560	1671	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
AnnaBridge	163:e59c8e839560	1672	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1673
AnnaBridge	163:e59c8e839560	1674	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1675	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
AnnaBridge	163:e59c8e839560	1676	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
AnnaBridge	163:e59c8e839560	1677	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1678	/**
AnnaBridge	163:e59c8e839560	1679	* @}
AnnaBridge	163:e59c8e839560	1680	*/
AnnaBridge	163:e59c8e839560	1681
AnnaBridge	163:e59c8e839560	1682	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	1683	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	1684	* @{
AnnaBridge	163:e59c8e839560	1685	*/
AnnaBridge	163:e59c8e839560	1686	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	1687	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	1688	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	1689	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	1690	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	163:e59c8e839560	1691	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	163:e59c8e839560	1692	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	1693	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	163:e59c8e839560	1694	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	163:e59c8e839560	1695	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	163:e59c8e839560	1696	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	1697
AnnaBridge	163:e59c8e839560	1698	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	1699	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	1700	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	1701	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	1702	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	163:e59c8e839560	1703	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	163:e59c8e839560	1704	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	1705	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	163:e59c8e839560	1706	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	163:e59c8e839560	1707	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	163:e59c8e839560	1708	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	1709	/**
AnnaBridge	163:e59c8e839560	1710	* @}
AnnaBridge	163:e59c8e839560	1711	*/
AnnaBridge	163:e59c8e839560	1712
AnnaBridge	163:e59c8e839560	1713	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	1714	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	1715	* @{
AnnaBridge	163:e59c8e839560	1716	*/
AnnaBridge	163:e59c8e839560	1717	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	1718	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	1719	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	1720	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	1721
AnnaBridge	163:e59c8e839560	1722	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	1723	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	1724	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	1725	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	1726
AnnaBridge	163:e59c8e839560	1727	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1728	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge	163:e59c8e839560	1729	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
AnnaBridge	163:e59c8e839560	1730
AnnaBridge	163:e59c8e839560	1731	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge	163:e59c8e839560	1732	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge	163:e59c8e839560	1733	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1734	/**
AnnaBridge	163:e59c8e839560	1735	* @}
AnnaBridge	163:e59c8e839560	1736	*/
AnnaBridge	163:e59c8e839560	1737
AnnaBridge	163:e59c8e839560	1738	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	1739	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	1740	* @{
AnnaBridge	163:e59c8e839560	1741	*/
AnnaBridge	163:e59c8e839560	1742	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	1743	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	1744	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
AnnaBridge	163:e59c8e839560	1745	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge	163:e59c8e839560	1746
AnnaBridge	163:e59c8e839560	1747	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1748	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	1749	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	1750	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1751	/**
AnnaBridge	163:e59c8e839560	1752	* @}
AnnaBridge	163:e59c8e839560	1753	*/
AnnaBridge	163:e59c8e839560	1754
AnnaBridge	163:e59c8e839560	1755	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	1756	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	1757	* @{
AnnaBridge	163:e59c8e839560	1758	*/
AnnaBridge	163:e59c8e839560	1759	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	1760	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	1761	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	1762	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	1763	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	1764	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	1765	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	1766	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	1767	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	1768	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	1769	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	1770	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	163:e59c8e839560	1771	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	163:e59c8e839560	1772	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	1773	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	1774	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	1775	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	1776	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	1777
AnnaBridge	163:e59c8e839560	1778	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	1779	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	1780	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	1781	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	1782	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	1783	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	1784	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	1785	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	1786	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	1787	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	1788	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	1789	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	1790	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	1791	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	1792	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	1793	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	1794	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	163:e59c8e839560	1795	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	163:e59c8e839560	1796	/**
AnnaBridge	163:e59c8e839560	1797	* @}
AnnaBridge	163:e59c8e839560	1798	*/
AnnaBridge	163:e59c8e839560	1799
AnnaBridge	163:e59c8e839560	1800	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	1801	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	1802	* @{
AnnaBridge	163:e59c8e839560	1803	*/
AnnaBridge	163:e59c8e839560	1804	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	1805	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	1806	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
AnnaBridge	163:e59c8e839560	1807	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	1808	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	1809	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	1810	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	1811
AnnaBridge	163:e59c8e839560	1812	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	1813	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	1814	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	1815	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	1816	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	1817	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
AnnaBridge	163:e59c8e839560	1818	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	1819
AnnaBridge	163:e59c8e839560	1820	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1821	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
AnnaBridge	163:e59c8e839560	1822	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
AnnaBridge	163:e59c8e839560	1823	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1824
AnnaBridge	163:e59c8e839560	1825	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1826	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
AnnaBridge	163:e59c8e839560	1827	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
AnnaBridge	163:e59c8e839560	1828	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1829	/**
AnnaBridge	163:e59c8e839560	1830	* @}
AnnaBridge	163:e59c8e839560	1831	*/
AnnaBridge	163:e59c8e839560	1832
AnnaBridge	163:e59c8e839560	1833	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	1834	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	1835	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	1836	* power consumption.
AnnaBridge	163:e59c8e839560	1837	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	1838	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	1839	* @{
AnnaBridge	163:e59c8e839560	1840	*/
AnnaBridge	163:e59c8e839560	1841	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	1842	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	1843	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	1844	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	1845	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	163:e59c8e839560	1846	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	1847	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	163:e59c8e839560	1848	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	163:e59c8e839560	1849	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	163:e59c8e839560	1850	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	163:e59c8e839560	1851	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	1852	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	1853	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	163:e59c8e839560	1854	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	163:e59c8e839560	1855	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
AnnaBridge	163:e59c8e839560	1856	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	163:e59c8e839560	1857	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	1858	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	1859	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	1860	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	1861
AnnaBridge	163:e59c8e839560	1862	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	1863	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	1864	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	1865	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	1866	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	163:e59c8e839560	1867	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	1868	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	163:e59c8e839560	1869	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	163:e59c8e839560	1870	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	163:e59c8e839560	1871	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	163:e59c8e839560	1872	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	1873	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	1874	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	163:e59c8e839560	1875	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	163:e59c8e839560	1876	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	163:e59c8e839560	1877	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	1878	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	1879	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	1880	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	1881	/**
AnnaBridge	163:e59c8e839560	1882	* @}
AnnaBridge	163:e59c8e839560	1883	*/
AnnaBridge	163:e59c8e839560	1884
AnnaBridge	163:e59c8e839560	1885	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	1886	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	1887	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	1888	* power consumption.
AnnaBridge	163:e59c8e839560	1889	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	1890	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	1891	* @{
AnnaBridge	163:e59c8e839560	1892	*/
AnnaBridge	163:e59c8e839560	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	1894	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	1895
AnnaBridge	163:e59c8e839560	1896	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	1897	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	1898
AnnaBridge	163:e59c8e839560	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	1901
AnnaBridge	163:e59c8e839560	1902	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1903	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	163:e59c8e839560	1904	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	163:e59c8e839560	1905
AnnaBridge	163:e59c8e839560	1906	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	163:e59c8e839560	1907	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	163:e59c8e839560	1908	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1909	/**
AnnaBridge	163:e59c8e839560	1910	* @}
AnnaBridge	163:e59c8e839560	1911	*/
AnnaBridge	163:e59c8e839560	1912
AnnaBridge	163:e59c8e839560	1913	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	1914	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	1915	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	1916	* power consumption.
AnnaBridge	163:e59c8e839560	1917	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	1918	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	1919	* @{
AnnaBridge	163:e59c8e839560	1920	*/
AnnaBridge	163:e59c8e839560	1921	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	163:e59c8e839560	1922	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	163:e59c8e839560	1923
AnnaBridge	163:e59c8e839560	1924	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	1926	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	1927	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	1928	/**
AnnaBridge	163:e59c8e839560	1929	* @}
AnnaBridge	163:e59c8e839560	1930	*/
AnnaBridge	163:e59c8e839560	1931
AnnaBridge	163:e59c8e839560	1932	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	1933	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	1934	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	1935	* power consumption.
AnnaBridge	163:e59c8e839560	1936	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	1937	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	1938	* @{
AnnaBridge	163:e59c8e839560	1939	*/
AnnaBridge	163:e59c8e839560	1940	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	1941	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	1942	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	1943	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	1944	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	1945	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	1946	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	1947	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	1948	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	1949	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	1950	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	1951	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	163:e59c8e839560	1952	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	163:e59c8e839560	1953	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	1954	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	1955	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	1956	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	1957	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	1958
AnnaBridge	163:e59c8e839560	1959	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	1960	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	1961	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	1962	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	1963	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	1964	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	1965	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	1966	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	1967	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	1968	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	1969	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	1970	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	1971	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	1972	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	1973	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	1974	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	1975	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	163:e59c8e839560	1976	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	163:e59c8e839560	1977	/**
AnnaBridge	163:e59c8e839560	1978	* @}
AnnaBridge	163:e59c8e839560	1979	*/
AnnaBridge	163:e59c8e839560	1980
AnnaBridge	163:e59c8e839560	1981	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	1982	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	1983	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	1984	* power consumption.
AnnaBridge	163:e59c8e839560	1985	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	1986	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	1987	* @{
AnnaBridge	163:e59c8e839560	1988	*/
AnnaBridge	163:e59c8e839560	1989	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	1990	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	1991	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	1992	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	1993	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	163:e59c8e839560	1994	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	1995	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	1996	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	1997	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	1998
AnnaBridge	163:e59c8e839560	1999	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	2000	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	2001	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	2002	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	2003	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	2004	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	2005	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	2006	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	163:e59c8e839560	2007	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	2008
AnnaBridge	163:e59c8e839560	2009	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	2010	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	163:e59c8e839560	2011
AnnaBridge	163:e59c8e839560	2012	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	163:e59c8e839560	2013	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	2014
AnnaBridge	163:e59c8e839560	2015	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	2016	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
AnnaBridge	163:e59c8e839560	2017	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
AnnaBridge	163:e59c8e839560	2018	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	2019	/**
AnnaBridge	163:e59c8e839560	2020	* @}
AnnaBridge	163:e59c8e839560	2021	*/
AnnaBridge	163:e59c8e839560	2022	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	2023	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	2024
AnnaBridge	163:e59c8e839560	2025	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
AnnaBridge	163:e59c8e839560	2026	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2027	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2028	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2029	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2030	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2031	* using it.
AnnaBridge	163:e59c8e839560	2032	* @{
AnnaBridge	163:e59c8e839560	2033	*/
AnnaBridge	163:e59c8e839560	2034	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2035	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2036	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	2037	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2038	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	2039	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2040	} while(0U)
AnnaBridge	163:e59c8e839560	2041	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2042	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2043	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	2044	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2045	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	2046	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2047	} while(0U)
AnnaBridge	163:e59c8e839560	2048	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2049	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2050	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	2051	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2052	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	2053	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2054	} while(0U)
AnnaBridge	163:e59c8e839560	2055	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2056	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2057	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	2058	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2059	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	2060	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2061	} while(0U)
AnnaBridge	163:e59c8e839560	2062	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2063	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2064	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	2065	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2066	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	2067	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2068	} while(0U)
AnnaBridge	163:e59c8e839560	2069	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2070	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2071	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	163:e59c8e839560	2072	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2073	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	163:e59c8e839560	2074	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2075	} while(0U)
AnnaBridge	163:e59c8e839560	2076	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2077	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2078	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	2079	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2080	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	2081	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2082	} while(0U)
AnnaBridge	163:e59c8e839560	2083	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2084	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2085	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	2086	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2087	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	2088	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2089	} while(0U)
AnnaBridge	163:e59c8e839560	2090	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2091	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2092	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	2093	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2094	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	2095	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2096	} while(0U)
AnnaBridge	163:e59c8e839560	2097	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2098	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2099	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	2100	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2101	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	2102	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2103	} while(0U)
AnnaBridge	163:e59c8e839560	2104	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	2105	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	2106	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	163:e59c8e839560	2107	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	163:e59c8e839560	2108	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	163:e59c8e839560	2109	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	163:e59c8e839560	2110	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	163:e59c8e839560	2111	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	163:e59c8e839560	2112	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	163:e59c8e839560	2113	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	2114	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2115	/**
AnnaBridge	163:e59c8e839560	2116	* @brief Enable ETHERNET clock.
AnnaBridge	163:e59c8e839560	2117	*/
AnnaBridge	163:e59c8e839560	2118	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2119	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2120	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	163:e59c8e839560	2121	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2122	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	163:e59c8e839560	2123	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2124	} while(0U)
AnnaBridge	163:e59c8e839560	2125	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2126	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2127	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	163:e59c8e839560	2128	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2129	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	163:e59c8e839560	2130	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2131	} while(0U)
AnnaBridge	163:e59c8e839560	2132	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2133	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2134	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	163:e59c8e839560	2135	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2136	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	163:e59c8e839560	2137	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2138	} while(0U)
AnnaBridge	163:e59c8e839560	2139	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2140	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2141	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	163:e59c8e839560	2142	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2143	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	163:e59c8e839560	2144	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2145	} while(0U)
AnnaBridge	163:e59c8e839560	2146	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2147	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	2148	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	2149	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	163:e59c8e839560	2150	} while(0U)
AnnaBridge	163:e59c8e839560	2151
AnnaBridge	163:e59c8e839560	2152	/**
AnnaBridge	163:e59c8e839560	2153	* @brief Disable ETHERNET clock.
AnnaBridge	163:e59c8e839560	2154	*/
AnnaBridge	163:e59c8e839560	2155	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge	163:e59c8e839560	2156	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge	163:e59c8e839560	2157	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge	163:e59c8e839560	2158	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge	163:e59c8e839560	2159	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	163:e59c8e839560	2160	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	2161	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	2162	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	163:e59c8e839560	2163	} while(0U)
AnnaBridge	163:e59c8e839560	2164	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2165	/**
AnnaBridge	163:e59c8e839560	2166	* @}
AnnaBridge	163:e59c8e839560	2167	*/
AnnaBridge	163:e59c8e839560	2168
AnnaBridge	163:e59c8e839560	2169	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2170	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2171	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2172	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2173	* using it.
AnnaBridge	163:e59c8e839560	2174	* @{
AnnaBridge	163:e59c8e839560	2175	*/
AnnaBridge	163:e59c8e839560	2176	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	2177	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	2178	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	2179	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	2180	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	2181	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	163:e59c8e839560	2182	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	163:e59c8e839560	2183	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	163:e59c8e839560	2184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	163:e59c8e839560	2185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	2186
AnnaBridge	163:e59c8e839560	2187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	2188	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	2189	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	163:e59c8e839560	2190	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	163:e59c8e839560	2191	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	163:e59c8e839560	2192	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	163:e59c8e839560	2193	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
AnnaBridge	163:e59c8e839560	2194	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	2195	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	2196	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	2197	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2198	/**
AnnaBridge	163:e59c8e839560	2199	* @brief Enable ETHERNET clock.
AnnaBridge	163:e59c8e839560	2200	*/
AnnaBridge	163:e59c8e839560	2201	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge	163:e59c8e839560	2202	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge	163:e59c8e839560	2203	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge	163:e59c8e839560	2204	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge	163:e59c8e839560	2205	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge	163:e59c8e839560	2206	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge	163:e59c8e839560	2207	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge	163:e59c8e839560	2208	/**
AnnaBridge	163:e59c8e839560	2209	* @brief Disable ETHERNET clock.
AnnaBridge	163:e59c8e839560	2210	*/
AnnaBridge	163:e59c8e839560	2211	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge	163:e59c8e839560	2212	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge	163:e59c8e839560	2213	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge	163:e59c8e839560	2214	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge	163:e59c8e839560	2215	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge	163:e59c8e839560	2216	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge	163:e59c8e839560	2217	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
AnnaBridge	163:e59c8e839560	2218	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2219	/**
AnnaBridge	163:e59c8e839560	2220	* @}
AnnaBridge	163:e59c8e839560	2221	*/
AnnaBridge	163:e59c8e839560	2222
AnnaBridge	163:e59c8e839560	2223	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2224	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2225	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2226	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2227	* using it.
AnnaBridge	163:e59c8e839560	2228	* @{
AnnaBridge	163:e59c8e839560	2229	*/
AnnaBridge	163:e59c8e839560	2230	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	2231	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	2232	}while(0U)
AnnaBridge	163:e59c8e839560	2233
AnnaBridge	163:e59c8e839560	2234	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	2235
AnnaBridge	163:e59c8e839560	2236	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2237	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2238	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	2239	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2240	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	2241	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2242	} while(0U)
AnnaBridge	163:e59c8e839560	2243	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	163:e59c8e839560	2244
AnnaBridge	163:e59c8e839560	2245	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2246	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2247	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2248	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	2249	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2250	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	2251	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2252	} while(0U)
AnnaBridge	163:e59c8e839560	2253	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	163:e59c8e839560	2254	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2255
AnnaBridge	163:e59c8e839560	2256	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2257	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2258	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2259	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	163:e59c8e839560	2260	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2261	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	163:e59c8e839560	2262	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2263	} while(0U)
AnnaBridge	163:e59c8e839560	2264	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2265	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2266	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	163:e59c8e839560	2267	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2268	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	163:e59c8e839560	2269	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2270	} while(0U)
AnnaBridge	163:e59c8e839560	2271	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge	163:e59c8e839560	2272	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge	163:e59c8e839560	2273	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2274	/**
AnnaBridge	163:e59c8e839560	2275	* @}
AnnaBridge	163:e59c8e839560	2276	*/
AnnaBridge	163:e59c8e839560	2277
AnnaBridge	163:e59c8e839560	2278
AnnaBridge	163:e59c8e839560	2279	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2280	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2281	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2282	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2283	* using it.
AnnaBridge	163:e59c8e839560	2284	* @{
AnnaBridge	163:e59c8e839560	2285	*/
AnnaBridge	163:e59c8e839560	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	2287	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	2288
AnnaBridge	163:e59c8e839560	2289	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	163:e59c8e839560	2290	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	163:e59c8e839560	2291
AnnaBridge	163:e59c8e839560	2292	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2293	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	163:e59c8e839560	2294	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	163:e59c8e839560	2295	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2296
AnnaBridge	163:e59c8e839560	2297	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2298	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge	163:e59c8e839560	2299	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge	163:e59c8e839560	2300
AnnaBridge	163:e59c8e839560	2301	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge	163:e59c8e839560	2302	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge	163:e59c8e839560	2303	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2304	/**
AnnaBridge	163:e59c8e839560	2305	* @}
AnnaBridge	163:e59c8e839560	2306	*/
AnnaBridge	163:e59c8e839560	2307
AnnaBridge	163:e59c8e839560	2308	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2309	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	2310	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2311	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2312	* using it.
AnnaBridge	163:e59c8e839560	2313	* @{
AnnaBridge	163:e59c8e839560	2314	*/
AnnaBridge	163:e59c8e839560	2315	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2316	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2317	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	163:e59c8e839560	2318	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2319	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	163:e59c8e839560	2320	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2321	} while(0U)
AnnaBridge	163:e59c8e839560	2322	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
AnnaBridge	163:e59c8e839560	2323	/**
AnnaBridge	163:e59c8e839560	2324	* @}
AnnaBridge	163:e59c8e839560	2325	*/
AnnaBridge	163:e59c8e839560	2326
AnnaBridge	163:e59c8e839560	2327	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2328	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	2329	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2330	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2331	* using it.
AnnaBridge	163:e59c8e839560	2332	* @{
AnnaBridge	163:e59c8e839560	2333	*/
AnnaBridge	163:e59c8e839560	2334	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
AnnaBridge	163:e59c8e839560	2335	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
AnnaBridge	163:e59c8e839560	2336	/**
AnnaBridge	163:e59c8e839560	2337	* @}
AnnaBridge	163:e59c8e839560	2338	*/
AnnaBridge	163:e59c8e839560	2339
AnnaBridge	163:e59c8e839560	2340	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2341	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	2342	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2343	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2344	* using it.
AnnaBridge	163:e59c8e839560	2345	* @{
AnnaBridge	163:e59c8e839560	2346	*/
AnnaBridge	163:e59c8e839560	2347	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2348	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2349	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	2350	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2351	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	2352	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2353	} while(0U)
AnnaBridge	163:e59c8e839560	2354	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2355	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	2357	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	2359	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2360	} while(0U)
AnnaBridge	163:e59c8e839560	2361	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2362	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	2364	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	2366	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2367	} while(0U)
AnnaBridge	163:e59c8e839560	2368	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2369	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2370	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	2371	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2372	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	2373	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2374	} while(0U)
AnnaBridge	163:e59c8e839560	2375	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2376	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2377	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	2378	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2379	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	2380	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2381	} while(0U)
AnnaBridge	163:e59c8e839560	2382	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2383	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2384	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	2385	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2386	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	2387	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2388	} while(0U)
AnnaBridge	163:e59c8e839560	2389	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2390	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2391	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	2392	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2393	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	2394	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2395	} while(0U)
AnnaBridge	163:e59c8e839560	2396	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2397	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2398	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	2399	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2400	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	2401	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2402	} while(0U)
AnnaBridge	163:e59c8e839560	2403	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2404	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2405	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	2406	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2407	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	2408	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2409	} while(0U)
AnnaBridge	163:e59c8e839560	2410	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2411	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2412	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	2413	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2414	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	2415	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2416	} while(0U)
AnnaBridge	163:e59c8e839560	2417	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2418	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2419	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	2420	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2421	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	2422	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2423	} while(0U)
AnnaBridge	163:e59c8e839560	2424	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2425	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2426	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	2427	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2428	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	2429	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2430	} while(0U)
AnnaBridge	163:e59c8e839560	2431	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2432	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2433	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2434	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2435	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2436	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2437	} while(0U)
AnnaBridge	163:e59c8e839560	2438	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2439	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2440	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2441	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2442	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2443	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2444	} while(0U)
AnnaBridge	163:e59c8e839560	2445	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2446	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2447	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2448	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2449	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2450	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2451	} while(0U)
AnnaBridge	163:e59c8e839560	2452	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2453	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2454	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2455	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2456	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2457	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2458	} while(0U)
AnnaBridge	163:e59c8e839560	2459	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	2460	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	2461	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	2462	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	2463	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	2464	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	2465	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	163:e59c8e839560	2466	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	163:e59c8e839560	2467	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	163:e59c8e839560	2468	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	163:e59c8e839560	2469	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	163:e59c8e839560	2470	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	163:e59c8e839560	2471	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	163:e59c8e839560	2472	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	163:e59c8e839560	2473	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	163:e59c8e839560	2474	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	163:e59c8e839560	2475	/**
AnnaBridge	163:e59c8e839560	2476	* @}
AnnaBridge	163:e59c8e839560	2477	*/
AnnaBridge	163:e59c8e839560	2478
AnnaBridge	163:e59c8e839560	2479	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2480	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2481	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2482	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2483	* using it.
AnnaBridge	163:e59c8e839560	2484	* @{
AnnaBridge	163:e59c8e839560	2485	*/
AnnaBridge	163:e59c8e839560	2486	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2487	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2488	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2489	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2490	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2491	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	2492	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	163:e59c8e839560	2493	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	163:e59c8e839560	2494	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	163:e59c8e839560	2495	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	163:e59c8e839560	2496	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2497	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2498	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	163:e59c8e839560	2499	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2500	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2501	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	163:e59c8e839560	2502
AnnaBridge	163:e59c8e839560	2503	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2504	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2505	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2506	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2507	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2508	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	2509	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	163:e59c8e839560	2510	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	163:e59c8e839560	2511	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	163:e59c8e839560	2512	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	163:e59c8e839560	2513	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2514	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2515	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	163:e59c8e839560	2516	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2517	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2518	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	163:e59c8e839560	2519	/**
AnnaBridge	163:e59c8e839560	2520	* @}
AnnaBridge	163:e59c8e839560	2521	*/
AnnaBridge	163:e59c8e839560	2522
AnnaBridge	163:e59c8e839560	2523	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2524	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	2525	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2526	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2527	* using it.
AnnaBridge	163:e59c8e839560	2528	* @{
AnnaBridge	163:e59c8e839560	2529	*/
AnnaBridge	163:e59c8e839560	2530	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2531	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2532	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	2533	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2534	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	2535	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2536	} while(0U)
AnnaBridge	163:e59c8e839560	2537	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2538	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2539	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	2540	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2541	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	2542	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2543	} while(0U)
AnnaBridge	163:e59c8e839560	2544	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2545	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2546	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	2547	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2548	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	2549	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2550	} while(0U)
AnnaBridge	163:e59c8e839560	2551	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2552	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2553	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	2554	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2555	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	2556	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2557	} while(0U)
AnnaBridge	163:e59c8e839560	2558	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2559	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2560	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	2561	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2562	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	2563	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2564	} while(0U)
AnnaBridge	163:e59c8e839560	2565	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2566	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2567	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	2568	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2569	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	2570	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2571	} while(0U)
AnnaBridge	163:e59c8e839560	2572
AnnaBridge	163:e59c8e839560	2573	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	2574	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	2575	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	2576	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	163:e59c8e839560	2577	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	163:e59c8e839560	2578	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	163:e59c8e839560	2579	/**
AnnaBridge	163:e59c8e839560	2580	* @}
AnnaBridge	163:e59c8e839560	2581	*/
AnnaBridge	163:e59c8e839560	2582
AnnaBridge	163:e59c8e839560	2583	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2584	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2585	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2586	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2587	* using it.
AnnaBridge	163:e59c8e839560	2588	* @{
AnnaBridge	163:e59c8e839560	2589	*/
AnnaBridge	163:e59c8e839560	2590	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	2591	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2592	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	163:e59c8e839560	2593	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	163:e59c8e839560	2594	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2595	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2596
AnnaBridge	163:e59c8e839560	2597	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	2598	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2599	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	163:e59c8e839560	2600	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	163:e59c8e839560	2601	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2602	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2603	/**
AnnaBridge	163:e59c8e839560	2604	* @}
AnnaBridge	163:e59c8e839560	2605	*/
AnnaBridge	163:e59c8e839560	2606
AnnaBridge	163:e59c8e839560	2607	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	2608	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	2609	* @{
AnnaBridge	163:e59c8e839560	2610	*/
AnnaBridge	163:e59c8e839560	2611	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	2612	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2613	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	2614	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	2615	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	163:e59c8e839560	2616	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	163:e59c8e839560	2617	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	2618	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	2619
AnnaBridge	163:e59c8e839560	2620	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	2621	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2622	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	2623	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	2624	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	163:e59c8e839560	2625	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	163:e59c8e839560	2626	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	2627	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	2628	/**
AnnaBridge	163:e59c8e839560	2629	* @}
AnnaBridge	163:e59c8e839560	2630	*/
AnnaBridge	163:e59c8e839560	2631
AnnaBridge	163:e59c8e839560	2632	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	2633	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	2634	* @{
AnnaBridge	163:e59c8e839560	2635	*/
AnnaBridge	163:e59c8e839560	2636	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	2637	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	2638
AnnaBridge	163:e59c8e839560	2639	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2640	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	2641	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	2642	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2643
AnnaBridge	163:e59c8e839560	2644	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2645	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge	163:e59c8e839560	2646	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
AnnaBridge	163:e59c8e839560	2647
AnnaBridge	163:e59c8e839560	2648	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge	163:e59c8e839560	2649	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge	163:e59c8e839560	2650	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2651
AnnaBridge	163:e59c8e839560	2652	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	2653	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	2654
AnnaBridge	163:e59c8e839560	2655	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	2656	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	2657	/**
AnnaBridge	163:e59c8e839560	2658	* @}
AnnaBridge	163:e59c8e839560	2659	*/
AnnaBridge	163:e59c8e839560	2660
AnnaBridge	163:e59c8e839560	2661	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	2662	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	2663	* @{
AnnaBridge	163:e59c8e839560	2664	*/
AnnaBridge	163:e59c8e839560	2665	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	2666	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	2667
AnnaBridge	163:e59c8e839560	2668	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
AnnaBridge	163:e59c8e839560	2669	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
AnnaBridge	163:e59c8e839560	2670	/**
AnnaBridge	163:e59c8e839560	2671	* @}
AnnaBridge	163:e59c8e839560	2672	*/
AnnaBridge	163:e59c8e839560	2673
AnnaBridge	163:e59c8e839560	2674	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	2675	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	2676	* @{
AnnaBridge	163:e59c8e839560	2677	*/
AnnaBridge	163:e59c8e839560	2678	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	2679	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	2680	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	2681	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	2682	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	2683	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	2684	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	2685	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	2686	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	2687	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	2688	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	2689	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	2690	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2691	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2692	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2693	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2694
AnnaBridge	163:e59c8e839560	2695	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	2696	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2697	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2698	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2699	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2700	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	2701	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	2702	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	2703	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	2704	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	2705	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	2706	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	2707	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	2708	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	2709	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	2710	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	2711	/**
AnnaBridge	163:e59c8e839560	2712	* @}
AnnaBridge	163:e59c8e839560	2713	*/
AnnaBridge	163:e59c8e839560	2714
AnnaBridge	163:e59c8e839560	2715	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	2716	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	2717	* @{
AnnaBridge	163:e59c8e839560	2718	*/
AnnaBridge	163:e59c8e839560	2719	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	2720	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	2721	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	2722	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	2723
AnnaBridge	163:e59c8e839560	2724	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	2725	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	2726	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	2727	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	2728	/**
AnnaBridge	163:e59c8e839560	2729	* @}
AnnaBridge	163:e59c8e839560	2730	*/
AnnaBridge	163:e59c8e839560	2731
AnnaBridge	163:e59c8e839560	2732	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	2733	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	2734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	2735	* power consumption.
AnnaBridge	163:e59c8e839560	2736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	2737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	2738	* @{
AnnaBridge	163:e59c8e839560	2739	*/
AnnaBridge	163:e59c8e839560	2740	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	2741	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	2742	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	2743	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	2744	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	163:e59c8e839560	2745	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	2746	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	163:e59c8e839560	2747	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	163:e59c8e839560	2748	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	163:e59c8e839560	2749	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	163:e59c8e839560	2750	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	2751	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	2752	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	2753	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	2754	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	2755	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	2756
AnnaBridge	163:e59c8e839560	2757	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	2758	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	2759	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	2760	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	2761	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	163:e59c8e839560	2762	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	2763	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	163:e59c8e839560	2764	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	163:e59c8e839560	2765	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	163:e59c8e839560	2766	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	163:e59c8e839560	2767	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	2768	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	2769	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	2770	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	2771	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	2772	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	2773	/**
AnnaBridge	163:e59c8e839560	2774	* @}
AnnaBridge	163:e59c8e839560	2775	*/
AnnaBridge	163:e59c8e839560	2776
AnnaBridge	163:e59c8e839560	2777	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	2778	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	2779	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	2780	* power consumption.
AnnaBridge	163:e59c8e839560	2781	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	2782	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	2783	* @{
AnnaBridge	163:e59c8e839560	2784	*/
AnnaBridge	163:e59c8e839560	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	2786	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	2787
AnnaBridge	163:e59c8e839560	2788	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	2789	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	2790
AnnaBridge	163:e59c8e839560	2791	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	2793	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	2794	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2795
AnnaBridge	163:e59c8e839560	2796	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	2797	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	163:e59c8e839560	2798	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	163:e59c8e839560	2799
AnnaBridge	163:e59c8e839560	2800	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	163:e59c8e839560	2801	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	163:e59c8e839560	2802	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2803	/**
AnnaBridge	163:e59c8e839560	2804	* @}
AnnaBridge	163:e59c8e839560	2805	*/
AnnaBridge	163:e59c8e839560	2806
AnnaBridge	163:e59c8e839560	2807	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	2808	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	2809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	2810	* power consumption.
AnnaBridge	163:e59c8e839560	2811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	2812	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	2813	* @{
AnnaBridge	163:e59c8e839560	2814	*/
AnnaBridge	163:e59c8e839560	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	163:e59c8e839560	2816	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	163:e59c8e839560	2817	/**
AnnaBridge	163:e59c8e839560	2818	* @}
AnnaBridge	163:e59c8e839560	2819	*/
AnnaBridge	163:e59c8e839560	2820
AnnaBridge	163:e59c8e839560	2821	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	2822	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	2823	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	2824	* power consumption.
AnnaBridge	163:e59c8e839560	2825	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	2826	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	2827	* @{
AnnaBridge	163:e59c8e839560	2828	*/
AnnaBridge	163:e59c8e839560	2829	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	2830	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	2831	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	2832	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	2833	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	2834	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	2835	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	2836	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	2837	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	2838	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	2839	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	2840	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	2841	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	2842	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	2843	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	2844	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	2845
AnnaBridge	163:e59c8e839560	2846	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	2847	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	2848	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	2849	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	2850	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	2851	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	2852	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	2853	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	2854	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	2855	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	2856	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	2857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	2858	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	2859	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	2860	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	2861	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	2862	/**
AnnaBridge	163:e59c8e839560	2863	* @}
AnnaBridge	163:e59c8e839560	2864	*/
AnnaBridge	163:e59c8e839560	2865
AnnaBridge	163:e59c8e839560	2866	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	2867	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	2868	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	2869	* power consumption.
AnnaBridge	163:e59c8e839560	2870	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	2871	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	2872	* @{
AnnaBridge	163:e59c8e839560	2873	*/
AnnaBridge	163:e59c8e839560	2874	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	2875	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	2876	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	2877	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	2878	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	2879	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	2880
AnnaBridge	163:e59c8e839560	2881	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	2882	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	2883	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	2884	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	2885	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	2886	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	2887	/**
AnnaBridge	163:e59c8e839560	2888	* @}
AnnaBridge	163:e59c8e839560	2889	*/
AnnaBridge	163:e59c8e839560	2890	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	2891	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	2892
AnnaBridge	163:e59c8e839560	2893	/------------------------- STM32F401xE/STM32F401xC --------------------------/
AnnaBridge	163:e59c8e839560	2894	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
AnnaBridge	163:e59c8e839560	2895	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2896	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2897	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2898	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2899	* using it.
AnnaBridge	163:e59c8e839560	2900	* @{
AnnaBridge	163:e59c8e839560	2901	*/
AnnaBridge	163:e59c8e839560	2902	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2903	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2904	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	2905	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2906	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	2907	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2908	} while(0U)
AnnaBridge	163:e59c8e839560	2909	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2910	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2911	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	2912	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2913	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	2914	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2915	} while(0U)
AnnaBridge	163:e59c8e839560	2916	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2917	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2918	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	2919	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2920	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	2921	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2922	} while(0U)
AnnaBridge	163:e59c8e839560	2923	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2924	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2925	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	2926	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2927	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	2928	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2929	} while(0U)
AnnaBridge	163:e59c8e839560	2930
AnnaBridge	163:e59c8e839560	2931	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	2932	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	2933	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	2934	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	163:e59c8e839560	2935	/**
AnnaBridge	163:e59c8e839560	2936	* @}
AnnaBridge	163:e59c8e839560	2937	*/
AnnaBridge	163:e59c8e839560	2938
AnnaBridge	163:e59c8e839560	2939	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2940	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2941	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2942	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2943	* using it.
AnnaBridge	163:e59c8e839560	2944	* @{
AnnaBridge	163:e59c8e839560	2945	*/
AnnaBridge	163:e59c8e839560	2946	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	2947	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	2948	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	2949	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	2950
AnnaBridge	163:e59c8e839560	2951	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	2952	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	2953	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	2954	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	2955	/**
AnnaBridge	163:e59c8e839560	2956	* @}
AnnaBridge	163:e59c8e839560	2957	*/
AnnaBridge	163:e59c8e839560	2958
AnnaBridge	163:e59c8e839560	2959	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2960	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2961	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2962	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2963	* using it.
AnnaBridge	163:e59c8e839560	2964	* @{
AnnaBridge	163:e59c8e839560	2965	*/
AnnaBridge	163:e59c8e839560	2966	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	2967	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	2968	}while(0U)
AnnaBridge	163:e59c8e839560	2969
AnnaBridge	163:e59c8e839560	2970	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	2971	/**
AnnaBridge	163:e59c8e839560	2972	* @}
AnnaBridge	163:e59c8e839560	2973	*/
AnnaBridge	163:e59c8e839560	2974
AnnaBridge	163:e59c8e839560	2975	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2976	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2977	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2978	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2979	* using it.
AnnaBridge	163:e59c8e839560	2980	* @{
AnnaBridge	163:e59c8e839560	2981	*/
AnnaBridge	163:e59c8e839560	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	2983	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	2984	/**
AnnaBridge	163:e59c8e839560	2985	* @}
AnnaBridge	163:e59c8e839560	2986	*/
AnnaBridge	163:e59c8e839560	2987
AnnaBridge	163:e59c8e839560	2988	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	2989	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	2990	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2991	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2992	* using it.
AnnaBridge	163:e59c8e839560	2993	* @{
AnnaBridge	163:e59c8e839560	2994	*/
AnnaBridge	163:e59c8e839560	2995	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2996	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	2997	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	2998	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2999	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	3000	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3001	} while(0U)
AnnaBridge	163:e59c8e839560	3002	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3003	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3004	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	3005	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3006	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	3007	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3008	} while(0U)
AnnaBridge	163:e59c8e839560	3009	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3010	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3011	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	3012	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3013	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	3014	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3015	} while(0U)
AnnaBridge	163:e59c8e839560	3016	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3017	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3018	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	3019	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3020	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	3021	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3022	} while(0U)
AnnaBridge	163:e59c8e839560	3023	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3024	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3025	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	3026	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3027	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	3028	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3029	} while(0U)
AnnaBridge	163:e59c8e839560	3030	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	3031	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	3032	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	3033	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	3034	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	3035	/**
AnnaBridge	163:e59c8e839560	3036	* @}
AnnaBridge	163:e59c8e839560	3037	*/
AnnaBridge	163:e59c8e839560	3038
AnnaBridge	163:e59c8e839560	3039	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3040	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3041	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3042	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3043	* using it.
AnnaBridge	163:e59c8e839560	3044	* @{
AnnaBridge	163:e59c8e839560	3045	*/
AnnaBridge	163:e59c8e839560	3046	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	3047	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3048	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	3049	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3050	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3051
AnnaBridge	163:e59c8e839560	3052	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	3053	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3054	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	3055	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3056	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3057	/**
AnnaBridge	163:e59c8e839560	3058	* @}
AnnaBridge	163:e59c8e839560	3059	*/
AnnaBridge	163:e59c8e839560	3060
AnnaBridge	163:e59c8e839560	3061	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3062	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	3063	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3064	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3065	* using it.
AnnaBridge	163:e59c8e839560	3066	* @{
AnnaBridge	163:e59c8e839560	3067	*/
AnnaBridge	163:e59c8e839560	3068	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3069	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3070	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	3071	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3072	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	3073	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3074	} while(0U)
AnnaBridge	163:e59c8e839560	3075	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3076	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3077	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	3078	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3079	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	3080	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3081	} while(0U)
AnnaBridge	163:e59c8e839560	3082	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3083	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3084	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	3085	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3086	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	3087	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3088	} while(0U)
AnnaBridge	163:e59c8e839560	3089
AnnaBridge	163:e59c8e839560	3090	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	3091	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	3092	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	3093	/**
AnnaBridge	163:e59c8e839560	3094	* @}
AnnaBridge	163:e59c8e839560	3095	*/
AnnaBridge	163:e59c8e839560	3096
AnnaBridge	163:e59c8e839560	3097	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3098	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	3099	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3100	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3101	* using it.
AnnaBridge	163:e59c8e839560	3102	* @{
AnnaBridge	163:e59c8e839560	3103	*/
AnnaBridge	163:e59c8e839560	3104	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	3105	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	3106	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	163:e59c8e839560	3107
AnnaBridge	163:e59c8e839560	3108	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	3109	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	3110	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	163:e59c8e839560	3111	/**
AnnaBridge	163:e59c8e839560	3112	* @}
AnnaBridge	163:e59c8e839560	3113	*/
AnnaBridge	163:e59c8e839560	3114	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3115	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3116	* @{
AnnaBridge	163:e59c8e839560	3117	*/
AnnaBridge	163:e59c8e839560	3118	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3119	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	3120	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	3121	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3122
AnnaBridge	163:e59c8e839560	3123	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3124	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	3125	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	3126	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3127	/**
AnnaBridge	163:e59c8e839560	3128	* @}
AnnaBridge	163:e59c8e839560	3129	*/
AnnaBridge	163:e59c8e839560	3130
AnnaBridge	163:e59c8e839560	3131	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3132	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3133	* @{
AnnaBridge	163:e59c8e839560	3134	*/
AnnaBridge	163:e59c8e839560	3135	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3136	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	3137
AnnaBridge	163:e59c8e839560	3138	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3139	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	3140	/**
AnnaBridge	163:e59c8e839560	3141	* @}
AnnaBridge	163:e59c8e839560	3142	*/
AnnaBridge	163:e59c8e839560	3143
AnnaBridge	163:e59c8e839560	3144	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3145	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3146	* @{
AnnaBridge	163:e59c8e839560	3147	*/
AnnaBridge	163:e59c8e839560	3148	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3149	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	3150	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	3151	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	3152	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	3153	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	3154
AnnaBridge	163:e59c8e839560	3155	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3156	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	3157	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	3158	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	3159	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	3160	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	3161	/**
AnnaBridge	163:e59c8e839560	3162	* @}
AnnaBridge	163:e59c8e839560	3163	*/
AnnaBridge	163:e59c8e839560	3164
AnnaBridge	163:e59c8e839560	3165	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3166	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3167	* @{
AnnaBridge	163:e59c8e839560	3168	*/
AnnaBridge	163:e59c8e839560	3169	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3170	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	3171	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	3172	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	3173
AnnaBridge	163:e59c8e839560	3174	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3175	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	3176	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	3177	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	3178	/**
AnnaBridge	163:e59c8e839560	3179	* @}
AnnaBridge	163:e59c8e839560	3180	*/
AnnaBridge	163:e59c8e839560	3181
AnnaBridge	163:e59c8e839560	3182	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	3183	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	3184	* @{
AnnaBridge	163:e59c8e839560	3185	*/
AnnaBridge	163:e59c8e839560	3186	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3187	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3188	/**
AnnaBridge	163:e59c8e839560	3189	* @}
AnnaBridge	163:e59c8e839560	3190	*/
AnnaBridge	163:e59c8e839560	3191
AnnaBridge	163:e59c8e839560	3192	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3193	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3194	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3195	* power consumption.
AnnaBridge	163:e59c8e839560	3196	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3197	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3198	* @{
AnnaBridge	163:e59c8e839560	3199	*/
AnnaBridge	163:e59c8e839560	3200	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	3201	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	3202	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3203	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3204	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3205
AnnaBridge	163:e59c8e839560	3206	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	3207	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	3208	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3209	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3210	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3211	/**
AnnaBridge	163:e59c8e839560	3212	* @}
AnnaBridge	163:e59c8e839560	3213	*/
AnnaBridge	163:e59c8e839560	3214
AnnaBridge	163:e59c8e839560	3215	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3216	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3217	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3218	* power consumption.
AnnaBridge	163:e59c8e839560	3219	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3220	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3221	* @{
AnnaBridge	163:e59c8e839560	3222	*/
AnnaBridge	163:e59c8e839560	3223	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	3224
AnnaBridge	163:e59c8e839560	3225	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	3226	/**
AnnaBridge	163:e59c8e839560	3227	* @}
AnnaBridge	163:e59c8e839560	3228	*/
AnnaBridge	163:e59c8e839560	3229
AnnaBridge	163:e59c8e839560	3230	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3231	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3233	* power consumption.
AnnaBridge	163:e59c8e839560	3234	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3236	* @{
AnnaBridge	163:e59c8e839560	3237	*/
AnnaBridge	163:e59c8e839560	3238	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	3239	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	3240	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	3241	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	3242	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	3243
AnnaBridge	163:e59c8e839560	3244	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	3245	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	3246	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	3247	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	3248	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	3249	/**
AnnaBridge	163:e59c8e839560	3250	* @}
AnnaBridge	163:e59c8e839560	3251	*/
AnnaBridge	163:e59c8e839560	3252
AnnaBridge	163:e59c8e839560	3253	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3254	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3255	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3256	* power consumption.
AnnaBridge	163:e59c8e839560	3257	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3258	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3259	* @{
AnnaBridge	163:e59c8e839560	3260	*/
AnnaBridge	163:e59c8e839560	3261	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	3262	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	3263	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	3264
AnnaBridge	163:e59c8e839560	3265	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	3266	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	3267	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	3268	/**
AnnaBridge	163:e59c8e839560	3269	* @}
AnnaBridge	163:e59c8e839560	3270	*/
AnnaBridge	163:e59c8e839560	3271	#endif /* STM32F401xC \|\| STM32F401xE*/
AnnaBridge	163:e59c8e839560	3272	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	3273
AnnaBridge	163:e59c8e839560	3274	/-------------------------------- STM32F410xx -------------------------------/
AnnaBridge	163:e59c8e839560	3275	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	3276	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3277	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3278	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3279	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3280	* using it.
AnnaBridge	163:e59c8e839560	3281	* @{
AnnaBridge	163:e59c8e839560	3282	*/
AnnaBridge	163:e59c8e839560	3283	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3284	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3285	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3286	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3287	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3288	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3289	} while(0U)
AnnaBridge	163:e59c8e839560	3290	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3291	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3292	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	3293	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3294	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	3295	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3296	} while(0U)
AnnaBridge	163:e59c8e839560	3297	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	3298	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
AnnaBridge	163:e59c8e839560	3299	/**
AnnaBridge	163:e59c8e839560	3300	* @}
AnnaBridge	163:e59c8e839560	3301	*/
AnnaBridge	163:e59c8e839560	3302
AnnaBridge	163:e59c8e839560	3303	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3304	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3305	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3306	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3307	* using it.
AnnaBridge	163:e59c8e839560	3308	* @{
AnnaBridge	163:e59c8e839560	3309	*/
AnnaBridge	163:e59c8e839560	3310	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	3311	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
AnnaBridge	163:e59c8e839560	3312
AnnaBridge	163:e59c8e839560	3313	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	3314	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
AnnaBridge	163:e59c8e839560	3315	/**
AnnaBridge	163:e59c8e839560	3316	* @}
AnnaBridge	163:e59c8e839560	3317	*/
AnnaBridge	163:e59c8e839560	3318
AnnaBridge	163:e59c8e839560	3319	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3320	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	3321	* @{
AnnaBridge	163:e59c8e839560	3322	*/
AnnaBridge	163:e59c8e839560	3323	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3324	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	3326	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	3328	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3329	} while(0U)
AnnaBridge	163:e59c8e839560	3330	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3331	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3332	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	163:e59c8e839560	3333	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3334	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	163:e59c8e839560	3335	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3336	} while(0U)
AnnaBridge	163:e59c8e839560	3337	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3338	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3339	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	163:e59c8e839560	3340	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3341	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	163:e59c8e839560	3342	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3343	} while(0U)
AnnaBridge	163:e59c8e839560	3344	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3345	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3346	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	3347	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3348	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	3349	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3350	} while(0U)
AnnaBridge	163:e59c8e839560	3351	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3352	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3353	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	3354	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3355	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	3356	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3357	} while(0U)
AnnaBridge	163:e59c8e839560	3358
AnnaBridge	163:e59c8e839560	3359	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	3360	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
AnnaBridge	163:e59c8e839560	3361	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	163:e59c8e839560	3362	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	163:e59c8e839560	3363	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	163:e59c8e839560	3364	/**
AnnaBridge	163:e59c8e839560	3365	* @}
AnnaBridge	163:e59c8e839560	3366	*/
AnnaBridge	163:e59c8e839560	3367
AnnaBridge	163:e59c8e839560	3368	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3369	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3370	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3371	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3372	* using it.
AnnaBridge	163:e59c8e839560	3373	* @{
AnnaBridge	163:e59c8e839560	3374	*/
AnnaBridge	163:e59c8e839560	3375	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	3376	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
AnnaBridge	163:e59c8e839560	3377	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	163:e59c8e839560	3378	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	163:e59c8e839560	3379	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	163:e59c8e839560	3380
AnnaBridge	163:e59c8e839560	3381	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	3382	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
AnnaBridge	163:e59c8e839560	3383	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	163:e59c8e839560	3384	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	163:e59c8e839560	3385	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	163:e59c8e839560	3386	/**
AnnaBridge	163:e59c8e839560	3387	* @}
AnnaBridge	163:e59c8e839560	3388	*/
AnnaBridge	163:e59c8e839560	3389
AnnaBridge	163:e59c8e839560	3390	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3391	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	3392	* @{
AnnaBridge	163:e59c8e839560	3393	*/
AnnaBridge	163:e59c8e839560	3394	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3395	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3396	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	3397	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3398	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	3399	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3400	} while(0U)
AnnaBridge	163:e59c8e839560	3401	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3402	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3403	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	163:e59c8e839560	3404	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3405	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	163:e59c8e839560	3406	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3407	} while(0U)
AnnaBridge	163:e59c8e839560	3408	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	163:e59c8e839560	3409	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
AnnaBridge	163:e59c8e839560	3410	/**
AnnaBridge	163:e59c8e839560	3411	* @}
AnnaBridge	163:e59c8e839560	3412	*/
AnnaBridge	163:e59c8e839560	3413
AnnaBridge	163:e59c8e839560	3414	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3415	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	3416	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3417	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3418	* using it.
AnnaBridge	163:e59c8e839560	3419	* @{
AnnaBridge	163:e59c8e839560	3420	*/
AnnaBridge	163:e59c8e839560	3421	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	163:e59c8e839560	3422	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
AnnaBridge	163:e59c8e839560	3423
AnnaBridge	163:e59c8e839560	3424	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	163:e59c8e839560	3425	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
AnnaBridge	163:e59c8e839560	3426	/**
AnnaBridge	163:e59c8e839560	3427	* @}
AnnaBridge	163:e59c8e839560	3428	*/
AnnaBridge	163:e59c8e839560	3429
AnnaBridge	163:e59c8e839560	3430	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3431	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3432	* @{
AnnaBridge	163:e59c8e839560	3433	*/
AnnaBridge	163:e59c8e839560	3434	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3435	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	3436	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3437	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	3438	/**
AnnaBridge	163:e59c8e839560	3439	* @}
AnnaBridge	163:e59c8e839560	3440	*/
AnnaBridge	163:e59c8e839560	3441
AnnaBridge	163:e59c8e839560	3442	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3443	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3444	* @{
AnnaBridge	163:e59c8e839560	3445	*/
AnnaBridge	163:e59c8e839560	3446	#define __HAL_RCC_AHB2_FORCE_RESET()
AnnaBridge	163:e59c8e839560	3447	#define __HAL_RCC_AHB2_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	3448	/**
AnnaBridge	163:e59c8e839560	3449	* @}
AnnaBridge	163:e59c8e839560	3450	*/
AnnaBridge	163:e59c8e839560	3451
AnnaBridge	163:e59c8e839560	3452	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	3453	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	3454	* @{
AnnaBridge	163:e59c8e839560	3455	*/
AnnaBridge	163:e59c8e839560	3456	#define __HAL_RCC_AHB3_FORCE_RESET()
AnnaBridge	163:e59c8e839560	3457	#define __HAL_RCC_AHB3_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	3458	/**
AnnaBridge	163:e59c8e839560	3459	* @}
AnnaBridge	163:e59c8e839560	3460	*/
AnnaBridge	163:e59c8e839560	3461
AnnaBridge	163:e59c8e839560	3462	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3463	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3464	* @{
AnnaBridge	163:e59c8e839560	3465	*/
AnnaBridge	163:e59c8e839560	3466	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	3467	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	163:e59c8e839560	3468	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	3469	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	3470
AnnaBridge	163:e59c8e839560	3471	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	3472	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	163:e59c8e839560	3473	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	3474	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	3475	/**
AnnaBridge	163:e59c8e839560	3476	* @}
AnnaBridge	163:e59c8e839560	3477	*/
AnnaBridge	163:e59c8e839560	3478
AnnaBridge	163:e59c8e839560	3479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3480	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3481	* @{
AnnaBridge	163:e59c8e839560	3482	*/
AnnaBridge	163:e59c8e839560	3483	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	3484	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	3485	/**
AnnaBridge	163:e59c8e839560	3486	* @}
AnnaBridge	163:e59c8e839560	3487	*/
AnnaBridge	163:e59c8e839560	3488
AnnaBridge	163:e59c8e839560	3489	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3490	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3491	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3492	* power consumption.
AnnaBridge	163:e59c8e839560	3493	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3494	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3495	* @{
AnnaBridge	163:e59c8e839560	3496	*/
AnnaBridge	163:e59c8e839560	3497	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	3498	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3499	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3500	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3501
AnnaBridge	163:e59c8e839560	3502	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	3503	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3504	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3505	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3506	/**
AnnaBridge	163:e59c8e839560	3507	* @}
AnnaBridge	163:e59c8e839560	3508	*/
AnnaBridge	163:e59c8e839560	3509
AnnaBridge	163:e59c8e839560	3510	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3511	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3512	* @{
AnnaBridge	163:e59c8e839560	3513	*/
AnnaBridge	163:e59c8e839560	3514	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	3515	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	163:e59c8e839560	3516	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	163:e59c8e839560	3517	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	3518	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	3519
AnnaBridge	163:e59c8e839560	3520	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	3521	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	163:e59c8e839560	3522	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	163:e59c8e839560	3523	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	3524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	3525	/**
AnnaBridge	163:e59c8e839560	3526	* @}
AnnaBridge	163:e59c8e839560	3527	*/
AnnaBridge	163:e59c8e839560	3528
AnnaBridge	163:e59c8e839560	3529	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3530	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3531	* @{
AnnaBridge	163:e59c8e839560	3532	*/
AnnaBridge	163:e59c8e839560	3533	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	3534	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	163:e59c8e839560	3535	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	3536	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	163:e59c8e839560	3537	/**
AnnaBridge	163:e59c8e839560	3538	* @}
AnnaBridge	163:e59c8e839560	3539	*/
AnnaBridge	163:e59c8e839560	3540
AnnaBridge	163:e59c8e839560	3541	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	3542	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	3543
AnnaBridge	163:e59c8e839560	3544	/-------------------------------- STM32F411xx -------------------------------/
AnnaBridge	163:e59c8e839560	3545	#if defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	3546	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3547	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3548	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3549	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3550	* using it.
AnnaBridge	163:e59c8e839560	3551	* @{
AnnaBridge	163:e59c8e839560	3552	*/
AnnaBridge	163:e59c8e839560	3553	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3554	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	3556	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	3558	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3559	} while(0U)
AnnaBridge	163:e59c8e839560	3560	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3561	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	3563	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	3565	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3566	} while(0U)
AnnaBridge	163:e59c8e839560	3567	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3568	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	3570	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	3572	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3573	} while(0U)
AnnaBridge	163:e59c8e839560	3574	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3575	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3577	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3579	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3580	} while(0U)
AnnaBridge	163:e59c8e839560	3581	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	3582	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	3583	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	163:e59c8e839560	3584	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	3585	/**
AnnaBridge	163:e59c8e839560	3586	* @}
AnnaBridge	163:e59c8e839560	3587	*/
AnnaBridge	163:e59c8e839560	3588
AnnaBridge	163:e59c8e839560	3589	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3590	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3591	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3592	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3593	* using it.
AnnaBridge	163:e59c8e839560	3594	* @{
AnnaBridge	163:e59c8e839560	3595	*/
AnnaBridge	163:e59c8e839560	3596	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	3597	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	3598	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	3599	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	3600
AnnaBridge	163:e59c8e839560	3601	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	3602	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	3603	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	3604	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	3605	/**
AnnaBridge	163:e59c8e839560	3606	* @}
AnnaBridge	163:e59c8e839560	3607	*/
AnnaBridge	163:e59c8e839560	3608
AnnaBridge	163:e59c8e839560	3609	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3610	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	3611	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3612	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3613	* using it.
AnnaBridge	163:e59c8e839560	3614	* @{
AnnaBridge	163:e59c8e839560	3615	*/
AnnaBridge	163:e59c8e839560	3616	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	3617	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	3618	}while(0U)
AnnaBridge	163:e59c8e839560	3619
AnnaBridge	163:e59c8e839560	3620	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	3621	/**
AnnaBridge	163:e59c8e839560	3622	* @}
AnnaBridge	163:e59c8e839560	3623	*/
AnnaBridge	163:e59c8e839560	3624
AnnaBridge	163:e59c8e839560	3625	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3626	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	3627	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3628	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3629	* using it.
AnnaBridge	163:e59c8e839560	3630	* @{
AnnaBridge	163:e59c8e839560	3631	*/
AnnaBridge	163:e59c8e839560	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	3633	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	3634	/**
AnnaBridge	163:e59c8e839560	3635	* @}
AnnaBridge	163:e59c8e839560	3636	*/
AnnaBridge	163:e59c8e839560	3637
AnnaBridge	163:e59c8e839560	3638	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3639	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	3640	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3641	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3642	* using it.
AnnaBridge	163:e59c8e839560	3643	* @{
AnnaBridge	163:e59c8e839560	3644	*/
AnnaBridge	163:e59c8e839560	3645	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3646	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3647	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	3648	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3649	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	3650	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3651	} while(0U)
AnnaBridge	163:e59c8e839560	3652	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3653	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3654	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	3655	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3656	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	3657	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3658	} while(0U)
AnnaBridge	163:e59c8e839560	3659	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3660	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3661	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	3662	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3663	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	3664	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3665	} while(0U)
AnnaBridge	163:e59c8e839560	3666	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3667	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3668	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	3669	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3670	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	3671	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3672	} while(0U)
AnnaBridge	163:e59c8e839560	3673	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3674	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3675	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	3676	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3677	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	3678	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3679	} while(0U)
AnnaBridge	163:e59c8e839560	3680	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	3681	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	3682	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	3683	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	3684	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	3685	/**
AnnaBridge	163:e59c8e839560	3686	* @}
AnnaBridge	163:e59c8e839560	3687	*/
AnnaBridge	163:e59c8e839560	3688
AnnaBridge	163:e59c8e839560	3689	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3690	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3691	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3692	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3693	* using it.
AnnaBridge	163:e59c8e839560	3694	* @{
AnnaBridge	163:e59c8e839560	3695	*/
AnnaBridge	163:e59c8e839560	3696	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	3697	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3698	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	3699	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3700	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	3701
AnnaBridge	163:e59c8e839560	3702	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	3703	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3704	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	3705	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3706	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	3707	/**
AnnaBridge	163:e59c8e839560	3708	* @}
AnnaBridge	163:e59c8e839560	3709	*/
AnnaBridge	163:e59c8e839560	3710
AnnaBridge	163:e59c8e839560	3711	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3712	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	3713	* @{
AnnaBridge	163:e59c8e839560	3714	*/
AnnaBridge	163:e59c8e839560	3715	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3716	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3717	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	3718	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3719	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	3720	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3721	} while(0U)
AnnaBridge	163:e59c8e839560	3722	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3723	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	3725	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	3727	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3728	} while(0U)
AnnaBridge	163:e59c8e839560	3729	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3730	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3731	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	3732	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3733	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	3734	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3735	} while(0U)
AnnaBridge	163:e59c8e839560	3736	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3737	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3738	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	3739	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3740	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	3741	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3742	} while(0U)
AnnaBridge	163:e59c8e839560	3743	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	3744	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	3745	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	3746	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	163:e59c8e839560	3747	/**
AnnaBridge	163:e59c8e839560	3748	* @}
AnnaBridge	163:e59c8e839560	3749	*/
AnnaBridge	163:e59c8e839560	3750
AnnaBridge	163:e59c8e839560	3751	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	3752	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	3753	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3754	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3755	* using it.
AnnaBridge	163:e59c8e839560	3756	* @{
AnnaBridge	163:e59c8e839560	3757	*/
AnnaBridge	163:e59c8e839560	3758	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	3759	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	3760	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	163:e59c8e839560	3761	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	163:e59c8e839560	3762
AnnaBridge	163:e59c8e839560	3763	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	3764	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	3765	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	163:e59c8e839560	3766	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	163:e59c8e839560	3767	/**
AnnaBridge	163:e59c8e839560	3768	* @}
AnnaBridge	163:e59c8e839560	3769	*/
AnnaBridge	163:e59c8e839560	3770
AnnaBridge	163:e59c8e839560	3771	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3772	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3773	* @{
AnnaBridge	163:e59c8e839560	3774	*/
AnnaBridge	163:e59c8e839560	3775	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	3776	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	3777	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3778
AnnaBridge	163:e59c8e839560	3779	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	3780	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	3781	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	3782	/**
AnnaBridge	163:e59c8e839560	3783	* @}
AnnaBridge	163:e59c8e839560	3784	*/
AnnaBridge	163:e59c8e839560	3785
AnnaBridge	163:e59c8e839560	3786	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3787	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3788	* @{
AnnaBridge	163:e59c8e839560	3789	*/
AnnaBridge	163:e59c8e839560	3790	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3791	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	3792
AnnaBridge	163:e59c8e839560	3793	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3794	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	3795	/**
AnnaBridge	163:e59c8e839560	3796	* @}
AnnaBridge	163:e59c8e839560	3797	*/
AnnaBridge	163:e59c8e839560	3798
AnnaBridge	163:e59c8e839560	3799	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	3800	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	3801	* @{
AnnaBridge	163:e59c8e839560	3802	*/
AnnaBridge	163:e59c8e839560	3803	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	3804	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	3805	/**
AnnaBridge	163:e59c8e839560	3806	* @}
AnnaBridge	163:e59c8e839560	3807	*/
AnnaBridge	163:e59c8e839560	3808
AnnaBridge	163:e59c8e839560	3809	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	3810	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	3811	* @{
AnnaBridge	163:e59c8e839560	3812	*/
AnnaBridge	163:e59c8e839560	3813	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	3814	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	3815	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	3816	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	3817	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	3818
AnnaBridge	163:e59c8e839560	3819	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	3820	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	3821	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	3822	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	3823	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	3824	/**
AnnaBridge	163:e59c8e839560	3825	* @}
AnnaBridge	163:e59c8e839560	3826	*/
AnnaBridge	163:e59c8e839560	3827
AnnaBridge	163:e59c8e839560	3828	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	3829	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	3830	* @{
AnnaBridge	163:e59c8e839560	3831	*/
AnnaBridge	163:e59c8e839560	3832	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	3833	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	3834	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	3835	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	3836
AnnaBridge	163:e59c8e839560	3837	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	3838	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	3839	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	3840	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	3841	/**
AnnaBridge	163:e59c8e839560	3842	* @}
AnnaBridge	163:e59c8e839560	3843	*/
AnnaBridge	163:e59c8e839560	3844
AnnaBridge	163:e59c8e839560	3845	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3846	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3847	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3848	* power consumption.
AnnaBridge	163:e59c8e839560	3849	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3850	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3851	* @{
AnnaBridge	163:e59c8e839560	3852	*/
AnnaBridge	163:e59c8e839560	3853	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	3854	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	3855	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3856	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3857	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3858
AnnaBridge	163:e59c8e839560	3859	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	3860	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	3861	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	3862	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	3863	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	3864	/**
AnnaBridge	163:e59c8e839560	3865	* @}
AnnaBridge	163:e59c8e839560	3866	*/
AnnaBridge	163:e59c8e839560	3867
AnnaBridge	163:e59c8e839560	3868	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3869	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3870	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	3871	* power consumption.
AnnaBridge	163:e59c8e839560	3872	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	3873	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	3874	* @{
AnnaBridge	163:e59c8e839560	3875	*/
AnnaBridge	163:e59c8e839560	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	3877	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	3878	/**
AnnaBridge	163:e59c8e839560	3879	* @}
AnnaBridge	163:e59c8e839560	3880	*/
AnnaBridge	163:e59c8e839560	3881
AnnaBridge	163:e59c8e839560	3882	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3883	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3884	* @{
AnnaBridge	163:e59c8e839560	3885	*/
AnnaBridge	163:e59c8e839560	3886	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	3887	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	3888	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	3889	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	3890	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	3891
AnnaBridge	163:e59c8e839560	3892	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	3893	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	3894	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	3895	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	3896	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	3897	/**
AnnaBridge	163:e59c8e839560	3898	* @}
AnnaBridge	163:e59c8e839560	3899	*/
AnnaBridge	163:e59c8e839560	3900
AnnaBridge	163:e59c8e839560	3901	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	3902	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	3903	* @{
AnnaBridge	163:e59c8e839560	3904	*/
AnnaBridge	163:e59c8e839560	3905	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	3906	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	3907	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	3908	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	3909
AnnaBridge	163:e59c8e839560	3910	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	3911	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	3912	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	3913	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	3914	/**
AnnaBridge	163:e59c8e839560	3915	* @}
AnnaBridge	163:e59c8e839560	3916	*/
AnnaBridge	163:e59c8e839560	3917	#endif /* STM32F411xE */
AnnaBridge	163:e59c8e839560	3918	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	3919
AnnaBridge	163:e59c8e839560	3920	/---------------------------------- STM32F446xx -----------------------------/
AnnaBridge	163:e59c8e839560	3921	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	3922	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	3923	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	3924	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	3925	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	3926	* using it.
AnnaBridge	163:e59c8e839560	3927	* @{
AnnaBridge	163:e59c8e839560	3928	*/
AnnaBridge	163:e59c8e839560	3929	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3930	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3931	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	3932	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3933	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	163:e59c8e839560	3934	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3935	} while(0U)
AnnaBridge	163:e59c8e839560	3936	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3937	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3938	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	3939	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3940	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	163:e59c8e839560	3941	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3942	} while(0U)
AnnaBridge	163:e59c8e839560	3943	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3944	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3945	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3946	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3947	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	3948	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3949	} while(0U)
AnnaBridge	163:e59c8e839560	3950	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3951	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3952	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	3953	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3954	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	3955	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3956	} while(0U)
AnnaBridge	163:e59c8e839560	3957	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3958	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3959	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	3960	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3961	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	3962	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3963	} while(0U)
AnnaBridge	163:e59c8e839560	3964	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3965	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3966	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	3967	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3968	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	3969	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3970	} while(0U)
AnnaBridge	163:e59c8e839560	3971	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3972	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3973	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	3974	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3975	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	3976	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3977	} while(0U)
AnnaBridge	163:e59c8e839560	3978	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3979	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3980	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	3981	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3982	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	163:e59c8e839560	3983	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3984	} while(0U)
AnnaBridge	163:e59c8e839560	3985	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	3986	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	3987	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	3988	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	3989	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	163:e59c8e839560	3990	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	3991	} while(0U)
AnnaBridge	163:e59c8e839560	3992	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	3993	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	3994	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	163:e59c8e839560	3995	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	163:e59c8e839560	3996	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	163:e59c8e839560	3997	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	163:e59c8e839560	3998	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	163:e59c8e839560	3999	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	163:e59c8e839560	4000	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	4001	/**
AnnaBridge	163:e59c8e839560	4002	* @}
AnnaBridge	163:e59c8e839560	4003	*/
AnnaBridge	163:e59c8e839560	4004
AnnaBridge	163:e59c8e839560	4005	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4006	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	4007	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4008	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4009	* using it.
AnnaBridge	163:e59c8e839560	4010	* @{
AnnaBridge	163:e59c8e839560	4011	*/
AnnaBridge	163:e59c8e839560	4012	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	4013	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	4014	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	163:e59c8e839560	4015	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	163:e59c8e839560	4016	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	163:e59c8e839560	4017	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	4018	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	4019	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
AnnaBridge	163:e59c8e839560	4020	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	4021
AnnaBridge	163:e59c8e839560	4022	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	4023	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	4024	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	163:e59c8e839560	4025	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	163:e59c8e839560	4026	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	163:e59c8e839560	4027	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	163:e59c8e839560	4028	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	4029	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	4030	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	4031	/**
AnnaBridge	163:e59c8e839560	4032	* @}
AnnaBridge	163:e59c8e839560	4033	*/
AnnaBridge	163:e59c8e839560	4034
AnnaBridge	163:e59c8e839560	4035	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4036	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	4037	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4038	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4039	* using it.
AnnaBridge	163:e59c8e839560	4040	* @{
AnnaBridge	163:e59c8e839560	4041	*/
AnnaBridge	163:e59c8e839560	4042	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4043	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4044	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	4045	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4046	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	163:e59c8e839560	4047	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4048	} while(0U)
AnnaBridge	163:e59c8e839560	4049	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	163:e59c8e839560	4050	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	4051	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	4052	}while(0U)
AnnaBridge	163:e59c8e839560	4053
AnnaBridge	163:e59c8e839560	4054	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	4055
AnnaBridge	163:e59c8e839560	4056	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4057	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4058	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	4059	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4060	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	4061	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4062	} while(0U)
AnnaBridge	163:e59c8e839560	4063	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	163:e59c8e839560	4064	/**
AnnaBridge	163:e59c8e839560	4065	* @}
AnnaBridge	163:e59c8e839560	4066	*/
AnnaBridge	163:e59c8e839560	4067
AnnaBridge	163:e59c8e839560	4068	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4069	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	4070	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4071	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4072	* using it.
AnnaBridge	163:e59c8e839560	4073	* @{
AnnaBridge	163:e59c8e839560	4074	*/
AnnaBridge	163:e59c8e839560	4075	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	163:e59c8e839560	4076	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	163:e59c8e839560	4077
AnnaBridge	163:e59c8e839560	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	4079	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	4080
AnnaBridge	163:e59c8e839560	4081	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	163:e59c8e839560	4082	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	163:e59c8e839560	4083	/**
AnnaBridge	163:e59c8e839560	4084	* @}
AnnaBridge	163:e59c8e839560	4085	*/
AnnaBridge	163:e59c8e839560	4086
AnnaBridge	163:e59c8e839560	4087	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4088	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	4089	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4090	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4091	* using it.
AnnaBridge	163:e59c8e839560	4092	* @{
AnnaBridge	163:e59c8e839560	4093	*/
AnnaBridge	163:e59c8e839560	4094	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4095	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4096	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	163:e59c8e839560	4097	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4098	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	163:e59c8e839560	4099	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4100	} while(0U)
AnnaBridge	163:e59c8e839560	4101	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4102	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4103	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	4104	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4105	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	4106	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4107	} while(0U)
AnnaBridge	163:e59c8e839560	4108
AnnaBridge	163:e59c8e839560	4109	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge	163:e59c8e839560	4110	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	163:e59c8e839560	4111	/**
AnnaBridge	163:e59c8e839560	4112	* @}
AnnaBridge	163:e59c8e839560	4113	*/
AnnaBridge	163:e59c8e839560	4114
AnnaBridge	163:e59c8e839560	4115	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4116	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	4117	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4118	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4119	* using it.
AnnaBridge	163:e59c8e839560	4120	* @{
AnnaBridge	163:e59c8e839560	4121	*/
AnnaBridge	163:e59c8e839560	4122	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge	163:e59c8e839560	4123	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	4124
AnnaBridge	163:e59c8e839560	4125	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge	163:e59c8e839560	4126	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	163:e59c8e839560	4127	/**
AnnaBridge	163:e59c8e839560	4128	* @}
AnnaBridge	163:e59c8e839560	4129	*/
AnnaBridge	163:e59c8e839560	4130
AnnaBridge	163:e59c8e839560	4131	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4132	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	4133	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4134	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4135	* using it.
AnnaBridge	163:e59c8e839560	4136	* @{
AnnaBridge	163:e59c8e839560	4137	*/
AnnaBridge	163:e59c8e839560	4138	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4139	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4140	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	4141	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4142	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	4143	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4144	} while(0U)
AnnaBridge	163:e59c8e839560	4145	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4146	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4147	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	4148	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4149	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	4150	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4151	} while(0U)
AnnaBridge	163:e59c8e839560	4152	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4153	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4154	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	4155	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4156	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	4157	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4158	} while(0U)
AnnaBridge	163:e59c8e839560	4159	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4160	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4161	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	4162	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4163	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	4164	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4165	} while(0U)
AnnaBridge	163:e59c8e839560	4166	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4167	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4168	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	4169	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4170	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	4171	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4172	} while(0U)
AnnaBridge	163:e59c8e839560	4173	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4174	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4175	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	163:e59c8e839560	4176	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4177	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	163:e59c8e839560	4178	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4179	} while(0U)
AnnaBridge	163:e59c8e839560	4180	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4181	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4182	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	4183	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4184	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	4185	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4186	} while(0U)
AnnaBridge	163:e59c8e839560	4187	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4188	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4189	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	4190	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4191	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	4192	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4193	} while(0U)
AnnaBridge	163:e59c8e839560	4194	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4195	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4196	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	4197	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4198	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	4199	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4200	} while(0U)
AnnaBridge	163:e59c8e839560	4201	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4202	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4203	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	4204	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4205	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	4206	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4207	} while(0U)
AnnaBridge	163:e59c8e839560	4208	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4209	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4210	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	4211	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4212	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	4213	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4214	} while(0U)
AnnaBridge	163:e59c8e839560	4215	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4216	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	4218	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	4220	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4221	} while(0U)
AnnaBridge	163:e59c8e839560	4222	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4223	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	163:e59c8e839560	4225	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	163:e59c8e839560	4227	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4228	} while(0U)
AnnaBridge	163:e59c8e839560	4229	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4230	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	4232	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	4234	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4235	} while(0U)
AnnaBridge	163:e59c8e839560	4236	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4237	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4238	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	4239	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4240	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	4241	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4242	} while(0U)
AnnaBridge	163:e59c8e839560	4243	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4244	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4245	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	4246	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4247	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	4248	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4249	} while(0U)
AnnaBridge	163:e59c8e839560	4250	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4251	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4252	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	4253	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4254	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	4255	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4256	} while(0U)
AnnaBridge	163:e59c8e839560	4257	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4258	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4259	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	4260	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4261	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	4262	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4263	} while(0U)
AnnaBridge	163:e59c8e839560	4264	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4265	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4266	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	4267	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4268	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	4269	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4270	} while(0U)
AnnaBridge	163:e59c8e839560	4271	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	4272	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	4273	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	4274	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	4275	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	4276	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	4277	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	163:e59c8e839560	4278	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	163:e59c8e839560	4279	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	163:e59c8e839560	4280	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	163:e59c8e839560	4281	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
AnnaBridge	163:e59c8e839560	4282	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	163:e59c8e839560	4283	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	163:e59c8e839560	4284	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	163:e59c8e839560	4285	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	163:e59c8e839560	4286	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	163:e59c8e839560	4287	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	163:e59c8e839560	4288	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	163:e59c8e839560	4289	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	163:e59c8e839560	4290	/**
AnnaBridge	163:e59c8e839560	4291	* @}
AnnaBridge	163:e59c8e839560	4292	*/
AnnaBridge	163:e59c8e839560	4293
AnnaBridge	163:e59c8e839560	4294	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4295	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	4296	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4297	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4298	* using it.
AnnaBridge	163:e59c8e839560	4299	* @{
AnnaBridge	163:e59c8e839560	4300	*/
AnnaBridge	163:e59c8e839560	4301	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	4302	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	4303	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	4304	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	4305	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	4306	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	4307	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	163:e59c8e839560	4308	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	163:e59c8e839560	4309	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	163:e59c8e839560	4310	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	163:e59c8e839560	4311	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
AnnaBridge	163:e59c8e839560	4312	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	163:e59c8e839560	4313	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	163:e59c8e839560	4314	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	163:e59c8e839560	4315	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	163:e59c8e839560	4316	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	163:e59c8e839560	4317	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	163:e59c8e839560	4318	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	163:e59c8e839560	4319	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	163:e59c8e839560	4320
AnnaBridge	163:e59c8e839560	4321	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	4322	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	4323	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	4324	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	4325	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	4326	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	4327	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	163:e59c8e839560	4328	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	163:e59c8e839560	4329	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	163:e59c8e839560	4330	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	163:e59c8e839560	4331	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
AnnaBridge	163:e59c8e839560	4332	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	163:e59c8e839560	4333	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	163:e59c8e839560	4334	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	163:e59c8e839560	4335	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	163:e59c8e839560	4336	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	163:e59c8e839560	4337	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	163:e59c8e839560	4338	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	163:e59c8e839560	4339	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	163:e59c8e839560	4340	/**
AnnaBridge	163:e59c8e839560	4341	* @}
AnnaBridge	163:e59c8e839560	4342	*/
AnnaBridge	163:e59c8e839560	4343
AnnaBridge	163:e59c8e839560	4344	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4345	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	4346	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4347	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4348	* using it.
AnnaBridge	163:e59c8e839560	4349	* @{
AnnaBridge	163:e59c8e839560	4350	*/
AnnaBridge	163:e59c8e839560	4351	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4352	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4353	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	4354	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4355	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	4356	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4357	} while(0U)
AnnaBridge	163:e59c8e839560	4358	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4359	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4360	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	4361	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4362	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	163:e59c8e839560	4363	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4364	} while(0U)
AnnaBridge	163:e59c8e839560	4365	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4366	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4367	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	4368	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4369	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	163:e59c8e839560	4370	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4371	} while(0U)
AnnaBridge	163:e59c8e839560	4372	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4373	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4374	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	4375	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4376	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	4377	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4378	} while(0U)
AnnaBridge	163:e59c8e839560	4379	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4380	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4381	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	163:e59c8e839560	4382	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4383	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	163:e59c8e839560	4384	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4385	} while(0U)
AnnaBridge	163:e59c8e839560	4386	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4387	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4388	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	4389	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4390	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	4391	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4392	} while(0U)
AnnaBridge	163:e59c8e839560	4393	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4394	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	4396	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	4398	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4399	} while(0U)
AnnaBridge	163:e59c8e839560	4400	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4401	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	4403	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	4405	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4406	} while(0U)
AnnaBridge	163:e59c8e839560	4407	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	4408	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	4409	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	4410	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	163:e59c8e839560	4411	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	163:e59c8e839560	4412	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	163:e59c8e839560	4413	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	163:e59c8e839560	4414	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
AnnaBridge	163:e59c8e839560	4415	/**
AnnaBridge	163:e59c8e839560	4416	* @}
AnnaBridge	163:e59c8e839560	4417	*/
AnnaBridge	163:e59c8e839560	4418
AnnaBridge	163:e59c8e839560	4419	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4420	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	4421	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4422	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4423	* using it.
AnnaBridge	163:e59c8e839560	4424	* @{
AnnaBridge	163:e59c8e839560	4425	*/
AnnaBridge	163:e59c8e839560	4426	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	4427	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	4428	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	163:e59c8e839560	4429	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	163:e59c8e839560	4430	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	4431	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	163:e59c8e839560	4432	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	4433	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
AnnaBridge	163:e59c8e839560	4434
AnnaBridge	163:e59c8e839560	4435	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	4436	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	4437	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	163:e59c8e839560	4438	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	163:e59c8e839560	4439	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	4440	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	163:e59c8e839560	4441	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	4442	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
AnnaBridge	163:e59c8e839560	4443	/**
AnnaBridge	163:e59c8e839560	4444	* @}
AnnaBridge	163:e59c8e839560	4445	*/
AnnaBridge	163:e59c8e839560	4446
AnnaBridge	163:e59c8e839560	4447	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	4448	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	4449	* @{
AnnaBridge	163:e59c8e839560	4450	*/
AnnaBridge	163:e59c8e839560	4451	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	4452	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	4453	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	4454	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	4455	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	4456	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	4457
AnnaBridge	163:e59c8e839560	4458	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	4459	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	4460	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	4461	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	4462	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	163:e59c8e839560	4463	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	4464	/**
AnnaBridge	163:e59c8e839560	4465	* @}
AnnaBridge	163:e59c8e839560	4466	*/
AnnaBridge	163:e59c8e839560	4467
AnnaBridge	163:e59c8e839560	4468	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	4469	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	4470	* @{
AnnaBridge	163:e59c8e839560	4471	*/
AnnaBridge	163:e59c8e839560	4472	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	4473	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	4474	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	4475	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	4476
AnnaBridge	163:e59c8e839560	4477	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	4478	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	4479	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	4480	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	163:e59c8e839560	4481	/**
AnnaBridge	163:e59c8e839560	4482	* @}
AnnaBridge	163:e59c8e839560	4483	*/
AnnaBridge	163:e59c8e839560	4484
AnnaBridge	163:e59c8e839560	4485	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	4486	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	4487	* @{
AnnaBridge	163:e59c8e839560	4488	*/
AnnaBridge	163:e59c8e839560	4489	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	4490	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	4491
AnnaBridge	163:e59c8e839560	4492	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
AnnaBridge	163:e59c8e839560	4493	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	4494
AnnaBridge	163:e59c8e839560	4495	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge	163:e59c8e839560	4496	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	4497	/**
AnnaBridge	163:e59c8e839560	4498	* @}
AnnaBridge	163:e59c8e839560	4499	*/
AnnaBridge	163:e59c8e839560	4500
AnnaBridge	163:e59c8e839560	4501	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	4502	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	4503	* @{
AnnaBridge	163:e59c8e839560	4504	*/
AnnaBridge	163:e59c8e839560	4505	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	4506	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	4507	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	4508	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	4509	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	4510	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	163:e59c8e839560	4511	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	4512	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	4513	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	4514	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	4515	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	4516	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	4517	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	163:e59c8e839560	4518	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	4519	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	4520	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	4521	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	4522	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	4523	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	4524
AnnaBridge	163:e59c8e839560	4525	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	4526	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	4527	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	4528	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	4529	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	4530	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	4531	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	4532	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	4533	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	4534	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	4535	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	163:e59c8e839560	4536	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	4537	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	4538	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	4539	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	4540	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	4541	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	4542	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	163:e59c8e839560	4543	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	4544	/**
AnnaBridge	163:e59c8e839560	4545	* @}
AnnaBridge	163:e59c8e839560	4546	*/
AnnaBridge	163:e59c8e839560	4547
AnnaBridge	163:e59c8e839560	4548	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	4549	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	4550	* @{
AnnaBridge	163:e59c8e839560	4551	*/
AnnaBridge	163:e59c8e839560	4552	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	4553	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	4554	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
AnnaBridge	163:e59c8e839560	4555	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	4556	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	4557	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	4558
AnnaBridge	163:e59c8e839560	4559	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	4560	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	4561	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	4562	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	4563	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	4564	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
AnnaBridge	163:e59c8e839560	4565	/**
AnnaBridge	163:e59c8e839560	4566	* @}
AnnaBridge	163:e59c8e839560	4567	*/
AnnaBridge	163:e59c8e839560	4568
AnnaBridge	163:e59c8e839560	4569	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	4570	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	4571	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	4572	* power consumption.
AnnaBridge	163:e59c8e839560	4573	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	4574	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	4575	* @{
AnnaBridge	163:e59c8e839560	4576	*/
AnnaBridge	163:e59c8e839560	4577	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	4578	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	4579	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	4580	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	4581	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	4582	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	4583	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	4584	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	4585	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	4586	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	4587	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	4588
AnnaBridge	163:e59c8e839560	4589	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	4590	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	4591	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	4592	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	4593	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	4594	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	163:e59c8e839560	4595	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	163:e59c8e839560	4596	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	4597	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	4598	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	4599	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	163:e59c8e839560	4600	/**
AnnaBridge	163:e59c8e839560	4601	* @}
AnnaBridge	163:e59c8e839560	4602	*/
AnnaBridge	163:e59c8e839560	4603
AnnaBridge	163:e59c8e839560	4604	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	4605	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	4606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	4607	* power consumption.
AnnaBridge	163:e59c8e839560	4608	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	4609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	4610	* @{
AnnaBridge	163:e59c8e839560	4611	*/
AnnaBridge	163:e59c8e839560	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	4613	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	4614
AnnaBridge	163:e59c8e839560	4615	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	4616	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	4617
AnnaBridge	163:e59c8e839560	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	4619	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	163:e59c8e839560	4620	/**
AnnaBridge	163:e59c8e839560	4621	* @}
AnnaBridge	163:e59c8e839560	4622	*/
AnnaBridge	163:e59c8e839560	4623
AnnaBridge	163:e59c8e839560	4624	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	4625	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	4626	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	4627	* power consumption.
AnnaBridge	163:e59c8e839560	4628	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	4629	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	4630	* @{
AnnaBridge	163:e59c8e839560	4631	*/
AnnaBridge	163:e59c8e839560	4632	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	163:e59c8e839560	4633	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	4634
AnnaBridge	163:e59c8e839560	4635	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	163:e59c8e839560	4636	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	4637	/**
AnnaBridge	163:e59c8e839560	4638	* @}
AnnaBridge	163:e59c8e839560	4639	*/
AnnaBridge	163:e59c8e839560	4640
AnnaBridge	163:e59c8e839560	4641	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	4642	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	4643	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	4644	* power consumption.
AnnaBridge	163:e59c8e839560	4645	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	4646	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	4647	* @{
AnnaBridge	163:e59c8e839560	4648	*/
AnnaBridge	163:e59c8e839560	4649	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	4650	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	4651	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	4652	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	4653	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	4654	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	163:e59c8e839560	4655	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	4656	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	4657	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	4658	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	4659	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	4660	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	4661	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
AnnaBridge	163:e59c8e839560	4662	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	4663	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	4664	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	4665	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	4666	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	4667	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	4668
AnnaBridge	163:e59c8e839560	4669	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	4670	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	4671	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	4672	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	4673	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	4674	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	4675	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	4676	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	4677	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	4678	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	4679	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	163:e59c8e839560	4680	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	4681	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	4682	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	4683	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	4684	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	4685	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	4686	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
AnnaBridge	163:e59c8e839560	4687	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	4688	/**
AnnaBridge	163:e59c8e839560	4689	* @}
AnnaBridge	163:e59c8e839560	4690	*/
AnnaBridge	163:e59c8e839560	4691
AnnaBridge	163:e59c8e839560	4692	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	4693	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	4694	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	4695	* power consumption.
AnnaBridge	163:e59c8e839560	4696	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	4697	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	4698	* @{
AnnaBridge	163:e59c8e839560	4699	*/
AnnaBridge	163:e59c8e839560	4700	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	4701	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	4702	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	4703	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	4704	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	163:e59c8e839560	4705	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	4706	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	4707	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	4708
AnnaBridge	163:e59c8e839560	4709	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	4710	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	4711	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	4712	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	4713	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	163:e59c8e839560	4714	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	163:e59c8e839560	4715	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	4716	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	163:e59c8e839560	4717	/**
AnnaBridge	163:e59c8e839560	4718	* @}
AnnaBridge	163:e59c8e839560	4719	*/
AnnaBridge	163:e59c8e839560	4720
AnnaBridge	163:e59c8e839560	4721	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	4722	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	4723
AnnaBridge	163:e59c8e839560	4724	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
AnnaBridge	163:e59c8e839560	4725	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4726	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4727	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	4728	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4729	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4730	* using it.
AnnaBridge	163:e59c8e839560	4731	* @{
AnnaBridge	163:e59c8e839560	4732	*/
AnnaBridge	163:e59c8e839560	4733	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4734	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4735	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	4736	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4737	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	4738	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4739	} while(0U)
AnnaBridge	163:e59c8e839560	4740	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4741	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4742	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	4743	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4744	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	4745	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4746	} while(0U)
AnnaBridge	163:e59c8e839560	4747	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4748	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4749	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	4750	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4751	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	4752	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4753	} while(0U)
AnnaBridge	163:e59c8e839560	4754	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4755	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4756	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	4757	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4758	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	4759	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4760	} while(0U)
AnnaBridge	163:e59c8e839560	4761	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4762	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4763	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	4764	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4765	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	163:e59c8e839560	4766	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4767	} while(0U)
AnnaBridge	163:e59c8e839560	4768
AnnaBridge	163:e59c8e839560	4769	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	163:e59c8e839560	4770	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	4771	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	163:e59c8e839560	4772	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	163:e59c8e839560	4773	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	163:e59c8e839560	4774	/**
AnnaBridge	163:e59c8e839560	4775	* @}
AnnaBridge	163:e59c8e839560	4776	*/
AnnaBridge	163:e59c8e839560	4777
AnnaBridge	163:e59c8e839560	4778	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4779	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	163:e59c8e839560	4780	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4781	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4782	* using it.
AnnaBridge	163:e59c8e839560	4783	* @{
AnnaBridge	163:e59c8e839560	4784	*/
AnnaBridge	163:e59c8e839560	4785	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	4786	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	4787	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	163:e59c8e839560	4788	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	163:e59c8e839560	4789	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	4790
AnnaBridge	163:e59c8e839560	4791	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	4792	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	4793	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	163:e59c8e839560	4794	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	163:e59c8e839560	4795	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	4796	/**
AnnaBridge	163:e59c8e839560	4797	* @}
AnnaBridge	163:e59c8e839560	4798	*/
AnnaBridge	163:e59c8e839560	4799
AnnaBridge	163:e59c8e839560	4800	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4801	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	4802	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4803	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4804	* using it.
AnnaBridge	163:e59c8e839560	4805	* @{
AnnaBridge	163:e59c8e839560	4806	*/
AnnaBridge	163:e59c8e839560	4807	#if defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4808	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4809	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4810	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	163:e59c8e839560	4811	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4812	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	163:e59c8e839560	4813	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4814	} while(0U)
AnnaBridge	163:e59c8e839560	4815
AnnaBridge	163:e59c8e839560	4816	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
AnnaBridge	163:e59c8e839560	4817	#endif /* STM32F423xx */
AnnaBridge	163:e59c8e839560	4818
AnnaBridge	163:e59c8e839560	4819	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4820	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4821	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	4822	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4823	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	163:e59c8e839560	4824	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4825	} while(0U)
AnnaBridge	163:e59c8e839560	4826	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	163:e59c8e839560	4827
AnnaBridge	163:e59c8e839560	4828	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	163:e59c8e839560	4829	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	163:e59c8e839560	4830	}while(0U)
AnnaBridge	163:e59c8e839560	4831
AnnaBridge	163:e59c8e839560	4832	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	163:e59c8e839560	4833	/**
AnnaBridge	163:e59c8e839560	4834	* @}
AnnaBridge	163:e59c8e839560	4835	*/
AnnaBridge	163:e59c8e839560	4836
AnnaBridge	163:e59c8e839560	4837	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4838	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	163:e59c8e839560	4839	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4840	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4841	* using it.
AnnaBridge	163:e59c8e839560	4842	* @{
AnnaBridge	163:e59c8e839560	4843	*/
AnnaBridge	163:e59c8e839560	4844	#if defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4845	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
AnnaBridge	163:e59c8e839560	4846	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
AnnaBridge	163:e59c8e839560	4847	#endif /* STM32F423xx */
AnnaBridge	163:e59c8e839560	4848
AnnaBridge	163:e59c8e839560	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	163:e59c8e839560	4850	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	163:e59c8e839560	4851
AnnaBridge	163:e59c8e839560	4852	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	163:e59c8e839560	4853	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	163:e59c8e839560	4854	/**
AnnaBridge	163:e59c8e839560	4855	* @}
AnnaBridge	163:e59c8e839560	4856	*/
AnnaBridge	163:e59c8e839560	4857
AnnaBridge	163:e59c8e839560	4858	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4859	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	4860	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4861	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4862	* using it.
AnnaBridge	163:e59c8e839560	4863	* @{
AnnaBridge	163:e59c8e839560	4864	*/
AnnaBridge	163:e59c8e839560	4865	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4866	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4867	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4868	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	163:e59c8e839560	4869	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4870	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	163:e59c8e839560	4871	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4872	} while(0U)
AnnaBridge	163:e59c8e839560	4873	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4874	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4875	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	4876	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4877	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	163:e59c8e839560	4878	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4879	} while(0U)
AnnaBridge	163:e59c8e839560	4880
AnnaBridge	163:e59c8e839560	4881	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
AnnaBridge	163:e59c8e839560	4882	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	163:e59c8e839560	4883	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	4884	/**
AnnaBridge	163:e59c8e839560	4885	* @}
AnnaBridge	163:e59c8e839560	4886	*/
AnnaBridge	163:e59c8e839560	4887
AnnaBridge	163:e59c8e839560	4888	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	4889	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	163:e59c8e839560	4890	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4891	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4892	* using it.
AnnaBridge	163:e59c8e839560	4893	* @{
AnnaBridge	163:e59c8e839560	4894	*/
AnnaBridge	163:e59c8e839560	4895	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4896	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
AnnaBridge	163:e59c8e839560	4897	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	163:e59c8e839560	4898
AnnaBridge	163:e59c8e839560	4899	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
AnnaBridge	163:e59c8e839560	4900	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	163:e59c8e839560	4901	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	4902
AnnaBridge	163:e59c8e839560	4903	/**
AnnaBridge	163:e59c8e839560	4904	* @}
AnnaBridge	163:e59c8e839560	4905	*/
AnnaBridge	163:e59c8e839560	4906
AnnaBridge	163:e59c8e839560	4907	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	4908	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	4909	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	4910	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	4911	* using it.
AnnaBridge	163:e59c8e839560	4912	* @{
AnnaBridge	163:e59c8e839560	4913	*/
AnnaBridge	163:e59c8e839560	4914	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4915	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	4917	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	4919	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4920	} while(0U)
AnnaBridge	163:e59c8e839560	4921	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4922	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	4924	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	4926	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4927	} while(0U)
AnnaBridge	163:e59c8e839560	4928	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4929	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	4931	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	4933	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4934	} while(0U)
AnnaBridge	163:e59c8e839560	4935	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4936	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	4938	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	4940	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4941	} while(0U)
AnnaBridge	163:e59c8e839560	4942	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4943	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	4945	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	4947	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4948	} while(0U)
AnnaBridge	163:e59c8e839560	4949	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4950	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4951	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4952	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	163:e59c8e839560	4953	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4954	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	163:e59c8e839560	4955	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4956	} while(0U)
AnnaBridge	163:e59c8e839560	4957	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	4958	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4959	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4960	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	163:e59c8e839560	4961	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4962	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	163:e59c8e839560	4963	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4964	} while(0U)
AnnaBridge	163:e59c8e839560	4965	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4966	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4967	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4968	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	4969	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4970	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	4971	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4972	} while(0U)
AnnaBridge	163:e59c8e839560	4973	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	4974
AnnaBridge	163:e59c8e839560	4975	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	4976	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4977	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4978	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	4979	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4980	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	4981	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4982	} while(0U)
AnnaBridge	163:e59c8e839560	4983	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4984	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4985	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	4986	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4987	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	4988	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4989	} while(0U)
AnnaBridge	163:e59c8e839560	4990	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	4991
AnnaBridge	163:e59c8e839560	4992	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	4993	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	4994	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	4995	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	4996	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	163:e59c8e839560	4997	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	4998	} while(0U)
AnnaBridge	163:e59c8e839560	4999	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5000	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5001	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	5002	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5003	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	163:e59c8e839560	5004	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5005	} while(0U)
AnnaBridge	163:e59c8e839560	5006	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5007	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5008	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	5009	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5010	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	163:e59c8e839560	5011	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5012	} while(0U)
AnnaBridge	163:e59c8e839560	5013	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5014	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5015	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	163:e59c8e839560	5017	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	163:e59c8e839560	5019	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5020	} while(0U)
AnnaBridge	163:e59c8e839560	5021	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5022	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5023	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	5025	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	5027	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5028	} while(0U)
AnnaBridge	163:e59c8e839560	5029	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5030	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5031	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	5032	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5033	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	5034	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5035	} while(0U)
AnnaBridge	163:e59c8e839560	5036	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5037	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5038	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	5039	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5040	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	5041	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5042	} while(0U)
AnnaBridge	163:e59c8e839560	5043	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5044	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	5046	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	5048	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5049	} while(0U)
AnnaBridge	163:e59c8e839560	5050	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5051	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5052	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	5053	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5054	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	5055	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5056	} while(0U)
AnnaBridge	163:e59c8e839560	5057	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5058	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5059	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5060	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	5061	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5062	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	163:e59c8e839560	5063	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5064	} while(0U)
AnnaBridge	163:e59c8e839560	5065	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5066	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5067	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	163:e59c8e839560	5068	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5069	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	163:e59c8e839560	5070	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5071	} while(0U)
AnnaBridge	163:e59c8e839560	5072	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5073	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5074	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	163:e59c8e839560	5075	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5076	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	163:e59c8e839560	5077	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5078	} while(0U)
AnnaBridge	163:e59c8e839560	5079	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5080
AnnaBridge	163:e59c8e839560	5081	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	5082	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	5083	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	5084	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	5085	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	163:e59c8e839560	5086	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	163:e59c8e839560	5087	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	163:e59c8e839560	5088	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	163:e59c8e839560	5089	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5090	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	163:e59c8e839560	5091	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5092	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
AnnaBridge	163:e59c8e839560	5093	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	5094	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5095	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	163:e59c8e839560	5096	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5097	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5098	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	163:e59c8e839560	5099	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	163:e59c8e839560	5100	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5101	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	5102	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	163:e59c8e839560	5103	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	163:e59c8e839560	5104	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	163:e59c8e839560	5105	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5106	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
AnnaBridge	163:e59c8e839560	5107	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	163:e59c8e839560	5108	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	163:e59c8e839560	5109	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	163:e59c8e839560	5110	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5111
AnnaBridge	163:e59c8e839560	5112	/**
AnnaBridge	163:e59c8e839560	5113	* @}
AnnaBridge	163:e59c8e839560	5114	*/
AnnaBridge	163:e59c8e839560	5115
AnnaBridge	163:e59c8e839560	5116	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	5117	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	5118	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	5119	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	5120	* using it.
AnnaBridge	163:e59c8e839560	5121	* @{
AnnaBridge	163:e59c8e839560	5122	*/
AnnaBridge	163:e59c8e839560	5123	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	5124	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	5125	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	5126	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	5127	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	163:e59c8e839560	5128	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	163:e59c8e839560	5129	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	163:e59c8e839560	5130	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	163:e59c8e839560	5131	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5132	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	163:e59c8e839560	5133	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5134	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
AnnaBridge	163:e59c8e839560	5135	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	5136	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5137	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	163:e59c8e839560	5138	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	163:e59c8e839560	5139	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5140	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	163:e59c8e839560	5141	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	163:e59c8e839560	5142	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5143	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	5144	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	163:e59c8e839560	5145	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
AnnaBridge	163:e59c8e839560	5146	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	163:e59c8e839560	5147	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5148	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
AnnaBridge	163:e59c8e839560	5149	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	163:e59c8e839560	5150	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	163:e59c8e839560	5151	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	163:e59c8e839560	5152	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5153
AnnaBridge	163:e59c8e839560	5154	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	5155	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	5156	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	5157	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	5158	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	163:e59c8e839560	5159	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	163:e59c8e839560	5160	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	163:e59c8e839560	5161	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	163:e59c8e839560	5162	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5163	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	163:e59c8e839560	5164	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5165	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
AnnaBridge	163:e59c8e839560	5166	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	5167	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5168	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	163:e59c8e839560	5169	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	163:e59c8e839560	5170	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5171	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	163:e59c8e839560	5172	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	163:e59c8e839560	5173	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5174	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	5175	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	163:e59c8e839560	5176	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	163:e59c8e839560	5177	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	163:e59c8e839560	5178	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5179	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
AnnaBridge	163:e59c8e839560	5180	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	163:e59c8e839560	5181	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	163:e59c8e839560	5182	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	163:e59c8e839560	5183	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5184	/**
AnnaBridge	163:e59c8e839560	5185	* @}
AnnaBridge	163:e59c8e839560	5186	*/
AnnaBridge	163:e59c8e839560	5187	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	163:e59c8e839560	5188	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	5189	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	5190	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	5191	* using it.
AnnaBridge	163:e59c8e839560	5192	* @{
AnnaBridge	163:e59c8e839560	5193	*/
AnnaBridge	163:e59c8e839560	5194	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5195	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5196	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	5197	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5198	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	5199	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5200	} while(0U)
AnnaBridge	163:e59c8e839560	5201	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5202	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5203	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5204	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	163:e59c8e839560	5205	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5206	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	163:e59c8e839560	5207	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5208	} while(0U)
AnnaBridge	163:e59c8e839560	5209	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5210	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5211	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	163:e59c8e839560	5212	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5213	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	163:e59c8e839560	5214	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5215	} while(0U)
AnnaBridge	163:e59c8e839560	5216	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5217	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5218	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5219	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	5220	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5221	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	163:e59c8e839560	5222	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5223	} while(0U)
AnnaBridge	163:e59c8e839560	5224	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5225	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5226	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	5227	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5228	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	5229	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5230	} while(0U)
AnnaBridge	163:e59c8e839560	5231	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5232	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5233	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	163:e59c8e839560	5234	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5235	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	163:e59c8e839560	5236	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5237	} while(0U)
AnnaBridge	163:e59c8e839560	5238	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5239	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5240	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	5241	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5242	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	163:e59c8e839560	5243	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5244	} while(0U)
AnnaBridge	163:e59c8e839560	5245	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5246	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5247	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	5248	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5249	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	163:e59c8e839560	5250	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5251	} while(0U)
AnnaBridge	163:e59c8e839560	5252	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5253	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5254	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5255	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	5256	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5257	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	163:e59c8e839560	5258	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5259	} while(0U)
AnnaBridge	163:e59c8e839560	5260	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5261	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5262	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5263	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	163:e59c8e839560	5264	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5265	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	163:e59c8e839560	5266	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5267	} while(0U)
AnnaBridge	163:e59c8e839560	5268	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5269	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	5270	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	5271	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	163:e59c8e839560	5272	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	5273	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	163:e59c8e839560	5274	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	5275	} while(0U)
AnnaBridge	163:e59c8e839560	5276	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5277
AnnaBridge	163:e59c8e839560	5278	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	163:e59c8e839560	5279	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5280	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
AnnaBridge	163:e59c8e839560	5281	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
AnnaBridge	163:e59c8e839560	5282	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5283	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	163:e59c8e839560	5284	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	5285	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
AnnaBridge	163:e59c8e839560	5286	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	163:e59c8e839560	5287	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	163:e59c8e839560	5288	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5289	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	163:e59c8e839560	5290	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5291	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
AnnaBridge	163:e59c8e839560	5292	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5293	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
AnnaBridge	163:e59c8e839560	5294	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5295	/**
AnnaBridge	163:e59c8e839560	5296	* @}
AnnaBridge	163:e59c8e839560	5297	*/
AnnaBridge	163:e59c8e839560	5298
AnnaBridge	163:e59c8e839560	5299	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	5300	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	5301	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	5302	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	5303	* using it.
AnnaBridge	163:e59c8e839560	5304	* @{
AnnaBridge	163:e59c8e839560	5305	*/
AnnaBridge	163:e59c8e839560	5306	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	163:e59c8e839560	5307	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5308	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
AnnaBridge	163:e59c8e839560	5309	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
AnnaBridge	163:e59c8e839560	5310	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5311	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	163:e59c8e839560	5312	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	5313	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
AnnaBridge	163:e59c8e839560	5314	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	163:e59c8e839560	5315	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	163:e59c8e839560	5316	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5317	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	5318	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5319	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
AnnaBridge	163:e59c8e839560	5320	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5321	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	5322	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5323
AnnaBridge	163:e59c8e839560	5324	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	163:e59c8e839560	5325	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5326	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
AnnaBridge	163:e59c8e839560	5327	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
AnnaBridge	163:e59c8e839560	5328	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5329	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	163:e59c8e839560	5330	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	5331	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
AnnaBridge	163:e59c8e839560	5332	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	163:e59c8e839560	5333	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	163:e59c8e839560	5334	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5335	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	5336	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5337	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
AnnaBridge	163:e59c8e839560	5338	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5339	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	5340	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5341	/**
AnnaBridge	163:e59c8e839560	5342	* @}
AnnaBridge	163:e59c8e839560	5343	*/
AnnaBridge	163:e59c8e839560	5344
AnnaBridge	163:e59c8e839560	5345	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	163:e59c8e839560	5346	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	163:e59c8e839560	5347	* @{
AnnaBridge	163:e59c8e839560	5348	*/
AnnaBridge	163:e59c8e839560	5349	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	5350	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	5351	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	5352	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	5353	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	5354
AnnaBridge	163:e59c8e839560	5355	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	5356	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	5357	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	5358	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	5359	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	163:e59c8e839560	5360	/**
AnnaBridge	163:e59c8e839560	5361	* @}
AnnaBridge	163:e59c8e839560	5362	*/
AnnaBridge	163:e59c8e839560	5363
AnnaBridge	163:e59c8e839560	5364	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	163:e59c8e839560	5365	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	163:e59c8e839560	5366	* @{
AnnaBridge	163:e59c8e839560	5367	*/
AnnaBridge	163:e59c8e839560	5368	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	5369	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	5370
AnnaBridge	163:e59c8e839560	5371	#if defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5372	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
AnnaBridge	163:e59c8e839560	5373	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
AnnaBridge	163:e59c8e839560	5374	#endif /* STM32F423xx */
AnnaBridge	163:e59c8e839560	5375
AnnaBridge	163:e59c8e839560	5376	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	5377	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	163:e59c8e839560	5378
AnnaBridge	163:e59c8e839560	5379	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	5380	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	163:e59c8e839560	5381	/**
AnnaBridge	163:e59c8e839560	5382	* @}
AnnaBridge	163:e59c8e839560	5383	*/
AnnaBridge	163:e59c8e839560	5384
AnnaBridge	163:e59c8e839560	5385	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	163:e59c8e839560	5386	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	163:e59c8e839560	5387	* @{
AnnaBridge	163:e59c8e839560	5388	*/
AnnaBridge	163:e59c8e839560	5389	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5390	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	5391	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	163:e59c8e839560	5392
AnnaBridge	163:e59c8e839560	5393	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
AnnaBridge	163:e59c8e839560	5394	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	5395
AnnaBridge	163:e59c8e839560	5396	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
AnnaBridge	163:e59c8e839560	5397	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	163:e59c8e839560	5398	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5399	#if defined(STM32F412Cx)
AnnaBridge	163:e59c8e839560	5400	#define __HAL_RCC_AHB3_FORCE_RESET()
AnnaBridge	163:e59c8e839560	5401	#define __HAL_RCC_AHB3_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	5402
AnnaBridge	163:e59c8e839560	5403	#define __HAL_RCC_FSMC_FORCE_RESET()
AnnaBridge	163:e59c8e839560	5404	#define __HAL_RCC_QSPI_FORCE_RESET()
AnnaBridge	163:e59c8e839560	5405
AnnaBridge	163:e59c8e839560	5406	#define __HAL_RCC_FSMC_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	5407	#define __HAL_RCC_QSPI_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	5408	#endif /* STM32F412Cx */
AnnaBridge	163:e59c8e839560	5409	/**
AnnaBridge	163:e59c8e839560	5410	* @}
AnnaBridge	163:e59c8e839560	5411	*/
AnnaBridge	163:e59c8e839560	5412
AnnaBridge	163:e59c8e839560	5413	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	5414	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	5415	* @{
AnnaBridge	163:e59c8e839560	5416	*/
AnnaBridge	163:e59c8e839560	5417	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	5418	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	5419	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	5420	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	5421	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	5422	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	5423	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	5424	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	5425	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5426	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	163:e59c8e839560	5427	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5428	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	5429	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5430	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	5431	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5432	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5433	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	5434	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	5435	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5436	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	5437	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	5438	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	5439	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	5440	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5441	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
AnnaBridge	163:e59c8e839560	5442	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	5443	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	163:e59c8e839560	5444	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	163:e59c8e839560	5445	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5446
AnnaBridge	163:e59c8e839560	5447	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	5448	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	5449	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	5450	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	5451	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	5452	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	5453	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	5454	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	5455	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5456	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	163:e59c8e839560	5457	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5458	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	5459	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5460	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	5461	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5462	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5463	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	5464	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	5465	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5466	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	5467	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	163:e59c8e839560	5468	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	163:e59c8e839560	5469	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	163:e59c8e839560	5470	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5471	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
AnnaBridge	163:e59c8e839560	5472	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	163:e59c8e839560	5473	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	163:e59c8e839560	5474	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	163:e59c8e839560	5475	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5476	/**
AnnaBridge	163:e59c8e839560	5477	* @}
AnnaBridge	163:e59c8e839560	5478	*/
AnnaBridge	163:e59c8e839560	5479
AnnaBridge	163:e59c8e839560	5480	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	5481	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	5482	* @{
AnnaBridge	163:e59c8e839560	5483	*/
AnnaBridge	163:e59c8e839560	5484	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	5485	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5486	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
AnnaBridge	163:e59c8e839560	5487	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
AnnaBridge	163:e59c8e839560	5488	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5489	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	5490	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	5491	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	5492	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	5493	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5494	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	5495	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5496	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	163:e59c8e839560	5497	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5498	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	163:e59c8e839560	5499	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5500
AnnaBridge	163:e59c8e839560	5501	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	5502	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5503	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
AnnaBridge	163:e59c8e839560	5504	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
AnnaBridge	163:e59c8e839560	5505	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5506	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	163:e59c8e839560	5507	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	5508	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	163:e59c8e839560	5509	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	163:e59c8e839560	5510	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5511	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	163:e59c8e839560	5512	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5513	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	163:e59c8e839560	5514	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5515	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	163:e59c8e839560	5516	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5517	/**
AnnaBridge	163:e59c8e839560	5518	* @}
AnnaBridge	163:e59c8e839560	5519	*/
AnnaBridge	163:e59c8e839560	5520
AnnaBridge	163:e59c8e839560	5521	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	5522	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	5523	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	5524	* power consumption.
AnnaBridge	163:e59c8e839560	5525	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	5526	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	5527	* @{
AnnaBridge	163:e59c8e839560	5528	*/
AnnaBridge	163:e59c8e839560	5529	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	5530	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	5531	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	5532	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	5533	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	5534	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	5535	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	5536	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5537	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	5538	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5539
AnnaBridge	163:e59c8e839560	5540	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	163:e59c8e839560	5541	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	163:e59c8e839560	5542	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	163:e59c8e839560	5543	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	163:e59c8e839560	5544	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	163:e59c8e839560	5545	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	163:e59c8e839560	5546	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	163:e59c8e839560	5547	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5548	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	163:e59c8e839560	5549	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5550	/**
AnnaBridge	163:e59c8e839560	5551	* @}
AnnaBridge	163:e59c8e839560	5552	*/
AnnaBridge	163:e59c8e839560	5553
AnnaBridge	163:e59c8e839560	5554	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	5555	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	5556	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	5557	* power consumption.
AnnaBridge	163:e59c8e839560	5558	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	5559	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	5560	* @{
AnnaBridge	163:e59c8e839560	5561	*/
AnnaBridge	163:e59c8e839560	5562	#if defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5563	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
AnnaBridge	163:e59c8e839560	5564	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
AnnaBridge	163:e59c8e839560	5565	#endif /* STM32F423xx */
AnnaBridge	163:e59c8e839560	5566
AnnaBridge	163:e59c8e839560	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	5568	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	163:e59c8e839560	5569
AnnaBridge	163:e59c8e839560	5570	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	5571	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	163:e59c8e839560	5572	/**
AnnaBridge	163:e59c8e839560	5573	* @}
AnnaBridge	163:e59c8e839560	5574	*/
AnnaBridge	163:e59c8e839560	5575
AnnaBridge	163:e59c8e839560	5576	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	5577	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	5578	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	5579	* power consumption.
AnnaBridge	163:e59c8e839560	5580	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	5581	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	5582	* @{
AnnaBridge	163:e59c8e839560	5583	*/
AnnaBridge	163:e59c8e839560	5584	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5585	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	163:e59c8e839560	5586	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	5587
AnnaBridge	163:e59c8e839560	5588	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	163:e59c8e839560	5589	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	163:e59c8e839560	5590	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5591
AnnaBridge	163:e59c8e839560	5592	/**
AnnaBridge	163:e59c8e839560	5593	* @}
AnnaBridge	163:e59c8e839560	5594	*/
AnnaBridge	163:e59c8e839560	5595
AnnaBridge	163:e59c8e839560	5596	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	5597	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	5598	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	5599	* power consumption.
AnnaBridge	163:e59c8e839560	5600	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	5601	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	5602	* @{
AnnaBridge	163:e59c8e839560	5603	*/
AnnaBridge	163:e59c8e839560	5604	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	5605	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	5606	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	5607	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	5608	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	5609	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	5610	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	5611	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	5612	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5613	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	163:e59c8e839560	5614	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5615	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	163:e59c8e839560	5616	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	5617	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5618	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	5619	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5620	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5621	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	5622	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	5623	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5624	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	5625	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	5626	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	5627	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	5628	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5629	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	163:e59c8e839560	5630	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	5631	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	163:e59c8e839560	5632	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	163:e59c8e839560	5633	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5634
AnnaBridge	163:e59c8e839560	5635	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	163:e59c8e839560	5636	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	163:e59c8e839560	5637	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	163:e59c8e839560	5638	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	163:e59c8e839560	5639	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	163:e59c8e839560	5640	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	163:e59c8e839560	5641	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	163:e59c8e839560	5642	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	163:e59c8e839560	5643	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5644	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	163:e59c8e839560	5645	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5646	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	163:e59c8e839560	5647	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	163:e59c8e839560	5648	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5649	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	163:e59c8e839560	5650	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5651	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5652	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	163:e59c8e839560	5653	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	163:e59c8e839560	5654	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5655	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	163:e59c8e839560	5656	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	163:e59c8e839560	5657	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	163:e59c8e839560	5658	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	163:e59c8e839560	5659	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5660	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	163:e59c8e839560	5661	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	163:e59c8e839560	5662	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	163:e59c8e839560	5663	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	163:e59c8e839560	5664	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5665	/**
AnnaBridge	163:e59c8e839560	5666	* @}
AnnaBridge	163:e59c8e839560	5667	*/
AnnaBridge	163:e59c8e839560	5668
AnnaBridge	163:e59c8e839560	5669	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	163:e59c8e839560	5670	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	163:e59c8e839560	5671	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	163:e59c8e839560	5672	* power consumption.
AnnaBridge	163:e59c8e839560	5673	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	163:e59c8e839560	5674	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	163:e59c8e839560	5675	* @{
AnnaBridge	163:e59c8e839560	5676	*/
AnnaBridge	163:e59c8e839560	5677	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	5678	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5679	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
AnnaBridge	163:e59c8e839560	5680	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
AnnaBridge	163:e59c8e839560	5681	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5682	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	5683	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	5684	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	163:e59c8e839560	5685	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	5686	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	5687	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5688	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	5689	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5690	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	163:e59c8e839560	5691	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5692	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	163:e59c8e839560	5693	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5694
AnnaBridge	163:e59c8e839560	5695	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	163:e59c8e839560	5696	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5697	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
AnnaBridge	163:e59c8e839560	5698	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
AnnaBridge	163:e59c8e839560	5699	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5700	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	163:e59c8e839560	5701	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	163:e59c8e839560	5702	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	163:e59c8e839560	5703	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	163:e59c8e839560	5704	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	163:e59c8e839560	5705	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5706	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	163:e59c8e839560	5707	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5708	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	163:e59c8e839560	5709	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5710	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	163:e59c8e839560	5711	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5712	/**
AnnaBridge	163:e59c8e839560	5713	* @}
AnnaBridge	163:e59c8e839560	5714	*/
AnnaBridge	163:e59c8e839560	5715	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	5716	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	5717
AnnaBridge	163:e59c8e839560	5718	/------------------------------- PLL Configuration --------------------------/
AnnaBridge	163:e59c8e839560	5719	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	163:e59c8e839560	5720	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	5721	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5722	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	163:e59c8e839560	5723	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	163:e59c8e839560	5724	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	163:e59c8e839560	5725	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	5726	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	5727	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	5728	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	163:e59c8e839560	5729	* @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	5730	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5731	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5732	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5733	* of 2 MHz to limit PLL jitter.
AnnaBridge	163:e59c8e839560	5734	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	163:e59c8e839560	5735	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5736	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5737	* output frequency is between 100 and 432 MHz.
AnnaBridge	163:e59c8e839560	5738	*
AnnaBridge	163:e59c8e839560	5739	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
AnnaBridge	163:e59c8e839560	5740	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	163:e59c8e839560	5741	*
AnnaBridge	163:e59c8e839560	5742	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
AnnaBridge	163:e59c8e839560	5743	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5744	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	163:e59c8e839560	5745	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	163:e59c8e839560	5746	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	163:e59c8e839560	5747	* correctly.
AnnaBridge	163:e59c8e839560	5748	*
AnnaBridge	163:e59c8e839560	5749	* @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
AnnaBridge	163:e59c8e839560	5750	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5751	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
AnnaBridge	163:e59c8e839560	5752	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
AnnaBridge	163:e59c8e839560	5753	*
AnnaBridge	163:e59c8e839560	5754	*/
AnnaBridge	163:e59c8e839560	5755	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
AnnaBridge	163:e59c8e839560	5756	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
AnnaBridge	163:e59c8e839560	5757	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
AnnaBridge	163:e59c8e839560	5758	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
AnnaBridge	163:e59c8e839560	5759	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) \| \
AnnaBridge	163:e59c8e839560	5760	((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
AnnaBridge	163:e59c8e839560	5761	#else
AnnaBridge	163:e59c8e839560	5762	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	163:e59c8e839560	5763	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	163:e59c8e839560	5764	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	163:e59c8e839560	5765	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	5766	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	5767	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	5768	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	163:e59c8e839560	5769	* @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	5770	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5771	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5772	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5773	* of 2 MHz to limit PLL jitter.
AnnaBridge	163:e59c8e839560	5774	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	163:e59c8e839560	5775	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	163:e59c8e839560	5776	* Except for STM32F411xE devices where Min_Data = 192.
AnnaBridge	163:e59c8e839560	5777	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5778	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
AnnaBridge	163:e59c8e839560	5779	* where frequency is between 192 and 432 MHz.
AnnaBridge	163:e59c8e839560	5780	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
AnnaBridge	163:e59c8e839560	5781	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	163:e59c8e839560	5782	*
AnnaBridge	163:e59c8e839560	5783	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
AnnaBridge	163:e59c8e839560	5784	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5785	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	163:e59c8e839560	5786	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	163:e59c8e839560	5787	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	163:e59c8e839560	5788	* correctly.
AnnaBridge	163:e59c8e839560	5789	*
AnnaBridge	163:e59c8e839560	5790	*/
AnnaBridge	163:e59c8e839560	5791	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
AnnaBridge	163:e59c8e839560	5792	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
AnnaBridge	163:e59c8e839560	5793	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
AnnaBridge	163:e59c8e839560	5794	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
AnnaBridge	163:e59c8e839560	5795	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
AnnaBridge	163:e59c8e839560	5796	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	5797	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	5798
AnnaBridge	163:e59c8e839560	5799	/----------------------------PLLI2S Configuration ---------------------------/
AnnaBridge	163:e59c8e839560	5800	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	5801	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	5802	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	163:e59c8e839560	5803	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	5804	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5805
AnnaBridge	163:e59c8e839560	5806	/** @brief Macros to enable or disable the PLLI2S.
AnnaBridge	163:e59c8e839560	5807	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	5808	*/
AnnaBridge	163:e59c8e839560	5809	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
AnnaBridge	163:e59c8e839560	5810	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
AnnaBridge	163:e59c8e839560	5811
AnnaBridge	163:e59c8e839560	5812	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	5813	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	163:e59c8e839560	5814	STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	5815	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	5816	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	163:e59c8e839560	5817	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5818	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	163:e59c8e839560	5819	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5820	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	163:e59c8e839560	5821	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5822	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5823	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5824	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	163:e59c8e839560	5825	*
AnnaBridge	163:e59c8e839560	5826	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	163:e59c8e839560	5827	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5828	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5829	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5830	*
AnnaBridge	163:e59c8e839560	5831	* @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
AnnaBridge	163:e59c8e839560	5832	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	163:e59c8e839560	5833	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
AnnaBridge	163:e59c8e839560	5834	*
AnnaBridge	163:e59c8e839560	5835	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	163:e59c8e839560	5836	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5837	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	163:e59c8e839560	5838	* on the I2S clock frequency.
AnnaBridge	163:e59c8e839560	5839	*
AnnaBridge	163:e59c8e839560	5840	* @param __PLLI2SQ__ specifies the division factor for SAI clock
AnnaBridge	163:e59c8e839560	5841	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5842	*/
AnnaBridge	163:e59c8e839560	5843	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge	163:e59c8e839560	5844	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5845	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5846	((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) \|\
AnnaBridge	163:e59c8e839560	5847	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
AnnaBridge	163:e59c8e839560	5848	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	163:e59c8e839560	5849	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	5850	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	5851	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	163:e59c8e839560	5852	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5853	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	163:e59c8e839560	5854	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5855	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	163:e59c8e839560	5856	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5857	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5858	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5859	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	163:e59c8e839560	5860	*
AnnaBridge	163:e59c8e839560	5861	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	163:e59c8e839560	5862	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5863	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5864	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5865	*
AnnaBridge	163:e59c8e839560	5866	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	163:e59c8e839560	5867	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5868	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	163:e59c8e839560	5869	* on the I2S clock frequency.
AnnaBridge	163:e59c8e839560	5870	*
AnnaBridge	163:e59c8e839560	5871	* @param __PLLI2SQ__ specifies the division factor for SAI clock
AnnaBridge	163:e59c8e839560	5872	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5873	*/
AnnaBridge	163:e59c8e839560	5874	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge	163:e59c8e839560	5875	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5876	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5877	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
AnnaBridge	163:e59c8e839560	5878	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	163:e59c8e839560	5879	#else
AnnaBridge	163:e59c8e839560	5880	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	163:e59c8e839560	5881	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5882	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	163:e59c8e839560	5883	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5884	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	163:e59c8e839560	5885	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5886	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5887	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5888	*
AnnaBridge	163:e59c8e839560	5889	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	163:e59c8e839560	5890	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5891	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	163:e59c8e839560	5892	* on the I2S clock frequency.
AnnaBridge	163:e59c8e839560	5893	*
AnnaBridge	163:e59c8e839560	5894	*/
AnnaBridge	163:e59c8e839560	5895	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
AnnaBridge	163:e59c8e839560	5896	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5897	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	163:e59c8e839560	5898	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	5899
AnnaBridge	163:e59c8e839560	5900	#if defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	5901	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	163:e59c8e839560	5902	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5903	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5904	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	163:e59c8e839560	5905	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5906	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	163:e59c8e839560	5907	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5908	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
AnnaBridge	163:e59c8e839560	5909	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5910	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5911	* of 2 MHz to limit PLLI2S jitter.
AnnaBridge	163:e59c8e839560	5912	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	163:e59c8e839560	5913	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5914	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5915	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5916	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	163:e59c8e839560	5917	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5918	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	163:e59c8e839560	5919	* on the I2S clock frequency.
AnnaBridge	163:e59c8e839560	5920	*/
AnnaBridge	163:e59c8e839560	5921	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5922	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5923	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	163:e59c8e839560	5924	#endif /* STM32F411xE */
AnnaBridge	163:e59c8e839560	5925
AnnaBridge	163:e59c8e839560	5926	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	5927	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
AnnaBridge	163:e59c8e839560	5928	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	163:e59c8e839560	5929	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	163:e59c8e839560	5930	* HAL_RCC_ClockConfig() API)
AnnaBridge	163:e59c8e839560	5931	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	163:e59c8e839560	5932	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5933	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5934	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5935	* @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	5936	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5937	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
AnnaBridge	163:e59c8e839560	5938	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
AnnaBridge	163:e59c8e839560	5939	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	163:e59c8e839560	5940	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5941	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	163:e59c8e839560	5942	* on the I2S clock frequency.
AnnaBridge	163:e59c8e839560	5943	*/
AnnaBridge	163:e59c8e839560	5944	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
AnnaBridge	163:e59c8e839560	5945	((__PLLI2SQ__) << 24U) \|\
AnnaBridge	163:e59c8e839560	5946	((__PLLI2SR__) << 28U))
AnnaBridge	163:e59c8e839560	5947	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	5948	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	5949
AnnaBridge	163:e59c8e839560	5950	/------------------------------ PLLSAI Configuration ------------------------/
AnnaBridge	163:e59c8e839560	5951	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	5952	/** @brief Macros to Enable or Disable the PLLISAI.
AnnaBridge	163:e59c8e839560	5953	* @note The PLLSAI is only available with STM32F429x/439x Devices.
AnnaBridge	163:e59c8e839560	5954	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	5955	*/
AnnaBridge	163:e59c8e839560	5956	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
AnnaBridge	163:e59c8e839560	5957	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
AnnaBridge	163:e59c8e839560	5958
AnnaBridge	163:e59c8e839560	5959	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	5960	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	163:e59c8e839560	5961	*
AnnaBridge	163:e59c8e839560	5962	* @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
AnnaBridge	163:e59c8e839560	5963	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	163:e59c8e839560	5964	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
AnnaBridge	163:e59c8e839560	5965	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	163:e59c8e839560	5966	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	163:e59c8e839560	5967	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
AnnaBridge	163:e59c8e839560	5968	*
AnnaBridge	163:e59c8e839560	5969	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	163:e59c8e839560	5970	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5971	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5972	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5973	*
AnnaBridge	163:e59c8e839560	5974	* @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	163:e59c8e839560	5975	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	163:e59c8e839560	5976	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
AnnaBridge	163:e59c8e839560	5977	*
AnnaBridge	163:e59c8e839560	5978	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	163:e59c8e839560	5979	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	5980	*
AnnaBridge	163:e59c8e839560	5981	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	163:e59c8e839560	5982	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	5983	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
AnnaBridge	163:e59c8e839560	5984	*/
AnnaBridge	163:e59c8e839560	5985	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	163:e59c8e839560	5986	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
AnnaBridge	163:e59c8e839560	5987	((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
AnnaBridge	163:e59c8e839560	5988	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \| \
AnnaBridge	163:e59c8e839560	5989	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
AnnaBridge	163:e59c8e839560	5990	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	5991
AnnaBridge	163:e59c8e839560	5992	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	5993	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	163:e59c8e839560	5994	*
AnnaBridge	163:e59c8e839560	5995	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	163:e59c8e839560	5996	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	5997	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	5998	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5999	*
AnnaBridge	163:e59c8e839560	6000	* @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
AnnaBridge	163:e59c8e839560	6001	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	163:e59c8e839560	6002	*
AnnaBridge	163:e59c8e839560	6003	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	163:e59c8e839560	6004	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	6005	*
AnnaBridge	163:e59c8e839560	6006	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	163:e59c8e839560	6007	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	6008	*/
AnnaBridge	163:e59c8e839560	6009	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	163:e59c8e839560	6010	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \|\
AnnaBridge	163:e59c8e839560	6011	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \|\
AnnaBridge	163:e59c8e839560	6012	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \|\
AnnaBridge	163:e59c8e839560	6013	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
AnnaBridge	163:e59c8e839560	6014	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6015
AnnaBridge	163:e59c8e839560	6016	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	163:e59c8e839560	6017	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	163:e59c8e839560	6018	*
AnnaBridge	163:e59c8e839560	6019	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	163:e59c8e839560	6020	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	163:e59c8e839560	6021	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	163:e59c8e839560	6022	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	6023	*
AnnaBridge	163:e59c8e839560	6024	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	163:e59c8e839560	6025	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	163:e59c8e839560	6026	*
AnnaBridge	163:e59c8e839560	6027	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	163:e59c8e839560	6028	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	163:e59c8e839560	6029	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
AnnaBridge	163:e59c8e839560	6030	*/
AnnaBridge	163:e59c8e839560	6031	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	163:e59c8e839560	6032	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
AnnaBridge	163:e59c8e839560	6033	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \| \
AnnaBridge	163:e59c8e839560	6034	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
AnnaBridge	163:e59c8e839560	6035	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	163:e59c8e839560	6036
AnnaBridge	163:e59c8e839560	6037	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6038	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	6039
AnnaBridge	163:e59c8e839560	6040	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
AnnaBridge	163:e59c8e839560	6041	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6042	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	163:e59c8e839560	6043	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	163:e59c8e839560	6044	* @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	6045	* This parameter must be a number between 1 and 32.
AnnaBridge	163:e59c8e839560	6046	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
AnnaBridge	163:e59c8e839560	6047	*/
AnnaBridge	163:e59c8e839560	6048	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
AnnaBridge	163:e59c8e839560	6049
AnnaBridge	163:e59c8e839560	6050	/** @brief Macro to configure the SAI clock Divider coming from PLL.
AnnaBridge	163:e59c8e839560	6051	* @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	6052	* This parameter must be a number between 1 and 32.
AnnaBridge	163:e59c8e839560	6053	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
AnnaBridge	163:e59c8e839560	6054	*/
AnnaBridge	163:e59c8e839560	6055	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
AnnaBridge	163:e59c8e839560	6056	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6057
AnnaBridge	163:e59c8e839560	6058	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	163:e59c8e839560	6059	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6060	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	163:e59c8e839560	6061	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	163:e59c8e839560	6062	* @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	163:e59c8e839560	6063	* This parameter must be a number between 1 and 32.
AnnaBridge	163:e59c8e839560	6064	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
AnnaBridge	163:e59c8e839560	6065	*/
AnnaBridge	163:e59c8e839560	6066	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
AnnaBridge	163:e59c8e839560	6067
AnnaBridge	163:e59c8e839560	6068	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
AnnaBridge	163:e59c8e839560	6069	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	163:e59c8e839560	6070	* @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
AnnaBridge	163:e59c8e839560	6071	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
AnnaBridge	163:e59c8e839560	6072	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
AnnaBridge	163:e59c8e839560	6073	*/
AnnaBridge	163:e59c8e839560	6074	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
AnnaBridge	163:e59c8e839560	6075	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6076
AnnaBridge	163:e59c8e839560	6077	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6078	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
AnnaBridge	163:e59c8e839560	6079	*
AnnaBridge	163:e59c8e839560	6080	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	163:e59c8e839560	6081	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	163:e59c8e839560	6082	* @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
AnnaBridge	163:e59c8e839560	6083	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
AnnaBridge	163:e59c8e839560	6084	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
AnnaBridge	163:e59c8e839560	6085	*/
AnnaBridge	163:e59c8e839560	6086	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
AnnaBridge	163:e59c8e839560	6087	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6088	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	6089
AnnaBridge	163:e59c8e839560	6090	/------------------------- Peripheral Clock selection -----------------------/
AnnaBridge	163:e59c8e839560	6091	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	163:e59c8e839560	6092	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	6093	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	163:e59c8e839560	6094	defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6095	/** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	6096	* @note This function must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	6097	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	163:e59c8e839560	6098	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6099	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	163:e59c8e839560	6100	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	6101	* used as I2S clock source.
AnnaBridge	163:e59c8e839560	6102	*/
AnnaBridge	163:e59c8e839560	6103	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
AnnaBridge	163:e59c8e839560	6104
AnnaBridge	163:e59c8e839560	6105
AnnaBridge	163:e59c8e839560	6106	/** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	6107	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6108	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	163:e59c8e839560	6109	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	6110	* used as I2S clock source
AnnaBridge	163:e59c8e839560	6111	*/
AnnaBridge	163:e59c8e839560	6112	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge	163:e59c8e839560	6113	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6114
AnnaBridge	163:e59c8e839560	6115	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6116
AnnaBridge	163:e59c8e839560	6117	/** @brief Macro to configure SAI1BlockA clock source selection.
AnnaBridge	163:e59c8e839560	6118	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	163:e59c8e839560	6119	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6120	* the SAI clock.
AnnaBridge	163:e59c8e839560	6121	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	163:e59c8e839560	6122	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6123	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	163:e59c8e839560	6124	* as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6125	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	163:e59c8e839560	6126	* as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6127	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	6128	* used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6129	*/
AnnaBridge	163:e59c8e839560	6130	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6131
AnnaBridge	163:e59c8e839560	6132	/** @brief Macro to configure SAI1BlockB clock source selection.
AnnaBridge	163:e59c8e839560	6133	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	163:e59c8e839560	6134	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6135	* the SAI clock.
AnnaBridge	163:e59c8e839560	6136	* @param __SOURCE__ specifies the SAI Block B clock source.
AnnaBridge	163:e59c8e839560	6137	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6138	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	163:e59c8e839560	6139	* as SAI1 Block B clock.
AnnaBridge	163:e59c8e839560	6140	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	163:e59c8e839560	6141	* as SAI1 Block B clock.
AnnaBridge	163:e59c8e839560	6142	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	6143	* used as SAI1 Block B clock.
AnnaBridge	163:e59c8e839560	6144	*/
AnnaBridge	163:e59c8e839560	6145	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6146	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6147
AnnaBridge	163:e59c8e839560	6148	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	6149	/** @brief Macro to configure SAI1 clock source selection.
AnnaBridge	163:e59c8e839560	6150	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	163:e59c8e839560	6151	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6152	* the SAI clock.
AnnaBridge	163:e59c8e839560	6153	* @param __SOURCE__ specifies the SAI1 clock source.
AnnaBridge	163:e59c8e839560	6154	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6155	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6156	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6157	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6158	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6159	*/
AnnaBridge	163:e59c8e839560	6160	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6161
AnnaBridge	163:e59c8e839560	6162	/** @brief Macro to Get SAI1 clock source selection.
AnnaBridge	163:e59c8e839560	6163	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	163:e59c8e839560	6164	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6165	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6166	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6167	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6168	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
AnnaBridge	163:e59c8e839560	6169	*/
AnnaBridge	163:e59c8e839560	6170	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
AnnaBridge	163:e59c8e839560	6171
AnnaBridge	163:e59c8e839560	6172	/** @brief Macro to configure SAI2 clock source selection.
AnnaBridge	163:e59c8e839560	6173	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	163:e59c8e839560	6174	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6175	* the SAI clock.
AnnaBridge	163:e59c8e839560	6176	* @param __SOURCE__ specifies the SAI2 clock source.
AnnaBridge	163:e59c8e839560	6177	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6178	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6179	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6180	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6181	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6182	*/
AnnaBridge	163:e59c8e839560	6183	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6184
AnnaBridge	163:e59c8e839560	6185	/** @brief Macro to Get SAI2 clock source selection.
AnnaBridge	163:e59c8e839560	6186	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	163:e59c8e839560	6187	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6188	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6189	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6190	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6191	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
AnnaBridge	163:e59c8e839560	6192	*/
AnnaBridge	163:e59c8e839560	6193	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
AnnaBridge	163:e59c8e839560	6194
AnnaBridge	163:e59c8e839560	6195	/** @brief Macro to configure I2S APB1 clock source selection.
AnnaBridge	163:e59c8e839560	6196	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
AnnaBridge	163:e59c8e839560	6197	* @param __SOURCE__ specifies the I2S APB1 clock source.
AnnaBridge	163:e59c8e839560	6198	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6199	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	163:e59c8e839560	6200	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	163:e59c8e839560	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
AnnaBridge	163:e59c8e839560	6202	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6203	*/
AnnaBridge	163:e59c8e839560	6204	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6205
AnnaBridge	163:e59c8e839560	6206	/** @brief Macro to Get I2S APB1 clock source selection.
AnnaBridge	163:e59c8e839560	6207	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6208	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	163:e59c8e839560	6209	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	163:e59c8e839560	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
AnnaBridge	163:e59c8e839560	6211	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6212	*/
AnnaBridge	163:e59c8e839560	6213	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
AnnaBridge	163:e59c8e839560	6214
AnnaBridge	163:e59c8e839560	6215	/** @brief Macro to configure I2S APB2 clock source selection.
AnnaBridge	163:e59c8e839560	6216	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
AnnaBridge	163:e59c8e839560	6217	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	163:e59c8e839560	6218	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6219	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	163:e59c8e839560	6220	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	163:e59c8e839560	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
AnnaBridge	163:e59c8e839560	6222	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6223	*/
AnnaBridge	163:e59c8e839560	6224	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6225
AnnaBridge	163:e59c8e839560	6226	/** @brief Macro to Get I2S APB2 clock source selection.
AnnaBridge	163:e59c8e839560	6227	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6228	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	163:e59c8e839560	6229	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	163:e59c8e839560	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
AnnaBridge	163:e59c8e839560	6231	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6232	*/
AnnaBridge	163:e59c8e839560	6233	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
AnnaBridge	163:e59c8e839560	6234
AnnaBridge	163:e59c8e839560	6235	/** @brief Macro to configure the CEC clock.
AnnaBridge	163:e59c8e839560	6236	* @param __SOURCE__ specifies the CEC clock source.
AnnaBridge	163:e59c8e839560	6237	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6238	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
AnnaBridge	163:e59c8e839560	6239	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	163:e59c8e839560	6240	*/
AnnaBridge	163:e59c8e839560	6241	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6242
AnnaBridge	163:e59c8e839560	6243	/** @brief Macro to Get the CEC clock.
AnnaBridge	163:e59c8e839560	6244	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6245	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
AnnaBridge	163:e59c8e839560	6246	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	163:e59c8e839560	6247	*/
AnnaBridge	163:e59c8e839560	6248	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
AnnaBridge	163:e59c8e839560	6249
AnnaBridge	163:e59c8e839560	6250	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6251	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	163:e59c8e839560	6252	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6253	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6254	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6255	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6256	*/
AnnaBridge	163:e59c8e839560	6257	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6258
AnnaBridge	163:e59c8e839560	6259	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6260	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6261	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6262	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6263	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6264	*/
AnnaBridge	163:e59c8e839560	6265	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	163:e59c8e839560	6266
AnnaBridge	163:e59c8e839560	6267	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6268	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	163:e59c8e839560	6269	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6270	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6271	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6272	*/
AnnaBridge	163:e59c8e839560	6273	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6274
AnnaBridge	163:e59c8e839560	6275	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	163:e59c8e839560	6276	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6277	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6278	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6279	*/
AnnaBridge	163:e59c8e839560	6280	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
AnnaBridge	163:e59c8e839560	6281
AnnaBridge	163:e59c8e839560	6282	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6283	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	163:e59c8e839560	6284	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6285	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6286	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6287	*/
AnnaBridge	163:e59c8e839560	6288	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6289
AnnaBridge	163:e59c8e839560	6290	/** @brief Macro to Get the SDIO clock.
AnnaBridge	163:e59c8e839560	6291	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6292	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6293	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6294	*/
AnnaBridge	163:e59c8e839560	6295	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
AnnaBridge	163:e59c8e839560	6296
AnnaBridge	163:e59c8e839560	6297	/** @brief Macro to configure the SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6298	* @param __SOURCE__ specifies the SPDIFRX clock source.
AnnaBridge	163:e59c8e839560	6299	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6301	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6302	*/
AnnaBridge	163:e59c8e839560	6303	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6304
AnnaBridge	163:e59c8e839560	6305	/** @brief Macro to Get the SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6306	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6308	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6309	*/
AnnaBridge	163:e59c8e839560	6310	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
AnnaBridge	163:e59c8e839560	6311	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	6312
AnnaBridge	163:e59c8e839560	6313	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6314
AnnaBridge	163:e59c8e839560	6315	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6316	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	163:e59c8e839560	6317	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6318	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6319	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6320	*/
AnnaBridge	163:e59c8e839560	6321	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6322
AnnaBridge	163:e59c8e839560	6323	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	163:e59c8e839560	6324	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6325	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6326	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6327	*/
AnnaBridge	163:e59c8e839560	6328	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
AnnaBridge	163:e59c8e839560	6329
AnnaBridge	163:e59c8e839560	6330	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6331	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	163:e59c8e839560	6332	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6333	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6334	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6335	*/
AnnaBridge	163:e59c8e839560	6336	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6337
AnnaBridge	163:e59c8e839560	6338	/** @brief Macro to Get the SDIO clock.
AnnaBridge	163:e59c8e839560	6339	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6340	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6341	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6342	*/
AnnaBridge	163:e59c8e839560	6343	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
AnnaBridge	163:e59c8e839560	6344
AnnaBridge	163:e59c8e839560	6345	/** @brief Macro to configure the DSI clock.
AnnaBridge	163:e59c8e839560	6346	* @param __SOURCE__ specifies the DSI clock source.
AnnaBridge	163:e59c8e839560	6347	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6348	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	163:e59c8e839560	6349	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	163:e59c8e839560	6350	*/
AnnaBridge	163:e59c8e839560	6351	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6352
AnnaBridge	163:e59c8e839560	6353	/** @brief Macro to Get the DSI clock.
AnnaBridge	163:e59c8e839560	6354	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6355	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	163:e59c8e839560	6356	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	163:e59c8e839560	6357	*/
AnnaBridge	163:e59c8e839560	6358	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
AnnaBridge	163:e59c8e839560	6359
AnnaBridge	163:e59c8e839560	6360	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6361
AnnaBridge	163:e59c8e839560	6362	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	6363	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6364	/** @brief Macro to configure the DFSDM1 clock.
AnnaBridge	163:e59c8e839560	6365	* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge	163:e59c8e839560	6366	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6367	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	163:e59c8e839560	6368	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	163:e59c8e839560	6369	* @retval None
AnnaBridge	163:e59c8e839560	6370	*/
AnnaBridge	163:e59c8e839560	6371	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
AnnaBridge	163:e59c8e839560	6372
AnnaBridge	163:e59c8e839560	6373	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	163:e59c8e839560	6374	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6375	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	163:e59c8e839560	6376	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	163:e59c8e839560	6377	*/
AnnaBridge	163:e59c8e839560	6378	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
AnnaBridge	163:e59c8e839560	6379
AnnaBridge	163:e59c8e839560	6380	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	163:e59c8e839560	6381	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	163:e59c8e839560	6382	STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6383	* @param __SOURCE__ specifies the DFSDM1 Audio clock source.
AnnaBridge	163:e59c8e839560	6384	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	163:e59c8e839560	6386	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	163:e59c8e839560	6387	*/
AnnaBridge	163:e59c8e839560	6388	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6389
AnnaBridge	163:e59c8e839560	6390	/** @brief Macro to Get DFSDM1 Audio clock source selection.
AnnaBridge	163:e59c8e839560	6391	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	163:e59c8e839560	6392	STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6393	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	163:e59c8e839560	6395	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	163:e59c8e839560	6396	*/
AnnaBridge	163:e59c8e839560	6397	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
AnnaBridge	163:e59c8e839560	6398
AnnaBridge	163:e59c8e839560	6399	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6400	/** @brief Macro to configure the DFSDM2 clock.
AnnaBridge	163:e59c8e839560	6401	* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge	163:e59c8e839560	6402	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6403	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	163:e59c8e839560	6404	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	163:e59c8e839560	6405	* @retval None
AnnaBridge	163:e59c8e839560	6406	*/
AnnaBridge	163:e59c8e839560	6407	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
AnnaBridge	163:e59c8e839560	6408
AnnaBridge	163:e59c8e839560	6409	/** @brief Macro to get the DFSDM2 clock source.
AnnaBridge	163:e59c8e839560	6410	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6411	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	163:e59c8e839560	6412	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	163:e59c8e839560	6413	*/
AnnaBridge	163:e59c8e839560	6414	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
AnnaBridge	163:e59c8e839560	6415
AnnaBridge	163:e59c8e839560	6416	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	163:e59c8e839560	6417	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6418	* @param __SOURCE__ specifies the DFSDM2 Audio clock source.
AnnaBridge	163:e59c8e839560	6419	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	163:e59c8e839560	6421	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	163:e59c8e839560	6422	*/
AnnaBridge	163:e59c8e839560	6423	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6424
AnnaBridge	163:e59c8e839560	6425	/** @brief Macro to Get DFSDM2 Audio clock source selection.
AnnaBridge	163:e59c8e839560	6426	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6427	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	163:e59c8e839560	6429	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	163:e59c8e839560	6430	*/
AnnaBridge	163:e59c8e839560	6431	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
AnnaBridge	163:e59c8e839560	6432
AnnaBridge	163:e59c8e839560	6433	/** @brief Macro to configure SAI1BlockA clock source selection.
AnnaBridge	163:e59c8e839560	6434	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6435	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6436	* the SAI clock.
AnnaBridge	163:e59c8e839560	6437	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	163:e59c8e839560	6438	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6439	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6440	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6441	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6442	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6443	*/
AnnaBridge	163:e59c8e839560	6444	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6445
AnnaBridge	163:e59c8e839560	6446	/** @brief Macro to Get SAI1 BlockA clock source selection.
AnnaBridge	163:e59c8e839560	6447	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6448	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6449	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6450	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6451	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6452	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6453	*/
AnnaBridge	163:e59c8e839560	6454	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
AnnaBridge	163:e59c8e839560	6455
AnnaBridge	163:e59c8e839560	6456	/** @brief Macro to configure SAI1 BlockB clock source selection.
AnnaBridge	163:e59c8e839560	6457	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6458	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	163:e59c8e839560	6459	* the SAI clock.
AnnaBridge	163:e59c8e839560	6460	* @param __SOURCE__ specifies the SAI Block B clock source.
AnnaBridge	163:e59c8e839560	6461	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6462	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6463	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6464	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6465	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6466	*/
AnnaBridge	163:e59c8e839560	6467	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6468
AnnaBridge	163:e59c8e839560	6469	/** @brief Macro to Get SAI1 BlockB clock source selection.
AnnaBridge	163:e59c8e839560	6470	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6471	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6472	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6473	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6474	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	163:e59c8e839560	6475	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6476	*/
AnnaBridge	163:e59c8e839560	6477	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
AnnaBridge	163:e59c8e839560	6478
AnnaBridge	163:e59c8e839560	6479	/** @brief Macro to configure the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6480	* @param __SOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	163:e59c8e839560	6481	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6482	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6483	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6484	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6485	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6486	*/
AnnaBridge	163:e59c8e839560	6487	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6488
AnnaBridge	163:e59c8e839560	6489	/** @brief Macro to Get the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6490	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6491	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6492	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6493	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6494	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6495	*/
AnnaBridge	163:e59c8e839560	6496	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
AnnaBridge	163:e59c8e839560	6497	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6498
AnnaBridge	163:e59c8e839560	6499	/** @brief Macro to configure I2S APB1 clock source selection.
AnnaBridge	163:e59c8e839560	6500	* @param __SOURCE__ specifies the I2S APB1 clock source.
AnnaBridge	163:e59c8e839560	6501	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6502	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	163:e59c8e839560	6503	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	163:e59c8e839560	6505	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6506	*/
AnnaBridge	163:e59c8e839560	6507	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6508
AnnaBridge	163:e59c8e839560	6509	/** @brief Macro to Get I2S APB1 clock source selection.
AnnaBridge	163:e59c8e839560	6510	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6511	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	163:e59c8e839560	6512	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	163:e59c8e839560	6514	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6515	*/
AnnaBridge	163:e59c8e839560	6516	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
AnnaBridge	163:e59c8e839560	6517
AnnaBridge	163:e59c8e839560	6518	/** @brief Macro to configure I2S APB2 clock source selection.
AnnaBridge	163:e59c8e839560	6519	* @param __SOURCE__ specifies the I2S APB2 clock source.
AnnaBridge	163:e59c8e839560	6520	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6521	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	163:e59c8e839560	6522	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	163:e59c8e839560	6524	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6525	*/
AnnaBridge	163:e59c8e839560	6526	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6527
AnnaBridge	163:e59c8e839560	6528	/** @brief Macro to Get I2S APB2 clock source selection.
AnnaBridge	163:e59c8e839560	6529	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6530	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	163:e59c8e839560	6531	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	163:e59c8e839560	6533	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6534	*/
AnnaBridge	163:e59c8e839560	6535	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
AnnaBridge	163:e59c8e839560	6536
AnnaBridge	163:e59c8e839560	6537	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
AnnaBridge	163:e59c8e839560	6538	* @note This macro must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	6539	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	163:e59c8e839560	6540	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6541	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	163:e59c8e839560	6542	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	6543	* used as I2S clock source.
AnnaBridge	163:e59c8e839560	6544	*/
AnnaBridge	163:e59c8e839560	6545	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
AnnaBridge	163:e59c8e839560	6546
AnnaBridge	163:e59c8e839560	6547	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6548	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	163:e59c8e839560	6549	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6550	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6551	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6552	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6553	*/
AnnaBridge	163:e59c8e839560	6554	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6555
AnnaBridge	163:e59c8e839560	6556	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6557	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6558	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6559	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6560	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6561	*/
AnnaBridge	163:e59c8e839560	6562	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	163:e59c8e839560	6563
AnnaBridge	163:e59c8e839560	6564	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6565	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	163:e59c8e839560	6566	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6567	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6568	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6569	*/
AnnaBridge	163:e59c8e839560	6570	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6571
AnnaBridge	163:e59c8e839560	6572	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	163:e59c8e839560	6573	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6574	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	163:e59c8e839560	6575	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
AnnaBridge	163:e59c8e839560	6576	*/
AnnaBridge	163:e59c8e839560	6577	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
AnnaBridge	163:e59c8e839560	6578
AnnaBridge	163:e59c8e839560	6579	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6580	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	163:e59c8e839560	6581	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6582	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6583	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6584	*/
AnnaBridge	163:e59c8e839560	6585	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6586
AnnaBridge	163:e59c8e839560	6587	/** @brief Macro to Get the SDIO clock.
AnnaBridge	163:e59c8e839560	6588	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6589	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6590	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	163:e59c8e839560	6591	*/
AnnaBridge	163:e59c8e839560	6592	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
AnnaBridge	163:e59c8e839560	6593
AnnaBridge	163:e59c8e839560	6594	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	6595
AnnaBridge	163:e59c8e839560	6596	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	6597	/** @brief Macro to configure I2S clock source selection.
AnnaBridge	163:e59c8e839560	6598	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	163:e59c8e839560	6599	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6600	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
AnnaBridge	163:e59c8e839560	6601	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6602	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
AnnaBridge	163:e59c8e839560	6603	*/
AnnaBridge	163:e59c8e839560	6604	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
AnnaBridge	163:e59c8e839560	6605
AnnaBridge	163:e59c8e839560	6606	/** @brief Macro to Get I2S clock source selection.
AnnaBridge	163:e59c8e839560	6607	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6608	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
AnnaBridge	163:e59c8e839560	6609	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	163:e59c8e839560	6610	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
AnnaBridge	163:e59c8e839560	6611	*/
AnnaBridge	163:e59c8e839560	6612	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
AnnaBridge	163:e59c8e839560	6613
AnnaBridge	163:e59c8e839560	6614	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6615	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	163:e59c8e839560	6616	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6617	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6618	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6619	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6620	*/
AnnaBridge	163:e59c8e839560	6621	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6622
AnnaBridge	163:e59c8e839560	6623	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6624	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6625	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6626	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6627	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	163:e59c8e839560	6628	*/
AnnaBridge	163:e59c8e839560	6629	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	163:e59c8e839560	6630
AnnaBridge	163:e59c8e839560	6631	/** @brief Macro to configure the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6632	* @param __SOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	163:e59c8e839560	6633	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6634	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6635	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6636	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6637	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6638	*/
AnnaBridge	163:e59c8e839560	6639	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	163:e59c8e839560	6640
AnnaBridge	163:e59c8e839560	6641	/** @brief Macro to Get the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6642	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	6643	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6644	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6645	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6646	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	163:e59c8e839560	6647	*/
AnnaBridge	163:e59c8e839560	6648	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
AnnaBridge	163:e59c8e839560	6649	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	6650
AnnaBridge	163:e59c8e839560	6651	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	6652	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
AnnaBridge	163:e59c8e839560	6653	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	163:e59c8e839560	6654	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	163:e59c8e839560	6655	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6656	/** @brief Macro to configure the Timers clocks prescalers
AnnaBridge	163:e59c8e839560	6657	* @note This feature is only available with STM32F429x/439x Devices.
AnnaBridge	163:e59c8e839560	6658	* @param __PRESC__ specifies the Timers clocks prescalers selection
AnnaBridge	163:e59c8e839560	6659	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	6660	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	163:e59c8e839560	6661	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
AnnaBridge	163:e59c8e839560	6662	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
AnnaBridge	163:e59c8e839560	6663	* division by 4 or more.
AnnaBridge	163:e59c8e839560	6664	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	163:e59c8e839560	6665	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge	163:e59c8e839560	6666	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
AnnaBridge	163:e59c8e839560	6667	* to division by 8 or more.
AnnaBridge	163:e59c8e839560	6668	*/
AnnaBridge	163:e59c8e839560	6669	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
AnnaBridge	163:e59c8e839560	6670
AnnaBridge	163:e59c8e839560	6671	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
AnnaBridge	163:e59c8e839560	6672	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
AnnaBridge	163:e59c8e839560	6673	STM32F423xx */
AnnaBridge	163:e59c8e839560	6674
AnnaBridge	163:e59c8e839560	6675	/----------------------------------------------------------------------------/
AnnaBridge	163:e59c8e839560	6676
AnnaBridge	163:e59c8e839560	6677	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6678	/** @brief Enable PLLSAI_RDY interrupt.
AnnaBridge	163:e59c8e839560	6679	*/
AnnaBridge	163:e59c8e839560	6680	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	163:e59c8e839560	6681
AnnaBridge	163:e59c8e839560	6682	/** @brief Disable PLLSAI_RDY interrupt.
AnnaBridge	163:e59c8e839560	6683	*/
AnnaBridge	163:e59c8e839560	6684	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
AnnaBridge	163:e59c8e839560	6685
AnnaBridge	163:e59c8e839560	6686	/** @brief Clear the PLLSAI RDY interrupt pending bits.
AnnaBridge	163:e59c8e839560	6687	*/
AnnaBridge	163:e59c8e839560	6688	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
AnnaBridge	163:e59c8e839560	6689
AnnaBridge	163:e59c8e839560	6690	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
AnnaBridge	163:e59c8e839560	6691	* @retval The new state (TRUE or FALSE).
AnnaBridge	163:e59c8e839560	6692	*/
AnnaBridge	163:e59c8e839560	6693	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	163:e59c8e839560	6694
AnnaBridge	163:e59c8e839560	6695	/** @brief Check PLLSAI RDY flag is set or not.
AnnaBridge	163:e59c8e839560	6696	* @retval The new state (TRUE or FALSE).
AnnaBridge	163:e59c8e839560	6697	*/
AnnaBridge	163:e59c8e839560	6698	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
AnnaBridge	163:e59c8e839560	6699
AnnaBridge	163:e59c8e839560	6700	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6701
AnnaBridge	163:e59c8e839560	6702	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	6703	/** @brief Macros to enable or disable the RCC MCO1 feature.
AnnaBridge	163:e59c8e839560	6704	*/
AnnaBridge	163:e59c8e839560	6705	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
AnnaBridge	163:e59c8e839560	6706	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
AnnaBridge	163:e59c8e839560	6707
AnnaBridge	163:e59c8e839560	6708	/** @brief Macros to enable or disable the RCC MCO2 feature.
AnnaBridge	163:e59c8e839560	6709	*/
AnnaBridge	163:e59c8e839560	6710	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
AnnaBridge	163:e59c8e839560	6711	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
AnnaBridge	163:e59c8e839560	6712
AnnaBridge	163:e59c8e839560	6713	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	6714
AnnaBridge	163:e59c8e839560	6715	/**
AnnaBridge	163:e59c8e839560	6716	* @}
AnnaBridge	163:e59c8e839560	6717	*/
AnnaBridge	163:e59c8e839560	6718
AnnaBridge	163:e59c8e839560	6719	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	6720	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	163:e59c8e839560	6721	* @{
AnnaBridge	163:e59c8e839560	6722	*/
AnnaBridge	163:e59c8e839560	6723
AnnaBridge	163:e59c8e839560	6724	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	163:e59c8e839560	6725	* @{
AnnaBridge	163:e59c8e839560	6726	*/
AnnaBridge	163:e59c8e839560	6727	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	163:e59c8e839560	6728	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	163:e59c8e839560	6729
AnnaBridge	163:e59c8e839560	6730	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	163:e59c8e839560	6731
AnnaBridge	163:e59c8e839560	6732	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
AnnaBridge	163:e59c8e839560	6733	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	163:e59c8e839560	6734	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	163:e59c8e839560	6735	defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6736	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
AnnaBridge	163:e59c8e839560	6737	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6738	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	163:e59c8e839560	6739	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
AnnaBridge	163:e59c8e839560	6740	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
AnnaBridge	163:e59c8e839560	6741	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	163:e59c8e839560	6742	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	163:e59c8e839560	6743	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
AnnaBridge	163:e59c8e839560	6744	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
AnnaBridge	163:e59c8e839560	6745	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	163:e59c8e839560	6746	/**
AnnaBridge	163:e59c8e839560	6747	* @}
AnnaBridge	163:e59c8e839560	6748	*/
AnnaBridge	163:e59c8e839560	6749
AnnaBridge	163:e59c8e839560	6750	/**
AnnaBridge	163:e59c8e839560	6751	* @}
AnnaBridge	163:e59c8e839560	6752	*/
AnnaBridge	163:e59c8e839560	6753	/* Private types -------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	6754	/* Private variables ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	6755	/* Private constants ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	6756	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
AnnaBridge	163:e59c8e839560	6757	* @{
AnnaBridge	163:e59c8e839560	6758	*/
AnnaBridge	163:e59c8e839560	6759
AnnaBridge	163:e59c8e839560	6760	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
AnnaBridge	163:e59c8e839560	6761	* @brief RCC registers bit address in the alias region
AnnaBridge	163:e59c8e839560	6762	* @{
AnnaBridge	163:e59c8e839560	6763	*/
AnnaBridge	163:e59c8e839560	6764	/* --- CR Register ---*/
AnnaBridge	163:e59c8e839560	6765	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	6766	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6767	/* Alias word address of PLLSAION bit */
AnnaBridge	163:e59c8e839560	6768	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
AnnaBridge	163:e59c8e839560	6769	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6770
AnnaBridge	163:e59c8e839560	6771	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	163:e59c8e839560	6772	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6773
AnnaBridge	163:e59c8e839560	6774	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	6775	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	6776	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	163:e59c8e839560	6777	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	6778	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6779	/* Alias word address of PLLI2SON bit */
AnnaBridge	163:e59c8e839560	6780	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
AnnaBridge	163:e59c8e839560	6781	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6782	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	6783	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	163:e59c8e839560	6784	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6785
AnnaBridge	163:e59c8e839560	6786	/* --- DCKCFGR Register ---*/
AnnaBridge	163:e59c8e839560	6787	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	6788	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
AnnaBridge	163:e59c8e839560	6789	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	163:e59c8e839560	6790	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	163:e59c8e839560	6791	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6792	/* Alias word address of TIMPRE bit */
AnnaBridge	163:e59c8e839560	6793	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
AnnaBridge	163:e59c8e839560	6794	#define RCC_TIMPRE_BIT_NUMBER 0x18U
AnnaBridge	163:e59c8e839560	6795	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6796	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
AnnaBridge	163:e59c8e839560	6797	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	163:e59c8e839560	6798	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6799
AnnaBridge	163:e59c8e839560	6800	/* --- CFGR Register ---*/
AnnaBridge	163:e59c8e839560	6801	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
AnnaBridge	163:e59c8e839560	6802	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	6803	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	6804	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	163:e59c8e839560	6805	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6806	/* Alias word address of I2SSRC bit */
AnnaBridge	163:e59c8e839560	6807	#define RCC_I2SSRC_BIT_NUMBER 0x17U
AnnaBridge	163:e59c8e839560	6808	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6809
AnnaBridge	163:e59c8e839560	6810	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	163:e59c8e839560	6811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	6812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6813
AnnaBridge	163:e59c8e839560	6814	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	6815	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6816	/* --- PLLI2SCFGR Register ---*/
AnnaBridge	163:e59c8e839560	6817	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
AnnaBridge	163:e59c8e839560	6818	/* Alias word address of PLLI2SSRC bit */
AnnaBridge	163:e59c8e839560	6819	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
AnnaBridge	163:e59c8e839560	6820	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6821
AnnaBridge	163:e59c8e839560	6822	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	163:e59c8e839560	6823	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	163:e59c8e839560	6824
AnnaBridge	163:e59c8e839560	6825	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	6826	/* Alias word address of MCO1EN bit */
AnnaBridge	163:e59c8e839560	6827	#define RCC_MCO1EN_BIT_NUMBER 0x8U
AnnaBridge	163:e59c8e839560	6828	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6829
AnnaBridge	163:e59c8e839560	6830	/* Alias word address of MCO2EN bit */
AnnaBridge	163:e59c8e839560	6831	#define RCC_MCO2EN_BIT_NUMBER 0x9U
AnnaBridge	163:e59c8e839560	6832	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
AnnaBridge	163:e59c8e839560	6833	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	6834
AnnaBridge	163:e59c8e839560	6835	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge	163:e59c8e839560	6836	/**
AnnaBridge	163:e59c8e839560	6837	* @}
AnnaBridge	163:e59c8e839560	6838	*/
AnnaBridge	163:e59c8e839560	6839
AnnaBridge	163:e59c8e839560	6840	/**
AnnaBridge	163:e59c8e839560	6841	* @}
AnnaBridge	163:e59c8e839560	6842	*/
AnnaBridge	163:e59c8e839560	6843
AnnaBridge	163:e59c8e839560	6844	/* Private macros ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	6845	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	163:e59c8e839560	6846	* @{
AnnaBridge	163:e59c8e839560	6847	*/
AnnaBridge	163:e59c8e839560	6848	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	163:e59c8e839560	6849	* @{
AnnaBridge	163:e59c8e839560	6850	*/
AnnaBridge	163:e59c8e839560	6851	#if defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	6852	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	163:e59c8e839560	6853	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	163:e59c8e839560	6854	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
AnnaBridge	163:e59c8e839560	6855	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
AnnaBridge	163:e59c8e839560	6856	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
AnnaBridge	163:e59c8e839560	6857	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6858	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	163:e59c8e839560	6859	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	163:e59c8e839560	6860	#endif /* STM32F411xE */
AnnaBridge	163:e59c8e839560	6861
AnnaBridge	163:e59c8e839560	6862	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
AnnaBridge	163:e59c8e839560	6863	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
AnnaBridge	163:e59c8e839560	6864	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	163:e59c8e839560	6865
AnnaBridge	163:e59c8e839560	6866	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	163:e59c8e839560	6867	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
AnnaBridge	163:e59c8e839560	6868	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	163:e59c8e839560	6869
AnnaBridge	163:e59c8e839560	6870	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	163:e59c8e839560	6871	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
AnnaBridge	163:e59c8e839560	6872	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	163:e59c8e839560	6873
AnnaBridge	163:e59c8e839560	6874	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	6875	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
AnnaBridge	163:e59c8e839560	6876	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	6877
AnnaBridge	163:e59c8e839560	6878	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	6879	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
AnnaBridge	163:e59c8e839560	6880	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	6881
AnnaBridge	163:e59c8e839560	6882	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6883	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
AnnaBridge	163:e59c8e839560	6884	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6885
AnnaBridge	163:e59c8e839560	6886	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	163:e59c8e839560	6887	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
AnnaBridge	163:e59c8e839560	6888	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	163:e59c8e839560	6889
AnnaBridge	163:e59c8e839560	6890	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6891	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
AnnaBridge	163:e59c8e839560	6892	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6893
AnnaBridge	163:e59c8e839560	6894	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	6895
AnnaBridge	163:e59c8e839560	6896	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
AnnaBridge	163:e59c8e839560	6897	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6898	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	163:e59c8e839560	6899
AnnaBridge	163:e59c8e839560	6900	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	163:e59c8e839560	6901
AnnaBridge	163:e59c8e839560	6902	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	163:e59c8e839560	6903
AnnaBridge	163:e59c8e839560	6904	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	6905
AnnaBridge	163:e59c8e839560	6906	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	163:e59c8e839560	6907
AnnaBridge	163:e59c8e839560	6908	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	163:e59c8e839560	6909
AnnaBridge	163:e59c8e839560	6910	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
AnnaBridge	163:e59c8e839560	6911	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
AnnaBridge	163:e59c8e839560	6912	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
AnnaBridge	163:e59c8e839560	6913	((VALUE) == RCC_PLLSAIDIVR_16))
AnnaBridge	163:e59c8e839560	6914	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	6915
AnnaBridge	163:e59c8e839560	6916	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	6917	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	6918	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	163:e59c8e839560	6919
AnnaBridge	163:e59c8e839560	6920	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	163:e59c8e839560	6921	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	163:e59c8e839560	6922	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6923
AnnaBridge	163:e59c8e839560	6924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	6925	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	6926
AnnaBridge	163:e59c8e839560	6927	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	163:e59c8e839560	6928	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	163:e59c8e839560	6929
AnnaBridge	163:e59c8e839560	6930	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	163:e59c8e839560	6931	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	163:e59c8e839560	6932	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	6933
AnnaBridge	163:e59c8e839560	6934	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	163:e59c8e839560	6935	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
AnnaBridge	163:e59c8e839560	6936	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
AnnaBridge	163:e59c8e839560	6937	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	163:e59c8e839560	6938
AnnaBridge	163:e59c8e839560	6939	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6940	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	6941	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	6942	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	6943
AnnaBridge	163:e59c8e839560	6944	#if defined(STM32F446xx)
AnnaBridge	163:e59c8e839560	6945	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	6946
AnnaBridge	163:e59c8e839560	6947	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
AnnaBridge	163:e59c8e839560	6948	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
AnnaBridge	163:e59c8e839560	6949	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
AnnaBridge	163:e59c8e839560	6950	((VALUE) == RCC_PLLI2SP_DIV8))
AnnaBridge	163:e59c8e839560	6951
AnnaBridge	163:e59c8e839560	6952	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
AnnaBridge	163:e59c8e839560	6953
AnnaBridge	163:e59c8e839560	6954	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
AnnaBridge	163:e59c8e839560	6955	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
AnnaBridge	163:e59c8e839560	6956	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
AnnaBridge	163:e59c8e839560	6957	((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge	163:e59c8e839560	6958
AnnaBridge	163:e59c8e839560	6959	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
AnnaBridge	163:e59c8e839560	6960	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	6961	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6962	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
AnnaBridge	163:e59c8e839560	6963
AnnaBridge	163:e59c8e839560	6964	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
AnnaBridge	163:e59c8e839560	6965	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	6966	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6967	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	6968
AnnaBridge	163:e59c8e839560	6969	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	6970	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	6971	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6972	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	6973
AnnaBridge	163:e59c8e839560	6974	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	6975	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	6976	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6977	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	6978
AnnaBridge	163:e59c8e839560	6979	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	163:e59c8e839560	6980	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	163:e59c8e839560	6981	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	6982
AnnaBridge	163:e59c8e839560	6983	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
AnnaBridge	163:e59c8e839560	6984	((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge	163:e59c8e839560	6985
AnnaBridge	163:e59c8e839560	6986	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	163:e59c8e839560	6987	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
AnnaBridge	163:e59c8e839560	6988
AnnaBridge	163:e59c8e839560	6989	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	163:e59c8e839560	6990	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	6991
AnnaBridge	163:e59c8e839560	6992	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	6993	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
AnnaBridge	163:e59c8e839560	6994	#endif /* STM32F446xx */
AnnaBridge	163:e59c8e839560	6995
AnnaBridge	163:e59c8e839560	6996	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	6997	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	6998
AnnaBridge	163:e59c8e839560	6999	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
AnnaBridge	163:e59c8e839560	7000	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
AnnaBridge	163:e59c8e839560	7001	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
AnnaBridge	163:e59c8e839560	7002	((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge	163:e59c8e839560	7003
AnnaBridge	163:e59c8e839560	7004	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	163:e59c8e839560	7005	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
AnnaBridge	163:e59c8e839560	7006
AnnaBridge	163:e59c8e839560	7007	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	163:e59c8e839560	7008	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	7009
AnnaBridge	163:e59c8e839560	7010	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	7011	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
AnnaBridge	163:e59c8e839560	7012
AnnaBridge	163:e59c8e839560	7013	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	163:e59c8e839560	7014	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	163:e59c8e839560	7015	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	163:e59c8e839560	7016
AnnaBridge	163:e59c8e839560	7017	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	163:e59c8e839560	7018	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	7019	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	163:e59c8e839560	7020
AnnaBridge	163:e59c8e839560	7021	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	163:e59c8e839560	7022
AnnaBridge	163:e59c8e839560	7023	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
AnnaBridge	163:e59c8e839560	7024	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
AnnaBridge	163:e59c8e839560	7025
AnnaBridge	163:e59c8e839560	7026	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	7027	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	7028	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	7029	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	7030
AnnaBridge	163:e59c8e839560	7031	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	163:e59c8e839560	7032	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	7033	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	7034	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	7035
AnnaBridge	163:e59c8e839560	7036	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	163:e59c8e839560	7037	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	163:e59c8e839560	7038	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	7039
AnnaBridge	163:e59c8e839560	7040	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	163:e59c8e839560	7041	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
AnnaBridge	163:e59c8e839560	7042
AnnaBridge	163:e59c8e839560	7043	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	163:e59c8e839560	7044	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	7045
AnnaBridge	163:e59c8e839560	7046	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	163:e59c8e839560	7047	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	7048
AnnaBridge	163:e59c8e839560	7049	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	163:e59c8e839560	7050	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
AnnaBridge	163:e59c8e839560	7051
AnnaBridge	163:e59c8e839560	7052	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	7053	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
AnnaBridge	163:e59c8e839560	7054	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	7055
AnnaBridge	163:e59c8e839560	7056	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	163:e59c8e839560	7057	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
AnnaBridge	163:e59c8e839560	7058
AnnaBridge	163:e59c8e839560	7059	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	163:e59c8e839560	7060	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
AnnaBridge	163:e59c8e839560	7061	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
AnnaBridge	163:e59c8e839560	7062	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	163:e59c8e839560	7063
AnnaBridge	163:e59c8e839560	7064	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	163:e59c8e839560	7065	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	7066	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	7067	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	7068
AnnaBridge	163:e59c8e839560	7069	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	163:e59c8e839560	7070	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
AnnaBridge	163:e59c8e839560	7071	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
AnnaBridge	163:e59c8e839560	7072	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
AnnaBridge	163:e59c8e839560	7073
AnnaBridge	163:e59c8e839560	7074	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	163:e59c8e839560	7075
AnnaBridge	163:e59c8e839560	7076	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	163:e59c8e839560	7077
AnnaBridge	163:e59c8e839560	7078	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	7079	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	7080
AnnaBridge	163:e59c8e839560	7081	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	163:e59c8e839560	7082	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	163:e59c8e839560	7083	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	163:e59c8e839560	7084	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	163:e59c8e839560	7085	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	163:e59c8e839560	7086
AnnaBridge	163:e59c8e839560	7087	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
AnnaBridge	163:e59c8e839560	7088	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge	163:e59c8e839560	7089
AnnaBridge	163:e59c8e839560	7090	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	163:e59c8e839560	7091	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
AnnaBridge	163:e59c8e839560	7092	STM32F412Rx */
AnnaBridge	163:e59c8e839560	7093
AnnaBridge	163:e59c8e839560	7094	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	7095	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
AnnaBridge	163:e59c8e839560	7096	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge	163:e59c8e839560	7097	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	163:e59c8e839560	7098	/**
AnnaBridge	163:e59c8e839560	7099	* @}
AnnaBridge	163:e59c8e839560	7100	*/
AnnaBridge	163:e59c8e839560	7101
AnnaBridge	163:e59c8e839560	7102	/**
AnnaBridge	163:e59c8e839560	7103	* @}
AnnaBridge	163:e59c8e839560	7104	*/
AnnaBridge	163:e59c8e839560	7105
AnnaBridge	163:e59c8e839560	7106	/**
AnnaBridge	163:e59c8e839560	7107	* @}
AnnaBridge	163:e59c8e839560	7108	*/
AnnaBridge	163:e59c8e839560	7109
AnnaBridge	163:e59c8e839560	7110	/**
AnnaBridge	163:e59c8e839560	7111	* @}
AnnaBridge	163:e59c8e839560	7112	*/
AnnaBridge	163:e59c8e839560	7113	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	7114	}
AnnaBridge	163:e59c8e839560	7115	#endif
AnnaBridge	163:e59c8e839560	7116
AnnaBridge	163:e59c8e839560	7117	#endif /* __STM32F4xx_HAL_RCC_EX_H */
AnnaBridge	163:e59c8e839560	7118
AnnaBridge	163:e59c8e839560	7119	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/