mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F412ZG/TOOLCHAIN_ARM_STD/stm32f4xx_ll_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@163:e59c8e839560

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f4xx_ll_rcc.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of RCC LL module.
AnnaBridge	145:64910690c574	6	******************************************************************************
AnnaBridge	145:64910690c574	7	* @attention
AnnaBridge	145:64910690c574	8	*
AnnaBridge	145:64910690c574	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	12	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	14	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	17	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	19	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	20	* without specific prior written permission.
AnnaBridge	145:64910690c574	21	*
AnnaBridge	145:64910690c574	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	32	*
AnnaBridge	145:64910690c574	33	******************************************************************************
AnnaBridge	145:64910690c574	34	*/
AnnaBridge	145:64910690c574	35
AnnaBridge	145:64910690c574	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	37	#ifndef __STM32F4xx_LL_RCC_H
AnnaBridge	145:64910690c574	38	#define __STM32F4xx_LL_RCC_H
AnnaBridge	145:64910690c574	39
AnnaBridge	145:64910690c574	40	#ifdef __cplusplus
AnnaBridge	145:64910690c574	41	extern "C" {
AnnaBridge	145:64910690c574	42	#endif
AnnaBridge	145:64910690c574	43
AnnaBridge	145:64910690c574	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	45	#include "stm32f4xx.h"
AnnaBridge	145:64910690c574	46
AnnaBridge	145:64910690c574	47	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	145:64910690c574	48	* @{
AnnaBridge	145:64910690c574	49	*/
AnnaBridge	145:64910690c574	50
AnnaBridge	145:64910690c574	51	#if defined(RCC)
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	/** @defgroup RCC_LL RCC
AnnaBridge	145:64910690c574	54	* @{
AnnaBridge	145:64910690c574	55	*/
AnnaBridge	145:64910690c574	56
AnnaBridge	145:64910690c574	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	145:64910690c574	60	* @{
AnnaBridge	145:64910690c574	61	*/
AnnaBridge	145:64910690c574	62
AnnaBridge	145:64910690c574	63	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
AnnaBridge	145:64910690c574	64	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
AnnaBridge	145:64910690c574	65	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
AnnaBridge	145:64910690c574	66
AnnaBridge	145:64910690c574	67	/**
AnnaBridge	145:64910690c574	68	* @}
AnnaBridge	145:64910690c574	69	*/
AnnaBridge	145:64910690c574	70	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	71	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	72	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	73	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	145:64910690c574	74	* @{
AnnaBridge	145:64910690c574	75	*/
AnnaBridge	145:64910690c574	76	/**
AnnaBridge	145:64910690c574	77	* @}
AnnaBridge	145:64910690c574	78	*/
AnnaBridge	145:64910690c574	79	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	80	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	81	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	82	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	145:64910690c574	83	* @{
AnnaBridge	145:64910690c574	84	*/
AnnaBridge	145:64910690c574	85
AnnaBridge	145:64910690c574	86	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	145:64910690c574	87	* @{
AnnaBridge	145:64910690c574	88	*/
AnnaBridge	145:64910690c574	89
AnnaBridge	145:64910690c574	90	/**
AnnaBridge	145:64910690c574	91	* @brief RCC Clocks Frequency Structure
AnnaBridge	145:64910690c574	92	*/
AnnaBridge	145:64910690c574	93	typedef struct
AnnaBridge	145:64910690c574	94	{
AnnaBridge	145:64910690c574	95	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	145:64910690c574	96	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	145:64910690c574	97	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	145:64910690c574	98	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	145:64910690c574	99	} LL_RCC_ClocksTypeDef;
AnnaBridge	145:64910690c574	100
AnnaBridge	145:64910690c574	101	/**
AnnaBridge	145:64910690c574	102	* @}
AnnaBridge	145:64910690c574	103	*/
AnnaBridge	145:64910690c574	104
AnnaBridge	145:64910690c574	105	/**
AnnaBridge	145:64910690c574	106	* @}
AnnaBridge	145:64910690c574	107	*/
AnnaBridge	145:64910690c574	108	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	109
AnnaBridge	145:64910690c574	110	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	111	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	145:64910690c574	112	* @{
AnnaBridge	145:64910690c574	113	*/
AnnaBridge	145:64910690c574	114
AnnaBridge	145:64910690c574	115	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	145:64910690c574	116	* @brief Defines used to adapt values of different oscillators
AnnaBridge	145:64910690c574	117	* @note These values could be modified in the user environment according to
AnnaBridge	145:64910690c574	118	* HW set-up.
AnnaBridge	145:64910690c574	119	* @{
AnnaBridge	145:64910690c574	120	*/
AnnaBridge	145:64910690c574	121	#if !defined (HSE_VALUE)
AnnaBridge	145:64910690c574	122	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	145:64910690c574	123	#endif /* HSE_VALUE */
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	#if !defined (HSI_VALUE)
AnnaBridge	145:64910690c574	126	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	145:64910690c574	127	#endif /* HSI_VALUE */
AnnaBridge	145:64910690c574	128
AnnaBridge	145:64910690c574	129	#if !defined (LSE_VALUE)
AnnaBridge	145:64910690c574	130	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	145:64910690c574	131	#endif /* LSE_VALUE */
AnnaBridge	145:64910690c574	132
AnnaBridge	145:64910690c574	133	#if !defined (LSI_VALUE)
AnnaBridge	145:64910690c574	134	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	145:64910690c574	135	#endif /* LSI_VALUE */
AnnaBridge	145:64910690c574	136
AnnaBridge	145:64910690c574	137	#if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge	145:64910690c574	138	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
AnnaBridge	145:64910690c574	139	#endif /* EXTERNAL_CLOCK_VALUE */
AnnaBridge	145:64910690c574	140	/**
AnnaBridge	145:64910690c574	141	* @}
AnnaBridge	145:64910690c574	142	*/
AnnaBridge	145:64910690c574	143
AnnaBridge	145:64910690c574	144	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	145:64910690c574	145	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	145:64910690c574	146	* @{
AnnaBridge	145:64910690c574	147	*/
AnnaBridge	145:64910690c574	148	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	145:64910690c574	149	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	145:64910690c574	150	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	145:64910690c574	151	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	145:64910690c574	152	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	145:64910690c574	153	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	154	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
AnnaBridge	145:64910690c574	155	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	156	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	157	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
AnnaBridge	145:64910690c574	158	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	159	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	145:64910690c574	160	/**
AnnaBridge	145:64910690c574	161	* @}
AnnaBridge	145:64910690c574	162	*/
AnnaBridge	145:64910690c574	163
AnnaBridge	145:64910690c574	164	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	165	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	145:64910690c574	166	* @{
AnnaBridge	145:64910690c574	167	*/
AnnaBridge	145:64910690c574	168	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	145:64910690c574	169	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	145:64910690c574	170	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	145:64910690c574	171	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	145:64910690c574	172	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	145:64910690c574	173	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	174	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
AnnaBridge	145:64910690c574	175	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	176	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	177	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
AnnaBridge	145:64910690c574	178	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	179	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	145:64910690c574	180	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	145:64910690c574	181	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	145:64910690c574	182	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	145:64910690c574	183	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	145:64910690c574	184	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	145:64910690c574	185	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	145:64910690c574	186	#if defined(RCC_CSR_BORRSTF)
AnnaBridge	145:64910690c574	187	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	145:64910690c574	188	#endif /* RCC_CSR_BORRSTF */
AnnaBridge	145:64910690c574	189	/**
AnnaBridge	145:64910690c574	190	* @}
AnnaBridge	145:64910690c574	191	*/
AnnaBridge	145:64910690c574	192
AnnaBridge	145:64910690c574	193	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	194	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	145:64910690c574	195	* @{
AnnaBridge	145:64910690c574	196	*/
AnnaBridge	145:64910690c574	197	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	145:64910690c574	198	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	145:64910690c574	199	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	145:64910690c574	200	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	145:64910690c574	201	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	145:64910690c574	202	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	203	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
AnnaBridge	145:64910690c574	204	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	205	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	206	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
AnnaBridge	145:64910690c574	207	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	208	/**
AnnaBridge	145:64910690c574	209	* @}
AnnaBridge	145:64910690c574	210	*/
AnnaBridge	145:64910690c574	211
AnnaBridge	145:64910690c574	212	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	145:64910690c574	213	* @{
AnnaBridge	145:64910690c574	214	*/
AnnaBridge	145:64910690c574	215	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	145:64910690c574	216	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	145:64910690c574	217	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	145:64910690c574	218	#if defined(RCC_CFGR_SW_PLLR)
AnnaBridge	145:64910690c574	219	#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /!< PLLR selection as system clock /
AnnaBridge	145:64910690c574	220	#endif /* RCC_CFGR_SW_PLLR */
AnnaBridge	145:64910690c574	221	/**
AnnaBridge	145:64910690c574	222	* @}
AnnaBridge	145:64910690c574	223	*/
AnnaBridge	145:64910690c574	224
AnnaBridge	145:64910690c574	225	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	145:64910690c574	226	* @{
AnnaBridge	145:64910690c574	227	*/
AnnaBridge	145:64910690c574	228	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	145:64910690c574	229	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	145:64910690c574	230	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	145:64910690c574	231	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
AnnaBridge	145:64910690c574	232	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /!< PLLR used as system clock /
AnnaBridge	145:64910690c574	233	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
AnnaBridge	145:64910690c574	234	/**
AnnaBridge	145:64910690c574	235	* @}
AnnaBridge	145:64910690c574	236	*/
AnnaBridge	145:64910690c574	237
AnnaBridge	145:64910690c574	238	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	145:64910690c574	239	* @{
AnnaBridge	145:64910690c574	240	*/
AnnaBridge	145:64910690c574	241	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	145:64910690c574	242	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	145:64910690c574	243	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	145:64910690c574	244	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	145:64910690c574	245	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	145:64910690c574	246	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	145:64910690c574	247	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	145:64910690c574	248	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	145:64910690c574	249	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	145:64910690c574	250	/**
AnnaBridge	145:64910690c574	251	* @}
AnnaBridge	145:64910690c574	252	*/
AnnaBridge	145:64910690c574	253
AnnaBridge	145:64910690c574	254	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	145:64910690c574	255	* @{
AnnaBridge	145:64910690c574	256	*/
AnnaBridge	145:64910690c574	257	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	145:64910690c574	258	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	145:64910690c574	259	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	145:64910690c574	260	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	145:64910690c574	261	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	145:64910690c574	262	/**
AnnaBridge	145:64910690c574	263	* @}
AnnaBridge	145:64910690c574	264	*/
AnnaBridge	145:64910690c574	265
AnnaBridge	145:64910690c574	266	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	145:64910690c574	267	* @{
AnnaBridge	145:64910690c574	268	*/
AnnaBridge	145:64910690c574	269	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	145:64910690c574	270	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	145:64910690c574	271	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	145:64910690c574	272	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	145:64910690c574	273	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	145:64910690c574	274	/**
AnnaBridge	145:64910690c574	275	* @}
AnnaBridge	145:64910690c574	276	*/
AnnaBridge	145:64910690c574	277
AnnaBridge	145:64910690c574	278	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
AnnaBridge	145:64910690c574	279	* @{
AnnaBridge	145:64910690c574	280	*/
AnnaBridge	145:64910690c574	281	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
AnnaBridge	145:64910690c574	282	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
AnnaBridge	145:64910690c574	283	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
AnnaBridge	145:64910690c574	284	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
AnnaBridge	145:64910690c574	285	#if defined(RCC_CFGR_MCO2)
AnnaBridge	145:64910690c574	286	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
AnnaBridge	145:64910690c574	287	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
AnnaBridge	145:64910690c574	288	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
AnnaBridge	145:64910690c574	289	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
AnnaBridge	145:64910690c574	290	#endif /* RCC_CFGR_MCO2 */
AnnaBridge	145:64910690c574	291	/**
AnnaBridge	145:64910690c574	292	* @}
AnnaBridge	145:64910690c574	293	*/
AnnaBridge	145:64910690c574	294
AnnaBridge	145:64910690c574	295	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
AnnaBridge	145:64910690c574	296	* @{
AnnaBridge	145:64910690c574	297	*/
AnnaBridge	145:64910690c574	298	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
AnnaBridge	145:64910690c574	299	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
AnnaBridge	145:64910690c574	300	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
AnnaBridge	145:64910690c574	301	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
AnnaBridge	145:64910690c574	302	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
AnnaBridge	145:64910690c574	303	#if defined(RCC_CFGR_MCO2PRE)
AnnaBridge	145:64910690c574	304	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
AnnaBridge	145:64910690c574	305	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
AnnaBridge	145:64910690c574	306	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
AnnaBridge	145:64910690c574	307	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
AnnaBridge	145:64910690c574	308	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
AnnaBridge	145:64910690c574	309	#endif /* RCC_CFGR_MCO2PRE */
AnnaBridge	145:64910690c574	310	/**
AnnaBridge	145:64910690c574	311	* @}
AnnaBridge	145:64910690c574	312	*/
AnnaBridge	145:64910690c574	313
AnnaBridge	145:64910690c574	314	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
AnnaBridge	145:64910690c574	315	* @{
AnnaBridge	145:64910690c574	316	*/
AnnaBridge	145:64910690c574	317	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
AnnaBridge	145:64910690c574	318	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
AnnaBridge	145:64910690c574	319	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
AnnaBridge	145:64910690c574	320	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
AnnaBridge	145:64910690c574	321	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
AnnaBridge	145:64910690c574	322	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
AnnaBridge	145:64910690c574	323	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
AnnaBridge	145:64910690c574	324	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
AnnaBridge	145:64910690c574	325	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
AnnaBridge	145:64910690c574	326	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
AnnaBridge	145:64910690c574	327	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
AnnaBridge	145:64910690c574	328	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
AnnaBridge	145:64910690c574	329	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
AnnaBridge	145:64910690c574	330	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
AnnaBridge	145:64910690c574	331	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
AnnaBridge	145:64910690c574	332	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
AnnaBridge	145:64910690c574	333	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
AnnaBridge	145:64910690c574	334	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
AnnaBridge	145:64910690c574	335	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
AnnaBridge	145:64910690c574	336	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
AnnaBridge	145:64910690c574	337	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
AnnaBridge	145:64910690c574	338	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
AnnaBridge	145:64910690c574	339	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
AnnaBridge	145:64910690c574	340	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
AnnaBridge	145:64910690c574	341	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
AnnaBridge	145:64910690c574	342	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
AnnaBridge	145:64910690c574	343	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
AnnaBridge	145:64910690c574	344	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
AnnaBridge	145:64910690c574	345	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
AnnaBridge	145:64910690c574	346	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
AnnaBridge	145:64910690c574	347	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
AnnaBridge	145:64910690c574	348	/**
AnnaBridge	145:64910690c574	349	* @}
AnnaBridge	145:64910690c574	350	*/
AnnaBridge	145:64910690c574	351
AnnaBridge	145:64910690c574	352	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	353	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	145:64910690c574	354	* @{
AnnaBridge	145:64910690c574	355	*/
AnnaBridge	145:64910690c574	356	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	145:64910690c574	357	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	145:64910690c574	358	/**
AnnaBridge	145:64910690c574	359	* @}
AnnaBridge	145:64910690c574	360	*/
AnnaBridge	145:64910690c574	361	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	362
AnnaBridge	145:64910690c574	363	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	364	/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
AnnaBridge	145:64910690c574	365	* @{
AnnaBridge	145:64910690c574	366	*/
AnnaBridge	145:64910690c574	367	#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as FMPI2C1 clock source /
AnnaBridge	145:64910690c574	368	#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /!< SYSCLK clock used as FMPI2C1 clock source /
AnnaBridge	145:64910690c574	369	#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /!< HSI clock used as FMPI2C1 clock source /
AnnaBridge	145:64910690c574	370	/**
AnnaBridge	145:64910690c574	371	* @}
AnnaBridge	145:64910690c574	372	*/
AnnaBridge	145:64910690c574	373	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	374
AnnaBridge	145:64910690c574	375	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	376	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	145:64910690c574	377	* @{
AnnaBridge	145:64910690c574	378	*/
AnnaBridge	145:64910690c574	379	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
AnnaBridge	145:64910690c574	380	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
AnnaBridge	145:64910690c574	381	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
AnnaBridge	145:64910690c574	382	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
AnnaBridge	145:64910690c574	383	/**
AnnaBridge	145:64910690c574	384	* @}
AnnaBridge	145:64910690c574	385	*/
AnnaBridge	145:64910690c574	386	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	387
AnnaBridge	145:64910690c574	388	#if defined(SAI1)
AnnaBridge	145:64910690c574	389	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
AnnaBridge	145:64910690c574	390	* @{
AnnaBridge	145:64910690c574	391	*/
AnnaBridge	145:64910690c574	392	#if defined(RCC_DCKCFGR_SAI1SRC)
AnnaBridge	145:64910690c574	393	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	394	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /!< PLLI2S clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	395	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /!< PLL clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	396	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC >> 16)) /!< External pin clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	397	#endif /* RCC_DCKCFGR_SAI1SRC */
AnnaBridge	145:64910690c574	398	#if defined(RCC_DCKCFGR_SAI2SRC)
AnnaBridge	145:64910690c574	399	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	400	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /!< PLLI2S clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	401	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /!< PLL clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	402	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC >> 16)) /!< PLL Main clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	403	#endif /* RCC_DCKCFGR_SAI2SRC */
AnnaBridge	145:64910690c574	404	#if defined(RCC_DCKCFGR_SAI1ASRC)
AnnaBridge	145:64910690c574	405	#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
AnnaBridge	145:64910690c574	406	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	407	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< External pin used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	408	#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< PLL clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	409	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC >> 16)) /!< PLL Main clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	410	#else
AnnaBridge	145:64910690c574	411	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	412	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	413	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< External pin clock used as SAI1 block A clock source /
AnnaBridge	145:64910690c574	414	#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
AnnaBridge	145:64910690c574	415	#endif /* RCC_DCKCFGR_SAI1ASRC */
AnnaBridge	145:64910690c574	416	#if defined(RCC_DCKCFGR_SAI1BSRC)
AnnaBridge	145:64910690c574	417	#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
AnnaBridge	145:64910690c574	418	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	419	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< External pin used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	420	#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< PLL clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	421	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC >> 16)) /!< PLL Main clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	422	#else
AnnaBridge	145:64910690c574	423	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	424	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	425	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< External pin clock used as SAI1 block B clock source /
AnnaBridge	145:64910690c574	426	#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
AnnaBridge	145:64910690c574	427	#endif /* RCC_DCKCFGR_SAI1BSRC */
AnnaBridge	145:64910690c574	428	/**
AnnaBridge	145:64910690c574	429	* @}
AnnaBridge	145:64910690c574	430	*/
AnnaBridge	145:64910690c574	431	#endif /* SAI1 */
AnnaBridge	145:64910690c574	432
AnnaBridge	145:64910690c574	433	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	145:64910690c574	434	/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
AnnaBridge	145:64910690c574	435	* @{
AnnaBridge	145:64910690c574	436	*/
AnnaBridge	145:64910690c574	437	#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /!< PLL 48M domain clock used as SDIO clock /
AnnaBridge	145:64910690c574	438	#if defined(RCC_DCKCFGR_SDIOSEL)
AnnaBridge	145:64910690c574	439	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /!< System clock clock used as SDIO clock /
AnnaBridge	145:64910690c574	440	#else
AnnaBridge	145:64910690c574	441	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /!< System clock clock used as SDIO clock /
AnnaBridge	145:64910690c574	442	#endif /* RCC_DCKCFGR_SDIOSEL */
AnnaBridge	145:64910690c574	443	/**
AnnaBridge	145:64910690c574	444	* @}
AnnaBridge	145:64910690c574	445	*/
AnnaBridge	145:64910690c574	446	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
AnnaBridge	145:64910690c574	447
AnnaBridge	145:64910690c574	448	#if defined(DSI)
AnnaBridge	145:64910690c574	449	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
AnnaBridge	145:64910690c574	450	* @{
AnnaBridge	145:64910690c574	451	*/
AnnaBridge	145:64910690c574	452	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
AnnaBridge	145:64910690c574	453	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /!< PLL clock used as DSI byte lane clock source /
AnnaBridge	145:64910690c574	454	/**
AnnaBridge	145:64910690c574	455	* @}
AnnaBridge	145:64910690c574	456	*/
AnnaBridge	145:64910690c574	457	#endif /* DSI */
AnnaBridge	145:64910690c574	458
AnnaBridge	145:64910690c574	459	#if defined(CEC)
AnnaBridge	145:64910690c574	460	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
AnnaBridge	145:64910690c574	461	* @{
AnnaBridge	145:64910690c574	462	*/
AnnaBridge	145:64910690c574	463	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /!< HSI oscillator clock divided by 488 used as CEC clock /
AnnaBridge	145:64910690c574	464	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /!< LSE oscillator clock used as CEC clock /
AnnaBridge	145:64910690c574	465	/**
AnnaBridge	145:64910690c574	466	* @}
AnnaBridge	145:64910690c574	467	*/
AnnaBridge	145:64910690c574	468	#endif /* CEC */
AnnaBridge	145:64910690c574	469
AnnaBridge	145:64910690c574	470	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
AnnaBridge	145:64910690c574	471	* @{
AnnaBridge	145:64910690c574	472	*/
AnnaBridge	145:64910690c574	473	#if defined(RCC_CFGR_I2SSRC)
AnnaBridge	145:64910690c574	474	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
AnnaBridge	145:64910690c574	475	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
AnnaBridge	145:64910690c574	476	#endif /* RCC_CFGR_I2SSRC */
AnnaBridge	145:64910690c574	477	#if defined(RCC_DCKCFGR_I2SSRC)
AnnaBridge	145:64910690c574	478	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC \| 0x00000000U) /!< PLL clock used as I2S1 clock source /
AnnaBridge	145:64910690c574	479	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_0 >> 16)) /!< External pin used as I2S1 clock source /
AnnaBridge	145:64910690c574	480	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_1 >> 16)) /!< PLL Main clock used as I2S1 clock source /
AnnaBridge	145:64910690c574	481	#endif /* RCC_DCKCFGR_I2SSRC */
AnnaBridge	145:64910690c574	482	#if defined(RCC_DCKCFGR_I2S1SRC)
AnnaBridge	145:64910690c574	483	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC \| 0x00000000U) /!< PLLI2S clock used as I2S1 clock source /
AnnaBridge	145:64910690c574	484	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /!< External pin used as I2S1 clock source /
AnnaBridge	145:64910690c574	485	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /!< PLL clock used as I2S1 clock source /
AnnaBridge	145:64910690c574	486	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC >> 16)) /!< PLL Main clock used as I2S1 clock source /
AnnaBridge	145:64910690c574	487	#endif /* RCC_DCKCFGR_I2S1SRC */
AnnaBridge	145:64910690c574	488	#if defined(RCC_DCKCFGR_I2S2SRC)
AnnaBridge	145:64910690c574	489	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC \| 0x00000000U) /!< PLLI2S clock used as I2S2 clock source /
AnnaBridge	145:64910690c574	490	#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /!< External pin used as I2S2 clock source /
AnnaBridge	145:64910690c574	491	#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /!< PLL clock used as I2S2 clock source /
AnnaBridge	145:64910690c574	492	#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC >> 16)) /!< PLL Main clock used as I2S2 clock source /
AnnaBridge	145:64910690c574	493	#endif /* RCC_DCKCFGR_I2S2SRC */
AnnaBridge	145:64910690c574	494	/**
AnnaBridge	145:64910690c574	495	* @}
AnnaBridge	145:64910690c574	496	*/
AnnaBridge	145:64910690c574	497
AnnaBridge	145:64910690c574	498	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	499	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
AnnaBridge	145:64910690c574	500	* @{
AnnaBridge	145:64910690c574	501	*/
AnnaBridge	145:64910690c574	502	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	503	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
AnnaBridge	145:64910690c574	504	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
AnnaBridge	145:64910690c574	505	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	506	#if defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	507	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
AnnaBridge	145:64910690c574	508	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	509	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
AnnaBridge	145:64910690c574	510	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	511	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	512	#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /!< PLLI2S oscillator clock used as 48Mhz domain clock /
AnnaBridge	145:64910690c574	513	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	514	#endif /* RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	515	/**
AnnaBridge	145:64910690c574	516	* @}
AnnaBridge	145:64910690c574	517	*/
AnnaBridge	145:64910690c574	518
AnnaBridge	145:64910690c574	519	#if defined(RNG)
AnnaBridge	145:64910690c574	520	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	145:64910690c574	521	* @{
AnnaBridge	145:64910690c574	522	*/
AnnaBridge	145:64910690c574	523	#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as RNG clock source /
AnnaBridge	145:64910690c574	524	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	525	#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as RNG clock source /
AnnaBridge	145:64910690c574	526	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	527	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	528	#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as RNG clock source /
AnnaBridge	145:64910690c574	529	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	530	/**
AnnaBridge	145:64910690c574	531	* @}
AnnaBridge	145:64910690c574	532	*/
AnnaBridge	145:64910690c574	533	#endif /* RNG */
AnnaBridge	145:64910690c574	534
AnnaBridge	145:64910690c574	535	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	536	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	145:64910690c574	537	* @{
AnnaBridge	145:64910690c574	538	*/
AnnaBridge	145:64910690c574	539	#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as USB clock source /
AnnaBridge	145:64910690c574	540	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	541	#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as USB clock source /
AnnaBridge	145:64910690c574	542	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	543	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	544	#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as USB clock source /
AnnaBridge	145:64910690c574	545	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	546	/**
AnnaBridge	145:64910690c574	547	* @}
AnnaBridge	145:64910690c574	548	*/
AnnaBridge	145:64910690c574	549	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
AnnaBridge	145:64910690c574	550
AnnaBridge	145:64910690c574	551	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	552
AnnaBridge	145:64910690c574	553	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	554	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
AnnaBridge	145:64910690c574	555	* @{
AnnaBridge	145:64910690c574	556	*/
AnnaBridge	145:64910690c574	557	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM1 Audio clock source /
AnnaBridge	145:64910690c574	558	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /!< I2S2 clock used as DFSDM1 Audio clock source /
AnnaBridge	145:64910690c574	559	#if defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	560	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM2 Audio clock source /
AnnaBridge	145:64910690c574	561	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /!< I2S2 clock used as DFSDM2 Audio clock source /
AnnaBridge	145:64910690c574	562	#endif /* DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	563	/**
AnnaBridge	145:64910690c574	564	* @}
AnnaBridge	145:64910690c574	565	*/
AnnaBridge	145:64910690c574	566
AnnaBridge	145:64910690c574	567	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
AnnaBridge	145:64910690c574	568	* @{
AnnaBridge	145:64910690c574	569	*/
AnnaBridge	145:64910690c574	570	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
AnnaBridge	145:64910690c574	571	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM1 clock /
AnnaBridge	145:64910690c574	572	#if defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	573	#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM2 clock /
AnnaBridge	145:64910690c574	574	#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM2 clock /
AnnaBridge	145:64910690c574	575	#endif /* DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	576	/**
AnnaBridge	145:64910690c574	577	* @}
AnnaBridge	145:64910690c574	578	*/
AnnaBridge	145:64910690c574	579	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	580
AnnaBridge	145:64910690c574	581	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	582	/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
AnnaBridge	145:64910690c574	583	* @{
AnnaBridge	145:64910690c574	584	*/
AnnaBridge	145:64910690c574	585	#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /!< FMPI2C1 Clock source selection /
AnnaBridge	145:64910690c574	586	/**
AnnaBridge	145:64910690c574	587	* @}
AnnaBridge	145:64910690c574	588	*/
AnnaBridge	145:64910690c574	589	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	590
AnnaBridge	145:64910690c574	591	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	592	/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
AnnaBridge	145:64910690c574	593	* @{
AnnaBridge	145:64910690c574	594	*/
AnnaBridge	145:64910690c574	595	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as SPDIFRX clock source /
AnnaBridge	145:64910690c574	596	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /!< PLLI2S clock used as SPDIFRX clock source /
AnnaBridge	145:64910690c574	597	/**
AnnaBridge	145:64910690c574	598	* @}
AnnaBridge	145:64910690c574	599	*/
AnnaBridge	145:64910690c574	600	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	601
AnnaBridge	145:64910690c574	602	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	603	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
AnnaBridge	145:64910690c574	604	* @{
AnnaBridge	145:64910690c574	605	*/
AnnaBridge	145:64910690c574	606	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
AnnaBridge	145:64910690c574	607	/**
AnnaBridge	145:64910690c574	608	* @}
AnnaBridge	145:64910690c574	609	*/
AnnaBridge	145:64910690c574	610	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	611
AnnaBridge	145:64910690c574	612	#if defined(SAI1)
AnnaBridge	145:64910690c574	613	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
AnnaBridge	145:64910690c574	614	* @{
AnnaBridge	145:64910690c574	615	*/
AnnaBridge	145:64910690c574	616	#if defined(RCC_DCKCFGR_SAI1ASRC)
AnnaBridge	145:64910690c574	617	#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /!< SAI1 block A Clock source selection /
AnnaBridge	145:64910690c574	618	#endif /* RCC_DCKCFGR_SAI1ASRC */
AnnaBridge	145:64910690c574	619	#if defined(RCC_DCKCFGR_SAI1BSRC)
AnnaBridge	145:64910690c574	620	#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /!< SAI1 block B Clock source selection /
AnnaBridge	145:64910690c574	621	#endif /* RCC_DCKCFGR_SAI1BSRC */
AnnaBridge	145:64910690c574	622	#if defined(RCC_DCKCFGR_SAI1SRC)
AnnaBridge	145:64910690c574	623	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /!< SAI1 Clock source selection /
AnnaBridge	145:64910690c574	624	#endif /* RCC_DCKCFGR_SAI1SRC */
AnnaBridge	145:64910690c574	625	#if defined(RCC_DCKCFGR_SAI2SRC)
AnnaBridge	145:64910690c574	626	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /!< SAI2 Clock source selection /
AnnaBridge	145:64910690c574	627	#endif /* RCC_DCKCFGR_SAI2SRC */
AnnaBridge	145:64910690c574	628	/**
AnnaBridge	145:64910690c574	629	* @}
AnnaBridge	145:64910690c574	630	*/
AnnaBridge	145:64910690c574	631	#endif /* SAI1 */
AnnaBridge	145:64910690c574	632
AnnaBridge	145:64910690c574	633	#if defined(SDIO)
AnnaBridge	145:64910690c574	634	/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
AnnaBridge	145:64910690c574	635	* @{
AnnaBridge	145:64910690c574	636	*/
AnnaBridge	145:64910690c574	637	#if defined(RCC_DCKCFGR_SDIOSEL)
AnnaBridge	145:64910690c574	638	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /!< SDIO Clock source selection /
AnnaBridge	145:64910690c574	639	#elif defined(RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	145:64910690c574	640	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /!< SDIO Clock source selection /
AnnaBridge	145:64910690c574	641	#else
AnnaBridge	145:64910690c574	642	#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /!< SDIO Clock source selection /
AnnaBridge	145:64910690c574	643	#endif
AnnaBridge	145:64910690c574	644	/**
AnnaBridge	145:64910690c574	645	* @}
AnnaBridge	145:64910690c574	646	*/
AnnaBridge	145:64910690c574	647	#endif /* SDIO */
AnnaBridge	145:64910690c574	648
AnnaBridge	145:64910690c574	649	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	650	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
AnnaBridge	145:64910690c574	651	* @{
AnnaBridge	145:64910690c574	652	*/
AnnaBridge	145:64910690c574	653	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	654	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /!< CK48M Domain clock source selection /
AnnaBridge	145:64910690c574	655	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	656	#if defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	657	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
AnnaBridge	145:64910690c574	658	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	659	/**
AnnaBridge	145:64910690c574	660	* @}
AnnaBridge	145:64910690c574	661	*/
AnnaBridge	145:64910690c574	662	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	663
AnnaBridge	145:64910690c574	664	#if defined(RNG)
AnnaBridge	145:64910690c574	665	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	145:64910690c574	666	* @{
AnnaBridge	145:64910690c574	667	*/
AnnaBridge	145:64910690c574	668	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	669	#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< RNG Clock source selection /
AnnaBridge	145:64910690c574	670	#else
AnnaBridge	145:64910690c574	671	#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /!< RNG Clock source selection /
AnnaBridge	145:64910690c574	672	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	673	/**
AnnaBridge	145:64910690c574	674	* @}
AnnaBridge	145:64910690c574	675	*/
AnnaBridge	145:64910690c574	676	#endif /* RNG */
AnnaBridge	145:64910690c574	677
AnnaBridge	145:64910690c574	678	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	679	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	145:64910690c574	680	* @{
AnnaBridge	145:64910690c574	681	*/
AnnaBridge	145:64910690c574	682	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	683	#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< USB Clock source selection /
AnnaBridge	145:64910690c574	684	#else
AnnaBridge	145:64910690c574	685	#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /!< USB Clock source selection /
AnnaBridge	145:64910690c574	686	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	687	/**
AnnaBridge	145:64910690c574	688	* @}
AnnaBridge	145:64910690c574	689	*/
AnnaBridge	145:64910690c574	690	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
AnnaBridge	145:64910690c574	691
AnnaBridge	145:64910690c574	692	#if defined(CEC)
AnnaBridge	145:64910690c574	693	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
AnnaBridge	145:64910690c574	694	* @{
AnnaBridge	145:64910690c574	695	*/
AnnaBridge	145:64910690c574	696	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
AnnaBridge	145:64910690c574	697	/**
AnnaBridge	145:64910690c574	698	* @}
AnnaBridge	145:64910690c574	699	*/
AnnaBridge	145:64910690c574	700	#endif /* CEC */
AnnaBridge	145:64910690c574	701
AnnaBridge	145:64910690c574	702	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
AnnaBridge	145:64910690c574	703	* @{
AnnaBridge	145:64910690c574	704	*/
AnnaBridge	145:64910690c574	705	#if defined(RCC_CFGR_I2SSRC)
AnnaBridge	145:64910690c574	706	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
AnnaBridge	145:64910690c574	707	#endif /* RCC_CFGR_I2SSRC */
AnnaBridge	145:64910690c574	708	#if defined(RCC_DCKCFGR_I2SSRC)
AnnaBridge	145:64910690c574	709	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /!< I2S1 Clock source selection /
AnnaBridge	145:64910690c574	710	#endif /* RCC_DCKCFGR_I2SSRC */
AnnaBridge	145:64910690c574	711	#if defined(RCC_DCKCFGR_I2S1SRC)
AnnaBridge	145:64910690c574	712	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /!< I2S1 Clock source selection /
AnnaBridge	145:64910690c574	713	#endif /* RCC_DCKCFGR_I2S1SRC */
AnnaBridge	145:64910690c574	714	#if defined(RCC_DCKCFGR_I2S2SRC)
AnnaBridge	145:64910690c574	715	#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /!< I2S2 Clock source selection /
AnnaBridge	145:64910690c574	716	#endif /* RCC_DCKCFGR_I2S2SRC */
AnnaBridge	145:64910690c574	717	/**
AnnaBridge	145:64910690c574	718	* @}
AnnaBridge	145:64910690c574	719	*/
AnnaBridge	145:64910690c574	720
AnnaBridge	145:64910690c574	721	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	722	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
AnnaBridge	145:64910690c574	723	* @{
AnnaBridge	145:64910690c574	724	*/
AnnaBridge	145:64910690c574	725	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /!< DFSDM1 Audio Clock source selection /
AnnaBridge	145:64910690c574	726	#if defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	727	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /!< DFSDM2 Audio Clock source selection /
AnnaBridge	145:64910690c574	728	#endif /* DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	729	/**
AnnaBridge	145:64910690c574	730	* @}
AnnaBridge	145:64910690c574	731	*/
AnnaBridge	145:64910690c574	732
AnnaBridge	145:64910690c574	733	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
AnnaBridge	145:64910690c574	734	* @{
AnnaBridge	145:64910690c574	735	*/
AnnaBridge	145:64910690c574	736	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	145:64910690c574	737	#if defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	738	#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM2 Clock source selection /
AnnaBridge	145:64910690c574	739	#endif /* DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	740	/**
AnnaBridge	145:64910690c574	741	* @}
AnnaBridge	145:64910690c574	742	*/
AnnaBridge	145:64910690c574	743	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	744
AnnaBridge	145:64910690c574	745	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	746	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
AnnaBridge	145:64910690c574	747	* @{
AnnaBridge	145:64910690c574	748	*/
AnnaBridge	145:64910690c574	749	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /!< SPDIFRX Clock source selection /
AnnaBridge	145:64910690c574	750	/**
AnnaBridge	145:64910690c574	751	* @}
AnnaBridge	145:64910690c574	752	*/
AnnaBridge	145:64910690c574	753	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	754
AnnaBridge	145:64910690c574	755	#if defined(DSI)
AnnaBridge	145:64910690c574	756	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
AnnaBridge	145:64910690c574	757	* @{
AnnaBridge	145:64910690c574	758	*/
AnnaBridge	145:64910690c574	759	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /!< DSI Clock source selection /
AnnaBridge	145:64910690c574	760	/**
AnnaBridge	145:64910690c574	761	* @}
AnnaBridge	145:64910690c574	762	*/
AnnaBridge	145:64910690c574	763	#endif /* DSI */
AnnaBridge	145:64910690c574	764
AnnaBridge	145:64910690c574	765	#if defined(LTDC)
AnnaBridge	145:64910690c574	766	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
AnnaBridge	145:64910690c574	767	* @{
AnnaBridge	145:64910690c574	768	*/
AnnaBridge	145:64910690c574	769	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /!< LTDC Clock source selection /
AnnaBridge	145:64910690c574	770	/**
AnnaBridge	145:64910690c574	771	* @}
AnnaBridge	145:64910690c574	772	*/
AnnaBridge	145:64910690c574	773	#endif /* LTDC */
AnnaBridge	145:64910690c574	774
AnnaBridge	145:64910690c574	775
AnnaBridge	145:64910690c574	776	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	145:64910690c574	777	* @{
AnnaBridge	145:64910690c574	778	*/
AnnaBridge	145:64910690c574	779	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	145:64910690c574	780	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	145:64910690c574	781	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	145:64910690c574	782	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
AnnaBridge	145:64910690c574	783	/**
AnnaBridge	145:64910690c574	784	* @}
AnnaBridge	145:64910690c574	785	*/
AnnaBridge	145:64910690c574	786
AnnaBridge	145:64910690c574	787	#if defined(RCC_DCKCFGR_TIMPRE)
AnnaBridge	145:64910690c574	788	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
AnnaBridge	145:64910690c574	789	* @{
AnnaBridge	145:64910690c574	790	*/
AnnaBridge	145:64910690c574	791	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
AnnaBridge	145:64910690c574	792	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /!< Timers clock to four time PCLK /
AnnaBridge	145:64910690c574	793	/**
AnnaBridge	145:64910690c574	794	* @}
AnnaBridge	145:64910690c574	795	*/
AnnaBridge	145:64910690c574	796	#endif /* RCC_DCKCFGR_TIMPRE */
AnnaBridge	145:64910690c574	797
AnnaBridge	145:64910690c574	798	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
AnnaBridge	145:64910690c574	799	* @{
AnnaBridge	145:64910690c574	800	*/
AnnaBridge	145:64910690c574	801	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	145:64910690c574	802	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	145:64910690c574	803	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
AnnaBridge	145:64910690c574	804	#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC \| 0x80U) /!< I2S External pin input clock selected as PLLI2S entry clock source /
AnnaBridge	145:64910690c574	805	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
AnnaBridge	145:64910690c574	806	/**
AnnaBridge	145:64910690c574	807	* @}
AnnaBridge	145:64910690c574	808	*/
AnnaBridge	145:64910690c574	809
AnnaBridge	145:64910690c574	810	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
AnnaBridge	145:64910690c574	811	* @{
AnnaBridge	145:64910690c574	812	*/
AnnaBridge	145:64910690c574	813	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
AnnaBridge	145:64910690c574	814	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
AnnaBridge	145:64910690c574	815	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
AnnaBridge	145:64910690c574	816	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
AnnaBridge	145:64910690c574	817	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
AnnaBridge	145:64910690c574	818	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
AnnaBridge	145:64910690c574	819	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
AnnaBridge	145:64910690c574	820	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
AnnaBridge	145:64910690c574	821	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
AnnaBridge	145:64910690c574	822	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
AnnaBridge	145:64910690c574	823	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
AnnaBridge	145:64910690c574	824	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
AnnaBridge	145:64910690c574	825	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
AnnaBridge	145:64910690c574	826	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
AnnaBridge	145:64910690c574	827	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
AnnaBridge	145:64910690c574	828	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
AnnaBridge	145:64910690c574	829	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
AnnaBridge	145:64910690c574	830	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
AnnaBridge	145:64910690c574	831	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
AnnaBridge	145:64910690c574	832	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
AnnaBridge	145:64910690c574	833	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
AnnaBridge	145:64910690c574	834	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
AnnaBridge	145:64910690c574	835	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
AnnaBridge	145:64910690c574	836	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
AnnaBridge	145:64910690c574	837	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
AnnaBridge	145:64910690c574	838	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
AnnaBridge	145:64910690c574	839	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
AnnaBridge	145:64910690c574	840	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
AnnaBridge	145:64910690c574	841	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
AnnaBridge	145:64910690c574	842	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
AnnaBridge	145:64910690c574	843	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
AnnaBridge	145:64910690c574	844	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
AnnaBridge	145:64910690c574	845	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
AnnaBridge	145:64910690c574	846	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
AnnaBridge	145:64910690c574	847	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
AnnaBridge	145:64910690c574	848	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
AnnaBridge	145:64910690c574	849	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
AnnaBridge	145:64910690c574	850	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
AnnaBridge	145:64910690c574	851	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
AnnaBridge	145:64910690c574	852	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
AnnaBridge	145:64910690c574	853	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
AnnaBridge	145:64910690c574	854	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
AnnaBridge	145:64910690c574	855	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
AnnaBridge	145:64910690c574	856	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
AnnaBridge	145:64910690c574	857	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
AnnaBridge	145:64910690c574	858	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
AnnaBridge	145:64910690c574	859	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
AnnaBridge	145:64910690c574	860	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
AnnaBridge	145:64910690c574	861	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
AnnaBridge	145:64910690c574	862	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
AnnaBridge	145:64910690c574	863	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
AnnaBridge	145:64910690c574	864	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
AnnaBridge	145:64910690c574	865	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
AnnaBridge	145:64910690c574	866	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
AnnaBridge	145:64910690c574	867	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
AnnaBridge	145:64910690c574	868	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
AnnaBridge	145:64910690c574	869	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
AnnaBridge	145:64910690c574	870	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
AnnaBridge	145:64910690c574	871	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
AnnaBridge	145:64910690c574	872	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
AnnaBridge	145:64910690c574	873	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
AnnaBridge	145:64910690c574	874	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
AnnaBridge	145:64910690c574	875	/**
AnnaBridge	145:64910690c574	876	* @}
AnnaBridge	145:64910690c574	877	*/
AnnaBridge	145:64910690c574	878
AnnaBridge	145:64910690c574	879	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	145:64910690c574	880	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
AnnaBridge	145:64910690c574	881	* @{
AnnaBridge	145:64910690c574	882	*/
AnnaBridge	145:64910690c574	883	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
AnnaBridge	145:64910690c574	884	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
AnnaBridge	145:64910690c574	885	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
AnnaBridge	145:64910690c574	886	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
AnnaBridge	145:64910690c574	887	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
AnnaBridge	145:64910690c574	888	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
AnnaBridge	145:64910690c574	889	/**
AnnaBridge	145:64910690c574	890	* @}
AnnaBridge	145:64910690c574	891	*/
AnnaBridge	145:64910690c574	892	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	145:64910690c574	893
AnnaBridge	145:64910690c574	894	#if defined(RCC_DCKCFGR_PLLDIVR)
AnnaBridge	145:64910690c574	895	/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
AnnaBridge	145:64910690c574	896	* @{
AnnaBridge	145:64910690c574	897	*/
AnnaBridge	145:64910690c574	898	#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 1 /
AnnaBridge	145:64910690c574	899	#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 2 /
AnnaBridge	145:64910690c574	900	#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 3 /
AnnaBridge	145:64910690c574	901	#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 4 /
AnnaBridge	145:64910690c574	902	#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 5 /
AnnaBridge	145:64910690c574	903	#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 6 /
AnnaBridge	145:64910690c574	904	#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 7 /
AnnaBridge	145:64910690c574	905	#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 8 /
AnnaBridge	145:64910690c574	906	#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 9 /
AnnaBridge	145:64910690c574	907	#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 10 /
AnnaBridge	145:64910690c574	908	#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 11 /
AnnaBridge	145:64910690c574	909	#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 12 /
AnnaBridge	145:64910690c574	910	#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 13 /
AnnaBridge	145:64910690c574	911	#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 14 /
AnnaBridge	145:64910690c574	912	#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 15 /
AnnaBridge	145:64910690c574	913	#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /!< PLL division factor for PLLDIVR output by 16 /
AnnaBridge	145:64910690c574	914	#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 17 /
AnnaBridge	145:64910690c574	915	#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 18 /
AnnaBridge	145:64910690c574	916	#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 19 /
AnnaBridge	145:64910690c574	917	#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 20 /
AnnaBridge	145:64910690c574	918	#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 21 /
AnnaBridge	145:64910690c574	919	#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 22 /
AnnaBridge	145:64910690c574	920	#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 23 /
AnnaBridge	145:64910690c574	921	#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 24 /
AnnaBridge	145:64910690c574	922	#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 25 /
AnnaBridge	145:64910690c574	923	#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 26 /
AnnaBridge	145:64910690c574	924	#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 27 /
AnnaBridge	145:64910690c574	925	#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 28 /
AnnaBridge	145:64910690c574	926	#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 29 /
AnnaBridge	145:64910690c574	927	#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 30 /
AnnaBridge	145:64910690c574	928	#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 31 /
AnnaBridge	145:64910690c574	929	/**
AnnaBridge	145:64910690c574	930	* @}
AnnaBridge	145:64910690c574	931	*/
AnnaBridge	145:64910690c574	932	#endif /* RCC_DCKCFGR_PLLDIVR */
AnnaBridge	145:64910690c574	933
AnnaBridge	145:64910690c574	934	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	145:64910690c574	935	* @{
AnnaBridge	145:64910690c574	936	*/
AnnaBridge	145:64910690c574	937	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	145:64910690c574	938	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	145:64910690c574	939	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	145:64910690c574	940	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	145:64910690c574	941	/**
AnnaBridge	145:64910690c574	942	* @}
AnnaBridge	145:64910690c574	943	*/
AnnaBridge	145:64910690c574	944
AnnaBridge	145:64910690c574	945	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	145:64910690c574	946	* @{
AnnaBridge	145:64910690c574	947	*/
AnnaBridge	145:64910690c574	948	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	145:64910690c574	949	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
AnnaBridge	145:64910690c574	950	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	145:64910690c574	951	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
AnnaBridge	145:64910690c574	952	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	145:64910690c574	953	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
AnnaBridge	145:64910690c574	954	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	145:64910690c574	955	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
AnnaBridge	145:64910690c574	956	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
AnnaBridge	145:64910690c574	957	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
AnnaBridge	145:64910690c574	958	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
AnnaBridge	145:64910690c574	959	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
AnnaBridge	145:64910690c574	960	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
AnnaBridge	145:64910690c574	961	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
AnnaBridge	145:64910690c574	962	/**
AnnaBridge	145:64910690c574	963	* @}
AnnaBridge	145:64910690c574	964	*/
AnnaBridge	145:64910690c574	965
AnnaBridge	145:64910690c574	966	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
AnnaBridge	145:64910690c574	967	* @{
AnnaBridge	145:64910690c574	968	*/
AnnaBridge	145:64910690c574	969	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
AnnaBridge	145:64910690c574	970	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
AnnaBridge	145:64910690c574	971	/**
AnnaBridge	145:64910690c574	972	* @}
AnnaBridge	145:64910690c574	973	*/
AnnaBridge	145:64910690c574	974
AnnaBridge	145:64910690c574	975	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	976	/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
AnnaBridge	145:64910690c574	977	* @{
AnnaBridge	145:64910690c574	978	*/
AnnaBridge	145:64910690c574	979	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	980	#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 2 /
AnnaBridge	145:64910690c574	981	#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 3 /
AnnaBridge	145:64910690c574	982	#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 4 /
AnnaBridge	145:64910690c574	983	#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 5 /
AnnaBridge	145:64910690c574	984	#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 6 /
AnnaBridge	145:64910690c574	985	#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 7 /
AnnaBridge	145:64910690c574	986	#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 8 /
AnnaBridge	145:64910690c574	987	#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 9 /
AnnaBridge	145:64910690c574	988	#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 10 /
AnnaBridge	145:64910690c574	989	#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 11 /
AnnaBridge	145:64910690c574	990	#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 12 /
AnnaBridge	145:64910690c574	991	#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 13 /
AnnaBridge	145:64910690c574	992	#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 14 /
AnnaBridge	145:64910690c574	993	#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 15 /
AnnaBridge	145:64910690c574	994	#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 16 /
AnnaBridge	145:64910690c574	995	#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 17 /
AnnaBridge	145:64910690c574	996	#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 18 /
AnnaBridge	145:64910690c574	997	#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 19 /
AnnaBridge	145:64910690c574	998	#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 20 /
AnnaBridge	145:64910690c574	999	#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 21 /
AnnaBridge	145:64910690c574	1000	#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 22 /
AnnaBridge	145:64910690c574	1001	#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 23 /
AnnaBridge	145:64910690c574	1002	#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 24 /
AnnaBridge	145:64910690c574	1003	#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 25 /
AnnaBridge	145:64910690c574	1004	#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 26 /
AnnaBridge	145:64910690c574	1005	#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 27 /
AnnaBridge	145:64910690c574	1006	#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 28 /
AnnaBridge	145:64910690c574	1007	#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 29 /
AnnaBridge	145:64910690c574	1008	#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 30 /
AnnaBridge	145:64910690c574	1009	#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 31 /
AnnaBridge	145:64910690c574	1010	#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /!< PLLI2S division factor for PLLI2SM output by 32 /
AnnaBridge	145:64910690c574	1011	#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 33 /
AnnaBridge	145:64910690c574	1012	#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 34 /
AnnaBridge	145:64910690c574	1013	#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 35 /
AnnaBridge	145:64910690c574	1014	#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 36 /
AnnaBridge	145:64910690c574	1015	#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 37 /
AnnaBridge	145:64910690c574	1016	#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 38 /
AnnaBridge	145:64910690c574	1017	#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 39 /
AnnaBridge	145:64910690c574	1018	#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 40 /
AnnaBridge	145:64910690c574	1019	#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 41 /
AnnaBridge	145:64910690c574	1020	#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 42 /
AnnaBridge	145:64910690c574	1021	#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 43 /
AnnaBridge	145:64910690c574	1022	#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 44 /
AnnaBridge	145:64910690c574	1023	#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 45 /
AnnaBridge	145:64910690c574	1024	#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 46 /
AnnaBridge	145:64910690c574	1025	#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 47 /
AnnaBridge	145:64910690c574	1026	#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 48 /
AnnaBridge	145:64910690c574	1027	#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 49 /
AnnaBridge	145:64910690c574	1028	#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 50 /
AnnaBridge	145:64910690c574	1029	#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 51 /
AnnaBridge	145:64910690c574	1030	#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 52 /
AnnaBridge	145:64910690c574	1031	#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 53 /
AnnaBridge	145:64910690c574	1032	#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 54 /
AnnaBridge	145:64910690c574	1033	#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 55 /
AnnaBridge	145:64910690c574	1034	#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 56 /
AnnaBridge	145:64910690c574	1035	#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 57 /
AnnaBridge	145:64910690c574	1036	#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 58 /
AnnaBridge	145:64910690c574	1037	#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 59 /
AnnaBridge	145:64910690c574	1038	#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 60 /
AnnaBridge	145:64910690c574	1039	#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 61 /
AnnaBridge	145:64910690c574	1040	#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 62 /
AnnaBridge	145:64910690c574	1041	#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 63 /
AnnaBridge	145:64910690c574	1042	#else
AnnaBridge	145:64910690c574	1043	#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLI2S division factor for PLLI2SM output by 2 /
AnnaBridge	145:64910690c574	1044	#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLI2S division factor for PLLI2SM output by 3 /
AnnaBridge	145:64910690c574	1045	#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLI2S division factor for PLLI2SM output by 4 /
AnnaBridge	145:64910690c574	1046	#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLI2S division factor for PLLI2SM output by 5 /
AnnaBridge	145:64910690c574	1047	#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLI2S division factor for PLLI2SM output by 6 /
AnnaBridge	145:64910690c574	1048	#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLI2S division factor for PLLI2SM output by 7 /
AnnaBridge	145:64910690c574	1049	#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLI2S division factor for PLLI2SM output by 8 /
AnnaBridge	145:64910690c574	1050	#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLI2S division factor for PLLI2SM output by 9 /
AnnaBridge	145:64910690c574	1051	#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLI2S division factor for PLLI2SM output by 10 /
AnnaBridge	145:64910690c574	1052	#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLI2S division factor for PLLI2SM output by 11 /
AnnaBridge	145:64910690c574	1053	#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLI2S division factor for PLLI2SM output by 12 /
AnnaBridge	145:64910690c574	1054	#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLI2S division factor for PLLI2SM output by 13 /
AnnaBridge	145:64910690c574	1055	#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLI2S division factor for PLLI2SM output by 14 /
AnnaBridge	145:64910690c574	1056	#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLI2S division factor for PLLI2SM output by 15 /
AnnaBridge	145:64910690c574	1057	#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLI2S division factor for PLLI2SM output by 16 /
AnnaBridge	145:64910690c574	1058	#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLI2S division factor for PLLI2SM output by 17 /
AnnaBridge	145:64910690c574	1059	#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLI2S division factor for PLLI2SM output by 18 /
AnnaBridge	145:64910690c574	1060	#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLI2S division factor for PLLI2SM output by 19 /
AnnaBridge	145:64910690c574	1061	#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLI2S division factor for PLLI2SM output by 20 /
AnnaBridge	145:64910690c574	1062	#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLI2S division factor for PLLI2SM output by 21 /
AnnaBridge	145:64910690c574	1063	#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLI2S division factor for PLLI2SM output by 22 /
AnnaBridge	145:64910690c574	1064	#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLI2S division factor for PLLI2SM output by 23 /
AnnaBridge	145:64910690c574	1065	#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLI2S division factor for PLLI2SM output by 24 /
AnnaBridge	145:64910690c574	1066	#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLI2S division factor for PLLI2SM output by 25 /
AnnaBridge	145:64910690c574	1067	#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLI2S division factor for PLLI2SM output by 26 /
AnnaBridge	145:64910690c574	1068	#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLI2S division factor for PLLI2SM output by 27 /
AnnaBridge	145:64910690c574	1069	#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLI2S division factor for PLLI2SM output by 28 /
AnnaBridge	145:64910690c574	1070	#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLI2S division factor for PLLI2SM output by 29 /
AnnaBridge	145:64910690c574	1071	#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLI2S division factor for PLLI2SM output by 30 /
AnnaBridge	145:64910690c574	1072	#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLI2S division factor for PLLI2SM output by 31 /
AnnaBridge	145:64910690c574	1073	#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLI2S division factor for PLLI2SM output by 32 /
AnnaBridge	145:64910690c574	1074	#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLI2S division factor for PLLI2SM output by 33 /
AnnaBridge	145:64910690c574	1075	#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLI2S division factor for PLLI2SM output by 34 /
AnnaBridge	145:64910690c574	1076	#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLI2S division factor for PLLI2SM output by 35 /
AnnaBridge	145:64910690c574	1077	#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLI2S division factor for PLLI2SM output by 36 /
AnnaBridge	145:64910690c574	1078	#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLI2S division factor for PLLI2SM output by 37 /
AnnaBridge	145:64910690c574	1079	#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLI2S division factor for PLLI2SM output by 38 /
AnnaBridge	145:64910690c574	1080	#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLI2S division factor for PLLI2SM output by 39 /
AnnaBridge	145:64910690c574	1081	#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLI2S division factor for PLLI2SM output by 40 /
AnnaBridge	145:64910690c574	1082	#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLI2S division factor for PLLI2SM output by 41 /
AnnaBridge	145:64910690c574	1083	#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLI2S division factor for PLLI2SM output by 42 /
AnnaBridge	145:64910690c574	1084	#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLI2S division factor for PLLI2SM output by 43 /
AnnaBridge	145:64910690c574	1085	#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLI2S division factor for PLLI2SM output by 44 /
AnnaBridge	145:64910690c574	1086	#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLI2S division factor for PLLI2SM output by 45 /
AnnaBridge	145:64910690c574	1087	#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLI2S division factor for PLLI2SM output by 46 /
AnnaBridge	145:64910690c574	1088	#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLI2S division factor for PLLI2SM output by 47 /
AnnaBridge	145:64910690c574	1089	#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLI2S division factor for PLLI2SM output by 48 /
AnnaBridge	145:64910690c574	1090	#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLI2S division factor for PLLI2SM output by 49 /
AnnaBridge	145:64910690c574	1091	#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLI2S division factor for PLLI2SM output by 50 /
AnnaBridge	145:64910690c574	1092	#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLI2S division factor for PLLI2SM output by 51 /
AnnaBridge	145:64910690c574	1093	#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLI2S division factor for PLLI2SM output by 52 /
AnnaBridge	145:64910690c574	1094	#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLI2S division factor for PLLI2SM output by 53 /
AnnaBridge	145:64910690c574	1095	#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLI2S division factor for PLLI2SM output by 54 /
AnnaBridge	145:64910690c574	1096	#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLI2S division factor for PLLI2SM output by 55 /
AnnaBridge	145:64910690c574	1097	#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLI2S division factor for PLLI2SM output by 56 /
AnnaBridge	145:64910690c574	1098	#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLI2S division factor for PLLI2SM output by 57 /
AnnaBridge	145:64910690c574	1099	#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLI2S division factor for PLLI2SM output by 58 /
AnnaBridge	145:64910690c574	1100	#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLI2S division factor for PLLI2SM output by 59 /
AnnaBridge	145:64910690c574	1101	#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLI2S division factor for PLLI2SM output by 60 /
AnnaBridge	145:64910690c574	1102	#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLI2S division factor for PLLI2SM output by 61 /
AnnaBridge	145:64910690c574	1103	#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLI2S division factor for PLLI2SM output by 62 /
AnnaBridge	145:64910690c574	1104	#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLI2S division factor for PLLI2SM output by 63 /
AnnaBridge	145:64910690c574	1105	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	1106	/**
AnnaBridge	145:64910690c574	1107	* @}
AnnaBridge	145:64910690c574	1108	*/
AnnaBridge	145:64910690c574	1109
AnnaBridge	145:64910690c574	1110	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
AnnaBridge	145:64910690c574	1111	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
AnnaBridge	145:64910690c574	1112	* @{
AnnaBridge	145:64910690c574	1113	*/
AnnaBridge	145:64910690c574	1114	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
AnnaBridge	145:64910690c574	1115	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
AnnaBridge	145:64910690c574	1116	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
AnnaBridge	145:64910690c574	1117	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
AnnaBridge	145:64910690c574	1118	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
AnnaBridge	145:64910690c574	1119	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
AnnaBridge	145:64910690c574	1120	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
AnnaBridge	145:64910690c574	1121	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
AnnaBridge	145:64910690c574	1122	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
AnnaBridge	145:64910690c574	1123	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
AnnaBridge	145:64910690c574	1124	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
AnnaBridge	145:64910690c574	1125	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
AnnaBridge	145:64910690c574	1126	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
AnnaBridge	145:64910690c574	1127	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
AnnaBridge	145:64910690c574	1128	/**
AnnaBridge	145:64910690c574	1129	* @}
AnnaBridge	145:64910690c574	1130	*/
AnnaBridge	145:64910690c574	1131	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
AnnaBridge	145:64910690c574	1132
AnnaBridge	145:64910690c574	1133	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	1134	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
AnnaBridge	145:64910690c574	1135	* @{
AnnaBridge	145:64910690c574	1136	*/
AnnaBridge	145:64910690c574	1137	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
AnnaBridge	145:64910690c574	1138	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
AnnaBridge	145:64910690c574	1139	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
AnnaBridge	145:64910690c574	1140	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
AnnaBridge	145:64910690c574	1141	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
AnnaBridge	145:64910690c574	1142	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
AnnaBridge	145:64910690c574	1143	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
AnnaBridge	145:64910690c574	1144	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
AnnaBridge	145:64910690c574	1145	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
AnnaBridge	145:64910690c574	1146	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
AnnaBridge	145:64910690c574	1147	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
AnnaBridge	145:64910690c574	1148	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
AnnaBridge	145:64910690c574	1149	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
AnnaBridge	145:64910690c574	1150	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
AnnaBridge	145:64910690c574	1151	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
AnnaBridge	145:64910690c574	1152	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
AnnaBridge	145:64910690c574	1153	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
AnnaBridge	145:64910690c574	1154	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
AnnaBridge	145:64910690c574	1155	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
AnnaBridge	145:64910690c574	1156	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
AnnaBridge	145:64910690c574	1157	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
AnnaBridge	145:64910690c574	1158	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
AnnaBridge	145:64910690c574	1159	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
AnnaBridge	145:64910690c574	1160	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
AnnaBridge	145:64910690c574	1161	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
AnnaBridge	145:64910690c574	1162	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
AnnaBridge	145:64910690c574	1163	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
AnnaBridge	145:64910690c574	1164	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
AnnaBridge	145:64910690c574	1165	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
AnnaBridge	145:64910690c574	1166	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
AnnaBridge	145:64910690c574	1167	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
AnnaBridge	145:64910690c574	1168	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
AnnaBridge	145:64910690c574	1169	/**
AnnaBridge	145:64910690c574	1170	* @}
AnnaBridge	145:64910690c574	1171	*/
AnnaBridge	145:64910690c574	1172	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	1173
AnnaBridge	145:64910690c574	1174	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
AnnaBridge	145:64910690c574	1175	/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
AnnaBridge	145:64910690c574	1176	* @{
AnnaBridge	145:64910690c574	1177	*/
AnnaBridge	145:64910690c574	1178	#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 1 /
AnnaBridge	145:64910690c574	1179	#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 2 /
AnnaBridge	145:64910690c574	1180	#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 3 /
AnnaBridge	145:64910690c574	1181	#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 4 /
AnnaBridge	145:64910690c574	1182	#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 5 /
AnnaBridge	145:64910690c574	1183	#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 6 /
AnnaBridge	145:64910690c574	1184	#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 7 /
AnnaBridge	145:64910690c574	1185	#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 8 /
AnnaBridge	145:64910690c574	1186	#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 9 /
AnnaBridge	145:64910690c574	1187	#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 10 /
AnnaBridge	145:64910690c574	1188	#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 11 /
AnnaBridge	145:64910690c574	1189	#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 12 /
AnnaBridge	145:64910690c574	1190	#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 13 /
AnnaBridge	145:64910690c574	1191	#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 14 /
AnnaBridge	145:64910690c574	1192	#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 15 /
AnnaBridge	145:64910690c574	1193	#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /!< PLLI2S division factor for PLLI2SDIVR output by 16 /
AnnaBridge	145:64910690c574	1194	#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 17 /
AnnaBridge	145:64910690c574	1195	#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 18 /
AnnaBridge	145:64910690c574	1196	#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 19 /
AnnaBridge	145:64910690c574	1197	#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 20 /
AnnaBridge	145:64910690c574	1198	#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 21 /
AnnaBridge	145:64910690c574	1199	#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 22 /
AnnaBridge	145:64910690c574	1200	#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 23 /
AnnaBridge	145:64910690c574	1201	#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 24 /
AnnaBridge	145:64910690c574	1202	#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 25 /
AnnaBridge	145:64910690c574	1203	#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 26 /
AnnaBridge	145:64910690c574	1204	#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 27 /
AnnaBridge	145:64910690c574	1205	#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 28 /
AnnaBridge	145:64910690c574	1206	#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 29 /
AnnaBridge	145:64910690c574	1207	#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 30 /
AnnaBridge	145:64910690c574	1208	#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 31 /
AnnaBridge	145:64910690c574	1209	/**
AnnaBridge	145:64910690c574	1210	* @}
AnnaBridge	145:64910690c574	1211	*/
AnnaBridge	145:64910690c574	1212	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
AnnaBridge	145:64910690c574	1213
AnnaBridge	145:64910690c574	1214	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
AnnaBridge	145:64910690c574	1215	* @{
AnnaBridge	145:64910690c574	1216	*/
AnnaBridge	145:64910690c574	1217	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
AnnaBridge	145:64910690c574	1218	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
AnnaBridge	145:64910690c574	1219	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
AnnaBridge	145:64910690c574	1220	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
AnnaBridge	145:64910690c574	1221	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
AnnaBridge	145:64910690c574	1222	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
AnnaBridge	145:64910690c574	1223	/**
AnnaBridge	145:64910690c574	1224	* @}
AnnaBridge	145:64910690c574	1225	*/
AnnaBridge	145:64910690c574	1226
AnnaBridge	145:64910690c574	1227	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
AnnaBridge	145:64910690c574	1228	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
AnnaBridge	145:64910690c574	1229	* @{
AnnaBridge	145:64910690c574	1230	*/
AnnaBridge	145:64910690c574	1231	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
AnnaBridge	145:64910690c574	1232	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
AnnaBridge	145:64910690c574	1233	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
AnnaBridge	145:64910690c574	1234	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
AnnaBridge	145:64910690c574	1235	/**
AnnaBridge	145:64910690c574	1236	* @}
AnnaBridge	145:64910690c574	1237	*/
AnnaBridge	145:64910690c574	1238	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
AnnaBridge	145:64910690c574	1239	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	1240
AnnaBridge	145:64910690c574	1241	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	1242	/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
AnnaBridge	145:64910690c574	1243	* @{
AnnaBridge	145:64910690c574	1244	*/
AnnaBridge	145:64910690c574	1245	#if defined(RCC_PLLSAICFGR_PLLSAIM)
AnnaBridge	145:64910690c574	1246	#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 2 /
AnnaBridge	145:64910690c574	1247	#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 3 /
AnnaBridge	145:64910690c574	1248	#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 4 /
AnnaBridge	145:64910690c574	1249	#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 5 /
AnnaBridge	145:64910690c574	1250	#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 6 /
AnnaBridge	145:64910690c574	1251	#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 7 /
AnnaBridge	145:64910690c574	1252	#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 8 /
AnnaBridge	145:64910690c574	1253	#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 9 /
AnnaBridge	145:64910690c574	1254	#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 10 /
AnnaBridge	145:64910690c574	1255	#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 11 /
AnnaBridge	145:64910690c574	1256	#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 12 /
AnnaBridge	145:64910690c574	1257	#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 13 /
AnnaBridge	145:64910690c574	1258	#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 14 /
AnnaBridge	145:64910690c574	1259	#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 15 /
AnnaBridge	145:64910690c574	1260	#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 16 /
AnnaBridge	145:64910690c574	1261	#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 17 /
AnnaBridge	145:64910690c574	1262	#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 18 /
AnnaBridge	145:64910690c574	1263	#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 19 /
AnnaBridge	145:64910690c574	1264	#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 20 /
AnnaBridge	145:64910690c574	1265	#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 21 /
AnnaBridge	145:64910690c574	1266	#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 22 /
AnnaBridge	145:64910690c574	1267	#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 23 /
AnnaBridge	145:64910690c574	1268	#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 24 /
AnnaBridge	145:64910690c574	1269	#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 25 /
AnnaBridge	145:64910690c574	1270	#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 26 /
AnnaBridge	145:64910690c574	1271	#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 27 /
AnnaBridge	145:64910690c574	1272	#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 28 /
AnnaBridge	145:64910690c574	1273	#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 29 /
AnnaBridge	145:64910690c574	1274	#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 30 /
AnnaBridge	145:64910690c574	1275	#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 31 /
AnnaBridge	145:64910690c574	1276	#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /!< PLLSAI division factor for PLLSAIM output by 32 /
AnnaBridge	145:64910690c574	1277	#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 33 /
AnnaBridge	145:64910690c574	1278	#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 34 /
AnnaBridge	145:64910690c574	1279	#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 35 /
AnnaBridge	145:64910690c574	1280	#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 36 /
AnnaBridge	145:64910690c574	1281	#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 37 /
AnnaBridge	145:64910690c574	1282	#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 38 /
AnnaBridge	145:64910690c574	1283	#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 39 /
AnnaBridge	145:64910690c574	1284	#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 40 /
AnnaBridge	145:64910690c574	1285	#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 41 /
AnnaBridge	145:64910690c574	1286	#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 42 /
AnnaBridge	145:64910690c574	1287	#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 43 /
AnnaBridge	145:64910690c574	1288	#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 44 /
AnnaBridge	145:64910690c574	1289	#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 45 /
AnnaBridge	145:64910690c574	1290	#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 46 /
AnnaBridge	145:64910690c574	1291	#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 47 /
AnnaBridge	145:64910690c574	1292	#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 48 /
AnnaBridge	145:64910690c574	1293	#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 49 /
AnnaBridge	145:64910690c574	1294	#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 50 /
AnnaBridge	145:64910690c574	1295	#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 51 /
AnnaBridge	145:64910690c574	1296	#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 52 /
AnnaBridge	145:64910690c574	1297	#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 53 /
AnnaBridge	145:64910690c574	1298	#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 54 /
AnnaBridge	145:64910690c574	1299	#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 55 /
AnnaBridge	145:64910690c574	1300	#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 56 /
AnnaBridge	145:64910690c574	1301	#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 57 /
AnnaBridge	145:64910690c574	1302	#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 58 /
AnnaBridge	145:64910690c574	1303	#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 59 /
AnnaBridge	145:64910690c574	1304	#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 60 /
AnnaBridge	145:64910690c574	1305	#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 61 /
AnnaBridge	145:64910690c574	1306	#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 62 /
AnnaBridge	145:64910690c574	1307	#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 63 /
AnnaBridge	145:64910690c574	1308	#else
AnnaBridge	145:64910690c574	1309	#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLSAI division factor for PLLSAIM output by 2 /
AnnaBridge	145:64910690c574	1310	#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLSAI division factor for PLLSAIM output by 3 /
AnnaBridge	145:64910690c574	1311	#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLSAI division factor for PLLSAIM output by 4 /
AnnaBridge	145:64910690c574	1312	#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLSAI division factor for PLLSAIM output by 5 /
AnnaBridge	145:64910690c574	1313	#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLSAI division factor for PLLSAIM output by 6 /
AnnaBridge	145:64910690c574	1314	#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLSAI division factor for PLLSAIM output by 7 /
AnnaBridge	145:64910690c574	1315	#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLSAI division factor for PLLSAIM output by 8 /
AnnaBridge	145:64910690c574	1316	#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLSAI division factor for PLLSAIM output by 9 /
AnnaBridge	145:64910690c574	1317	#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLSAI division factor for PLLSAIM output by 10 /
AnnaBridge	145:64910690c574	1318	#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLSAI division factor for PLLSAIM output by 11 /
AnnaBridge	145:64910690c574	1319	#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLSAI division factor for PLLSAIM output by 12 /
AnnaBridge	145:64910690c574	1320	#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLSAI division factor for PLLSAIM output by 13 /
AnnaBridge	145:64910690c574	1321	#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLSAI division factor for PLLSAIM output by 14 /
AnnaBridge	145:64910690c574	1322	#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLSAI division factor for PLLSAIM output by 15 /
AnnaBridge	145:64910690c574	1323	#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLSAI division factor for PLLSAIM output by 16 /
AnnaBridge	145:64910690c574	1324	#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLSAI division factor for PLLSAIM output by 17 /
AnnaBridge	145:64910690c574	1325	#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLSAI division factor for PLLSAIM output by 18 /
AnnaBridge	145:64910690c574	1326	#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLSAI division factor for PLLSAIM output by 19 /
AnnaBridge	145:64910690c574	1327	#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLSAI division factor for PLLSAIM output by 20 /
AnnaBridge	145:64910690c574	1328	#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLSAI division factor for PLLSAIM output by 21 /
AnnaBridge	145:64910690c574	1329	#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLSAI division factor for PLLSAIM output by 22 /
AnnaBridge	145:64910690c574	1330	#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLSAI division factor for PLLSAIM output by 23 /
AnnaBridge	145:64910690c574	1331	#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLSAI division factor for PLLSAIM output by 24 /
AnnaBridge	145:64910690c574	1332	#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLSAI division factor for PLLSAIM output by 25 /
AnnaBridge	145:64910690c574	1333	#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLSAI division factor for PLLSAIM output by 26 /
AnnaBridge	145:64910690c574	1334	#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLSAI division factor for PLLSAIM output by 27 /
AnnaBridge	145:64910690c574	1335	#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLSAI division factor for PLLSAIM output by 28 /
AnnaBridge	145:64910690c574	1336	#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLSAI division factor for PLLSAIM output by 29 /
AnnaBridge	145:64910690c574	1337	#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLSAI division factor for PLLSAIM output by 30 /
AnnaBridge	145:64910690c574	1338	#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLSAI division factor for PLLSAIM output by 31 /
AnnaBridge	145:64910690c574	1339	#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLSAI division factor for PLLSAIM output by 32 /
AnnaBridge	145:64910690c574	1340	#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLSAI division factor for PLLSAIM output by 33 /
AnnaBridge	145:64910690c574	1341	#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLSAI division factor for PLLSAIM output by 34 /
AnnaBridge	145:64910690c574	1342	#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLSAI division factor for PLLSAIM output by 35 /
AnnaBridge	145:64910690c574	1343	#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLSAI division factor for PLLSAIM output by 36 /
AnnaBridge	145:64910690c574	1344	#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLSAI division factor for PLLSAIM output by 37 /
AnnaBridge	145:64910690c574	1345	#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLSAI division factor for PLLSAIM output by 38 /
AnnaBridge	145:64910690c574	1346	#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLSAI division factor for PLLSAIM output by 39 /
AnnaBridge	145:64910690c574	1347	#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLSAI division factor for PLLSAIM output by 40 /
AnnaBridge	145:64910690c574	1348	#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLSAI division factor for PLLSAIM output by 41 /
AnnaBridge	145:64910690c574	1349	#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLSAI division factor for PLLSAIM output by 42 /
AnnaBridge	145:64910690c574	1350	#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLSAI division factor for PLLSAIM output by 43 /
AnnaBridge	145:64910690c574	1351	#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLSAI division factor for PLLSAIM output by 44 /
AnnaBridge	145:64910690c574	1352	#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLSAI division factor for PLLSAIM output by 45 /
AnnaBridge	145:64910690c574	1353	#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLSAI division factor for PLLSAIM output by 46 /
AnnaBridge	145:64910690c574	1354	#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLSAI division factor for PLLSAIM output by 47 /
AnnaBridge	145:64910690c574	1355	#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLSAI division factor for PLLSAIM output by 48 /
AnnaBridge	145:64910690c574	1356	#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLSAI division factor for PLLSAIM output by 49 /
AnnaBridge	145:64910690c574	1357	#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLSAI division factor for PLLSAIM output by 50 /
AnnaBridge	145:64910690c574	1358	#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLSAI division factor for PLLSAIM output by 51 /
AnnaBridge	145:64910690c574	1359	#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLSAI division factor for PLLSAIM output by 52 /
AnnaBridge	145:64910690c574	1360	#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLSAI division factor for PLLSAIM output by 53 /
AnnaBridge	145:64910690c574	1361	#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLSAI division factor for PLLSAIM output by 54 /
AnnaBridge	145:64910690c574	1362	#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLSAI division factor for PLLSAIM output by 55 /
AnnaBridge	145:64910690c574	1363	#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLSAI division factor for PLLSAIM output by 56 /
AnnaBridge	145:64910690c574	1364	#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLSAI division factor for PLLSAIM output by 57 /
AnnaBridge	145:64910690c574	1365	#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLSAI division factor for PLLSAIM output by 58 /
AnnaBridge	145:64910690c574	1366	#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLSAI division factor for PLLSAIM output by 59 /
AnnaBridge	145:64910690c574	1367	#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLSAI division factor for PLLSAIM output by 60 /
AnnaBridge	145:64910690c574	1368	#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLSAI division factor for PLLSAIM output by 61 /
AnnaBridge	145:64910690c574	1369	#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLSAI division factor for PLLSAIM output by 62 /
AnnaBridge	145:64910690c574	1370	#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLSAI division factor for PLLSAIM output by 63 /
AnnaBridge	145:64910690c574	1371	#endif /* RCC_PLLSAICFGR_PLLSAIM */
AnnaBridge	145:64910690c574	1372	/**
AnnaBridge	145:64910690c574	1373	* @}
AnnaBridge	145:64910690c574	1374	*/
AnnaBridge	145:64910690c574	1375
AnnaBridge	145:64910690c574	1376	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
AnnaBridge	145:64910690c574	1377	* @{
AnnaBridge	145:64910690c574	1378	*/
AnnaBridge	145:64910690c574	1379	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
AnnaBridge	145:64910690c574	1380	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
AnnaBridge	145:64910690c574	1381	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
AnnaBridge	145:64910690c574	1382	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
AnnaBridge	145:64910690c574	1383	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
AnnaBridge	145:64910690c574	1384	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
AnnaBridge	145:64910690c574	1385	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
AnnaBridge	145:64910690c574	1386	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
AnnaBridge	145:64910690c574	1387	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
AnnaBridge	145:64910690c574	1388	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
AnnaBridge	145:64910690c574	1389	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
AnnaBridge	145:64910690c574	1390	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
AnnaBridge	145:64910690c574	1391	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
AnnaBridge	145:64910690c574	1392	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
AnnaBridge	145:64910690c574	1393	/**
AnnaBridge	145:64910690c574	1394	* @}
AnnaBridge	145:64910690c574	1395	*/
AnnaBridge	145:64910690c574	1396
AnnaBridge	145:64910690c574	1397	#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
AnnaBridge	145:64910690c574	1398	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
AnnaBridge	145:64910690c574	1399	* @{
AnnaBridge	145:64910690c574	1400	*/
AnnaBridge	145:64910690c574	1401	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
AnnaBridge	145:64910690c574	1402	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
AnnaBridge	145:64910690c574	1403	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
AnnaBridge	145:64910690c574	1404	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
AnnaBridge	145:64910690c574	1405	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
AnnaBridge	145:64910690c574	1406	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
AnnaBridge	145:64910690c574	1407	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
AnnaBridge	145:64910690c574	1408	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
AnnaBridge	145:64910690c574	1409	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
AnnaBridge	145:64910690c574	1410	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
AnnaBridge	145:64910690c574	1411	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
AnnaBridge	145:64910690c574	1412	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
AnnaBridge	145:64910690c574	1413	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
AnnaBridge	145:64910690c574	1414	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
AnnaBridge	145:64910690c574	1415	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
AnnaBridge	145:64910690c574	1416	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
AnnaBridge	145:64910690c574	1417	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
AnnaBridge	145:64910690c574	1418	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
AnnaBridge	145:64910690c574	1419	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
AnnaBridge	145:64910690c574	1420	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
AnnaBridge	145:64910690c574	1421	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
AnnaBridge	145:64910690c574	1422	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
AnnaBridge	145:64910690c574	1423	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
AnnaBridge	145:64910690c574	1424	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
AnnaBridge	145:64910690c574	1425	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
AnnaBridge	145:64910690c574	1426	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
AnnaBridge	145:64910690c574	1427	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
AnnaBridge	145:64910690c574	1428	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
AnnaBridge	145:64910690c574	1429	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
AnnaBridge	145:64910690c574	1430	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
AnnaBridge	145:64910690c574	1431	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
AnnaBridge	145:64910690c574	1432	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
AnnaBridge	145:64910690c574	1433	/**
AnnaBridge	145:64910690c574	1434	* @}
AnnaBridge	145:64910690c574	1435	*/
AnnaBridge	145:64910690c574	1436	#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
AnnaBridge	145:64910690c574	1437
AnnaBridge	145:64910690c574	1438	#if defined(RCC_PLLSAICFGR_PLLSAIR)
AnnaBridge	145:64910690c574	1439	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
AnnaBridge	145:64910690c574	1440	* @{
AnnaBridge	145:64910690c574	1441	*/
AnnaBridge	145:64910690c574	1442	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
AnnaBridge	145:64910690c574	1443	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
AnnaBridge	145:64910690c574	1444	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
AnnaBridge	145:64910690c574	1445	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
AnnaBridge	145:64910690c574	1446	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
AnnaBridge	145:64910690c574	1447	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
AnnaBridge	145:64910690c574	1448	/**
AnnaBridge	145:64910690c574	1449	* @}
AnnaBridge	145:64910690c574	1450	*/
AnnaBridge	145:64910690c574	1451	#endif /* RCC_PLLSAICFGR_PLLSAIR */
AnnaBridge	145:64910690c574	1452
AnnaBridge	145:64910690c574	1453	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
AnnaBridge	145:64910690c574	1454	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
AnnaBridge	145:64910690c574	1455	* @{
AnnaBridge	145:64910690c574	1456	*/
AnnaBridge	145:64910690c574	1457	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
AnnaBridge	145:64910690c574	1458	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
AnnaBridge	145:64910690c574	1459	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
AnnaBridge	145:64910690c574	1460	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 \| RCC_DCKCFGR_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
AnnaBridge	145:64910690c574	1461	/**
AnnaBridge	145:64910690c574	1462	* @}
AnnaBridge	145:64910690c574	1463	*/
AnnaBridge	145:64910690c574	1464	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
AnnaBridge	145:64910690c574	1465
AnnaBridge	145:64910690c574	1466	#if defined(RCC_PLLSAICFGR_PLLSAIP)
AnnaBridge	145:64910690c574	1467	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
AnnaBridge	145:64910690c574	1468	* @{
AnnaBridge	145:64910690c574	1469	*/
AnnaBridge	145:64910690c574	1470	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
AnnaBridge	145:64910690c574	1471	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
AnnaBridge	145:64910690c574	1472	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
AnnaBridge	145:64910690c574	1473	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
AnnaBridge	145:64910690c574	1474	/**
AnnaBridge	145:64910690c574	1475	* @}
AnnaBridge	145:64910690c574	1476	*/
AnnaBridge	145:64910690c574	1477	#endif /* RCC_PLLSAICFGR_PLLSAIP */
AnnaBridge	145:64910690c574	1478	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	1479	/**
AnnaBridge	145:64910690c574	1480	* @}
AnnaBridge	145:64910690c574	1481	*/
AnnaBridge	145:64910690c574	1482
AnnaBridge	145:64910690c574	1483	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1484	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	145:64910690c574	1485	* @{
AnnaBridge	145:64910690c574	1486	*/
AnnaBridge	145:64910690c574	1487
AnnaBridge	145:64910690c574	1488	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	1489	* @{
AnnaBridge	145:64910690c574	1490	*/
AnnaBridge	145:64910690c574	1491
AnnaBridge	145:64910690c574	1492	/**
AnnaBridge	145:64910690c574	1493	* @brief Write a value in RCC register
AnnaBridge	145:64910690c574	1494	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	1495	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	1496	* @retval None
AnnaBridge	145:64910690c574	1497	*/
AnnaBridge	145:64910690c574	1498	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	1499
AnnaBridge	145:64910690c574	1500	/**
AnnaBridge	145:64910690c574	1501	* @brief Read a value in RCC register
AnnaBridge	145:64910690c574	1502	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	1503	* @retval Register value
AnnaBridge	145:64910690c574	1504	*/
AnnaBridge	145:64910690c574	1505	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	145:64910690c574	1506	/**
AnnaBridge	145:64910690c574	1507	* @}
AnnaBridge	145:64910690c574	1508	*/
AnnaBridge	145:64910690c574	1509
AnnaBridge	145:64910690c574	1510	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	145:64910690c574	1511	* @{
AnnaBridge	145:64910690c574	1512	*/
AnnaBridge	145:64910690c574	1513
AnnaBridge	145:64910690c574	1514	/**
AnnaBridge	145:64910690c574	1515	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	145:64910690c574	1516	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1517	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	145:64910690c574	1518	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1519	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1520	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1521	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1522	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1523	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1524	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1525	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1526	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1527	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1528	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1529	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1530	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1531	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1532	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1533	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1534	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1535	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1536	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1537	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1538	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1539	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1540	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1541	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1542	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1543	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1544	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1546	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1547	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1548	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1549	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1550	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1551	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1552	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1553	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1554	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1555	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1556	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1557	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1558	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1559	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1560	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1561	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1562	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1563	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1564	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1565	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1566	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1569	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1570	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1571	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1572	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1573	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1574	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1575	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1576	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1577	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1578	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1579	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1580	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1581	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1582	* @param __PLLN__ Between 50/192(*) and 432
AnnaBridge	145:64910690c574	1583	*
AnnaBridge	145:64910690c574	1584	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1585	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1586	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	1587	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	1588	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	1589	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	1590	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	1591	*/
AnnaBridge	145:64910690c574	1592	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1593	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
AnnaBridge	145:64910690c574	1594
AnnaBridge	145:64910690c574	1595	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
AnnaBridge	145:64910690c574	1596	/**
AnnaBridge	145:64910690c574	1597	* @brief Helper macro to calculate the PLLRCLK frequency on system domain
AnnaBridge	145:64910690c574	1598	* @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1599	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	145:64910690c574	1600	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1601	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1602	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1603	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1604	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1605	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1606	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1607	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1608	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1609	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1610	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1611	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1612	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1613	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1614	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1615	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1616	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1617	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1618	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1619	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1620	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1621	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1622	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1623	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1624	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1625	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1626	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1627	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1628	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1629	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1630	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1631	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1632	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1633	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1634	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1635	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1636	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1637	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1638	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1639	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1640	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1641	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1642	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1643	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1644	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1645	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1646	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1647	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1648	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1649	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1650	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1651	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1652	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1653	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1654	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1655	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1656	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1657	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1658	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1659	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1660	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1661	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1662	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1663	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1664	* @param __PLLN__ Between 50 and 432
AnnaBridge	145:64910690c574	1665	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1666	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	1667	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	1668	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	1669	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	1670	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	1671	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	1672	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	1673	*/
AnnaBridge	145:64910690c574	1674	#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1675	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	145:64910690c574	1676
AnnaBridge	145:64910690c574	1677	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
AnnaBridge	145:64910690c574	1678
AnnaBridge	145:64910690c574	1679	/**
AnnaBridge	145:64910690c574	1680	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	145:64910690c574	1681	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1682	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	145:64910690c574	1683	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1684	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1685	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1686	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1687	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1688	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1689	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1690	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1691	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1692	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1693	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1694	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1695	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1696	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1697	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1698	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1699	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1700	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1701	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1702	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1703	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1704	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1705	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1706	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1707	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1708	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1709	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1710	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1711	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1712	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1713	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1714	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1715	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1716	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1717	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1718	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1719	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1720	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1721	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1722	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1723	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1724	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1725	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1726	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1727	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1728	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1729	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1730	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1731	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1732	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1733	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1734	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1735	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1736	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1737	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1738	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1739	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1740	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1741	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1742	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1743	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1744	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1745	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1746	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1747	* @param __PLLN__ Between 50/192(*) and 432
AnnaBridge	145:64910690c574	1748	*
AnnaBridge	145:64910690c574	1749	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1750	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1751	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	1752	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	1753	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	1754	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	1755	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	1756	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	1757	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	1758	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	1759	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	1760	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	1761	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	1762	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	1763	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	1764	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	1765	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	1766	*/
AnnaBridge	145:64910690c574	1767	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1768	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
AnnaBridge	145:64910690c574	1769
AnnaBridge	145:64910690c574	1770	#if defined(DSI)
AnnaBridge	145:64910690c574	1771	/**
AnnaBridge	145:64910690c574	1772	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
AnnaBridge	145:64910690c574	1773	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1774	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	145:64910690c574	1775	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1776	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1777	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1778	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1779	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1780	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1781	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1782	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1783	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1784	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1785	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1786	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1787	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1788	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1789	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1790	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1791	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1792	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1793	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1794	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1795	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1796	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1797	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1798	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1799	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1800	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1801	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1802	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1803	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1804	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1805	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1806	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1807	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1808	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1809	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1810	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1811	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1812	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1813	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1814	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1815	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1816	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1817	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1818	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1819	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1820	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1821	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1822	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1823	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1824	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1825	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1826	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1827	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1828	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1829	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1830	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1831	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1832	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1833	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1834	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1835	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1836	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1837	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1838	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1839	* @param __PLLN__ Between 50 and 432
AnnaBridge	145:64910690c574	1840	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1841	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	1842	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	1843	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	1844	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	1845	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	1846	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	1847	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	1848	*/
AnnaBridge	145:64910690c574	1849	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1850	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	145:64910690c574	1851	#endif /* DSI */
AnnaBridge	145:64910690c574	1852
AnnaBridge	145:64910690c574	1853	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
AnnaBridge	145:64910690c574	1854	/**
AnnaBridge	145:64910690c574	1855	* @brief Helper macro to calculate the PLLCLK frequency used on I2S
AnnaBridge	145:64910690c574	1856	* @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1857	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	145:64910690c574	1858	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1859	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1860	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1861	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1862	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1863	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1864	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1865	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1866	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1867	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1868	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1869	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1870	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1871	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1872	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1873	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1874	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1875	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1876	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1877	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1878	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1879	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1880	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1881	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1882	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1883	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1884	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1885	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1886	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1887	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1888	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1889	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1890	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1891	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1892	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1893	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1894	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1895	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1896	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1897	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1898	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1899	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1900	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1901	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1902	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1903	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1904	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1905	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1906	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1907	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1908	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1909	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1910	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1911	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1912	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1913	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1914	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1915	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1916	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1917	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1918	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1919	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1920	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1921	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1922	* @param __PLLN__ Between 50 and 432
AnnaBridge	145:64910690c574	1923	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1924	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	1925	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	1926	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	1927	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	1928	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	1929	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	1930	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	1931	*/
AnnaBridge	145:64910690c574	1932	#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1933	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	145:64910690c574	1934	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
AnnaBridge	145:64910690c574	1935
AnnaBridge	145:64910690c574	1936	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	1937	/**
AnnaBridge	145:64910690c574	1938	* @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
AnnaBridge	145:64910690c574	1939	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	1940	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	145:64910690c574	1941	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	1942	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1943	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1944	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1945	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1946	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1947	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1948	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1949	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1950	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1951	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1952	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1953	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1954	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1955	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1956	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1957	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1958	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1959	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1960	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1961	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1962	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1963	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1964	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1965	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1966	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1967	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1968	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1969	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1970	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1971	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1972	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1973	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1974	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1975	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1976	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1977	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1978	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1979	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1980	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1981	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1982	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1983	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1984	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1985	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1986	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1987	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1988	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1989	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1990	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1991	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1992	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1993	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1994	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1995	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1996	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1997	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1998	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1999	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	2000	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	2001	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	2002	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	2003	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	2004	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	2005	* @param __PLLN__ Between 50 and 432
AnnaBridge	145:64910690c574	2006	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2007	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	2008	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	2009	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	2010	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	2011	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	2012	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	2013	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	2014	*/
AnnaBridge	145:64910690c574	2015	#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	2016	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	145:64910690c574	2017	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	2018
AnnaBridge	145:64910690c574	2019	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	145:64910690c574	2020	#if defined(SAI1)
AnnaBridge	145:64910690c574	2021	/**
AnnaBridge	145:64910690c574	2022	* @brief Helper macro to calculate the PLLCLK frequency used on SAI
AnnaBridge	145:64910690c574	2023	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	2024	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
AnnaBridge	145:64910690c574	2025	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2026	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2027	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	2028	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	2029	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	2030	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	2031	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	2032	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	2033	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	2034	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	2035	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	2036	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	2037	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	2038	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	2039	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	2040	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	2041	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	2042	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	2043	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	2044	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	2045	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	2046	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	2047	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	2048	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	2049	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	2050	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	2051	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	2052	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	2053	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	2054	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	2055	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	2056	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	2057	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	2058	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	2059	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	2060	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	2061	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	2062	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	2063	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	2064	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	2065	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	2066	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	2067	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	2068	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	2069	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	2070	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	2071	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	2072	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	2073	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	2074	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	2075	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	2076	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	2077	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	2078	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	2079	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	2080	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	2081	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	2082	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	2083	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	2084	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	2085	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	2086	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	2087	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	2088	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	2089	* @param __PLLN__ Between 50 and 432
AnnaBridge	145:64910690c574	2090	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2091	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	2092	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	2093	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	2094	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	2095	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	2096	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	2097	* @param __PLLDIVR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2098	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
AnnaBridge	145:64910690c574	2099	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
AnnaBridge	145:64910690c574	2100	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
AnnaBridge	145:64910690c574	2101	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
AnnaBridge	145:64910690c574	2102	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
AnnaBridge	145:64910690c574	2103	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
AnnaBridge	145:64910690c574	2104	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
AnnaBridge	145:64910690c574	2105	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
AnnaBridge	145:64910690c574	2106	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
AnnaBridge	145:64910690c574	2107	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
AnnaBridge	145:64910690c574	2108	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
AnnaBridge	145:64910690c574	2109	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
AnnaBridge	145:64910690c574	2110	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
AnnaBridge	145:64910690c574	2111	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
AnnaBridge	145:64910690c574	2112	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
AnnaBridge	145:64910690c574	2113	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
AnnaBridge	145:64910690c574	2114	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
AnnaBridge	145:64910690c574	2115	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
AnnaBridge	145:64910690c574	2116	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
AnnaBridge	145:64910690c574	2117	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
AnnaBridge	145:64910690c574	2118	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
AnnaBridge	145:64910690c574	2119	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
AnnaBridge	145:64910690c574	2120	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
AnnaBridge	145:64910690c574	2121	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
AnnaBridge	145:64910690c574	2122	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
AnnaBridge	145:64910690c574	2123	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
AnnaBridge	145:64910690c574	2124	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
AnnaBridge	145:64910690c574	2125	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
AnnaBridge	145:64910690c574	2126	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
AnnaBridge	145:64910690c574	2127	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
AnnaBridge	145:64910690c574	2128	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
AnnaBridge	145:64910690c574	2129	*
AnnaBridge	145:64910690c574	2130	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2131	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	2132	*/
AnnaBridge	145:64910690c574	2133	#if defined(RCC_DCKCFGR_PLLDIVR)
AnnaBridge	145:64910690c574	2134	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	2135	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
AnnaBridge	145:64910690c574	2136	#else
AnnaBridge	145:64910690c574	2137	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	2138	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	145:64910690c574	2139	#endif /* RCC_DCKCFGR_PLLDIVR */
AnnaBridge	145:64910690c574	2140	#endif /* SAI1 */
AnnaBridge	145:64910690c574	2141	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	145:64910690c574	2142
AnnaBridge	145:64910690c574	2143	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	2144	/**
AnnaBridge	145:64910690c574	2145	* @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
AnnaBridge	145:64910690c574	2146	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
AnnaBridge	145:64910690c574	2147	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
AnnaBridge	145:64910690c574	2148	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2149	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2150	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	2151	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	2152	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	2153	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	2154	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	2155	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	2156	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	2157	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	2158	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	2159	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	2160	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	2161	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	2162	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	2163	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	2164	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	2165	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	2166	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	2167	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	2168	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	2169	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	2170	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	2171	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	2172	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	2173	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	2174	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	2175	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	2176	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	2177	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	2178	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	2179	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	2180	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	2181	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	2182	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	2183	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	2184	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	2185	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	2186	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	2187	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	2188	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	2189	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	2190	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	2191	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	2192	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	2193	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	2194	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	2195	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	2196	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	2197	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	2198	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	2199	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	2200	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	2201	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	2202	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	2203	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	2204	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	2205	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	2206	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	2207	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	2208	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	2209	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	2210	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	2211	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	2212	* @param __PLLSAIN__ Between 49/50(*) and 432
AnnaBridge	145:64910690c574	2213	*
AnnaBridge	145:64910690c574	2214	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2215	* @param __PLLSAIQ__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2216	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	145:64910690c574	2217	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	145:64910690c574	2218	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	145:64910690c574	2219	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	145:64910690c574	2220	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	145:64910690c574	2221	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	145:64910690c574	2222	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	145:64910690c574	2223	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	145:64910690c574	2224	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	145:64910690c574	2225	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	145:64910690c574	2226	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	145:64910690c574	2227	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	145:64910690c574	2228	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	145:64910690c574	2229	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	145:64910690c574	2230	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2231	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	145:64910690c574	2232	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	145:64910690c574	2233	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	145:64910690c574	2234	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	145:64910690c574	2235	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	145:64910690c574	2236	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	145:64910690c574	2237	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	145:64910690c574	2238	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	145:64910690c574	2239	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	145:64910690c574	2240	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	145:64910690c574	2241	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	145:64910690c574	2242	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	145:64910690c574	2243	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	145:64910690c574	2244	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	145:64910690c574	2245	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	145:64910690c574	2246	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	145:64910690c574	2247	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	145:64910690c574	2248	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	145:64910690c574	2249	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	145:64910690c574	2250	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	145:64910690c574	2251	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	145:64910690c574	2252	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	145:64910690c574	2253	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	145:64910690c574	2254	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	145:64910690c574	2255	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	145:64910690c574	2256	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	145:64910690c574	2257	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	145:64910690c574	2258	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	145:64910690c574	2259	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	145:64910690c574	2260	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	145:64910690c574	2261	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	145:64910690c574	2262	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	145:64910690c574	2263	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	145:64910690c574	2264	*/
AnnaBridge	145:64910690c574	2265	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	145:64910690c574	2266	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
AnnaBridge	145:64910690c574	2267
AnnaBridge	145:64910690c574	2268	#if defined(RCC_PLLSAICFGR_PLLSAIP)
AnnaBridge	145:64910690c574	2269	/**
AnnaBridge	145:64910690c574	2270	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
AnnaBridge	145:64910690c574	2271	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
AnnaBridge	145:64910690c574	2272	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
AnnaBridge	145:64910690c574	2273	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2274	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2275	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	2276	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	2277	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	2278	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	2279	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	2280	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	2281	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	2282	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	2283	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	2284	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	2285	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	2286	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	2287	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	2288	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	2289	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	2290	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	2291	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	2292	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	2293	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	2294	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	2295	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	2296	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	2297	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	2298	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	2299	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	2300	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	2301	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	2302	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	2303	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	2304	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	2305	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	2306	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	2307	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	2308	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	2309	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	2310	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	2311	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	2312	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	2313	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	2314	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	2315	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	2316	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	2317	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	2318	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	2319	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	2320	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	2321	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	2322	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	2323	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	2324	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	2325	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	2326	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	2327	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	2328	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	2329	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	2330	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	2331	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	2332	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	2333	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	2334	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	2335	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	2336	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	2337	* @param __PLLSAIN__ Between 50 and 432
AnnaBridge	145:64910690c574	2338	* @param __PLLSAIP__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2339	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	145:64910690c574	2340	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	145:64910690c574	2341	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	145:64910690c574	2342	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	145:64910690c574	2343	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	145:64910690c574	2344	*/
AnnaBridge	145:64910690c574	2345	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	145:64910690c574	2346	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
AnnaBridge	145:64910690c574	2347	#endif /* RCC_PLLSAICFGR_PLLSAIP */
AnnaBridge	145:64910690c574	2348
AnnaBridge	145:64910690c574	2349	#if defined(LTDC)
AnnaBridge	145:64910690c574	2350	/**
AnnaBridge	145:64910690c574	2351	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
AnnaBridge	145:64910690c574	2352	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
AnnaBridge	145:64910690c574	2353	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
AnnaBridge	145:64910690c574	2354	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2355	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2356	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	2357	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	2358	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	2359	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	2360	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	2361	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	2362	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	2363	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	2364	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	2365	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	2366	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	2367	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	2368	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	2369	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	2370	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	2371	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	2372	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	2373	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	2374	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	2375	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	2376	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	2377	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	2378	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	2379	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	2380	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	2381	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	2382	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	2383	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	2384	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	2385	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	2386	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	2387	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	2388	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	2389	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	2390	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	2391	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	2392	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	2393	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	2394	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	2395	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	2396	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	2397	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	2398	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	2399	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	2400	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	2401	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	2402	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	2403	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	2404	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	2405	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	2406	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	2407	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	2408	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	2409	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	2410	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	2411	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	2412	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	2413	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	2414	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	2415	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	2416	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	2417	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	2418	* @param __PLLSAIN__ Between 49/50(*) and 432
AnnaBridge	145:64910690c574	2419	*
AnnaBridge	145:64910690c574	2420	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2421	* @param __PLLSAIR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2422	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	145:64910690c574	2423	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	145:64910690c574	2424	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	145:64910690c574	2425	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	145:64910690c574	2426	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	145:64910690c574	2427	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	145:64910690c574	2428	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2429	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	145:64910690c574	2430	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	145:64910690c574	2431	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	145:64910690c574	2432	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	145:64910690c574	2433	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	145:64910690c574	2434	*/
AnnaBridge	145:64910690c574	2435	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	145:64910690c574	2436	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
AnnaBridge	145:64910690c574	2437	#endif /* LTDC */
AnnaBridge	145:64910690c574	2438	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	2439
AnnaBridge	145:64910690c574	2440	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	2441	#if defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR)
AnnaBridge	145:64910690c574	2442	/**
AnnaBridge	145:64910690c574	2443	* @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
AnnaBridge	145:64910690c574	2444	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
AnnaBridge	145:64910690c574	2445	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
AnnaBridge	145:64910690c574	2446	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2447	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2448	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	2449	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	2450	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	2451	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	2452	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	2453	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	2454	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	2455	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	2456	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	2457	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	2458	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	2459	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	2460	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	2461	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	2462	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	2463	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	2464	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	2465	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	2466	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	2467	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	2468	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	2469	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	2470	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	2471	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	2472	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	2473	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	2474	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	2475	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	2476	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	2477	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	2478	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	2479	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	2480	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	2481	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	2482	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	2483	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	2484	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	2485	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	2486	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	2487	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	2488	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	2489	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	2490	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	2491	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	2492	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	2493	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	2494	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	2495	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	2496	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	2497	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	2498	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	2499	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	2500	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	2501	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	2502	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	2503	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	2504	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	2505	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	2506	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	2507	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	2508	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	2509	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	2510	* @param __PLLI2SN__ Between 50/192(*) and 432
AnnaBridge	145:64910690c574	2511	*
AnnaBridge	145:64910690c574	2512	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2513	* @param __PLLI2SQ_R__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2514	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
AnnaBridge	145:64910690c574	2515	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
AnnaBridge	145:64910690c574	2516	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
AnnaBridge	145:64910690c574	2517	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
AnnaBridge	145:64910690c574	2518	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
AnnaBridge	145:64910690c574	2519	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
AnnaBridge	145:64910690c574	2520	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
AnnaBridge	145:64910690c574	2521	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
AnnaBridge	145:64910690c574	2522	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
AnnaBridge	145:64910690c574	2523	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
AnnaBridge	145:64910690c574	2524	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
AnnaBridge	145:64910690c574	2525	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
AnnaBridge	145:64910690c574	2526	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
AnnaBridge	145:64910690c574	2527	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
AnnaBridge	145:64910690c574	2528	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
AnnaBridge	145:64910690c574	2529	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
AnnaBridge	145:64910690c574	2530	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
AnnaBridge	145:64910690c574	2531	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
AnnaBridge	145:64910690c574	2532	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
AnnaBridge	145:64910690c574	2533	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
AnnaBridge	145:64910690c574	2534	*
AnnaBridge	145:64910690c574	2535	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2536	* @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2537	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
AnnaBridge	145:64910690c574	2538	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
AnnaBridge	145:64910690c574	2539	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
AnnaBridge	145:64910690c574	2540	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
AnnaBridge	145:64910690c574	2541	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
AnnaBridge	145:64910690c574	2542	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
AnnaBridge	145:64910690c574	2543	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
AnnaBridge	145:64910690c574	2544	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
AnnaBridge	145:64910690c574	2545	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
AnnaBridge	145:64910690c574	2546	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
AnnaBridge	145:64910690c574	2547	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
AnnaBridge	145:64910690c574	2548	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
AnnaBridge	145:64910690c574	2549	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
AnnaBridge	145:64910690c574	2550	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
AnnaBridge	145:64910690c574	2551	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
AnnaBridge	145:64910690c574	2552	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
AnnaBridge	145:64910690c574	2553	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
AnnaBridge	145:64910690c574	2554	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
AnnaBridge	145:64910690c574	2555	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
AnnaBridge	145:64910690c574	2556	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
AnnaBridge	145:64910690c574	2557	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
AnnaBridge	145:64910690c574	2558	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
AnnaBridge	145:64910690c574	2559	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
AnnaBridge	145:64910690c574	2560	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
AnnaBridge	145:64910690c574	2561	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
AnnaBridge	145:64910690c574	2562	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
AnnaBridge	145:64910690c574	2563	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
AnnaBridge	145:64910690c574	2564	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
AnnaBridge	145:64910690c574	2565	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
AnnaBridge	145:64910690c574	2566	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
AnnaBridge	145:64910690c574	2567	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
AnnaBridge	145:64910690c574	2568	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
AnnaBridge	145:64910690c574	2569	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
AnnaBridge	145:64910690c574	2570	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
AnnaBridge	145:64910690c574	2571	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
AnnaBridge	145:64910690c574	2572	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
AnnaBridge	145:64910690c574	2573	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
AnnaBridge	145:64910690c574	2574	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
AnnaBridge	145:64910690c574	2575	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
AnnaBridge	145:64910690c574	2576	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
AnnaBridge	145:64910690c574	2577	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
AnnaBridge	145:64910690c574	2578	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
AnnaBridge	145:64910690c574	2579	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
AnnaBridge	145:64910690c574	2580	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
AnnaBridge	145:64910690c574	2581	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
AnnaBridge	145:64910690c574	2582	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
AnnaBridge	145:64910690c574	2583	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
AnnaBridge	145:64910690c574	2584	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
AnnaBridge	145:64910690c574	2585	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
AnnaBridge	145:64910690c574	2586	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
AnnaBridge	145:64910690c574	2587	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
AnnaBridge	145:64910690c574	2588	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
AnnaBridge	145:64910690c574	2589	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
AnnaBridge	145:64910690c574	2590	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
AnnaBridge	145:64910690c574	2591	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
AnnaBridge	145:64910690c574	2592	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
AnnaBridge	145:64910690c574	2593	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
AnnaBridge	145:64910690c574	2594	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
AnnaBridge	145:64910690c574	2595	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
AnnaBridge	145:64910690c574	2596	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
AnnaBridge	145:64910690c574	2597	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
AnnaBridge	145:64910690c574	2598	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
AnnaBridge	145:64910690c574	2599	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
AnnaBridge	145:64910690c574	2600	*
AnnaBridge	145:64910690c574	2601	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2602	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	2603	*/
AnnaBridge	145:64910690c574	2604	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	2605	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	2606	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
AnnaBridge	145:64910690c574	2607	#else
AnnaBridge	145:64910690c574	2608	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	2609	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
AnnaBridge	145:64910690c574	2610
AnnaBridge	145:64910690c574	2611	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	2612	#endif /* RCC_DCKCFGR_PLLI2SDIVQ \|\| RCC_DCKCFGR_PLLI2SDIVR */
AnnaBridge	145:64910690c574	2613
AnnaBridge	145:64910690c574	2614	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	2615	/**
AnnaBridge	145:64910690c574	2616	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
AnnaBridge	145:64910690c574	2617	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
AnnaBridge	145:64910690c574	2618	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
AnnaBridge	145:64910690c574	2619	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2620	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2621	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	2622	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	2623	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	2624	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	2625	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	2626	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	2627	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	2628	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	2629	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	2630	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	2631	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	2632	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	2633	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	2634	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	2635	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	2636	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	2637	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	2638	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	2639	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	2640	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	2641	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	2642	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	2643	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	2644	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	2645	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	2646	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	2647	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	2648	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	2649	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	2650	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	2651	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	2652	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	2653	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	2654	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	2655	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	2656	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	2657	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	2658	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	2659	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	2660	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	2661	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	2662	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	2663	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	2664	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	2665	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	2666	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	2667	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	2668	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	2669	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	2670	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	2671	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	2672	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	2673	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	2674	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	2675	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	2676	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	2677	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	2678	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	2679	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	2680	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	2681	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	2682	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	2683	* @param __PLLI2SN__ Between 50 and 432
AnnaBridge	145:64910690c574	2684	* @param __PLLI2SP__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2685	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	145:64910690c574	2686	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	145:64910690c574	2687	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	145:64910690c574	2688	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	145:64910690c574	2689	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	2690	*/
AnnaBridge	145:64910690c574	2691	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	2692	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
AnnaBridge	145:64910690c574	2693
AnnaBridge	145:64910690c574	2694	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	2695
AnnaBridge	145:64910690c574	2696	/**
AnnaBridge	145:64910690c574	2697	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
AnnaBridge	145:64910690c574	2698	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
AnnaBridge	145:64910690c574	2699	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
AnnaBridge	145:64910690c574	2700	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2701	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2702	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	2703	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	2704	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	2705	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	2706	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	2707	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	2708	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	2709	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	2710	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	2711	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	2712	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	2713	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	2714	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	2715	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	2716	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	2717	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	2718	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	2719	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	2720	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	2721	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	2722	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	2723	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	2724	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	2725	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	2726	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	2727	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	2728	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	2729	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	2730	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	2731	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	2732	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	2733	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	2734	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	2735	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	2736	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	2737	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	2738	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	2739	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	2740	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	2741	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	2742	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	2743	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	2744	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	2745	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	2746	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	2747	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	2748	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	2749	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	2750	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	2751	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	2752	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	2753	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	2754	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	2755	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	2756	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	2757	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	2758	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	2759	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	2760	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	2761	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	2762	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	2763	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	2764	* @param __PLLI2SN__ Between 50/192(*) and 432
AnnaBridge	145:64910690c574	2765	*
AnnaBridge	145:64910690c574	2766	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2767	* @param __PLLI2SR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2768	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	2769	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	2770	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	2771	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	2772	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	2773	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	2774	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	2775	*/
AnnaBridge	145:64910690c574	2776	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	2777	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
AnnaBridge	145:64910690c574	2778
AnnaBridge	145:64910690c574	2779	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	2780	/**
AnnaBridge	145:64910690c574	2781	* @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
AnnaBridge	145:64910690c574	2782	* @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
AnnaBridge	145:64910690c574	2783	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
AnnaBridge	145:64910690c574	2784	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	2785	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2786	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	2787	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	2788	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	2789	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	2790	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	2791	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	2792	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	2793	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	2794	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	2795	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	2796	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	2797	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	2798	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	2799	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	2800	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	2801	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	2802	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	2803	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	2804	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	2805	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	2806	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	2807	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	2808	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	2809	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	2810	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	2811	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	2812	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	2813	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	2814	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	2815	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	2816	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	2817	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	2818	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	2819	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	2820	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	2821	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	2822	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	2823	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	2824	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	2825	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	2826	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	2827	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	2828	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	2829	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	2830	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	2831	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	2832	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	2833	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	2834	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	2835	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	2836	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	2837	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	2838	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	2839	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	2840	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	2841	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	2842	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	2843	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	2844	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	2845	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	2846	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	2847	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	2848	* @param __PLLI2SN__ Between 50 and 432
AnnaBridge	145:64910690c574	2849	* @param __PLLI2SQ__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2850	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	145:64910690c574	2851	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	145:64910690c574	2852	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	145:64910690c574	2853	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	145:64910690c574	2854	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	145:64910690c574	2855	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	145:64910690c574	2856	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	145:64910690c574	2857	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	145:64910690c574	2858	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	145:64910690c574	2859	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	145:64910690c574	2860	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	145:64910690c574	2861	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	145:64910690c574	2862	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	145:64910690c574	2863	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	145:64910690c574	2864	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	2865	*/
AnnaBridge	145:64910690c574	2866	#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	2867	((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
AnnaBridge	145:64910690c574	2868
AnnaBridge	145:64910690c574	2869	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	2870	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	2871
AnnaBridge	145:64910690c574	2872	/**
AnnaBridge	145:64910690c574	2873	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	145:64910690c574	2874	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
AnnaBridge	145:64910690c574	2875	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2876	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	2877	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	2878	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	2879	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	2880	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	2881	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	2882	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	2883	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	2884	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	2885	* @retval HCLK clock frequency (in Hz)
AnnaBridge	145:64910690c574	2886	*/
AnnaBridge	145:64910690c574	2887	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	145:64910690c574	2888
AnnaBridge	145:64910690c574	2889	/**
AnnaBridge	145:64910690c574	2890	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	145:64910690c574	2891	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	145:64910690c574	2892	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2893	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	2894	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	2895	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	2896	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	2897	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	2898	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	145:64910690c574	2899	*/
AnnaBridge	145:64910690c574	2900	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	145:64910690c574	2901
AnnaBridge	145:64910690c574	2902	/**
AnnaBridge	145:64910690c574	2903	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	145:64910690c574	2904	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	145:64910690c574	2905	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2906	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	2907	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	2908	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	2909	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	2910	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	2911	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	145:64910690c574	2912	*/
AnnaBridge	145:64910690c574	2913	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	145:64910690c574	2914
AnnaBridge	145:64910690c574	2915	/**
AnnaBridge	145:64910690c574	2916	* @}
AnnaBridge	145:64910690c574	2917	*/
AnnaBridge	145:64910690c574	2918
AnnaBridge	145:64910690c574	2919	/**
AnnaBridge	145:64910690c574	2920	* @}
AnnaBridge	145:64910690c574	2921	*/
AnnaBridge	145:64910690c574	2922
AnnaBridge	145:64910690c574	2923	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	2924	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	145:64910690c574	2925	* @{
AnnaBridge	145:64910690c574	2926	*/
AnnaBridge	145:64910690c574	2927
AnnaBridge	145:64910690c574	2928	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	145:64910690c574	2929	* @{
AnnaBridge	145:64910690c574	2930	*/
AnnaBridge	145:64910690c574	2931
AnnaBridge	145:64910690c574	2932	/**
AnnaBridge	145:64910690c574	2933	* @brief Enable the Clock Security System.
AnnaBridge	145:64910690c574	2934	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	145:64910690c574	2935	* @retval None
AnnaBridge	145:64910690c574	2936	*/
AnnaBridge	145:64910690c574	2937	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	145:64910690c574	2938	{
AnnaBridge	145:64910690c574	2939	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	145:64910690c574	2940	}
AnnaBridge	145:64910690c574	2941
AnnaBridge	145:64910690c574	2942	/**
AnnaBridge	145:64910690c574	2943	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	145:64910690c574	2944	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	145:64910690c574	2945	* @retval None
AnnaBridge	145:64910690c574	2946	*/
AnnaBridge	145:64910690c574	2947	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	145:64910690c574	2948	{
AnnaBridge	145:64910690c574	2949	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	145:64910690c574	2950	}
AnnaBridge	145:64910690c574	2951
AnnaBridge	145:64910690c574	2952	/**
AnnaBridge	145:64910690c574	2953	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	145:64910690c574	2954	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	145:64910690c574	2955	* @retval None
AnnaBridge	145:64910690c574	2956	*/
AnnaBridge	145:64910690c574	2957	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	145:64910690c574	2958	{
AnnaBridge	145:64910690c574	2959	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	145:64910690c574	2960	}
AnnaBridge	145:64910690c574	2961
AnnaBridge	145:64910690c574	2962	/**
AnnaBridge	145:64910690c574	2963	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	145:64910690c574	2964	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	145:64910690c574	2965	* @retval None
AnnaBridge	145:64910690c574	2966	*/
AnnaBridge	145:64910690c574	2967	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	145:64910690c574	2968	{
AnnaBridge	145:64910690c574	2969	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	145:64910690c574	2970	}
AnnaBridge	145:64910690c574	2971
AnnaBridge	145:64910690c574	2972	/**
AnnaBridge	145:64910690c574	2973	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	145:64910690c574	2974	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	145:64910690c574	2975	* @retval None
AnnaBridge	145:64910690c574	2976	*/
AnnaBridge	145:64910690c574	2977	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	145:64910690c574	2978	{
AnnaBridge	145:64910690c574	2979	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	145:64910690c574	2980	}
AnnaBridge	145:64910690c574	2981
AnnaBridge	145:64910690c574	2982	/**
AnnaBridge	145:64910690c574	2983	* @brief Check if HSE oscillator Ready
AnnaBridge	145:64910690c574	2984	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	145:64910690c574	2985	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2986	*/
AnnaBridge	145:64910690c574	2987	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	145:64910690c574	2988	{
AnnaBridge	145:64910690c574	2989	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	145:64910690c574	2990	}
AnnaBridge	145:64910690c574	2991
AnnaBridge	145:64910690c574	2992	/**
AnnaBridge	145:64910690c574	2993	* @}
AnnaBridge	145:64910690c574	2994	*/
AnnaBridge	145:64910690c574	2995
AnnaBridge	145:64910690c574	2996	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	145:64910690c574	2997	* @{
AnnaBridge	145:64910690c574	2998	*/
AnnaBridge	145:64910690c574	2999
AnnaBridge	145:64910690c574	3000	/**
AnnaBridge	145:64910690c574	3001	* @brief Enable HSI oscillator
AnnaBridge	145:64910690c574	3002	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	145:64910690c574	3003	* @retval None
AnnaBridge	145:64910690c574	3004	*/
AnnaBridge	145:64910690c574	3005	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	145:64910690c574	3006	{
AnnaBridge	145:64910690c574	3007	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	145:64910690c574	3008	}
AnnaBridge	145:64910690c574	3009
AnnaBridge	145:64910690c574	3010	/**
AnnaBridge	145:64910690c574	3011	* @brief Disable HSI oscillator
AnnaBridge	145:64910690c574	3012	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	145:64910690c574	3013	* @retval None
AnnaBridge	145:64910690c574	3014	*/
AnnaBridge	145:64910690c574	3015	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	145:64910690c574	3016	{
AnnaBridge	145:64910690c574	3017	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	145:64910690c574	3018	}
AnnaBridge	145:64910690c574	3019
AnnaBridge	145:64910690c574	3020	/**
AnnaBridge	145:64910690c574	3021	* @brief Check if HSI clock is ready
AnnaBridge	145:64910690c574	3022	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	145:64910690c574	3023	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	3024	*/
AnnaBridge	145:64910690c574	3025	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	145:64910690c574	3026	{
AnnaBridge	145:64910690c574	3027	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	145:64910690c574	3028	}
AnnaBridge	145:64910690c574	3029
AnnaBridge	145:64910690c574	3030	/**
AnnaBridge	145:64910690c574	3031	* @brief Get HSI Calibration value
AnnaBridge	145:64910690c574	3032	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	145:64910690c574	3033	* HSITRIM and the factory trim value
AnnaBridge	145:64910690c574	3034	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	145:64910690c574	3035	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	145:64910690c574	3036	*/
AnnaBridge	145:64910690c574	3037	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	145:64910690c574	3038	{
AnnaBridge	145:64910690c574	3039	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
AnnaBridge	145:64910690c574	3040	}
AnnaBridge	145:64910690c574	3041
AnnaBridge	145:64910690c574	3042	/**
AnnaBridge	145:64910690c574	3043	* @brief Set HSI Calibration trimming
AnnaBridge	145:64910690c574	3044	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	145:64910690c574	3045	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	145:64910690c574	3046	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	145:64910690c574	3047	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	145:64910690c574	3048	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	145:64910690c574	3049	* @retval None
AnnaBridge	145:64910690c574	3050	*/
AnnaBridge	145:64910690c574	3051	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	145:64910690c574	3052	{
AnnaBridge	145:64910690c574	3053	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
AnnaBridge	145:64910690c574	3054	}
AnnaBridge	145:64910690c574	3055
AnnaBridge	145:64910690c574	3056	/**
AnnaBridge	145:64910690c574	3057	* @brief Get HSI Calibration trimming
AnnaBridge	145:64910690c574	3058	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	145:64910690c574	3059	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	145:64910690c574	3060	*/
AnnaBridge	145:64910690c574	3061	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	145:64910690c574	3062	{
AnnaBridge	145:64910690c574	3063	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
AnnaBridge	145:64910690c574	3064	}
AnnaBridge	145:64910690c574	3065
AnnaBridge	145:64910690c574	3066	/**
AnnaBridge	145:64910690c574	3067	* @}
AnnaBridge	145:64910690c574	3068	*/
AnnaBridge	145:64910690c574	3069
AnnaBridge	145:64910690c574	3070	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	145:64910690c574	3071	* @{
AnnaBridge	145:64910690c574	3072	*/
AnnaBridge	145:64910690c574	3073
AnnaBridge	145:64910690c574	3074	/**
AnnaBridge	145:64910690c574	3075	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	145:64910690c574	3076	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	145:64910690c574	3077	* @retval None
AnnaBridge	145:64910690c574	3078	*/
AnnaBridge	145:64910690c574	3079	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	145:64910690c574	3080	{
AnnaBridge	145:64910690c574	3081	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	145:64910690c574	3082	}
AnnaBridge	145:64910690c574	3083
AnnaBridge	145:64910690c574	3084	/**
AnnaBridge	145:64910690c574	3085	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	145:64910690c574	3086	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	145:64910690c574	3087	* @retval None
AnnaBridge	145:64910690c574	3088	*/
AnnaBridge	145:64910690c574	3089	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	145:64910690c574	3090	{
AnnaBridge	145:64910690c574	3091	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	145:64910690c574	3092	}
AnnaBridge	145:64910690c574	3093
AnnaBridge	145:64910690c574	3094	/**
AnnaBridge	145:64910690c574	3095	* @brief Enable external clock source (LSE bypass).
AnnaBridge	145:64910690c574	3096	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	145:64910690c574	3097	* @retval None
AnnaBridge	145:64910690c574	3098	*/
AnnaBridge	145:64910690c574	3099	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	145:64910690c574	3100	{
AnnaBridge	145:64910690c574	3101	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	145:64910690c574	3102	}
AnnaBridge	145:64910690c574	3103
AnnaBridge	145:64910690c574	3104	/**
AnnaBridge	145:64910690c574	3105	* @brief Disable external clock source (LSE bypass).
AnnaBridge	145:64910690c574	3106	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	145:64910690c574	3107	* @retval None
AnnaBridge	145:64910690c574	3108	*/
AnnaBridge	145:64910690c574	3109	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	145:64910690c574	3110	{
AnnaBridge	145:64910690c574	3111	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	145:64910690c574	3112	}
AnnaBridge	145:64910690c574	3113
AnnaBridge	145:64910690c574	3114	/**
AnnaBridge	145:64910690c574	3115	* @brief Check if LSE oscillator Ready
AnnaBridge	145:64910690c574	3116	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	145:64910690c574	3117	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	3118	*/
AnnaBridge	145:64910690c574	3119	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	145:64910690c574	3120	{
AnnaBridge	145:64910690c574	3121	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	145:64910690c574	3122	}
AnnaBridge	145:64910690c574	3123
AnnaBridge	145:64910690c574	3124	#if defined(RCC_BDCR_LSEMOD)
AnnaBridge	145:64910690c574	3125	/**
AnnaBridge	145:64910690c574	3126	* @brief Enable LSE high drive mode.
AnnaBridge	145:64910690c574	3127	* @note LSE high drive mode can be enabled only when the LSE clock is disabled
AnnaBridge	145:64910690c574	3128	* @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
AnnaBridge	145:64910690c574	3129	* @retval None
AnnaBridge	145:64910690c574	3130	*/
AnnaBridge	145:64910690c574	3131	__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
AnnaBridge	145:64910690c574	3132	{
AnnaBridge	145:64910690c574	3133	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
AnnaBridge	145:64910690c574	3134	}
AnnaBridge	145:64910690c574	3135
AnnaBridge	145:64910690c574	3136	/**
AnnaBridge	145:64910690c574	3137	* @brief Disable LSE high drive mode.
AnnaBridge	145:64910690c574	3138	* @note LSE high drive mode can be disabled only when the LSE clock is disabled
AnnaBridge	145:64910690c574	3139	* @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
AnnaBridge	145:64910690c574	3140	* @retval None
AnnaBridge	145:64910690c574	3141	*/
AnnaBridge	145:64910690c574	3142	__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
AnnaBridge	145:64910690c574	3143	{
AnnaBridge	145:64910690c574	3144	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
AnnaBridge	145:64910690c574	3145	}
AnnaBridge	145:64910690c574	3146	#endif /* RCC_BDCR_LSEMOD */
AnnaBridge	145:64910690c574	3147
AnnaBridge	145:64910690c574	3148	/**
AnnaBridge	145:64910690c574	3149	* @}
AnnaBridge	145:64910690c574	3150	*/
AnnaBridge	145:64910690c574	3151
AnnaBridge	145:64910690c574	3152	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	145:64910690c574	3153	* @{
AnnaBridge	145:64910690c574	3154	*/
AnnaBridge	145:64910690c574	3155
AnnaBridge	145:64910690c574	3156	/**
AnnaBridge	145:64910690c574	3157	* @brief Enable LSI Oscillator
AnnaBridge	145:64910690c574	3158	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	145:64910690c574	3159	* @retval None
AnnaBridge	145:64910690c574	3160	*/
AnnaBridge	145:64910690c574	3161	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	145:64910690c574	3162	{
AnnaBridge	145:64910690c574	3163	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	145:64910690c574	3164	}
AnnaBridge	145:64910690c574	3165
AnnaBridge	145:64910690c574	3166	/**
AnnaBridge	145:64910690c574	3167	* @brief Disable LSI Oscillator
AnnaBridge	145:64910690c574	3168	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	145:64910690c574	3169	* @retval None
AnnaBridge	145:64910690c574	3170	*/
AnnaBridge	145:64910690c574	3171	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	145:64910690c574	3172	{
AnnaBridge	145:64910690c574	3173	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	145:64910690c574	3174	}
AnnaBridge	145:64910690c574	3175
AnnaBridge	145:64910690c574	3176	/**
AnnaBridge	145:64910690c574	3177	* @brief Check if LSI is Ready
AnnaBridge	145:64910690c574	3178	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	145:64910690c574	3179	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	3180	*/
AnnaBridge	145:64910690c574	3181	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	145:64910690c574	3182	{
AnnaBridge	145:64910690c574	3183	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	145:64910690c574	3184	}
AnnaBridge	145:64910690c574	3185
AnnaBridge	145:64910690c574	3186	/**
AnnaBridge	145:64910690c574	3187	* @}
AnnaBridge	145:64910690c574	3188	*/
AnnaBridge	145:64910690c574	3189
AnnaBridge	145:64910690c574	3190	/** @defgroup RCC_LL_EF_System System
AnnaBridge	145:64910690c574	3191	* @{
AnnaBridge	145:64910690c574	3192	*/
AnnaBridge	145:64910690c574	3193
AnnaBridge	145:64910690c574	3194	/**
AnnaBridge	145:64910690c574	3195	* @brief Configure the system clock source
AnnaBridge	145:64910690c574	3196	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	145:64910690c574	3197	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3198	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	3199	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	3200	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3201	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
AnnaBridge	145:64910690c574	3202	*
AnnaBridge	145:64910690c574	3203	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3204	* @retval None
AnnaBridge	145:64910690c574	3205	*/
AnnaBridge	145:64910690c574	3206	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	145:64910690c574	3207	{
AnnaBridge	145:64910690c574	3208	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	145:64910690c574	3209	}
AnnaBridge	145:64910690c574	3210
AnnaBridge	145:64910690c574	3211	/**
AnnaBridge	145:64910690c574	3212	* @brief Get the system clock source
AnnaBridge	145:64910690c574	3213	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	145:64910690c574	3214	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3215	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	145:64910690c574	3216	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	145:64910690c574	3217	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	145:64910690c574	3218	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
AnnaBridge	145:64910690c574	3219	*
AnnaBridge	145:64910690c574	3220	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3221	*/
AnnaBridge	145:64910690c574	3222	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	145:64910690c574	3223	{
AnnaBridge	145:64910690c574	3224	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	145:64910690c574	3225	}
AnnaBridge	145:64910690c574	3226
AnnaBridge	145:64910690c574	3227	/**
AnnaBridge	145:64910690c574	3228	* @brief Set AHB prescaler
AnnaBridge	145:64910690c574	3229	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	145:64910690c574	3230	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3231	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	3232	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	3233	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	3234	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	3235	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	3236	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	3237	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	3238	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	3239	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	3240	* @retval None
AnnaBridge	145:64910690c574	3241	*/
AnnaBridge	145:64910690c574	3242	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	3243	{
AnnaBridge	145:64910690c574	3244	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	145:64910690c574	3245	}
AnnaBridge	145:64910690c574	3246
AnnaBridge	145:64910690c574	3247	/**
AnnaBridge	145:64910690c574	3248	* @brief Set APB1 prescaler
AnnaBridge	145:64910690c574	3249	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	145:64910690c574	3250	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3251	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	3252	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	3253	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	3254	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	3255	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	3256	* @retval None
AnnaBridge	145:64910690c574	3257	*/
AnnaBridge	145:64910690c574	3258	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	3259	{
AnnaBridge	145:64910690c574	3260	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	145:64910690c574	3261	}
AnnaBridge	145:64910690c574	3262
AnnaBridge	145:64910690c574	3263	/**
AnnaBridge	145:64910690c574	3264	* @brief Set APB2 prescaler
AnnaBridge	145:64910690c574	3265	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	145:64910690c574	3266	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3267	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	3268	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	3269	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	3270	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	3271	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	3272	* @retval None
AnnaBridge	145:64910690c574	3273	*/
AnnaBridge	145:64910690c574	3274	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	3275	{
AnnaBridge	145:64910690c574	3276	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	145:64910690c574	3277	}
AnnaBridge	145:64910690c574	3278
AnnaBridge	145:64910690c574	3279	/**
AnnaBridge	145:64910690c574	3280	* @brief Get AHB prescaler
AnnaBridge	145:64910690c574	3281	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	145:64910690c574	3282	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3283	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	3284	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	3285	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	3286	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	3287	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	3288	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	3289	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	3290	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	3291	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	3292	*/
AnnaBridge	145:64910690c574	3293	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	145:64910690c574	3294	{
AnnaBridge	145:64910690c574	3295	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	145:64910690c574	3296	}
AnnaBridge	145:64910690c574	3297
AnnaBridge	145:64910690c574	3298	/**
AnnaBridge	145:64910690c574	3299	* @brief Get APB1 prescaler
AnnaBridge	145:64910690c574	3300	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	145:64910690c574	3301	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3302	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	3303	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	3304	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	3305	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	3306	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	3307	*/
AnnaBridge	145:64910690c574	3308	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	145:64910690c574	3309	{
AnnaBridge	145:64910690c574	3310	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	145:64910690c574	3311	}
AnnaBridge	145:64910690c574	3312
AnnaBridge	145:64910690c574	3313	/**
AnnaBridge	145:64910690c574	3314	* @brief Get APB2 prescaler
AnnaBridge	145:64910690c574	3315	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	145:64910690c574	3316	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3317	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	3318	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	3319	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	3320	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	3321	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	3322	*/
AnnaBridge	145:64910690c574	3323	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	145:64910690c574	3324	{
AnnaBridge	145:64910690c574	3325	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	145:64910690c574	3326	}
AnnaBridge	145:64910690c574	3327
AnnaBridge	145:64910690c574	3328	/**
AnnaBridge	145:64910690c574	3329	* @}
AnnaBridge	145:64910690c574	3330	*/
AnnaBridge	145:64910690c574	3331
AnnaBridge	145:64910690c574	3332	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	145:64910690c574	3333	* @{
AnnaBridge	145:64910690c574	3334	*/
AnnaBridge	145:64910690c574	3335
AnnaBridge	145:64910690c574	3336	#if defined(RCC_CFGR_MCO1EN)
AnnaBridge	145:64910690c574	3337	/**
AnnaBridge	145:64910690c574	3338	* @brief Enable MCO1 output
AnnaBridge	145:64910690c574	3339	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
AnnaBridge	145:64910690c574	3340	* @retval None
AnnaBridge	145:64910690c574	3341	*/
AnnaBridge	145:64910690c574	3342	__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
AnnaBridge	145:64910690c574	3343	{
AnnaBridge	145:64910690c574	3344	SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
AnnaBridge	145:64910690c574	3345	}
AnnaBridge	145:64910690c574	3346
AnnaBridge	145:64910690c574	3347	/**
AnnaBridge	145:64910690c574	3348	* @brief Disable MCO1 output
AnnaBridge	145:64910690c574	3349	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
AnnaBridge	145:64910690c574	3350	* @retval None
AnnaBridge	145:64910690c574	3351	*/
AnnaBridge	145:64910690c574	3352	__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
AnnaBridge	145:64910690c574	3353	{
AnnaBridge	145:64910690c574	3354	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
AnnaBridge	145:64910690c574	3355	}
AnnaBridge	145:64910690c574	3356	#endif /* RCC_CFGR_MCO1EN */
AnnaBridge	145:64910690c574	3357
AnnaBridge	145:64910690c574	3358	#if defined(RCC_CFGR_MCO2EN)
AnnaBridge	145:64910690c574	3359	/**
AnnaBridge	145:64910690c574	3360	* @brief Enable MCO2 output
AnnaBridge	145:64910690c574	3361	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
AnnaBridge	145:64910690c574	3362	* @retval None
AnnaBridge	145:64910690c574	3363	*/
AnnaBridge	145:64910690c574	3364	__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
AnnaBridge	145:64910690c574	3365	{
AnnaBridge	145:64910690c574	3366	SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
AnnaBridge	145:64910690c574	3367	}
AnnaBridge	145:64910690c574	3368
AnnaBridge	145:64910690c574	3369	/**
AnnaBridge	145:64910690c574	3370	* @brief Disable MCO2 output
AnnaBridge	145:64910690c574	3371	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
AnnaBridge	145:64910690c574	3372	* @retval None
AnnaBridge	145:64910690c574	3373	*/
AnnaBridge	145:64910690c574	3374	__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
AnnaBridge	145:64910690c574	3375	{
AnnaBridge	145:64910690c574	3376	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
AnnaBridge	145:64910690c574	3377	}
AnnaBridge	145:64910690c574	3378	#endif /* RCC_CFGR_MCO2EN */
AnnaBridge	145:64910690c574	3379
AnnaBridge	145:64910690c574	3380	/**
AnnaBridge	145:64910690c574	3381	* @brief Configure MCOx
AnnaBridge	145:64910690c574	3382	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	3383	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	3384	* CFGR MCO2 LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	3385	* CFGR MCO2PRE LL_RCC_ConfigMCO
AnnaBridge	145:64910690c574	3386	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3387	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	145:64910690c574	3388	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	145:64910690c574	3389	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	145:64910690c574	3390	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	145:64910690c574	3391	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
AnnaBridge	145:64910690c574	3392	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
AnnaBridge	145:64910690c574	3393	* @arg @ref LL_RCC_MCO2SOURCE_HSE
AnnaBridge	145:64910690c574	3394	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
AnnaBridge	145:64910690c574	3395	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3396	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	145:64910690c574	3397	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	145:64910690c574	3398	* @arg @ref LL_RCC_MCO1_DIV_3
AnnaBridge	145:64910690c574	3399	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	145:64910690c574	3400	* @arg @ref LL_RCC_MCO1_DIV_5
AnnaBridge	145:64910690c574	3401	* @arg @ref LL_RCC_MCO2_DIV_1
AnnaBridge	145:64910690c574	3402	* @arg @ref LL_RCC_MCO2_DIV_2
AnnaBridge	145:64910690c574	3403	* @arg @ref LL_RCC_MCO2_DIV_3
AnnaBridge	145:64910690c574	3404	* @arg @ref LL_RCC_MCO2_DIV_4
AnnaBridge	145:64910690c574	3405	* @arg @ref LL_RCC_MCO2_DIV_5
AnnaBridge	145:64910690c574	3406	* @retval None
AnnaBridge	145:64910690c574	3407	*/
AnnaBridge	145:64910690c574	3408	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	145:64910690c574	3409	{
AnnaBridge	145:64910690c574	3410	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
AnnaBridge	145:64910690c574	3411	}
AnnaBridge	145:64910690c574	3412
AnnaBridge	145:64910690c574	3413	/**
AnnaBridge	145:64910690c574	3414	* @}
AnnaBridge	145:64910690c574	3415	*/
AnnaBridge	145:64910690c574	3416
AnnaBridge	145:64910690c574	3417	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	145:64910690c574	3418	* @{
AnnaBridge	145:64910690c574	3419	*/
AnnaBridge	145:64910690c574	3420	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	3421	/**
AnnaBridge	145:64910690c574	3422	* @brief Configure FMPI2C clock source
AnnaBridge	145:64910690c574	3423	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
AnnaBridge	145:64910690c574	3424	* @param FMPI2CxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3425	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
AnnaBridge	145:64910690c574	3426	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3427	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	3428	* @retval None
AnnaBridge	145:64910690c574	3429	*/
AnnaBridge	145:64910690c574	3430	__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
AnnaBridge	145:64910690c574	3431	{
AnnaBridge	145:64910690c574	3432	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
AnnaBridge	145:64910690c574	3433	}
AnnaBridge	145:64910690c574	3434	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	3435
AnnaBridge	145:64910690c574	3436	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	3437	/**
AnnaBridge	145:64910690c574	3438	* @brief Configure LPTIMx clock source
AnnaBridge	145:64910690c574	3439	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
AnnaBridge	145:64910690c574	3440	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3441	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	145:64910690c574	3442	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	3443	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	3444	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	3445	* @retval None
AnnaBridge	145:64910690c574	3446	*/
AnnaBridge	145:64910690c574	3447	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
AnnaBridge	145:64910690c574	3448	{
AnnaBridge	145:64910690c574	3449	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
AnnaBridge	145:64910690c574	3450	}
AnnaBridge	145:64910690c574	3451	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	3452
AnnaBridge	145:64910690c574	3453	#if defined(SAI1)
AnnaBridge	145:64910690c574	3454	/**
AnnaBridge	145:64910690c574	3455	* @brief Configure SAIx clock source
AnnaBridge	145:64910690c574	3456	* @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
AnnaBridge	145:64910690c574	3457	* DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
AnnaBridge	145:64910690c574	3458	* DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
AnnaBridge	145:64910690c574	3459	* DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
AnnaBridge	145:64910690c574	3460	* @param SAIxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3461	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3462	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3463	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3464	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3465	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3466	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3467	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3468	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3469	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3470	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3471	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3472	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3473	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3474	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3475	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3476	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3477	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3478	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3479	*
AnnaBridge	145:64910690c574	3480	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3481	* @retval None
AnnaBridge	145:64910690c574	3482	*/
AnnaBridge	145:64910690c574	3483	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
AnnaBridge	145:64910690c574	3484	{
AnnaBridge	145:64910690c574	3485	MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
AnnaBridge	145:64910690c574	3486	}
AnnaBridge	145:64910690c574	3487	#endif /* SAI1 */
AnnaBridge	145:64910690c574	3488
AnnaBridge	145:64910690c574	3489	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	145:64910690c574	3490	/**
AnnaBridge	145:64910690c574	3491	* @brief Configure SDIO clock source
AnnaBridge	145:64910690c574	3492	* @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
AnnaBridge	145:64910690c574	3493	* DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
AnnaBridge	145:64910690c574	3494	* @param SDIOxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3495	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
AnnaBridge	145:64910690c574	3496	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3497	* @retval None
AnnaBridge	145:64910690c574	3498	*/
AnnaBridge	145:64910690c574	3499	__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
AnnaBridge	145:64910690c574	3500	{
AnnaBridge	145:64910690c574	3501	#if defined(RCC_DCKCFGR_SDIOSEL)
AnnaBridge	145:64910690c574	3502	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
AnnaBridge	145:64910690c574	3503	#else
AnnaBridge	145:64910690c574	3504	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
AnnaBridge	145:64910690c574	3505	#endif /* RCC_DCKCFGR_SDIOSEL */
AnnaBridge	145:64910690c574	3506	}
AnnaBridge	145:64910690c574	3507	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
AnnaBridge	145:64910690c574	3508
AnnaBridge	145:64910690c574	3509	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	3510	/**
AnnaBridge	145:64910690c574	3511	* @brief Configure 48Mhz domain clock source
AnnaBridge	145:64910690c574	3512	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
AnnaBridge	145:64910690c574	3513	* DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
AnnaBridge	145:64910690c574	3514	* @param CK48MxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3515	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3516	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3517	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3518	*
AnnaBridge	145:64910690c574	3519	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3520	* @retval None
AnnaBridge	145:64910690c574	3521	*/
AnnaBridge	145:64910690c574	3522	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
AnnaBridge	145:64910690c574	3523	{
AnnaBridge	145:64910690c574	3524	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3525	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
AnnaBridge	145:64910690c574	3526	#else
AnnaBridge	145:64910690c574	3527	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
AnnaBridge	145:64910690c574	3528	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3529	}
AnnaBridge	145:64910690c574	3530
AnnaBridge	145:64910690c574	3531	#if defined(RNG)
AnnaBridge	145:64910690c574	3532	/**
AnnaBridge	145:64910690c574	3533	* @brief Configure RNG clock source
AnnaBridge	145:64910690c574	3534	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
AnnaBridge	145:64910690c574	3535	* DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
AnnaBridge	145:64910690c574	3536	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3537	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3538	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3539	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3540	*
AnnaBridge	145:64910690c574	3541	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3542	* @retval None
AnnaBridge	145:64910690c574	3543	*/
AnnaBridge	145:64910690c574	3544	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
AnnaBridge	145:64910690c574	3545	{
AnnaBridge	145:64910690c574	3546	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3547	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
AnnaBridge	145:64910690c574	3548	#else
AnnaBridge	145:64910690c574	3549	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
AnnaBridge	145:64910690c574	3550	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3551	}
AnnaBridge	145:64910690c574	3552	#endif /* RNG */
AnnaBridge	145:64910690c574	3553
AnnaBridge	145:64910690c574	3554	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	3555	/**
AnnaBridge	145:64910690c574	3556	* @brief Configure USB clock source
AnnaBridge	145:64910690c574	3557	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
AnnaBridge	145:64910690c574	3558	* DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
AnnaBridge	145:64910690c574	3559	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3560	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3561	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3562	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3563	*
AnnaBridge	145:64910690c574	3564	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3565	* @retval None
AnnaBridge	145:64910690c574	3566	*/
AnnaBridge	145:64910690c574	3567	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	145:64910690c574	3568	{
AnnaBridge	145:64910690c574	3569	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3570	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
AnnaBridge	145:64910690c574	3571	#else
AnnaBridge	145:64910690c574	3572	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
AnnaBridge	145:64910690c574	3573	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3574	}
AnnaBridge	145:64910690c574	3575	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
AnnaBridge	145:64910690c574	3576	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	3577
AnnaBridge	145:64910690c574	3578	#if defined(CEC)
AnnaBridge	145:64910690c574	3579	/**
AnnaBridge	145:64910690c574	3580	* @brief Configure CEC clock source
AnnaBridge	145:64910690c574	3581	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
AnnaBridge	145:64910690c574	3582	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3583	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
AnnaBridge	145:64910690c574	3584	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	3585	* @retval None
AnnaBridge	145:64910690c574	3586	*/
AnnaBridge	145:64910690c574	3587	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	3588	{
AnnaBridge	145:64910690c574	3589	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
AnnaBridge	145:64910690c574	3590	}
AnnaBridge	145:64910690c574	3591	#endif /* CEC */
AnnaBridge	145:64910690c574	3592
AnnaBridge	145:64910690c574	3593	/**
AnnaBridge	145:64910690c574	3594	* @brief Configure I2S clock source
AnnaBridge	145:64910690c574	3595	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
AnnaBridge	145:64910690c574	3596	* DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
AnnaBridge	145:64910690c574	3597	* DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
AnnaBridge	145:64910690c574	3598	* DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
AnnaBridge	145:64910690c574	3599	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3600	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3601	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	145:64910690c574	3602	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3603	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3604	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3605	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3606	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3607	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3608	*
AnnaBridge	145:64910690c574	3609	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3610	* @retval None
AnnaBridge	145:64910690c574	3611	*/
AnnaBridge	145:64910690c574	3612	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	3613	{
AnnaBridge	145:64910690c574	3614	#if defined(RCC_CFGR_I2SSRC)
AnnaBridge	145:64910690c574	3615	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
AnnaBridge	145:64910690c574	3616	#else
AnnaBridge	145:64910690c574	3617	MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
AnnaBridge	145:64910690c574	3618	#endif /* RCC_CFGR_I2SSRC */
AnnaBridge	145:64910690c574	3619	}
AnnaBridge	145:64910690c574	3620
AnnaBridge	145:64910690c574	3621	#if defined(DSI)
AnnaBridge	145:64910690c574	3622	/**
AnnaBridge	145:64910690c574	3623	* @brief Configure DSI clock source
AnnaBridge	145:64910690c574	3624	* @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
AnnaBridge	145:64910690c574	3625	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3626	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	145:64910690c574	3627	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3628	* @retval None
AnnaBridge	145:64910690c574	3629	*/
AnnaBridge	145:64910690c574	3630	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	3631	{
AnnaBridge	145:64910690c574	3632	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
AnnaBridge	145:64910690c574	3633	}
AnnaBridge	145:64910690c574	3634	#endif /* DSI */
AnnaBridge	145:64910690c574	3635
AnnaBridge	145:64910690c574	3636	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	3637	/**
AnnaBridge	145:64910690c574	3638	* @brief Configure DFSDM Audio clock source
AnnaBridge	145:64910690c574	3639	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
AnnaBridge	145:64910690c574	3640	* DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
AnnaBridge	145:64910690c574	3641	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3642	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
AnnaBridge	145:64910690c574	3643	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
AnnaBridge	145:64910690c574	3644	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
AnnaBridge	145:64910690c574	3645	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
AnnaBridge	145:64910690c574	3646	*
AnnaBridge	145:64910690c574	3647	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3648	* @retval None
AnnaBridge	145:64910690c574	3649	*/
AnnaBridge	145:64910690c574	3650	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	3651	{
AnnaBridge	145:64910690c574	3652	MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
AnnaBridge	145:64910690c574	3653	}
AnnaBridge	145:64910690c574	3654
AnnaBridge	145:64910690c574	3655	/**
AnnaBridge	145:64910690c574	3656	* @brief Configure DFSDM Kernel clock source
AnnaBridge	145:64910690c574	3657	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	145:64910690c574	3658	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3659	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	145:64910690c574	3660	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3661	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
AnnaBridge	145:64910690c574	3662	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
AnnaBridge	145:64910690c574	3663	*
AnnaBridge	145:64910690c574	3664	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3665	* @retval None
AnnaBridge	145:64910690c574	3666	*/
AnnaBridge	145:64910690c574	3667	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	3668	{
AnnaBridge	145:64910690c574	3669	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
AnnaBridge	145:64910690c574	3670	}
AnnaBridge	145:64910690c574	3671	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	3672
AnnaBridge	145:64910690c574	3673	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	3674	/**
AnnaBridge	145:64910690c574	3675	* @brief Configure SPDIFRX clock source
AnnaBridge	145:64910690c574	3676	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
AnnaBridge	145:64910690c574	3677	* @param SPDIFRXxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3678	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3679	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
AnnaBridge	145:64910690c574	3680	*
AnnaBridge	145:64910690c574	3681	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3682	* @retval None
AnnaBridge	145:64910690c574	3683	*/
AnnaBridge	145:64910690c574	3684	__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
AnnaBridge	145:64910690c574	3685	{
AnnaBridge	145:64910690c574	3686	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
AnnaBridge	145:64910690c574	3687	}
AnnaBridge	145:64910690c574	3688	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	3689
AnnaBridge	145:64910690c574	3690	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	3691	/**
AnnaBridge	145:64910690c574	3692	* @brief Get FMPI2C clock source
AnnaBridge	145:64910690c574	3693	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
AnnaBridge	145:64910690c574	3694	* @param FMPI2Cx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3695	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
AnnaBridge	145:64910690c574	3696	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3697	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
AnnaBridge	145:64910690c574	3698	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3699	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	3700	*/
AnnaBridge	145:64910690c574	3701	__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
AnnaBridge	145:64910690c574	3702	{
AnnaBridge	145:64910690c574	3703	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
AnnaBridge	145:64910690c574	3704	}
AnnaBridge	145:64910690c574	3705	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	3706
AnnaBridge	145:64910690c574	3707	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	3708	/**
AnnaBridge	145:64910690c574	3709	* @brief Get LPTIMx clock source
AnnaBridge	145:64910690c574	3710	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
AnnaBridge	145:64910690c574	3711	* @param LPTIMx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3712	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	145:64910690c574	3713	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3714	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	145:64910690c574	3715	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	3716	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	3717	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	3718	*/
AnnaBridge	145:64910690c574	3719	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
AnnaBridge	145:64910690c574	3720	{
AnnaBridge	145:64910690c574	3721	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
AnnaBridge	145:64910690c574	3722	}
AnnaBridge	145:64910690c574	3723	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	3724
AnnaBridge	145:64910690c574	3725	#if defined(SAI1)
AnnaBridge	145:64910690c574	3726	/**
AnnaBridge	145:64910690c574	3727	* @brief Get SAIx clock source
AnnaBridge	145:64910690c574	3728	* @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
AnnaBridge	145:64910690c574	3729	* DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
AnnaBridge	145:64910690c574	3730	* DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
AnnaBridge	145:64910690c574	3731	* DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
AnnaBridge	145:64910690c574	3732	* @param SAIx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3733	* @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3734	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3735	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3736	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3737	*
AnnaBridge	145:64910690c574	3738	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3739	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3740	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3741	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3742	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3743	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3744	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3745	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3746	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3747	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3748	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3749	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3750	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3751	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3752	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3753	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3754	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3755	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3756	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3757	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3758	*
AnnaBridge	145:64910690c574	3759	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3760	*/
AnnaBridge	145:64910690c574	3761	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
AnnaBridge	145:64910690c574	3762	{
AnnaBridge	145:64910690c574	3763	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U \| SAIx);
AnnaBridge	145:64910690c574	3764	}
AnnaBridge	145:64910690c574	3765	#endif /* SAI1 */
AnnaBridge	145:64910690c574	3766
AnnaBridge	145:64910690c574	3767	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	145:64910690c574	3768	/**
AnnaBridge	145:64910690c574	3769	* @brief Get SDIOx clock source
AnnaBridge	145:64910690c574	3770	* @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
AnnaBridge	145:64910690c574	3771	* DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
AnnaBridge	145:64910690c574	3772	* @param SDIOx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3773	* @arg @ref LL_RCC_SDIO_CLKSOURCE
AnnaBridge	145:64910690c574	3774	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3775	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
AnnaBridge	145:64910690c574	3776	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3777	*/
AnnaBridge	145:64910690c574	3778	__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
AnnaBridge	145:64910690c574	3779	{
AnnaBridge	145:64910690c574	3780	#if defined(RCC_DCKCFGR_SDIOSEL)
AnnaBridge	145:64910690c574	3781	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
AnnaBridge	145:64910690c574	3782	#else
AnnaBridge	145:64910690c574	3783	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
AnnaBridge	145:64910690c574	3784	#endif /* RCC_DCKCFGR_SDIOSEL */
AnnaBridge	145:64910690c574	3785	}
AnnaBridge	145:64910690c574	3786	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
AnnaBridge	145:64910690c574	3787
AnnaBridge	145:64910690c574	3788	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	145:64910690c574	3789	/**
AnnaBridge	145:64910690c574	3790	* @brief Get 48Mhz domain clock source
AnnaBridge	145:64910690c574	3791	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
AnnaBridge	145:64910690c574	3792	* DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
AnnaBridge	145:64910690c574	3793	* @param CK48Mx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3794	* @arg @ref LL_RCC_CK48M_CLKSOURCE
AnnaBridge	145:64910690c574	3795	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3796	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3797	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3798	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3799	*
AnnaBridge	145:64910690c574	3800	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3801	*/
AnnaBridge	145:64910690c574	3802	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
AnnaBridge	145:64910690c574	3803	{
AnnaBridge	145:64910690c574	3804	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3805	return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
AnnaBridge	145:64910690c574	3806	#else
AnnaBridge	145:64910690c574	3807	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
AnnaBridge	145:64910690c574	3808	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3809	}
AnnaBridge	145:64910690c574	3810
AnnaBridge	145:64910690c574	3811	#if defined(RNG)
AnnaBridge	145:64910690c574	3812	/**
AnnaBridge	145:64910690c574	3813	* @brief Get RNGx clock source
AnnaBridge	145:64910690c574	3814	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
AnnaBridge	145:64910690c574	3815	* DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
AnnaBridge	145:64910690c574	3816	* @param RNGx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3817	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	145:64910690c574	3818	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3819	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3820	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3821	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3822	*
AnnaBridge	145:64910690c574	3823	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3824	*/
AnnaBridge	145:64910690c574	3825	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
AnnaBridge	145:64910690c574	3826	{
AnnaBridge	145:64910690c574	3827	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3828	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
AnnaBridge	145:64910690c574	3829	#else
AnnaBridge	145:64910690c574	3830	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
AnnaBridge	145:64910690c574	3831	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3832	}
AnnaBridge	145:64910690c574	3833	#endif /* RNG */
AnnaBridge	145:64910690c574	3834
AnnaBridge	145:64910690c574	3835	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	3836	/**
AnnaBridge	145:64910690c574	3837	* @brief Get USBx clock source
AnnaBridge	145:64910690c574	3838	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
AnnaBridge	145:64910690c574	3839	* DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
AnnaBridge	145:64910690c574	3840	* @param USBx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3841	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	145:64910690c574	3842	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3843	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3844	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
AnnaBridge	145:64910690c574	3845	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3846	*
AnnaBridge	145:64910690c574	3847	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3848	*/
AnnaBridge	145:64910690c574	3849	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	145:64910690c574	3850	{
AnnaBridge	145:64910690c574	3851	#if defined(RCC_DCKCFGR_CK48MSEL)
AnnaBridge	145:64910690c574	3852	return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
AnnaBridge	145:64910690c574	3853	#else
AnnaBridge	145:64910690c574	3854	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
AnnaBridge	145:64910690c574	3855	#endif /* RCC_DCKCFGR_CK48MSEL */
AnnaBridge	145:64910690c574	3856	}
AnnaBridge	145:64910690c574	3857	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
AnnaBridge	145:64910690c574	3858	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
AnnaBridge	145:64910690c574	3859
AnnaBridge	145:64910690c574	3860	#if defined(CEC)
AnnaBridge	145:64910690c574	3861	/**
AnnaBridge	145:64910690c574	3862	* @brief Get CEC Clock Source
AnnaBridge	145:64910690c574	3863	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
AnnaBridge	145:64910690c574	3864	* @param CECx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3865	* @arg @ref LL_RCC_CEC_CLKSOURCE
AnnaBridge	145:64910690c574	3866	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3867	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
AnnaBridge	145:64910690c574	3868	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	3869	*/
AnnaBridge	145:64910690c574	3870	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
AnnaBridge	145:64910690c574	3871	{
AnnaBridge	145:64910690c574	3872	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
AnnaBridge	145:64910690c574	3873	}
AnnaBridge	145:64910690c574	3874	#endif /* CEC */
AnnaBridge	145:64910690c574	3875
AnnaBridge	145:64910690c574	3876	/**
AnnaBridge	145:64910690c574	3877	* @brief Get I2S Clock Source
AnnaBridge	145:64910690c574	3878	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
AnnaBridge	145:64910690c574	3879	* DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
AnnaBridge	145:64910690c574	3880	* DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
AnnaBridge	145:64910690c574	3881	* DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
AnnaBridge	145:64910690c574	3882	* @param I2Sx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3883	* @arg @ref LL_RCC_I2S1_CLKSOURCE
AnnaBridge	145:64910690c574	3884	* @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3885	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3886	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3887	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	145:64910690c574	3888	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3889	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3890	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
AnnaBridge	145:64910690c574	3891	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
AnnaBridge	145:64910690c574	3892	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
AnnaBridge	145:64910690c574	3893	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
AnnaBridge	145:64910690c574	3894	*
AnnaBridge	145:64910690c574	3895	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3896	*/
AnnaBridge	145:64910690c574	3897	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
AnnaBridge	145:64910690c574	3898	{
AnnaBridge	145:64910690c574	3899	#if defined(RCC_CFGR_I2SSRC)
AnnaBridge	145:64910690c574	3900	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
AnnaBridge	145:64910690c574	3901	#else
AnnaBridge	145:64910690c574	3902	return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U \| I2Sx);
AnnaBridge	145:64910690c574	3903	#endif /* RCC_CFGR_I2SSRC */
AnnaBridge	145:64910690c574	3904	}
AnnaBridge	145:64910690c574	3905
AnnaBridge	145:64910690c574	3906	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	3907	/**
AnnaBridge	145:64910690c574	3908	* @brief Get DFSDM Audio Clock Source
AnnaBridge	145:64910690c574	3909	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
AnnaBridge	145:64910690c574	3910	* DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
AnnaBridge	145:64910690c574	3911	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3912	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
AnnaBridge	145:64910690c574	3913	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3914	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3915	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
AnnaBridge	145:64910690c574	3916	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
AnnaBridge	145:64910690c574	3917	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
AnnaBridge	145:64910690c574	3918	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
AnnaBridge	145:64910690c574	3919	*
AnnaBridge	145:64910690c574	3920	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3921	*/
AnnaBridge	145:64910690c574	3922	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
AnnaBridge	145:64910690c574	3923	{
AnnaBridge	145:64910690c574	3924	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U \| DFSDMx);
AnnaBridge	145:64910690c574	3925	}
AnnaBridge	145:64910690c574	3926
AnnaBridge	145:64910690c574	3927	/**
AnnaBridge	145:64910690c574	3928	* @brief Get DFSDM Audio Clock Source
AnnaBridge	145:64910690c574	3929	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	145:64910690c574	3930	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3931	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	145:64910690c574	3932	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
AnnaBridge	145:64910690c574	3933	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3934	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	145:64910690c574	3935	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	145:64910690c574	3936	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
AnnaBridge	145:64910690c574	3937	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
AnnaBridge	145:64910690c574	3938	*
AnnaBridge	145:64910690c574	3939	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3940	*/
AnnaBridge	145:64910690c574	3941	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
AnnaBridge	145:64910690c574	3942	{
AnnaBridge	145:64910690c574	3943	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
AnnaBridge	145:64910690c574	3944	}
AnnaBridge	145:64910690c574	3945	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	3946
AnnaBridge	145:64910690c574	3947	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	3948	/**
AnnaBridge	145:64910690c574	3949	* @brief Get SPDIFRX clock source
AnnaBridge	145:64910690c574	3950	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
AnnaBridge	145:64910690c574	3951	* @param SPDIFRXx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3952	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
AnnaBridge	145:64910690c574	3953	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3954	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3955	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
AnnaBridge	145:64910690c574	3956	*
AnnaBridge	145:64910690c574	3957	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	3958	*/
AnnaBridge	145:64910690c574	3959	__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
AnnaBridge	145:64910690c574	3960	{
AnnaBridge	145:64910690c574	3961	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
AnnaBridge	145:64910690c574	3962	}
AnnaBridge	145:64910690c574	3963	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	3964
AnnaBridge	145:64910690c574	3965	#if defined(DSI)
AnnaBridge	145:64910690c574	3966	/**
AnnaBridge	145:64910690c574	3967	* @brief Get DSI Clock Source
AnnaBridge	145:64910690c574	3968	* @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
AnnaBridge	145:64910690c574	3969	* @param DSIx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3970	* @arg @ref LL_RCC_DSI_CLKSOURCE
AnnaBridge	145:64910690c574	3971	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	3972	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	145:64910690c574	3973	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	3974	*/
AnnaBridge	145:64910690c574	3975	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
AnnaBridge	145:64910690c574	3976	{
AnnaBridge	145:64910690c574	3977	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
AnnaBridge	145:64910690c574	3978	}
AnnaBridge	145:64910690c574	3979	#endif /* DSI */
AnnaBridge	145:64910690c574	3980
AnnaBridge	145:64910690c574	3981	/**
AnnaBridge	145:64910690c574	3982	* @}
AnnaBridge	145:64910690c574	3983	*/
AnnaBridge	145:64910690c574	3984
AnnaBridge	145:64910690c574	3985	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	145:64910690c574	3986	* @{
AnnaBridge	145:64910690c574	3987	*/
AnnaBridge	145:64910690c574	3988
AnnaBridge	145:64910690c574	3989	/**
AnnaBridge	145:64910690c574	3990	* @brief Set RTC Clock Source
AnnaBridge	145:64910690c574	3991	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	145:64910690c574	3992	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	145:64910690c574	3993	* set). The BDRST bit can be used to reset them.
AnnaBridge	145:64910690c574	3994	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	145:64910690c574	3995	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	3996	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	145:64910690c574	3997	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	3998	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	3999	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	4000	* @retval None
AnnaBridge	145:64910690c574	4001	*/
AnnaBridge	145:64910690c574	4002	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	4003	{
AnnaBridge	145:64910690c574	4004	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	145:64910690c574	4005	}
AnnaBridge	145:64910690c574	4006
AnnaBridge	145:64910690c574	4007	/**
AnnaBridge	145:64910690c574	4008	* @brief Get RTC Clock Source
AnnaBridge	145:64910690c574	4009	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	145:64910690c574	4010	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4011	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	145:64910690c574	4012	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	4013	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	4014	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	4015	*/
AnnaBridge	145:64910690c574	4016	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	145:64910690c574	4017	{
AnnaBridge	145:64910690c574	4018	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	145:64910690c574	4019	}
AnnaBridge	145:64910690c574	4020
AnnaBridge	145:64910690c574	4021	/**
AnnaBridge	145:64910690c574	4022	* @brief Enable RTC
AnnaBridge	145:64910690c574	4023	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	145:64910690c574	4024	* @retval None
AnnaBridge	145:64910690c574	4025	*/
AnnaBridge	145:64910690c574	4026	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	145:64910690c574	4027	{
AnnaBridge	145:64910690c574	4028	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	145:64910690c574	4029	}
AnnaBridge	145:64910690c574	4030
AnnaBridge	145:64910690c574	4031	/**
AnnaBridge	145:64910690c574	4032	* @brief Disable RTC
AnnaBridge	145:64910690c574	4033	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	145:64910690c574	4034	* @retval None
AnnaBridge	145:64910690c574	4035	*/
AnnaBridge	145:64910690c574	4036	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	145:64910690c574	4037	{
AnnaBridge	145:64910690c574	4038	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	145:64910690c574	4039	}
AnnaBridge	145:64910690c574	4040
AnnaBridge	145:64910690c574	4041	/**
AnnaBridge	145:64910690c574	4042	* @brief Check if RTC has been enabled or not
AnnaBridge	145:64910690c574	4043	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	145:64910690c574	4044	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	4045	*/
AnnaBridge	145:64910690c574	4046	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	145:64910690c574	4047	{
AnnaBridge	145:64910690c574	4048	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	145:64910690c574	4049	}
AnnaBridge	145:64910690c574	4050
AnnaBridge	145:64910690c574	4051	/**
AnnaBridge	145:64910690c574	4052	* @brief Force the Backup domain reset
AnnaBridge	145:64910690c574	4053	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	145:64910690c574	4054	* @retval None
AnnaBridge	145:64910690c574	4055	*/
AnnaBridge	145:64910690c574	4056	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	145:64910690c574	4057	{
AnnaBridge	145:64910690c574	4058	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	145:64910690c574	4059	}
AnnaBridge	145:64910690c574	4060
AnnaBridge	145:64910690c574	4061	/**
AnnaBridge	145:64910690c574	4062	* @brief Release the Backup domain reset
AnnaBridge	145:64910690c574	4063	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	145:64910690c574	4064	* @retval None
AnnaBridge	145:64910690c574	4065	*/
AnnaBridge	145:64910690c574	4066	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	145:64910690c574	4067	{
AnnaBridge	145:64910690c574	4068	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	145:64910690c574	4069	}
AnnaBridge	145:64910690c574	4070
AnnaBridge	145:64910690c574	4071	/**
AnnaBridge	145:64910690c574	4072	* @brief Set HSE Prescalers for RTC Clock
AnnaBridge	145:64910690c574	4073	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	145:64910690c574	4074	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4075	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	145:64910690c574	4076	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	145:64910690c574	4077	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	145:64910690c574	4078	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	145:64910690c574	4079	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	145:64910690c574	4080	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	145:64910690c574	4081	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	145:64910690c574	4082	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	145:64910690c574	4083	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	145:64910690c574	4084	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	145:64910690c574	4085	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	145:64910690c574	4086	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	145:64910690c574	4087	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	145:64910690c574	4088	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	145:64910690c574	4089	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	145:64910690c574	4090	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	145:64910690c574	4091	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	145:64910690c574	4092	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	145:64910690c574	4093	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	145:64910690c574	4094	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	145:64910690c574	4095	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	145:64910690c574	4096	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	145:64910690c574	4097	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	145:64910690c574	4098	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	145:64910690c574	4099	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	145:64910690c574	4100	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	145:64910690c574	4101	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	145:64910690c574	4102	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	145:64910690c574	4103	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	145:64910690c574	4104	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	145:64910690c574	4105	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	145:64910690c574	4106	* @retval None
AnnaBridge	145:64910690c574	4107	*/
AnnaBridge	145:64910690c574	4108	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	4109	{
AnnaBridge	145:64910690c574	4110	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
AnnaBridge	145:64910690c574	4111	}
AnnaBridge	145:64910690c574	4112
AnnaBridge	145:64910690c574	4113	/**
AnnaBridge	145:64910690c574	4114	* @brief Get HSE Prescalers for RTC Clock
AnnaBridge	145:64910690c574	4115	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	145:64910690c574	4116	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4117	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	145:64910690c574	4118	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	145:64910690c574	4119	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	145:64910690c574	4120	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	145:64910690c574	4121	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	145:64910690c574	4122	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	145:64910690c574	4123	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	145:64910690c574	4124	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	145:64910690c574	4125	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	145:64910690c574	4126	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	145:64910690c574	4127	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	145:64910690c574	4128	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	145:64910690c574	4129	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	145:64910690c574	4130	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	145:64910690c574	4131	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	145:64910690c574	4132	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	145:64910690c574	4133	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	145:64910690c574	4134	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	145:64910690c574	4135	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	145:64910690c574	4136	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	145:64910690c574	4137	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	145:64910690c574	4138	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	145:64910690c574	4139	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	145:64910690c574	4140	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	145:64910690c574	4141	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	145:64910690c574	4142	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	145:64910690c574	4143	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	145:64910690c574	4144	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	145:64910690c574	4145	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	145:64910690c574	4146	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	145:64910690c574	4147	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	145:64910690c574	4148	*/
AnnaBridge	145:64910690c574	4149	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	145:64910690c574	4150	{
AnnaBridge	145:64910690c574	4151	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
AnnaBridge	145:64910690c574	4152	}
AnnaBridge	145:64910690c574	4153
AnnaBridge	145:64910690c574	4154	/**
AnnaBridge	145:64910690c574	4155	* @}
AnnaBridge	145:64910690c574	4156	*/
AnnaBridge	145:64910690c574	4157
AnnaBridge	145:64910690c574	4158	#if defined(RCC_DCKCFGR_TIMPRE)
AnnaBridge	145:64910690c574	4159	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
AnnaBridge	145:64910690c574	4160	* @{
AnnaBridge	145:64910690c574	4161	*/
AnnaBridge	145:64910690c574	4162
AnnaBridge	145:64910690c574	4163	/**
AnnaBridge	145:64910690c574	4164	* @brief Set Timers Clock Prescalers
AnnaBridge	145:64910690c574	4165	* @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
AnnaBridge	145:64910690c574	4166	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4167	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	145:64910690c574	4168	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	145:64910690c574	4169	* @retval None
AnnaBridge	145:64910690c574	4170	*/
AnnaBridge	145:64910690c574	4171	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	4172	{
AnnaBridge	145:64910690c574	4173	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
AnnaBridge	145:64910690c574	4174	}
AnnaBridge	145:64910690c574	4175
AnnaBridge	145:64910690c574	4176	/**
AnnaBridge	145:64910690c574	4177	* @brief Get Timers Clock Prescalers
AnnaBridge	145:64910690c574	4178	* @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
AnnaBridge	145:64910690c574	4179	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4180	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	145:64910690c574	4181	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	145:64910690c574	4182	*/
AnnaBridge	145:64910690c574	4183	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
AnnaBridge	145:64910690c574	4184	{
AnnaBridge	145:64910690c574	4185	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
AnnaBridge	145:64910690c574	4186	}
AnnaBridge	145:64910690c574	4187
AnnaBridge	145:64910690c574	4188	/**
AnnaBridge	145:64910690c574	4189	* @}
AnnaBridge	145:64910690c574	4190	*/
AnnaBridge	145:64910690c574	4191	#endif /* RCC_DCKCFGR_TIMPRE */
AnnaBridge	145:64910690c574	4192
AnnaBridge	145:64910690c574	4193	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	145:64910690c574	4194	* @{
AnnaBridge	145:64910690c574	4195	*/
AnnaBridge	145:64910690c574	4196
AnnaBridge	145:64910690c574	4197	/**
AnnaBridge	145:64910690c574	4198	* @brief Enable PLL
AnnaBridge	145:64910690c574	4199	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	145:64910690c574	4200	* @retval None
AnnaBridge	145:64910690c574	4201	*/
AnnaBridge	145:64910690c574	4202	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	145:64910690c574	4203	{
AnnaBridge	145:64910690c574	4204	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	145:64910690c574	4205	}
AnnaBridge	145:64910690c574	4206
AnnaBridge	145:64910690c574	4207	/**
AnnaBridge	145:64910690c574	4208	* @brief Disable PLL
AnnaBridge	145:64910690c574	4209	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	145:64910690c574	4210	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	145:64910690c574	4211	* @retval None
AnnaBridge	145:64910690c574	4212	*/
AnnaBridge	145:64910690c574	4213	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	145:64910690c574	4214	{
AnnaBridge	145:64910690c574	4215	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	145:64910690c574	4216	}
AnnaBridge	145:64910690c574	4217
AnnaBridge	145:64910690c574	4218	/**
AnnaBridge	145:64910690c574	4219	* @brief Check if PLL Ready
AnnaBridge	145:64910690c574	4220	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	145:64910690c574	4221	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	4222	*/
AnnaBridge	145:64910690c574	4223	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	145:64910690c574	4224	{
AnnaBridge	145:64910690c574	4225	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	145:64910690c574	4226	}
AnnaBridge	145:64910690c574	4227
AnnaBridge	145:64910690c574	4228	/**
AnnaBridge	145:64910690c574	4229	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	145:64910690c574	4230	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4231	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	4232	* @note PLLN/PLLP can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4233	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	4234	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	4235	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	4236	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	4237	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	145:64910690c574	4238	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4239	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4240	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4241	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4242	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4243	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4244	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4245	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4246	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4247	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4248	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4249	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4250	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4251	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4252	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4253	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4254	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4255	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4256	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4257	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4258	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4259	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4260	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4261	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4262	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4263	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4264	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4265	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4266	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4267	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4268	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4269	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4270	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4271	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4272	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4273	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4274	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4275	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4276	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4277	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4278	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4279	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4280	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4281	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4282	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4283	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4284	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4285	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4286	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4287	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4288	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4289	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4290	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4291	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4292	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4293	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4294	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4295	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4296	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4297	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4298	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4299	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4300	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4301	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4302	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4303	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4304	* @param PLLN Between 50/192(*) and 432
AnnaBridge	145:64910690c574	4305	*
AnnaBridge	145:64910690c574	4306	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	4307	* @param PLLP_R This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4308	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	4309	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	4310	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	4311	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	4312	* @arg @ref LL_RCC_PLLR_DIV_2 (*)
AnnaBridge	145:64910690c574	4313	* @arg @ref LL_RCC_PLLR_DIV_3 (*)
AnnaBridge	145:64910690c574	4314	* @arg @ref LL_RCC_PLLR_DIV_4 (*)
AnnaBridge	145:64910690c574	4315	* @arg @ref LL_RCC_PLLR_DIV_5 (*)
AnnaBridge	145:64910690c574	4316	* @arg @ref LL_RCC_PLLR_DIV_6 (*)
AnnaBridge	145:64910690c574	4317	* @arg @ref LL_RCC_PLLR_DIV_7 (*)
AnnaBridge	145:64910690c574	4318	*
AnnaBridge	145:64910690c574	4319	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	4320	* @retval None
AnnaBridge	145:64910690c574	4321	*/
AnnaBridge	145:64910690c574	4322	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
AnnaBridge	145:64910690c574	4323	{
AnnaBridge	145:64910690c574	4324	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN,
AnnaBridge	145:64910690c574	4325	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	145:64910690c574	4326	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
AnnaBridge	145:64910690c574	4327	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
AnnaBridge	145:64910690c574	4328	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
AnnaBridge	145:64910690c574	4329	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
AnnaBridge	145:64910690c574	4330	}
AnnaBridge	145:64910690c574	4331
AnnaBridge	145:64910690c574	4332	/**
AnnaBridge	145:64910690c574	4333	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	145:64910690c574	4334	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4335	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	4336	* @note PLLN/PLLQ can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4337	* @note This can be selected for USB, RNG, SDIO
AnnaBridge	145:64910690c574	4338	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	4339	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	4340	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	4341	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	145:64910690c574	4342	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4343	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4344	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4345	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4346	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4347	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4348	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4349	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4350	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4351	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4352	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4353	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4354	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4355	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4356	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4357	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4358	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4359	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4360	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4361	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4362	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4363	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4364	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4365	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4366	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4367	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4368	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4369	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4370	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4371	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4372	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4373	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4374	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4375	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4376	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4377	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4378	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4379	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4380	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4381	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4382	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4383	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4384	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4385	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4386	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4387	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4388	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4389	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4390	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4391	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4392	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4393	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4394	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4395	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4396	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4397	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4398	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4399	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4400	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4401	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4402	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4403	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4404	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4405	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4406	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4407	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4408	* @param PLLN Between 50/192(*) and 432
AnnaBridge	145:64910690c574	4409	*
AnnaBridge	145:64910690c574	4410	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	4411	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4412	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	4413	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	4414	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	4415	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	4416	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	4417	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	4418	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	4419	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	4420	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	4421	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	4422	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	4423	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	4424	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	4425	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	4426	* @retval None
AnnaBridge	145:64910690c574	4427	*/
AnnaBridge	145:64910690c574	4428	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	145:64910690c574	4429	{
AnnaBridge	145:64910690c574	4430	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	145:64910690c574	4431	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	145:64910690c574	4432	}
AnnaBridge	145:64910690c574	4433
AnnaBridge	145:64910690c574	4434	#if defined(DSI)
AnnaBridge	145:64910690c574	4435	/**
AnnaBridge	145:64910690c574	4436	* @brief Configure PLL used for DSI clock
AnnaBridge	145:64910690c574	4437	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4438	* PLLI2S and PLLSAI are disabled
AnnaBridge	145:64910690c574	4439	* @note PLLN/PLLR can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4440	* @note This can be selected for DSI
AnnaBridge	145:64910690c574	4441	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	145:64910690c574	4442	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	145:64910690c574	4443	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	145:64910690c574	4444	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
AnnaBridge	145:64910690c574	4445	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4446	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4447	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4448	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4449	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4450	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4451	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4452	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4453	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4454	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4455	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4456	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4457	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4458	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4459	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4460	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4461	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4462	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4463	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4464	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4465	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4466	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4467	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4468	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4469	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4470	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4471	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4472	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4473	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4474	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4475	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4476	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4477	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4478	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4479	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4480	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4481	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4482	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4483	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4484	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4485	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4486	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4487	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4488	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4489	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4490	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4491	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4492	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4493	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4494	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4495	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4496	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4497	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4498	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4499	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4500	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4501	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4502	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4503	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4504	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4505	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4506	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4507	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4508	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4509	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4510	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4511	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	4512	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4513	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	4514	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	4515	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	4516	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	4517	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	4518	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	4519	* @retval None
AnnaBridge	145:64910690c574	4520	*/
AnnaBridge	145:64910690c574	4521	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	4522	{
AnnaBridge	145:64910690c574	4523	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	145:64910690c574	4524	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	145:64910690c574	4525	}
AnnaBridge	145:64910690c574	4526	#endif /* DSI */
AnnaBridge	145:64910690c574	4527
AnnaBridge	145:64910690c574	4528	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
AnnaBridge	145:64910690c574	4529	/**
AnnaBridge	145:64910690c574	4530	* @brief Configure PLL used for I2S clock
AnnaBridge	145:64910690c574	4531	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4532	* PLLI2S and PLLSAI are disabled
AnnaBridge	145:64910690c574	4533	* @note PLLN/PLLR can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4534	* @note This can be selected for I2S
AnnaBridge	145:64910690c574	4535	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	4536	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	4537	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	4538	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
AnnaBridge	145:64910690c574	4539	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4540	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4541	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4542	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4543	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4544	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4545	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4546	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4547	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4548	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4549	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4550	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4551	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4552	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4553	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4554	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4555	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4556	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4557	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4558	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4559	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4560	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4561	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4562	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4563	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4564	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4565	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4566	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4567	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4568	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4569	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4570	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4571	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4572	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4573	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4574	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4575	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4576	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4577	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4578	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4579	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4580	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4581	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4582	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4583	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4584	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4585	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4586	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4587	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4588	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4589	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4590	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4591	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4592	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4593	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4594	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4595	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4596	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4597	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4598	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4599	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4600	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4601	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4602	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4603	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4604	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4605	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	4606	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4607	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	4608	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	4609	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	4610	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	4611	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	4612	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	4613	* @retval None
AnnaBridge	145:64910690c574	4614	*/
AnnaBridge	145:64910690c574	4615	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	4616	{
AnnaBridge	145:64910690c574	4617	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	145:64910690c574	4618	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	145:64910690c574	4619	}
AnnaBridge	145:64910690c574	4620	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
AnnaBridge	145:64910690c574	4621
AnnaBridge	145:64910690c574	4622	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	4623	/**
AnnaBridge	145:64910690c574	4624	* @brief Configure PLL used for SPDIFRX clock
AnnaBridge	145:64910690c574	4625	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4626	* PLLI2S and PLLSAI are disabled
AnnaBridge	145:64910690c574	4627	* @note PLLN/PLLR can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4628	* @note This can be selected for SPDIFRX
AnnaBridge	145:64910690c574	4629	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	4630	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	4631	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	4632	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
AnnaBridge	145:64910690c574	4633	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4634	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4635	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4636	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4637	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4638	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4639	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4640	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4641	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4642	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4643	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4644	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4645	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4646	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4647	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4648	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4649	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4650	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4651	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4652	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4653	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4654	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4655	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4656	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4657	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4658	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4659	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4660	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4661	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4662	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4663	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4664	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4665	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4666	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4667	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4668	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4669	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4670	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4671	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4672	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4673	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4674	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4675	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4676	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4677	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4678	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4679	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4680	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4681	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4682	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4683	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4684	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4685	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4686	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4687	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4688	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4689	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4690	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4691	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4692	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4693	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4694	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4695	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4696	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4697	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4698	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4699	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	4700	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4701	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	4702	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	4703	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	4704	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	4705	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	4706	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	4707	* @retval None
AnnaBridge	145:64910690c574	4708	*/
AnnaBridge	145:64910690c574	4709	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	4710	{
AnnaBridge	145:64910690c574	4711	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	145:64910690c574	4712	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	145:64910690c574	4713	}
AnnaBridge	145:64910690c574	4714	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	4715
AnnaBridge	145:64910690c574	4716	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	145:64910690c574	4717	#if defined(SAI1)
AnnaBridge	145:64910690c574	4718	/**
AnnaBridge	145:64910690c574	4719	* @brief Configure PLL used for SAI clock
AnnaBridge	145:64910690c574	4720	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	4721	* PLLI2S and PLLSAI are disabled
AnnaBridge	145:64910690c574	4722	* @note PLLN/PLLR can be written only when PLL is disabled
AnnaBridge	145:64910690c574	4723	* @note This can be selected for SAI
AnnaBridge	145:64910690c574	4724	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	4725	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	4726	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	4727	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	4728	* DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
AnnaBridge	145:64910690c574	4729	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4730	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	4731	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	4732	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4733	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4734	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4735	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	4736	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	4737	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	4738	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	4739	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	4740	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	4741	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	4742	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	4743	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	4744	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	4745	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	4746	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	4747	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	4748	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	4749	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	4750	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	4751	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	4752	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	4753	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	4754	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	4755	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	4756	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	4757	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	4758	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	4759	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	4760	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	4761	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	4762	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	4763	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	4764	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	4765	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	4766	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	4767	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	4768	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	4769	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	4770	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	4771	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	4772	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	4773	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	4774	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	4775	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	4776	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	4777	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	4778	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	4779	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	4780	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	4781	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	4782	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	4783	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	4784	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	4785	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	4786	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	4787	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	4788	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	4789	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	4790	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	4791	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	4792	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	4793	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	4794	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	4795	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	4796	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4797	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	4798	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	4799	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	4800	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	4801	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	4802	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	4803	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	4804	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
AnnaBridge	145:64910690c574	4805	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
AnnaBridge	145:64910690c574	4806	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
AnnaBridge	145:64910690c574	4807	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
AnnaBridge	145:64910690c574	4808	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
AnnaBridge	145:64910690c574	4809	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
AnnaBridge	145:64910690c574	4810	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
AnnaBridge	145:64910690c574	4811	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
AnnaBridge	145:64910690c574	4812	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
AnnaBridge	145:64910690c574	4813	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
AnnaBridge	145:64910690c574	4814	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
AnnaBridge	145:64910690c574	4815	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
AnnaBridge	145:64910690c574	4816	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
AnnaBridge	145:64910690c574	4817	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
AnnaBridge	145:64910690c574	4818	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
AnnaBridge	145:64910690c574	4819	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
AnnaBridge	145:64910690c574	4820	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
AnnaBridge	145:64910690c574	4821	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
AnnaBridge	145:64910690c574	4822	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
AnnaBridge	145:64910690c574	4823	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
AnnaBridge	145:64910690c574	4824	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
AnnaBridge	145:64910690c574	4825	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
AnnaBridge	145:64910690c574	4826	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
AnnaBridge	145:64910690c574	4827	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
AnnaBridge	145:64910690c574	4828	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
AnnaBridge	145:64910690c574	4829	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
AnnaBridge	145:64910690c574	4830	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
AnnaBridge	145:64910690c574	4831	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
AnnaBridge	145:64910690c574	4832	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
AnnaBridge	145:64910690c574	4833	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
AnnaBridge	145:64910690c574	4834	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
AnnaBridge	145:64910690c574	4835	*
AnnaBridge	145:64910690c574	4836	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	4837	* @retval None
AnnaBridge	145:64910690c574	4838	*/
AnnaBridge	145:64910690c574	4839	#if defined(RCC_DCKCFGR_PLLDIVR)
AnnaBridge	145:64910690c574	4840	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	145:64910690c574	4841	#else
AnnaBridge	145:64910690c574	4842	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	4843	#endif /* RCC_DCKCFGR_PLLDIVR */
AnnaBridge	145:64910690c574	4844	{
AnnaBridge	145:64910690c574	4845	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	145:64910690c574	4846	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	145:64910690c574	4847	#if defined(RCC_DCKCFGR_PLLDIVR)
AnnaBridge	145:64910690c574	4848	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
AnnaBridge	145:64910690c574	4849	#endif /* RCC_DCKCFGR_PLLDIVR */
AnnaBridge	145:64910690c574	4850	}
AnnaBridge	145:64910690c574	4851	#endif /* SAI1 */
AnnaBridge	145:64910690c574	4852	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	145:64910690c574	4853
AnnaBridge	145:64910690c574	4854	/**
AnnaBridge	163:e59c8e839560	4855	* @brief Configure PLL clock source
AnnaBridge	163:e59c8e839560	4856	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
AnnaBridge	163:e59c8e839560	4857	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	4858	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	163:e59c8e839560	4859	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	163:e59c8e839560	4860	* @retval None
AnnaBridge	163:e59c8e839560	4861	*/
AnnaBridge	163:e59c8e839560	4862	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	163:e59c8e839560	4863	{
AnnaBridge	163:e59c8e839560	4864	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
AnnaBridge	163:e59c8e839560	4865	}
AnnaBridge	163:e59c8e839560	4866
AnnaBridge	163:e59c8e839560	4867	/**
AnnaBridge	163:e59c8e839560	4868	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	163:e59c8e839560	4869	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	163:e59c8e839560	4870	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	4871	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	163:e59c8e839560	4872	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	163:e59c8e839560	4873	*/
AnnaBridge	163:e59c8e839560	4874	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	163:e59c8e839560	4875	{
AnnaBridge	163:e59c8e839560	4876	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	163:e59c8e839560	4877	}
AnnaBridge	163:e59c8e839560	4878
AnnaBridge	163:e59c8e839560	4879	/**
AnnaBridge	145:64910690c574	4880	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	145:64910690c574	4881	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	145:64910690c574	4882	* @retval Between 50/192(*) and 432
AnnaBridge	145:64910690c574	4883	*
AnnaBridge	145:64910690c574	4884	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	4885	*/
AnnaBridge	145:64910690c574	4886	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	145:64910690c574	4887	{
AnnaBridge	145:64910690c574	4888	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	145:64910690c574	4889	}
AnnaBridge	145:64910690c574	4890
AnnaBridge	145:64910690c574	4891	/**
AnnaBridge	145:64910690c574	4892	* @brief Get Main PLL division factor for PLLP
AnnaBridge	145:64910690c574	4893	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	145:64910690c574	4894	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4895	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	4896	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	4897	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	4898	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	4899	*/
AnnaBridge	145:64910690c574	4900	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	145:64910690c574	4901	{
AnnaBridge	145:64910690c574	4902	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	145:64910690c574	4903	}
AnnaBridge	145:64910690c574	4904
AnnaBridge	145:64910690c574	4905	/**
AnnaBridge	145:64910690c574	4906	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	145:64910690c574	4907	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
AnnaBridge	145:64910690c574	4908	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	145:64910690c574	4909	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4910	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	4911	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	4912	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	4913	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	4914	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	4915	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	4916	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	4917	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	4918	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	4919	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	4920	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	4921	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	4922	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	4923	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	4924	*/
AnnaBridge	145:64910690c574	4925	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	145:64910690c574	4926	{
AnnaBridge	145:64910690c574	4927	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	145:64910690c574	4928	}
AnnaBridge	145:64910690c574	4929
AnnaBridge	145:64910690c574	4930	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	145:64910690c574	4931	/**
AnnaBridge	145:64910690c574	4932	* @brief Get Main PLL division factor for PLLR
AnnaBridge	145:64910690c574	4933	* @note used for PLLCLK (system clock)
AnnaBridge	145:64910690c574	4934	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
AnnaBridge	145:64910690c574	4935	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4936	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	145:64910690c574	4937	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	145:64910690c574	4938	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	145:64910690c574	4939	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	145:64910690c574	4940	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	145:64910690c574	4941	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	145:64910690c574	4942	*/
AnnaBridge	145:64910690c574	4943	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
AnnaBridge	145:64910690c574	4944	{
AnnaBridge	145:64910690c574	4945	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
AnnaBridge	145:64910690c574	4946	}
AnnaBridge	145:64910690c574	4947	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	145:64910690c574	4948
AnnaBridge	145:64910690c574	4949	#if defined(RCC_DCKCFGR_PLLDIVR)
AnnaBridge	145:64910690c574	4950	/**
AnnaBridge	145:64910690c574	4951	* @brief Get Main PLL division factor for PLLDIVR
AnnaBridge	145:64910690c574	4952	* @note used for PLLSAICLK (SAI1 and SAI2 clock)
AnnaBridge	145:64910690c574	4953	* @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
AnnaBridge	145:64910690c574	4954	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4955	* @arg @ref LL_RCC_PLLDIVR_DIV_1
AnnaBridge	145:64910690c574	4956	* @arg @ref LL_RCC_PLLDIVR_DIV_2
AnnaBridge	145:64910690c574	4957	* @arg @ref LL_RCC_PLLDIVR_DIV_3
AnnaBridge	145:64910690c574	4958	* @arg @ref LL_RCC_PLLDIVR_DIV_4
AnnaBridge	145:64910690c574	4959	* @arg @ref LL_RCC_PLLDIVR_DIV_5
AnnaBridge	145:64910690c574	4960	* @arg @ref LL_RCC_PLLDIVR_DIV_6
AnnaBridge	145:64910690c574	4961	* @arg @ref LL_RCC_PLLDIVR_DIV_7
AnnaBridge	145:64910690c574	4962	* @arg @ref LL_RCC_PLLDIVR_DIV_8
AnnaBridge	145:64910690c574	4963	* @arg @ref LL_RCC_PLLDIVR_DIV_9
AnnaBridge	145:64910690c574	4964	* @arg @ref LL_RCC_PLLDIVR_DIV_10
AnnaBridge	145:64910690c574	4965	* @arg @ref LL_RCC_PLLDIVR_DIV_11
AnnaBridge	145:64910690c574	4966	* @arg @ref LL_RCC_PLLDIVR_DIV_12
AnnaBridge	145:64910690c574	4967	* @arg @ref LL_RCC_PLLDIVR_DIV_13
AnnaBridge	145:64910690c574	4968	* @arg @ref LL_RCC_PLLDIVR_DIV_14
AnnaBridge	145:64910690c574	4969	* @arg @ref LL_RCC_PLLDIVR_DIV_15
AnnaBridge	145:64910690c574	4970	* @arg @ref LL_RCC_PLLDIVR_DIV_16
AnnaBridge	145:64910690c574	4971	* @arg @ref LL_RCC_PLLDIVR_DIV_17
AnnaBridge	145:64910690c574	4972	* @arg @ref LL_RCC_PLLDIVR_DIV_18
AnnaBridge	145:64910690c574	4973	* @arg @ref LL_RCC_PLLDIVR_DIV_19
AnnaBridge	145:64910690c574	4974	* @arg @ref LL_RCC_PLLDIVR_DIV_20
AnnaBridge	145:64910690c574	4975	* @arg @ref LL_RCC_PLLDIVR_DIV_21
AnnaBridge	145:64910690c574	4976	* @arg @ref LL_RCC_PLLDIVR_DIV_22
AnnaBridge	145:64910690c574	4977	* @arg @ref LL_RCC_PLLDIVR_DIV_23
AnnaBridge	145:64910690c574	4978	* @arg @ref LL_RCC_PLLDIVR_DIV_24
AnnaBridge	145:64910690c574	4979	* @arg @ref LL_RCC_PLLDIVR_DIV_25
AnnaBridge	145:64910690c574	4980	* @arg @ref LL_RCC_PLLDIVR_DIV_26
AnnaBridge	145:64910690c574	4981	* @arg @ref LL_RCC_PLLDIVR_DIV_27
AnnaBridge	145:64910690c574	4982	* @arg @ref LL_RCC_PLLDIVR_DIV_28
AnnaBridge	145:64910690c574	4983	* @arg @ref LL_RCC_PLLDIVR_DIV_29
AnnaBridge	145:64910690c574	4984	* @arg @ref LL_RCC_PLLDIVR_DIV_30
AnnaBridge	145:64910690c574	4985	* @arg @ref LL_RCC_PLLDIVR_DIV_31
AnnaBridge	145:64910690c574	4986	*/
AnnaBridge	145:64910690c574	4987	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
AnnaBridge	145:64910690c574	4988	{
AnnaBridge	145:64910690c574	4989	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
AnnaBridge	145:64910690c574	4990	}
AnnaBridge	145:64910690c574	4991	#endif /* RCC_DCKCFGR_PLLDIVR */
AnnaBridge	145:64910690c574	4992
AnnaBridge	145:64910690c574	4993	/**
AnnaBridge	145:64910690c574	4994	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	145:64910690c574	4995	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	145:64910690c574	4996	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	4997	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	4998	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	4999	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	5000	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	5001	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	5002	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	5003	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	5004	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	5005	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	5006	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	5007	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	5008	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	5009	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	5010	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	5011	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	5012	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	5013	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	5014	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	5015	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	5016	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	5017	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	5018	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	5019	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	5020	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	5021	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	5022	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	5023	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	5024	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	5025	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	5026	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	5027	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	5028	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	5029	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	5030	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	5031	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	5032	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	5033	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	5034	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	5035	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	5036	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	5037	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	5038	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	5039	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	5040	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	5041	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	5042	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	5043	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	5044	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	5045	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	5046	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	5047	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	5048	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	5049	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	5050	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	5051	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	5052	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	5053	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	5054	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	5055	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	5056	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	5057	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	5058	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	5059	*/
AnnaBridge	145:64910690c574	5060	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	145:64910690c574	5061	{
AnnaBridge	145:64910690c574	5062	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	145:64910690c574	5063	}
AnnaBridge	145:64910690c574	5064
AnnaBridge	145:64910690c574	5065	/**
AnnaBridge	145:64910690c574	5066	* @brief Configure Spread Spectrum used for PLL
AnnaBridge	145:64910690c574	5067	* @note These bits must be written before enabling PLL
AnnaBridge	145:64910690c574	5068	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	145:64910690c574	5069	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	145:64910690c574	5070	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
AnnaBridge	145:64910690c574	5071	* @param Mod Between Min_Data=0 and Max_Data=8191
AnnaBridge	145:64910690c574	5072	* @param Inc Between Min_Data=0 and Max_Data=32767
AnnaBridge	145:64910690c574	5073	* @param Sel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5074	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	145:64910690c574	5075	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	145:64910690c574	5076	* @retval None
AnnaBridge	145:64910690c574	5077	*/
AnnaBridge	145:64910690c574	5078	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
AnnaBridge	145:64910690c574	5079	{
AnnaBridge	145:64910690c574	5080	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
AnnaBridge	145:64910690c574	5081	}
AnnaBridge	145:64910690c574	5082
AnnaBridge	145:64910690c574	5083	/**
AnnaBridge	145:64910690c574	5084	* @brief Get Spread Spectrum Modulation Period for PLL
AnnaBridge	145:64910690c574	5085	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
AnnaBridge	145:64910690c574	5086	* @retval Between Min_Data=0 and Max_Data=8191
AnnaBridge	145:64910690c574	5087	*/
AnnaBridge	145:64910690c574	5088	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
AnnaBridge	145:64910690c574	5089	{
AnnaBridge	145:64910690c574	5090	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
AnnaBridge	145:64910690c574	5091	}
AnnaBridge	145:64910690c574	5092
AnnaBridge	145:64910690c574	5093	/**
AnnaBridge	145:64910690c574	5094	* @brief Get Spread Spectrum Incrementation Step for PLL
AnnaBridge	145:64910690c574	5095	* @note Must be written before enabling PLL
AnnaBridge	145:64910690c574	5096	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
AnnaBridge	145:64910690c574	5097	* @retval Between Min_Data=0 and Max_Data=32767
AnnaBridge	145:64910690c574	5098	*/
AnnaBridge	145:64910690c574	5099	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
AnnaBridge	145:64910690c574	5100	{
AnnaBridge	145:64910690c574	5101	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
AnnaBridge	145:64910690c574	5102	}
AnnaBridge	145:64910690c574	5103
AnnaBridge	145:64910690c574	5104	/**
AnnaBridge	145:64910690c574	5105	* @brief Get Spread Spectrum Selection for PLL
AnnaBridge	145:64910690c574	5106	* @note Must be written before enabling PLL
AnnaBridge	145:64910690c574	5107	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
AnnaBridge	145:64910690c574	5108	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5109	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	145:64910690c574	5110	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	145:64910690c574	5111	*/
AnnaBridge	145:64910690c574	5112	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
AnnaBridge	145:64910690c574	5113	{
AnnaBridge	145:64910690c574	5114	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
AnnaBridge	145:64910690c574	5115	}
AnnaBridge	145:64910690c574	5116
AnnaBridge	145:64910690c574	5117	/**
AnnaBridge	145:64910690c574	5118	* @brief Enable Spread Spectrum for PLL.
AnnaBridge	145:64910690c574	5119	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
AnnaBridge	145:64910690c574	5120	* @retval None
AnnaBridge	145:64910690c574	5121	*/
AnnaBridge	145:64910690c574	5122	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
AnnaBridge	145:64910690c574	5123	{
AnnaBridge	145:64910690c574	5124	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	145:64910690c574	5125	}
AnnaBridge	145:64910690c574	5126
AnnaBridge	145:64910690c574	5127	/**
AnnaBridge	145:64910690c574	5128	* @brief Disable Spread Spectrum for PLL.
AnnaBridge	145:64910690c574	5129	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
AnnaBridge	145:64910690c574	5130	* @retval None
AnnaBridge	145:64910690c574	5131	*/
AnnaBridge	145:64910690c574	5132	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
AnnaBridge	145:64910690c574	5133	{
AnnaBridge	145:64910690c574	5134	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	145:64910690c574	5135	}
AnnaBridge	145:64910690c574	5136
AnnaBridge	145:64910690c574	5137	/**
AnnaBridge	145:64910690c574	5138	* @}
AnnaBridge	145:64910690c574	5139	*/
AnnaBridge	145:64910690c574	5140
AnnaBridge	145:64910690c574	5141	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	5142	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
AnnaBridge	145:64910690c574	5143	* @{
AnnaBridge	145:64910690c574	5144	*/
AnnaBridge	145:64910690c574	5145
AnnaBridge	145:64910690c574	5146	/**
AnnaBridge	145:64910690c574	5147	* @brief Enable PLLI2S
AnnaBridge	145:64910690c574	5148	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
AnnaBridge	145:64910690c574	5149	* @retval None
AnnaBridge	145:64910690c574	5150	*/
AnnaBridge	145:64910690c574	5151	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
AnnaBridge	145:64910690c574	5152	{
AnnaBridge	145:64910690c574	5153	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	145:64910690c574	5154	}
AnnaBridge	145:64910690c574	5155
AnnaBridge	145:64910690c574	5156	/**
AnnaBridge	145:64910690c574	5157	* @brief Disable PLLI2S
AnnaBridge	145:64910690c574	5158	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
AnnaBridge	145:64910690c574	5159	* @retval None
AnnaBridge	145:64910690c574	5160	*/
AnnaBridge	145:64910690c574	5161	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
AnnaBridge	145:64910690c574	5162	{
AnnaBridge	145:64910690c574	5163	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	145:64910690c574	5164	}
AnnaBridge	145:64910690c574	5165
AnnaBridge	145:64910690c574	5166	/**
AnnaBridge	145:64910690c574	5167	* @brief Check if PLLI2S Ready
AnnaBridge	145:64910690c574	5168	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
AnnaBridge	145:64910690c574	5169	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	5170	*/
AnnaBridge	145:64910690c574	5171	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
AnnaBridge	145:64910690c574	5172	{
AnnaBridge	145:64910690c574	5173	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
AnnaBridge	145:64910690c574	5174	}
AnnaBridge	145:64910690c574	5175
AnnaBridge	145:64910690c574	5176	#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR))
AnnaBridge	145:64910690c574	5177	/**
AnnaBridge	145:64910690c574	5178	* @brief Configure PLLI2S used for SAI domain clock
AnnaBridge	145:64910690c574	5179	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	5180	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	5181	* @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
AnnaBridge	145:64910690c574	5182	* @note This can be selected for SAI
AnnaBridge	145:64910690c574	5183	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5184	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5185	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5186	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5187	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5188	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5189	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5190	* DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5191	* DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
AnnaBridge	145:64910690c574	5192	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5193	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	5194	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	5195	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
AnnaBridge	145:64910690c574	5196	*
AnnaBridge	145:64910690c574	5197	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5198	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5199	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	5200	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	5201	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	5202	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	5203	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	5204	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	5205	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	5206	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	5207	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	5208	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	5209	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	5210	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	5211	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	5212	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	5213	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	5214	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	5215	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	5216	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	5217	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	5218	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	5219	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	5220	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	5221	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	5222	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	5223	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	5224	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	5225	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	5226	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	5227	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	5228	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	5229	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	5230	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	5231	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	5232	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	5233	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	5234	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	5235	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	5236	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	5237	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	5238	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	5239	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	5240	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	5241	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	5242	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	5243	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	5244	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	5245	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	5246	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	5247	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	5248	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	5249	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	5250	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	5251	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	5252	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	5253	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	5254	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	5255	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	5256	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	5257	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	5258	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	5259	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	5260	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	5261	* @param PLLN Between 50/192(*) and 432
AnnaBridge	145:64910690c574	5262	*
AnnaBridge	145:64910690c574	5263	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5264	* @param PLLQ_R This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5265	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
AnnaBridge	145:64910690c574	5266	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
AnnaBridge	145:64910690c574	5267	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
AnnaBridge	145:64910690c574	5268	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
AnnaBridge	145:64910690c574	5269	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
AnnaBridge	145:64910690c574	5270	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
AnnaBridge	145:64910690c574	5271	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
AnnaBridge	145:64910690c574	5272	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
AnnaBridge	145:64910690c574	5273	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
AnnaBridge	145:64910690c574	5274	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
AnnaBridge	145:64910690c574	5275	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
AnnaBridge	145:64910690c574	5276	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
AnnaBridge	145:64910690c574	5277	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
AnnaBridge	145:64910690c574	5278	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
AnnaBridge	145:64910690c574	5279	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
AnnaBridge	145:64910690c574	5280	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
AnnaBridge	145:64910690c574	5281	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
AnnaBridge	145:64910690c574	5282	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
AnnaBridge	145:64910690c574	5283	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
AnnaBridge	145:64910690c574	5284	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
AnnaBridge	145:64910690c574	5285	*
AnnaBridge	145:64910690c574	5286	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5287	* @param PLLDIVQ_R This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5288	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
AnnaBridge	145:64910690c574	5289	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
AnnaBridge	145:64910690c574	5290	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
AnnaBridge	145:64910690c574	5291	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
AnnaBridge	145:64910690c574	5292	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
AnnaBridge	145:64910690c574	5293	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
AnnaBridge	145:64910690c574	5294	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
AnnaBridge	145:64910690c574	5295	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
AnnaBridge	145:64910690c574	5296	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
AnnaBridge	145:64910690c574	5297	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
AnnaBridge	145:64910690c574	5298	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
AnnaBridge	145:64910690c574	5299	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
AnnaBridge	145:64910690c574	5300	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
AnnaBridge	145:64910690c574	5301	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
AnnaBridge	145:64910690c574	5302	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
AnnaBridge	145:64910690c574	5303	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
AnnaBridge	145:64910690c574	5304	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
AnnaBridge	145:64910690c574	5305	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
AnnaBridge	145:64910690c574	5306	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
AnnaBridge	145:64910690c574	5307	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
AnnaBridge	145:64910690c574	5308	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
AnnaBridge	145:64910690c574	5309	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
AnnaBridge	145:64910690c574	5310	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
AnnaBridge	145:64910690c574	5311	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
AnnaBridge	145:64910690c574	5312	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
AnnaBridge	145:64910690c574	5313	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
AnnaBridge	145:64910690c574	5314	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
AnnaBridge	145:64910690c574	5315	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
AnnaBridge	145:64910690c574	5316	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
AnnaBridge	145:64910690c574	5317	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
AnnaBridge	145:64910690c574	5318	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
AnnaBridge	145:64910690c574	5319	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
AnnaBridge	145:64910690c574	5320	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
AnnaBridge	145:64910690c574	5321	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
AnnaBridge	145:64910690c574	5322	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
AnnaBridge	145:64910690c574	5323	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
AnnaBridge	145:64910690c574	5324	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
AnnaBridge	145:64910690c574	5325	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
AnnaBridge	145:64910690c574	5326	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
AnnaBridge	145:64910690c574	5327	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
AnnaBridge	145:64910690c574	5328	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
AnnaBridge	145:64910690c574	5329	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
AnnaBridge	145:64910690c574	5330	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
AnnaBridge	145:64910690c574	5331	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
AnnaBridge	145:64910690c574	5332	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
AnnaBridge	145:64910690c574	5333	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
AnnaBridge	145:64910690c574	5334	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
AnnaBridge	145:64910690c574	5335	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
AnnaBridge	145:64910690c574	5336	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
AnnaBridge	145:64910690c574	5337	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
AnnaBridge	145:64910690c574	5338	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
AnnaBridge	145:64910690c574	5339	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
AnnaBridge	145:64910690c574	5340	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
AnnaBridge	145:64910690c574	5341	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
AnnaBridge	145:64910690c574	5342	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
AnnaBridge	145:64910690c574	5343	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
AnnaBridge	145:64910690c574	5344	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
AnnaBridge	145:64910690c574	5345	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
AnnaBridge	145:64910690c574	5346	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
AnnaBridge	145:64910690c574	5347	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
AnnaBridge	145:64910690c574	5348	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
AnnaBridge	145:64910690c574	5349	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
AnnaBridge	145:64910690c574	5350	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
AnnaBridge	145:64910690c574	5351	*
AnnaBridge	145:64910690c574	5352	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5353	* @retval None
AnnaBridge	145:64910690c574	5354	*/
AnnaBridge	145:64910690c574	5355	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
AnnaBridge	145:64910690c574	5356	{
AnnaBridge	145:64910690c574	5357	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
AnnaBridge	145:64910690c574	5358	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
AnnaBridge	145:64910690c574	5359	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	5360	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
AnnaBridge	145:64910690c574	5361	#else
AnnaBridge	145:64910690c574	5362	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	5363	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	5364	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
AnnaBridge	145:64910690c574	5365	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	5366	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
AnnaBridge	145:64910690c574	5367	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
AnnaBridge	145:64910690c574	5368	#else
AnnaBridge	145:64910690c574	5369	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
AnnaBridge	145:64910690c574	5370	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
AnnaBridge	145:64910690c574	5371	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	5372	}
AnnaBridge	145:64910690c574	5373	#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
AnnaBridge	145:64910690c574	5374
AnnaBridge	145:64910690c574	5375	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	5376	/**
AnnaBridge	145:64910690c574	5377	* @brief Configure PLLI2S used for 48Mhz domain clock
AnnaBridge	145:64910690c574	5378	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	5379	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	5380	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
AnnaBridge	145:64910690c574	5381	* @note This can be selected for RNG, USB, SDIO
AnnaBridge	145:64910690c574	5382	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	5383	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	5384	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	5385	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	5386	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	5387	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
AnnaBridge	145:64910690c574	5388	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5389	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	5390	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	5391	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
AnnaBridge	145:64910690c574	5392	*
AnnaBridge	145:64910690c574	5393	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5394	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5395	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	5396	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	5397	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	5398	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	5399	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	5400	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	5401	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	5402	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	5403	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	5404	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	5405	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	5406	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	5407	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	5408	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	5409	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	5410	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	5411	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	5412	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	5413	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	5414	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	5415	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	5416	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	5417	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	5418	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	5419	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	5420	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	5421	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	5422	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	5423	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	5424	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	5425	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	5426	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	5427	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	5428	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	5429	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	5430	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	5431	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	5432	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	5433	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	5434	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	5435	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	5436	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	5437	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	5438	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	5439	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	5440	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	5441	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	5442	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	5443	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	5444	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	5445	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	5446	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	5447	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	5448	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	5449	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	5450	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	5451	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	5452	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	5453	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	5454	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	5455	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	5456	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	5457	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	5458	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5459	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	145:64910690c574	5460	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	145:64910690c574	5461	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	145:64910690c574	5462	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	145:64910690c574	5463	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	145:64910690c574	5464	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	145:64910690c574	5465	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	145:64910690c574	5466	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	145:64910690c574	5467	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	145:64910690c574	5468	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	145:64910690c574	5469	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	145:64910690c574	5470	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	145:64910690c574	5471	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	145:64910690c574	5472	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	145:64910690c574	5473	* @retval None
AnnaBridge	145:64910690c574	5474	*/
AnnaBridge	145:64910690c574	5475	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	145:64910690c574	5476	{
AnnaBridge	145:64910690c574	5477	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
AnnaBridge	145:64910690c574	5478	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
AnnaBridge	145:64910690c574	5479	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	5480	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
AnnaBridge	145:64910690c574	5481	#else
AnnaBridge	145:64910690c574	5482	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	5483	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	5484	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
AnnaBridge	145:64910690c574	5485	}
AnnaBridge	145:64910690c574	5486	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	5487
AnnaBridge	145:64910690c574	5488	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	5489	/**
AnnaBridge	145:64910690c574	5490	* @brief Configure PLLI2S used for SPDIFRX domain clock
AnnaBridge	145:64910690c574	5491	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	5492	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	5493	* @note PLLN/PLLP can be written only when PLLI2S is disabled
AnnaBridge	145:64910690c574	5494	* @note This can be selected for SPDIFRX
AnnaBridge	145:64910690c574	5495	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	5496	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	5497	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	5498	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	145:64910690c574	5499	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
AnnaBridge	145:64910690c574	5500	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5501	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	5502	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	5503	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5504	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	5505	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	5506	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	5507	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	5508	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	5509	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	5510	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	5511	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	5512	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	5513	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	5514	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	5515	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	5516	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	5517	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	5518	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	5519	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	5520	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	5521	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	5522	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	5523	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	5524	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	5525	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	5526	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	5527	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	5528	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	5529	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	5530	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	5531	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	5532	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	5533	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	5534	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	5535	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	5536	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	5537	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	5538	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	5539	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	5540	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	5541	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	5542	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	5543	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	5544	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	5545	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	5546	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	5547	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	5548	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	5549	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	5550	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	5551	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	5552	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	5553	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	5554	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	5555	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	5556	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	5557	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	5558	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	5559	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	5560	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	5561	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	5562	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	5563	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	5564	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	5565	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	5566	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	5567	* @param PLLP This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5568	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	145:64910690c574	5569	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	145:64910690c574	5570	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	145:64910690c574	5571	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	145:64910690c574	5572	* @retval None
AnnaBridge	145:64910690c574	5573	*/
AnnaBridge	145:64910690c574	5574	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	145:64910690c574	5575	{
AnnaBridge	145:64910690c574	5576	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	145:64910690c574	5577	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	5578	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
AnnaBridge	145:64910690c574	5579	#else
AnnaBridge	145:64910690c574	5580	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	5581	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	5582	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
AnnaBridge	145:64910690c574	5583	}
AnnaBridge	145:64910690c574	5584	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	5585
AnnaBridge	145:64910690c574	5586	/**
AnnaBridge	145:64910690c574	5587	* @brief Configure PLLI2S used for I2S1 domain clock
AnnaBridge	145:64910690c574	5588	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	5589	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	5590	* @note PLLN/PLLR can be written only when PLLI2S is disabled
AnnaBridge	145:64910690c574	5591	* @note This can be selected for I2S
AnnaBridge	145:64910690c574	5592	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	5593	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	5594	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	5595	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	5596	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	5597	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
AnnaBridge	145:64910690c574	5598	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5599	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	5600	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	5601	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
AnnaBridge	145:64910690c574	5602	*
AnnaBridge	145:64910690c574	5603	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5604	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5605	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	5606	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	5607	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	5608	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	5609	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	5610	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	5611	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	5612	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	5613	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	5614	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	5615	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	5616	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	5617	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	5618	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	5619	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	5620	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	5621	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	5622	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	5623	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	5624	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	5625	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	5626	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	5627	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	5628	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	5629	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	5630	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	5631	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	5632	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	5633	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	5634	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	5635	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	5636	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	5637	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	5638	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	5639	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	5640	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	5641	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	5642	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	5643	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	5644	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	5645	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	5646	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	5647	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	5648	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	5649	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	5650	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	5651	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	5652	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	5653	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	5654	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	5655	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	5656	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	5657	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	5658	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	5659	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	5660	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	5661	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	5662	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	5663	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	5664	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	5665	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	5666	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	5667	* @param PLLN Between 50/192(*) and 432
AnnaBridge	145:64910690c574	5668	*
AnnaBridge	145:64910690c574	5669	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5670	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	5671	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	5672	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	5673	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	5674	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	5675	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	5676	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	5677	* @retval None
AnnaBridge	145:64910690c574	5678	*/
AnnaBridge	145:64910690c574	5679	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	5680	{
AnnaBridge	145:64910690c574	5681	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
AnnaBridge	145:64910690c574	5682	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
AnnaBridge	145:64910690c574	5683	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	5684	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
AnnaBridge	145:64910690c574	5685	#else
AnnaBridge	145:64910690c574	5686	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	5687	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	5688	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
AnnaBridge	145:64910690c574	5689	}
AnnaBridge	145:64910690c574	5690
AnnaBridge	145:64910690c574	5691	/**
AnnaBridge	145:64910690c574	5692	* @brief Get I2SPLL multiplication factor for VCO
AnnaBridge	145:64910690c574	5693	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
AnnaBridge	145:64910690c574	5694	* @retval Between 50/192(*) and 432
AnnaBridge	145:64910690c574	5695	*
AnnaBridge	145:64910690c574	5696	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5697	*/
AnnaBridge	145:64910690c574	5698	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
AnnaBridge	145:64910690c574	5699	{
AnnaBridge	145:64910690c574	5700	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
AnnaBridge	145:64910690c574	5701	}
AnnaBridge	145:64910690c574	5702
AnnaBridge	145:64910690c574	5703	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
AnnaBridge	145:64910690c574	5704	/**
AnnaBridge	145:64910690c574	5705	* @brief Get I2SPLL division factor for PLLI2SQ
AnnaBridge	145:64910690c574	5706	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
AnnaBridge	145:64910690c574	5707	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5708	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	145:64910690c574	5709	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	145:64910690c574	5710	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	145:64910690c574	5711	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	145:64910690c574	5712	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	145:64910690c574	5713	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	145:64910690c574	5714	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	145:64910690c574	5715	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	145:64910690c574	5716	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	145:64910690c574	5717	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	145:64910690c574	5718	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	145:64910690c574	5719	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	145:64910690c574	5720	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	145:64910690c574	5721	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	145:64910690c574	5722	*/
AnnaBridge	145:64910690c574	5723	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
AnnaBridge	145:64910690c574	5724	{
AnnaBridge	145:64910690c574	5725	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
AnnaBridge	145:64910690c574	5726	}
AnnaBridge	145:64910690c574	5727	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
AnnaBridge	145:64910690c574	5728
AnnaBridge	145:64910690c574	5729	/**
AnnaBridge	145:64910690c574	5730	* @brief Get I2SPLL division factor for PLLI2SR
AnnaBridge	145:64910690c574	5731	* @note used for PLLI2SCLK (I2S clock)
AnnaBridge	145:64910690c574	5732	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
AnnaBridge	145:64910690c574	5733	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5734	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	5735	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	5736	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	5737	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	5738	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	5739	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	5740	*/
AnnaBridge	145:64910690c574	5741	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
AnnaBridge	145:64910690c574	5742	{
AnnaBridge	145:64910690c574	5743	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
AnnaBridge	145:64910690c574	5744	}
AnnaBridge	145:64910690c574	5745
AnnaBridge	145:64910690c574	5746	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
AnnaBridge	145:64910690c574	5747	/**
AnnaBridge	145:64910690c574	5748	* @brief Get I2SPLL division factor for PLLI2SP
AnnaBridge	145:64910690c574	5749	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
AnnaBridge	145:64910690c574	5750	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
AnnaBridge	145:64910690c574	5751	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5752	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	145:64910690c574	5753	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	145:64910690c574	5754	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	145:64910690c574	5755	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	145:64910690c574	5756	*/
AnnaBridge	145:64910690c574	5757	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
AnnaBridge	145:64910690c574	5758	{
AnnaBridge	145:64910690c574	5759	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
AnnaBridge	145:64910690c574	5760	}
AnnaBridge	145:64910690c574	5761	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
AnnaBridge	145:64910690c574	5762
AnnaBridge	145:64910690c574	5763	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
AnnaBridge	145:64910690c574	5764	/**
AnnaBridge	145:64910690c574	5765	* @brief Get I2SPLL division factor for PLLI2SDIVQ
AnnaBridge	145:64910690c574	5766	* @note used PLLSAICLK selected (SAI clock)
AnnaBridge	145:64910690c574	5767	* @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
AnnaBridge	145:64910690c574	5768	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5769	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
AnnaBridge	145:64910690c574	5770	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
AnnaBridge	145:64910690c574	5771	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
AnnaBridge	145:64910690c574	5772	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
AnnaBridge	145:64910690c574	5773	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
AnnaBridge	145:64910690c574	5774	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
AnnaBridge	145:64910690c574	5775	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
AnnaBridge	145:64910690c574	5776	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
AnnaBridge	145:64910690c574	5777	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
AnnaBridge	145:64910690c574	5778	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
AnnaBridge	145:64910690c574	5779	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
AnnaBridge	145:64910690c574	5780	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
AnnaBridge	145:64910690c574	5781	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
AnnaBridge	145:64910690c574	5782	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
AnnaBridge	145:64910690c574	5783	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
AnnaBridge	145:64910690c574	5784	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
AnnaBridge	145:64910690c574	5785	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
AnnaBridge	145:64910690c574	5786	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
AnnaBridge	145:64910690c574	5787	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
AnnaBridge	145:64910690c574	5788	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
AnnaBridge	145:64910690c574	5789	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
AnnaBridge	145:64910690c574	5790	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
AnnaBridge	145:64910690c574	5791	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
AnnaBridge	145:64910690c574	5792	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
AnnaBridge	145:64910690c574	5793	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
AnnaBridge	145:64910690c574	5794	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
AnnaBridge	145:64910690c574	5795	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
AnnaBridge	145:64910690c574	5796	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
AnnaBridge	145:64910690c574	5797	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
AnnaBridge	145:64910690c574	5798	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
AnnaBridge	145:64910690c574	5799	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
AnnaBridge	145:64910690c574	5800	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
AnnaBridge	145:64910690c574	5801	*/
AnnaBridge	145:64910690c574	5802	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
AnnaBridge	145:64910690c574	5803	{
AnnaBridge	145:64910690c574	5804	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
AnnaBridge	145:64910690c574	5805	}
AnnaBridge	145:64910690c574	5806	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
AnnaBridge	145:64910690c574	5807
AnnaBridge	145:64910690c574	5808	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
AnnaBridge	145:64910690c574	5809	/**
AnnaBridge	145:64910690c574	5810	* @brief Get I2SPLL division factor for PLLI2SDIVR
AnnaBridge	145:64910690c574	5811	* @note used PLLSAICLK selected (SAI clock)
AnnaBridge	145:64910690c574	5812	* @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
AnnaBridge	145:64910690c574	5813	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5814	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
AnnaBridge	145:64910690c574	5815	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
AnnaBridge	145:64910690c574	5816	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
AnnaBridge	145:64910690c574	5817	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
AnnaBridge	145:64910690c574	5818	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
AnnaBridge	145:64910690c574	5819	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
AnnaBridge	145:64910690c574	5820	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
AnnaBridge	145:64910690c574	5821	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
AnnaBridge	145:64910690c574	5822	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
AnnaBridge	145:64910690c574	5823	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
AnnaBridge	145:64910690c574	5824	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
AnnaBridge	145:64910690c574	5825	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
AnnaBridge	145:64910690c574	5826	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
AnnaBridge	145:64910690c574	5827	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
AnnaBridge	145:64910690c574	5828	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
AnnaBridge	145:64910690c574	5829	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
AnnaBridge	145:64910690c574	5830	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
AnnaBridge	145:64910690c574	5831	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
AnnaBridge	145:64910690c574	5832	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
AnnaBridge	145:64910690c574	5833	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
AnnaBridge	145:64910690c574	5834	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
AnnaBridge	145:64910690c574	5835	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
AnnaBridge	145:64910690c574	5836	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
AnnaBridge	145:64910690c574	5837	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
AnnaBridge	145:64910690c574	5838	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
AnnaBridge	145:64910690c574	5839	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
AnnaBridge	145:64910690c574	5840	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
AnnaBridge	145:64910690c574	5841	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
AnnaBridge	145:64910690c574	5842	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
AnnaBridge	145:64910690c574	5843	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
AnnaBridge	145:64910690c574	5844	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
AnnaBridge	145:64910690c574	5845	*/
AnnaBridge	145:64910690c574	5846	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
AnnaBridge	145:64910690c574	5847	{
AnnaBridge	145:64910690c574	5848	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
AnnaBridge	145:64910690c574	5849	}
AnnaBridge	145:64910690c574	5850	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
AnnaBridge	145:64910690c574	5851
AnnaBridge	145:64910690c574	5852	/**
AnnaBridge	145:64910690c574	5853	* @brief Get division factor for PLLI2S input clock
AnnaBridge	145:64910690c574	5854	* @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
AnnaBridge	145:64910690c574	5855	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
AnnaBridge	145:64910690c574	5856	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5857	* @arg @ref LL_RCC_PLLI2SM_DIV_2
AnnaBridge	145:64910690c574	5858	* @arg @ref LL_RCC_PLLI2SM_DIV_3
AnnaBridge	145:64910690c574	5859	* @arg @ref LL_RCC_PLLI2SM_DIV_4
AnnaBridge	145:64910690c574	5860	* @arg @ref LL_RCC_PLLI2SM_DIV_5
AnnaBridge	145:64910690c574	5861	* @arg @ref LL_RCC_PLLI2SM_DIV_6
AnnaBridge	145:64910690c574	5862	* @arg @ref LL_RCC_PLLI2SM_DIV_7
AnnaBridge	145:64910690c574	5863	* @arg @ref LL_RCC_PLLI2SM_DIV_8
AnnaBridge	145:64910690c574	5864	* @arg @ref LL_RCC_PLLI2SM_DIV_9
AnnaBridge	145:64910690c574	5865	* @arg @ref LL_RCC_PLLI2SM_DIV_10
AnnaBridge	145:64910690c574	5866	* @arg @ref LL_RCC_PLLI2SM_DIV_11
AnnaBridge	145:64910690c574	5867	* @arg @ref LL_RCC_PLLI2SM_DIV_12
AnnaBridge	145:64910690c574	5868	* @arg @ref LL_RCC_PLLI2SM_DIV_13
AnnaBridge	145:64910690c574	5869	* @arg @ref LL_RCC_PLLI2SM_DIV_14
AnnaBridge	145:64910690c574	5870	* @arg @ref LL_RCC_PLLI2SM_DIV_15
AnnaBridge	145:64910690c574	5871	* @arg @ref LL_RCC_PLLI2SM_DIV_16
AnnaBridge	145:64910690c574	5872	* @arg @ref LL_RCC_PLLI2SM_DIV_17
AnnaBridge	145:64910690c574	5873	* @arg @ref LL_RCC_PLLI2SM_DIV_18
AnnaBridge	145:64910690c574	5874	* @arg @ref LL_RCC_PLLI2SM_DIV_19
AnnaBridge	145:64910690c574	5875	* @arg @ref LL_RCC_PLLI2SM_DIV_20
AnnaBridge	145:64910690c574	5876	* @arg @ref LL_RCC_PLLI2SM_DIV_21
AnnaBridge	145:64910690c574	5877	* @arg @ref LL_RCC_PLLI2SM_DIV_22
AnnaBridge	145:64910690c574	5878	* @arg @ref LL_RCC_PLLI2SM_DIV_23
AnnaBridge	145:64910690c574	5879	* @arg @ref LL_RCC_PLLI2SM_DIV_24
AnnaBridge	145:64910690c574	5880	* @arg @ref LL_RCC_PLLI2SM_DIV_25
AnnaBridge	145:64910690c574	5881	* @arg @ref LL_RCC_PLLI2SM_DIV_26
AnnaBridge	145:64910690c574	5882	* @arg @ref LL_RCC_PLLI2SM_DIV_27
AnnaBridge	145:64910690c574	5883	* @arg @ref LL_RCC_PLLI2SM_DIV_28
AnnaBridge	145:64910690c574	5884	* @arg @ref LL_RCC_PLLI2SM_DIV_29
AnnaBridge	145:64910690c574	5885	* @arg @ref LL_RCC_PLLI2SM_DIV_30
AnnaBridge	145:64910690c574	5886	* @arg @ref LL_RCC_PLLI2SM_DIV_31
AnnaBridge	145:64910690c574	5887	* @arg @ref LL_RCC_PLLI2SM_DIV_32
AnnaBridge	145:64910690c574	5888	* @arg @ref LL_RCC_PLLI2SM_DIV_33
AnnaBridge	145:64910690c574	5889	* @arg @ref LL_RCC_PLLI2SM_DIV_34
AnnaBridge	145:64910690c574	5890	* @arg @ref LL_RCC_PLLI2SM_DIV_35
AnnaBridge	145:64910690c574	5891	* @arg @ref LL_RCC_PLLI2SM_DIV_36
AnnaBridge	145:64910690c574	5892	* @arg @ref LL_RCC_PLLI2SM_DIV_37
AnnaBridge	145:64910690c574	5893	* @arg @ref LL_RCC_PLLI2SM_DIV_38
AnnaBridge	145:64910690c574	5894	* @arg @ref LL_RCC_PLLI2SM_DIV_39
AnnaBridge	145:64910690c574	5895	* @arg @ref LL_RCC_PLLI2SM_DIV_40
AnnaBridge	145:64910690c574	5896	* @arg @ref LL_RCC_PLLI2SM_DIV_41
AnnaBridge	145:64910690c574	5897	* @arg @ref LL_RCC_PLLI2SM_DIV_42
AnnaBridge	145:64910690c574	5898	* @arg @ref LL_RCC_PLLI2SM_DIV_43
AnnaBridge	145:64910690c574	5899	* @arg @ref LL_RCC_PLLI2SM_DIV_44
AnnaBridge	145:64910690c574	5900	* @arg @ref LL_RCC_PLLI2SM_DIV_45
AnnaBridge	145:64910690c574	5901	* @arg @ref LL_RCC_PLLI2SM_DIV_46
AnnaBridge	145:64910690c574	5902	* @arg @ref LL_RCC_PLLI2SM_DIV_47
AnnaBridge	145:64910690c574	5903	* @arg @ref LL_RCC_PLLI2SM_DIV_48
AnnaBridge	145:64910690c574	5904	* @arg @ref LL_RCC_PLLI2SM_DIV_49
AnnaBridge	145:64910690c574	5905	* @arg @ref LL_RCC_PLLI2SM_DIV_50
AnnaBridge	145:64910690c574	5906	* @arg @ref LL_RCC_PLLI2SM_DIV_51
AnnaBridge	145:64910690c574	5907	* @arg @ref LL_RCC_PLLI2SM_DIV_52
AnnaBridge	145:64910690c574	5908	* @arg @ref LL_RCC_PLLI2SM_DIV_53
AnnaBridge	145:64910690c574	5909	* @arg @ref LL_RCC_PLLI2SM_DIV_54
AnnaBridge	145:64910690c574	5910	* @arg @ref LL_RCC_PLLI2SM_DIV_55
AnnaBridge	145:64910690c574	5911	* @arg @ref LL_RCC_PLLI2SM_DIV_56
AnnaBridge	145:64910690c574	5912	* @arg @ref LL_RCC_PLLI2SM_DIV_57
AnnaBridge	145:64910690c574	5913	* @arg @ref LL_RCC_PLLI2SM_DIV_58
AnnaBridge	145:64910690c574	5914	* @arg @ref LL_RCC_PLLI2SM_DIV_59
AnnaBridge	145:64910690c574	5915	* @arg @ref LL_RCC_PLLI2SM_DIV_60
AnnaBridge	145:64910690c574	5916	* @arg @ref LL_RCC_PLLI2SM_DIV_61
AnnaBridge	145:64910690c574	5917	* @arg @ref LL_RCC_PLLI2SM_DIV_62
AnnaBridge	145:64910690c574	5918	* @arg @ref LL_RCC_PLLI2SM_DIV_63
AnnaBridge	145:64910690c574	5919	*/
AnnaBridge	145:64910690c574	5920	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
AnnaBridge	145:64910690c574	5921	{
AnnaBridge	145:64910690c574	5922	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
AnnaBridge	145:64910690c574	5923	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
AnnaBridge	145:64910690c574	5924	#else
AnnaBridge	145:64910690c574	5925	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	145:64910690c574	5926	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
AnnaBridge	145:64910690c574	5927	}
AnnaBridge	145:64910690c574	5928
AnnaBridge	145:64910690c574	5929	/**
AnnaBridge	145:64910690c574	5930	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	145:64910690c574	5931	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
AnnaBridge	145:64910690c574	5932	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
AnnaBridge	145:64910690c574	5933	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	5934	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	5935	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	5936	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
AnnaBridge	145:64910690c574	5937	*
AnnaBridge	145:64910690c574	5938	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	5939	*/
AnnaBridge	145:64910690c574	5940	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
AnnaBridge	145:64910690c574	5941	{
AnnaBridge	145:64910690c574	5942	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
AnnaBridge	145:64910690c574	5943	register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
AnnaBridge	145:64910690c574	5944	register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
AnnaBridge	145:64910690c574	5945	register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
AnnaBridge	145:64910690c574	5946	return (uint32_t)(pllsrc \| plli2sssrc0 \| plli2sssrc1);
AnnaBridge	145:64910690c574	5947	#else
AnnaBridge	145:64910690c574	5948	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	145:64910690c574	5949	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
AnnaBridge	145:64910690c574	5950	}
AnnaBridge	145:64910690c574	5951
AnnaBridge	145:64910690c574	5952	/**
AnnaBridge	145:64910690c574	5953	* @}
AnnaBridge	145:64910690c574	5954	*/
AnnaBridge	145:64910690c574	5955	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	5956
AnnaBridge	145:64910690c574	5957	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	5958	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
AnnaBridge	145:64910690c574	5959	* @{
AnnaBridge	145:64910690c574	5960	*/
AnnaBridge	145:64910690c574	5961
AnnaBridge	145:64910690c574	5962	/**
AnnaBridge	145:64910690c574	5963	* @brief Enable PLLSAI
AnnaBridge	145:64910690c574	5964	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
AnnaBridge	145:64910690c574	5965	* @retval None
AnnaBridge	145:64910690c574	5966	*/
AnnaBridge	145:64910690c574	5967	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
AnnaBridge	145:64910690c574	5968	{
AnnaBridge	145:64910690c574	5969	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
AnnaBridge	145:64910690c574	5970	}
AnnaBridge	145:64910690c574	5971
AnnaBridge	145:64910690c574	5972	/**
AnnaBridge	145:64910690c574	5973	* @brief Disable PLLSAI
AnnaBridge	145:64910690c574	5974	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
AnnaBridge	145:64910690c574	5975	* @retval None
AnnaBridge	145:64910690c574	5976	*/
AnnaBridge	145:64910690c574	5977	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
AnnaBridge	145:64910690c574	5978	{
AnnaBridge	145:64910690c574	5979	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
AnnaBridge	145:64910690c574	5980	}
AnnaBridge	145:64910690c574	5981
AnnaBridge	145:64910690c574	5982	/**
AnnaBridge	145:64910690c574	5983	* @brief Check if PLLSAI Ready
AnnaBridge	145:64910690c574	5984	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
AnnaBridge	145:64910690c574	5985	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	5986	*/
AnnaBridge	145:64910690c574	5987	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
AnnaBridge	145:64910690c574	5988	{
AnnaBridge	145:64910690c574	5989	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
AnnaBridge	145:64910690c574	5990	}
AnnaBridge	145:64910690c574	5991
AnnaBridge	145:64910690c574	5992	/**
AnnaBridge	145:64910690c574	5993	* @brief Configure PLLSAI used for SAI domain clock
AnnaBridge	145:64910690c574	5994	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	5995	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	5996	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
AnnaBridge	145:64910690c574	5997	* @note This can be selected for SAI
AnnaBridge	145:64910690c574	5998	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	5999	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	6000	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	6001	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	6002	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	145:64910690c574	6003	* DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
AnnaBridge	145:64910690c574	6004	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6005	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	6006	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	6007	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6008	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	6009	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	6010	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	6011	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	6012	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	6013	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	6014	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	6015	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	6016	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	6017	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	6018	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	6019	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	6020	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	6021	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	6022	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	6023	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	6024	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	6025	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	6026	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	6027	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	6028	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	6029	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	6030	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	6031	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	6032	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	6033	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	6034	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	6035	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	6036	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	6037	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	6038	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	6039	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	6040	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	6041	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	6042	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	6043	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	6044	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	6045	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	6046	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	6047	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	6048	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	6049	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	6050	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	6051	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	6052	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	6053	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	6054	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	6055	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	6056	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	6057	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	6058	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	6059	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	6060	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	6061	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	6062	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	6063	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	6064	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	6065	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	6066	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	6067	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	6068	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	6069	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	6070	* @param PLLN Between 49/50(*) and 432
AnnaBridge	145:64910690c574	6071	*
AnnaBridge	145:64910690c574	6072	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	6073	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6074	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	145:64910690c574	6075	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	145:64910690c574	6076	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	145:64910690c574	6077	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	145:64910690c574	6078	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	145:64910690c574	6079	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	145:64910690c574	6080	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	145:64910690c574	6081	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	145:64910690c574	6082	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	145:64910690c574	6083	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	145:64910690c574	6084	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	145:64910690c574	6085	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	145:64910690c574	6086	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	145:64910690c574	6087	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	145:64910690c574	6088	* @param PLLDIVQ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6089	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	145:64910690c574	6090	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	145:64910690c574	6091	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	145:64910690c574	6092	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	145:64910690c574	6093	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	145:64910690c574	6094	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	145:64910690c574	6095	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	145:64910690c574	6096	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	145:64910690c574	6097	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	145:64910690c574	6098	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	145:64910690c574	6099	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	145:64910690c574	6100	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	145:64910690c574	6101	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	145:64910690c574	6102	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	145:64910690c574	6103	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	145:64910690c574	6104	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	145:64910690c574	6105	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	145:64910690c574	6106	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	145:64910690c574	6107	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	145:64910690c574	6108	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	145:64910690c574	6109	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	145:64910690c574	6110	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	145:64910690c574	6111	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	145:64910690c574	6112	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	145:64910690c574	6113	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	145:64910690c574	6114	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	145:64910690c574	6115	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	145:64910690c574	6116	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	145:64910690c574	6117	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	145:64910690c574	6118	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	145:64910690c574	6119	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	145:64910690c574	6120	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	145:64910690c574	6121	* @retval None
AnnaBridge	145:64910690c574	6122	*/
AnnaBridge	145:64910690c574	6123	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
AnnaBridge	145:64910690c574	6124	{
AnnaBridge	145:64910690c574	6125	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	145:64910690c574	6126	#if defined(RCC_PLLSAICFGR_PLLSAIM)
AnnaBridge	145:64910690c574	6127	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
AnnaBridge	145:64910690c574	6128	#else
AnnaBridge	145:64910690c574	6129	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	6130	#endif /* RCC_PLLSAICFGR_PLLSAIM */
AnnaBridge	145:64910690c574	6131	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
AnnaBridge	145:64910690c574	6132	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
AnnaBridge	145:64910690c574	6133	}
AnnaBridge	145:64910690c574	6134
AnnaBridge	145:64910690c574	6135	#if defined(RCC_PLLSAICFGR_PLLSAIP)
AnnaBridge	145:64910690c574	6136	/**
AnnaBridge	145:64910690c574	6137	* @brief Configure PLLSAI used for 48Mhz domain clock
AnnaBridge	145:64910690c574	6138	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	6139	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	6140	* @note PLLN/PLLP can be written only when PLLSAI is disabled
AnnaBridge	145:64910690c574	6141	* @note This can be selected for USB, RNG, SDIO
AnnaBridge	145:64910690c574	6142	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	6143	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	6144	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	6145	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	6146	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
AnnaBridge	145:64910690c574	6147	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6148	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	6149	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	6150	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6151	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	6152	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	6153	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	6154	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	6155	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	6156	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	6157	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	6158	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	6159	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	6160	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	6161	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	6162	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	6163	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	6164	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	6165	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	6166	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	6167	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	6168	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	6169	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	6170	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	6171	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	6172	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	6173	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	6174	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	6175	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	6176	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	6177	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	6178	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	6179	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	6180	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	6181	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	6182	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	6183	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	6184	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	6185	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	6186	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	6187	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	6188	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	6189	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	6190	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	6191	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	6192	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	6193	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	6194	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	6195	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	6196	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	6197	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	6198	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	6199	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	6200	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	6201	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	6202	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	6203	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	6204	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	6205	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	6206	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	6207	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	6208	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	6209	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	6210	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	6211	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	6212	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	6213	* @param PLLN Between 50 and 432
AnnaBridge	145:64910690c574	6214	* @param PLLP This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6215	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	145:64910690c574	6216	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	145:64910690c574	6217	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	145:64910690c574	6218	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	145:64910690c574	6219	* @retval None
AnnaBridge	145:64910690c574	6220	*/
AnnaBridge	145:64910690c574	6221	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	145:64910690c574	6222	{
AnnaBridge	145:64910690c574	6223	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	145:64910690c574	6224	#if defined(RCC_PLLSAICFGR_PLLSAIM)
AnnaBridge	145:64910690c574	6225	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
AnnaBridge	145:64910690c574	6226	#else
AnnaBridge	145:64910690c574	6227	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
AnnaBridge	145:64910690c574	6228	#endif /* RCC_PLLSAICFGR_PLLSAIM */
AnnaBridge	145:64910690c574	6229	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
AnnaBridge	145:64910690c574	6230	}
AnnaBridge	145:64910690c574	6231	#endif /* RCC_PLLSAICFGR_PLLSAIP */
AnnaBridge	145:64910690c574	6232
AnnaBridge	145:64910690c574	6233	#if defined(LTDC)
AnnaBridge	145:64910690c574	6234	/**
AnnaBridge	145:64910690c574	6235	* @brief Configure PLLSAI used for LTDC domain clock
AnnaBridge	145:64910690c574	6236	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	6237	* PLLI2S and PLLSAI(*) are disabled
AnnaBridge	145:64910690c574	6238	* @note PLLN/PLLR can be written only when PLLSAI is disabled
AnnaBridge	145:64910690c574	6239	* @note This can be selected for LTDC
AnnaBridge	145:64910690c574	6240	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	145:64910690c574	6241	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	145:64910690c574	6242	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	145:64910690c574	6243	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	145:64910690c574	6244	* DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
AnnaBridge	145:64910690c574	6245	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6246	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	6247	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	6248	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6249	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	6250	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	6251	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	6252	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	6253	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	6254	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	6255	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	6256	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	6257	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	6258	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	6259	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	6260	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	6261	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	6262	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	6263	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	6264	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	6265	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	6266	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	6267	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	6268	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	6269	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	6270	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	6271	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	6272	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	6273	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	6274	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	6275	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	6276	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	6277	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	6278	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	6279	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	6280	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	6281	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	6282	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	6283	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	6284	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	6285	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	6286	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	6287	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	6288	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	6289	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	6290	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	6291	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	6292	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	6293	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	6294	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	6295	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	6296	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	6297	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	6298	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	6299	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	6300	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	6301	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	6302	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	6303	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	6304	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	6305	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	6306	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	6307	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	6308	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	6309	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	6310	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	6311	* @param PLLN Between 49/50(*) and 432
AnnaBridge	145:64910690c574	6312	*
AnnaBridge	145:64910690c574	6313	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	6314	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6315	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	145:64910690c574	6316	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	145:64910690c574	6317	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	145:64910690c574	6318	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	145:64910690c574	6319	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	145:64910690c574	6320	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	145:64910690c574	6321	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6322	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	145:64910690c574	6323	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	145:64910690c574	6324	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	145:64910690c574	6325	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	145:64910690c574	6326	* @retval None
AnnaBridge	145:64910690c574	6327	*/
AnnaBridge	145:64910690c574	6328	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	145:64910690c574	6329	{
AnnaBridge	145:64910690c574	6330	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	6331	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
AnnaBridge	145:64910690c574	6332	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
AnnaBridge	145:64910690c574	6333	}
AnnaBridge	145:64910690c574	6334	#endif /* LTDC */
AnnaBridge	145:64910690c574	6335
AnnaBridge	145:64910690c574	6336	/**
AnnaBridge	145:64910690c574	6337	* @brief Get division factor for PLLSAI input clock
AnnaBridge	145:64910690c574	6338	* @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
AnnaBridge	145:64910690c574	6339	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
AnnaBridge	145:64910690c574	6340	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6341	* @arg @ref LL_RCC_PLLSAIM_DIV_2
AnnaBridge	145:64910690c574	6342	* @arg @ref LL_RCC_PLLSAIM_DIV_3
AnnaBridge	145:64910690c574	6343	* @arg @ref LL_RCC_PLLSAIM_DIV_4
AnnaBridge	145:64910690c574	6344	* @arg @ref LL_RCC_PLLSAIM_DIV_5
AnnaBridge	145:64910690c574	6345	* @arg @ref LL_RCC_PLLSAIM_DIV_6
AnnaBridge	145:64910690c574	6346	* @arg @ref LL_RCC_PLLSAIM_DIV_7
AnnaBridge	145:64910690c574	6347	* @arg @ref LL_RCC_PLLSAIM_DIV_8
AnnaBridge	145:64910690c574	6348	* @arg @ref LL_RCC_PLLSAIM_DIV_9
AnnaBridge	145:64910690c574	6349	* @arg @ref LL_RCC_PLLSAIM_DIV_10
AnnaBridge	145:64910690c574	6350	* @arg @ref LL_RCC_PLLSAIM_DIV_11
AnnaBridge	145:64910690c574	6351	* @arg @ref LL_RCC_PLLSAIM_DIV_12
AnnaBridge	145:64910690c574	6352	* @arg @ref LL_RCC_PLLSAIM_DIV_13
AnnaBridge	145:64910690c574	6353	* @arg @ref LL_RCC_PLLSAIM_DIV_14
AnnaBridge	145:64910690c574	6354	* @arg @ref LL_RCC_PLLSAIM_DIV_15
AnnaBridge	145:64910690c574	6355	* @arg @ref LL_RCC_PLLSAIM_DIV_16
AnnaBridge	145:64910690c574	6356	* @arg @ref LL_RCC_PLLSAIM_DIV_17
AnnaBridge	145:64910690c574	6357	* @arg @ref LL_RCC_PLLSAIM_DIV_18
AnnaBridge	145:64910690c574	6358	* @arg @ref LL_RCC_PLLSAIM_DIV_19
AnnaBridge	145:64910690c574	6359	* @arg @ref LL_RCC_PLLSAIM_DIV_20
AnnaBridge	145:64910690c574	6360	* @arg @ref LL_RCC_PLLSAIM_DIV_21
AnnaBridge	145:64910690c574	6361	* @arg @ref LL_RCC_PLLSAIM_DIV_22
AnnaBridge	145:64910690c574	6362	* @arg @ref LL_RCC_PLLSAIM_DIV_23
AnnaBridge	145:64910690c574	6363	* @arg @ref LL_RCC_PLLSAIM_DIV_24
AnnaBridge	145:64910690c574	6364	* @arg @ref LL_RCC_PLLSAIM_DIV_25
AnnaBridge	145:64910690c574	6365	* @arg @ref LL_RCC_PLLSAIM_DIV_26
AnnaBridge	145:64910690c574	6366	* @arg @ref LL_RCC_PLLSAIM_DIV_27
AnnaBridge	145:64910690c574	6367	* @arg @ref LL_RCC_PLLSAIM_DIV_28
AnnaBridge	145:64910690c574	6368	* @arg @ref LL_RCC_PLLSAIM_DIV_29
AnnaBridge	145:64910690c574	6369	* @arg @ref LL_RCC_PLLSAIM_DIV_30
AnnaBridge	145:64910690c574	6370	* @arg @ref LL_RCC_PLLSAIM_DIV_31
AnnaBridge	145:64910690c574	6371	* @arg @ref LL_RCC_PLLSAIM_DIV_32
AnnaBridge	145:64910690c574	6372	* @arg @ref LL_RCC_PLLSAIM_DIV_33
AnnaBridge	145:64910690c574	6373	* @arg @ref LL_RCC_PLLSAIM_DIV_34
AnnaBridge	145:64910690c574	6374	* @arg @ref LL_RCC_PLLSAIM_DIV_35
AnnaBridge	145:64910690c574	6375	* @arg @ref LL_RCC_PLLSAIM_DIV_36
AnnaBridge	145:64910690c574	6376	* @arg @ref LL_RCC_PLLSAIM_DIV_37
AnnaBridge	145:64910690c574	6377	* @arg @ref LL_RCC_PLLSAIM_DIV_38
AnnaBridge	145:64910690c574	6378	* @arg @ref LL_RCC_PLLSAIM_DIV_39
AnnaBridge	145:64910690c574	6379	* @arg @ref LL_RCC_PLLSAIM_DIV_40
AnnaBridge	145:64910690c574	6380	* @arg @ref LL_RCC_PLLSAIM_DIV_41
AnnaBridge	145:64910690c574	6381	* @arg @ref LL_RCC_PLLSAIM_DIV_42
AnnaBridge	145:64910690c574	6382	* @arg @ref LL_RCC_PLLSAIM_DIV_43
AnnaBridge	145:64910690c574	6383	* @arg @ref LL_RCC_PLLSAIM_DIV_44
AnnaBridge	145:64910690c574	6384	* @arg @ref LL_RCC_PLLSAIM_DIV_45
AnnaBridge	145:64910690c574	6385	* @arg @ref LL_RCC_PLLSAIM_DIV_46
AnnaBridge	145:64910690c574	6386	* @arg @ref LL_RCC_PLLSAIM_DIV_47
AnnaBridge	145:64910690c574	6387	* @arg @ref LL_RCC_PLLSAIM_DIV_48
AnnaBridge	145:64910690c574	6388	* @arg @ref LL_RCC_PLLSAIM_DIV_49
AnnaBridge	145:64910690c574	6389	* @arg @ref LL_RCC_PLLSAIM_DIV_50
AnnaBridge	145:64910690c574	6390	* @arg @ref LL_RCC_PLLSAIM_DIV_51
AnnaBridge	145:64910690c574	6391	* @arg @ref LL_RCC_PLLSAIM_DIV_52
AnnaBridge	145:64910690c574	6392	* @arg @ref LL_RCC_PLLSAIM_DIV_53
AnnaBridge	145:64910690c574	6393	* @arg @ref LL_RCC_PLLSAIM_DIV_54
AnnaBridge	145:64910690c574	6394	* @arg @ref LL_RCC_PLLSAIM_DIV_55
AnnaBridge	145:64910690c574	6395	* @arg @ref LL_RCC_PLLSAIM_DIV_56
AnnaBridge	145:64910690c574	6396	* @arg @ref LL_RCC_PLLSAIM_DIV_57
AnnaBridge	145:64910690c574	6397	* @arg @ref LL_RCC_PLLSAIM_DIV_58
AnnaBridge	145:64910690c574	6398	* @arg @ref LL_RCC_PLLSAIM_DIV_59
AnnaBridge	145:64910690c574	6399	* @arg @ref LL_RCC_PLLSAIM_DIV_60
AnnaBridge	145:64910690c574	6400	* @arg @ref LL_RCC_PLLSAIM_DIV_61
AnnaBridge	145:64910690c574	6401	* @arg @ref LL_RCC_PLLSAIM_DIV_62
AnnaBridge	145:64910690c574	6402	* @arg @ref LL_RCC_PLLSAIM_DIV_63
AnnaBridge	145:64910690c574	6403	*/
AnnaBridge	145:64910690c574	6404	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
AnnaBridge	145:64910690c574	6405	{
AnnaBridge	145:64910690c574	6406	#if defined(RCC_PLLSAICFGR_PLLSAIM)
AnnaBridge	145:64910690c574	6407	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
AnnaBridge	145:64910690c574	6408	#else
AnnaBridge	145:64910690c574	6409	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	145:64910690c574	6410	#endif /* RCC_PLLSAICFGR_PLLSAIM */
AnnaBridge	145:64910690c574	6411	}
AnnaBridge	145:64910690c574	6412
AnnaBridge	145:64910690c574	6413	/**
AnnaBridge	145:64910690c574	6414	* @brief Get SAIPLL multiplication factor for VCO
AnnaBridge	145:64910690c574	6415	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
AnnaBridge	145:64910690c574	6416	* @retval Between 49/50(*) and 432
AnnaBridge	145:64910690c574	6417	*
AnnaBridge	145:64910690c574	6418	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	6419	*/
AnnaBridge	145:64910690c574	6420	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
AnnaBridge	145:64910690c574	6421	{
AnnaBridge	145:64910690c574	6422	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
AnnaBridge	145:64910690c574	6423	}
AnnaBridge	145:64910690c574	6424
AnnaBridge	145:64910690c574	6425	/**
AnnaBridge	145:64910690c574	6426	* @brief Get SAIPLL division factor for PLLSAIQ
AnnaBridge	145:64910690c574	6427	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
AnnaBridge	145:64910690c574	6428	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6429	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	145:64910690c574	6430	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	145:64910690c574	6431	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	145:64910690c574	6432	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	145:64910690c574	6433	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	145:64910690c574	6434	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	145:64910690c574	6435	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	145:64910690c574	6436	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	145:64910690c574	6437	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	145:64910690c574	6438	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	145:64910690c574	6439	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	145:64910690c574	6440	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	145:64910690c574	6441	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	145:64910690c574	6442	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	145:64910690c574	6443	*/
AnnaBridge	145:64910690c574	6444	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
AnnaBridge	145:64910690c574	6445	{
AnnaBridge	145:64910690c574	6446	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
AnnaBridge	145:64910690c574	6447	}
AnnaBridge	145:64910690c574	6448
AnnaBridge	145:64910690c574	6449	#if defined(RCC_PLLSAICFGR_PLLSAIR)
AnnaBridge	145:64910690c574	6450	/**
AnnaBridge	145:64910690c574	6451	* @brief Get SAIPLL division factor for PLLSAIR
AnnaBridge	145:64910690c574	6452	* @note used for PLLSAICLK (SAI clock)
AnnaBridge	145:64910690c574	6453	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
AnnaBridge	145:64910690c574	6454	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6455	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	145:64910690c574	6456	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	145:64910690c574	6457	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	145:64910690c574	6458	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	145:64910690c574	6459	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	145:64910690c574	6460	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	145:64910690c574	6461	*/
AnnaBridge	145:64910690c574	6462	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
AnnaBridge	145:64910690c574	6463	{
AnnaBridge	145:64910690c574	6464	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
AnnaBridge	145:64910690c574	6465	}
AnnaBridge	145:64910690c574	6466	#endif /* RCC_PLLSAICFGR_PLLSAIR */
AnnaBridge	145:64910690c574	6467
AnnaBridge	145:64910690c574	6468	#if defined(RCC_PLLSAICFGR_PLLSAIP)
AnnaBridge	145:64910690c574	6469	/**
AnnaBridge	145:64910690c574	6470	* @brief Get SAIPLL division factor for PLLSAIP
AnnaBridge	145:64910690c574	6471	* @note used for PLL48MCLK (48M domain clock)
AnnaBridge	145:64910690c574	6472	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
AnnaBridge	145:64910690c574	6473	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6474	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	145:64910690c574	6475	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	145:64910690c574	6476	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	145:64910690c574	6477	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	145:64910690c574	6478	*/
AnnaBridge	145:64910690c574	6479	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
AnnaBridge	145:64910690c574	6480	{
AnnaBridge	145:64910690c574	6481	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
AnnaBridge	145:64910690c574	6482	}
AnnaBridge	145:64910690c574	6483	#endif /* RCC_PLLSAICFGR_PLLSAIP */
AnnaBridge	145:64910690c574	6484
AnnaBridge	145:64910690c574	6485	/**
AnnaBridge	145:64910690c574	6486	* @brief Get SAIPLL division factor for PLLSAIDIVQ
AnnaBridge	145:64910690c574	6487	* @note used PLLSAICLK selected (SAI clock)
AnnaBridge	145:64910690c574	6488	* @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
AnnaBridge	145:64910690c574	6489	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6490	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	145:64910690c574	6491	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	145:64910690c574	6492	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	145:64910690c574	6493	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	145:64910690c574	6494	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	145:64910690c574	6495	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	145:64910690c574	6496	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	145:64910690c574	6497	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	145:64910690c574	6498	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	145:64910690c574	6499	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	145:64910690c574	6500	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	145:64910690c574	6501	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	145:64910690c574	6502	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	145:64910690c574	6503	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	145:64910690c574	6504	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	145:64910690c574	6505	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	145:64910690c574	6506	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	145:64910690c574	6507	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	145:64910690c574	6508	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	145:64910690c574	6509	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	145:64910690c574	6510	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	145:64910690c574	6511	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	145:64910690c574	6512	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	145:64910690c574	6513	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	145:64910690c574	6514	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	145:64910690c574	6515	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	145:64910690c574	6516	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	145:64910690c574	6517	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	145:64910690c574	6518	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	145:64910690c574	6519	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	145:64910690c574	6520	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	145:64910690c574	6521	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	145:64910690c574	6522	*/
AnnaBridge	145:64910690c574	6523	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
AnnaBridge	145:64910690c574	6524	{
AnnaBridge	145:64910690c574	6525	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
AnnaBridge	145:64910690c574	6526	}
AnnaBridge	145:64910690c574	6527
AnnaBridge	145:64910690c574	6528	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
AnnaBridge	145:64910690c574	6529	/**
AnnaBridge	145:64910690c574	6530	* @brief Get SAIPLL division factor for PLLSAIDIVR
AnnaBridge	145:64910690c574	6531	* @note used for LTDC domain clock
AnnaBridge	145:64910690c574	6532	* @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
AnnaBridge	145:64910690c574	6533	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	6534	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	145:64910690c574	6535	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	145:64910690c574	6536	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	145:64910690c574	6537	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	145:64910690c574	6538	*/
AnnaBridge	145:64910690c574	6539	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
AnnaBridge	145:64910690c574	6540	{
AnnaBridge	145:64910690c574	6541	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
AnnaBridge	145:64910690c574	6542	}
AnnaBridge	145:64910690c574	6543	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
AnnaBridge	145:64910690c574	6544
AnnaBridge	145:64910690c574	6545	/**
AnnaBridge	145:64910690c574	6546	* @}
AnnaBridge	145:64910690c574	6547	*/
AnnaBridge	145:64910690c574	6548	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	6549
AnnaBridge	145:64910690c574	6550	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	145:64910690c574	6551	* @{
AnnaBridge	145:64910690c574	6552	*/
AnnaBridge	145:64910690c574	6553
AnnaBridge	145:64910690c574	6554	/**
AnnaBridge	145:64910690c574	6555	* @brief Clear LSI ready interrupt flag
AnnaBridge	145:64910690c574	6556	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	145:64910690c574	6557	* @retval None
AnnaBridge	145:64910690c574	6558	*/
AnnaBridge	145:64910690c574	6559	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	145:64910690c574	6560	{
AnnaBridge	145:64910690c574	6561	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	145:64910690c574	6562	}
AnnaBridge	145:64910690c574	6563
AnnaBridge	145:64910690c574	6564	/**
AnnaBridge	145:64910690c574	6565	* @brief Clear LSE ready interrupt flag
AnnaBridge	145:64910690c574	6566	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	145:64910690c574	6567	* @retval None
AnnaBridge	145:64910690c574	6568	*/
AnnaBridge	145:64910690c574	6569	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	145:64910690c574	6570	{
AnnaBridge	145:64910690c574	6571	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	145:64910690c574	6572	}
AnnaBridge	145:64910690c574	6573
AnnaBridge	145:64910690c574	6574	/**
AnnaBridge	145:64910690c574	6575	* @brief Clear HSI ready interrupt flag
AnnaBridge	145:64910690c574	6576	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	145:64910690c574	6577	* @retval None
AnnaBridge	145:64910690c574	6578	*/
AnnaBridge	145:64910690c574	6579	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	145:64910690c574	6580	{
AnnaBridge	145:64910690c574	6581	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	145:64910690c574	6582	}
AnnaBridge	145:64910690c574	6583
AnnaBridge	145:64910690c574	6584	/**
AnnaBridge	145:64910690c574	6585	* @brief Clear HSE ready interrupt flag
AnnaBridge	145:64910690c574	6586	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	145:64910690c574	6587	* @retval None
AnnaBridge	145:64910690c574	6588	*/
AnnaBridge	145:64910690c574	6589	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	145:64910690c574	6590	{
AnnaBridge	145:64910690c574	6591	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	145:64910690c574	6592	}
AnnaBridge	145:64910690c574	6593
AnnaBridge	145:64910690c574	6594	/**
AnnaBridge	145:64910690c574	6595	* @brief Clear PLL ready interrupt flag
AnnaBridge	145:64910690c574	6596	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	145:64910690c574	6597	* @retval None
AnnaBridge	145:64910690c574	6598	*/
AnnaBridge	145:64910690c574	6599	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	145:64910690c574	6600	{
AnnaBridge	145:64910690c574	6601	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	145:64910690c574	6602	}
AnnaBridge	145:64910690c574	6603
AnnaBridge	145:64910690c574	6604	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	6605	/**
AnnaBridge	145:64910690c574	6606	* @brief Clear PLLI2S ready interrupt flag
AnnaBridge	145:64910690c574	6607	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
AnnaBridge	145:64910690c574	6608	* @retval None
AnnaBridge	145:64910690c574	6609	*/
AnnaBridge	145:64910690c574	6610	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	6611	{
AnnaBridge	145:64910690c574	6612	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
AnnaBridge	145:64910690c574	6613	}
AnnaBridge	145:64910690c574	6614
AnnaBridge	145:64910690c574	6615	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	6616
AnnaBridge	145:64910690c574	6617	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	6618	/**
AnnaBridge	145:64910690c574	6619	* @brief Clear PLLSAI ready interrupt flag
AnnaBridge	145:64910690c574	6620	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
AnnaBridge	145:64910690c574	6621	* @retval None
AnnaBridge	145:64910690c574	6622	*/
AnnaBridge	145:64910690c574	6623	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
AnnaBridge	145:64910690c574	6624	{
AnnaBridge	145:64910690c574	6625	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
AnnaBridge	145:64910690c574	6626	}
AnnaBridge	145:64910690c574	6627
AnnaBridge	145:64910690c574	6628	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	6629
AnnaBridge	145:64910690c574	6630	/**
AnnaBridge	145:64910690c574	6631	* @brief Clear Clock security system interrupt flag
AnnaBridge	145:64910690c574	6632	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	145:64910690c574	6633	* @retval None
AnnaBridge	145:64910690c574	6634	*/
AnnaBridge	145:64910690c574	6635	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	145:64910690c574	6636	{
AnnaBridge	145:64910690c574	6637	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	145:64910690c574	6638	}
AnnaBridge	145:64910690c574	6639
AnnaBridge	145:64910690c574	6640	/**
AnnaBridge	145:64910690c574	6641	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	145:64910690c574	6642	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	145:64910690c574	6643	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6644	*/
AnnaBridge	145:64910690c574	6645	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	145:64910690c574	6646	{
AnnaBridge	145:64910690c574	6647	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	145:64910690c574	6648	}
AnnaBridge	145:64910690c574	6649
AnnaBridge	145:64910690c574	6650	/**
AnnaBridge	145:64910690c574	6651	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	145:64910690c574	6652	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	145:64910690c574	6653	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6654	*/
AnnaBridge	145:64910690c574	6655	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	145:64910690c574	6656	{
AnnaBridge	145:64910690c574	6657	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	145:64910690c574	6658	}
AnnaBridge	145:64910690c574	6659
AnnaBridge	145:64910690c574	6660	/**
AnnaBridge	145:64910690c574	6661	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	145:64910690c574	6662	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	145:64910690c574	6663	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6664	*/
AnnaBridge	145:64910690c574	6665	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	145:64910690c574	6666	{
AnnaBridge	145:64910690c574	6667	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	145:64910690c574	6668	}
AnnaBridge	145:64910690c574	6669
AnnaBridge	145:64910690c574	6670	/**
AnnaBridge	145:64910690c574	6671	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	145:64910690c574	6672	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	145:64910690c574	6673	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6674	*/
AnnaBridge	145:64910690c574	6675	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	145:64910690c574	6676	{
AnnaBridge	145:64910690c574	6677	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	145:64910690c574	6678	}
AnnaBridge	145:64910690c574	6679
AnnaBridge	145:64910690c574	6680	/**
AnnaBridge	145:64910690c574	6681	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	145:64910690c574	6682	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	145:64910690c574	6683	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6684	*/
AnnaBridge	145:64910690c574	6685	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	145:64910690c574	6686	{
AnnaBridge	145:64910690c574	6687	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	145:64910690c574	6688	}
AnnaBridge	145:64910690c574	6689
AnnaBridge	145:64910690c574	6690	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	6691	/**
AnnaBridge	145:64910690c574	6692	* @brief Check if PLLI2S ready interrupt occurred or not
AnnaBridge	145:64910690c574	6693	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
AnnaBridge	145:64910690c574	6694	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6695	*/
AnnaBridge	145:64910690c574	6696	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	6697	{
AnnaBridge	145:64910690c574	6698	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
AnnaBridge	145:64910690c574	6699	}
AnnaBridge	145:64910690c574	6700	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	6701
AnnaBridge	145:64910690c574	6702	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	6703	/**
AnnaBridge	145:64910690c574	6704	* @brief Check if PLLSAI ready interrupt occurred or not
AnnaBridge	145:64910690c574	6705	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
AnnaBridge	145:64910690c574	6706	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6707	*/
AnnaBridge	145:64910690c574	6708	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
AnnaBridge	145:64910690c574	6709	{
AnnaBridge	145:64910690c574	6710	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
AnnaBridge	145:64910690c574	6711	}
AnnaBridge	145:64910690c574	6712	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	6713
AnnaBridge	145:64910690c574	6714	/**
AnnaBridge	145:64910690c574	6715	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	145:64910690c574	6716	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	145:64910690c574	6717	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6718	*/
AnnaBridge	145:64910690c574	6719	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	145:64910690c574	6720	{
AnnaBridge	145:64910690c574	6721	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	145:64910690c574	6722	}
AnnaBridge	145:64910690c574	6723
AnnaBridge	145:64910690c574	6724	/**
AnnaBridge	145:64910690c574	6725	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	145:64910690c574	6726	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	145:64910690c574	6727	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6728	*/
AnnaBridge	145:64910690c574	6729	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	145:64910690c574	6730	{
AnnaBridge	145:64910690c574	6731	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	145:64910690c574	6732	}
AnnaBridge	145:64910690c574	6733
AnnaBridge	145:64910690c574	6734	/**
AnnaBridge	145:64910690c574	6735	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	145:64910690c574	6736	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	145:64910690c574	6737	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6738	*/
AnnaBridge	145:64910690c574	6739	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	145:64910690c574	6740	{
AnnaBridge	145:64910690c574	6741	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	145:64910690c574	6742	}
AnnaBridge	145:64910690c574	6743
AnnaBridge	145:64910690c574	6744	/**
AnnaBridge	145:64910690c574	6745	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	145:64910690c574	6746	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	145:64910690c574	6747	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6748	*/
AnnaBridge	145:64910690c574	6749	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	145:64910690c574	6750	{
AnnaBridge	145:64910690c574	6751	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	145:64910690c574	6752	}
AnnaBridge	145:64910690c574	6753
AnnaBridge	145:64910690c574	6754	/**
AnnaBridge	145:64910690c574	6755	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	145:64910690c574	6756	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	145:64910690c574	6757	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6758	*/
AnnaBridge	145:64910690c574	6759	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	145:64910690c574	6760	{
AnnaBridge	145:64910690c574	6761	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	145:64910690c574	6762	}
AnnaBridge	145:64910690c574	6763
AnnaBridge	145:64910690c574	6764	/**
AnnaBridge	145:64910690c574	6765	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	145:64910690c574	6766	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	145:64910690c574	6767	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6768	*/
AnnaBridge	145:64910690c574	6769	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	145:64910690c574	6770	{
AnnaBridge	145:64910690c574	6771	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	145:64910690c574	6772	}
AnnaBridge	145:64910690c574	6773
AnnaBridge	145:64910690c574	6774	/**
AnnaBridge	145:64910690c574	6775	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	145:64910690c574	6776	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	145:64910690c574	6777	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6778	*/
AnnaBridge	145:64910690c574	6779	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	145:64910690c574	6780	{
AnnaBridge	145:64910690c574	6781	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	145:64910690c574	6782	}
AnnaBridge	145:64910690c574	6783
AnnaBridge	145:64910690c574	6784	#if defined(RCC_CSR_BORRSTF)
AnnaBridge	145:64910690c574	6785	/**
AnnaBridge	145:64910690c574	6786	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	145:64910690c574	6787	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	145:64910690c574	6788	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6789	*/
AnnaBridge	145:64910690c574	6790	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	145:64910690c574	6791	{
AnnaBridge	145:64910690c574	6792	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	145:64910690c574	6793	}
AnnaBridge	145:64910690c574	6794	#endif /* RCC_CSR_BORRSTF */
AnnaBridge	145:64910690c574	6795
AnnaBridge	145:64910690c574	6796	/**
AnnaBridge	145:64910690c574	6797	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	145:64910690c574	6798	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	145:64910690c574	6799	* @retval None
AnnaBridge	145:64910690c574	6800	*/
AnnaBridge	145:64910690c574	6801	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	145:64910690c574	6802	{
AnnaBridge	145:64910690c574	6803	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	145:64910690c574	6804	}
AnnaBridge	145:64910690c574	6805
AnnaBridge	145:64910690c574	6806	/**
AnnaBridge	145:64910690c574	6807	* @}
AnnaBridge	145:64910690c574	6808	*/
AnnaBridge	145:64910690c574	6809
AnnaBridge	145:64910690c574	6810	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	145:64910690c574	6811	* @{
AnnaBridge	145:64910690c574	6812	*/
AnnaBridge	145:64910690c574	6813
AnnaBridge	145:64910690c574	6814	/**
AnnaBridge	145:64910690c574	6815	* @brief Enable LSI ready interrupt
AnnaBridge	145:64910690c574	6816	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	145:64910690c574	6817	* @retval None
AnnaBridge	145:64910690c574	6818	*/
AnnaBridge	145:64910690c574	6819	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	145:64910690c574	6820	{
AnnaBridge	145:64910690c574	6821	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	145:64910690c574	6822	}
AnnaBridge	145:64910690c574	6823
AnnaBridge	145:64910690c574	6824	/**
AnnaBridge	145:64910690c574	6825	* @brief Enable LSE ready interrupt
AnnaBridge	145:64910690c574	6826	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	145:64910690c574	6827	* @retval None
AnnaBridge	145:64910690c574	6828	*/
AnnaBridge	145:64910690c574	6829	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	145:64910690c574	6830	{
AnnaBridge	145:64910690c574	6831	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	145:64910690c574	6832	}
AnnaBridge	145:64910690c574	6833
AnnaBridge	145:64910690c574	6834	/**
AnnaBridge	145:64910690c574	6835	* @brief Enable HSI ready interrupt
AnnaBridge	145:64910690c574	6836	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	145:64910690c574	6837	* @retval None
AnnaBridge	145:64910690c574	6838	*/
AnnaBridge	145:64910690c574	6839	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	145:64910690c574	6840	{
AnnaBridge	145:64910690c574	6841	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	145:64910690c574	6842	}
AnnaBridge	145:64910690c574	6843
AnnaBridge	145:64910690c574	6844	/**
AnnaBridge	145:64910690c574	6845	* @brief Enable HSE ready interrupt
AnnaBridge	145:64910690c574	6846	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	145:64910690c574	6847	* @retval None
AnnaBridge	145:64910690c574	6848	*/
AnnaBridge	145:64910690c574	6849	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	145:64910690c574	6850	{
AnnaBridge	145:64910690c574	6851	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	145:64910690c574	6852	}
AnnaBridge	145:64910690c574	6853
AnnaBridge	145:64910690c574	6854	/**
AnnaBridge	145:64910690c574	6855	* @brief Enable PLL ready interrupt
AnnaBridge	145:64910690c574	6856	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	145:64910690c574	6857	* @retval None
AnnaBridge	145:64910690c574	6858	*/
AnnaBridge	145:64910690c574	6859	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	145:64910690c574	6860	{
AnnaBridge	145:64910690c574	6861	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	145:64910690c574	6862	}
AnnaBridge	145:64910690c574	6863
AnnaBridge	145:64910690c574	6864	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	6865	/**
AnnaBridge	145:64910690c574	6866	* @brief Enable PLLI2S ready interrupt
AnnaBridge	145:64910690c574	6867	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
AnnaBridge	145:64910690c574	6868	* @retval None
AnnaBridge	145:64910690c574	6869	*/
AnnaBridge	145:64910690c574	6870	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	6871	{
AnnaBridge	145:64910690c574	6872	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	145:64910690c574	6873	}
AnnaBridge	145:64910690c574	6874	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	6875
AnnaBridge	145:64910690c574	6876	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	6877	/**
AnnaBridge	145:64910690c574	6878	* @brief Enable PLLSAI ready interrupt
AnnaBridge	145:64910690c574	6879	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
AnnaBridge	145:64910690c574	6880	* @retval None
AnnaBridge	145:64910690c574	6881	*/
AnnaBridge	145:64910690c574	6882	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
AnnaBridge	145:64910690c574	6883	{
AnnaBridge	145:64910690c574	6884	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
AnnaBridge	145:64910690c574	6885	}
AnnaBridge	145:64910690c574	6886	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	6887
AnnaBridge	145:64910690c574	6888	/**
AnnaBridge	145:64910690c574	6889	* @brief Disable LSI ready interrupt
AnnaBridge	145:64910690c574	6890	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	145:64910690c574	6891	* @retval None
AnnaBridge	145:64910690c574	6892	*/
AnnaBridge	145:64910690c574	6893	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	145:64910690c574	6894	{
AnnaBridge	145:64910690c574	6895	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	145:64910690c574	6896	}
AnnaBridge	145:64910690c574	6897
AnnaBridge	145:64910690c574	6898	/**
AnnaBridge	145:64910690c574	6899	* @brief Disable LSE ready interrupt
AnnaBridge	145:64910690c574	6900	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	145:64910690c574	6901	* @retval None
AnnaBridge	145:64910690c574	6902	*/
AnnaBridge	145:64910690c574	6903	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	145:64910690c574	6904	{
AnnaBridge	145:64910690c574	6905	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	145:64910690c574	6906	}
AnnaBridge	145:64910690c574	6907
AnnaBridge	145:64910690c574	6908	/**
AnnaBridge	145:64910690c574	6909	* @brief Disable HSI ready interrupt
AnnaBridge	145:64910690c574	6910	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	145:64910690c574	6911	* @retval None
AnnaBridge	145:64910690c574	6912	*/
AnnaBridge	145:64910690c574	6913	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	145:64910690c574	6914	{
AnnaBridge	145:64910690c574	6915	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	145:64910690c574	6916	}
AnnaBridge	145:64910690c574	6917
AnnaBridge	145:64910690c574	6918	/**
AnnaBridge	145:64910690c574	6919	* @brief Disable HSE ready interrupt
AnnaBridge	145:64910690c574	6920	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	145:64910690c574	6921	* @retval None
AnnaBridge	145:64910690c574	6922	*/
AnnaBridge	145:64910690c574	6923	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	145:64910690c574	6924	{
AnnaBridge	145:64910690c574	6925	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	145:64910690c574	6926	}
AnnaBridge	145:64910690c574	6927
AnnaBridge	145:64910690c574	6928	/**
AnnaBridge	145:64910690c574	6929	* @brief Disable PLL ready interrupt
AnnaBridge	145:64910690c574	6930	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	145:64910690c574	6931	* @retval None
AnnaBridge	145:64910690c574	6932	*/
AnnaBridge	145:64910690c574	6933	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	145:64910690c574	6934	{
AnnaBridge	145:64910690c574	6935	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	145:64910690c574	6936	}
AnnaBridge	145:64910690c574	6937
AnnaBridge	145:64910690c574	6938	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	6939	/**
AnnaBridge	145:64910690c574	6940	* @brief Disable PLLI2S ready interrupt
AnnaBridge	145:64910690c574	6941	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
AnnaBridge	145:64910690c574	6942	* @retval None
AnnaBridge	145:64910690c574	6943	*/
AnnaBridge	145:64910690c574	6944	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	6945	{
AnnaBridge	145:64910690c574	6946	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	145:64910690c574	6947	}
AnnaBridge	145:64910690c574	6948
AnnaBridge	145:64910690c574	6949	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	6950
AnnaBridge	145:64910690c574	6951	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	6952	/**
AnnaBridge	145:64910690c574	6953	* @brief Disable PLLSAI ready interrupt
AnnaBridge	145:64910690c574	6954	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
AnnaBridge	145:64910690c574	6955	* @retval None
AnnaBridge	145:64910690c574	6956	*/
AnnaBridge	145:64910690c574	6957	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
AnnaBridge	145:64910690c574	6958	{
AnnaBridge	145:64910690c574	6959	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
AnnaBridge	145:64910690c574	6960	}
AnnaBridge	145:64910690c574	6961	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	6962
AnnaBridge	145:64910690c574	6963	/**
AnnaBridge	145:64910690c574	6964	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	6965	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	145:64910690c574	6966	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6967	*/
AnnaBridge	145:64910690c574	6968	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	145:64910690c574	6969	{
AnnaBridge	145:64910690c574	6970	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	145:64910690c574	6971	}
AnnaBridge	145:64910690c574	6972
AnnaBridge	145:64910690c574	6973	/**
AnnaBridge	145:64910690c574	6974	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	6975	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	145:64910690c574	6976	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6977	*/
AnnaBridge	145:64910690c574	6978	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	145:64910690c574	6979	{
AnnaBridge	145:64910690c574	6980	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	145:64910690c574	6981	}
AnnaBridge	145:64910690c574	6982
AnnaBridge	145:64910690c574	6983	/**
AnnaBridge	145:64910690c574	6984	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	6985	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	145:64910690c574	6986	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6987	*/
AnnaBridge	145:64910690c574	6988	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	145:64910690c574	6989	{
AnnaBridge	145:64910690c574	6990	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	145:64910690c574	6991	}
AnnaBridge	145:64910690c574	6992
AnnaBridge	145:64910690c574	6993	/**
AnnaBridge	145:64910690c574	6994	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	6995	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	145:64910690c574	6996	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	6997	*/
AnnaBridge	145:64910690c574	6998	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	145:64910690c574	6999	{
AnnaBridge	145:64910690c574	7000	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	145:64910690c574	7001	}
AnnaBridge	145:64910690c574	7002
AnnaBridge	145:64910690c574	7003	/**
AnnaBridge	145:64910690c574	7004	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	7005	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	145:64910690c574	7006	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	7007	*/
AnnaBridge	145:64910690c574	7008	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	145:64910690c574	7009	{
AnnaBridge	145:64910690c574	7010	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	145:64910690c574	7011	}
AnnaBridge	145:64910690c574	7012
AnnaBridge	145:64910690c574	7013	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	145:64910690c574	7014	/**
AnnaBridge	145:64910690c574	7015	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	7016	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
AnnaBridge	145:64910690c574	7017	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	7018	*/
AnnaBridge	145:64910690c574	7019	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	7020	{
AnnaBridge	145:64910690c574	7021	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
AnnaBridge	145:64910690c574	7022	}
AnnaBridge	145:64910690c574	7023
AnnaBridge	145:64910690c574	7024	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	145:64910690c574	7025
AnnaBridge	145:64910690c574	7026	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	145:64910690c574	7027	/**
AnnaBridge	145:64910690c574	7028	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	7029	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
AnnaBridge	145:64910690c574	7030	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	7031	*/
AnnaBridge	145:64910690c574	7032	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
AnnaBridge	145:64910690c574	7033	{
AnnaBridge	145:64910690c574	7034	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
AnnaBridge	145:64910690c574	7035	}
AnnaBridge	145:64910690c574	7036	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	145:64910690c574	7037
AnnaBridge	145:64910690c574	7038	/**
AnnaBridge	145:64910690c574	7039	* @}
AnnaBridge	145:64910690c574	7040	*/
AnnaBridge	145:64910690c574	7041
AnnaBridge	145:64910690c574	7042	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	7043	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	145:64910690c574	7044	* @{
AnnaBridge	145:64910690c574	7045	*/
AnnaBridge	145:64910690c574	7046	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	145:64910690c574	7047	/**
AnnaBridge	145:64910690c574	7048	* @}
AnnaBridge	145:64910690c574	7049	*/
AnnaBridge	145:64910690c574	7050
AnnaBridge	145:64910690c574	7051	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	145:64910690c574	7052	* @{
AnnaBridge	145:64910690c574	7053	*/
AnnaBridge	145:64910690c574	7054	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	145:64910690c574	7055	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	7056	uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
AnnaBridge	145:64910690c574	7057	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	7058	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	7059	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	145:64910690c574	7060	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	7061	#if defined(SAI1)
AnnaBridge	145:64910690c574	7062	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	145:64910690c574	7063	#endif /* SAI1 */
AnnaBridge	145:64910690c574	7064	#if defined(SDIO)
AnnaBridge	145:64910690c574	7065	uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
AnnaBridge	145:64910690c574	7066	#endif /* SDIO */
AnnaBridge	145:64910690c574	7067	#if defined(RNG)
AnnaBridge	145:64910690c574	7068	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
AnnaBridge	145:64910690c574	7069	#endif /* RNG */
AnnaBridge	145:64910690c574	7070	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	7071	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	145:64910690c574	7072	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
AnnaBridge	145:64910690c574	7073	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	7074	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	145:64910690c574	7075	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
AnnaBridge	145:64910690c574	7076	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	7077	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
AnnaBridge	145:64910690c574	7078	#if defined(CEC)
AnnaBridge	145:64910690c574	7079	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
AnnaBridge	145:64910690c574	7080	#endif /* CEC */
AnnaBridge	145:64910690c574	7081	#if defined(LTDC)
AnnaBridge	145:64910690c574	7082	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
AnnaBridge	145:64910690c574	7083	#endif /* LTDC */
AnnaBridge	145:64910690c574	7084	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	7085	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
AnnaBridge	145:64910690c574	7086	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	7087	#if defined(DSI)
AnnaBridge	145:64910690c574	7088	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
AnnaBridge	145:64910690c574	7089	#endif /* DSI */
AnnaBridge	145:64910690c574	7090	/**
AnnaBridge	145:64910690c574	7091	* @}
AnnaBridge	145:64910690c574	7092	*/
AnnaBridge	145:64910690c574	7093	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	7094
AnnaBridge	145:64910690c574	7095	/**
AnnaBridge	145:64910690c574	7096	* @}
AnnaBridge	145:64910690c574	7097	*/
AnnaBridge	145:64910690c574	7098
AnnaBridge	145:64910690c574	7099	/**
AnnaBridge	145:64910690c574	7100	* @}
AnnaBridge	145:64910690c574	7101	*/
AnnaBridge	145:64910690c574	7102
AnnaBridge	145:64910690c574	7103	#endif /* defined(RCC) */
AnnaBridge	145:64910690c574	7104
AnnaBridge	145:64910690c574	7105	/**
AnnaBridge	145:64910690c574	7106	* @}
AnnaBridge	145:64910690c574	7107	*/
AnnaBridge	145:64910690c574	7108
AnnaBridge	145:64910690c574	7109	#ifdef __cplusplus
AnnaBridge	145:64910690c574	7110	}
AnnaBridge	145:64910690c574	7111	#endif
AnnaBridge	145:64910690c574	7112
AnnaBridge	145:64910690c574	7113	#endif /* __STM32F4xx_LL_RCC_H */
AnnaBridge	145:64910690c574	7114
AnnaBridge	145:64910690c574	7115	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/