mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F412ZG/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_MTB_MTS_DRAGONFLY/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@163:e59c8e839560

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/**
AnnaBridge	161:aa5281ff4a02	2	******************************************************************************
AnnaBridge	161:aa5281ff4a02	3	* @file stm32f4xx_ll_fmc.h
AnnaBridge	161:aa5281ff4a02	4	* @author MCD Application Team
AnnaBridge	161:aa5281ff4a02	5	* @brief Header file of FMC HAL module.
AnnaBridge	161:aa5281ff4a02	6	******************************************************************************
AnnaBridge	161:aa5281ff4a02	7	* @attention
AnnaBridge	161:aa5281ff4a02	8	*
AnnaBridge	161:aa5281ff4a02	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	161:aa5281ff4a02	10	*
AnnaBridge	161:aa5281ff4a02	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	161:aa5281ff4a02	12	* are permitted provided that the following conditions are met:
AnnaBridge	161:aa5281ff4a02	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	161:aa5281ff4a02	14	* this list of conditions and the following disclaimer.
AnnaBridge	161:aa5281ff4a02	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	161:aa5281ff4a02	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	161:aa5281ff4a02	17	* and/or other materials provided with the distribution.
AnnaBridge	161:aa5281ff4a02	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	161:aa5281ff4a02	19	* may be used to endorse or promote products derived from this software
AnnaBridge	161:aa5281ff4a02	20	* without specific prior written permission.
AnnaBridge	161:aa5281ff4a02	21	*
AnnaBridge	161:aa5281ff4a02	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	161:aa5281ff4a02	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	161:aa5281ff4a02	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	161:aa5281ff4a02	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	161:aa5281ff4a02	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	161:aa5281ff4a02	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	161:aa5281ff4a02	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	161:aa5281ff4a02	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	161:aa5281ff4a02	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	161:aa5281ff4a02	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	161:aa5281ff4a02	32	*
AnnaBridge	161:aa5281ff4a02	33	******************************************************************************
AnnaBridge	161:aa5281ff4a02	34	*/
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	161:aa5281ff4a02	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	161:aa5281ff4a02	37	#ifndef __STM32F4xx_LL_FMC_H
AnnaBridge	161:aa5281ff4a02	38	#define __STM32F4xx_LL_FMC_H
AnnaBridge	161:aa5281ff4a02	39
AnnaBridge	161:aa5281ff4a02	40	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	41	extern "C" {
AnnaBridge	161:aa5281ff4a02	42	#endif
AnnaBridge	161:aa5281ff4a02	43
AnnaBridge	161:aa5281ff4a02	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	161:aa5281ff4a02	46
AnnaBridge	161:aa5281ff4a02	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	161:aa5281ff4a02	48	* @{
AnnaBridge	161:aa5281ff4a02	49	*/
AnnaBridge	161:aa5281ff4a02	50
AnnaBridge	161:aa5281ff4a02	51	/** @addtogroup FMC_LL
AnnaBridge	161:aa5281ff4a02	52	* @{
AnnaBridge	161:aa5281ff4a02	53	*/
AnnaBridge	161:aa5281ff4a02	54	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	161:aa5281ff4a02	55	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	56	/* Private types -------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	57	/** @defgroup FMC_LL_Private_Types FMC Private Types
AnnaBridge	161:aa5281ff4a02	58	* @{
AnnaBridge	161:aa5281ff4a02	59	*/
AnnaBridge	161:aa5281ff4a02	60
AnnaBridge	161:aa5281ff4a02	61	/**
AnnaBridge	161:aa5281ff4a02	62	* @brief FMC NORSRAM Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	63	*/
AnnaBridge	161:aa5281ff4a02	64	typedef struct
AnnaBridge	161:aa5281ff4a02	65	{
AnnaBridge	161:aa5281ff4a02	66	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	161:aa5281ff4a02	67	This parameter can be a value of @ref FMC_NORSRAM_Bank */
AnnaBridge	161:aa5281ff4a02	68
AnnaBridge	161:aa5281ff4a02	69	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	161:aa5281ff4a02	70	multiplexed on the data bus or not.
AnnaBridge	161:aa5281ff4a02	71	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
AnnaBridge	161:aa5281ff4a02	72
AnnaBridge	161:aa5281ff4a02	73	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	161:aa5281ff4a02	74	the corresponding memory device.
AnnaBridge	161:aa5281ff4a02	75	This parameter can be a value of @ref FMC_Memory_Type */
AnnaBridge	161:aa5281ff4a02	76
AnnaBridge	161:aa5281ff4a02	77	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	161:aa5281ff4a02	78	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
AnnaBridge	161:aa5281ff4a02	79
AnnaBridge	161:aa5281ff4a02	80	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	161:aa5281ff4a02	81	valid only with synchronous burst Flash memories.
AnnaBridge	161:aa5281ff4a02	82	This parameter can be a value of @ref FMC_Burst_Access_Mode */
AnnaBridge	161:aa5281ff4a02	83
AnnaBridge	161:aa5281ff4a02	84	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	161:aa5281ff4a02	85	the Flash memory in burst mode.
AnnaBridge	161:aa5281ff4a02	86	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
AnnaBridge	161:aa5281ff4a02	87
AnnaBridge	161:aa5281ff4a02	88	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	161:aa5281ff4a02	89	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	161:aa5281ff4a02	90	This parameter can be a value of @ref FMC_Wrap_Mode
AnnaBridge	161:aa5281ff4a02	91	This mode is not available for the STM32F446/467/479xx devices */
AnnaBridge	161:aa5281ff4a02	92
AnnaBridge	161:aa5281ff4a02	93	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	161:aa5281ff4a02	94	clock cycle before the wait state or during the wait state,
AnnaBridge	161:aa5281ff4a02	95	valid only when accessing memories in burst mode.
AnnaBridge	161:aa5281ff4a02	96	This parameter can be a value of @ref FMC_Wait_Timing */
AnnaBridge	161:aa5281ff4a02	97
AnnaBridge	161:aa5281ff4a02	98	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
AnnaBridge	161:aa5281ff4a02	99	This parameter can be a value of @ref FMC_Write_Operation */
AnnaBridge	161:aa5281ff4a02	100
AnnaBridge	161:aa5281ff4a02	101	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	161:aa5281ff4a02	102	signal, valid for Flash memory access in burst mode.
AnnaBridge	161:aa5281ff4a02	103	This parameter can be a value of @ref FMC_Wait_Signal */
AnnaBridge	161:aa5281ff4a02	104
AnnaBridge	161:aa5281ff4a02	105	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	161:aa5281ff4a02	106	This parameter can be a value of @ref FMC_Extended_Mode */
AnnaBridge	161:aa5281ff4a02	107
AnnaBridge	161:aa5281ff4a02	108	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	161:aa5281ff4a02	109	valid only with asynchronous Flash memories.
AnnaBridge	161:aa5281ff4a02	110	This parameter can be a value of @ref FMC_AsynchronousWait */
AnnaBridge	161:aa5281ff4a02	111
AnnaBridge	161:aa5281ff4a02	112	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	161:aa5281ff4a02	113	This parameter can be a value of @ref FMC_Write_Burst */
AnnaBridge	161:aa5281ff4a02	114
AnnaBridge	161:aa5281ff4a02	115	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	161:aa5281ff4a02	116	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	161:aa5281ff4a02	117	through FMC_BCR2..4 registers.
AnnaBridge	161:aa5281ff4a02	118	This parameter can be a value of @ref FMC_Continous_Clock */
AnnaBridge	161:aa5281ff4a02	119
AnnaBridge	161:aa5281ff4a02	120	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	161:aa5281ff4a02	121	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	161:aa5281ff4a02	122	through FMC_BCR2..4 registers.
AnnaBridge	161:aa5281ff4a02	123	This parameter can be a value of @ref FMC_Write_FIFO
AnnaBridge	161:aa5281ff4a02	124	This mode is available only for the STM32F446/469/479xx devices */
AnnaBridge	161:aa5281ff4a02	125
AnnaBridge	161:aa5281ff4a02	126	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	161:aa5281ff4a02	127	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	161:aa5281ff4a02	128	}FMC_NORSRAM_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	129
AnnaBridge	161:aa5281ff4a02	130	/**
AnnaBridge	161:aa5281ff4a02	131	* @brief FMC NORSRAM Timing parameters structure definition
AnnaBridge	161:aa5281ff4a02	132	*/
AnnaBridge	161:aa5281ff4a02	133	typedef struct
AnnaBridge	161:aa5281ff4a02	134	{
AnnaBridge	161:aa5281ff4a02	135	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	136	the duration of the address setup time.
AnnaBridge	161:aa5281ff4a02	137	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	138	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	139
AnnaBridge	161:aa5281ff4a02	140	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	141	the duration of the address hold time.
AnnaBridge	161:aa5281ff4a02	142	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	143	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	144
AnnaBridge	161:aa5281ff4a02	145	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	146	the duration of the data setup time.
AnnaBridge	161:aa5281ff4a02	147	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	161:aa5281ff4a02	148	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	161:aa5281ff4a02	149	NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	150
AnnaBridge	161:aa5281ff4a02	151	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	161:aa5281ff4a02	152	the duration of the bus turnaround.
AnnaBridge	161:aa5281ff4a02	153	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	161:aa5281ff4a02	154	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	161:aa5281ff4a02	155
AnnaBridge	161:aa5281ff4a02	156	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	161:aa5281ff4a02	157	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	161:aa5281ff4a02	158	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	161:aa5281ff4a02	159	accesses. */
AnnaBridge	161:aa5281ff4a02	160
AnnaBridge	161:aa5281ff4a02	161	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	161:aa5281ff4a02	162	to the memory before getting the first data.
AnnaBridge	161:aa5281ff4a02	163	The parameter value depends on the memory type as shown below:
AnnaBridge	161:aa5281ff4a02	164	- It must be set to 0 in case of a CRAM
AnnaBridge	161:aa5281ff4a02	165	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	161:aa5281ff4a02	166	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	161:aa5281ff4a02	167	with synchronous burst mode enable */
AnnaBridge	161:aa5281ff4a02	168
AnnaBridge	161:aa5281ff4a02	169	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	161:aa5281ff4a02	170	This parameter can be a value of @ref FMC_Access_Mode */
AnnaBridge	161:aa5281ff4a02	171	}FMC_NORSRAM_TimingTypeDef;
AnnaBridge	161:aa5281ff4a02	172
AnnaBridge	161:aa5281ff4a02	173	/**
AnnaBridge	161:aa5281ff4a02	174	* @brief FMC NAND Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	175	*/
AnnaBridge	161:aa5281ff4a02	176	typedef struct
AnnaBridge	161:aa5281ff4a02	177	{
AnnaBridge	161:aa5281ff4a02	178	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	161:aa5281ff4a02	179	This parameter can be a value of @ref FMC_NAND_Bank */
AnnaBridge	161:aa5281ff4a02	180
AnnaBridge	161:aa5281ff4a02	181	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	161:aa5281ff4a02	182	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	161:aa5281ff4a02	183
AnnaBridge	161:aa5281ff4a02	184	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	161:aa5281ff4a02	185	This parameter can be any value of @ref FMC_NAND_Data_Width */
AnnaBridge	161:aa5281ff4a02	186
AnnaBridge	161:aa5281ff4a02	187	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	161:aa5281ff4a02	188	This parameter can be any value of @ref FMC_ECC */
AnnaBridge	161:aa5281ff4a02	189
AnnaBridge	161:aa5281ff4a02	190	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	161:aa5281ff4a02	191	This parameter can be any value of @ref FMC_ECC_Page_Size */
AnnaBridge	161:aa5281ff4a02	192
AnnaBridge	161:aa5281ff4a02	193	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	194	delay between CLE low and RE low.
AnnaBridge	161:aa5281ff4a02	195	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	196
AnnaBridge	161:aa5281ff4a02	197	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	198	delay between ALE low and RE low.
AnnaBridge	161:aa5281ff4a02	199	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	200	}FMC_NAND_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	201
AnnaBridge	161:aa5281ff4a02	202	/**
AnnaBridge	161:aa5281ff4a02	203	* @brief FMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	161:aa5281ff4a02	204	*/
AnnaBridge	161:aa5281ff4a02	205	typedef struct
AnnaBridge	161:aa5281ff4a02	206	{
AnnaBridge	161:aa5281ff4a02	207	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	161:aa5281ff4a02	208	the command assertion for NAND-Flash read or write access
AnnaBridge	161:aa5281ff4a02	209	to common/Attribute or I/O memory space (depending on
AnnaBridge	161:aa5281ff4a02	210	the memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	211	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	212
AnnaBridge	161:aa5281ff4a02	213	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	161:aa5281ff4a02	214	command for NAND-Flash read or write access to
AnnaBridge	161:aa5281ff4a02	215	common/Attribute or I/O memory space (depending on the
AnnaBridge	161:aa5281ff4a02	216	memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	217	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	218
AnnaBridge	161:aa5281ff4a02	219	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	161:aa5281ff4a02	220	(and data for write access) after the command de-assertion
AnnaBridge	161:aa5281ff4a02	221	for NAND-Flash read or write access to common/Attribute
AnnaBridge	161:aa5281ff4a02	222	or I/O memory space (depending on the memory space timing
AnnaBridge	161:aa5281ff4a02	223	to be configured).
AnnaBridge	161:aa5281ff4a02	224	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	225
AnnaBridge	161:aa5281ff4a02	226	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	161:aa5281ff4a02	227	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	161:aa5281ff4a02	228	write access to common/Attribute or I/O memory space (depending
AnnaBridge	161:aa5281ff4a02	229	on the memory space timing to be configured).
AnnaBridge	161:aa5281ff4a02	230	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	231	}FMC_NAND_PCC_TimingTypeDef;
AnnaBridge	161:aa5281ff4a02	232
AnnaBridge	161:aa5281ff4a02	233	/**
AnnaBridge	161:aa5281ff4a02	234	* @brief FMC NAND Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	235	*/
AnnaBridge	161:aa5281ff4a02	236	typedef struct
AnnaBridge	161:aa5281ff4a02	237	{
AnnaBridge	161:aa5281ff4a02	238	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	161:aa5281ff4a02	239	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	161:aa5281ff4a02	240
AnnaBridge	161:aa5281ff4a02	241	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	242	delay between CLE low and RE low.
AnnaBridge	161:aa5281ff4a02	243	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	244
AnnaBridge	161:aa5281ff4a02	245	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	161:aa5281ff4a02	246	delay between ALE low and RE low.
AnnaBridge	161:aa5281ff4a02	247	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	161:aa5281ff4a02	248	}FMC_PCCARD_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	249
AnnaBridge	161:aa5281ff4a02	250	/**
AnnaBridge	161:aa5281ff4a02	251	* @brief FMC SDRAM Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	252	*/
AnnaBridge	161:aa5281ff4a02	253	typedef struct
AnnaBridge	161:aa5281ff4a02	254	{
AnnaBridge	161:aa5281ff4a02	255	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
AnnaBridge	161:aa5281ff4a02	256	This parameter can be a value of @ref FMC_SDRAM_Bank */
AnnaBridge	161:aa5281ff4a02	257
AnnaBridge	161:aa5281ff4a02	258	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	161:aa5281ff4a02	259	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
AnnaBridge	161:aa5281ff4a02	260
AnnaBridge	161:aa5281ff4a02	261	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	161:aa5281ff4a02	262	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
AnnaBridge	161:aa5281ff4a02	263
AnnaBridge	161:aa5281ff4a02	264	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
AnnaBridge	161:aa5281ff4a02	265	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
AnnaBridge	161:aa5281ff4a02	266
AnnaBridge	161:aa5281ff4a02	267	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
AnnaBridge	161:aa5281ff4a02	268	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
AnnaBridge	161:aa5281ff4a02	269
AnnaBridge	161:aa5281ff4a02	270	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	271	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
AnnaBridge	161:aa5281ff4a02	272
AnnaBridge	161:aa5281ff4a02	273	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
AnnaBridge	161:aa5281ff4a02	274	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
AnnaBridge	161:aa5281ff4a02	275
AnnaBridge	161:aa5281ff4a02	276	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
AnnaBridge	161:aa5281ff4a02	277	to disable the clock before changing frequency.
AnnaBridge	161:aa5281ff4a02	278	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
AnnaBridge	161:aa5281ff4a02	279
AnnaBridge	161:aa5281ff4a02	280	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
AnnaBridge	161:aa5281ff4a02	281	commands during the CAS latency and stores data in the Read FIFO.
AnnaBridge	161:aa5281ff4a02	282	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
AnnaBridge	161:aa5281ff4a02	283
AnnaBridge	161:aa5281ff4a02	284	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
AnnaBridge	161:aa5281ff4a02	285	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
AnnaBridge	161:aa5281ff4a02	286	}FMC_SDRAM_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	287
AnnaBridge	161:aa5281ff4a02	288	/**
AnnaBridge	161:aa5281ff4a02	289	* @brief FMC SDRAM Timing parameters structure definition
AnnaBridge	161:aa5281ff4a02	290	*/
AnnaBridge	161:aa5281ff4a02	291	typedef struct
AnnaBridge	161:aa5281ff4a02	292	{
AnnaBridge	161:aa5281ff4a02	293	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
AnnaBridge	161:aa5281ff4a02	294	an active or Refresh command in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	295	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	296
AnnaBridge	161:aa5281ff4a02	297	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
AnnaBridge	161:aa5281ff4a02	298	issuing the Activate command in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	300
AnnaBridge	161:aa5281ff4a02	301	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
AnnaBridge	161:aa5281ff4a02	302	cycles.
AnnaBridge	161:aa5281ff4a02	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	304
AnnaBridge	161:aa5281ff4a02	305	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
AnnaBridge	161:aa5281ff4a02	306	and the delay between two consecutive Refresh commands in number of
AnnaBridge	161:aa5281ff4a02	307	memory clock cycles.
AnnaBridge	161:aa5281ff4a02	308	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	309
AnnaBridge	161:aa5281ff4a02	310	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	312
AnnaBridge	161:aa5281ff4a02	313	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
AnnaBridge	161:aa5281ff4a02	314	in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	316
AnnaBridge	161:aa5281ff4a02	317	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
AnnaBridge	161:aa5281ff4a02	318	command in number of memory clock cycles.
AnnaBridge	161:aa5281ff4a02	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	320	}FMC_SDRAM_TimingTypeDef;
AnnaBridge	161:aa5281ff4a02	321
AnnaBridge	161:aa5281ff4a02	322	/**
AnnaBridge	161:aa5281ff4a02	323	* @brief SDRAM command parameters structure definition
AnnaBridge	161:aa5281ff4a02	324	*/
AnnaBridge	161:aa5281ff4a02	325	typedef struct
AnnaBridge	161:aa5281ff4a02	326	{
AnnaBridge	161:aa5281ff4a02	327	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
AnnaBridge	161:aa5281ff4a02	328	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
AnnaBridge	161:aa5281ff4a02	329
AnnaBridge	161:aa5281ff4a02	330	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
AnnaBridge	161:aa5281ff4a02	331	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
AnnaBridge	161:aa5281ff4a02	332
AnnaBridge	161:aa5281ff4a02	333	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
AnnaBridge	161:aa5281ff4a02	334	in auto refresh mode.
AnnaBridge	161:aa5281ff4a02	335	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	161:aa5281ff4a02	336	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
AnnaBridge	161:aa5281ff4a02	337	}FMC_SDRAM_CommandTypeDef;
AnnaBridge	161:aa5281ff4a02	338	/**
AnnaBridge	161:aa5281ff4a02	339	* @}
AnnaBridge	161:aa5281ff4a02	340	*/
AnnaBridge	161:aa5281ff4a02	341
AnnaBridge	161:aa5281ff4a02	342	/* Private constants ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	343	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
AnnaBridge	161:aa5281ff4a02	344	* @{
AnnaBridge	161:aa5281ff4a02	345	*/
AnnaBridge	161:aa5281ff4a02	346
AnnaBridge	161:aa5281ff4a02	347	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
AnnaBridge	161:aa5281ff4a02	348	* @{
AnnaBridge	161:aa5281ff4a02	349	*/
AnnaBridge	161:aa5281ff4a02	350	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
AnnaBridge	161:aa5281ff4a02	351	* @{
AnnaBridge	161:aa5281ff4a02	352	*/
AnnaBridge	161:aa5281ff4a02	353	#define FMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	161:aa5281ff4a02	354	#define FMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	161:aa5281ff4a02	355	#define FMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	161:aa5281ff4a02	356	#define FMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	161:aa5281ff4a02	357	/**
AnnaBridge	161:aa5281ff4a02	358	* @}
AnnaBridge	161:aa5281ff4a02	359	*/
AnnaBridge	161:aa5281ff4a02	360
AnnaBridge	161:aa5281ff4a02	361	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
AnnaBridge	161:aa5281ff4a02	362	* @{
AnnaBridge	161:aa5281ff4a02	363	*/
AnnaBridge	161:aa5281ff4a02	364	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	365	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	366	/**
AnnaBridge	161:aa5281ff4a02	367	* @}
AnnaBridge	161:aa5281ff4a02	368	*/
AnnaBridge	161:aa5281ff4a02	369
AnnaBridge	161:aa5281ff4a02	370	/** @defgroup FMC_Memory_Type FMC Memory Type
AnnaBridge	161:aa5281ff4a02	371	* @{
AnnaBridge	161:aa5281ff4a02	372	*/
AnnaBridge	161:aa5281ff4a02	373	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	161:aa5281ff4a02	374	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge	161:aa5281ff4a02	375	#define FMC_MEMORY_TYPE_NOR 0x00000008U
AnnaBridge	161:aa5281ff4a02	376	/**
AnnaBridge	161:aa5281ff4a02	377	* @}
AnnaBridge	161:aa5281ff4a02	378	*/
AnnaBridge	161:aa5281ff4a02	379
AnnaBridge	161:aa5281ff4a02	380	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
AnnaBridge	161:aa5281ff4a02	381	* @{
AnnaBridge	161:aa5281ff4a02	382	*/
AnnaBridge	161:aa5281ff4a02	383	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	384	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	161:aa5281ff4a02	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	161:aa5281ff4a02	386	/**
AnnaBridge	161:aa5281ff4a02	387	* @}
AnnaBridge	161:aa5281ff4a02	388	*/
AnnaBridge	161:aa5281ff4a02	389
AnnaBridge	161:aa5281ff4a02	390	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
AnnaBridge	161:aa5281ff4a02	391	* @{
AnnaBridge	161:aa5281ff4a02	392	*/
AnnaBridge	161:aa5281ff4a02	393	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge	161:aa5281ff4a02	394	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	395	/**
AnnaBridge	161:aa5281ff4a02	396	* @}
AnnaBridge	161:aa5281ff4a02	397	*/
AnnaBridge	161:aa5281ff4a02	398
AnnaBridge	161:aa5281ff4a02	399	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
AnnaBridge	161:aa5281ff4a02	400	* @{
AnnaBridge	161:aa5281ff4a02	401	*/
AnnaBridge	161:aa5281ff4a02	402	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	403	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
AnnaBridge	161:aa5281ff4a02	404	/**
AnnaBridge	161:aa5281ff4a02	405	* @}
AnnaBridge	161:aa5281ff4a02	406	*/
AnnaBridge	161:aa5281ff4a02	407
AnnaBridge	161:aa5281ff4a02	408	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
AnnaBridge	161:aa5281ff4a02	409	* @{
AnnaBridge	161:aa5281ff4a02	410	*/
AnnaBridge	161:aa5281ff4a02	411	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	161:aa5281ff4a02	412	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
AnnaBridge	161:aa5281ff4a02	413	/**
AnnaBridge	161:aa5281ff4a02	414	* @}
AnnaBridge	161:aa5281ff4a02	415	*/
AnnaBridge	161:aa5281ff4a02	416
AnnaBridge	161:aa5281ff4a02	417	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
AnnaBridge	161:aa5281ff4a02	418	* @{
AnnaBridge	161:aa5281ff4a02	419	*/
AnnaBridge	161:aa5281ff4a02	420	/** @note This mode is not available for the STM32F446/469/479xx devices
AnnaBridge	161:aa5281ff4a02	421	*/
AnnaBridge	161:aa5281ff4a02	422	#define FMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	423	#define FMC_WRAP_MODE_ENABLE 0x00000400U
AnnaBridge	161:aa5281ff4a02	424	/**
AnnaBridge	161:aa5281ff4a02	425	* @}
AnnaBridge	161:aa5281ff4a02	426	*/
AnnaBridge	161:aa5281ff4a02	427
AnnaBridge	161:aa5281ff4a02	428	/** @defgroup FMC_Wait_Timing FMC Wait Timing
AnnaBridge	161:aa5281ff4a02	429	* @{
AnnaBridge	161:aa5281ff4a02	430	*/
AnnaBridge	161:aa5281ff4a02	431	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	161:aa5281ff4a02	432	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
AnnaBridge	161:aa5281ff4a02	433	/**
AnnaBridge	161:aa5281ff4a02	434	* @}
AnnaBridge	161:aa5281ff4a02	435	*/
AnnaBridge	161:aa5281ff4a02	436
AnnaBridge	161:aa5281ff4a02	437	/** @defgroup FMC_Write_Operation FMC Write Operation
AnnaBridge	161:aa5281ff4a02	438	* @{
AnnaBridge	161:aa5281ff4a02	439	*/
AnnaBridge	161:aa5281ff4a02	440	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	441	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
AnnaBridge	161:aa5281ff4a02	442	/**
AnnaBridge	161:aa5281ff4a02	443	* @}
AnnaBridge	161:aa5281ff4a02	444	*/
AnnaBridge	161:aa5281ff4a02	445
AnnaBridge	161:aa5281ff4a02	446	/** @defgroup FMC_Wait_Signal FMC Wait Signal
AnnaBridge	161:aa5281ff4a02	447	* @{
AnnaBridge	161:aa5281ff4a02	448	*/
AnnaBridge	161:aa5281ff4a02	449	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	450	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
AnnaBridge	161:aa5281ff4a02	451	/**
AnnaBridge	161:aa5281ff4a02	452	* @}
AnnaBridge	161:aa5281ff4a02	453	*/
AnnaBridge	161:aa5281ff4a02	454
AnnaBridge	161:aa5281ff4a02	455	/** @defgroup FMC_Extended_Mode FMC Extended Mode
AnnaBridge	161:aa5281ff4a02	456	* @{
AnnaBridge	161:aa5281ff4a02	457	*/
AnnaBridge	161:aa5281ff4a02	458	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	459	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
AnnaBridge	161:aa5281ff4a02	460	/**
AnnaBridge	161:aa5281ff4a02	461	* @}
AnnaBridge	161:aa5281ff4a02	462	*/
AnnaBridge	161:aa5281ff4a02	463
AnnaBridge	161:aa5281ff4a02	464	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
AnnaBridge	161:aa5281ff4a02	465	* @{
AnnaBridge	161:aa5281ff4a02	466	*/
AnnaBridge	161:aa5281ff4a02	467	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	468	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
AnnaBridge	161:aa5281ff4a02	469	/**
AnnaBridge	161:aa5281ff4a02	470	* @}
AnnaBridge	161:aa5281ff4a02	471	*/
AnnaBridge	161:aa5281ff4a02	472
AnnaBridge	161:aa5281ff4a02	473	/** @defgroup FMC_Page_Size FMC Page Size
AnnaBridge	161:aa5281ff4a02	474	* @{
AnnaBridge	161:aa5281ff4a02	475	*/
AnnaBridge	161:aa5281ff4a02	476	#define FMC_PAGE_SIZE_NONE 0x00000000U
AnnaBridge	161:aa5281ff4a02	477	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
AnnaBridge	161:aa5281ff4a02	478	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
AnnaBridge	161:aa5281ff4a02	479	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
AnnaBridge	161:aa5281ff4a02	480	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
AnnaBridge	161:aa5281ff4a02	481	/**
AnnaBridge	161:aa5281ff4a02	482	* @}
AnnaBridge	161:aa5281ff4a02	483	*/
AnnaBridge	161:aa5281ff4a02	484
AnnaBridge	161:aa5281ff4a02	485	/** @defgroup FMC_Write_FIFO FMC Write FIFO
AnnaBridge	161:aa5281ff4a02	486	* @note These values are available only for the STM32F446/469/479xx devices.
AnnaBridge	161:aa5281ff4a02	487	* @{
AnnaBridge	161:aa5281ff4a02	488	*/
AnnaBridge	161:aa5281ff4a02	489	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
AnnaBridge	161:aa5281ff4a02	490	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	491	/**
AnnaBridge	161:aa5281ff4a02	492	* @}
AnnaBridge	161:aa5281ff4a02	493	*/
AnnaBridge	161:aa5281ff4a02	494
AnnaBridge	161:aa5281ff4a02	495	/** @defgroup FMC_Write_Burst FMC Write Burst
AnnaBridge	161:aa5281ff4a02	496	* @{
AnnaBridge	161:aa5281ff4a02	497	*/
AnnaBridge	161:aa5281ff4a02	498	#define FMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	499	#define FMC_WRITE_BURST_ENABLE 0x00080000U
AnnaBridge	161:aa5281ff4a02	500	/**
AnnaBridge	161:aa5281ff4a02	501	* @}
AnnaBridge	161:aa5281ff4a02	502	*/
AnnaBridge	161:aa5281ff4a02	503
AnnaBridge	161:aa5281ff4a02	504	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
AnnaBridge	161:aa5281ff4a02	505	* @{
AnnaBridge	161:aa5281ff4a02	506	*/
AnnaBridge	161:aa5281ff4a02	507	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge	161:aa5281ff4a02	508	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
AnnaBridge	161:aa5281ff4a02	509	/**
AnnaBridge	161:aa5281ff4a02	510	* @}
AnnaBridge	161:aa5281ff4a02	511	*/
AnnaBridge	161:aa5281ff4a02	512
AnnaBridge	161:aa5281ff4a02	513	/** @defgroup FMC_Access_Mode FMC Access Mode
AnnaBridge	161:aa5281ff4a02	514	* @{
AnnaBridge	161:aa5281ff4a02	515	*/
AnnaBridge	161:aa5281ff4a02	516	#define FMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	161:aa5281ff4a02	517	#define FMC_ACCESS_MODE_B 0x10000000U
AnnaBridge	161:aa5281ff4a02	518	#define FMC_ACCESS_MODE_C 0x20000000U
AnnaBridge	161:aa5281ff4a02	519	#define FMC_ACCESS_MODE_D 0x30000000U
AnnaBridge	161:aa5281ff4a02	520	/**
AnnaBridge	161:aa5281ff4a02	521	* @}
AnnaBridge	161:aa5281ff4a02	522	*/
AnnaBridge	161:aa5281ff4a02	523
AnnaBridge	161:aa5281ff4a02	524	/**
AnnaBridge	161:aa5281ff4a02	525	* @}
AnnaBridge	161:aa5281ff4a02	526	*/
AnnaBridge	161:aa5281ff4a02	527
AnnaBridge	161:aa5281ff4a02	528	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
AnnaBridge	161:aa5281ff4a02	529	* @{
AnnaBridge	161:aa5281ff4a02	530	*/
AnnaBridge	161:aa5281ff4a02	531	/** @defgroup FMC_NAND_Bank FMC NAND Bank
AnnaBridge	161:aa5281ff4a02	532	* @{
AnnaBridge	161:aa5281ff4a02	533	*/
AnnaBridge	161:aa5281ff4a02	534	#define FMC_NAND_BANK2 0x00000010U
AnnaBridge	161:aa5281ff4a02	535	#define FMC_NAND_BANK3 0x00000100U
AnnaBridge	161:aa5281ff4a02	536	/**
AnnaBridge	161:aa5281ff4a02	537	* @}
AnnaBridge	161:aa5281ff4a02	538	*/
AnnaBridge	161:aa5281ff4a02	539
AnnaBridge	161:aa5281ff4a02	540	/** @defgroup FMC_Wait_feature FMC Wait feature
AnnaBridge	161:aa5281ff4a02	541	* @{
AnnaBridge	161:aa5281ff4a02	542	*/
AnnaBridge	161:aa5281ff4a02	543	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	544	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	545	/**
AnnaBridge	161:aa5281ff4a02	546	* @}
AnnaBridge	161:aa5281ff4a02	547	*/
AnnaBridge	161:aa5281ff4a02	548
AnnaBridge	161:aa5281ff4a02	549	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
AnnaBridge	161:aa5281ff4a02	550	* @{
AnnaBridge	161:aa5281ff4a02	551	*/
AnnaBridge	161:aa5281ff4a02	552	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	161:aa5281ff4a02	553	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
AnnaBridge	161:aa5281ff4a02	554	/**
AnnaBridge	161:aa5281ff4a02	555	* @}
AnnaBridge	161:aa5281ff4a02	556	*/
AnnaBridge	161:aa5281ff4a02	557
AnnaBridge	161:aa5281ff4a02	558	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
AnnaBridge	161:aa5281ff4a02	559	* @{
AnnaBridge	161:aa5281ff4a02	560	*/
AnnaBridge	161:aa5281ff4a02	561	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	562	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	161:aa5281ff4a02	563	/**
AnnaBridge	161:aa5281ff4a02	564	* @}
AnnaBridge	161:aa5281ff4a02	565	*/
AnnaBridge	161:aa5281ff4a02	566
AnnaBridge	161:aa5281ff4a02	567	/** @defgroup FMC_ECC FMC ECC
AnnaBridge	161:aa5281ff4a02	568	* @{
AnnaBridge	161:aa5281ff4a02	569	*/
AnnaBridge	161:aa5281ff4a02	570	#define FMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	571	#define FMC_NAND_ECC_ENABLE 0x00000040U
AnnaBridge	161:aa5281ff4a02	572	/**
AnnaBridge	161:aa5281ff4a02	573	* @}
AnnaBridge	161:aa5281ff4a02	574	*/
AnnaBridge	161:aa5281ff4a02	575
AnnaBridge	161:aa5281ff4a02	576	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
AnnaBridge	161:aa5281ff4a02	577	* @{
AnnaBridge	161:aa5281ff4a02	578	*/
AnnaBridge	161:aa5281ff4a02	579	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	161:aa5281ff4a02	580	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge	161:aa5281ff4a02	581	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge	161:aa5281ff4a02	582	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge	161:aa5281ff4a02	583	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge	161:aa5281ff4a02	584	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
AnnaBridge	161:aa5281ff4a02	585	/**
AnnaBridge	161:aa5281ff4a02	586	* @}
AnnaBridge	161:aa5281ff4a02	587	*/
AnnaBridge	161:aa5281ff4a02	588
AnnaBridge	161:aa5281ff4a02	589	/**
AnnaBridge	161:aa5281ff4a02	590	* @}
AnnaBridge	161:aa5281ff4a02	591	*/
AnnaBridge	161:aa5281ff4a02	592
AnnaBridge	161:aa5281ff4a02	593	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
AnnaBridge	161:aa5281ff4a02	594	* @{
AnnaBridge	161:aa5281ff4a02	595	*/
AnnaBridge	161:aa5281ff4a02	596	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
AnnaBridge	161:aa5281ff4a02	597	* @{
AnnaBridge	161:aa5281ff4a02	598	*/
AnnaBridge	161:aa5281ff4a02	599	#define FMC_SDRAM_BANK1 0x00000000U
AnnaBridge	161:aa5281ff4a02	600	#define FMC_SDRAM_BANK2 0x00000001U
AnnaBridge	161:aa5281ff4a02	601	/**
AnnaBridge	161:aa5281ff4a02	602	* @}
AnnaBridge	161:aa5281ff4a02	603	*/
AnnaBridge	161:aa5281ff4a02	604
AnnaBridge	161:aa5281ff4a02	605	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
AnnaBridge	161:aa5281ff4a02	606	* @{
AnnaBridge	161:aa5281ff4a02	607	*/
AnnaBridge	161:aa5281ff4a02	608	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	609	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
AnnaBridge	161:aa5281ff4a02	610	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
AnnaBridge	161:aa5281ff4a02	611	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
AnnaBridge	161:aa5281ff4a02	612	/**
AnnaBridge	161:aa5281ff4a02	613	* @}
AnnaBridge	161:aa5281ff4a02	614	*/
AnnaBridge	161:aa5281ff4a02	615
AnnaBridge	161:aa5281ff4a02	616	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
AnnaBridge	161:aa5281ff4a02	617	* @{
AnnaBridge	161:aa5281ff4a02	618	*/
AnnaBridge	161:aa5281ff4a02	619	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
AnnaBridge	161:aa5281ff4a02	620	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
AnnaBridge	161:aa5281ff4a02	621	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
AnnaBridge	161:aa5281ff4a02	622	/**
AnnaBridge	161:aa5281ff4a02	623	* @}
AnnaBridge	161:aa5281ff4a02	624	*/
AnnaBridge	161:aa5281ff4a02	625
AnnaBridge	161:aa5281ff4a02	626	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
AnnaBridge	161:aa5281ff4a02	627	* @{
AnnaBridge	161:aa5281ff4a02	628	*/
AnnaBridge	161:aa5281ff4a02	629	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	161:aa5281ff4a02	630	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	161:aa5281ff4a02	631	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	161:aa5281ff4a02	632	/**
AnnaBridge	161:aa5281ff4a02	633	* @}
AnnaBridge	161:aa5281ff4a02	634	*/
AnnaBridge	161:aa5281ff4a02	635
AnnaBridge	161:aa5281ff4a02	636	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
AnnaBridge	161:aa5281ff4a02	637	* @{
AnnaBridge	161:aa5281ff4a02	638	*/
AnnaBridge	161:aa5281ff4a02	639	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
AnnaBridge	161:aa5281ff4a02	640	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
AnnaBridge	161:aa5281ff4a02	641	/**
AnnaBridge	161:aa5281ff4a02	642	* @}
AnnaBridge	161:aa5281ff4a02	643	*/
AnnaBridge	161:aa5281ff4a02	644
AnnaBridge	161:aa5281ff4a02	645	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
AnnaBridge	161:aa5281ff4a02	646	* @{
AnnaBridge	161:aa5281ff4a02	647	*/
AnnaBridge	161:aa5281ff4a02	648	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
AnnaBridge	161:aa5281ff4a02	649	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
AnnaBridge	161:aa5281ff4a02	650	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
AnnaBridge	161:aa5281ff4a02	651	/**
AnnaBridge	161:aa5281ff4a02	652	* @}
AnnaBridge	161:aa5281ff4a02	653	*/
AnnaBridge	161:aa5281ff4a02	654
AnnaBridge	161:aa5281ff4a02	655	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
AnnaBridge	161:aa5281ff4a02	656	* @{
AnnaBridge	161:aa5281ff4a02	657	*/
AnnaBridge	161:aa5281ff4a02	658	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	659	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
AnnaBridge	161:aa5281ff4a02	660
AnnaBridge	161:aa5281ff4a02	661	/**
AnnaBridge	161:aa5281ff4a02	662	* @}
AnnaBridge	161:aa5281ff4a02	663	*/
AnnaBridge	161:aa5281ff4a02	664
AnnaBridge	161:aa5281ff4a02	665	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
AnnaBridge	161:aa5281ff4a02	666	* @{
AnnaBridge	161:aa5281ff4a02	667	*/
AnnaBridge	161:aa5281ff4a02	668	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	669	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
AnnaBridge	161:aa5281ff4a02	670	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
AnnaBridge	161:aa5281ff4a02	671	/**
AnnaBridge	161:aa5281ff4a02	672	* @}
AnnaBridge	161:aa5281ff4a02	673	*/
AnnaBridge	161:aa5281ff4a02	674
AnnaBridge	161:aa5281ff4a02	675	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
AnnaBridge	161:aa5281ff4a02	676	* @{
AnnaBridge	161:aa5281ff4a02	677	*/
AnnaBridge	161:aa5281ff4a02	678	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	679	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
AnnaBridge	161:aa5281ff4a02	680	/**
AnnaBridge	161:aa5281ff4a02	681	* @}
AnnaBridge	161:aa5281ff4a02	682	*/
AnnaBridge	161:aa5281ff4a02	683
AnnaBridge	161:aa5281ff4a02	684	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
AnnaBridge	161:aa5281ff4a02	685	* @{
AnnaBridge	161:aa5281ff4a02	686	*/
AnnaBridge	161:aa5281ff4a02	687	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
AnnaBridge	161:aa5281ff4a02	688	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
AnnaBridge	161:aa5281ff4a02	689	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
AnnaBridge	161:aa5281ff4a02	690	/**
AnnaBridge	161:aa5281ff4a02	691	* @}
AnnaBridge	161:aa5281ff4a02	692	*/
AnnaBridge	161:aa5281ff4a02	693
AnnaBridge	161:aa5281ff4a02	694	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
AnnaBridge	161:aa5281ff4a02	695	* @{
AnnaBridge	161:aa5281ff4a02	696	*/
AnnaBridge	161:aa5281ff4a02	697	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
AnnaBridge	161:aa5281ff4a02	698	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
AnnaBridge	161:aa5281ff4a02	699	#define FMC_SDRAM_CMD_PALL 0x00000002U
AnnaBridge	161:aa5281ff4a02	700	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
AnnaBridge	161:aa5281ff4a02	701	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
AnnaBridge	161:aa5281ff4a02	702	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
AnnaBridge	161:aa5281ff4a02	703	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
AnnaBridge	161:aa5281ff4a02	704	/**
AnnaBridge	161:aa5281ff4a02	705	* @}
AnnaBridge	161:aa5281ff4a02	706	*/
AnnaBridge	161:aa5281ff4a02	707
AnnaBridge	161:aa5281ff4a02	708	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
AnnaBridge	161:aa5281ff4a02	709	* @{
AnnaBridge	161:aa5281ff4a02	710	*/
AnnaBridge	161:aa5281ff4a02	711	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
AnnaBridge	161:aa5281ff4a02	712	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
AnnaBridge	161:aa5281ff4a02	713	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
AnnaBridge	161:aa5281ff4a02	714	/**
AnnaBridge	161:aa5281ff4a02	715	* @}
AnnaBridge	161:aa5281ff4a02	716	*/
AnnaBridge	161:aa5281ff4a02	717
AnnaBridge	161:aa5281ff4a02	718	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
AnnaBridge	161:aa5281ff4a02	719	* @{
AnnaBridge	161:aa5281ff4a02	720	*/
AnnaBridge	161:aa5281ff4a02	721	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
AnnaBridge	161:aa5281ff4a02	722	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
AnnaBridge	161:aa5281ff4a02	723	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
AnnaBridge	161:aa5281ff4a02	724	/**
AnnaBridge	161:aa5281ff4a02	725	* @}
AnnaBridge	161:aa5281ff4a02	726	*/
AnnaBridge	161:aa5281ff4a02	727
AnnaBridge	161:aa5281ff4a02	728	/**
AnnaBridge	161:aa5281ff4a02	729	* @}
AnnaBridge	161:aa5281ff4a02	730	*/
AnnaBridge	161:aa5281ff4a02	731
AnnaBridge	161:aa5281ff4a02	732	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
AnnaBridge	161:aa5281ff4a02	733	* @{
AnnaBridge	161:aa5281ff4a02	734	*/
AnnaBridge	161:aa5281ff4a02	735	#define FMC_IT_RISING_EDGE 0x00000008U
AnnaBridge	161:aa5281ff4a02	736	#define FMC_IT_LEVEL 0x00000010U
AnnaBridge	161:aa5281ff4a02	737	#define FMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge	161:aa5281ff4a02	738	#define FMC_IT_REFRESH_ERROR 0x00004000U
AnnaBridge	161:aa5281ff4a02	739	/**
AnnaBridge	161:aa5281ff4a02	740	* @}
AnnaBridge	161:aa5281ff4a02	741	*/
AnnaBridge	161:aa5281ff4a02	742
AnnaBridge	161:aa5281ff4a02	743	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
AnnaBridge	161:aa5281ff4a02	744	* @{
AnnaBridge	161:aa5281ff4a02	745	*/
AnnaBridge	161:aa5281ff4a02	746	#define FMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge	161:aa5281ff4a02	747	#define FMC_FLAG_LEVEL 0x00000002U
AnnaBridge	161:aa5281ff4a02	748	#define FMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge	161:aa5281ff4a02	749	#define FMC_FLAG_FEMPT 0x00000040U
AnnaBridge	161:aa5281ff4a02	750	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
AnnaBridge	161:aa5281ff4a02	751	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
AnnaBridge	161:aa5281ff4a02	752	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
AnnaBridge	161:aa5281ff4a02	753	/**
AnnaBridge	161:aa5281ff4a02	754	* @}
AnnaBridge	161:aa5281ff4a02	755	*/
AnnaBridge	161:aa5281ff4a02	756
AnnaBridge	161:aa5281ff4a02	757	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
AnnaBridge	161:aa5281ff4a02	758	* @{
AnnaBridge	161:aa5281ff4a02	759	*/
AnnaBridge	161:aa5281ff4a02	760	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	761	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
AnnaBridge	161:aa5281ff4a02	762	#else
AnnaBridge	161:aa5281ff4a02	763	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
AnnaBridge	161:aa5281ff4a02	764	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
AnnaBridge	161:aa5281ff4a02	765	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	161:aa5281ff4a02	766	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
AnnaBridge	161:aa5281ff4a02	767	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
AnnaBridge	161:aa5281ff4a02	768	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
AnnaBridge	161:aa5281ff4a02	769
AnnaBridge	161:aa5281ff4a02	770
AnnaBridge	161:aa5281ff4a02	771	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	772	#define FMC_NAND_DEVICE FMC_Bank3
AnnaBridge	161:aa5281ff4a02	773	#else
AnnaBridge	161:aa5281ff4a02	774	#define FMC_NAND_DEVICE FMC_Bank2_3
AnnaBridge	161:aa5281ff4a02	775	#define FMC_PCCARD_DEVICE FMC_Bank4
AnnaBridge	161:aa5281ff4a02	776	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	161:aa5281ff4a02	777	#define FMC_NORSRAM_DEVICE FMC_Bank1
AnnaBridge	161:aa5281ff4a02	778	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
AnnaBridge	161:aa5281ff4a02	779	#define FMC_SDRAM_DEVICE FMC_Bank5_6
AnnaBridge	161:aa5281ff4a02	780	/**
AnnaBridge	161:aa5281ff4a02	781	* @}
AnnaBridge	161:aa5281ff4a02	782	*/
AnnaBridge	161:aa5281ff4a02	783
AnnaBridge	161:aa5281ff4a02	784	/**
AnnaBridge	161:aa5281ff4a02	785	* @}
AnnaBridge	161:aa5281ff4a02	786	*/
AnnaBridge	161:aa5281ff4a02	787
AnnaBridge	161:aa5281ff4a02	788	/* Private macro -------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	789	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
AnnaBridge	161:aa5281ff4a02	790	* @{
AnnaBridge	161:aa5281ff4a02	791	*/
AnnaBridge	161:aa5281ff4a02	792
AnnaBridge	161:aa5281ff4a02	793	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
AnnaBridge	161:aa5281ff4a02	794	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	161:aa5281ff4a02	795	* @{
AnnaBridge	161:aa5281ff4a02	796	*/
AnnaBridge	161:aa5281ff4a02	797	/**
AnnaBridge	161:aa5281ff4a02	798	* @brief Enable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	799	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	800	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	161:aa5281ff4a02	801	* @retval None
AnnaBridge	161:aa5281ff4a02	802	*/
AnnaBridge	161:aa5281ff4a02	803	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
AnnaBridge	161:aa5281ff4a02	804
AnnaBridge	161:aa5281ff4a02	805	/**
AnnaBridge	161:aa5281ff4a02	806	* @brief Disable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	807	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	808	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	161:aa5281ff4a02	809	* @retval None
AnnaBridge	161:aa5281ff4a02	810	*/
AnnaBridge	161:aa5281ff4a02	811	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
AnnaBridge	161:aa5281ff4a02	812	/**
AnnaBridge	161:aa5281ff4a02	813	* @}
AnnaBridge	161:aa5281ff4a02	814	*/
AnnaBridge	161:aa5281ff4a02	815
AnnaBridge	161:aa5281ff4a02	816	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
AnnaBridge	161:aa5281ff4a02	817	* @brief macros to handle NAND device enable/disable
AnnaBridge	161:aa5281ff4a02	818	* @{
AnnaBridge	161:aa5281ff4a02	819	*/
AnnaBridge	161:aa5281ff4a02	820	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	821	/**
AnnaBridge	161:aa5281ff4a02	822	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	823	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	824	* @param __BANK__ FMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	825	* @retval None
AnnaBridge	161:aa5281ff4a02	826	*/
AnnaBridge	161:aa5281ff4a02	827	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
AnnaBridge	161:aa5281ff4a02	828
AnnaBridge	161:aa5281ff4a02	829	/**
AnnaBridge	161:aa5281ff4a02	830	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	831	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	832	* @param __BANK__ FMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	833	* @retval None
AnnaBridge	161:aa5281ff4a02	834	*/
AnnaBridge	161:aa5281ff4a02	835	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
AnnaBridge	161:aa5281ff4a02	836	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	161:aa5281ff4a02	837	/**
AnnaBridge	161:aa5281ff4a02	838	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	839	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	840	* @param __BANK__ FMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	841	* @retval None
AnnaBridge	161:aa5281ff4a02	842	*/
AnnaBridge	161:aa5281ff4a02	843	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
AnnaBridge	161:aa5281ff4a02	844	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
AnnaBridge	161:aa5281ff4a02	845
AnnaBridge	161:aa5281ff4a02	846	/**
AnnaBridge	161:aa5281ff4a02	847	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	848	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	849	* @param __BANK__ FMC_NAND Bank
AnnaBridge	161:aa5281ff4a02	850	* @retval None
AnnaBridge	161:aa5281ff4a02	851	*/
AnnaBridge	161:aa5281ff4a02	852	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
AnnaBridge	161:aa5281ff4a02	853	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
AnnaBridge	161:aa5281ff4a02	854
AnnaBridge	161:aa5281ff4a02	855	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
AnnaBridge	161:aa5281ff4a02	856	/**
AnnaBridge	161:aa5281ff4a02	857	* @}
AnnaBridge	161:aa5281ff4a02	858	*/
AnnaBridge	161:aa5281ff4a02	859	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	161:aa5281ff4a02	860	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
AnnaBridge	161:aa5281ff4a02	861	* @brief macros to handle SRAM read/write operations
AnnaBridge	161:aa5281ff4a02	862	* @{
AnnaBridge	161:aa5281ff4a02	863	*/
AnnaBridge	161:aa5281ff4a02	864	/**
AnnaBridge	161:aa5281ff4a02	865	* @brief Enable the PCCARD device access.
AnnaBridge	163:e59c8e839560	866	* @param __INSTANCE__ FMC_PCCARD Instance
AnnaBridge	161:aa5281ff4a02	867	* @retval None
AnnaBridge	161:aa5281ff4a02	868	*/
AnnaBridge	161:aa5281ff4a02	869	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
AnnaBridge	161:aa5281ff4a02	870
AnnaBridge	161:aa5281ff4a02	871	/**
AnnaBridge	161:aa5281ff4a02	872	* @brief Disable the PCCARD device access.
AnnaBridge	163:e59c8e839560	873	* @param __INSTANCE__ FMC_PCCARD Instance
AnnaBridge	161:aa5281ff4a02	874	* @retval None
AnnaBridge	161:aa5281ff4a02	875	*/
AnnaBridge	161:aa5281ff4a02	876	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
AnnaBridge	161:aa5281ff4a02	877	/**
AnnaBridge	161:aa5281ff4a02	878	* @}
AnnaBridge	161:aa5281ff4a02	879	*/
AnnaBridge	161:aa5281ff4a02	880	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	161:aa5281ff4a02	881
AnnaBridge	161:aa5281ff4a02	882	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
AnnaBridge	161:aa5281ff4a02	883	* @brief macros to handle FMC flags and interrupts
AnnaBridge	161:aa5281ff4a02	884	* @{
AnnaBridge	161:aa5281ff4a02	885	*/
AnnaBridge	161:aa5281ff4a02	886	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	887	/**
AnnaBridge	161:aa5281ff4a02	888	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	889	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	163:e59c8e839560	890	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	891	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	892	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	893	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	894	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	895	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	896	* @retval None
AnnaBridge	161:aa5281ff4a02	897	*/
AnnaBridge	161:aa5281ff4a02	898	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	899
AnnaBridge	161:aa5281ff4a02	900	/**
AnnaBridge	161:aa5281ff4a02	901	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	902	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	903	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	904	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	905	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	906	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	907	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	908	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	909	* @retval None
AnnaBridge	161:aa5281ff4a02	910	*/
AnnaBridge	161:aa5281ff4a02	911	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	912
AnnaBridge	161:aa5281ff4a02	913	/**
AnnaBridge	161:aa5281ff4a02	914	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	915	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	916	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	917	* @param __FLAG__ FMC_NAND flag
AnnaBridge	161:aa5281ff4a02	918	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	919	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	920	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	921	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	922	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	923	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	924	*/
AnnaBridge	161:aa5281ff4a02	925	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	926	/**
AnnaBridge	161:aa5281ff4a02	927	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	928	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	929	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	930	* @param __FLAG__ FMC_NAND flag
AnnaBridge	161:aa5281ff4a02	931	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	932	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	933	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	934	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	935	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	936	* @retval None
AnnaBridge	161:aa5281ff4a02	937	*/
AnnaBridge	161:aa5281ff4a02	938	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
AnnaBridge	161:aa5281ff4a02	939	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	161:aa5281ff4a02	940	/**
AnnaBridge	161:aa5281ff4a02	941	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	942	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	163:e59c8e839560	943	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	944	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	945	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	946	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	947	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	948	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	949	* @retval None
AnnaBridge	161:aa5281ff4a02	950	*/
AnnaBridge	161:aa5281ff4a02	951	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
AnnaBridge	161:aa5281ff4a02	952	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
AnnaBridge	161:aa5281ff4a02	953
AnnaBridge	161:aa5281ff4a02	954	/**
AnnaBridge	161:aa5281ff4a02	955	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	956	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	957	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	958	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	161:aa5281ff4a02	959	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	960	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	961	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	962	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	963	* @retval None
AnnaBridge	161:aa5281ff4a02	964	*/
AnnaBridge	161:aa5281ff4a02	965	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
AnnaBridge	161:aa5281ff4a02	966	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
AnnaBridge	161:aa5281ff4a02	967
AnnaBridge	161:aa5281ff4a02	968	/**
AnnaBridge	161:aa5281ff4a02	969	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	970	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	971	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	972	* @param __FLAG__ FMC_NAND flag
AnnaBridge	161:aa5281ff4a02	973	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	974	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	975	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	976	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	977	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	978	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	979	*/
AnnaBridge	161:aa5281ff4a02	980	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	161:aa5281ff4a02	981	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	161:aa5281ff4a02	982	/**
AnnaBridge	161:aa5281ff4a02	983	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	984	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	985	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	986	* @param __FLAG__ FMC_NAND flag
AnnaBridge	161:aa5281ff4a02	987	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	988	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	989	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	990	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	991	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	992	* @retval None
AnnaBridge	161:aa5281ff4a02	993	*/
AnnaBridge	161:aa5281ff4a02	994	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
AnnaBridge	161:aa5281ff4a02	995	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
AnnaBridge	161:aa5281ff4a02	996	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
AnnaBridge	161:aa5281ff4a02	997
AnnaBridge	161:aa5281ff4a02	998	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	161:aa5281ff4a02	999	/**
AnnaBridge	161:aa5281ff4a02	1000	* @brief Enable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	1001	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1002	* @param __INTERRUPT__ FMC_PCCARD interrupt
AnnaBridge	161:aa5281ff4a02	1003	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1004	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	1005	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	1006	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	1007	* @retval None
AnnaBridge	161:aa5281ff4a02	1008	*/
AnnaBridge	161:aa5281ff4a02	1009	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1010
AnnaBridge	161:aa5281ff4a02	1011	/**
AnnaBridge	161:aa5281ff4a02	1012	* @brief Disable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	1013	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1014	* @param __INTERRUPT__ FMC_PCCARD interrupt
AnnaBridge	161:aa5281ff4a02	1015	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1016	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	161:aa5281ff4a02	1017	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	161:aa5281ff4a02	1018	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	161:aa5281ff4a02	1019	* @retval None
AnnaBridge	161:aa5281ff4a02	1020	*/
AnnaBridge	161:aa5281ff4a02	1021	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1022
AnnaBridge	161:aa5281ff4a02	1023	/**
AnnaBridge	161:aa5281ff4a02	1024	* @brief Get flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	1025	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1026	* @param __FLAG__ FMC_PCCARD flag
AnnaBridge	161:aa5281ff4a02	1027	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1028	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	1029	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	1030	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	1031	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	1032	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1033	*/
AnnaBridge	161:aa5281ff4a02	1034	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1035
AnnaBridge	161:aa5281ff4a02	1036	/**
AnnaBridge	161:aa5281ff4a02	1037	* @brief Clear flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	1038	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1039	* @param __FLAG__ FMC_PCCARD flag
AnnaBridge	161:aa5281ff4a02	1040	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1041	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	161:aa5281ff4a02	1042	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	161:aa5281ff4a02	1043	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	161:aa5281ff4a02	1044	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	161:aa5281ff4a02	1045	* @retval None
AnnaBridge	161:aa5281ff4a02	1046	*/
AnnaBridge	161:aa5281ff4a02	1047	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
AnnaBridge	161:aa5281ff4a02	1048	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	161:aa5281ff4a02	1049
AnnaBridge	161:aa5281ff4a02	1050	/**
AnnaBridge	161:aa5281ff4a02	1051	* @brief Enable the SDRAM device interrupt.
AnnaBridge	163:e59c8e839560	1052	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1053	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	161:aa5281ff4a02	1054	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1055	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	161:aa5281ff4a02	1056	* @retval None
AnnaBridge	161:aa5281ff4a02	1057	*/
AnnaBridge	161:aa5281ff4a02	1058	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1059
AnnaBridge	161:aa5281ff4a02	1060	/**
AnnaBridge	161:aa5281ff4a02	1061	* @brief Disable the SDRAM device interrupt.
AnnaBridge	163:e59c8e839560	1062	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1063	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	161:aa5281ff4a02	1064	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1065	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	161:aa5281ff4a02	1066	* @retval None
AnnaBridge	161:aa5281ff4a02	1067	*/
AnnaBridge	161:aa5281ff4a02	1068	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1069
AnnaBridge	161:aa5281ff4a02	1070	/**
AnnaBridge	161:aa5281ff4a02	1071	* @brief Get flag status of the SDRAM device.
AnnaBridge	163:e59c8e839560	1072	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1073	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	161:aa5281ff4a02	1074	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1075	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
AnnaBridge	161:aa5281ff4a02	1076	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
AnnaBridge	161:aa5281ff4a02	1077	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
AnnaBridge	161:aa5281ff4a02	1078	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1079	*/
AnnaBridge	161:aa5281ff4a02	1080	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1081
AnnaBridge	161:aa5281ff4a02	1082	/**
AnnaBridge	161:aa5281ff4a02	1083	* @brief Clear flag status of the SDRAM device.
AnnaBridge	163:e59c8e839560	1084	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1085	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	161:aa5281ff4a02	1086	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1087	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
AnnaBridge	161:aa5281ff4a02	1088	* @retval None
AnnaBridge	161:aa5281ff4a02	1089	*/
AnnaBridge	161:aa5281ff4a02	1090	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1091	/**
AnnaBridge	161:aa5281ff4a02	1092	* @}
AnnaBridge	161:aa5281ff4a02	1093	*/
AnnaBridge	161:aa5281ff4a02	1094
AnnaBridge	161:aa5281ff4a02	1095	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
AnnaBridge	161:aa5281ff4a02	1096	* @{
AnnaBridge	161:aa5281ff4a02	1097	*/
AnnaBridge	161:aa5281ff4a02	1098	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
AnnaBridge	161:aa5281ff4a02	1099	((BANK) == FMC_NORSRAM_BANK2) \|\| \
AnnaBridge	161:aa5281ff4a02	1100	((BANK) == FMC_NORSRAM_BANK3) \|\| \
AnnaBridge	161:aa5281ff4a02	1101	((BANK) == FMC_NORSRAM_BANK4))
AnnaBridge	161:aa5281ff4a02	1102
AnnaBridge	161:aa5281ff4a02	1103	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1104	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	161:aa5281ff4a02	1105
AnnaBridge	161:aa5281ff4a02	1106	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	161:aa5281ff4a02	1107	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	161:aa5281ff4a02	1108	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
AnnaBridge	161:aa5281ff4a02	1109
AnnaBridge	161:aa5281ff4a02	1110	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	161:aa5281ff4a02	1111	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	161:aa5281ff4a02	1112	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	161:aa5281ff4a02	1113
AnnaBridge	161:aa5281ff4a02	1114	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
AnnaBridge	161:aa5281ff4a02	1115	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
AnnaBridge	161:aa5281ff4a02	1116	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
AnnaBridge	161:aa5281ff4a02	1117	((__MODE__) == FMC_ACCESS_MODE_D))
AnnaBridge	161:aa5281ff4a02	1118
AnnaBridge	161:aa5281ff4a02	1119	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
AnnaBridge	161:aa5281ff4a02	1120	((BANK) == FMC_NAND_BANK3))
AnnaBridge	161:aa5281ff4a02	1121
AnnaBridge	161:aa5281ff4a02	1122	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1123	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1124
AnnaBridge	161:aa5281ff4a02	1125	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	161:aa5281ff4a02	1126	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	161:aa5281ff4a02	1127
AnnaBridge	161:aa5281ff4a02	1128	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1129	((STATE) == FMC_NAND_ECC_ENABLE))
AnnaBridge	161:aa5281ff4a02	1130
AnnaBridge	161:aa5281ff4a02	1131	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	1132	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	1133	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	161:aa5281ff4a02	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	161:aa5281ff4a02	1137
AnnaBridge	161:aa5281ff4a02	1138	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1139
AnnaBridge	161:aa5281ff4a02	1140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1141
AnnaBridge	161:aa5281ff4a02	1142	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1143
AnnaBridge	161:aa5281ff4a02	1144	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1145
AnnaBridge	161:aa5281ff4a02	1146	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1147
AnnaBridge	161:aa5281ff4a02	1148	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	161:aa5281ff4a02	1149
AnnaBridge	161:aa5281ff4a02	1150	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
AnnaBridge	161:aa5281ff4a02	1151
AnnaBridge	161:aa5281ff4a02	1152	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	161:aa5281ff4a02	1153
AnnaBridge	161:aa5281ff4a02	1154	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
AnnaBridge	161:aa5281ff4a02	1155
AnnaBridge	161:aa5281ff4a02	1156	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
AnnaBridge	161:aa5281ff4a02	1157
AnnaBridge	161:aa5281ff4a02	1158	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1159	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1160
AnnaBridge	161:aa5281ff4a02	1161	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	161:aa5281ff4a02	1162	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	161:aa5281ff4a02	1163
AnnaBridge	161:aa5281ff4a02	1164	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	161:aa5281ff4a02	1165	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1166	((__MODE__) == FMC_WRAP_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1167	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	161:aa5281ff4a02	1168
AnnaBridge	161:aa5281ff4a02	1169	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	161:aa5281ff4a02	1170	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
AnnaBridge	161:aa5281ff4a02	1171
AnnaBridge	161:aa5281ff4a02	1172	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1173	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
AnnaBridge	161:aa5281ff4a02	1174
AnnaBridge	161:aa5281ff4a02	1175	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1176	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	161:aa5281ff4a02	1177
AnnaBridge	161:aa5281ff4a02	1178	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1179	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1180
AnnaBridge	161:aa5281ff4a02	1181	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1182	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	161:aa5281ff4a02	1183
AnnaBridge	161:aa5281ff4a02	1184	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1185	((__BURST__) == FMC_WRITE_BURST_ENABLE))
AnnaBridge	161:aa5281ff4a02	1186
AnnaBridge	161:aa5281ff4a02	1187	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	161:aa5281ff4a02	1188	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	161:aa5281ff4a02	1189
AnnaBridge	161:aa5281ff4a02	1190	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	161:aa5281ff4a02	1191
AnnaBridge	161:aa5281ff4a02	1192	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	161:aa5281ff4a02	1193
AnnaBridge	161:aa5281ff4a02	1194	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	161:aa5281ff4a02	1195
AnnaBridge	161:aa5281ff4a02	1196	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	161:aa5281ff4a02	1197
AnnaBridge	161:aa5281ff4a02	1198	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	161:aa5281ff4a02	1199
AnnaBridge	161:aa5281ff4a02	1200	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
AnnaBridge	161:aa5281ff4a02	1201
AnnaBridge	161:aa5281ff4a02	1202	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
AnnaBridge	161:aa5281ff4a02	1203	((BANK) == FMC_SDRAM_BANK2))
AnnaBridge	161:aa5281ff4a02	1204
AnnaBridge	161:aa5281ff4a02	1205	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
AnnaBridge	161:aa5281ff4a02	1206	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
AnnaBridge	161:aa5281ff4a02	1207	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
AnnaBridge	161:aa5281ff4a02	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
AnnaBridge	161:aa5281ff4a02	1209
AnnaBridge	161:aa5281ff4a02	1210	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
AnnaBridge	161:aa5281ff4a02	1211	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
AnnaBridge	161:aa5281ff4a02	1212	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
AnnaBridge	161:aa5281ff4a02	1213
AnnaBridge	161:aa5281ff4a02	1214	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	161:aa5281ff4a02	1215	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	161:aa5281ff4a02	1216	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
AnnaBridge	161:aa5281ff4a02	1217
AnnaBridge	161:aa5281ff4a02	1218	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
AnnaBridge	161:aa5281ff4a02	1219	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
AnnaBridge	161:aa5281ff4a02	1220
AnnaBridge	161:aa5281ff4a02	1221
AnnaBridge	161:aa5281ff4a02	1222	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
AnnaBridge	161:aa5281ff4a02	1223	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
AnnaBridge	161:aa5281ff4a02	1224	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
AnnaBridge	161:aa5281ff4a02	1225
AnnaBridge	161:aa5281ff4a02	1226	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1227	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
AnnaBridge	161:aa5281ff4a02	1228	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
AnnaBridge	161:aa5281ff4a02	1229
AnnaBridge	161:aa5281ff4a02	1230	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1231	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
AnnaBridge	161:aa5281ff4a02	1232
AnnaBridge	161:aa5281ff4a02	1233
AnnaBridge	161:aa5281ff4a02	1234	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
AnnaBridge	161:aa5281ff4a02	1235	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
AnnaBridge	161:aa5281ff4a02	1236	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
AnnaBridge	161:aa5281ff4a02	1237
AnnaBridge	161:aa5281ff4a02	1238	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	161:aa5281ff4a02	1239
AnnaBridge	161:aa5281ff4a02	1240	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	161:aa5281ff4a02	1241
AnnaBridge	161:aa5281ff4a02	1242	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
AnnaBridge	161:aa5281ff4a02	1243
AnnaBridge	161:aa5281ff4a02	1244	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	161:aa5281ff4a02	1245
AnnaBridge	161:aa5281ff4a02	1246	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
AnnaBridge	161:aa5281ff4a02	1247
AnnaBridge	161:aa5281ff4a02	1248	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	161:aa5281ff4a02	1249
AnnaBridge	161:aa5281ff4a02	1250	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	161:aa5281ff4a02	1251
AnnaBridge	161:aa5281ff4a02	1252	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
AnnaBridge	161:aa5281ff4a02	1253	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1254	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
AnnaBridge	161:aa5281ff4a02	1255	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
AnnaBridge	161:aa5281ff4a02	1256	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
AnnaBridge	161:aa5281ff4a02	1257	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
AnnaBridge	161:aa5281ff4a02	1258	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
AnnaBridge	161:aa5281ff4a02	1259
AnnaBridge	161:aa5281ff4a02	1260	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
AnnaBridge	161:aa5281ff4a02	1261	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
AnnaBridge	161:aa5281ff4a02	1262	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
AnnaBridge	161:aa5281ff4a02	1263
AnnaBridge	161:aa5281ff4a02	1264	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
AnnaBridge	161:aa5281ff4a02	1265
AnnaBridge	161:aa5281ff4a02	1266	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
AnnaBridge	161:aa5281ff4a02	1267
AnnaBridge	161:aa5281ff4a02	1268	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
AnnaBridge	161:aa5281ff4a02	1269
AnnaBridge	161:aa5281ff4a02	1270	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
AnnaBridge	161:aa5281ff4a02	1271
AnnaBridge	161:aa5281ff4a02	1272	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1273	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
AnnaBridge	161:aa5281ff4a02	1274
AnnaBridge	161:aa5281ff4a02	1275	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	1276	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
AnnaBridge	161:aa5281ff4a02	1277	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
AnnaBridge	161:aa5281ff4a02	1278	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
AnnaBridge	161:aa5281ff4a02	1279	((SIZE) == FMC_PAGE_SIZE_1024))
AnnaBridge	161:aa5281ff4a02	1280
AnnaBridge	161:aa5281ff4a02	1281	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	1282	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	1283	((FIFO) == FMC_WRITE_FIFO_ENABLE))
AnnaBridge	161:aa5281ff4a02	1284	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	161:aa5281ff4a02	1285
AnnaBridge	161:aa5281ff4a02	1286	/**
AnnaBridge	161:aa5281ff4a02	1287	* @}
AnnaBridge	161:aa5281ff4a02	1288	*/
AnnaBridge	161:aa5281ff4a02	1289
AnnaBridge	161:aa5281ff4a02	1290	/**
AnnaBridge	161:aa5281ff4a02	1291	* @}
AnnaBridge	161:aa5281ff4a02	1292	*/
AnnaBridge	161:aa5281ff4a02	1293
AnnaBridge	161:aa5281ff4a02	1294	/* Private functions ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1295	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
AnnaBridge	161:aa5281ff4a02	1296	* @{
AnnaBridge	161:aa5281ff4a02	1297	*/
AnnaBridge	161:aa5281ff4a02	1298
AnnaBridge	161:aa5281ff4a02	1299	/** @defgroup FMC_LL_NORSRAM NOR SRAM
AnnaBridge	161:aa5281ff4a02	1300	* @{
AnnaBridge	161:aa5281ff4a02	1301	*/
AnnaBridge	161:aa5281ff4a02	1302	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	1303	* @{
AnnaBridge	161:aa5281ff4a02	1304	*/
AnnaBridge	161:aa5281ff4a02	1305	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	1306	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1307	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	161:aa5281ff4a02	1308	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1309	/**
AnnaBridge	161:aa5281ff4a02	1310	* @}
AnnaBridge	161:aa5281ff4a02	1311	*/
AnnaBridge	161:aa5281ff4a02	1312
AnnaBridge	161:aa5281ff4a02	1313	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	161:aa5281ff4a02	1314	* @{
AnnaBridge	161:aa5281ff4a02	1315	*/
AnnaBridge	161:aa5281ff4a02	1316	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1317	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1318	/**
AnnaBridge	161:aa5281ff4a02	1319	* @}
AnnaBridge	161:aa5281ff4a02	1320	*/
AnnaBridge	161:aa5281ff4a02	1321	/**
AnnaBridge	161:aa5281ff4a02	1322	* @}
AnnaBridge	161:aa5281ff4a02	1323	*/
AnnaBridge	161:aa5281ff4a02	1324
AnnaBridge	161:aa5281ff4a02	1325	/** @defgroup FMC_LL_NAND NAND
AnnaBridge	161:aa5281ff4a02	1326	* @{
AnnaBridge	161:aa5281ff4a02	1327	*/
AnnaBridge	161:aa5281ff4a02	1328	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	1329	* @{
AnnaBridge	161:aa5281ff4a02	1330	*/
AnnaBridge	161:aa5281ff4a02	1331	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	1332	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1333	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1334	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1335	/**
AnnaBridge	161:aa5281ff4a02	1336	* @}
AnnaBridge	161:aa5281ff4a02	1337	*/
AnnaBridge	161:aa5281ff4a02	1338
AnnaBridge	161:aa5281ff4a02	1339	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	161:aa5281ff4a02	1340	* @{
AnnaBridge	161:aa5281ff4a02	1341	*/
AnnaBridge	161:aa5281ff4a02	1342	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1343	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1344	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	1345
AnnaBridge	161:aa5281ff4a02	1346	/**
AnnaBridge	161:aa5281ff4a02	1347	* @}
AnnaBridge	161:aa5281ff4a02	1348	*/
AnnaBridge	161:aa5281ff4a02	1349	/**
AnnaBridge	161:aa5281ff4a02	1350	* @}
AnnaBridge	161:aa5281ff4a02	1351	*/
AnnaBridge	161:aa5281ff4a02	1352	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	161:aa5281ff4a02	1353	/** @defgroup FMC_LL_PCCARD PCCARD
AnnaBridge	161:aa5281ff4a02	1354	* @{
AnnaBridge	161:aa5281ff4a02	1355	*/
AnnaBridge	161:aa5281ff4a02	1356	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	1357	* @{
AnnaBridge	161:aa5281ff4a02	1358	*/
AnnaBridge	161:aa5281ff4a02	1359	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	1360	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1361	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1362	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	161:aa5281ff4a02	1363	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
AnnaBridge	161:aa5281ff4a02	1364	/**
AnnaBridge	161:aa5281ff4a02	1365	* @}
AnnaBridge	161:aa5281ff4a02	1366	*/
AnnaBridge	161:aa5281ff4a02	1367	/**
AnnaBridge	161:aa5281ff4a02	1368	* @}
AnnaBridge	161:aa5281ff4a02	1369	*/
AnnaBridge	161:aa5281ff4a02	1370	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	161:aa5281ff4a02	1371
AnnaBridge	161:aa5281ff4a02	1372	/** @defgroup FMC_LL_SDRAM SDRAM
AnnaBridge	161:aa5281ff4a02	1373	* @{
AnnaBridge	161:aa5281ff4a02	1374	*/
AnnaBridge	161:aa5281ff4a02	1375	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
AnnaBridge	161:aa5281ff4a02	1376	* @{
AnnaBridge	161:aa5281ff4a02	1377	*/
AnnaBridge	161:aa5281ff4a02	1378	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
AnnaBridge	161:aa5281ff4a02	1379	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1380	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1381	/**
AnnaBridge	161:aa5281ff4a02	1382	* @}
AnnaBridge	161:aa5281ff4a02	1383	*/
AnnaBridge	161:aa5281ff4a02	1384
AnnaBridge	161:aa5281ff4a02	1385	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
AnnaBridge	161:aa5281ff4a02	1386	* @{
AnnaBridge	161:aa5281ff4a02	1387	*/
AnnaBridge	161:aa5281ff4a02	1388	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1389	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1390	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	1391	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
AnnaBridge	161:aa5281ff4a02	1392	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
AnnaBridge	161:aa5281ff4a02	1393	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	161:aa5281ff4a02	1394	/**
AnnaBridge	161:aa5281ff4a02	1395	* @}
AnnaBridge	161:aa5281ff4a02	1396	*/
AnnaBridge	161:aa5281ff4a02	1397	/**
AnnaBridge	161:aa5281ff4a02	1398	* @}
AnnaBridge	161:aa5281ff4a02	1399	*/
AnnaBridge	161:aa5281ff4a02	1400
AnnaBridge	161:aa5281ff4a02	1401	/**
AnnaBridge	161:aa5281ff4a02	1402	* @}
AnnaBridge	161:aa5281ff4a02	1403	*/
AnnaBridge	161:aa5281ff4a02	1404
AnnaBridge	161:aa5281ff4a02	1405	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	161:aa5281ff4a02	1406	/**
AnnaBridge	161:aa5281ff4a02	1407	* @}
AnnaBridge	161:aa5281ff4a02	1408	*/
AnnaBridge	161:aa5281ff4a02	1409
AnnaBridge	161:aa5281ff4a02	1410	/**
AnnaBridge	161:aa5281ff4a02	1411	* @}
AnnaBridge	161:aa5281ff4a02	1412	*/
AnnaBridge	161:aa5281ff4a02	1413	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	1414	}
AnnaBridge	161:aa5281ff4a02	1415	#endif
AnnaBridge	161:aa5281ff4a02	1416
AnnaBridge	161:aa5281ff4a02	1417	#endif /* __STM32F4xx_LL_FMC_H */
AnnaBridge	161:aa5281ff4a02	1418
AnnaBridge	161:aa5281ff4a02	1419	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/