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TARGET_NUCLEO_F410RB/TOOLCHAIN_ARM_STD/stm32f410rx.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f410rx.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * This file contains:
AnnaBridge 171:3a7713b1edbc 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 9 * - peripherals registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 10 * - Macros to access peripheral's registers hardware
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 13 * @attention
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 18 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 20 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 23 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 25 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 26 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 40 */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /** @addtogroup CMSIS_Device
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** @addtogroup stm32f410rx
AnnaBridge 171:3a7713b1edbc 47 * @{
AnnaBridge 171:3a7713b1edbc 48 */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 #ifndef __STM32F410Rx_H
AnnaBridge 171:3a7713b1edbc 51 #define __STM32F410Rx_H
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 54 extern "C" {
AnnaBridge 171:3a7713b1edbc 55 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 171:3a7713b1edbc 65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
AnnaBridge 171:3a7713b1edbc 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 68 /* MBED */
AnnaBridge 171:3a7713b1edbc 69 #ifndef __FPU_PRESENT
AnnaBridge 171:3a7713b1edbc 70 #define __FPU_PRESENT 1U /*!< FPU present */
AnnaBridge 171:3a7713b1edbc 71 #endif /* __FPU_PRESENT */
AnnaBridge 171:3a7713b1edbc 72 /* MBED */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /**
AnnaBridge 171:3a7713b1edbc 75 * @}
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 171:3a7713b1edbc 79 * @{
AnnaBridge 171:3a7713b1edbc 80 */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /**
AnnaBridge 171:3a7713b1edbc 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 84 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 85 */
AnnaBridge 171:3a7713b1edbc 86 typedef enum
AnnaBridge 171:3a7713b1edbc 87 {
AnnaBridge 171:3a7713b1edbc 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 171:3a7713b1edbc 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 171:3a7713b1edbc 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 171:3a7713b1edbc 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 171:3a7713b1edbc 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 171:3a7713b1edbc 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 171:3a7713b1edbc 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 171:3a7713b1edbc 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 171:3a7713b1edbc 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 171:3a7713b1edbc 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 171:3a7713b1edbc 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 171:3a7713b1edbc 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 116 ADC_IRQn = 18, /*!< ADC1 global Interrupts */
AnnaBridge 171:3a7713b1edbc 117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 171:3a7713b1edbc 118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 171:3a7713b1edbc 119 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
AnnaBridge 171:3a7713b1edbc 120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 171:3a7713b1edbc 121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 122 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 123 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 124 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 125 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 126 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 127 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 128 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 129 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 130 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 171:3a7713b1edbc 131 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 132 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 171:3a7713b1edbc 133 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 134 TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
AnnaBridge 171:3a7713b1edbc 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 171:3a7713b1edbc 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 140 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 171:3a7713b1edbc 141 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 171:3a7713b1edbc 142 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 171:3a7713b1edbc 143 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 171:3a7713b1edbc 144 RNG_IRQn = 80, /*!< RNG global Interrupt */
AnnaBridge 171:3a7713b1edbc 145 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 171:3a7713b1edbc 146 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 147 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 148 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 149 LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
AnnaBridge 171:3a7713b1edbc 150 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /**
AnnaBridge 171:3a7713b1edbc 153 * @}
AnnaBridge 171:3a7713b1edbc 154 */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 157 #include "system_stm32f4xx.h"
AnnaBridge 171:3a7713b1edbc 158 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 161 * @{
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /**
AnnaBridge 171:3a7713b1edbc 165 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 typedef struct
AnnaBridge 171:3a7713b1edbc 169 {
AnnaBridge 171:3a7713b1edbc 170 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 171 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 186 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 190 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 typedef struct
AnnaBridge 171:3a7713b1edbc 193 {
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 171:3a7713b1edbc 197 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 171:3a7713b1edbc 198 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /**
AnnaBridge 171:3a7713b1edbc 201 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 202 */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 typedef struct
AnnaBridge 171:3a7713b1edbc 205 {
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 207 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 208 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 171:3a7713b1edbc 209 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 211 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /**
AnnaBridge 171:3a7713b1edbc 214 * @brief Digital to Analog Converter
AnnaBridge 171:3a7713b1edbc 215 */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 typedef struct
AnnaBridge 171:3a7713b1edbc 218 {
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 226 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 227 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 231 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 232 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 233 } DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 typedef struct
AnnaBridge 171:3a7713b1edbc 240 {
AnnaBridge 171:3a7713b1edbc 241 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 245 }DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 typedef struct
AnnaBridge 171:3a7713b1edbc 253 {
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 171:3a7713b1edbc 260 } DMA_Stream_TypeDef;
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 typedef struct
AnnaBridge 171:3a7713b1edbc 263 {
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 265 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 266 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 267 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 268 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /**
AnnaBridge 171:3a7713b1edbc 271 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 272 */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 typedef struct
AnnaBridge 171:3a7713b1edbc 275 {
AnnaBridge 171:3a7713b1edbc 276 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 277 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 278 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 282 } EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 /**
AnnaBridge 171:3a7713b1edbc 285 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 286 */
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 typedef struct
AnnaBridge 171:3a7713b1edbc 289 {
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 291 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 292 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 293 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 295 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 296 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 297 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /**
AnnaBridge 171:3a7713b1edbc 300 * @brief General Purpose I/O
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 typedef struct
AnnaBridge 171:3a7713b1edbc 304 {
AnnaBridge 171:3a7713b1edbc 305 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 314 } GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /**
AnnaBridge 171:3a7713b1edbc 317 * @brief System configuration controller
AnnaBridge 171:3a7713b1edbc 318 */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 typedef struct
AnnaBridge 171:3a7713b1edbc 321 {
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 171:3a7713b1edbc 325 uint32_t RESERVED; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 326 __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 327 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 328 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 329 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /**
AnnaBridge 171:3a7713b1edbc 332 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 typedef struct
AnnaBridge 171:3a7713b1edbc 336 {
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 347 } I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /**
AnnaBridge 171:3a7713b1edbc 350 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 351 */
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 typedef struct
AnnaBridge 171:3a7713b1edbc 354 {
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 361 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 364 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 366 } FMPI2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /**
AnnaBridge 171:3a7713b1edbc 369 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 370 */
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 typedef struct
AnnaBridge 171:3a7713b1edbc 373 {
AnnaBridge 171:3a7713b1edbc 374 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 375 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 376 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 378 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /**
AnnaBridge 171:3a7713b1edbc 382 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 383 */
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 typedef struct
AnnaBridge 171:3a7713b1edbc 386 {
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 389 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /**
AnnaBridge 171:3a7713b1edbc 392 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 393 */
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 typedef struct
AnnaBridge 171:3a7713b1edbc 396 {
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 400 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 402 uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 405 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 171:3a7713b1edbc 406 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 407 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 409 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 410 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 171:3a7713b1edbc 411 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 412 uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 414 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 415 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 418 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 420 uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
AnnaBridge 171:3a7713b1edbc 421 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 424 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 /**
AnnaBridge 171:3a7713b1edbc 427 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 typedef struct
AnnaBridge 171:3a7713b1edbc 431 {
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 436 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 437 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 438 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 439 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 440 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 446 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 451 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 171:3a7713b1edbc 452 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 472 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 /**
AnnaBridge 171:3a7713b1edbc 475 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 476 */
AnnaBridge 171:3a7713b1edbc 477
AnnaBridge 171:3a7713b1edbc 478 typedef struct
AnnaBridge 171:3a7713b1edbc 479 {
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 481 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 482 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 489 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 /**
AnnaBridge 171:3a7713b1edbc 493 * @brief TIM
AnnaBridge 171:3a7713b1edbc 494 */
AnnaBridge 171:3a7713b1edbc 495
AnnaBridge 171:3a7713b1edbc 496 typedef struct
AnnaBridge 171:3a7713b1edbc 497 {
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 507 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 513 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 515 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 517 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 519 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 520
AnnaBridge 171:3a7713b1edbc 521 /**
AnnaBridge 171:3a7713b1edbc 522 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 523 */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 typedef struct
AnnaBridge 171:3a7713b1edbc 526 {
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 529 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 532 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 533 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 534 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536 /**
AnnaBridge 171:3a7713b1edbc 537 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 538 */
AnnaBridge 171:3a7713b1edbc 539
AnnaBridge 171:3a7713b1edbc 540 typedef struct
AnnaBridge 171:3a7713b1edbc 541 {
AnnaBridge 171:3a7713b1edbc 542 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 544 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 545 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /**
AnnaBridge 171:3a7713b1edbc 548 * @brief RNG
AnnaBridge 171:3a7713b1edbc 549 */
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 typedef struct
AnnaBridge 171:3a7713b1edbc 552 {
AnnaBridge 171:3a7713b1edbc 553 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 554 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 555 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 556 } RNG_TypeDef;
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /**
AnnaBridge 171:3a7713b1edbc 560 * @brief LPTIMER
AnnaBridge 171:3a7713b1edbc 561 */
AnnaBridge 171:3a7713b1edbc 562 typedef struct
AnnaBridge 171:3a7713b1edbc 563 {
AnnaBridge 171:3a7713b1edbc 564 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 565 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 573 } LPTIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 /**
AnnaBridge 171:3a7713b1edbc 576 * @}
AnnaBridge 171:3a7713b1edbc 577 */
AnnaBridge 171:3a7713b1edbc 578
AnnaBridge 171:3a7713b1edbc 579 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 580 * @{
AnnaBridge 171:3a7713b1edbc 581 */
AnnaBridge 171:3a7713b1edbc 582 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
AnnaBridge 171:3a7713b1edbc 583 #define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
AnnaBridge 171:3a7713b1edbc 584 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
AnnaBridge 171:3a7713b1edbc 585 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 586 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 587 #define FLASH_END 0x0801FFFFU /*!< FLASH end address */
AnnaBridge 171:3a7713b1edbc 588 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 171:3a7713b1edbc 589 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 592 #define SRAM_BASE SRAM1_BASE
AnnaBridge 171:3a7713b1edbc 593 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 171:3a7713b1edbc 594
AnnaBridge 171:3a7713b1edbc 595 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 596 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 597 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 171:3a7713b1edbc 598 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 601 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 171:3a7713b1edbc 602 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 603 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
AnnaBridge 171:3a7713b1edbc 604 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 171:3a7713b1edbc 605 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 171:3a7713b1edbc 606 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 607 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 171:3a7713b1edbc 608 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 609 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 171:3a7713b1edbc 610 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 171:3a7713b1edbc 611 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 171:3a7713b1edbc 612 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
AnnaBridge 171:3a7713b1edbc 613 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 171:3a7713b1edbc 614 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 /*!< APB2 peripherals */
AnnaBridge 171:3a7713b1edbc 617 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 618 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 619 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 171:3a7713b1edbc 620 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 171:3a7713b1edbc 621 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 171:3a7713b1edbc 622 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 623 #define ADC_BASE ADC1_COMMON_BASE
AnnaBridge 171:3a7713b1edbc 624 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 625 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 626 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 627 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 171:3a7713b1edbc 628 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 171:3a7713b1edbc 629 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
AnnaBridge 171:3a7713b1edbc 630
AnnaBridge 171:3a7713b1edbc 631 /*!< AHB1 peripherals */
AnnaBridge 171:3a7713b1edbc 632 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 633 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 634 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 171:3a7713b1edbc 635 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 171:3a7713b1edbc 636 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 637 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 638 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 639 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 171:3a7713b1edbc 640 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 171:3a7713b1edbc 641 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 171:3a7713b1edbc 642 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 171:3a7713b1edbc 643 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 171:3a7713b1edbc 644 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 171:3a7713b1edbc 645 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 171:3a7713b1edbc 646 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 171:3a7713b1edbc 647 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 171:3a7713b1edbc 648 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 171:3a7713b1edbc 649 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 171:3a7713b1edbc 650 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 171:3a7713b1edbc 651 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 171:3a7713b1edbc 652 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 171:3a7713b1edbc 653 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 171:3a7713b1edbc 654 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 171:3a7713b1edbc 655 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 171:3a7713b1edbc 656 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 171:3a7713b1edbc 657
AnnaBridge 171:3a7713b1edbc 658 #define RNG_BASE (PERIPH_BASE + 0x80000U)
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 /*!< Debug MCU registers base address */
AnnaBridge 171:3a7713b1edbc 661 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 171:3a7713b1edbc 664 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 171:3a7713b1edbc 665 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 171:3a7713b1edbc 666 /**
AnnaBridge 171:3a7713b1edbc 667 * @}
AnnaBridge 171:3a7713b1edbc 668 */
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 671 * @{
AnnaBridge 171:3a7713b1edbc 672 */
AnnaBridge 171:3a7713b1edbc 673 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 171:3a7713b1edbc 674 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 171:3a7713b1edbc 675 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 676 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 677 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 678 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 679 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 171:3a7713b1edbc 680 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 681 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 171:3a7713b1edbc 682 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
AnnaBridge 171:3a7713b1edbc 683 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 171:3a7713b1edbc 684 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 685 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 171:3a7713b1edbc 686 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
AnnaBridge 171:3a7713b1edbc 687 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 171:3a7713b1edbc 688 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 689 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 171:3a7713b1edbc 690 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 691 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
AnnaBridge 171:3a7713b1edbc 692 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 693 #define ADC ADC1_COMMON
AnnaBridge 171:3a7713b1edbc 694 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 695 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 696 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 697 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 171:3a7713b1edbc 698 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 171:3a7713b1edbc 699 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 171:3a7713b1edbc 700 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 701 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 702 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 703 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 171:3a7713b1edbc 704 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 705 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 706 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 707 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 708 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 171:3a7713b1edbc 709 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 171:3a7713b1edbc 710 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 171:3a7713b1edbc 711 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 171:3a7713b1edbc 712 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 171:3a7713b1edbc 713 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 171:3a7713b1edbc 714 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 171:3a7713b1edbc 715 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 171:3a7713b1edbc 716 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 171:3a7713b1edbc 717 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 171:3a7713b1edbc 718 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 171:3a7713b1edbc 719 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 171:3a7713b1edbc 720 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 171:3a7713b1edbc 721 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 171:3a7713b1edbc 722 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 171:3a7713b1edbc 723 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 171:3a7713b1edbc 724 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 171:3a7713b1edbc 725 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 171:3a7713b1edbc 726 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 727
AnnaBridge 171:3a7713b1edbc 728 /**
AnnaBridge 171:3a7713b1edbc 729 * @}
AnnaBridge 171:3a7713b1edbc 730 */
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 733 * @{
AnnaBridge 171:3a7713b1edbc 734 */
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 737 * @{
AnnaBridge 171:3a7713b1edbc 738 */
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 741 /* Peripheral Registers_Bits_Definition */
AnnaBridge 171:3a7713b1edbc 742 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 745 /* */
AnnaBridge 171:3a7713b1edbc 746 /* Analog to Digital Converter */
AnnaBridge 171:3a7713b1edbc 747 /* */
AnnaBridge 171:3a7713b1edbc 748 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 749
AnnaBridge 171:3a7713b1edbc 750 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 751 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 752 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 753 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 754 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 755 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 756 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 171:3a7713b1edbc 757 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 758 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 759 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 760 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 761 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 762 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 763 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 764 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 765 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 766 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 767 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 768 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 771 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 772 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 773 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 171:3a7713b1edbc 774 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 775 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 776 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 777 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 778 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 779 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 780 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 781 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 171:3a7713b1edbc 782 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 783 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 784 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 171:3a7713b1edbc 785 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 786 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 787 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 171:3a7713b1edbc 788 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 789 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 790 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 171:3a7713b1edbc 791 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 792 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 793 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 171:3a7713b1edbc 794 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 171:3a7713b1edbc 795 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 796 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 171:3a7713b1edbc 797 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 798 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 799 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 171:3a7713b1edbc 800 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 801 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 802 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 171:3a7713b1edbc 803 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 804 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 805 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 171:3a7713b1edbc 806 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 807 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 808 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 809 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 810 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 811 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 171:3a7713b1edbc 812 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 813 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 814 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 171:3a7713b1edbc 815 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 171:3a7713b1edbc 816 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 817 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 171:3a7713b1edbc 818 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 819 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 820 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 821 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 822 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 823
AnnaBridge 171:3a7713b1edbc 824 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 825 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 826 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 827 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 171:3a7713b1edbc 828 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 829 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 830 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 171:3a7713b1edbc 831 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 171:3a7713b1edbc 832 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 833 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 171:3a7713b1edbc 834 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 835 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 836 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 171:3a7713b1edbc 837 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 838 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 839 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 171:3a7713b1edbc 840 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 841 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 842 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 171:3a7713b1edbc 843 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 844 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 845 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 171:3a7713b1edbc 846 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 847 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 848 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 849 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 850 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 851 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 852 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 171:3a7713b1edbc 853 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 854 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 855 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 171:3a7713b1edbc 856 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 857 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 171:3a7713b1edbc 858 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 859 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 860 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 171:3a7713b1edbc 861 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 862 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 863 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 864 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 865 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 866 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 867 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 171:3a7713b1edbc 868 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 869 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 870 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 171:3a7713b1edbc 871 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 872 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 171:3a7713b1edbc 875 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 876 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 877 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 878 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 879 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 880 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 881 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 171:3a7713b1edbc 882 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 883 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 884 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 885 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 886 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 887 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 171:3a7713b1edbc 888 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 889 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 890 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 891 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 892 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 893 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 171:3a7713b1edbc 894 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 895 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 896 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 897 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 898 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 899 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 171:3a7713b1edbc 900 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 901 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 902 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 903 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 904 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 905 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 906 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 907 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 908 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 909 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 910 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 911 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 171:3a7713b1edbc 912 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 913 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 914 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 915 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 916 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 917 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 171:3a7713b1edbc 918 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 919 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 920 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 921 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 922 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 923 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 171:3a7713b1edbc 924 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 925 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 926 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 927 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 928 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 929
AnnaBridge 171:3a7713b1edbc 930 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 171:3a7713b1edbc 931 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 932 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 933 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 934 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 935 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 936 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 937 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 938 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 939 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 940 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 941 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 942 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 943 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 944 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 945 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 946 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 947 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 948 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 949 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 950 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 951 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 952 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 953 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 954 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 955 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 956 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 957 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 958 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 959 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 960 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 961 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 171:3a7713b1edbc 962 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 963 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 964 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 965 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 966 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 967 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 968 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 969 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 970 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 971 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 972 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 973 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 171:3a7713b1edbc 974 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 975 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 976 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 977 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 978 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 979 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 980 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 981 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 982 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 983 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 984 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 985 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 171:3a7713b1edbc 986 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 987 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 988 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 989 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 990 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 991
AnnaBridge 171:3a7713b1edbc 992 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 171:3a7713b1edbc 993 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 994 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 995 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 171:3a7713b1edbc 998 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 999 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1000 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 171:3a7713b1edbc 1001
AnnaBridge 171:3a7713b1edbc 1002 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1003 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1004 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1005 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 171:3a7713b1edbc 1006
AnnaBridge 171:3a7713b1edbc 1007 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1008 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1009 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1010 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 171:3a7713b1edbc 1011
AnnaBridge 171:3a7713b1edbc 1012 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 171:3a7713b1edbc 1013 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1014 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1015 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 171:3a7713b1edbc 1016
AnnaBridge 171:3a7713b1edbc 1017 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 171:3a7713b1edbc 1018 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1019 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1020 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 171:3a7713b1edbc 1021
AnnaBridge 171:3a7713b1edbc 1022 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1023 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1024 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1025 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1026 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1027 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1028 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1029 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1030 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1031 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1032 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1033 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1034 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1035 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1036 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1037 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1038 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1039 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1040 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1041 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1042 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1043 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1044 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1045 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1046 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1047 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1048 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1049 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1050 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1051 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1052 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1053 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1054 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1055 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1056 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 1057 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 171:3a7713b1edbc 1058 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1059 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1060 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1061 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1062
AnnaBridge 171:3a7713b1edbc 1063 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1064 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1065 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1066 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1067 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1068 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1069 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1070 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1071 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1072 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1073 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1074 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1075 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1076 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1077 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1078 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1079 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1080 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1081 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1082 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1083 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1084 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1085 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1086 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1087 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1088 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1089 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1090 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1091 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1092 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1093 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1094 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1095 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1096 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1097 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1098 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1099 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1100 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1101 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1102 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1103 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1104 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1105 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1106 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1107 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1108 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1109 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1110 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1111 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1114 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1115 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1116 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1117 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1118 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1119 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1120 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1121 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1122 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1123 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1124 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1125 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1126 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1127 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1128 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1129 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1130 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1131 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1132 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1133 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1134 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1135 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1136 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1137 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1138 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1139 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1140 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1141 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1142 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1143 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1144 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1145 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1146 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1147 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1148 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1149 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1150 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1151 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1152 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1153 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1154 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1155 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1156 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1157 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1158 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1159 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1160 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1161 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 171:3a7713b1edbc 1164 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1165 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1166 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1167 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1168 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1169 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1170 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1171 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1172 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1173 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1174 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1175 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1176 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1177 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1178 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1179 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1180 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1181 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1182 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1183 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1184 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1185 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1186 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1187 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1188 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1189 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1190 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1191 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1192 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1193 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1194 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1195 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1196 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1197 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 1198 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 171:3a7713b1edbc 1199 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1200 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1203 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1204 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1205 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1206
AnnaBridge 171:3a7713b1edbc 1207 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1208 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1209 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1210 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1211
AnnaBridge 171:3a7713b1edbc 1212 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1213 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1214 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1215 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1216
AnnaBridge 171:3a7713b1edbc 1217 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1218 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1219 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1220 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1221
AnnaBridge 171:3a7713b1edbc 1222 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 1223 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1224 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1225 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 171:3a7713b1edbc 1226 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1227 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 1228 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 1231 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1232 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1233 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 1234 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1235 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1236 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 171:3a7713b1edbc 1237 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1238 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1239 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 1240 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1241 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1242 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 1243 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1244 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1245 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 1246 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1247 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1248 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 171:3a7713b1edbc 1249
AnnaBridge 171:3a7713b1edbc 1250 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1251 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 1254 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1255 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1256 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 171:3a7713b1edbc 1257 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1258 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1259 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1260 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1261 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1262 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1263 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 1264 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 171:3a7713b1edbc 1265 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1266 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1267 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1268 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1269 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1270 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1271 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 171:3a7713b1edbc 1272 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1273 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 1274 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 171:3a7713b1edbc 1275 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1276 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1277 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1278 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 1279 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 171:3a7713b1edbc 1280 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1281 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1282 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1283 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1284 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 171:3a7713b1edbc 1285 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1286 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1287 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 171:3a7713b1edbc 1288
AnnaBridge 171:3a7713b1edbc 1289 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 171:3a7713b1edbc 1290 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1291 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1292 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 171:3a7713b1edbc 1293 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1294 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 1295 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 171:3a7713b1edbc 1296
AnnaBridge 171:3a7713b1edbc 1297 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1298 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 171:3a7713b1edbc 1299 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 171:3a7713b1edbc 1300
AnnaBridge 171:3a7713b1edbc 1301 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1302 /* */
AnnaBridge 171:3a7713b1edbc 1303 /* CRC calculation unit */
AnnaBridge 171:3a7713b1edbc 1304 /* */
AnnaBridge 171:3a7713b1edbc 1305 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1306 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 1307 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1308 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1309 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 1310
AnnaBridge 171:3a7713b1edbc 1311
AnnaBridge 171:3a7713b1edbc 1312 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 1313 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1314 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1315 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 1316
AnnaBridge 171:3a7713b1edbc 1317
AnnaBridge 171:3a7713b1edbc 1318 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1319 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1320 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1321 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1324 /* */
AnnaBridge 171:3a7713b1edbc 1325 /* Digital to Analog Converter */
AnnaBridge 171:3a7713b1edbc 1326 /* */
AnnaBridge 171:3a7713b1edbc 1327 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1328 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1329 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1330 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1331 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 171:3a7713b1edbc 1332 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1333 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1334 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 171:3a7713b1edbc 1335 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1336 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1337 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 171:3a7713b1edbc 1338
AnnaBridge 171:3a7713b1edbc 1339 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1340 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1341 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 1342 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1343 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1344 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1345
AnnaBridge 171:3a7713b1edbc 1346 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1347 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1348 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 1349 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1350 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1351
AnnaBridge 171:3a7713b1edbc 1352 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1353 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 1354 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 1355 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1356 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1357 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1358 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1359
AnnaBridge 171:3a7713b1edbc 1360 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1361 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1362 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 171:3a7713b1edbc 1363 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1364 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1365 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
AnnaBridge 171:3a7713b1edbc 1366 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1367 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1368 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 171:3a7713b1edbc 1369 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1370 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1371 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 171:3a7713b1edbc 1372 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1373 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1374 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 171:3a7713b1edbc 1375
AnnaBridge 171:3a7713b1edbc 1376 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1377 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 1378 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 1379 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1380 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1381 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1382
AnnaBridge 171:3a7713b1edbc 1383 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1384 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 1385 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 1386 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1387 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1390 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 1391 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 1392 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1393 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1394 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1395 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1396
AnnaBridge 171:3a7713b1edbc 1397 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1398 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1399 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 171:3a7713b1edbc 1400 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1401 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1402 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
AnnaBridge 171:3a7713b1edbc 1403
AnnaBridge 171:3a7713b1edbc 1404 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 171:3a7713b1edbc 1405 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1406 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1407 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 171:3a7713b1edbc 1408 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1409 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1410 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 171:3a7713b1edbc 1411
AnnaBridge 171:3a7713b1edbc 1412 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 1413 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1414 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1415 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1416
AnnaBridge 171:3a7713b1edbc 1417 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 171:3a7713b1edbc 1418 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1419 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1420 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1421
AnnaBridge 171:3a7713b1edbc 1422 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 171:3a7713b1edbc 1423 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1424 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1425 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1426
AnnaBridge 171:3a7713b1edbc 1427 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 1428 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1429 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1430 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1431
AnnaBridge 171:3a7713b1edbc 1432 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 171:3a7713b1edbc 1433 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1434 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1435 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1436
AnnaBridge 171:3a7713b1edbc 1437 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 171:3a7713b1edbc 1438 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1439 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1440 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1441
AnnaBridge 171:3a7713b1edbc 1442 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 171:3a7713b1edbc 1443 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1444 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1445 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1446 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1447 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 1448 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1449
AnnaBridge 171:3a7713b1edbc 1450 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 171:3a7713b1edbc 1451 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1452 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1453 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1454 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1455 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 171:3a7713b1edbc 1456 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1457
AnnaBridge 171:3a7713b1edbc 1458 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 171:3a7713b1edbc 1459 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1460 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1461 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1462 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1463 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 1464 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1465
AnnaBridge 171:3a7713b1edbc 1466 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1467 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1468 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1469 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 171:3a7713b1edbc 1470
AnnaBridge 171:3a7713b1edbc 1471 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1472 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1473 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1474 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 171:3a7713b1edbc 1475
AnnaBridge 171:3a7713b1edbc 1476 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 1477 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1478 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1479 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 1480 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1481 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1482 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 1483
AnnaBridge 171:3a7713b1edbc 1484
AnnaBridge 171:3a7713b1edbc 1485 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1486 /* */
AnnaBridge 171:3a7713b1edbc 1487 /* DMA Controller */
AnnaBridge 171:3a7713b1edbc 1488 /* */
AnnaBridge 171:3a7713b1edbc 1489 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1490 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 171:3a7713b1edbc 1491 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1492 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 171:3a7713b1edbc 1493 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 171:3a7713b1edbc 1494 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 171:3a7713b1edbc 1495 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 171:3a7713b1edbc 1496 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 171:3a7713b1edbc 1497 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1498 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 171:3a7713b1edbc 1499 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 171:3a7713b1edbc 1500 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1501 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1502 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1503 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 1504 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 171:3a7713b1edbc 1505 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1506 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1507 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1508 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1509 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 171:3a7713b1edbc 1510 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1511 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1512 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 171:3a7713b1edbc 1513 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1514 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 1515 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 171:3a7713b1edbc 1516 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1517 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1518 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1519 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1520 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 171:3a7713b1edbc 1521 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1522 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 1523 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 171:3a7713b1edbc 1524 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1525 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1526 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1527 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 1528 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 171:3a7713b1edbc 1529 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1530 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1531 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1532 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1533 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 171:3a7713b1edbc 1534 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1535 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1536 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 171:3a7713b1edbc 1537 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1538 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1539 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 171:3a7713b1edbc 1540 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1541 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1542 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 171:3a7713b1edbc 1543 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1544 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1545 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1546 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1547 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 171:3a7713b1edbc 1548 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1549 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1550 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 171:3a7713b1edbc 1551 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1552 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1553 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 171:3a7713b1edbc 1554 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1555 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1556 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 171:3a7713b1edbc 1557 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1558 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1559 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 171:3a7713b1edbc 1560 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1561 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1562 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 171:3a7713b1edbc 1563
AnnaBridge 171:3a7713b1edbc 1564 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1565 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1566 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1567 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
AnnaBridge 171:3a7713b1edbc 1568
AnnaBridge 171:3a7713b1edbc 1569 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 171:3a7713b1edbc 1570 #define DMA_SxNDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1571 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1572 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 171:3a7713b1edbc 1573 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1574 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1575 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1576 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1577 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1578 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1579 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1580 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1581 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1582 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1583 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1584 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1585 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1586 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1587 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1588 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1589
AnnaBridge 171:3a7713b1edbc 1590 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 171:3a7713b1edbc 1591 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1592 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1593 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 171:3a7713b1edbc 1594 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1595 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1596 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 171:3a7713b1edbc 1597 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1598 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1599 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1600 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1601 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1602 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 171:3a7713b1edbc 1603 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1604 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 1605 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 171:3a7713b1edbc 1606 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1607 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1608
AnnaBridge 171:3a7713b1edbc 1609 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 171:3a7713b1edbc 1610 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1611 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1612 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 171:3a7713b1edbc 1613 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1614 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1615 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 171:3a7713b1edbc 1616 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1617 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1618 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1619 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1620 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1621 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1622 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1623 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1624 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1625 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1626 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1627 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 171:3a7713b1edbc 1628 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1629 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1630 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 171:3a7713b1edbc 1631 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1632 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1633 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1634 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1635 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1636 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1637 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1638 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1639 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1640 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1641 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1642 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 171:3a7713b1edbc 1643 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1644 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1645 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 171:3a7713b1edbc 1646 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1647 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1648 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1649 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1650 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1651 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1652 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1653 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1654 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1655 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1656 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1657 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 171:3a7713b1edbc 1658 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1659 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1660 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 171:3a7713b1edbc 1661 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1662 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1663 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1664 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1665 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1666 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1667 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1668 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1669 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1670
AnnaBridge 171:3a7713b1edbc 1671 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 171:3a7713b1edbc 1672 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1673 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1674 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 171:3a7713b1edbc 1675 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1676 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1677 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 171:3a7713b1edbc 1678 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1679 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1680 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1681 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1682 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1683 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1684 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1685 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1686 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1687 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1688 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1689 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 171:3a7713b1edbc 1690 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1691 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1692 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 171:3a7713b1edbc 1693 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1694 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1695 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1696 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1697 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1698 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1699 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1700 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1701 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1702 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1703 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1704 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 171:3a7713b1edbc 1705 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1706 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1707 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 171:3a7713b1edbc 1708 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1709 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1710 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1711 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1712 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1713 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1714 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1715 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1716 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1717 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1718 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1719 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 171:3a7713b1edbc 1720 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1721 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1722 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 171:3a7713b1edbc 1723 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1724 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1725 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1726 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1727 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1728 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1729 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1730 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1731 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1732
AnnaBridge 171:3a7713b1edbc 1733 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 171:3a7713b1edbc 1734 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1735 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1736 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 171:3a7713b1edbc 1737 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1738 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1739 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 171:3a7713b1edbc 1740 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1741 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1742 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1743 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1744 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1745 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1746 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1747 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1748 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 171:3a7713b1edbc 1749 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1750 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1751 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 171:3a7713b1edbc 1752 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1753 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1754 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 171:3a7713b1edbc 1755 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1756 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1757 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1758 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1759 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1760 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1761 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1762 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1763 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 171:3a7713b1edbc 1764 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1765 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1766 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 171:3a7713b1edbc 1767 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1768 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1769 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 171:3a7713b1edbc 1770 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1771 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1772 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1773 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1774 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1775 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1776 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1777 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1778 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 171:3a7713b1edbc 1779 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1780 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1781 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 171:3a7713b1edbc 1782 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1783 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1784 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 171:3a7713b1edbc 1785 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1786 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1787 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1788 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1789 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1790 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1791 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1792 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1793 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 171:3a7713b1edbc 1794
AnnaBridge 171:3a7713b1edbc 1795 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 171:3a7713b1edbc 1796 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1797 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1798 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 171:3a7713b1edbc 1799 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1800 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1801 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 171:3a7713b1edbc 1802 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1803 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1804 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1805 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1806 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1807 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1808 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1809 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1810 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 171:3a7713b1edbc 1811 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1812 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1813 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 171:3a7713b1edbc 1814 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1815 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1816 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 171:3a7713b1edbc 1817 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1818 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1819 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1820 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1821 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1822 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1823 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1824 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1825 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 171:3a7713b1edbc 1826 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1827 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1828 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 171:3a7713b1edbc 1829 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1830 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1831 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 171:3a7713b1edbc 1832 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1833 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1834 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1835 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1836 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1837 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1838 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1839 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1840 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 171:3a7713b1edbc 1841 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1842 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1843 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 171:3a7713b1edbc 1844 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1845 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1846 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 171:3a7713b1edbc 1847 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1848 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1849 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1850 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1851 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1852 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1853 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1854 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1855 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 171:3a7713b1edbc 1856
AnnaBridge 171:3a7713b1edbc 1857 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 171:3a7713b1edbc 1858 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1859 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1860 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 1861
AnnaBridge 171:3a7713b1edbc 1862 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 171:3a7713b1edbc 1863 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1864 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1865 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 1866
AnnaBridge 171:3a7713b1edbc 1867 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 171:3a7713b1edbc 1868 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1869 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1870 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 1871
AnnaBridge 171:3a7713b1edbc 1872
AnnaBridge 171:3a7713b1edbc 1873 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1874 /* */
AnnaBridge 171:3a7713b1edbc 1875 /* External Interrupt/Event Controller */
AnnaBridge 171:3a7713b1edbc 1876 /* */
AnnaBridge 171:3a7713b1edbc 1877 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1878 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 1879 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1880 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1881 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 1882 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1883 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1884 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 1885 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1886 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1887 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 1888 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1889 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1890 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 1891 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1892 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1893 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 1894 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1895 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1896 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 1897 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1898 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1899 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 1900 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1901 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1902 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 1903 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1904 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1905 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 1906 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1907 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1908 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 1909 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1910 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1911 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 1912 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1913 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1914 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 1915 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1916 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1917 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 1918 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1919 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1920 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 1921 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1922 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1923 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 1924 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1925 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1926 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 1927 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1928 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1929 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 1930 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1931 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1932 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 1933 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1934 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1935 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 1936 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1937 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1938 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 1939 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1940 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1941 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 1942 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1943 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1944 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 1945 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1946 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1947 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 1948 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1949 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1950 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 1951
AnnaBridge 171:3a7713b1edbc 1952 /* Reference Defines */
AnnaBridge 171:3a7713b1edbc 1953 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 171:3a7713b1edbc 1954 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 171:3a7713b1edbc 1955 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 171:3a7713b1edbc 1956 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 171:3a7713b1edbc 1957 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 171:3a7713b1edbc 1958 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 171:3a7713b1edbc 1959 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 171:3a7713b1edbc 1960 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 171:3a7713b1edbc 1961 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 171:3a7713b1edbc 1962 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 171:3a7713b1edbc 1963 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 171:3a7713b1edbc 1964 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 171:3a7713b1edbc 1965 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 171:3a7713b1edbc 1966 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 171:3a7713b1edbc 1967 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 171:3a7713b1edbc 1968 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 171:3a7713b1edbc 1969 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 171:3a7713b1edbc 1970 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 171:3a7713b1edbc 1971 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 171:3a7713b1edbc 1972 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 171:3a7713b1edbc 1973 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 171:3a7713b1edbc 1974 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 171:3a7713b1edbc 1975 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 171:3a7713b1edbc 1976 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 171:3a7713b1edbc 1977 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1978 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 1979 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 1980
AnnaBridge 171:3a7713b1edbc 1981 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 171:3a7713b1edbc 1982 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1983 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1984 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 1985 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1986 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1987 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 1988 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1989 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1990 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 1991 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1992 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1993 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 1994 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1995 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1996 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 1997 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1998 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1999 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 2000 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2001 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2002 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 2003 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2004 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2005 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 2006 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2007 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2008 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 2009 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2010 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2011 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 2012 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2013 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2014 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 2015 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2016 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2017 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 2018 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2019 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2020 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 2021 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2022 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2023 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 2024 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2025 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2026 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 2027 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2028 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2029 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 2030 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2031 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2032 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 2033 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2034 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2035 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 2036 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2037 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2038 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 2039 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2040 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2041 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 2042 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2043 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2044 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 2045 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2046 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2047 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 2048 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2049 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2050 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 2051 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2052 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2053 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 2054
AnnaBridge 171:3a7713b1edbc 2055 /* Reference Defines */
AnnaBridge 171:3a7713b1edbc 2056 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 171:3a7713b1edbc 2057 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 171:3a7713b1edbc 2058 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 171:3a7713b1edbc 2059 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 171:3a7713b1edbc 2060 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 171:3a7713b1edbc 2061 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 171:3a7713b1edbc 2062 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 171:3a7713b1edbc 2063 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 171:3a7713b1edbc 2064 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 171:3a7713b1edbc 2065 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 171:3a7713b1edbc 2066 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 171:3a7713b1edbc 2067 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 171:3a7713b1edbc 2068 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 171:3a7713b1edbc 2069 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 171:3a7713b1edbc 2070 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 171:3a7713b1edbc 2071 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 171:3a7713b1edbc 2072 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 171:3a7713b1edbc 2073 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 171:3a7713b1edbc 2074 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 171:3a7713b1edbc 2075 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 171:3a7713b1edbc 2076 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 171:3a7713b1edbc 2077 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 171:3a7713b1edbc 2078 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 171:3a7713b1edbc 2079 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 171:3a7713b1edbc 2080
AnnaBridge 171:3a7713b1edbc 2081 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 171:3a7713b1edbc 2082 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2083 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2084 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 2085 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2086 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2087 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 2088 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2089 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2090 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 2091 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2092 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2093 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 2094 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2095 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2096 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 2097 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2098 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2099 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 2100 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2101 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2102 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 2103 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2104 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2105 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 2106 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2107 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2108 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 2109 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2110 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2111 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 2112 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2113 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2114 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 2115 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2116 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2117 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 2118 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2119 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2120 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 2121 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2122 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2123 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 2124 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2125 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2126 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 2127 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2128 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2129 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 2130 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2131 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2132 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 2133 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2134 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2135 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 2136 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2137 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2138 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 2139 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2140 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2141 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 2142 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2143 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2144 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 2145 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2146 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2147 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 2148 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2149 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2150 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 2151 #define EXTI_RTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2152 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2153 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 2154
AnnaBridge 171:3a7713b1edbc 2155 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 171:3a7713b1edbc 2156 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2157 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2158 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 2159 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2160 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2161 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 2162 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2163 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2164 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 2165 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2166 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2167 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 2168 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2169 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2170 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 2171 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2172 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2173 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 2174 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2175 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2176 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 2177 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2178 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2179 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 2180 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2181 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2182 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 2183 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2184 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2185 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 2186 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2187 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2188 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 2189 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2190 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2191 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 2192 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2193 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2194 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 2195 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2196 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2197 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 2198 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2199 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2200 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 2201 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2202 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2203 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 2204 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2205 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2206 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 2207 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2208 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2209 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 2210 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2211 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2212 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 2213 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2214 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2215 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 2216 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2217 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2218 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 2219 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2220 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2221 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 2222 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2223 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2224 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 2225 #define EXTI_FTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2226 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2227 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 2228
AnnaBridge 171:3a7713b1edbc 2229 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 171:3a7713b1edbc 2230 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2231 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2232 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 2233 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2234 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2235 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 2236 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2237 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2238 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 2239 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2240 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2241 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 2242 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2243 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2244 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 2245 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2246 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2247 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 2248 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2249 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2250 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 2251 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2252 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2253 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 2254 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2255 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2256 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 2257 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2258 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2259 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 2260 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2261 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2262 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 2263 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2264 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2265 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 2266 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2267 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2268 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 2269 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2270 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2271 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 2272 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2273 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2274 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 2275 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2276 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2277 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 2278 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2279 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2280 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 2281 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2282 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2283 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 171:3a7713b1edbc 2284 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2285 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2286 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 171:3a7713b1edbc 2287 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2288 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2289 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 2290 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2291 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2292 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 171:3a7713b1edbc 2293 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2294 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2295 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 171:3a7713b1edbc 2296 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2297 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2298 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 2299 #define EXTI_SWIER_SWIER23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2300 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2301 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
AnnaBridge 171:3a7713b1edbc 2302
AnnaBridge 171:3a7713b1edbc 2303 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 171:3a7713b1edbc 2304 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2305 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2306 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 171:3a7713b1edbc 2307 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2308 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2309 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 171:3a7713b1edbc 2310 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2311 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2312 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 171:3a7713b1edbc 2313 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2314 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2315 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 171:3a7713b1edbc 2316 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2317 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2318 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 171:3a7713b1edbc 2319 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2320 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2321 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 171:3a7713b1edbc 2322 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2323 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2324 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 171:3a7713b1edbc 2325 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2326 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2327 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 171:3a7713b1edbc 2328 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2329 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2330 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 171:3a7713b1edbc 2331 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2332 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2333 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 171:3a7713b1edbc 2334 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2335 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2336 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 171:3a7713b1edbc 2337 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2338 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2339 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 171:3a7713b1edbc 2340 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2341 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2342 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 171:3a7713b1edbc 2343 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2344 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2345 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 171:3a7713b1edbc 2346 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2347 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2348 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 171:3a7713b1edbc 2349 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2350 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2351 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 171:3a7713b1edbc 2352 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2353 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2354 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 171:3a7713b1edbc 2355 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2356 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2357 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 171:3a7713b1edbc 2358 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2359 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2360 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 171:3a7713b1edbc 2361 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2362 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2363 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 171:3a7713b1edbc 2364 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2365 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2366 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 171:3a7713b1edbc 2367 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2368 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2369 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 171:3a7713b1edbc 2370 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2371 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2372 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 171:3a7713b1edbc 2373 #define EXTI_PR_PR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2374 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2375 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
AnnaBridge 171:3a7713b1edbc 2376
AnnaBridge 171:3a7713b1edbc 2377 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2378 /* */
AnnaBridge 171:3a7713b1edbc 2379 /* FLASH */
AnnaBridge 171:3a7713b1edbc 2380 /* */
AnnaBridge 171:3a7713b1edbc 2381 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2382 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 171:3a7713b1edbc 2383 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2384 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2385 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 171:3a7713b1edbc 2386 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 171:3a7713b1edbc 2387 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 171:3a7713b1edbc 2388 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 171:3a7713b1edbc 2389 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 171:3a7713b1edbc 2390 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 171:3a7713b1edbc 2391 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 171:3a7713b1edbc 2392 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 171:3a7713b1edbc 2393 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 171:3a7713b1edbc 2394
AnnaBridge 171:3a7713b1edbc 2395 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2396 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2397 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 171:3a7713b1edbc 2398 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2399 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2400 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 171:3a7713b1edbc 2401 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2402 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2403 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 171:3a7713b1edbc 2404 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2405 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2406 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 171:3a7713b1edbc 2407 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2408 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2409 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 171:3a7713b1edbc 2410 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2411 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 171:3a7713b1edbc 2412 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 171:3a7713b1edbc 2413 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2414 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 171:3a7713b1edbc 2415 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
AnnaBridge 171:3a7713b1edbc 2416
AnnaBridge 171:3a7713b1edbc 2417 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 171:3a7713b1edbc 2418 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2419 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2420 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 171:3a7713b1edbc 2421 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2422 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2423 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 171:3a7713b1edbc 2424 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2425 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2426 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 171:3a7713b1edbc 2427 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2428 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2429 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 171:3a7713b1edbc 2430 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2431 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2432 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 171:3a7713b1edbc 2433 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2434 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2435 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 171:3a7713b1edbc 2436 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2437 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2438 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 171:3a7713b1edbc 2439 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2440 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2441 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 171:3a7713b1edbc 2442
AnnaBridge 171:3a7713b1edbc 2443 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 171:3a7713b1edbc 2444 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2445 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2446 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 171:3a7713b1edbc 2447 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2448 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2449 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 171:3a7713b1edbc 2450 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2451 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2452 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 171:3a7713b1edbc 2453 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2454 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 2455 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 171:3a7713b1edbc 2456 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2457 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2458 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2459 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2460 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2461 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2462 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2463 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 171:3a7713b1edbc 2464 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2465 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2466 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2467 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2468 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 171:3a7713b1edbc 2469 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2470 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2471 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 171:3a7713b1edbc 2472 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2473 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2474 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 171:3a7713b1edbc 2475
AnnaBridge 171:3a7713b1edbc 2476 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 171:3a7713b1edbc 2477 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2478 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2479 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 171:3a7713b1edbc 2480 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2481 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2482 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 171:3a7713b1edbc 2483
AnnaBridge 171:3a7713b1edbc 2484 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 171:3a7713b1edbc 2485 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 171:3a7713b1edbc 2486 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2487 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2488 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 171:3a7713b1edbc 2489 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2490 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2491 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 171:3a7713b1edbc 2492 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2493 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2494 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 171:3a7713b1edbc 2495 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2496 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2497 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 171:3a7713b1edbc 2498 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2499 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2500 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 171:3a7713b1edbc 2501 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2502 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2503 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2504 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2505 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2506 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2507 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2508 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2509 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2510 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 2511 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 171:3a7713b1edbc 2512 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 171:3a7713b1edbc 2513 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 171:3a7713b1edbc 2514 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 171:3a7713b1edbc 2515 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 171:3a7713b1edbc 2516 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 171:3a7713b1edbc 2517 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 171:3a7713b1edbc 2518 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 171:3a7713b1edbc 2519 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 171:3a7713b1edbc 2520 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 171:3a7713b1edbc 2521 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 171:3a7713b1edbc 2522 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 171:3a7713b1edbc 2523 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 171:3a7713b1edbc 2524
AnnaBridge 171:3a7713b1edbc 2525 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 171:3a7713b1edbc 2526 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2527 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 2528 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 171:3a7713b1edbc 2529 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2530 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2531 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2532 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2533 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2534 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2535 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2536 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2537 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2538 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2539 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2540 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2541
AnnaBridge 171:3a7713b1edbc 2542 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2543 /* */
AnnaBridge 171:3a7713b1edbc 2544 /* General Purpose I/O */
AnnaBridge 171:3a7713b1edbc 2545 /* */
AnnaBridge 171:3a7713b1edbc 2546 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2547 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 2548 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2549 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2550 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 171:3a7713b1edbc 2551 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2552 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2553 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2554 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2555 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 171:3a7713b1edbc 2556 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2557 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2558 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2559 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2560 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 171:3a7713b1edbc 2561 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2562 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2563 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2564 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2565 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 171:3a7713b1edbc 2566 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2567 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2568 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2569 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2570 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 171:3a7713b1edbc 2571 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2572 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2573 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2574 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2575 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 171:3a7713b1edbc 2576 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2577 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2578 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2579 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2580 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 171:3a7713b1edbc 2581 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2582 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2583 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2584 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2585 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 171:3a7713b1edbc 2586 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2587 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2588 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2589 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2590 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 171:3a7713b1edbc 2591 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2592 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2593 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2594 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2595 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 171:3a7713b1edbc 2596 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2597 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2598 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2599 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2600 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 171:3a7713b1edbc 2601 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2602 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2603 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2604 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2605 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 171:3a7713b1edbc 2606 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2607 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2608 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2609 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2610 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 171:3a7713b1edbc 2611 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2612 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2613 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2614 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2615 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 171:3a7713b1edbc 2616 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2617 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2618 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2619 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2620 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 171:3a7713b1edbc 2621 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2622 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2623 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2624 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2625 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 171:3a7713b1edbc 2626 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2627 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2628
AnnaBridge 171:3a7713b1edbc 2629 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2630 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2631 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2632 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 171:3a7713b1edbc 2633 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2634 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2635 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2636 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2637 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 171:3a7713b1edbc 2638 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2639 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2640 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2641 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2642 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 171:3a7713b1edbc 2643 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2644 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2645 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2646 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2647 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 171:3a7713b1edbc 2648 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2649 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2650 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2651 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2652 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 171:3a7713b1edbc 2653 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2654 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2655 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2656 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2657 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 171:3a7713b1edbc 2658 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2659 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2660 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2661 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2662 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 171:3a7713b1edbc 2663 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2664 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2665 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2666 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2667 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 171:3a7713b1edbc 2668 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2669 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2670 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2671 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2672 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 171:3a7713b1edbc 2673 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2674 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2675 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2676 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2677 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 171:3a7713b1edbc 2678 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2679 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2680 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2681 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2682 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 171:3a7713b1edbc 2683 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2684 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2685 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2686 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2687 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 171:3a7713b1edbc 2688 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2689 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2690 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2691 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2692 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 171:3a7713b1edbc 2693 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2694 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2695 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2696 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2697 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 171:3a7713b1edbc 2698 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2699 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2700 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2701 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2702 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 171:3a7713b1edbc 2703 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2704 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2705 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2706 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2707 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 171:3a7713b1edbc 2708 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2709 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2710
AnnaBridge 171:3a7713b1edbc 2711 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 171:3a7713b1edbc 2712 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2713 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2714 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 171:3a7713b1edbc 2715 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2716 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2717 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 171:3a7713b1edbc 2718 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2719 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2720 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 171:3a7713b1edbc 2721 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2722 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2723 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 171:3a7713b1edbc 2724 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2725 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2726 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 171:3a7713b1edbc 2727 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2728 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2729 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 171:3a7713b1edbc 2730 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2731 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2732 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 171:3a7713b1edbc 2733 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2734 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2735 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 171:3a7713b1edbc 2736 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2737 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2738 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 171:3a7713b1edbc 2739 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2740 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2741 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 171:3a7713b1edbc 2742 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2743 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2744 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 171:3a7713b1edbc 2745 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2746 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2747 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 171:3a7713b1edbc 2748 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2749 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2750 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 171:3a7713b1edbc 2751 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2752 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2753 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 171:3a7713b1edbc 2754 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2755 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2756 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 171:3a7713b1edbc 2757 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2758 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2759 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 171:3a7713b1edbc 2760
AnnaBridge 171:3a7713b1edbc 2761 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2762 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 171:3a7713b1edbc 2763 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 171:3a7713b1edbc 2764 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 171:3a7713b1edbc 2765 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 171:3a7713b1edbc 2766 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 171:3a7713b1edbc 2767 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 171:3a7713b1edbc 2768 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 171:3a7713b1edbc 2769 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 171:3a7713b1edbc 2770 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 171:3a7713b1edbc 2771 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 171:3a7713b1edbc 2772 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 171:3a7713b1edbc 2773 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 171:3a7713b1edbc 2774 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 171:3a7713b1edbc 2775 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 171:3a7713b1edbc 2776 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 171:3a7713b1edbc 2777 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
AnnaBridge 171:3a7713b1edbc 2778
AnnaBridge 171:3a7713b1edbc 2779 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 171:3a7713b1edbc 2780 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2781 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2782 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 171:3a7713b1edbc 2783 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2784 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2785 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2786 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2787 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 171:3a7713b1edbc 2788 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2789 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2790 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2791 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2792 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 171:3a7713b1edbc 2793 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2794 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2795 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2796 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2797 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 171:3a7713b1edbc 2798 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2799 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2800 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2801 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2802 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 171:3a7713b1edbc 2803 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2804 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2805 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2806 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2807 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 171:3a7713b1edbc 2808 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2809 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2810 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2811 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2812 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 171:3a7713b1edbc 2813 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2814 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2815 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2816 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2817 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 171:3a7713b1edbc 2818 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2819 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2820 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2821 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2822 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 171:3a7713b1edbc 2823 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2824 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2825 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2826 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2827 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 171:3a7713b1edbc 2828 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2829 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2830 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2831 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2832 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 171:3a7713b1edbc 2833 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2834 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2835 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2836 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2837 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 171:3a7713b1edbc 2838 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2839 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2840 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2841 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2842 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 171:3a7713b1edbc 2843 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2844 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2845 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2846 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2847 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 171:3a7713b1edbc 2848 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2849 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2850 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2851 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2852 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 171:3a7713b1edbc 2853 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2854 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2855 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2856 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2857 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 171:3a7713b1edbc 2858 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2859 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2860
AnnaBridge 171:3a7713b1edbc 2861 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2862 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 171:3a7713b1edbc 2863 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 171:3a7713b1edbc 2864 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 171:3a7713b1edbc 2865 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 171:3a7713b1edbc 2866 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 171:3a7713b1edbc 2867 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 171:3a7713b1edbc 2868 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 171:3a7713b1edbc 2869 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 171:3a7713b1edbc 2870 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 171:3a7713b1edbc 2871 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 171:3a7713b1edbc 2872 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 171:3a7713b1edbc 2873 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 171:3a7713b1edbc 2874 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 171:3a7713b1edbc 2875 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 171:3a7713b1edbc 2876 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 171:3a7713b1edbc 2877 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 171:3a7713b1edbc 2878 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 171:3a7713b1edbc 2879 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 171:3a7713b1edbc 2880 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 171:3a7713b1edbc 2881 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 171:3a7713b1edbc 2882 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 171:3a7713b1edbc 2883 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 171:3a7713b1edbc 2884 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 171:3a7713b1edbc 2885 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 171:3a7713b1edbc 2886 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 171:3a7713b1edbc 2887 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 171:3a7713b1edbc 2888 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 171:3a7713b1edbc 2889 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 171:3a7713b1edbc 2890 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 171:3a7713b1edbc 2891 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 171:3a7713b1edbc 2892 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 171:3a7713b1edbc 2893 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 171:3a7713b1edbc 2894 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 171:3a7713b1edbc 2895 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 171:3a7713b1edbc 2896 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 171:3a7713b1edbc 2897 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 171:3a7713b1edbc 2898 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 171:3a7713b1edbc 2899 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 171:3a7713b1edbc 2900 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 171:3a7713b1edbc 2901 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 171:3a7713b1edbc 2902 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 171:3a7713b1edbc 2903 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 171:3a7713b1edbc 2904 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 171:3a7713b1edbc 2905 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 171:3a7713b1edbc 2906 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 171:3a7713b1edbc 2907 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 171:3a7713b1edbc 2908 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 171:3a7713b1edbc 2909 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
AnnaBridge 171:3a7713b1edbc 2910
AnnaBridge 171:3a7713b1edbc 2911 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 171:3a7713b1edbc 2912 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2913 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2914 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 171:3a7713b1edbc 2915 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2916 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2917 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2918 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2919 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 171:3a7713b1edbc 2920 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2921 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2922 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2923 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2924 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 171:3a7713b1edbc 2925 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2926 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2927 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2928 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2929 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 171:3a7713b1edbc 2930 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2931 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2932 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2933 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2934 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 171:3a7713b1edbc 2935 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2936 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2937 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2938 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2939 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 171:3a7713b1edbc 2940 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2941 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2942 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2943 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2944 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 171:3a7713b1edbc 2945 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2946 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2947 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2948 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2949 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 171:3a7713b1edbc 2950 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2951 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2952 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2953 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2954 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 171:3a7713b1edbc 2955 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2956 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2957 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2958 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2959 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 171:3a7713b1edbc 2960 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2961 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2962 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2963 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2964 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 171:3a7713b1edbc 2965 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2966 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2967 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2968 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2969 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 171:3a7713b1edbc 2970 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2971 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2972 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2973 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2974 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 171:3a7713b1edbc 2975 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2976 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2977 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2978 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2979 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 171:3a7713b1edbc 2980 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2981 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2982 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2983 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2984 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 171:3a7713b1edbc 2985 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2986 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2987 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2988 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2989 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 171:3a7713b1edbc 2990 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2991 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2992
AnnaBridge 171:3a7713b1edbc 2993 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2994 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 171:3a7713b1edbc 2995 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 171:3a7713b1edbc 2996 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 171:3a7713b1edbc 2997 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 171:3a7713b1edbc 2998 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 171:3a7713b1edbc 2999 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 171:3a7713b1edbc 3000 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 171:3a7713b1edbc 3001 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 171:3a7713b1edbc 3002 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 171:3a7713b1edbc 3003 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 171:3a7713b1edbc 3004 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 171:3a7713b1edbc 3005 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 171:3a7713b1edbc 3006 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 171:3a7713b1edbc 3007 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 171:3a7713b1edbc 3008 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 171:3a7713b1edbc 3009 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 171:3a7713b1edbc 3010 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 171:3a7713b1edbc 3011 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 171:3a7713b1edbc 3012 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 171:3a7713b1edbc 3013 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 171:3a7713b1edbc 3014 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 171:3a7713b1edbc 3015 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 171:3a7713b1edbc 3016 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 171:3a7713b1edbc 3017 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 171:3a7713b1edbc 3018 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 171:3a7713b1edbc 3019 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 171:3a7713b1edbc 3020 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 171:3a7713b1edbc 3021 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 171:3a7713b1edbc 3022 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 171:3a7713b1edbc 3023 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 171:3a7713b1edbc 3024 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 171:3a7713b1edbc 3025 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 171:3a7713b1edbc 3026 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 171:3a7713b1edbc 3027 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 171:3a7713b1edbc 3028 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 171:3a7713b1edbc 3029 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 171:3a7713b1edbc 3030 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 171:3a7713b1edbc 3031 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 171:3a7713b1edbc 3032 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 171:3a7713b1edbc 3033 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 171:3a7713b1edbc 3034 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 171:3a7713b1edbc 3035 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 171:3a7713b1edbc 3036 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 171:3a7713b1edbc 3037 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 171:3a7713b1edbc 3038 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 171:3a7713b1edbc 3039 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 171:3a7713b1edbc 3040 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 171:3a7713b1edbc 3041 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
AnnaBridge 171:3a7713b1edbc 3042
AnnaBridge 171:3a7713b1edbc 3043 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 3044 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3045 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3046 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 171:3a7713b1edbc 3047 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3048 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3049 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 171:3a7713b1edbc 3050 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3051 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3052 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 171:3a7713b1edbc 3053 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3054 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3055 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 171:3a7713b1edbc 3056 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3057 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3058 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 171:3a7713b1edbc 3059 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3060 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3061 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 171:3a7713b1edbc 3062 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3063 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3064 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 171:3a7713b1edbc 3065 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3066 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3067 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 171:3a7713b1edbc 3068 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3069 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3070 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 171:3a7713b1edbc 3071 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3072 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3073 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 171:3a7713b1edbc 3074 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3075 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3076 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 171:3a7713b1edbc 3077 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3078 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3079 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 171:3a7713b1edbc 3080 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3081 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3082 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 171:3a7713b1edbc 3083 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3084 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3085 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 171:3a7713b1edbc 3086 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3087 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3088 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 171:3a7713b1edbc 3089 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3090 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3091 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 171:3a7713b1edbc 3092
AnnaBridge 171:3a7713b1edbc 3093 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3094 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 171:3a7713b1edbc 3095 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 171:3a7713b1edbc 3096 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 171:3a7713b1edbc 3097 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 171:3a7713b1edbc 3098 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 171:3a7713b1edbc 3099 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 171:3a7713b1edbc 3100 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 171:3a7713b1edbc 3101 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 171:3a7713b1edbc 3102 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 171:3a7713b1edbc 3103 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 171:3a7713b1edbc 3104 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 171:3a7713b1edbc 3105 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 171:3a7713b1edbc 3106 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 171:3a7713b1edbc 3107 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 171:3a7713b1edbc 3108 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 171:3a7713b1edbc 3109 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
AnnaBridge 171:3a7713b1edbc 3110
AnnaBridge 171:3a7713b1edbc 3111 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 171:3a7713b1edbc 3112 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3113 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3114 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 171:3a7713b1edbc 3115 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3116 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3117 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 171:3a7713b1edbc 3118 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3119 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3120 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 171:3a7713b1edbc 3121 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3122 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3123 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 171:3a7713b1edbc 3124 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3125 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3126 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 171:3a7713b1edbc 3127 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3128 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3129 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 171:3a7713b1edbc 3130 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3131 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3132 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 171:3a7713b1edbc 3133 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3134 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3135 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 171:3a7713b1edbc 3136 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3137 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3138 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 171:3a7713b1edbc 3139 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3140 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3141 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 171:3a7713b1edbc 3142 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3143 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3144 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 171:3a7713b1edbc 3145 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3146 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3147 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 171:3a7713b1edbc 3148 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3149 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3150 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 171:3a7713b1edbc 3151 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3152 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3153 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 171:3a7713b1edbc 3154 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3155 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3156 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 171:3a7713b1edbc 3157 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3158 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3159 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 171:3a7713b1edbc 3160 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3161 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 171:3a7713b1edbc 3162 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 171:3a7713b1edbc 3163 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 171:3a7713b1edbc 3164 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 171:3a7713b1edbc 3165 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 171:3a7713b1edbc 3166 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 171:3a7713b1edbc 3167 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 171:3a7713b1edbc 3168 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 171:3a7713b1edbc 3169 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 171:3a7713b1edbc 3170 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 171:3a7713b1edbc 3171 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 171:3a7713b1edbc 3172 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 171:3a7713b1edbc 3173 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 171:3a7713b1edbc 3174 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 171:3a7713b1edbc 3175 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 171:3a7713b1edbc 3176 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
AnnaBridge 171:3a7713b1edbc 3177
AnnaBridge 171:3a7713b1edbc 3178 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 171:3a7713b1edbc 3179 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3180 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3181 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 171:3a7713b1edbc 3182 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3183 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3184 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 171:3a7713b1edbc 3185 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3186 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3187 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 171:3a7713b1edbc 3188 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3189 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3190 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 171:3a7713b1edbc 3191 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3192 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3193 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 171:3a7713b1edbc 3194 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3195 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3196 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 171:3a7713b1edbc 3197 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3198 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3199 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 171:3a7713b1edbc 3200 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3201 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3202 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 171:3a7713b1edbc 3203 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3204 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3205 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 171:3a7713b1edbc 3206 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3207 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3208 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 171:3a7713b1edbc 3209 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3210 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3211 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 171:3a7713b1edbc 3212 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3213 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3214 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 171:3a7713b1edbc 3215 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3216 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3217 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 171:3a7713b1edbc 3218 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3219 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3220 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 171:3a7713b1edbc 3221 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3222 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3223 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 171:3a7713b1edbc 3224 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3225 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3226 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 171:3a7713b1edbc 3227 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3228 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3229 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 171:3a7713b1edbc 3230 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3231 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3232 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 171:3a7713b1edbc 3233 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3234 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3235 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 171:3a7713b1edbc 3236 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3237 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3238 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 171:3a7713b1edbc 3239 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3240 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3241 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 171:3a7713b1edbc 3242 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3243 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3244 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 171:3a7713b1edbc 3245 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3246 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3247 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 171:3a7713b1edbc 3248 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3249 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3250 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 171:3a7713b1edbc 3251 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3252 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3253 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 171:3a7713b1edbc 3254 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3255 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3256 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 171:3a7713b1edbc 3257 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3258 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3259 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 171:3a7713b1edbc 3260 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3261 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3262 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 171:3a7713b1edbc 3263 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3264 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3265 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 171:3a7713b1edbc 3266 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3267 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3268 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 171:3a7713b1edbc 3269 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3270 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3271 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 171:3a7713b1edbc 3272 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3273 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3274 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 171:3a7713b1edbc 3275
AnnaBridge 171:3a7713b1edbc 3276 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3277 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 171:3a7713b1edbc 3278 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 171:3a7713b1edbc 3279 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 171:3a7713b1edbc 3280 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 171:3a7713b1edbc 3281 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 171:3a7713b1edbc 3282 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 171:3a7713b1edbc 3283 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 171:3a7713b1edbc 3284 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 171:3a7713b1edbc 3285 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 171:3a7713b1edbc 3286 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 171:3a7713b1edbc 3287 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 171:3a7713b1edbc 3288 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 171:3a7713b1edbc 3289 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 171:3a7713b1edbc 3290 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 171:3a7713b1edbc 3291 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 171:3a7713b1edbc 3292 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 171:3a7713b1edbc 3293 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 171:3a7713b1edbc 3294 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 171:3a7713b1edbc 3295 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 171:3a7713b1edbc 3296 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 171:3a7713b1edbc 3297 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 171:3a7713b1edbc 3298 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 171:3a7713b1edbc 3299 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 171:3a7713b1edbc 3300 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 171:3a7713b1edbc 3301 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 171:3a7713b1edbc 3302 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 171:3a7713b1edbc 3303 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 171:3a7713b1edbc 3304 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 171:3a7713b1edbc 3305 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 171:3a7713b1edbc 3306 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 171:3a7713b1edbc 3307 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 171:3a7713b1edbc 3308 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 171:3a7713b1edbc 3309 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 171:3a7713b1edbc 3310 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3311 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3312 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 3313 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3314 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3315 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 3316 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3317 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3318 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 3319 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3320 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3321 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 3322 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3323 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3324 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 3325 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3326 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3327 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 3328 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3329 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3330 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 3331 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3332 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3333 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 3334 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3335 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3336 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 3337 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3338 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3339 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 3340 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3341 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3342 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 3343 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3344 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3345 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 3346 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3347 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3348 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 3349 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3350 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3351 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 3352 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3353 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3354 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 3355 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3356 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3357 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 3358 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3359 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3360 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 3361 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 171:3a7713b1edbc 3362 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3363 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3364 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 171:3a7713b1edbc 3365 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3366 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3367 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3368 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3369 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3370 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 3371 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 171:3a7713b1edbc 3372 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3373 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3374 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3375 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3376 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3377 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3378 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 171:3a7713b1edbc 3379 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3380 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3381 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3382 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3383 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3384 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 3385 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 171:3a7713b1edbc 3386 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3387 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3388 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3389 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3390 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3391 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3392 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 171:3a7713b1edbc 3393 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3394 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3395 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3396 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3397 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3398 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3399 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 171:3a7713b1edbc 3400 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3401 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3402 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3403 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3404 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3405 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3406 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 171:3a7713b1edbc 3407 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3408 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3409 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3410 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3411 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3412 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 3413 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 171:3a7713b1edbc 3414 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3415 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3416 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3417 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3418
AnnaBridge 171:3a7713b1edbc 3419 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3420 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 171:3a7713b1edbc 3421 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 171:3a7713b1edbc 3422 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 171:3a7713b1edbc 3423 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 171:3a7713b1edbc 3424 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 171:3a7713b1edbc 3425 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 171:3a7713b1edbc 3426 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 171:3a7713b1edbc 3427 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 171:3a7713b1edbc 3428 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 171:3a7713b1edbc 3429 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 171:3a7713b1edbc 3430 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 171:3a7713b1edbc 3431 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 171:3a7713b1edbc 3432 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 171:3a7713b1edbc 3433 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 171:3a7713b1edbc 3434 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 171:3a7713b1edbc 3435 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 171:3a7713b1edbc 3436 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 171:3a7713b1edbc 3437 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 171:3a7713b1edbc 3438 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 171:3a7713b1edbc 3439 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 171:3a7713b1edbc 3440 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 171:3a7713b1edbc 3441 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 171:3a7713b1edbc 3442 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 171:3a7713b1edbc 3443 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 171:3a7713b1edbc 3444 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 171:3a7713b1edbc 3445 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 171:3a7713b1edbc 3446 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 171:3a7713b1edbc 3447 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 171:3a7713b1edbc 3448 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 171:3a7713b1edbc 3449 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 171:3a7713b1edbc 3450 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 171:3a7713b1edbc 3451 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 171:3a7713b1edbc 3452 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 171:3a7713b1edbc 3453 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 171:3a7713b1edbc 3454 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 171:3a7713b1edbc 3455 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 171:3a7713b1edbc 3456 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 171:3a7713b1edbc 3457 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 171:3a7713b1edbc 3458 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 171:3a7713b1edbc 3459 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 171:3a7713b1edbc 3460
AnnaBridge 171:3a7713b1edbc 3461 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 171:3a7713b1edbc 3462 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3463 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3464 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 171:3a7713b1edbc 3465 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3466 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3467 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3468 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3469 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3470 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 3471 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 171:3a7713b1edbc 3472 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3473 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3474 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3475 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3476 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3477 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3478 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 171:3a7713b1edbc 3479 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3480 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3481 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3482 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3483 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3484 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 3485 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 171:3a7713b1edbc 3486 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3487 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3488 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3489 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3490 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3491 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3492 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 171:3a7713b1edbc 3493 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3494 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3495 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3496 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3497 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3498 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3499 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 171:3a7713b1edbc 3500 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3501 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3502 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3503 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3504 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3505 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3506 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 171:3a7713b1edbc 3507 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3508 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3509 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3510 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3511 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3512 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 3513 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 171:3a7713b1edbc 3514 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3515 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3516 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3517 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3518
AnnaBridge 171:3a7713b1edbc 3519 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3520 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 171:3a7713b1edbc 3521 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 171:3a7713b1edbc 3522 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 171:3a7713b1edbc 3523 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 171:3a7713b1edbc 3524 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 171:3a7713b1edbc 3525 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 171:3a7713b1edbc 3526 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 171:3a7713b1edbc 3527 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 171:3a7713b1edbc 3528 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 171:3a7713b1edbc 3529 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 171:3a7713b1edbc 3530 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 171:3a7713b1edbc 3531 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 171:3a7713b1edbc 3532 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 171:3a7713b1edbc 3533 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 171:3a7713b1edbc 3534 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 171:3a7713b1edbc 3535 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 171:3a7713b1edbc 3536 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 171:3a7713b1edbc 3537 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 171:3a7713b1edbc 3538 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 171:3a7713b1edbc 3539 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 171:3a7713b1edbc 3540 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 171:3a7713b1edbc 3541 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 171:3a7713b1edbc 3542 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 171:3a7713b1edbc 3543 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 171:3a7713b1edbc 3544 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 171:3a7713b1edbc 3545 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 171:3a7713b1edbc 3546 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 171:3a7713b1edbc 3547 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 171:3a7713b1edbc 3548 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 171:3a7713b1edbc 3549 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 171:3a7713b1edbc 3550 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 171:3a7713b1edbc 3551 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 171:3a7713b1edbc 3552 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 171:3a7713b1edbc 3553 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 171:3a7713b1edbc 3554 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 171:3a7713b1edbc 3555 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 171:3a7713b1edbc 3556 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 171:3a7713b1edbc 3557 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 171:3a7713b1edbc 3558 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 171:3a7713b1edbc 3559 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 171:3a7713b1edbc 3560
AnnaBridge 171:3a7713b1edbc 3561 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 171:3a7713b1edbc 3562 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3563 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3564 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 171:3a7713b1edbc 3565 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3566 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3567 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 171:3a7713b1edbc 3568 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3569 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3570 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 171:3a7713b1edbc 3571 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3572 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3573 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 171:3a7713b1edbc 3574 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3575 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3576 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 171:3a7713b1edbc 3577 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3578 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3579 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 171:3a7713b1edbc 3580 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3581 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3582 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 171:3a7713b1edbc 3583 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3584 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3585 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 171:3a7713b1edbc 3586 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3587 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3588 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 171:3a7713b1edbc 3589 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3590 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3591 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 171:3a7713b1edbc 3592 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3593 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3594 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 171:3a7713b1edbc 3595 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3596 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3597 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 171:3a7713b1edbc 3598 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3599 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3600 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 171:3a7713b1edbc 3601 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3602 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3603 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 171:3a7713b1edbc 3604 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3605 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3606 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 171:3a7713b1edbc 3607 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3608 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3609 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 171:3a7713b1edbc 3610
AnnaBridge 171:3a7713b1edbc 3611
AnnaBridge 171:3a7713b1edbc 3612 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3613 /* */
AnnaBridge 171:3a7713b1edbc 3614 /* Inter-integrated Circuit Interface */
AnnaBridge 171:3a7713b1edbc 3615 /* */
AnnaBridge 171:3a7713b1edbc 3616 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3617 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 3618 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3619 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3620 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 171:3a7713b1edbc 3621 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3622 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3623 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 171:3a7713b1edbc 3624 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3625 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3626 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 171:3a7713b1edbc 3627 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3628 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3629 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 171:3a7713b1edbc 3630 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3631 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3632 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 171:3a7713b1edbc 3633 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3634 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3635 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 171:3a7713b1edbc 3636 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3637 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3638 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3639 #define I2C_CR1_START_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3640 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3641 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 171:3a7713b1edbc 3642 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3643 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3644 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 171:3a7713b1edbc 3645 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3646 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3647 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 171:3a7713b1edbc 3648 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3649 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3650 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 171:3a7713b1edbc 3651 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3652 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3653 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 171:3a7713b1edbc 3654 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3655 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3656 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 171:3a7713b1edbc 3657 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3658 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3659 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
AnnaBridge 171:3a7713b1edbc 3660
AnnaBridge 171:3a7713b1edbc 3661 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 3662 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3663 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 3664 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 171:3a7713b1edbc 3665 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3666 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3667 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3668 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3669 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3670 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3671
AnnaBridge 171:3a7713b1edbc 3672 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3673 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3674 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3675 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3676 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3677 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3678 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3679 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3680 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3681 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3682 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3683 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 171:3a7713b1edbc 3684 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3685 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3686 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 171:3a7713b1edbc 3689 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 171:3a7713b1edbc 3690 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 171:3a7713b1edbc 3691
AnnaBridge 171:3a7713b1edbc 3692 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3693 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3694 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 3695 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3696 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3697 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 3698 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3699 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3700 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 3701 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3702 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3703 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 3704 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3705 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3706 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 171:3a7713b1edbc 3707 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3708 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3709 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 171:3a7713b1edbc 3710 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3711 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3712 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 171:3a7713b1edbc 3713 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3714 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3715 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 171:3a7713b1edbc 3716 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3717 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3718 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 171:3a7713b1edbc 3719 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3720 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3721 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 171:3a7713b1edbc 3722
AnnaBridge 171:3a7713b1edbc 3723 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3724 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3725 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3726
AnnaBridge 171:3a7713b1edbc 3727 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 171:3a7713b1edbc 3728 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3729 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3730 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 171:3a7713b1edbc 3731 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3732 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 3733 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
AnnaBridge 171:3a7713b1edbc 3734
AnnaBridge 171:3a7713b1edbc 3735 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 171:3a7713b1edbc 3736 #define I2C_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3737 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3738 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
AnnaBridge 171:3a7713b1edbc 3739
AnnaBridge 171:3a7713b1edbc 3740 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 171:3a7713b1edbc 3741 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3742 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3743 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 171:3a7713b1edbc 3744 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3745 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3746 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 171:3a7713b1edbc 3747 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3748 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3749 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 171:3a7713b1edbc 3750 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3751 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3752 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 171:3a7713b1edbc 3753 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3754 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3755 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3756 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3757 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3758 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 171:3a7713b1edbc 3759 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3760 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3761 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 171:3a7713b1edbc 3762 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3763 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3764 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 171:3a7713b1edbc 3765 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3766 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3767 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 171:3a7713b1edbc 3768 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3769 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3770 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 171:3a7713b1edbc 3771 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3772 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3773 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 3774 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3775 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3776 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 171:3a7713b1edbc 3777 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3778 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3779 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 171:3a7713b1edbc 3780 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3781 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3782 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
AnnaBridge 171:3a7713b1edbc 3783
AnnaBridge 171:3a7713b1edbc 3784 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 171:3a7713b1edbc 3785 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3786 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3787 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 171:3a7713b1edbc 3788 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3789 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3790 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 171:3a7713b1edbc 3791 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3792 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3793 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 171:3a7713b1edbc 3794 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3795 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3796 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3797 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3798 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3799 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3800 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3801 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3802 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3803 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3804 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3805 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3806 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3807 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3808 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
AnnaBridge 171:3a7713b1edbc 3809
AnnaBridge 171:3a7713b1edbc 3810 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 3811 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3812 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 3813 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 171:3a7713b1edbc 3814 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3815 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3816 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 171:3a7713b1edbc 3817 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3818 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3819 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
AnnaBridge 171:3a7713b1edbc 3820
AnnaBridge 171:3a7713b1edbc 3821 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 171:3a7713b1edbc 3822 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3823 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 3824 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 171:3a7713b1edbc 3825
AnnaBridge 171:3a7713b1edbc 3826 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 171:3a7713b1edbc 3827 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3828 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3829 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 171:3a7713b1edbc 3830 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3831 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3832 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
AnnaBridge 171:3a7713b1edbc 3833
AnnaBridge 171:3a7713b1edbc 3834 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3835 /* */
AnnaBridge 171:3a7713b1edbc 3836 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 3837 /* */
AnnaBridge 171:3a7713b1edbc 3838 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3839 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 3840 #define FMPI2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3841 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3842 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 171:3a7713b1edbc 3843 #define FMPI2C_CR1_TXIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3844 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3845 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 171:3a7713b1edbc 3846 #define FMPI2C_CR1_RXIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3847 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3848 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 171:3a7713b1edbc 3849 #define FMPI2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3850 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3851 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 171:3a7713b1edbc 3852 #define FMPI2C_CR1_NACKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3853 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3854 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 171:3a7713b1edbc 3855 #define FMPI2C_CR1_STOPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3856 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3857 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 3858 #define FMPI2C_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3859 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3860 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 3861 #define FMPI2C_CR1_ERRIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3862 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3863 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 171:3a7713b1edbc 3864 #define FMPI2C_CR1_DFN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3865 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3866 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 3867 #define FMPI2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3868 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3869 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 171:3a7713b1edbc 3870 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3871 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3872 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 171:3a7713b1edbc 3873 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3874 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3875 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 171:3a7713b1edbc 3876 #define FMPI2C_CR1_SBC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3877 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3878 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 171:3a7713b1edbc 3879 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3880 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3881 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 171:3a7713b1edbc 3882 #define FMPI2C_CR1_GCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3883 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3884 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 171:3a7713b1edbc 3885 #define FMPI2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3886 #define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3887 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 171:3a7713b1edbc 3888 #define FMPI2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3889 #define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3890 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 171:3a7713b1edbc 3891 #define FMPI2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3892 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3893 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 171:3a7713b1edbc 3894 #define FMPI2C_CR1_PECEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3895 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3896 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 171:3a7713b1edbc 3897
AnnaBridge 171:3a7713b1edbc 3898 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 3899 #define FMPI2C_CR2_SADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3900 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 3901 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 171:3a7713b1edbc 3902 #define FMPI2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3903 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3904 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 171:3a7713b1edbc 3905 #define FMPI2C_CR2_ADD10_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3906 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3907 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 171:3a7713b1edbc 3908 #define FMPI2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3909 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3910 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 171:3a7713b1edbc 3911 #define FMPI2C_CR2_START_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3912 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3913 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
AnnaBridge 171:3a7713b1edbc 3914 #define FMPI2C_CR2_STOP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3915 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3916 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 171:3a7713b1edbc 3917 #define FMPI2C_CR2_NACK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3918 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3919 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 171:3a7713b1edbc 3920 #define FMPI2C_CR2_NBYTES_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3921 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 3922 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 171:3a7713b1edbc 3923 #define FMPI2C_CR2_RELOAD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3924 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3925 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 171:3a7713b1edbc 3926 #define FMPI2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3927 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3928 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 171:3a7713b1edbc 3929 #define FMPI2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3930 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3931 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 171:3a7713b1edbc 3932
AnnaBridge 171:3a7713b1edbc 3933 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 171:3a7713b1edbc 3934 #define FMPI2C_OAR1_OA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3935 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 3936 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 171:3a7713b1edbc 3937 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3938 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3939 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 171:3a7713b1edbc 3940 #define FMPI2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3941 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3942 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 171:3a7713b1edbc 3943
AnnaBridge 171:3a7713b1edbc 3944 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 171:3a7713b1edbc 3945 #define FMPI2C_OAR2_OA2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3946 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 3947 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 171:3a7713b1edbc 3948 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3949 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 3950 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 171:3a7713b1edbc 3951 #define FMPI2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3952 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3953 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 171:3a7713b1edbc 3954
AnnaBridge 171:3a7713b1edbc 3955 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 171:3a7713b1edbc 3956 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3957 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3958 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 171:3a7713b1edbc 3959 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3960 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3961 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 171:3a7713b1edbc 3962 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3963 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3964 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 171:3a7713b1edbc 3965 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3966 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3967 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 171:3a7713b1edbc 3968 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3969 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 3970 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 171:3a7713b1edbc 3971
AnnaBridge 171:3a7713b1edbc 3972 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 171:3a7713b1edbc 3973 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3974 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 3975 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 171:3a7713b1edbc 3976 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3977 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3978 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 171:3a7713b1edbc 3979 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3980 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3981 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 171:3a7713b1edbc 3982 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3983 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 3984 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
AnnaBridge 171:3a7713b1edbc 3985 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3986 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3987 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 171:3a7713b1edbc 3988
AnnaBridge 171:3a7713b1edbc 3989 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 171:3a7713b1edbc 3990 #define FMPI2C_ISR_TXE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3991 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3992 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 3993 #define FMPI2C_ISR_TXIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3994 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3995 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 171:3a7713b1edbc 3996 #define FMPI2C_ISR_RXNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3997 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3998 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 3999 #define FMPI2C_ISR_ADDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4000 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4001 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
AnnaBridge 171:3a7713b1edbc 4002 #define FMPI2C_ISR_NACKF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4003 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4004 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 171:3a7713b1edbc 4005 #define FMPI2C_ISR_STOPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4006 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4007 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 171:3a7713b1edbc 4008 #define FMPI2C_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4009 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4010 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 171:3a7713b1edbc 4011 #define FMPI2C_ISR_TCR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4012 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4013 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 171:3a7713b1edbc 4014 #define FMPI2C_ISR_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4015 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4016 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 4017 #define FMPI2C_ISR_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4018 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4019 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 4020 #define FMPI2C_ISR_OVR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4021 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4022 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 4023 #define FMPI2C_ISR_PECERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4024 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4025 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 171:3a7713b1edbc 4026 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4027 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4028 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 171:3a7713b1edbc 4029 #define FMPI2C_ISR_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4030 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4031 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 171:3a7713b1edbc 4032 #define FMPI2C_ISR_BUSY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4033 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4034 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 171:3a7713b1edbc 4035 #define FMPI2C_ISR_DIR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4036 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4037 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 171:3a7713b1edbc 4038 #define FMPI2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4039 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 4040 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 171:3a7713b1edbc 4041
AnnaBridge 171:3a7713b1edbc 4042 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 171:3a7713b1edbc 4043 #define FMPI2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4044 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4045 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 171:3a7713b1edbc 4046 #define FMPI2C_ICR_NACKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4047 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4048 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 171:3a7713b1edbc 4049 #define FMPI2C_ICR_STOPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4050 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4051 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 171:3a7713b1edbc 4052 #define FMPI2C_ICR_BERRCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4053 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4054 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 171:3a7713b1edbc 4055 #define FMPI2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4056 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4057 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 171:3a7713b1edbc 4058 #define FMPI2C_ICR_OVRCF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4059 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4060 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 171:3a7713b1edbc 4061 #define FMPI2C_ICR_PECCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4062 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4063 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 171:3a7713b1edbc 4064 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4065 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4066 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 171:3a7713b1edbc 4067 #define FMPI2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4068 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4069 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 171:3a7713b1edbc 4070
AnnaBridge 171:3a7713b1edbc 4071 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 171:3a7713b1edbc 4072 #define FMPI2C_PECR_PEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4073 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4074 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 171:3a7713b1edbc 4075
AnnaBridge 171:3a7713b1edbc 4076 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 171:3a7713b1edbc 4077 #define FMPI2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4078 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4079 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 171:3a7713b1edbc 4080
AnnaBridge 171:3a7713b1edbc 4081 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 171:3a7713b1edbc 4082 #define FMPI2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4083 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4084 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 171:3a7713b1edbc 4085
AnnaBridge 171:3a7713b1edbc 4086
AnnaBridge 171:3a7713b1edbc 4087
AnnaBridge 171:3a7713b1edbc 4088 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4089 /* */
AnnaBridge 171:3a7713b1edbc 4090 /* Independent WATCHDOG */
AnnaBridge 171:3a7713b1edbc 4091 /* */
AnnaBridge 171:3a7713b1edbc 4092 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4093 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 4094 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4095 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4096 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 4097
AnnaBridge 171:3a7713b1edbc 4098 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 171:3a7713b1edbc 4099 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4100 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 4101 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 4102 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 4103 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 4104 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 171:3a7713b1edbc 4105
AnnaBridge 171:3a7713b1edbc 4106 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 171:3a7713b1edbc 4107 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4108 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 4109 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 4110
AnnaBridge 171:3a7713b1edbc 4111 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 4112 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4113 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4114 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 4115 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4116 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4117 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 4118
AnnaBridge 171:3a7713b1edbc 4119
AnnaBridge 171:3a7713b1edbc 4120
AnnaBridge 171:3a7713b1edbc 4121 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4122 /* */
AnnaBridge 171:3a7713b1edbc 4123 /* Power Control */
AnnaBridge 171:3a7713b1edbc 4124 /* */
AnnaBridge 171:3a7713b1edbc 4125 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4126 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 171:3a7713b1edbc 4127 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4128 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4129 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 171:3a7713b1edbc 4130 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4131 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4132 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 171:3a7713b1edbc 4133 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4134 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4135 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 4136 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4137 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4138 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 171:3a7713b1edbc 4139 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4140 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4141 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 4142
AnnaBridge 171:3a7713b1edbc 4143 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4144 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 4145 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 171:3a7713b1edbc 4146 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4147 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4148 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4149
AnnaBridge 171:3a7713b1edbc 4150 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 4151 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 4152 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 4153 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 4154 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 4155 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 4156 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 4157 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 4158 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 4159 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4160 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4161 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 171:3a7713b1edbc 4162 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4163 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4164 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 171:3a7713b1edbc 4165 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4166 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4167 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 171:3a7713b1edbc 4168 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4169 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4170 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 171:3a7713b1edbc 4171 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4172 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4173 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 4174 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4175 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 4176 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 171:3a7713b1edbc 4177 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 4178 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 4179 #define PWR_CR_FMSSR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4180 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4181 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
AnnaBridge 171:3a7713b1edbc 4182 #define PWR_CR_FISSR_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4183 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4184 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
AnnaBridge 171:3a7713b1edbc 4185
AnnaBridge 171:3a7713b1edbc 4186 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 4187 #define PWR_CR_PMODE PWR_CR_VOS
AnnaBridge 171:3a7713b1edbc 4188
AnnaBridge 171:3a7713b1edbc 4189 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 4190 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4191 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4192 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 4193 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4194 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4195 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 171:3a7713b1edbc 4196 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4197 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4198 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 171:3a7713b1edbc 4199 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4200 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4201 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 171:3a7713b1edbc 4202 #define PWR_CSR_EWUP3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4203 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4204 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
AnnaBridge 171:3a7713b1edbc 4205 #define PWR_CSR_EWUP2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4206 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4207 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 4208 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4209 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4210 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 4211 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4212 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4213 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 171:3a7713b1edbc 4214 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4215 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4216 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 171:3a7713b1edbc 4217
AnnaBridge 171:3a7713b1edbc 4218 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 4219 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
AnnaBridge 171:3a7713b1edbc 4220
AnnaBridge 171:3a7713b1edbc 4221 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4222 /* */
AnnaBridge 171:3a7713b1edbc 4223 /* Reset and Clock Control */
AnnaBridge 171:3a7713b1edbc 4224 /* */
AnnaBridge 171:3a7713b1edbc 4225 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4226 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 4227 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4228 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4229 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 171:3a7713b1edbc 4230 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4231 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4232 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 4233
AnnaBridge 171:3a7713b1edbc 4234 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4235 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 4236 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 171:3a7713b1edbc 4237 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4238 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4239 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4240 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4241 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4242
AnnaBridge 171:3a7713b1edbc 4243 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4244 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 4245 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 171:3a7713b1edbc 4246 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4247 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4248 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4249 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4250 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4251 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4252 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4253 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4254
AnnaBridge 171:3a7713b1edbc 4255 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4256 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4257 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 171:3a7713b1edbc 4258 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4259 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4260 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 171:3a7713b1edbc 4261 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4262 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4263 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 4264 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4265 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4266 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 171:3a7713b1edbc 4267 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4268 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4269 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 171:3a7713b1edbc 4270 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4271 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4272 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 171:3a7713b1edbc 4273
AnnaBridge 171:3a7713b1edbc 4274 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 171:3a7713b1edbc 4275 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4276 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 4277 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 171:3a7713b1edbc 4278 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4279 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4280 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4281 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4282 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4283 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4284
AnnaBridge 171:3a7713b1edbc 4285 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4286 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 171:3a7713b1edbc 4287 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 171:3a7713b1edbc 4288 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4289 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4290 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4291 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4292 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4293 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4294 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4295 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4296 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4297
AnnaBridge 171:3a7713b1edbc 4298 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4299 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 4300 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 171:3a7713b1edbc 4301 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4302 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4303
AnnaBridge 171:3a7713b1edbc 4304 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4305 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4306 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 171:3a7713b1edbc 4307 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4308 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4309 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 171:3a7713b1edbc 4310 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 171:3a7713b1edbc 4311
AnnaBridge 171:3a7713b1edbc 4312 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4313 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 4314 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 171:3a7713b1edbc 4315 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4316 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4317 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4318 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4319 /*
AnnaBridge 171:3a7713b1edbc 4320 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 171:3a7713b1edbc 4321 */
AnnaBridge 171:3a7713b1edbc 4322 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
AnnaBridge 171:3a7713b1edbc 4323
AnnaBridge 171:3a7713b1edbc 4324 #define RCC_PLLCFGR_PLLR_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4325 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 4326 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
AnnaBridge 171:3a7713b1edbc 4327 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4328 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4329 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4330
AnnaBridge 171:3a7713b1edbc 4331 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 4332 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 4333 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4334 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4335 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 4336 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4337 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4338
AnnaBridge 171:3a7713b1edbc 4339 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 4340 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 4341 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 4342
AnnaBridge 171:3a7713b1edbc 4343 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 4344 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4345 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 4346 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 4347 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4348 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4349
AnnaBridge 171:3a7713b1edbc 4350 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 4351 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 4352 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 4353
AnnaBridge 171:3a7713b1edbc 4354 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 4355 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4356 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4357 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 4358 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4359 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4360 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4361 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4362
AnnaBridge 171:3a7713b1edbc 4363 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 4364 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4365 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4366 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4367 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4368 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 4369 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 4370 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 4371 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 4372 /*!< MCO1EN configuration */
AnnaBridge 171:3a7713b1edbc 4373 #define RCC_CFGR_MCO1EN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4374 #define RCC_CFGR_MCO1EN_Msk (0x1U << RCC_CFGR_MCO1EN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4375 #define RCC_CFGR_MCO1EN RCC_CFGR_MCO1EN_Msk /*!< MCO1EN bit */
AnnaBridge 171:3a7713b1edbc 4376
AnnaBridge 171:3a7713b1edbc 4377 /*!< MCO2EN configuration */
AnnaBridge 171:3a7713b1edbc 4378 #define RCC_CFGR_MCO2EN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4379 #define RCC_CFGR_MCO2EN_Msk (0x1U << RCC_CFGR_MCO2EN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4380 #define RCC_CFGR_MCO2EN RCC_CFGR_MCO2EN_Msk /*!< MCO2EN bit */
AnnaBridge 171:3a7713b1edbc 4381 /*!< PPRE1 configuration */
AnnaBridge 171:3a7713b1edbc 4382 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4383 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 171:3a7713b1edbc 4384 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 171:3a7713b1edbc 4385 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4386 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4387 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4388
AnnaBridge 171:3a7713b1edbc 4389 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 4390 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4391 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4392 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4393 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4394
AnnaBridge 171:3a7713b1edbc 4395 /*!< PPRE2 configuration */
AnnaBridge 171:3a7713b1edbc 4396 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4397 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 4398 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 4399 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4400 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4401 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4402
AnnaBridge 171:3a7713b1edbc 4403 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 4404 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4405 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4406 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4407 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4408
AnnaBridge 171:3a7713b1edbc 4409 /*!< RTCPRE configuration */
AnnaBridge 171:3a7713b1edbc 4410 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4411 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 4412 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 171:3a7713b1edbc 4413 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4414 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4415 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4416 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4417 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4418
AnnaBridge 171:3a7713b1edbc 4419 /*!< MCO1 configuration */
AnnaBridge 171:3a7713b1edbc 4420 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4421 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 4422 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 171:3a7713b1edbc 4423 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4424 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4425
AnnaBridge 171:3a7713b1edbc 4426
AnnaBridge 171:3a7713b1edbc 4427 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4428 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 4429 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 171:3a7713b1edbc 4430 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4431 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4432 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4433
AnnaBridge 171:3a7713b1edbc 4434 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4435 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 4436 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 171:3a7713b1edbc 4437 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4438 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4439 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4440
AnnaBridge 171:3a7713b1edbc 4441 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4442 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 4443 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 171:3a7713b1edbc 4444 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4445 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4446
AnnaBridge 171:3a7713b1edbc 4447 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 171:3a7713b1edbc 4448 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4449 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4450 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 4451 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4452 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4453 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 4454 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4455 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4456 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 4457 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4458 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4459 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 4460 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4461 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4462 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 171:3a7713b1edbc 4463
AnnaBridge 171:3a7713b1edbc 4464 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4465 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4466 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 171:3a7713b1edbc 4467 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4468 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4469 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 4470 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4471 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4472 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 4473 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4474 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4475 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 4476 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4477 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4478 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 4479 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4480 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4481 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 4482
AnnaBridge 171:3a7713b1edbc 4483 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4484 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4485 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 4486 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4487 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4488 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 4489 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4490 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4491 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 4492 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4493 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4494 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 4495 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4496 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4497 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 171:3a7713b1edbc 4498
AnnaBridge 171:3a7713b1edbc 4499 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4500 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4501 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 171:3a7713b1edbc 4502
AnnaBridge 171:3a7713b1edbc 4503 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 171:3a7713b1edbc 4504 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4505 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4506 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 171:3a7713b1edbc 4507 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4508 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4509 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 171:3a7713b1edbc 4510 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4511 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4512 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 171:3a7713b1edbc 4513 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4514 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4515 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 171:3a7713b1edbc 4516 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4517 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4518 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 171:3a7713b1edbc 4519 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4520 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4521 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 171:3a7713b1edbc 4522 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4523 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4524 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 171:3a7713b1edbc 4525 #define RCC_AHB1RSTR_RNGRST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4526 #define RCC_AHB1RSTR_RNGRST_Msk (0x1U << RCC_AHB1RSTR_RNGRST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4527 #define RCC_AHB1RSTR_RNGRST RCC_AHB1RSTR_RNGRST_Msk
AnnaBridge 171:3a7713b1edbc 4528
AnnaBridge 171:3a7713b1edbc 4529
AnnaBridge 171:3a7713b1edbc 4530 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 171:3a7713b1edbc 4531 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4532 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4533 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 171:3a7713b1edbc 4534 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4535 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4536 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 171:3a7713b1edbc 4537 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4538 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4539 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 4540 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4541 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4542 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 171:3a7713b1edbc 4543 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4544 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4545 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 171:3a7713b1edbc 4546 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4547 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4548 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 171:3a7713b1edbc 4549 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4550 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4551 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 171:3a7713b1edbc 4552 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4553 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4554 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 171:3a7713b1edbc 4555 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4556 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4557 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
AnnaBridge 171:3a7713b1edbc 4558 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4559 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4560 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 171:3a7713b1edbc 4561 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4562 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4563 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 171:3a7713b1edbc 4564
AnnaBridge 171:3a7713b1edbc 4565 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 171:3a7713b1edbc 4566 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4567 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4568 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 4569 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4570 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4571 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 171:3a7713b1edbc 4572 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4573 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4574 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 171:3a7713b1edbc 4575 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4576 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4577 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 171:3a7713b1edbc 4578 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4579 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4580 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 171:3a7713b1edbc 4581 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4582 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4583 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 171:3a7713b1edbc 4584 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4585 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4586 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 171:3a7713b1edbc 4587 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4588 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4589 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 171:3a7713b1edbc 4590 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4591 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4592 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 171:3a7713b1edbc 4593
AnnaBridge 171:3a7713b1edbc 4594 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 171:3a7713b1edbc 4595 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4596 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4597 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 171:3a7713b1edbc 4598 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4599 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4600 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 171:3a7713b1edbc 4601 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4602 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4603 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 171:3a7713b1edbc 4604 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4605 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4606 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 171:3a7713b1edbc 4607 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4608 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4609 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 171:3a7713b1edbc 4610 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4611 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4612 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 171:3a7713b1edbc 4613 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4614 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4615 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 171:3a7713b1edbc 4616 #define RCC_AHB1ENR_RNGEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4617 #define RCC_AHB1ENR_RNGEN_Msk (0x1U << RCC_AHB1ENR_RNGEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4618 #define RCC_AHB1ENR_RNGEN RCC_AHB1ENR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 4619
AnnaBridge 171:3a7713b1edbc 4620 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 171:3a7713b1edbc 4621 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4622 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4623 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 171:3a7713b1edbc 4624 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4625 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4626 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 171:3a7713b1edbc 4627 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4628 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4629 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 4630 #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4631 #define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4632 #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
AnnaBridge 171:3a7713b1edbc 4633 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4634 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4635 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 171:3a7713b1edbc 4636 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4637 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4638 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 171:3a7713b1edbc 4639 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4640 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4641 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 171:3a7713b1edbc 4642 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4643 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4644 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 171:3a7713b1edbc 4645 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4646 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4647 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 171:3a7713b1edbc 4648 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4649 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4650 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
AnnaBridge 171:3a7713b1edbc 4651 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4652 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4653 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 171:3a7713b1edbc 4654 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4655 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4656 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 171:3a7713b1edbc 4657
AnnaBridge 171:3a7713b1edbc 4658 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 171:3a7713b1edbc 4659 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4660 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4661 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 4662 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4663 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4664 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 171:3a7713b1edbc 4665 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4666 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4667 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 171:3a7713b1edbc 4668 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4669 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4670 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 171:3a7713b1edbc 4671 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4672 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4673 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 171:3a7713b1edbc 4674 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4675 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4676 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 171:3a7713b1edbc 4677 #define RCC_APB2ENR_EXTITEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4678 #define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4679 #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
AnnaBridge 171:3a7713b1edbc 4680 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4681 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4682 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 171:3a7713b1edbc 4683 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4684 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4685 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 171:3a7713b1edbc 4686 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4687 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4688 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 171:3a7713b1edbc 4689
AnnaBridge 171:3a7713b1edbc 4690 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 171:3a7713b1edbc 4691 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4692 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4693 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 171:3a7713b1edbc 4694 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4695 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4696 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4697 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4698 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4699 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4700 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4701 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4702 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4703 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4704 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4705 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4706 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4707 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4708 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4709 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4710 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4711 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4712 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4713 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4714 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4715 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4716 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4717 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4718 #define RCC_AHB1LPENR_RNGLPEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4719 #define RCC_AHB1LPENR_RNGLPEN_Msk (0x1U << RCC_AHB1LPENR_RNGLPEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4720 #define RCC_AHB1LPENR_RNGLPEN RCC_AHB1LPENR_RNGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4721
AnnaBridge 171:3a7713b1edbc 4722 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 171:3a7713b1edbc 4723 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4724 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4725 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4726 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4727 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4728 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4729 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4730 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4731 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4732 #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4733 #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4734 #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4735 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4736 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4737 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4738 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4739 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4740 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4741 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4742 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4743 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4744 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4745 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4746 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4747 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4748 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4749 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4750 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4751 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4752 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4753 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4754 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4755 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4756 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4757 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4758 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4759
AnnaBridge 171:3a7713b1edbc 4760 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 171:3a7713b1edbc 4761 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4762 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4763 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4764 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4765 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4766 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4767 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4768 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4769 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4770 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4771 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4772 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4773 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4774 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4775 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4776 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4777 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4778 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4779 #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4780 #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4781 #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
AnnaBridge 171:3a7713b1edbc 4782 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4783 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4784 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4785 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4786 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4787 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4788 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4789 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4790 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 171:3a7713b1edbc 4791
AnnaBridge 171:3a7713b1edbc 4792 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 171:3a7713b1edbc 4793 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4794 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4795 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 171:3a7713b1edbc 4796 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4797 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4798 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 171:3a7713b1edbc 4799 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4800 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4801 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 4802 #define RCC_BDCR_LSEMOD_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4803 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4804 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
AnnaBridge 171:3a7713b1edbc 4805
AnnaBridge 171:3a7713b1edbc 4806 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4807 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4808 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 171:3a7713b1edbc 4809 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4810 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4811
AnnaBridge 171:3a7713b1edbc 4812 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4813 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4814 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 171:3a7713b1edbc 4815 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4816 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4817 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 171:3a7713b1edbc 4818
AnnaBridge 171:3a7713b1edbc 4819 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 4820 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4821 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4822 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 171:3a7713b1edbc 4823 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4824 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4825 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 4826 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4827 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4828 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 171:3a7713b1edbc 4829 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4830 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4831 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4832 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4833 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4834 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4835 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4836 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4837 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4838 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4839 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4840 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4841 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4842 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4843 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4844 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4845 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4846 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4847 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4848 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4849 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 171:3a7713b1edbc 4850 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 4851 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 171:3a7713b1edbc 4852 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
AnnaBridge 171:3a7713b1edbc 4853
AnnaBridge 171:3a7713b1edbc 4854 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 171:3a7713b1edbc 4855 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4856 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 171:3a7713b1edbc 4857 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 171:3a7713b1edbc 4858 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4859 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 171:3a7713b1edbc 4860 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 171:3a7713b1edbc 4861 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4862 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4863 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 171:3a7713b1edbc 4864 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4865 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4866 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 171:3a7713b1edbc 4867
AnnaBridge 171:3a7713b1edbc 4868 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 171:3a7713b1edbc 4869
AnnaBridge 171:3a7713b1edbc 4870 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4871 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4872 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
AnnaBridge 171:3a7713b1edbc 4873 #define RCC_DCKCFGR_I2SSRC_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4874 #define RCC_DCKCFGR_I2SSRC_Msk (0x3U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 4875 #define RCC_DCKCFGR_I2SSRC RCC_DCKCFGR_I2SSRC_Msk
AnnaBridge 171:3a7713b1edbc 4876 #define RCC_DCKCFGR_I2SSRC_0 (0x1U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4877 #define RCC_DCKCFGR_I2SSRC_1 (0x2U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4878
AnnaBridge 171:3a7713b1edbc 4879 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
AnnaBridge 171:3a7713b1edbc 4880 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4881 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 4882 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
AnnaBridge 171:3a7713b1edbc 4883 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4884 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4885 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4886 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 4887 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
AnnaBridge 171:3a7713b1edbc 4888 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4889 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4890
AnnaBridge 171:3a7713b1edbc 4891
AnnaBridge 171:3a7713b1edbc 4892 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4893 /* */
AnnaBridge 171:3a7713b1edbc 4894 /* RNG */
AnnaBridge 171:3a7713b1edbc 4895 /* */
AnnaBridge 171:3a7713b1edbc 4896 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4897 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 171:3a7713b1edbc 4898 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4899 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4900 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 4901 #define RNG_CR_IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4902 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4903 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 171:3a7713b1edbc 4904
AnnaBridge 171:3a7713b1edbc 4905 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 171:3a7713b1edbc 4906 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4907 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4908 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 171:3a7713b1edbc 4909 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4910 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4911 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 171:3a7713b1edbc 4912 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4913 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4914 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 171:3a7713b1edbc 4915 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4916 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4917 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 171:3a7713b1edbc 4918 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4919 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4920 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 171:3a7713b1edbc 4921
AnnaBridge 171:3a7713b1edbc 4922 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4923 /* */
AnnaBridge 171:3a7713b1edbc 4924 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 4925 /* */
AnnaBridge 171:3a7713b1edbc 4926 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4927 /*
AnnaBridge 171:3a7713b1edbc 4928 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 171:3a7713b1edbc 4929 */
AnnaBridge 171:3a7713b1edbc 4930 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 171:3a7713b1edbc 4931 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 171:3a7713b1edbc 4932 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4933 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4934 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 4935 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4936 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 4937 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 4938 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4939 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4940 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4941 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 4942 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 4943 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4944 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4945 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4946 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4947 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4948 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 4949 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 4950 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4951 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4952 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4953 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4954 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4955 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 4956 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4957 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4958 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4959 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4960 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4961 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4962 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 4963 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4964 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4965 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4966 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4967 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4968 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 4969 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4970 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4971 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4972 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4973
AnnaBridge 171:3a7713b1edbc 4974 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 171:3a7713b1edbc 4975 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4976 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 4977 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 4978 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4979 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4980 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4981 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4982 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4983 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 4984 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 4985 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4986 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4987 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4988 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4989 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4990 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 4991 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 4992 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4993 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4994 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4995 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4996 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4997 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 4998 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4999 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5000 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 5001 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5002 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5003 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5004 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5005 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5006 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 5007 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5008 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5009 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5010 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5011 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5012 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5013 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5014 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5015 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5016 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5017
AnnaBridge 171:3a7713b1edbc 5018 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 5019 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5020 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5021 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 5022 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5023 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 5024 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 5025 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5026 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5027 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5028 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5029 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 5030 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5031 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5032 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 5033 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5034 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5035 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 5036 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5037 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5038 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 5039 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5040 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5041 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 5042 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5043 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5044 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 5045 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5046 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5047 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 171:3a7713b1edbc 5048 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5049 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5050 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 171:3a7713b1edbc 5051 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5052 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5053 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 5054 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5055 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5056 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 5057 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5058 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5059 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 171:3a7713b1edbc 5060 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5061 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5062 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 171:3a7713b1edbc 5063 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5064 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5065 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 5066 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5067 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5068 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 171:3a7713b1edbc 5069 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5070 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5071 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 5072 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5073 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5074 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 5075 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5076 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5077 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 5078 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5079 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5080 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 5081 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5082 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 5083 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 171:3a7713b1edbc 5084 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5085 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5086 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5087
AnnaBridge 171:3a7713b1edbc 5088 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5089 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 5090
AnnaBridge 171:3a7713b1edbc 5091 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 5092 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5093 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5094 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 5095 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5096 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5097 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 171:3a7713b1edbc 5098 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5099 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5100 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 5101 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5102 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5103 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 5104 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5105 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5106 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 5107 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5108 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5109 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 171:3a7713b1edbc 5110 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5111 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5112 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 171:3a7713b1edbc 5113 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5114 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5115 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 5116 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5117 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5118 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 5119 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5120 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5121 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 5122 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5123 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5124 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 5125 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5126 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5127 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 5128 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5129 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5130 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 5131 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5132 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5133 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 171:3a7713b1edbc 5134 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5135 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5136 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 171:3a7713b1edbc 5137 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5138 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5139 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 5140
AnnaBridge 171:3a7713b1edbc 5141 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 171:3a7713b1edbc 5142 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5143 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 5144 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 5145 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5146 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5147 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 5148
AnnaBridge 171:3a7713b1edbc 5149 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 171:3a7713b1edbc 5150 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5151 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5152 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 171:3a7713b1edbc 5153
AnnaBridge 171:3a7713b1edbc 5154 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 171:3a7713b1edbc 5155 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5156 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5157 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 171:3a7713b1edbc 5158 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5159 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 5160 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 171:3a7713b1edbc 5161
AnnaBridge 171:3a7713b1edbc 5162 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 171:3a7713b1edbc 5163 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5164 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5165 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 5166 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5167 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5168 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 5169 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5170 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 5171 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5172 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5173 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5174 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5175 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5176 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5177 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5178 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5179 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5180 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5181 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5182 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5183 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 5184 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5185 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5186 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5187 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5188 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5189 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5190 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5191 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5192 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5193 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5194 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5195 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5196 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5197 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5198 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5199 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5200 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5201 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 5202 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5203 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5204 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5205 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5206 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5207 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5208 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5209 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5210 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5211 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5212 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5213 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5214 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5215 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5216 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5217 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 5218 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5219 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5220 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5221 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5222 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5223 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5224 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5225 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5226 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5227 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5228 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5229 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5230 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5231
AnnaBridge 171:3a7713b1edbc 5232 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 171:3a7713b1edbc 5233 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5234 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5235 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 5236 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5237 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5238 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 5239 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5240 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 5241 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5242 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5243 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5244 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5245 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5246 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5247 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5248 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5249 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5250 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5251 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5252 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5253 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 5254 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5255 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5256 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5257 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5258 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5259 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5260 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5261 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5262 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5263 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5264 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5265 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5266 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5267 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5268 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5269 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5270 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5271 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 5272 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5273 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5274 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5275 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5276 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5277 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5278 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5279 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5280 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5281 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5282 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5283 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5284 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5285 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5286 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5287 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 5288 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5289 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5290 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5291 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5292 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5293 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5294 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5295 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5296 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5297 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5298 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5299 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5300 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5301
AnnaBridge 171:3a7713b1edbc 5302 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 171:3a7713b1edbc 5303 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5304 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5305 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 5306
AnnaBridge 171:3a7713b1edbc 5307 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 171:3a7713b1edbc 5308 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5309 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5310 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5311
AnnaBridge 171:3a7713b1edbc 5312 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 171:3a7713b1edbc 5313 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5314 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5315 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 5316 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5317 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5318 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 5319
AnnaBridge 171:3a7713b1edbc 5320 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 171:3a7713b1edbc 5321 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5322 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5323 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5324 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5325 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5326 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5327 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5328 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5329 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5330 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5331 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5332 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5333 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5334 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5335 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5336 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5337 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5338 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5339 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5340 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5341 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5342 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5343 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5344 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5345 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5346 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5347 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5348 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5349 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5350 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5351 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5352 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5353 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5354 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5355 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5356 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5357 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5358 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5359 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5360 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5361 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5362
AnnaBridge 171:3a7713b1edbc 5363 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 171:3a7713b1edbc 5364 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5365 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 5366 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 5367 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5368 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5369 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5370 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5371 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5372 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 5373 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5374 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5375 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 5376 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5377 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5378 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5379 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5380 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5381 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 5382 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5383 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5384 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5385 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5386 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5387 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5388 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5389 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5390 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5391 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5392
AnnaBridge 171:3a7713b1edbc 5393 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 171:3a7713b1edbc 5394 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5395 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5396 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5397
AnnaBridge 171:3a7713b1edbc 5398 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 171:3a7713b1edbc 5399 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5400 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5401 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 5402 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5403 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5404 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 5405 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5406 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5407 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 5408 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5409 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 5410 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 5411 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5412 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5413 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5414 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5415 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5416 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5417 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5418 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5419 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5420
AnnaBridge 171:3a7713b1edbc 5421 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 171:3a7713b1edbc 5422 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5423 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5424 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 171:3a7713b1edbc 5425 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5426 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5427 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 171:3a7713b1edbc 5428 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5429 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5430 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 171:3a7713b1edbc 5431 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5432 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5433 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 5434 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5435 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 5436 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 5437 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5438 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5439 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5440 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 5441 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 5442 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5443 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5444 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5445 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 5446 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 5447 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5448 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5449 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5450 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5451 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5452 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 5453 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5454 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5455 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 5456 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5457 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5458 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 5459 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5460 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5461 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 5462 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5463 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5464 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 171:3a7713b1edbc 5465 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5466 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5467 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 171:3a7713b1edbc 5468
AnnaBridge 171:3a7713b1edbc 5469 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5470 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
AnnaBridge 171:3a7713b1edbc 5471
AnnaBridge 171:3a7713b1edbc 5472 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 171:3a7713b1edbc 5473 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5474 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5475 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 5476 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5477 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5478 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5479 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5480 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5481 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5482 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5483
AnnaBridge 171:3a7713b1edbc 5484 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 171:3a7713b1edbc 5485 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5486 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5487 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 5488 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5489 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5490 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5491 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5492 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5493 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5494 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5495
AnnaBridge 171:3a7713b1edbc 5496 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 171:3a7713b1edbc 5497 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5498 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5499 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 5500
AnnaBridge 171:3a7713b1edbc 5501 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 171:3a7713b1edbc 5502 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5503 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5504 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 5505
AnnaBridge 171:3a7713b1edbc 5506 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 171:3a7713b1edbc 5507 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5508 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5509 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 5510
AnnaBridge 171:3a7713b1edbc 5511 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 171:3a7713b1edbc 5512 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5513 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5514 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 5515
AnnaBridge 171:3a7713b1edbc 5516 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 171:3a7713b1edbc 5517 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5518 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5519 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 5520
AnnaBridge 171:3a7713b1edbc 5521 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 171:3a7713b1edbc 5522 #define RTC_BKP5R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5523 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5524 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 171:3a7713b1edbc 5525
AnnaBridge 171:3a7713b1edbc 5526 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 171:3a7713b1edbc 5527 #define RTC_BKP6R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5528 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5529 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 171:3a7713b1edbc 5530
AnnaBridge 171:3a7713b1edbc 5531 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 171:3a7713b1edbc 5532 #define RTC_BKP7R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5533 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5534 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 171:3a7713b1edbc 5535
AnnaBridge 171:3a7713b1edbc 5536 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 171:3a7713b1edbc 5537 #define RTC_BKP8R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5538 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5539 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 171:3a7713b1edbc 5540
AnnaBridge 171:3a7713b1edbc 5541 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 171:3a7713b1edbc 5542 #define RTC_BKP9R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5543 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5544 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 171:3a7713b1edbc 5545
AnnaBridge 171:3a7713b1edbc 5546 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 171:3a7713b1edbc 5547 #define RTC_BKP10R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5548 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5549 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 171:3a7713b1edbc 5550
AnnaBridge 171:3a7713b1edbc 5551 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 171:3a7713b1edbc 5552 #define RTC_BKP11R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5553 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5554 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 171:3a7713b1edbc 5555
AnnaBridge 171:3a7713b1edbc 5556 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 171:3a7713b1edbc 5557 #define RTC_BKP12R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5558 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5559 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 171:3a7713b1edbc 5560
AnnaBridge 171:3a7713b1edbc 5561 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 171:3a7713b1edbc 5562 #define RTC_BKP13R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5563 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5564 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 171:3a7713b1edbc 5565
AnnaBridge 171:3a7713b1edbc 5566 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 171:3a7713b1edbc 5567 #define RTC_BKP14R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5568 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5569 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 171:3a7713b1edbc 5570
AnnaBridge 171:3a7713b1edbc 5571 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 171:3a7713b1edbc 5572 #define RTC_BKP15R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5573 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5574 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 171:3a7713b1edbc 5575
AnnaBridge 171:3a7713b1edbc 5576 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 171:3a7713b1edbc 5577 #define RTC_BKP16R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5578 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5579 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 171:3a7713b1edbc 5580
AnnaBridge 171:3a7713b1edbc 5581 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 171:3a7713b1edbc 5582 #define RTC_BKP17R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5583 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5584 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 171:3a7713b1edbc 5585
AnnaBridge 171:3a7713b1edbc 5586 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 171:3a7713b1edbc 5587 #define RTC_BKP18R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5588 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5589 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 171:3a7713b1edbc 5590
AnnaBridge 171:3a7713b1edbc 5591 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 171:3a7713b1edbc 5592 #define RTC_BKP19R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5593 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5594 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 171:3a7713b1edbc 5595
AnnaBridge 171:3a7713b1edbc 5596 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 5597 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 171:3a7713b1edbc 5598
AnnaBridge 171:3a7713b1edbc 5599 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5600 /* */
AnnaBridge 171:3a7713b1edbc 5601 /* Serial Peripheral Interface */
AnnaBridge 171:3a7713b1edbc 5602 /* */
AnnaBridge 171:3a7713b1edbc 5603 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5604
AnnaBridge 171:3a7713b1edbc 5605 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 5606 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5607 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5608 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 171:3a7713b1edbc 5609 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5610 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5611 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 171:3a7713b1edbc 5612 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5613 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5614 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 171:3a7713b1edbc 5615
AnnaBridge 171:3a7713b1edbc 5616 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5617 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 5618 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 5619 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5620 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5621 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5622
AnnaBridge 171:3a7713b1edbc 5623 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5624 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5625 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 171:3a7713b1edbc 5626 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5627 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5628 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 171:3a7713b1edbc 5629 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5630 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5631 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 171:3a7713b1edbc 5632 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5633 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5634 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 171:3a7713b1edbc 5635 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5636 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5637 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 171:3a7713b1edbc 5638 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5639 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5640 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 171:3a7713b1edbc 5641 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5642 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5643 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 5644 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5645 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5646 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 5647 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5648 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5649 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 5650 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5651 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5652 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 5653
AnnaBridge 171:3a7713b1edbc 5654 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 5655 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5656 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5657 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 5658 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5659 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5660 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 5661 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5662 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5663 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 171:3a7713b1edbc 5664 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5665 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5666 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 171:3a7713b1edbc 5667 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5668 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5669 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5670 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5671 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5672 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5673 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5674 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5675 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5676
AnnaBridge 171:3a7713b1edbc 5677 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 171:3a7713b1edbc 5678 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5679 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5680 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 5681 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5682 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5683 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 5684 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5685 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5686 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 171:3a7713b1edbc 5687 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5688 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5689 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 171:3a7713b1edbc 5690 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5691 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5692 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 171:3a7713b1edbc 5693 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5694 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5695 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 171:3a7713b1edbc 5696 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5697 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5698 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 171:3a7713b1edbc 5699 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5700 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5701 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 171:3a7713b1edbc 5702 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5703 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5704 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 171:3a7713b1edbc 5705
AnnaBridge 171:3a7713b1edbc 5706 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 171:3a7713b1edbc 5707 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5708 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5709 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 171:3a7713b1edbc 5710
AnnaBridge 171:3a7713b1edbc 5711 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 171:3a7713b1edbc 5712 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5713 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5714 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 5715
AnnaBridge 171:3a7713b1edbc 5716 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 5717 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5718 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5719 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 5720
AnnaBridge 171:3a7713b1edbc 5721 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 5722 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5723 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5724 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 5725
AnnaBridge 171:3a7713b1edbc 5726 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 171:3a7713b1edbc 5727 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5728 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5729 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 171:3a7713b1edbc 5730
AnnaBridge 171:3a7713b1edbc 5731 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5732 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 5733 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 171:3a7713b1edbc 5734 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5735 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5736
AnnaBridge 171:3a7713b1edbc 5737 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5738 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5739 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 171:3a7713b1edbc 5740
AnnaBridge 171:3a7713b1edbc 5741 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5742 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 5743 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 171:3a7713b1edbc 5744 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5745 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5746
AnnaBridge 171:3a7713b1edbc 5747 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5748 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5749 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 171:3a7713b1edbc 5750
AnnaBridge 171:3a7713b1edbc 5751 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5752 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 5753 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 171:3a7713b1edbc 5754 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5755 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5756
AnnaBridge 171:3a7713b1edbc 5757 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5758 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5759 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 171:3a7713b1edbc 5760 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5761 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5762 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 171:3a7713b1edbc 5763
AnnaBridge 171:3a7713b1edbc 5764 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 171:3a7713b1edbc 5765 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5766 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5767 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 171:3a7713b1edbc 5768 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5769 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5770 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 171:3a7713b1edbc 5771 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5772 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5773 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 171:3a7713b1edbc 5774
AnnaBridge 171:3a7713b1edbc 5775 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5776 /* */
AnnaBridge 171:3a7713b1edbc 5777 /* SYSCFG */
AnnaBridge 171:3a7713b1edbc 5778 /* */
AnnaBridge 171:3a7713b1edbc 5779 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5780 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 171:3a7713b1edbc 5781 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5782 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 5783 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 171:3a7713b1edbc 5784 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5785 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5786 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 171:3a7713b1edbc 5787 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5788 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5789 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 5790
AnnaBridge 171:3a7713b1edbc 5791 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 171:3a7713b1edbc 5792 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5793 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5794 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 5795 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5796 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5797 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 5798 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5799 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5800 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 5801 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5802 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5803 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 5804 /**
AnnaBridge 171:3a7713b1edbc 5805 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 5806 */
AnnaBridge 171:3a7713b1edbc 5807 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 171:3a7713b1edbc 5808 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 171:3a7713b1edbc 5809 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 171:3a7713b1edbc 5810 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 171:3a7713b1edbc 5811
AnnaBridge 171:3a7713b1edbc 5812 /**
AnnaBridge 171:3a7713b1edbc 5813 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 5814 */
AnnaBridge 171:3a7713b1edbc 5815 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 171:3a7713b1edbc 5816 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 171:3a7713b1edbc 5817 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 171:3a7713b1edbc 5818 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 171:3a7713b1edbc 5819
AnnaBridge 171:3a7713b1edbc 5820 /**
AnnaBridge 171:3a7713b1edbc 5821 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 5822 */
AnnaBridge 171:3a7713b1edbc 5823 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 171:3a7713b1edbc 5824 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 171:3a7713b1edbc 5825 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 171:3a7713b1edbc 5826 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 171:3a7713b1edbc 5827
AnnaBridge 171:3a7713b1edbc 5828 /**
AnnaBridge 171:3a7713b1edbc 5829 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 5830 */
AnnaBridge 171:3a7713b1edbc 5831 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 171:3a7713b1edbc 5832 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 171:3a7713b1edbc 5833 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 171:3a7713b1edbc 5834 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 171:3a7713b1edbc 5835
AnnaBridge 171:3a7713b1edbc 5836 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 171:3a7713b1edbc 5837 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5838 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5839 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 5840 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5841 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5842 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 5843 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5844 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5845 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 5846 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5847 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5848 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 5849
AnnaBridge 171:3a7713b1edbc 5850 /**
AnnaBridge 171:3a7713b1edbc 5851 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 5852 */
AnnaBridge 171:3a7713b1edbc 5853 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 171:3a7713b1edbc 5854 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 171:3a7713b1edbc 5855 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 171:3a7713b1edbc 5856 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 171:3a7713b1edbc 5857
AnnaBridge 171:3a7713b1edbc 5858 /**
AnnaBridge 171:3a7713b1edbc 5859 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 5860 */
AnnaBridge 171:3a7713b1edbc 5861 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 171:3a7713b1edbc 5862 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 171:3a7713b1edbc 5863 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 171:3a7713b1edbc 5864 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 171:3a7713b1edbc 5865
AnnaBridge 171:3a7713b1edbc 5866 /**
AnnaBridge 171:3a7713b1edbc 5867 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 5868 */
AnnaBridge 171:3a7713b1edbc 5869 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 171:3a7713b1edbc 5870 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 171:3a7713b1edbc 5871 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 171:3a7713b1edbc 5872 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 171:3a7713b1edbc 5873
AnnaBridge 171:3a7713b1edbc 5874 /**
AnnaBridge 171:3a7713b1edbc 5875 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 5876 */
AnnaBridge 171:3a7713b1edbc 5877 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 171:3a7713b1edbc 5878 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 171:3a7713b1edbc 5879 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 171:3a7713b1edbc 5880 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 171:3a7713b1edbc 5881
AnnaBridge 171:3a7713b1edbc 5882 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 171:3a7713b1edbc 5883 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5884 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5885 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 5886 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5887 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5888 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 5889 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5890 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5891 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 5892 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5893 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5894 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 5895
AnnaBridge 171:3a7713b1edbc 5896 /**
AnnaBridge 171:3a7713b1edbc 5897 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 5898 */
AnnaBridge 171:3a7713b1edbc 5899 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 171:3a7713b1edbc 5900 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 171:3a7713b1edbc 5901 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 171:3a7713b1edbc 5902 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 171:3a7713b1edbc 5903
AnnaBridge 171:3a7713b1edbc 5904 /**
AnnaBridge 171:3a7713b1edbc 5905 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 5906 */
AnnaBridge 171:3a7713b1edbc 5907 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 171:3a7713b1edbc 5908 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 171:3a7713b1edbc 5909 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 171:3a7713b1edbc 5910 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 171:3a7713b1edbc 5911
AnnaBridge 171:3a7713b1edbc 5912 /**
AnnaBridge 171:3a7713b1edbc 5913 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 5914 */
AnnaBridge 171:3a7713b1edbc 5915 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 171:3a7713b1edbc 5916 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 171:3a7713b1edbc 5917 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 171:3a7713b1edbc 5918 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 171:3a7713b1edbc 5919
AnnaBridge 171:3a7713b1edbc 5920 /**
AnnaBridge 171:3a7713b1edbc 5921 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 5922 */
AnnaBridge 171:3a7713b1edbc 5923 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 171:3a7713b1edbc 5924 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 171:3a7713b1edbc 5925 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 171:3a7713b1edbc 5926 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 171:3a7713b1edbc 5927
AnnaBridge 171:3a7713b1edbc 5928 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 171:3a7713b1edbc 5929 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5930 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5931 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 5932 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5933 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5934 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 5935 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5936 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5937 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 5938 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5939 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5940 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 5941
AnnaBridge 171:3a7713b1edbc 5942 /**
AnnaBridge 171:3a7713b1edbc 5943 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 5944 */
AnnaBridge 171:3a7713b1edbc 5945 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 171:3a7713b1edbc 5946 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 171:3a7713b1edbc 5947 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 171:3a7713b1edbc 5948 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 171:3a7713b1edbc 5949
AnnaBridge 171:3a7713b1edbc 5950 /**
AnnaBridge 171:3a7713b1edbc 5951 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 5952 */
AnnaBridge 171:3a7713b1edbc 5953 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 171:3a7713b1edbc 5954 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 171:3a7713b1edbc 5955 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 171:3a7713b1edbc 5956 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 171:3a7713b1edbc 5957
AnnaBridge 171:3a7713b1edbc 5958 /**
AnnaBridge 171:3a7713b1edbc 5959 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 5960 */
AnnaBridge 171:3a7713b1edbc 5961 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 171:3a7713b1edbc 5962 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 171:3a7713b1edbc 5963 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 171:3a7713b1edbc 5964 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 171:3a7713b1edbc 5965
AnnaBridge 171:3a7713b1edbc 5966 /**
AnnaBridge 171:3a7713b1edbc 5967 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 5968 */
AnnaBridge 171:3a7713b1edbc 5969 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 171:3a7713b1edbc 5970 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 171:3a7713b1edbc 5971 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 171:3a7713b1edbc 5972 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 171:3a7713b1edbc 5973
AnnaBridge 171:3a7713b1edbc 5974 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 171:3a7713b1edbc 5975 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5976 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5977 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 171:3a7713b1edbc 5978 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5979 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5980 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
AnnaBridge 171:3a7713b1edbc 5981 /****************** Bit definition for SYSCFG_CFGR register *****************/
AnnaBridge 171:3a7713b1edbc 5982 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5983 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5984 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
AnnaBridge 171:3a7713b1edbc 5985 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5986 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5987 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
AnnaBridge 171:3a7713b1edbc 5988
AnnaBridge 171:3a7713b1edbc 5989 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
AnnaBridge 171:3a7713b1edbc 5990 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5991 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5992 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
AnnaBridge 171:3a7713b1edbc 5993 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5994 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5995 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
AnnaBridge 171:3a7713b1edbc 5996
AnnaBridge 171:3a7713b1edbc 5997 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5998 /* */
AnnaBridge 171:3a7713b1edbc 5999 /* TIM */
AnnaBridge 171:3a7713b1edbc 6000 /* */
AnnaBridge 171:3a7713b1edbc 6001 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6002 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6003 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6004 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6005 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 6006 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6007 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6008 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 6009 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6010 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6011 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 6012 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6013 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6014 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 6015 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6016 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6017 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 6018
AnnaBridge 171:3a7713b1edbc 6019 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6020 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 6021 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 6022 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6023 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6024
AnnaBridge 171:3a7713b1edbc 6025 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6026 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6027 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 6028
AnnaBridge 171:3a7713b1edbc 6029 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6030 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6031 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 6032 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6033 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6034
AnnaBridge 171:3a7713b1edbc 6035 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6036 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6037 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6038 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 171:3a7713b1edbc 6039 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6040 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6041 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 171:3a7713b1edbc 6042 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6043 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6044 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 6045
AnnaBridge 171:3a7713b1edbc 6046 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6047 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6048 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 6049 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6050 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6051 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6052
AnnaBridge 171:3a7713b1edbc 6053 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6054 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6055 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 6056 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6057 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6058 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 171:3a7713b1edbc 6059 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6060 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6061 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 171:3a7713b1edbc 6062 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6063 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6064 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 171:3a7713b1edbc 6065 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6066 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6067 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 171:3a7713b1edbc 6068 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6069 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6070 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 171:3a7713b1edbc 6071 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6072 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6073 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 171:3a7713b1edbc 6074 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6075 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6076 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 6077
AnnaBridge 171:3a7713b1edbc 6078 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 171:3a7713b1edbc 6079 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6080 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 6081 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 6082 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6083 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6084 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6085
AnnaBridge 171:3a7713b1edbc 6086 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6087 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6088 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 6089 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6090 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6091 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6092
AnnaBridge 171:3a7713b1edbc 6093 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6094 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6095 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 6096
AnnaBridge 171:3a7713b1edbc 6097 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6098 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6099 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 6100 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6101 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6102 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 6103 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 6104
AnnaBridge 171:3a7713b1edbc 6105 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6106 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 6107 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 6108 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6109 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6110
AnnaBridge 171:3a7713b1edbc 6111 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6112 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6113 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 6114 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6115 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6116 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 6117
AnnaBridge 171:3a7713b1edbc 6118 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 171:3a7713b1edbc 6119 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6120 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6121 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 6122 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6123 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6124 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6125 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6126 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6127 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6128 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6129 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6130 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6131 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6132 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6133 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6134 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6135 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6136 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 171:3a7713b1edbc 6137 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6138 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6139 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 6140 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6141 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6142 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 171:3a7713b1edbc 6143 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6144 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6145 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 6146 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6147 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6148 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6149 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6150 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6151 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6152 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6153 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6154 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6155 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6156 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6157 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6158 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6159 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6160 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 6161 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6162 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6163 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 6164
AnnaBridge 171:3a7713b1edbc 6165 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 171:3a7713b1edbc 6166 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6167 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6168 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6169 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6170 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6171 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6172 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6173 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6174 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6175 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6176 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6177 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6178 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6179 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6180 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6181 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6182 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6183 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6184 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6185 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6186 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6187 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6188 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6189 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6190 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6191 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6192 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6193 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6194 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6195 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6196 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6197 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6198 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6199 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6200 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6201 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6202
AnnaBridge 171:3a7713b1edbc 6203 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 171:3a7713b1edbc 6204 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6205 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6206 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 6207 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6208 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6209 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 6210 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6211 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6212 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 6213 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6214 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6215 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 6216 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6217 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6218 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 6219 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6220 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6221 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 171:3a7713b1edbc 6222 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6223 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6224 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 6225 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6226 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6227 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 6228
AnnaBridge 171:3a7713b1edbc 6229 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6230 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6231 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6232 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 6233 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6234 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6235
AnnaBridge 171:3a7713b1edbc 6236 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6237 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6238 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 6239 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6240 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6241 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 6242
AnnaBridge 171:3a7713b1edbc 6243 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6244 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6245 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 6246 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6247 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6248 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6249
AnnaBridge 171:3a7713b1edbc 6250 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6251 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6252 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 171:3a7713b1edbc 6253
AnnaBridge 171:3a7713b1edbc 6254 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6255 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6256 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 6257 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6258 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6259
AnnaBridge 171:3a7713b1edbc 6260 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6261 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6262 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 6263 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6264 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6265 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 6266
AnnaBridge 171:3a7713b1edbc 6267 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6268 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 6269 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 6270 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6271 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6272 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 6273
AnnaBridge 171:3a7713b1edbc 6274 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6275 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6276 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6277
AnnaBridge 171:3a7713b1edbc 6278 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 6279
AnnaBridge 171:3a7713b1edbc 6280 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6281 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 6282 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6283 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6284 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6285
AnnaBridge 171:3a7713b1edbc 6286 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6287 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6288 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 6289 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6290 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6291 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6292 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6293
AnnaBridge 171:3a7713b1edbc 6294 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6295 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6296 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6297 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 6298 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 6299
AnnaBridge 171:3a7713b1edbc 6300 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6301 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6302 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 6303 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6304 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6305 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 6306 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 171:3a7713b1edbc 6307
AnnaBridge 171:3a7713b1edbc 6308 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6309 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6310 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6311 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 6312 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6313 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6314
AnnaBridge 171:3a7713b1edbc 6315 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6316 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6317 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 6318 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6319 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6320 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 6321
AnnaBridge 171:3a7713b1edbc 6322 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6323 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6324 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 6325 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6326 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6327 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6328
AnnaBridge 171:3a7713b1edbc 6329 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6330 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6331 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6332
AnnaBridge 171:3a7713b1edbc 6333 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6334 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6335 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 6336 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6337 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6338
AnnaBridge 171:3a7713b1edbc 6339 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6340 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6341 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 6342 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6343 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6344 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 6345
AnnaBridge 171:3a7713b1edbc 6346 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6347 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 6348 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 6349 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6350 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6351 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 6352
AnnaBridge 171:3a7713b1edbc 6353 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6354 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6355 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6356
AnnaBridge 171:3a7713b1edbc 6357 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 6358
AnnaBridge 171:3a7713b1edbc 6359 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6360 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 6361 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6362 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6363 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6364
AnnaBridge 171:3a7713b1edbc 6365 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6366 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6367 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 6368 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6369 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6370 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6371 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6372
AnnaBridge 171:3a7713b1edbc 6373 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6374 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6375 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6376 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 6377 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 6378
AnnaBridge 171:3a7713b1edbc 6379 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6380 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6381 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 6382 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6383 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6384 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 6385 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 171:3a7713b1edbc 6386
AnnaBridge 171:3a7713b1edbc 6387 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 171:3a7713b1edbc 6388 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6389 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6390 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 6391 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6392 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6393 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 6394 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6395 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6396 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 6397 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6398 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6399 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6400 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6401 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6402 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 6403 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6404 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6405 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 6406 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6407 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6408 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 6409 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6410 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6411 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6412 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6413 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6414 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 6415 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6416 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6417 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 6418 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6419 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6420 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 6421 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6422 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6423 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6424 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6425 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6426 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 6427 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6428 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6429 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 6430 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6431 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6432 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6433
AnnaBridge 171:3a7713b1edbc 6434 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 171:3a7713b1edbc 6435 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6436 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6437 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 6438
AnnaBridge 171:3a7713b1edbc 6439 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 171:3a7713b1edbc 6440 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6441 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6442 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 6443
AnnaBridge 171:3a7713b1edbc 6444 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 171:3a7713b1edbc 6445 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6446 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6447 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 6448
AnnaBridge 171:3a7713b1edbc 6449 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 171:3a7713b1edbc 6450 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6451 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6452 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 171:3a7713b1edbc 6453
AnnaBridge 171:3a7713b1edbc 6454 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6455 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6456 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6457 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 6458
AnnaBridge 171:3a7713b1edbc 6459 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6460 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6461 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6462 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 6463
AnnaBridge 171:3a7713b1edbc 6464 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 6465 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6466 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6467 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 6468
AnnaBridge 171:3a7713b1edbc 6469 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 6470 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6471 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6472 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 6473
AnnaBridge 171:3a7713b1edbc 6474 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 171:3a7713b1edbc 6475 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6476 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6477 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 171:3a7713b1edbc 6478 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6479 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6480 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6481 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6482 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6483 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6484 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6485 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6486
AnnaBridge 171:3a7713b1edbc 6487 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6488 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6489 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 171:3a7713b1edbc 6490 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6491 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6492
AnnaBridge 171:3a7713b1edbc 6493 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6494 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6495 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 171:3a7713b1edbc 6496 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6497 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6498 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 171:3a7713b1edbc 6499 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6500 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6501 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 171:3a7713b1edbc 6502 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6503 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6504 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 171:3a7713b1edbc 6505 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6506 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6507 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 171:3a7713b1edbc 6508 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6509 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6510 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 171:3a7713b1edbc 6511
AnnaBridge 171:3a7713b1edbc 6512 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 171:3a7713b1edbc 6513 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6514 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 6515 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 6516 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6517 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6518 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6519 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6520 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6521
AnnaBridge 171:3a7713b1edbc 6522 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6523 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 6524 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 6525 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6526 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 6527 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 6528 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 6529 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6530
AnnaBridge 171:3a7713b1edbc 6531 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 171:3a7713b1edbc 6532 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6533 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6534 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 6535
AnnaBridge 171:3a7713b1edbc 6536 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 171:3a7713b1edbc 6537 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6538 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6539 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 171:3a7713b1edbc 6540 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6541 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6542
AnnaBridge 171:3a7713b1edbc 6543 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6544 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 6545 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 171:3a7713b1edbc 6546 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6547 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6548
AnnaBridge 171:3a7713b1edbc 6549 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6550 /* */
AnnaBridge 171:3a7713b1edbc 6551 /* Low Power Timer (LPTIM) */
AnnaBridge 171:3a7713b1edbc 6552 /* */
AnnaBridge 171:3a7713b1edbc 6553 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6554 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 171:3a7713b1edbc 6555 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6556 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6557 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 171:3a7713b1edbc 6558 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6559 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6560 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 171:3a7713b1edbc 6561 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6562 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6563 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 171:3a7713b1edbc 6564 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6565 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6566 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 171:3a7713b1edbc 6567 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6568 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6569 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 171:3a7713b1edbc 6570 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6571 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6572 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 171:3a7713b1edbc 6573 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6574 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6575 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 171:3a7713b1edbc 6576
AnnaBridge 171:3a7713b1edbc 6577 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 171:3a7713b1edbc 6578 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6579 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6580 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 171:3a7713b1edbc 6581 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6582 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6583 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 171:3a7713b1edbc 6584 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6585 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6586 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 171:3a7713b1edbc 6587 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6588 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6589 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 6590 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6591 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6592 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 6593 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6594 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6595 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 171:3a7713b1edbc 6596 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6597 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6598 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 171:3a7713b1edbc 6599
AnnaBridge 171:3a7713b1edbc 6600 /****************** Bit definition for LPTIM_IER register ********************/
AnnaBridge 171:3a7713b1edbc 6601 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6602 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6603 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6604 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6605 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6606 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6607 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6608 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6609 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6610 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6611 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6612 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6613 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6614 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6615 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6616 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6617 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6618 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6619 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6620 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6621 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6622
AnnaBridge 171:3a7713b1edbc 6623 /****************** Bit definition for LPTIM_CFGR register *******************/
AnnaBridge 171:3a7713b1edbc 6624 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6625 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6626 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 171:3a7713b1edbc 6627
AnnaBridge 171:3a7713b1edbc 6628 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6629 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 6630 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 171:3a7713b1edbc 6631 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6632 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6633
AnnaBridge 171:3a7713b1edbc 6634 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6635 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 6636 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 171:3a7713b1edbc 6637 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6638 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6639
AnnaBridge 171:3a7713b1edbc 6640 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6641 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 6642 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 171:3a7713b1edbc 6643 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6644 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6645
AnnaBridge 171:3a7713b1edbc 6646 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6647 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 6648 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 171:3a7713b1edbc 6649 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6650 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6651 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6652
AnnaBridge 171:3a7713b1edbc 6653 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6654 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 6655 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 171:3a7713b1edbc 6656 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6657 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6658 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6659
AnnaBridge 171:3a7713b1edbc 6660 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6661 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 6662 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 171:3a7713b1edbc 6663 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6664 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6665
AnnaBridge 171:3a7713b1edbc 6666 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6667 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6668 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 171:3a7713b1edbc 6669 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6670 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6671 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 171:3a7713b1edbc 6672 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6673 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6674 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 171:3a7713b1edbc 6675 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6676 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6677 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 171:3a7713b1edbc 6678 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6679 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6680 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 171:3a7713b1edbc 6681 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6682 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6683 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 171:3a7713b1edbc 6684
AnnaBridge 171:3a7713b1edbc 6685 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 171:3a7713b1edbc 6686 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6687 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6688 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 171:3a7713b1edbc 6689 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6690 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6691 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 171:3a7713b1edbc 6692 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6693 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6694 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 171:3a7713b1edbc 6695
AnnaBridge 171:3a7713b1edbc 6696 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 171:3a7713b1edbc 6697 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6698 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6699 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 171:3a7713b1edbc 6700
AnnaBridge 171:3a7713b1edbc 6701 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 171:3a7713b1edbc 6702 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6703 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6704 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 171:3a7713b1edbc 6705
AnnaBridge 171:3a7713b1edbc 6706 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 171:3a7713b1edbc 6707 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6708 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6709 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 171:3a7713b1edbc 6710
AnnaBridge 171:3a7713b1edbc 6711 /****************** Bit definition for LPTIM_OR register *******************/
AnnaBridge 171:3a7713b1edbc 6712 #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6713 #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6714 #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
AnnaBridge 171:3a7713b1edbc 6715 #define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6716 #define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6717
AnnaBridge 171:3a7713b1edbc 6718 /* Legacy Defines */
AnnaBridge 171:3a7713b1edbc 6719 #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
AnnaBridge 171:3a7713b1edbc 6720 #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
AnnaBridge 171:3a7713b1edbc 6721 #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
AnnaBridge 171:3a7713b1edbc 6722
AnnaBridge 171:3a7713b1edbc 6723
AnnaBridge 171:3a7713b1edbc 6724 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6725 /* */
AnnaBridge 171:3a7713b1edbc 6726 /* Universal Synchronous Asynchronous Receiver Transmitter */
AnnaBridge 171:3a7713b1edbc 6727 /* */
AnnaBridge 171:3a7713b1edbc 6728 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6729 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 171:3a7713b1edbc 6730 #define USART_SR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6731 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6732 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 171:3a7713b1edbc 6733 #define USART_SR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6734 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6735 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 171:3a7713b1edbc 6736 #define USART_SR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6737 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6738 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 171:3a7713b1edbc 6739 #define USART_SR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6740 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6741 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 171:3a7713b1edbc 6742 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6743 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6744 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 171:3a7713b1edbc 6745 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6746 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6747 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 6748 #define USART_SR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6749 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6750 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 171:3a7713b1edbc 6751 #define USART_SR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6752 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6753 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 6754 #define USART_SR_LBD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6755 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6756 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 6757 #define USART_SR_CTS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6758 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6759 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
AnnaBridge 171:3a7713b1edbc 6760
AnnaBridge 171:3a7713b1edbc 6761 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 171:3a7713b1edbc 6762 #define USART_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6763 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 6764 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
AnnaBridge 171:3a7713b1edbc 6765
AnnaBridge 171:3a7713b1edbc 6766 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 6767 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6768 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6769 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 6770 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6771 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 6772 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 6773
AnnaBridge 171:3a7713b1edbc 6774 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6775 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6776 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6777 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 171:3a7713b1edbc 6778 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6779 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6780 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 171:3a7713b1edbc 6781 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6782 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6783 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 171:3a7713b1edbc 6784 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6785 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6786 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 6787 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6788 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6789 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6790 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6791 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6792 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6793 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6794 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6795 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6796 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6797 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6798 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6799 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6800 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6801 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6802 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6803 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6804 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 171:3a7713b1edbc 6805 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6806 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6807 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 6808 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6809 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6810 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 171:3a7713b1edbc 6811 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6812 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6813 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 171:3a7713b1edbc 6814 #define USART_CR1_UE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6815 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6816 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 171:3a7713b1edbc 6817 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6818 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6819 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
AnnaBridge 171:3a7713b1edbc 6820
AnnaBridge 171:3a7713b1edbc 6821 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6822 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6823 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6824 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 171:3a7713b1edbc 6825 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6826 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6827 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 6828 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6829 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6830 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6831 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6832 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6833 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 6834 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6835 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6836 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 171:3a7713b1edbc 6837 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6838 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6839 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 171:3a7713b1edbc 6840 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6841 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6842 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 171:3a7713b1edbc 6843
AnnaBridge 171:3a7713b1edbc 6844 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6845 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 6846 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 6847 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 6848 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 6849
AnnaBridge 171:3a7713b1edbc 6850 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6851 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6852 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
AnnaBridge 171:3a7713b1edbc 6853
AnnaBridge 171:3a7713b1edbc 6854 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 6855 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6856 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6857 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6858 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6859 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6860 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 6861 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6862 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6863 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 6864 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6865 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6866 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 6867 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6868 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6869 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 171:3a7713b1edbc 6870 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6871 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6872 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 171:3a7713b1edbc 6873 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6874 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6875 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 6876 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6877 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6878 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 6879 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6880 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6881 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 171:3a7713b1edbc 6882 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6883 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6884 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 171:3a7713b1edbc 6885 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6886 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6887 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6888 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6889 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6890 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
AnnaBridge 171:3a7713b1edbc 6891
AnnaBridge 171:3a7713b1edbc 6892 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 6893 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6894 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6895 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 6896 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6897 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6898 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6899 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6900 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6901 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6902 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6903 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6904
AnnaBridge 171:3a7713b1edbc 6905 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6906 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6907 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
AnnaBridge 171:3a7713b1edbc 6908
AnnaBridge 171:3a7713b1edbc 6909 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6910 /* */
AnnaBridge 171:3a7713b1edbc 6911 /* Window WATCHDOG */
AnnaBridge 171:3a7713b1edbc 6912 /* */
AnnaBridge 171:3a7713b1edbc 6913 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6914 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 6915 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6916 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 6917 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 6918 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 6919 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 6920 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 171:3a7713b1edbc 6921 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 171:3a7713b1edbc 6922 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 171:3a7713b1edbc 6923 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 171:3a7713b1edbc 6924 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 171:3a7713b1edbc 6925 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 6926 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 171:3a7713b1edbc 6927 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 171:3a7713b1edbc 6928 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 171:3a7713b1edbc 6929 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 171:3a7713b1edbc 6930 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 171:3a7713b1edbc 6931 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 171:3a7713b1edbc 6932 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 171:3a7713b1edbc 6933
AnnaBridge 171:3a7713b1edbc 6934 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6935 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6936 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 171:3a7713b1edbc 6937
AnnaBridge 171:3a7713b1edbc 6938 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 6939 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6940 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 6941 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 6942 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 6943 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 6944 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 6945 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 6946 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 6947 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 6948 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 6949 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 6950 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 171:3a7713b1edbc 6951 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 171:3a7713b1edbc 6952 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 171:3a7713b1edbc 6953 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 171:3a7713b1edbc 6954 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 171:3a7713b1edbc 6955 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 171:3a7713b1edbc 6956 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 171:3a7713b1edbc 6957
AnnaBridge 171:3a7713b1edbc 6958 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6959 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 6960 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 6961 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 6962 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 6963 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 6964 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 171:3a7713b1edbc 6965 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 171:3a7713b1edbc 6966
AnnaBridge 171:3a7713b1edbc 6967 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6968 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6969 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 6970
AnnaBridge 171:3a7713b1edbc 6971 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 6972 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6973 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6974 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6975
AnnaBridge 171:3a7713b1edbc 6976
AnnaBridge 171:3a7713b1edbc 6977 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6978 /* */
AnnaBridge 171:3a7713b1edbc 6979 /* DBG */
AnnaBridge 171:3a7713b1edbc 6980 /* */
AnnaBridge 171:3a7713b1edbc 6981 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6982 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 171:3a7713b1edbc 6983 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6984 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6985 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 171:3a7713b1edbc 6986 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6987 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 6988 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 171:3a7713b1edbc 6989
AnnaBridge 171:3a7713b1edbc 6990 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 171:3a7713b1edbc 6991 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6992 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6993 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 171:3a7713b1edbc 6994 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6995 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6996 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6997 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6998 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6999 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 171:3a7713b1edbc 7000 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7001 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7002 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 171:3a7713b1edbc 7003
AnnaBridge 171:3a7713b1edbc 7004 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7005 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7006 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 171:3a7713b1edbc 7007 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7008 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7009
AnnaBridge 171:3a7713b1edbc 7010 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 171:3a7713b1edbc 7011 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7012 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7013 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7014 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7015 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7016 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7017 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7018 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7019 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7020 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7021 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7022 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7023 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7024 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7025 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7026 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7027 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7028 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 7029 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7030 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7031 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 7032 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7033 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7034 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 7035 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 171:3a7713b1edbc 7036 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7037 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7038 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7039 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7040 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7041
AnnaBridge 171:3a7713b1edbc 7042 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 171:3a7713b1edbc 7043 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7044 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7045 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7046 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7047 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7048 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7049 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7050 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7051 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7052 /**
AnnaBridge 171:3a7713b1edbc 7053 * @}
AnnaBridge 171:3a7713b1edbc 7054 */
AnnaBridge 171:3a7713b1edbc 7055
AnnaBridge 171:3a7713b1edbc 7056 /**
AnnaBridge 171:3a7713b1edbc 7057 * @}
AnnaBridge 171:3a7713b1edbc 7058 */
AnnaBridge 171:3a7713b1edbc 7059
AnnaBridge 171:3a7713b1edbc 7060 /** @addtogroup Exported_macros
AnnaBridge 171:3a7713b1edbc 7061 * @{
AnnaBridge 171:3a7713b1edbc 7062 */
AnnaBridge 171:3a7713b1edbc 7063
AnnaBridge 171:3a7713b1edbc 7064 /******************************* ADC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7065 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 171:3a7713b1edbc 7066
AnnaBridge 171:3a7713b1edbc 7067 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 171:3a7713b1edbc 7068 /******************************* CRC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7069 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 171:3a7713b1edbc 7070
AnnaBridge 171:3a7713b1edbc 7071 /******************************* DAC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7072 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 171:3a7713b1edbc 7073
AnnaBridge 171:3a7713b1edbc 7074
AnnaBridge 171:3a7713b1edbc 7075 /******************************** DMA Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7076 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 171:3a7713b1edbc 7077 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 171:3a7713b1edbc 7078 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 171:3a7713b1edbc 7079 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 171:3a7713b1edbc 7080 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 171:3a7713b1edbc 7081 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 171:3a7713b1edbc 7082 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 171:3a7713b1edbc 7083 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 171:3a7713b1edbc 7084 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 171:3a7713b1edbc 7085 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 171:3a7713b1edbc 7086 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 171:3a7713b1edbc 7087 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 171:3a7713b1edbc 7088 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 171:3a7713b1edbc 7089 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 171:3a7713b1edbc 7090 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 171:3a7713b1edbc 7091 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 171:3a7713b1edbc 7092
AnnaBridge 171:3a7713b1edbc 7093 /******************************* GPIO Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7094 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 7095 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 7096 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 7097 ((INSTANCE) == GPIOH))
AnnaBridge 171:3a7713b1edbc 7098
AnnaBridge 171:3a7713b1edbc 7099 /******************************** I2C Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7100 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 7101 ((INSTANCE) == I2C2))
AnnaBridge 171:3a7713b1edbc 7102
AnnaBridge 171:3a7713b1edbc 7103 /******************************* SMBUS Instances ******************************/
AnnaBridge 171:3a7713b1edbc 7104 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 171:3a7713b1edbc 7105
AnnaBridge 171:3a7713b1edbc 7106 /******************************** I2S Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7107 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 7108 ((INSTANCE) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 7109 ((INSTANCE) == SPI5))
AnnaBridge 171:3a7713b1edbc 7110
AnnaBridge 171:3a7713b1edbc 7111
AnnaBridge 171:3a7713b1edbc 7112 /******************************* LPTIM Instances ******************************/
AnnaBridge 171:3a7713b1edbc 7113 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
AnnaBridge 171:3a7713b1edbc 7114
AnnaBridge 171:3a7713b1edbc 7115 /******************************* RNG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7116 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 171:3a7713b1edbc 7117
AnnaBridge 171:3a7713b1edbc 7118
AnnaBridge 171:3a7713b1edbc 7119
AnnaBridge 171:3a7713b1edbc 7120 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 7121 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 171:3a7713b1edbc 7122
AnnaBridge 171:3a7713b1edbc 7123
AnnaBridge 171:3a7713b1edbc 7124 /******************************** SPI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7125 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 7126 ((INSTANCE) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 7127 ((INSTANCE) == SPI5))
AnnaBridge 171:3a7713b1edbc 7128
AnnaBridge 171:3a7713b1edbc 7129
AnnaBridge 171:3a7713b1edbc 7130 /*************************** SPI Extended Instances ***************************/
AnnaBridge 171:3a7713b1edbc 7131 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 7132 ((INSTANCE) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 7133 ((INSTANCE) == SPI5))
AnnaBridge 171:3a7713b1edbc 7134 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 171:3a7713b1edbc 7135 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7136 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7137 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 7138 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 7139 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 7140
AnnaBridge 171:3a7713b1edbc 7141 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 171:3a7713b1edbc 7142 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7143 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7144 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 7145 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 7146
AnnaBridge 171:3a7713b1edbc 7147 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 7148 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7149 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7150 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 7151
AnnaBridge 171:3a7713b1edbc 7152 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 7153 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7154 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7155
AnnaBridge 171:3a7713b1edbc 7156 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 7157 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7158 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7159
AnnaBridge 171:3a7713b1edbc 7160 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 171:3a7713b1edbc 7161 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 7162
AnnaBridge 171:3a7713b1edbc 7163 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 171:3a7713b1edbc 7164 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7165 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7166
AnnaBridge 171:3a7713b1edbc 7167 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 171:3a7713b1edbc 7168 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7169 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7170 ((INSTANCE) == TIM6))
AnnaBridge 171:3a7713b1edbc 7171
AnnaBridge 171:3a7713b1edbc 7172 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 171:3a7713b1edbc 7173 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7174 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7175
AnnaBridge 171:3a7713b1edbc 7176 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 171:3a7713b1edbc 7177 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7178 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7179
AnnaBridge 171:3a7713b1edbc 7180 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 171:3a7713b1edbc 7181 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7182 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7183
AnnaBridge 171:3a7713b1edbc 7184 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 171:3a7713b1edbc 7185 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7186 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7187 ((INSTANCE) == TIM6))
AnnaBridge 171:3a7713b1edbc 7188
AnnaBridge 171:3a7713b1edbc 7189 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 171:3a7713b1edbc 7190 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7191 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7192 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 7193
AnnaBridge 171:3a7713b1edbc 7194 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 171:3a7713b1edbc 7195 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5)
AnnaBridge 171:3a7713b1edbc 7196
AnnaBridge 171:3a7713b1edbc 7197 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 171:3a7713b1edbc 7198 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7199 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7200
AnnaBridge 171:3a7713b1edbc 7201 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 171:3a7713b1edbc 7202 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7203 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 7204
AnnaBridge 171:3a7713b1edbc 7205 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 171:3a7713b1edbc 7206 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 7207 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 7208 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 7209 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 7210 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 7211 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 7212 || \
AnnaBridge 171:3a7713b1edbc 7213 (((INSTANCE) == TIM5) && \
AnnaBridge 171:3a7713b1edbc 7214 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 7215 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 7216 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 7217 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 7218 || \
AnnaBridge 171:3a7713b1edbc 7219 (((INSTANCE) == TIM9) && \
AnnaBridge 171:3a7713b1edbc 7220 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 7221 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 7222 || \
AnnaBridge 171:3a7713b1edbc 7223 (((INSTANCE) == TIM11) && \
AnnaBridge 171:3a7713b1edbc 7224 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 7225
AnnaBridge 171:3a7713b1edbc 7226 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 171:3a7713b1edbc 7227 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 7228 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 7229 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 7230 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 7231 ((CHANNEL) == TIM_CHANNEL_3))))
AnnaBridge 171:3a7713b1edbc 7232
AnnaBridge 171:3a7713b1edbc 7233 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 171:3a7713b1edbc 7234 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7235 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7236
AnnaBridge 171:3a7713b1edbc 7237 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 171:3a7713b1edbc 7238 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7239 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7240 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 7241 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 7242
AnnaBridge 171:3a7713b1edbc 7243 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 171:3a7713b1edbc 7244
AnnaBridge 171:3a7713b1edbc 7245 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 7246
AnnaBridge 171:3a7713b1edbc 7247 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 171:3a7713b1edbc 7248 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7249 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7250
AnnaBridge 171:3a7713b1edbc 7251 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 7252 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7253 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7254 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 7255
AnnaBridge 171:3a7713b1edbc 7256 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 7257 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7258 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7259
AnnaBridge 171:3a7713b1edbc 7260 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 171:3a7713b1edbc 7261 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 7262
AnnaBridge 171:3a7713b1edbc 7263 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 171:3a7713b1edbc 7264 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7265 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 7266 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 7267 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 171:3a7713b1edbc 7268 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 7269 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 7270 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 171:3a7713b1edbc 7271 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 7272
AnnaBridge 171:3a7713b1edbc 7273 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 7274 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 7275 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 7276 ((INSTANCE) == USART6))
AnnaBridge 171:3a7713b1edbc 7277
AnnaBridge 171:3a7713b1edbc 7278 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 7279 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 7280 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 7281 ((INSTANCE) == USART6))
AnnaBridge 171:3a7713b1edbc 7282
AnnaBridge 171:3a7713b1edbc 7283 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7284 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 171:3a7713b1edbc 7285
AnnaBridge 171:3a7713b1edbc 7286 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 7287 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 7288 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 7289 ((INSTANCE) == USART6))
AnnaBridge 171:3a7713b1edbc 7290 /******************** UART Instances : LIN mode **********************/
AnnaBridge 171:3a7713b1edbc 7291 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 171:3a7713b1edbc 7292
AnnaBridge 171:3a7713b1edbc 7293 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 171:3a7713b1edbc 7294 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 7295 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 7296 ((INSTANCE) == USART6))
AnnaBridge 171:3a7713b1edbc 7297
AnnaBridge 171:3a7713b1edbc 7298 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 7299 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 7300 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 7301 ((INSTANCE) == USART6))
AnnaBridge 171:3a7713b1edbc 7302
AnnaBridge 171:3a7713b1edbc 7303 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7304 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 171:3a7713b1edbc 7305
AnnaBridge 171:3a7713b1edbc 7306 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 7307 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 171:3a7713b1edbc 7308
AnnaBridge 171:3a7713b1edbc 7309
AnnaBridge 171:3a7713b1edbc 7310 /***************************** FMPI2C Instances *******************************/
AnnaBridge 171:3a7713b1edbc 7311 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
AnnaBridge 171:3a7713b1edbc 7312
AnnaBridge 171:3a7713b1edbc 7313 /*
AnnaBridge 171:3a7713b1edbc 7314 * @brief Specific devices reset values definitions
AnnaBridge 171:3a7713b1edbc 7315 */
AnnaBridge 171:3a7713b1edbc 7316 #define RCC_PLLCFGR_RST_VALUE 0x7F003010U
AnnaBridge 171:3a7713b1edbc 7317 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
AnnaBridge 171:3a7713b1edbc 7318
AnnaBridge 171:3a7713b1edbc 7319 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
AnnaBridge 171:3a7713b1edbc 7320 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
AnnaBridge 171:3a7713b1edbc 7321 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 171:3a7713b1edbc 7322 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 171:3a7713b1edbc 7323 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 171:3a7713b1edbc 7324 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 171:3a7713b1edbc 7325 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 171:3a7713b1edbc 7326 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 171:3a7713b1edbc 7327
AnnaBridge 171:3a7713b1edbc 7328 #define RCC_PLLN_MIN_VALUE 50U
AnnaBridge 171:3a7713b1edbc 7329 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 171:3a7713b1edbc 7330
AnnaBridge 171:3a7713b1edbc 7331 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 171:3a7713b1edbc 7332 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 171:3a7713b1edbc 7333 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 171:3a7713b1edbc 7334
AnnaBridge 171:3a7713b1edbc 7335 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 171:3a7713b1edbc 7336 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 171:3a7713b1edbc 7337
AnnaBridge 171:3a7713b1edbc 7338 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 171:3a7713b1edbc 7339 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 171:3a7713b1edbc 7340
AnnaBridge 171:3a7713b1edbc 7341
AnnaBridge 171:3a7713b1edbc 7342 /**
AnnaBridge 171:3a7713b1edbc 7343 * @}
AnnaBridge 171:3a7713b1edbc 7344 */
AnnaBridge 171:3a7713b1edbc 7345
AnnaBridge 171:3a7713b1edbc 7346 /**
AnnaBridge 171:3a7713b1edbc 7347 * @}
AnnaBridge 171:3a7713b1edbc 7348 */
AnnaBridge 171:3a7713b1edbc 7349
AnnaBridge 171:3a7713b1edbc 7350 /**
AnnaBridge 171:3a7713b1edbc 7351 * @}
AnnaBridge 171:3a7713b1edbc 7352 */
AnnaBridge 171:3a7713b1edbc 7353
AnnaBridge 171:3a7713b1edbc 7354 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 7355 }
AnnaBridge 171:3a7713b1edbc 7356 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 7357
AnnaBridge 171:3a7713b1edbc 7358 #endif /* __STM32F410Rx_H */
AnnaBridge 171:3a7713b1edbc 7359
AnnaBridge 171:3a7713b1edbc 7360
AnnaBridge 171:3a7713b1edbc 7361
AnnaBridge 171:3a7713b1edbc 7362 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/