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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_ll_tim.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h@168:b9e159c1930a

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32f3xx_ll_tim.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief Header file of TIM LL module.
AnnaBridge	163:e59c8e839560	6	******************************************************************************
AnnaBridge	163:e59c8e839560	7	* @attention
AnnaBridge	163:e59c8e839560	8	*
AnnaBridge	163:e59c8e839560	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	10	*
AnnaBridge	163:e59c8e839560	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	12	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	14	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	17	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	19	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	20	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	21	*
AnnaBridge	163:e59c8e839560	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	32	*
AnnaBridge	163:e59c8e839560	33	******************************************************************************
AnnaBridge	163:e59c8e839560	34	*/
AnnaBridge	163:e59c8e839560	35
AnnaBridge	163:e59c8e839560	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	37	#ifndef __STM32F3xx_LL_TIM_H
AnnaBridge	163:e59c8e839560	38	#define __STM32F3xx_LL_TIM_H
AnnaBridge	163:e59c8e839560	39
AnnaBridge	163:e59c8e839560	40	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	41	extern "C" {
AnnaBridge	163:e59c8e839560	42	#endif
AnnaBridge	163:e59c8e839560	43
AnnaBridge	163:e59c8e839560	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	45	#include "stm32f3xx.h"
AnnaBridge	163:e59c8e839560	46
AnnaBridge	163:e59c8e839560	47	/** @addtogroup STM32F3xx_LL_Driver
AnnaBridge	163:e59c8e839560	48	* @{
AnnaBridge	163:e59c8e839560	49	*/
AnnaBridge	163:e59c8e839560	50
AnnaBridge	163:e59c8e839560	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM18) \|\| defined (TIM19) \|\| defined (TIM20)
AnnaBridge	163:e59c8e839560	52
AnnaBridge	163:e59c8e839560	53	/** @defgroup TIM_LL TIM
AnnaBridge	163:e59c8e839560	54	* @{
AnnaBridge	163:e59c8e839560	55	*/
AnnaBridge	163:e59c8e839560	56
AnnaBridge	163:e59c8e839560	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	163:e59c8e839560	60	* @{
AnnaBridge	163:e59c8e839560	61	*/
AnnaBridge	163:e59c8e839560	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	163:e59c8e839560	63	{
AnnaBridge	163:e59c8e839560	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	163:e59c8e839560	65	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	163:e59c8e839560	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	163:e59c8e839560	67	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	163:e59c8e839560	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	163:e59c8e839560	69	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	163:e59c8e839560	70	0x04U, /* 6: TIMx_CH4 */
AnnaBridge	163:e59c8e839560	71	0x3CU, /* 7: TIMx_CH5 */
AnnaBridge	163:e59c8e839560	72	0x3CU /* 8: TIMx_CH6 */
AnnaBridge	163:e59c8e839560	73	};
AnnaBridge	163:e59c8e839560	74
AnnaBridge	163:e59c8e839560	75	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	163:e59c8e839560	76	{
AnnaBridge	163:e59c8e839560	77	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	163:e59c8e839560	78	0U, /* 1: - NA */
AnnaBridge	163:e59c8e839560	79	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	163:e59c8e839560	80	0U, /* 3: - NA */
AnnaBridge	163:e59c8e839560	81	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	163:e59c8e839560	82	0U, /* 5: - NA */
AnnaBridge	163:e59c8e839560	83	8U, /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	163:e59c8e839560	84	0U, /* 7: OC5M, OC5FE, OC5PE */
AnnaBridge	163:e59c8e839560	85	8U /* 8: OC6M, OC6FE, OC6PE */
AnnaBridge	163:e59c8e839560	86	};
AnnaBridge	163:e59c8e839560	87
AnnaBridge	163:e59c8e839560	88	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	163:e59c8e839560	89	{
AnnaBridge	163:e59c8e839560	90	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	163:e59c8e839560	91	0U, /* 1: - NA */
AnnaBridge	163:e59c8e839560	92	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	163:e59c8e839560	93	0U, /* 3: - NA */
AnnaBridge	163:e59c8e839560	94	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	163:e59c8e839560	95	0U, /* 5: - NA */
AnnaBridge	163:e59c8e839560	96	8U, /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	163:e59c8e839560	97	0U, /* 7: - NA */
AnnaBridge	163:e59c8e839560	98	0U /* 8: - NA */
AnnaBridge	163:e59c8e839560	99	};
AnnaBridge	163:e59c8e839560	100
AnnaBridge	163:e59c8e839560	101	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	163:e59c8e839560	102	{
AnnaBridge	163:e59c8e839560	103	0U, /* 0: CC1P */
AnnaBridge	163:e59c8e839560	104	2U, /* 1: CC1NP */
AnnaBridge	163:e59c8e839560	105	4U, /* 2: CC2P */
AnnaBridge	163:e59c8e839560	106	6U, /* 3: CC2NP */
AnnaBridge	163:e59c8e839560	107	8U, /* 4: CC3P */
AnnaBridge	163:e59c8e839560	108	10U, /* 5: CC3NP */
AnnaBridge	163:e59c8e839560	109	12U, /* 6: CC4P */
AnnaBridge	163:e59c8e839560	110	16U, /* 7: CC5P */
AnnaBridge	163:e59c8e839560	111	20U /* 8: CC6P */
AnnaBridge	163:e59c8e839560	112	};
AnnaBridge	163:e59c8e839560	113
AnnaBridge	163:e59c8e839560	114	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	163:e59c8e839560	115	{
AnnaBridge	163:e59c8e839560	116	0U, /* 0: OIS1 */
AnnaBridge	163:e59c8e839560	117	1U, /* 1: OIS1N */
AnnaBridge	163:e59c8e839560	118	2U, /* 2: OIS2 */
AnnaBridge	163:e59c8e839560	119	3U, /* 3: OIS2N */
AnnaBridge	163:e59c8e839560	120	4U, /* 4: OIS3 */
AnnaBridge	163:e59c8e839560	121	5U, /* 5: OIS3N */
AnnaBridge	163:e59c8e839560	122	6U, /* 6: OIS4 */
AnnaBridge	163:e59c8e839560	123	8U, /* 7: OIS5 */
AnnaBridge	163:e59c8e839560	124	10U /* 8: OIS6 */
AnnaBridge	163:e59c8e839560	125	};
AnnaBridge	163:e59c8e839560	126	/**
AnnaBridge	163:e59c8e839560	127	* @}
AnnaBridge	163:e59c8e839560	128	*/
AnnaBridge	163:e59c8e839560	129
AnnaBridge	163:e59c8e839560	130
AnnaBridge	163:e59c8e839560	131	/* Private constants ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	132	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	163:e59c8e839560	133	* @{
AnnaBridge	163:e59c8e839560	134	*/
AnnaBridge	163:e59c8e839560	135
AnnaBridge	163:e59c8e839560	136
AnnaBridge	168:b9e159c1930a	137	#define TIMx_OR_RMP_SHIFT 16U
AnnaBridge	168:b9e159c1930a	138	#define TIMx_OR_RMP_MASK 0x0000FFFFU
AnnaBridge	163:e59c8e839560	139	#if defined(TIM1)
AnnaBridge	168:b9e159c1930a	140	#define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	163:e59c8e839560	141	#endif /* TIM1 */
AnnaBridge	163:e59c8e839560	142	#if defined (TIM8)
AnnaBridge	168:b9e159c1930a	143	#define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	163:e59c8e839560	144	#endif /* TIM8 */
AnnaBridge	163:e59c8e839560	145	#if defined(TIM14)
AnnaBridge	168:b9e159c1930a	146	#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	163:e59c8e839560	147	#endif /* TIM14 */
AnnaBridge	163:e59c8e839560	148	#if defined(TIM16)
AnnaBridge	168:b9e159c1930a	149	#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	163:e59c8e839560	150	#endif /* TIM16 */
AnnaBridge	163:e59c8e839560	151	#if defined(TIM20)
AnnaBridge	168:b9e159c1930a	152	#define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	163:e59c8e839560	153	#endif /* TIM20 */
AnnaBridge	163:e59c8e839560	154
AnnaBridge	163:e59c8e839560	155	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	163:e59c8e839560	156	#define DT_DELAY_1 ((uint8_t)0x7FU)
AnnaBridge	163:e59c8e839560	157	#define DT_DELAY_2 ((uint8_t)0x3FU)
AnnaBridge	163:e59c8e839560	158	#define DT_DELAY_3 ((uint8_t)0x1FU)
AnnaBridge	163:e59c8e839560	159	#define DT_DELAY_4 ((uint8_t)0x1FU)
AnnaBridge	163:e59c8e839560	160
AnnaBridge	163:e59c8e839560	161	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	163:e59c8e839560	162	#define DT_RANGE_1 ((uint8_t)0x00U)
AnnaBridge	163:e59c8e839560	163	#define DT_RANGE_2 ((uint8_t)0x80U)
AnnaBridge	163:e59c8e839560	164	#define DT_RANGE_3 ((uint8_t)0xC0U)
AnnaBridge	163:e59c8e839560	165	#define DT_RANGE_4 ((uint8_t)0xE0U)
AnnaBridge	163:e59c8e839560	166
AnnaBridge	163:e59c8e839560	167
AnnaBridge	163:e59c8e839560	168	/**
AnnaBridge	163:e59c8e839560	169	* @}
AnnaBridge	163:e59c8e839560	170	*/
AnnaBridge	163:e59c8e839560	171
AnnaBridge	163:e59c8e839560	172	/* Private macros ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	173	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	163:e59c8e839560	174	* @{
AnnaBridge	163:e59c8e839560	175	*/
AnnaBridge	163:e59c8e839560	176	/** @brief Convert channel id into channel index.
AnnaBridge	163:e59c8e839560	177	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	178	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	179	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	180	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	181	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	182	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	183	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	184	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	185	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	186	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	187	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	188	* @retval none
AnnaBridge	163:e59c8e839560	189	*/
AnnaBridge	163:e59c8e839560	190	#if defined(TIM_CCR5_CCR5)
AnnaBridge	163:e59c8e839560	191	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	163:e59c8e839560	192	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	163:e59c8e839560	193	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	163:e59c8e839560	194	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	163:e59c8e839560	195	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	163:e59c8e839560	196	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	163:e59c8e839560	197	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
AnnaBridge	163:e59c8e839560	198	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
AnnaBridge	163:e59c8e839560	199	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
AnnaBridge	163:e59c8e839560	200	#else
AnnaBridge	163:e59c8e839560	201	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	163:e59c8e839560	202	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	163:e59c8e839560	203	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	163:e59c8e839560	204	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	163:e59c8e839560	205	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	163:e59c8e839560	206	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	163:e59c8e839560	207	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
AnnaBridge	163:e59c8e839560	208	#endif
AnnaBridge	163:e59c8e839560	209
AnnaBridge	163:e59c8e839560	210	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	163:e59c8e839560	211	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	163:e59c8e839560	212	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	213	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	163:e59c8e839560	214	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	163:e59c8e839560	215	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	163:e59c8e839560	216	* @retval none
AnnaBridge	163:e59c8e839560	217	*/
AnnaBridge	163:e59c8e839560	218	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	163:e59c8e839560	219	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	163:e59c8e839560	220	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	163:e59c8e839560	221	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	163:e59c8e839560	222	/**
AnnaBridge	163:e59c8e839560	223	* @}
AnnaBridge	163:e59c8e839560	224	*/
AnnaBridge	163:e59c8e839560	225
AnnaBridge	163:e59c8e839560	226
AnnaBridge	163:e59c8e839560	227	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	228	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	229	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	163:e59c8e839560	230	* @{
AnnaBridge	163:e59c8e839560	231	*/
AnnaBridge	163:e59c8e839560	232
AnnaBridge	163:e59c8e839560	233	/**
AnnaBridge	163:e59c8e839560	234	* @brief TIM Time Base configuration structure definition.
AnnaBridge	163:e59c8e839560	235	*/
AnnaBridge	163:e59c8e839560	236	typedef struct
AnnaBridge	163:e59c8e839560	237	{
AnnaBridge	163:e59c8e839560	238	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	163:e59c8e839560	239	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	163:e59c8e839560	240
AnnaBridge	163:e59c8e839560	241	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	163:e59c8e839560	242
AnnaBridge	163:e59c8e839560	243	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	163:e59c8e839560	244	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	163:e59c8e839560	245
AnnaBridge	163:e59c8e839560	246	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	163:e59c8e839560	247
AnnaBridge	163:e59c8e839560	248	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	163:e59c8e839560	249	Auto-Reload Register at the next update event.
AnnaBridge	163:e59c8e839560	250	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	163:e59c8e839560	251	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	252
AnnaBridge	163:e59c8e839560	253	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	163:e59c8e839560	254
AnnaBridge	163:e59c8e839560	255	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	163:e59c8e839560	256	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	163:e59c8e839560	257
AnnaBridge	163:e59c8e839560	258	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	163:e59c8e839560	259
AnnaBridge	163:e59c8e839560	260	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	163:e59c8e839560	261	reaches zero, an update event is generated and counting restarts
AnnaBridge	163:e59c8e839560	262	from the RCR value (N).
AnnaBridge	163:e59c8e839560	263	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	163:e59c8e839560	264	- the number of PWM periods in edge-aligned mode
AnnaBridge	163:e59c8e839560	265	- the number of half PWM period in center-aligned mode
AnnaBridge	163:e59c8e839560	266	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	163:e59c8e839560	267
AnnaBridge	163:e59c8e839560	268	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	163:e59c8e839560	269	} LL_TIM_InitTypeDef;
AnnaBridge	163:e59c8e839560	270
AnnaBridge	163:e59c8e839560	271	/**
AnnaBridge	163:e59c8e839560	272	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	163:e59c8e839560	273	*/
AnnaBridge	163:e59c8e839560	274	typedef struct
AnnaBridge	163:e59c8e839560	275	{
AnnaBridge	163:e59c8e839560	276	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	163:e59c8e839560	277	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	163:e59c8e839560	278
AnnaBridge	163:e59c8e839560	279	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	163:e59c8e839560	280
AnnaBridge	163:e59c8e839560	281	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	163:e59c8e839560	282	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	163:e59c8e839560	283
AnnaBridge	163:e59c8e839560	284	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	163:e59c8e839560	285
AnnaBridge	163:e59c8e839560	286	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	163:e59c8e839560	287	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	163:e59c8e839560	288
AnnaBridge	163:e59c8e839560	289	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	163:e59c8e839560	290
AnnaBridge	163:e59c8e839560	291	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	163:e59c8e839560	292	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	163:e59c8e839560	293
AnnaBridge	163:e59c8e839560	294	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	163:e59c8e839560	295
AnnaBridge	163:e59c8e839560	296	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	163:e59c8e839560	297	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	163:e59c8e839560	298
AnnaBridge	163:e59c8e839560	299	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	300
AnnaBridge	163:e59c8e839560	301	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	163:e59c8e839560	302	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	163:e59c8e839560	303
AnnaBridge	163:e59c8e839560	304	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	305
AnnaBridge	163:e59c8e839560	306
AnnaBridge	163:e59c8e839560	307	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	163:e59c8e839560	308	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	163:e59c8e839560	309
AnnaBridge	163:e59c8e839560	310	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	163:e59c8e839560	311
AnnaBridge	163:e59c8e839560	312	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	163:e59c8e839560	313	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	163:e59c8e839560	314
AnnaBridge	163:e59c8e839560	315	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	163:e59c8e839560	316	} LL_TIM_OC_InitTypeDef;
AnnaBridge	163:e59c8e839560	317
AnnaBridge	163:e59c8e839560	318	/**
AnnaBridge	163:e59c8e839560	319	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	163:e59c8e839560	320	*/
AnnaBridge	163:e59c8e839560	321
AnnaBridge	163:e59c8e839560	322	typedef struct
AnnaBridge	163:e59c8e839560	323	{
AnnaBridge	163:e59c8e839560	324
AnnaBridge	163:e59c8e839560	325	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	163:e59c8e839560	326	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	163:e59c8e839560	327
AnnaBridge	163:e59c8e839560	328	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	329
AnnaBridge	163:e59c8e839560	330	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	163:e59c8e839560	331	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	163:e59c8e839560	332
AnnaBridge	163:e59c8e839560	333	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	163:e59c8e839560	334
AnnaBridge	163:e59c8e839560	335	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	163:e59c8e839560	336	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	163:e59c8e839560	337
AnnaBridge	163:e59c8e839560	338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	163:e59c8e839560	339
AnnaBridge	163:e59c8e839560	340	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	163:e59c8e839560	341	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	163:e59c8e839560	342
AnnaBridge	163:e59c8e839560	343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	163:e59c8e839560	344	} LL_TIM_IC_InitTypeDef;
AnnaBridge	163:e59c8e839560	345
AnnaBridge	163:e59c8e839560	346
AnnaBridge	163:e59c8e839560	347	/**
AnnaBridge	163:e59c8e839560	348	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	163:e59c8e839560	349	*/
AnnaBridge	163:e59c8e839560	350	typedef struct
AnnaBridge	163:e59c8e839560	351	{
AnnaBridge	163:e59c8e839560	352	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	163:e59c8e839560	353	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	163:e59c8e839560	354
AnnaBridge	163:e59c8e839560	355	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	163:e59c8e839560	356
AnnaBridge	163:e59c8e839560	357	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	163:e59c8e839560	358	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	163:e59c8e839560	359
AnnaBridge	163:e59c8e839560	360	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	361
AnnaBridge	163:e59c8e839560	362	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	163:e59c8e839560	363	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	163:e59c8e839560	364
AnnaBridge	163:e59c8e839560	365	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	163:e59c8e839560	366
AnnaBridge	163:e59c8e839560	367	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	163:e59c8e839560	368	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	163:e59c8e839560	369
AnnaBridge	163:e59c8e839560	370	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	163:e59c8e839560	371
AnnaBridge	163:e59c8e839560	372	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	163:e59c8e839560	373	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	163:e59c8e839560	374
AnnaBridge	163:e59c8e839560	375	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	163:e59c8e839560	376
AnnaBridge	163:e59c8e839560	377	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	163:e59c8e839560	378	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	163:e59c8e839560	379
AnnaBridge	163:e59c8e839560	380	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	381
AnnaBridge	163:e59c8e839560	382	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	163:e59c8e839560	383	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	163:e59c8e839560	384
AnnaBridge	163:e59c8e839560	385	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	163:e59c8e839560	386
AnnaBridge	163:e59c8e839560	387	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	163:e59c8e839560	388	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	163:e59c8e839560	389
AnnaBridge	163:e59c8e839560	390	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	163:e59c8e839560	391
AnnaBridge	163:e59c8e839560	392	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	163:e59c8e839560	393	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	163:e59c8e839560	394
AnnaBridge	163:e59c8e839560	395	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	163:e59c8e839560	396
AnnaBridge	163:e59c8e839560	397	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	163:e59c8e839560	398
AnnaBridge	163:e59c8e839560	399	/**
AnnaBridge	163:e59c8e839560	400	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	163:e59c8e839560	401	*/
AnnaBridge	163:e59c8e839560	402	typedef struct
AnnaBridge	163:e59c8e839560	403	{
AnnaBridge	163:e59c8e839560	404
AnnaBridge	163:e59c8e839560	405	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	163:e59c8e839560	406	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	163:e59c8e839560	407
AnnaBridge	163:e59c8e839560	408	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	163:e59c8e839560	409
AnnaBridge	163:e59c8e839560	410	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	163:e59c8e839560	411	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	163:e59c8e839560	412	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	163:e59c8e839560	413	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	163:e59c8e839560	414
AnnaBridge	163:e59c8e839560	415	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	163:e59c8e839560	416
AnnaBridge	163:e59c8e839560	417	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	163:e59c8e839560	418	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	163:e59c8e839560	419
AnnaBridge	163:e59c8e839560	420	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	163:e59c8e839560	421
AnnaBridge	163:e59c8e839560	422	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	163:e59c8e839560	423	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	163:e59c8e839560	424	a change occurs on the Hall inputs.
AnnaBridge	163:e59c8e839560	425	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	163:e59c8e839560	426
AnnaBridge	163:e59c8e839560	427	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	163:e59c8e839560	428	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	163:e59c8e839560	429
AnnaBridge	168:b9e159c1930a	430	/**
AnnaBridge	168:b9e159c1930a	431	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	163:e59c8e839560	432	*/
AnnaBridge	163:e59c8e839560	433	typedef struct
AnnaBridge	163:e59c8e839560	434	{
AnnaBridge	163:e59c8e839560	435	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	163:e59c8e839560	436	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	163:e59c8e839560	437
AnnaBridge	163:e59c8e839560	438	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	168:b9e159c1930a	439
AnnaBridge	163:e59c8e839560	440	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	163:e59c8e839560	441
AnnaBridge	163:e59c8e839560	442	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	163:e59c8e839560	443	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	163:e59c8e839560	444
AnnaBridge	163:e59c8e839560	445	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	168:b9e159c1930a	446
AnnaBridge	163:e59c8e839560	447	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	163:e59c8e839560	448
AnnaBridge	163:e59c8e839560	449	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	163:e59c8e839560	450	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	168:b9e159c1930a	451
AnnaBridge	163:e59c8e839560	452	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	168:b9e159c1930a	453	has been written, their content is frozen until the next reset.*/
AnnaBridge	163:e59c8e839560	454
AnnaBridge	163:e59c8e839560	455	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	163:e59c8e839560	456	switching-on of the outputs.
AnnaBridge	163:e59c8e839560	457	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	163:e59c8e839560	458
AnnaBridge	163:e59c8e839560	459	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	168:b9e159c1930a	460
AnnaBridge	163:e59c8e839560	461	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	163:e59c8e839560	462
AnnaBridge	168:b9e159c1930a	463	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	163:e59c8e839560	464	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	163:e59c8e839560	465
AnnaBridge	163:e59c8e839560	466	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	163:e59c8e839560	467
AnnaBridge	163:e59c8e839560	468	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	469
AnnaBridge	163:e59c8e839560	470	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	163:e59c8e839560	471	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	163:e59c8e839560	472
AnnaBridge	163:e59c8e839560	473	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	168:b9e159c1930a	474
AnnaBridge	163:e59c8e839560	475	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	476
AnnaBridge	163:e59c8e839560	477	#if defined(TIM_BDTR_BKF)
AnnaBridge	163:e59c8e839560	478	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
AnnaBridge	163:e59c8e839560	479	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
AnnaBridge	163:e59c8e839560	480
AnnaBridge	163:e59c8e839560	481	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	168:b9e159c1930a	482
AnnaBridge	163:e59c8e839560	483	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	484
AnnaBridge	163:e59c8e839560	485	#endif /* TIM_BDTR_BKF */
AnnaBridge	163:e59c8e839560	486	#if defined(TIM_BDTR_BK2E)
AnnaBridge	168:b9e159c1930a	487	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
AnnaBridge	163:e59c8e839560	488	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
AnnaBridge	163:e59c8e839560	489
AnnaBridge	163:e59c8e839560	490	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
AnnaBridge	163:e59c8e839560	491
AnnaBridge	163:e59c8e839560	492	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	493
AnnaBridge	163:e59c8e839560	494	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
AnnaBridge	163:e59c8e839560	495	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
AnnaBridge	163:e59c8e839560	496
AnnaBridge	163:e59c8e839560	497	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	168:b9e159c1930a	498
AnnaBridge	163:e59c8e839560	499	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	500
AnnaBridge	163:e59c8e839560	501	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
AnnaBridge	163:e59c8e839560	502	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
AnnaBridge	163:e59c8e839560	503
AnnaBridge	163:e59c8e839560	504	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	168:b9e159c1930a	505
AnnaBridge	163:e59c8e839560	506	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	507
AnnaBridge	163:e59c8e839560	508	#endif /* TIM_BDTR_BK2E */
AnnaBridge	168:b9e159c1930a	509	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	163:e59c8e839560	510	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	163:e59c8e839560	511
AnnaBridge	163:e59c8e839560	512	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	168:b9e159c1930a	513
AnnaBridge	163:e59c8e839560	514	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	163:e59c8e839560	515	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	163:e59c8e839560	516
AnnaBridge	163:e59c8e839560	517	/**
AnnaBridge	163:e59c8e839560	518	* @}
AnnaBridge	163:e59c8e839560	519	*/
AnnaBridge	163:e59c8e839560	520	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	521
AnnaBridge	163:e59c8e839560	522	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	523	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	163:e59c8e839560	524	* @{
AnnaBridge	163:e59c8e839560	525	*/
AnnaBridge	163:e59c8e839560	526
AnnaBridge	163:e59c8e839560	527	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	163:e59c8e839560	528	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	163:e59c8e839560	529	* @{
AnnaBridge	163:e59c8e839560	530	*/
AnnaBridge	163:e59c8e839560	531	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	163:e59c8e839560	532	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	163:e59c8e839560	533	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	163:e59c8e839560	534	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	163:e59c8e839560	535	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	163:e59c8e839560	536	#if defined(TIM_CCMR1_OC1M_3)
AnnaBridge	163:e59c8e839560	537	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
AnnaBridge	163:e59c8e839560	538	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
AnnaBridge	163:e59c8e839560	539	#endif /* TIM_CCMR1_OC1M_3 */
AnnaBridge	163:e59c8e839560	540	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	163:e59c8e839560	541	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	163:e59c8e839560	542	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	163:e59c8e839560	543	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
AnnaBridge	163:e59c8e839560	544	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	163:e59c8e839560	545	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	163:e59c8e839560	546	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	163:e59c8e839560	547	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	163:e59c8e839560	548	/**
AnnaBridge	163:e59c8e839560	549	* @}
AnnaBridge	163:e59c8e839560	550	*/
AnnaBridge	163:e59c8e839560	551
AnnaBridge	163:e59c8e839560	552	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	553	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	163:e59c8e839560	554	* @{
AnnaBridge	163:e59c8e839560	555	*/
AnnaBridge	168:b9e159c1930a	556	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	163:e59c8e839560	557	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	163:e59c8e839560	558	/**
AnnaBridge	163:e59c8e839560	559	* @}
AnnaBridge	163:e59c8e839560	560	*/
AnnaBridge	163:e59c8e839560	561	#if defined(TIM_BDTR_BK2E)
AnnaBridge	163:e59c8e839560	562
AnnaBridge	163:e59c8e839560	563	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
AnnaBridge	163:e59c8e839560	564	* @{
AnnaBridge	163:e59c8e839560	565	*/
AnnaBridge	168:b9e159c1930a	566	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
AnnaBridge	163:e59c8e839560	567	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
AnnaBridge	163:e59c8e839560	568	/**
AnnaBridge	163:e59c8e839560	569	* @}
AnnaBridge	163:e59c8e839560	570	*/
AnnaBridge	163:e59c8e839560	571	#endif /* TIM_BDTR_BK2E */
AnnaBridge	163:e59c8e839560	572
AnnaBridge	163:e59c8e839560	573	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	163:e59c8e839560	574	* @{
AnnaBridge	163:e59c8e839560	575	*/
AnnaBridge	168:b9e159c1930a	576	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	163:e59c8e839560	577	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	163:e59c8e839560	578	/**
AnnaBridge	163:e59c8e839560	579	* @}
AnnaBridge	168:b9e159c1930a	580	*/
AnnaBridge	163:e59c8e839560	581	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	582
AnnaBridge	163:e59c8e839560	583	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	163:e59c8e839560	584	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	163:e59c8e839560	585	* @{
AnnaBridge	163:e59c8e839560	586	*/
AnnaBridge	163:e59c8e839560	587	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	163:e59c8e839560	588	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	163:e59c8e839560	589	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	163:e59c8e839560	590	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	163:e59c8e839560	591	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	163:e59c8e839560	592	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	163:e59c8e839560	593	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	163:e59c8e839560	594	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	163:e59c8e839560	595	/**
AnnaBridge	163:e59c8e839560	596	* @}
AnnaBridge	163:e59c8e839560	597	*/
AnnaBridge	163:e59c8e839560	598
AnnaBridge	163:e59c8e839560	599	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	163:e59c8e839560	600	* @{
AnnaBridge	163:e59c8e839560	601	*/
AnnaBridge	163:e59c8e839560	602	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	163:e59c8e839560	603	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	163:e59c8e839560	604	/**
AnnaBridge	163:e59c8e839560	605	* @}
AnnaBridge	163:e59c8e839560	606	*/
AnnaBridge	163:e59c8e839560	607
AnnaBridge	163:e59c8e839560	608	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	163:e59c8e839560	609	* @{
AnnaBridge	163:e59c8e839560	610	*/
AnnaBridge	163:e59c8e839560	611	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	163:e59c8e839560	612	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	163:e59c8e839560	613	/**
AnnaBridge	163:e59c8e839560	614	* @}
AnnaBridge	163:e59c8e839560	615	*/
AnnaBridge	163:e59c8e839560	616
AnnaBridge	163:e59c8e839560	617	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	163:e59c8e839560	618	* @{
AnnaBridge	163:e59c8e839560	619	*/
AnnaBridge	163:e59c8e839560	620	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	163:e59c8e839560	621	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	163:e59c8e839560	622	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	163:e59c8e839560	623	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	163:e59c8e839560	624	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	163:e59c8e839560	625	/**
AnnaBridge	163:e59c8e839560	626	* @}
AnnaBridge	163:e59c8e839560	627	*/
AnnaBridge	163:e59c8e839560	628
AnnaBridge	163:e59c8e839560	629	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	163:e59c8e839560	630	* @{
AnnaBridge	163:e59c8e839560	631	*/
AnnaBridge	163:e59c8e839560	632	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	163:e59c8e839560	633	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	163:e59c8e839560	634	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	163:e59c8e839560	635	/**
AnnaBridge	163:e59c8e839560	636	* @}
AnnaBridge	163:e59c8e839560	637	*/
AnnaBridge	163:e59c8e839560	638
AnnaBridge	163:e59c8e839560	639	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	163:e59c8e839560	640	* @{
AnnaBridge	163:e59c8e839560	641	*/
AnnaBridge	163:e59c8e839560	642	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	163:e59c8e839560	643	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	163:e59c8e839560	644	/**
AnnaBridge	163:e59c8e839560	645	* @}
AnnaBridge	163:e59c8e839560	646	*/
AnnaBridge	163:e59c8e839560	647
AnnaBridge	163:e59c8e839560	648	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	163:e59c8e839560	649	* @{
AnnaBridge	163:e59c8e839560	650	*/
AnnaBridge	163:e59c8e839560	651	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	163:e59c8e839560	652	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	163:e59c8e839560	653	/**
AnnaBridge	163:e59c8e839560	654	* @}
AnnaBridge	163:e59c8e839560	655	*/
AnnaBridge	163:e59c8e839560	656
AnnaBridge	163:e59c8e839560	657	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	163:e59c8e839560	658	* @{
AnnaBridge	163:e59c8e839560	659	*/
AnnaBridge	163:e59c8e839560	660	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	163:e59c8e839560	661	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	163:e59c8e839560	662	/**
AnnaBridge	163:e59c8e839560	663	* @}
AnnaBridge	163:e59c8e839560	664	*/
AnnaBridge	163:e59c8e839560	665
AnnaBridge	163:e59c8e839560	666	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	163:e59c8e839560	667	* @{
AnnaBridge	163:e59c8e839560	668	*/
AnnaBridge	163:e59c8e839560	669	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	163:e59c8e839560	670	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	163:e59c8e839560	671	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	163:e59c8e839560	672	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	163:e59c8e839560	673	/**
AnnaBridge	163:e59c8e839560	674	* @}
AnnaBridge	163:e59c8e839560	675	*/
AnnaBridge	163:e59c8e839560	676
AnnaBridge	163:e59c8e839560	677	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	163:e59c8e839560	678	* @{
AnnaBridge	163:e59c8e839560	679	*/
AnnaBridge	163:e59c8e839560	680	#if defined(TIM_CCMR1_OC1M_3)
AnnaBridge	163:e59c8e839560	681	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	163:e59c8e839560	682	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	163:e59c8e839560	683	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	163:e59c8e839560	684	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	163:e59c8e839560	685	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	163:e59c8e839560	686	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	163:e59c8e839560	687	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	163:e59c8e839560	688	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
AnnaBridge	163:e59c8e839560	689	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
AnnaBridge	163:e59c8e839560	690	#else
AnnaBridge	163:e59c8e839560	691	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	163:e59c8e839560	692	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	163:e59c8e839560	693	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	163:e59c8e839560	694	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	163:e59c8e839560	695	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	163:e59c8e839560	696	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	163:e59c8e839560	697	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	163:e59c8e839560	698	#endif
AnnaBridge	163:e59c8e839560	699	/**
AnnaBridge	163:e59c8e839560	700	* @}
AnnaBridge	163:e59c8e839560	701	*/
AnnaBridge	163:e59c8e839560	702
AnnaBridge	163:e59c8e839560	703	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	704	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	163:e59c8e839560	705	* @{
AnnaBridge	163:e59c8e839560	706	*/
AnnaBridge	163:e59c8e839560	707	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	163:e59c8e839560	708	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	163:e59c8e839560	709	/**
AnnaBridge	163:e59c8e839560	710	* @}
AnnaBridge	163:e59c8e839560	711	*/
AnnaBridge	163:e59c8e839560	712	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	713
AnnaBridge	163:e59c8e839560	714	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	163:e59c8e839560	715	* @{
AnnaBridge	163:e59c8e839560	716	*/
AnnaBridge	163:e59c8e839560	717	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	163:e59c8e839560	718	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	163:e59c8e839560	719	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	163:e59c8e839560	720	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	168:b9e159c1930a	721	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	163:e59c8e839560	722	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	163:e59c8e839560	723	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	163:e59c8e839560	724	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	163:e59c8e839560	725	#if defined(TIM_CCMR1_OC1M_3)
AnnaBridge	163:e59c8e839560	726	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
AnnaBridge	163:e59c8e839560	727	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
AnnaBridge	163:e59c8e839560	728	#endif
AnnaBridge	163:e59c8e839560	729	#if defined(TIM_CCMR1_OC1M_3)
AnnaBridge	163:e59c8e839560	730	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
AnnaBridge	163:e59c8e839560	731	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
AnnaBridge	163:e59c8e839560	732	#endif
AnnaBridge	163:e59c8e839560	733	#if defined(TIM_CCMR1_OC1M_3)
AnnaBridge	163:e59c8e839560	734	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
AnnaBridge	163:e59c8e839560	735	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
AnnaBridge	163:e59c8e839560	736	#endif
AnnaBridge	163:e59c8e839560	737	/**
AnnaBridge	163:e59c8e839560	738	* @}
AnnaBridge	163:e59c8e839560	739	*/
AnnaBridge	163:e59c8e839560	740
AnnaBridge	163:e59c8e839560	741	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	163:e59c8e839560	742	* @{
AnnaBridge	163:e59c8e839560	743	*/
AnnaBridge	163:e59c8e839560	744	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	163:e59c8e839560	745	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	163:e59c8e839560	746	/**
AnnaBridge	163:e59c8e839560	747	* @}
AnnaBridge	163:e59c8e839560	748	*/
AnnaBridge	163:e59c8e839560	749
AnnaBridge	163:e59c8e839560	750	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	163:e59c8e839560	751	* @{
AnnaBridge	163:e59c8e839560	752	*/
AnnaBridge	163:e59c8e839560	753	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	163:e59c8e839560	754	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	163:e59c8e839560	755	/**
AnnaBridge	163:e59c8e839560	756	* @}
AnnaBridge	163:e59c8e839560	757	*/
AnnaBridge	163:e59c8e839560	758
AnnaBridge	163:e59c8e839560	759	#if defined(TIM_CCR5_CCR5)
AnnaBridge	163:e59c8e839560	760	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
AnnaBridge	163:e59c8e839560	761	* @{
AnnaBridge	163:e59c8e839560	762	*/
AnnaBridge	163:e59c8e839560	763	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
AnnaBridge	163:e59c8e839560	764	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
AnnaBridge	163:e59c8e839560	765	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
AnnaBridge	163:e59c8e839560	766	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
AnnaBridge	163:e59c8e839560	767	/**
AnnaBridge	163:e59c8e839560	768	* @}
AnnaBridge	163:e59c8e839560	769	*/
AnnaBridge	163:e59c8e839560	770	#endif /* TIM_CCR5_CCR5 */
AnnaBridge	163:e59c8e839560	771
AnnaBridge	163:e59c8e839560	772	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	163:e59c8e839560	773	* @{
AnnaBridge	163:e59c8e839560	774	*/
AnnaBridge	168:b9e159c1930a	775	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	168:b9e159c1930a	776	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	168:b9e159c1930a	777	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	163:e59c8e839560	778	/**
AnnaBridge	163:e59c8e839560	779	* @}
AnnaBridge	163:e59c8e839560	780	*/
AnnaBridge	163:e59c8e839560	781
AnnaBridge	163:e59c8e839560	782	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	163:e59c8e839560	783	* @{
AnnaBridge	163:e59c8e839560	784	*/
AnnaBridge	163:e59c8e839560	785	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	168:b9e159c1930a	786	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	168:b9e159c1930a	787	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	168:b9e159c1930a	788	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	163:e59c8e839560	789	/**
AnnaBridge	163:e59c8e839560	790	* @}
AnnaBridge	163:e59c8e839560	791	*/
AnnaBridge	163:e59c8e839560	792
AnnaBridge	163:e59c8e839560	793	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	163:e59c8e839560	794	* @{
AnnaBridge	163:e59c8e839560	795	*/
AnnaBridge	168:b9e159c1930a	796	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	168:b9e159c1930a	797	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	168:b9e159c1930a	798	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	168:b9e159c1930a	799	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	168:b9e159c1930a	800	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	168:b9e159c1930a	801	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	168:b9e159c1930a	802	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	168:b9e159c1930a	803	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	168:b9e159c1930a	804	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	168:b9e159c1930a	805	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	168:b9e159c1930a	806	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	168:b9e159c1930a	807	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	168:b9e159c1930a	808	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	168:b9e159c1930a	809	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	168:b9e159c1930a	810	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	168:b9e159c1930a	811	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	163:e59c8e839560	812	/**
AnnaBridge	163:e59c8e839560	813	* @}
AnnaBridge	163:e59c8e839560	814	*/
AnnaBridge	163:e59c8e839560	815
AnnaBridge	163:e59c8e839560	816	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	163:e59c8e839560	817	* @{
AnnaBridge	163:e59c8e839560	818	*/
AnnaBridge	163:e59c8e839560	819	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	163:e59c8e839560	820	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	163:e59c8e839560	821	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	163:e59c8e839560	822	/**
AnnaBridge	163:e59c8e839560	823	* @}
AnnaBridge	163:e59c8e839560	824	*/
AnnaBridge	163:e59c8e839560	825
AnnaBridge	163:e59c8e839560	826	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	163:e59c8e839560	827	* @{
AnnaBridge	163:e59c8e839560	828	*/
AnnaBridge	163:e59c8e839560	829	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	168:b9e159c1930a	830	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	168:b9e159c1930a	831	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	163:e59c8e839560	832	/**
AnnaBridge	163:e59c8e839560	833	* @}
AnnaBridge	163:e59c8e839560	834	*/
AnnaBridge	163:e59c8e839560	835
AnnaBridge	163:e59c8e839560	836	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	163:e59c8e839560	837	* @{
AnnaBridge	163:e59c8e839560	838	*/
AnnaBridge	163:e59c8e839560	839	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	163:e59c8e839560	840	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	163:e59c8e839560	841	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	163:e59c8e839560	842	/**
AnnaBridge	163:e59c8e839560	843	* @}
AnnaBridge	163:e59c8e839560	844	*/
AnnaBridge	163:e59c8e839560	845
AnnaBridge	163:e59c8e839560	846	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	163:e59c8e839560	847	* @{
AnnaBridge	163:e59c8e839560	848	*/
AnnaBridge	163:e59c8e839560	849	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	163:e59c8e839560	850	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	163:e59c8e839560	851	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	163:e59c8e839560	852	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	163:e59c8e839560	853	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	163:e59c8e839560	854	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	163:e59c8e839560	855	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	163:e59c8e839560	856	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	163:e59c8e839560	857	/**
AnnaBridge	163:e59c8e839560	858	* @}
AnnaBridge	163:e59c8e839560	859	*/
AnnaBridge	163:e59c8e839560	860
AnnaBridge	163:e59c8e839560	861	#if defined(TIM_CR2_MMS2)
AnnaBridge	163:e59c8e839560	862	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
AnnaBridge	163:e59c8e839560	863	* @{
AnnaBridge	163:e59c8e839560	864	*/
AnnaBridge	163:e59c8e839560	865	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	866	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	867	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	868	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	869	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	870	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	871	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	872	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	873	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	874	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
AnnaBridge	163:e59c8e839560	875	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	876	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	877	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	878	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	879	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	880	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	163:e59c8e839560	881	/**
AnnaBridge	163:e59c8e839560	882	* @}
AnnaBridge	163:e59c8e839560	883	*/
AnnaBridge	163:e59c8e839560	884	#endif /* TIM_CR2_MMS2 */
AnnaBridge	163:e59c8e839560	885
AnnaBridge	163:e59c8e839560	886	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	163:e59c8e839560	887	* @{
AnnaBridge	163:e59c8e839560	888	*/
AnnaBridge	163:e59c8e839560	889	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	163:e59c8e839560	890	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	163:e59c8e839560	891	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	163:e59c8e839560	892	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	163:e59c8e839560	893	#if defined (TIM_SMCR_SMS_3)
AnnaBridge	163:e59c8e839560	894	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
AnnaBridge	163:e59c8e839560	895	#endif /* TIM_SMCR_SMS_3 */
AnnaBridge	163:e59c8e839560	896	/**
AnnaBridge	163:e59c8e839560	897	* @}
AnnaBridge	163:e59c8e839560	898	*/
AnnaBridge	163:e59c8e839560	899
AnnaBridge	163:e59c8e839560	900	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	163:e59c8e839560	901	* @{
AnnaBridge	163:e59c8e839560	902	*/
AnnaBridge	163:e59c8e839560	903	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	163:e59c8e839560	904	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	163:e59c8e839560	905	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	163:e59c8e839560	906	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	163:e59c8e839560	907	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	163:e59c8e839560	908	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	163:e59c8e839560	909	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	163:e59c8e839560	910	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	163:e59c8e839560	911	/**
AnnaBridge	163:e59c8e839560	912	* @}
AnnaBridge	163:e59c8e839560	913	*/
AnnaBridge	163:e59c8e839560	914
AnnaBridge	163:e59c8e839560	915	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	163:e59c8e839560	916	* @{
AnnaBridge	163:e59c8e839560	917	*/
AnnaBridge	163:e59c8e839560	918	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	163:e59c8e839560	919	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	163:e59c8e839560	920	/**
AnnaBridge	163:e59c8e839560	921	* @}
AnnaBridge	163:e59c8e839560	922	*/
AnnaBridge	163:e59c8e839560	923
AnnaBridge	163:e59c8e839560	924	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	163:e59c8e839560	925	* @{
AnnaBridge	163:e59c8e839560	926	*/
AnnaBridge	163:e59c8e839560	927	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	163:e59c8e839560	928	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	163:e59c8e839560	929	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	163:e59c8e839560	930	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	163:e59c8e839560	931	/**
AnnaBridge	163:e59c8e839560	932	* @}
AnnaBridge	163:e59c8e839560	933	*/
AnnaBridge	163:e59c8e839560	934
AnnaBridge	163:e59c8e839560	935	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	163:e59c8e839560	936	* @{
AnnaBridge	163:e59c8e839560	937	*/
AnnaBridge	163:e59c8e839560	938	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	163:e59c8e839560	939	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	163:e59c8e839560	940	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	163:e59c8e839560	941	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	163:e59c8e839560	942	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	163:e59c8e839560	943	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	168:b9e159c1930a	944	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	163:e59c8e839560	945	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	163:e59c8e839560	946	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	163:e59c8e839560	947	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	168:b9e159c1930a	948	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	163:e59c8e839560	949	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	168:b9e159c1930a	950	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	168:b9e159c1930a	951	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	168:b9e159c1930a	952	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	163:e59c8e839560	953	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	163:e59c8e839560	954	/**
AnnaBridge	163:e59c8e839560	955	* @}
AnnaBridge	163:e59c8e839560	956	*/
AnnaBridge	163:e59c8e839560	957
AnnaBridge	163:e59c8e839560	958
AnnaBridge	163:e59c8e839560	959	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	163:e59c8e839560	960	* @{
AnnaBridge	163:e59c8e839560	961	*/
AnnaBridge	163:e59c8e839560	962	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	163:e59c8e839560	963	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	163:e59c8e839560	964	/**
AnnaBridge	163:e59c8e839560	965	* @}
AnnaBridge	163:e59c8e839560	966	*/
AnnaBridge	163:e59c8e839560	967
AnnaBridge	163:e59c8e839560	968	#if defined(TIM_BDTR_BKF)
AnnaBridge	163:e59c8e839560	969	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
AnnaBridge	163:e59c8e839560	970	* @{
AnnaBridge	163:e59c8e839560	971	*/
AnnaBridge	163:e59c8e839560	972	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	163:e59c8e839560	973	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	163:e59c8e839560	974	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	163:e59c8e839560	975	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	163:e59c8e839560	976	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	163:e59c8e839560	977	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	163:e59c8e839560	978	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	163:e59c8e839560	979	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	163:e59c8e839560	980	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	163:e59c8e839560	981	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	163:e59c8e839560	982	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	163:e59c8e839560	983	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	163:e59c8e839560	984	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	163:e59c8e839560	985	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	163:e59c8e839560	986	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	163:e59c8e839560	987	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	163:e59c8e839560	988	/**
AnnaBridge	163:e59c8e839560	989	* @}
AnnaBridge	163:e59c8e839560	990	*/
AnnaBridge	163:e59c8e839560	991	#endif /* TIM_BDTR_BKF */
AnnaBridge	163:e59c8e839560	992
AnnaBridge	163:e59c8e839560	993	#if defined(TIM_BDTR_BK2P)
AnnaBridge	163:e59c8e839560	994	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
AnnaBridge	163:e59c8e839560	995	* @{
AnnaBridge	163:e59c8e839560	996	*/
AnnaBridge	163:e59c8e839560	997	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
AnnaBridge	163:e59c8e839560	998	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
AnnaBridge	163:e59c8e839560	999	/**
AnnaBridge	163:e59c8e839560	1000	* @}
AnnaBridge	163:e59c8e839560	1001	*/
AnnaBridge	163:e59c8e839560	1002	#endif /* TIM_BDTR_BK2P */
AnnaBridge	163:e59c8e839560	1003
AnnaBridge	163:e59c8e839560	1004	#if defined(TIM_BDTR_BK2F)
AnnaBridge	163:e59c8e839560	1005	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
AnnaBridge	163:e59c8e839560	1006	* @{
AnnaBridge	163:e59c8e839560	1007	*/
AnnaBridge	168:b9e159c1930a	1008	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	163:e59c8e839560	1009	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	163:e59c8e839560	1010	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	163:e59c8e839560	1011	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	163:e59c8e839560	1012	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	163:e59c8e839560	1013	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	163:e59c8e839560	1014	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	163:e59c8e839560	1015	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	163:e59c8e839560	1016	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	163:e59c8e839560	1017	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	163:e59c8e839560	1018	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	163:e59c8e839560	1019	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	163:e59c8e839560	1020	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	163:e59c8e839560	1021	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	163:e59c8e839560	1022	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	163:e59c8e839560	1023	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	163:e59c8e839560	1024	/**
AnnaBridge	163:e59c8e839560	1025	* @}
AnnaBridge	163:e59c8e839560	1026	*/
AnnaBridge	163:e59c8e839560	1027	#endif /* TIM_BDTR_BK2F */
AnnaBridge	163:e59c8e839560	1028
AnnaBridge	163:e59c8e839560	1029	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	163:e59c8e839560	1030	* @{
AnnaBridge	163:e59c8e839560	1031	*/
AnnaBridge	163:e59c8e839560	1032	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	163:e59c8e839560	1033	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	163:e59c8e839560	1034	/**
AnnaBridge	163:e59c8e839560	1035	* @}
AnnaBridge	163:e59c8e839560	1036	*/
AnnaBridge	163:e59c8e839560	1037
AnnaBridge	163:e59c8e839560	1038	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	163:e59c8e839560	1039	* @{
AnnaBridge	163:e59c8e839560	1040	*/
AnnaBridge	163:e59c8e839560	1041	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	163:e59c8e839560	1042	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	163:e59c8e839560	1043	/**
AnnaBridge	163:e59c8e839560	1044	* @}
AnnaBridge	163:e59c8e839560	1045	*/
AnnaBridge	163:e59c8e839560	1046
AnnaBridge	163:e59c8e839560	1047
AnnaBridge	163:e59c8e839560	1048	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	163:e59c8e839560	1049	* @{
AnnaBridge	163:e59c8e839560	1050	*/
AnnaBridge	163:e59c8e839560	1051	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1052	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1053	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1054	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1055	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1056	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1057	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1058	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1059	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1060	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1061	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1062	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1063	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1064	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1065	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1066	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1067	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1068	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1069	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1070	#if defined(TIM_CCR6_CCR6)
AnnaBridge	163:e59c8e839560	1071	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1072	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1073	#endif /* TIM_CCR6_CCR6 */
AnnaBridge	163:e59c8e839560	1074	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR register is the DMA base address for DMA burst /
AnnaBridge	163:e59c8e839560	1075	/**
AnnaBridge	163:e59c8e839560	1076	* @}
AnnaBridge	163:e59c8e839560	1077	*/
AnnaBridge	163:e59c8e839560	1078
AnnaBridge	163:e59c8e839560	1079	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	163:e59c8e839560	1080	* @{
AnnaBridge	163:e59c8e839560	1081	*/
AnnaBridge	163:e59c8e839560	1082	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1083	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1084	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1085	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1086	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1087	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1088	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1089	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1090	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1091	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1092	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1093	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1094	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1095	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1096	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1097	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1098	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1099	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	163:e59c8e839560	1100	/**
AnnaBridge	163:e59c8e839560	1101	* @}
AnnaBridge	163:e59c8e839560	1102	*/
AnnaBridge	163:e59c8e839560	1103
AnnaBridge	163:e59c8e839560	1104	#if defined(TIM1)
AnnaBridge	163:e59c8e839560	1105	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
AnnaBridge	168:b9e159c1930a	1106	* @{
AnnaBridge	168:b9e159c1930a	1107	*/
AnnaBridge	168:b9e159c1930a	1108	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
AnnaBridge	168:b9e159c1930a	1109	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
AnnaBridge	168:b9e159c1930a	1110	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1111	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 \| TIM1_OR_ETR_RMP_1\| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1112	/**
AnnaBridge	163:e59c8e839560	1113	* @}
AnnaBridge	163:e59c8e839560	1114	*/
AnnaBridge	163:e59c8e839560	1115	#if defined(ADC4)
AnnaBridge	168:b9e159c1930a	1116	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP TIM1 External Trigger ADC4 Remap
AnnaBridge	168:b9e159c1930a	1117	* @{
AnnaBridge	168:b9e159c1930a	1118	*/
AnnaBridge	168:b9e159c1930a	1119	#define LL_TIM_TIM1_ETR_ADC4_RMP_NC TIM1_OR_RMP_MASK /!< TIM1_ETR is not connected to ADC4 analog watchdog x/
AnnaBridge	168:b9e159c1930a	1120	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 1 /
AnnaBridge	168:b9e159c1930a	1121	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1122	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1123	/**
AnnaBridge	163:e59c8e839560	1124	* @}
AnnaBridge	163:e59c8e839560	1125	*/
AnnaBridge	163:e59c8e839560	1126	#else
AnnaBridge	163:e59c8e839560	1127	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
AnnaBridge	168:b9e159c1930a	1128	* @{
AnnaBridge	168:b9e159c1930a	1129	*/
AnnaBridge	168:b9e159c1930a	1130	#define LL_TIM_TIM1_ETR_ADC2_RMP_NC TIM1_OR_RMP_MASK /!< TIM1_ETR is not connected to ADC2 analog watchdog x/
AnnaBridge	168:b9e159c1930a	1131	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 1 /
AnnaBridge	168:b9e159c1930a	1132	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1133	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1134	/**
AnnaBridge	163:e59c8e839560	1135	* @}
AnnaBridge	163:e59c8e839560	1136	*/
AnnaBridge	163:e59c8e839560	1137	#endif /* ADC4 */
AnnaBridge	163:e59c8e839560	1138	#endif /* TIM1 */
AnnaBridge	163:e59c8e839560	1139	#if defined(TIM8)
AnnaBridge	163:e59c8e839560	1140	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
AnnaBridge	168:b9e159c1930a	1141	* @{
AnnaBridge	168:b9e159c1930a	1142	*/
AnnaBridge	168:b9e159c1930a	1143	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR_RMP_MASK /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
AnnaBridge	168:b9e159c1930a	1144	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
AnnaBridge	168:b9e159c1930a	1145	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1146	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 \| TIM8_OR_ETR_RMP_1 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1147	/**
AnnaBridge	163:e59c8e839560	1148	* @}
AnnaBridge	163:e59c8e839560	1149	*/
AnnaBridge	163:e59c8e839560	1150
AnnaBridge	163:e59c8e839560	1151	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
AnnaBridge	168:b9e159c1930a	1152	* @{
AnnaBridge	168:b9e159c1930a	1153	*/
AnnaBridge	168:b9e159c1930a	1154	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR_RMP_MASK /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
AnnaBridge	168:b9e159c1930a	1155	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
AnnaBridge	168:b9e159c1930a	1156	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1157	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 \| TIM8_OR_ETR_RMP_3 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1158	/**
AnnaBridge	163:e59c8e839560	1159	* @}
AnnaBridge	163:e59c8e839560	1160	*/
AnnaBridge	163:e59c8e839560	1161	#endif /* TIM8 */
AnnaBridge	163:e59c8e839560	1162	#if defined(TIM16)
AnnaBridge	163:e59c8e839560	1163	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
AnnaBridge	168:b9e159c1930a	1164	* @{
AnnaBridge	168:b9e159c1930a	1165	*/
AnnaBridge	168:b9e159c1930a	1166	#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /!< TIM16 input capture 1 is connected to GPIO /
AnnaBridge	168:b9e159c1930a	1167	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup interrupt /
AnnaBridge	168:b9e159c1930a	1168	#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to HSE/32 clock /
AnnaBridge	168:b9e159c1930a	1169	#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 \| TIM16_OR_TI1_RMP_0 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to MCO /
AnnaBridge	163:e59c8e839560	1170	/**
AnnaBridge	163:e59c8e839560	1171	* @}
AnnaBridge	163:e59c8e839560	1172	*/
AnnaBridge	163:e59c8e839560	1173	#endif /* TIM16 */
AnnaBridge	163:e59c8e839560	1174	#if defined(TIM20)
AnnaBridge	163:e59c8e839560	1175	/** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
AnnaBridge	168:b9e159c1930a	1176	* @{
AnnaBridge	168:b9e159c1930a	1177	*/
AnnaBridge	168:b9e159c1930a	1178	#define LL_TIM_TIM20_ETR_ADC3_RMP_NC TIM20_OR_RMP_MASK /!< TIM20_ETR is not connected to ADC3 analog watchdog x /
AnnaBridge	163:e59c8e839560	1179	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog /
AnnaBridge	163:e59c8e839560	1180	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1181	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 \| TIM20_OR_ETR_RMP_1 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1182	/**
AnnaBridge	163:e59c8e839560	1183	* @}
AnnaBridge	163:e59c8e839560	1184	*/
AnnaBridge	163:e59c8e839560	1185
AnnaBridge	163:e59c8e839560	1186	/** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
AnnaBridge	168:b9e159c1930a	1187	* @{
AnnaBridge	168:b9e159c1930a	1188	*/
AnnaBridge	168:b9e159c1930a	1189	#define LL_TIM_TIM20_ETR_ADC4_RMP_NC TIM20_OR_RMP_MASK /!< TIM20_ETR is not connected to ADC4 analog watchdog x /
AnnaBridge	163:e59c8e839560	1190	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 1 /
AnnaBridge	163:e59c8e839560	1191	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 2 /
AnnaBridge	163:e59c8e839560	1192	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 \| TIM20_OR_ETR_RMP_3 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 3 /
AnnaBridge	163:e59c8e839560	1193	/**
AnnaBridge	163:e59c8e839560	1194	* @}
AnnaBridge	163:e59c8e839560	1195	*/
AnnaBridge	163:e59c8e839560	1196	#endif /* TIM20 */
AnnaBridge	163:e59c8e839560	1197	#if defined(TIM14)
AnnaBridge	163:e59c8e839560	1198	/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
AnnaBridge	168:b9e159c1930a	1199	* @{
AnnaBridge	168:b9e159c1930a	1200	*/
AnnaBridge	168:b9e159c1930a	1201	#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /!< TIM14_TI1 is connected to GPIO /
AnnaBridge	168:b9e159c1930a	1202	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC Clock /
AnnaBridge	168:b9e159c1930a	1203	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 /
AnnaBridge	168:b9e159c1930a	1204	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
AnnaBridge	163:e59c8e839560	1205	/**
AnnaBridge	163:e59c8e839560	1206	* @}
AnnaBridge	163:e59c8e839560	1207	*/
AnnaBridge	163:e59c8e839560	1208	#endif /* TIM14 */
AnnaBridge	163:e59c8e839560	1209
AnnaBridge	163:e59c8e839560	1210	#if defined(TIM_SMCR_OCCS)
AnnaBridge	163:e59c8e839560	1211	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	163:e59c8e839560	1212	* @{
AnnaBridge	163:e59c8e839560	1213	*/
AnnaBridge	163:e59c8e839560	1214	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
AnnaBridge	168:b9e159c1930a	1215	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	163:e59c8e839560	1216	/**
AnnaBridge	163:e59c8e839560	1217	* @}
AnnaBridge	163:e59c8e839560	1218	*/
AnnaBridge	163:e59c8e839560	1219	#endif /* TIM_SMCR_OCCS*/
AnnaBridge	163:e59c8e839560	1220
AnnaBridge	163:e59c8e839560	1221	/**
AnnaBridge	163:e59c8e839560	1222	* @}
AnnaBridge	163:e59c8e839560	1223	*/
AnnaBridge	163:e59c8e839560	1224
AnnaBridge	163:e59c8e839560	1225	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1226	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	163:e59c8e839560	1227	* @{
AnnaBridge	163:e59c8e839560	1228	*/
AnnaBridge	163:e59c8e839560	1229
AnnaBridge	163:e59c8e839560	1230	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	163:e59c8e839560	1231	* @{
AnnaBridge	163:e59c8e839560	1232	*/
AnnaBridge	163:e59c8e839560	1233	/**
AnnaBridge	163:e59c8e839560	1234	* @brief Write a value in TIM register.
AnnaBridge	163:e59c8e839560	1235	* @param __INSTANCE__ TIM Instance
AnnaBridge	163:e59c8e839560	1236	* @param __REG__ Register to be written
AnnaBridge	163:e59c8e839560	1237	* @param __VALUE__ Value to be written in the register
AnnaBridge	163:e59c8e839560	1238	* @retval None
AnnaBridge	163:e59c8e839560	1239	*/
AnnaBridge	163:e59c8e839560	1240	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	163:e59c8e839560	1241
AnnaBridge	163:e59c8e839560	1242	/**
AnnaBridge	163:e59c8e839560	1243	* @brief Read a value in TIM register.
AnnaBridge	163:e59c8e839560	1244	* @param __INSTANCE__ TIM Instance
AnnaBridge	163:e59c8e839560	1245	* @param __REG__ Register to be read
AnnaBridge	163:e59c8e839560	1246	* @retval Register value
AnnaBridge	163:e59c8e839560	1247	*/
AnnaBridge	163:e59c8e839560	1248	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	163:e59c8e839560	1249	/**
AnnaBridge	163:e59c8e839560	1250	* @}
AnnaBridge	163:e59c8e839560	1251	*/
AnnaBridge	163:e59c8e839560	1252
AnnaBridge	163:e59c8e839560	1253	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	163:e59c8e839560	1254	* @{
AnnaBridge	163:e59c8e839560	1255	*/
AnnaBridge	163:e59c8e839560	1256	/**
AnnaBridge	163:e59c8e839560	1257	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
AnnaBridge	163:e59c8e839560	1258	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
AnnaBridge	163:e59c8e839560	1259	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
AnnaBridge	163:e59c8e839560	1260	* to TIMx_CNT register bit 31)
AnnaBridge	163:e59c8e839560	1261	* @param __CNT__ Counter value
AnnaBridge	163:e59c8e839560	1262	* @retval UIF status bit
AnnaBridge	163:e59c8e839560	1263	*/
AnnaBridge	163:e59c8e839560	1264	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
AnnaBridge	163:e59c8e839560	1265	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
AnnaBridge	163:e59c8e839560	1266
AnnaBridge	163:e59c8e839560	1267	/**
AnnaBridge	163:e59c8e839560	1268	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	163:e59c8e839560	1269	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	163:e59c8e839560	1270	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1271	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1272	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	163:e59c8e839560	1273	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	163:e59c8e839560	1274	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	163:e59c8e839560	1275	* @param __DT__ deadtime duration (in ns)
AnnaBridge	163:e59c8e839560	1276	* @retval DTG[0:7]
AnnaBridge	163:e59c8e839560	1277	*/
AnnaBridge	163:e59c8e839560	1278	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	163:e59c8e839560	1279	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	163:e59c8e839560	1280	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
AnnaBridge	163:e59c8e839560	1281	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
AnnaBridge	163:e59c8e839560	1282	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
AnnaBridge	163:e59c8e839560	1283	0U)
AnnaBridge	163:e59c8e839560	1284
AnnaBridge	163:e59c8e839560	1285	/**
AnnaBridge	163:e59c8e839560	1286	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	163:e59c8e839560	1287	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	163:e59c8e839560	1288	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1289	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1290	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	1291	*/
AnnaBridge	163:e59c8e839560	1292	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	163:e59c8e839560	1293	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	163:e59c8e839560	1294
AnnaBridge	163:e59c8e839560	1295	/**
AnnaBridge	163:e59c8e839560	1296	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	163:e59c8e839560	1297	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	163:e59c8e839560	1298	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1299	* @param __PSC__ prescaler
AnnaBridge	163:e59c8e839560	1300	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	163:e59c8e839560	1301	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	1302	*/
AnnaBridge	163:e59c8e839560	1303	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	163:e59c8e839560	1304	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	163:e59c8e839560	1305
AnnaBridge	163:e59c8e839560	1306	/**
AnnaBridge	163:e59c8e839560	1307	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	163:e59c8e839560	1308	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	163:e59c8e839560	1309	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1310	* @param __PSC__ prescaler
AnnaBridge	163:e59c8e839560	1311	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	163:e59c8e839560	1312	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	1313	*/
AnnaBridge	163:e59c8e839560	1314	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	163:e59c8e839560	1315	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	163:e59c8e839560	1316	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	163:e59c8e839560	1317
AnnaBridge	163:e59c8e839560	1318	/**
AnnaBridge	163:e59c8e839560	1319	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	163:e59c8e839560	1320	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	163:e59c8e839560	1321	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	163:e59c8e839560	1322	* @param __PSC__ prescaler
AnnaBridge	163:e59c8e839560	1323	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	163:e59c8e839560	1324	* @param __PULSE__ pulse duration (in us)
AnnaBridge	163:e59c8e839560	1325	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	1326	*/
AnnaBridge	163:e59c8e839560	1327	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	163:e59c8e839560	1328	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	163:e59c8e839560	1329	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	163:e59c8e839560	1330
AnnaBridge	163:e59c8e839560	1331	/**
AnnaBridge	163:e59c8e839560	1332	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	163:e59c8e839560	1333	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	163:e59c8e839560	1334	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1335	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	163:e59c8e839560	1336	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	163:e59c8e839560	1337	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	163:e59c8e839560	1338	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	163:e59c8e839560	1339	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	163:e59c8e839560	1340	*/
AnnaBridge	163:e59c8e839560	1341	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	168:b9e159c1930a	1342	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	163:e59c8e839560	1343
AnnaBridge	163:e59c8e839560	1344
AnnaBridge	163:e59c8e839560	1345	/**
AnnaBridge	163:e59c8e839560	1346	* @}
AnnaBridge	163:e59c8e839560	1347	*/
AnnaBridge	163:e59c8e839560	1348
AnnaBridge	163:e59c8e839560	1349
AnnaBridge	163:e59c8e839560	1350	/**
AnnaBridge	163:e59c8e839560	1351	* @}
AnnaBridge	163:e59c8e839560	1352	*/
AnnaBridge	163:e59c8e839560	1353
AnnaBridge	163:e59c8e839560	1354	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1355	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	163:e59c8e839560	1356	* @{
AnnaBridge	163:e59c8e839560	1357	*/
AnnaBridge	163:e59c8e839560	1358
AnnaBridge	163:e59c8e839560	1359	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	163:e59c8e839560	1360	* @{
AnnaBridge	163:e59c8e839560	1361	*/
AnnaBridge	163:e59c8e839560	1362	/**
AnnaBridge	163:e59c8e839560	1363	* @brief Enable timer counter.
AnnaBridge	163:e59c8e839560	1364	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	163:e59c8e839560	1365	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1366	* @retval None
AnnaBridge	163:e59c8e839560	1367	*/
AnnaBridge	163:e59c8e839560	1368	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1369	{
AnnaBridge	163:e59c8e839560	1370	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	163:e59c8e839560	1371	}
AnnaBridge	163:e59c8e839560	1372
AnnaBridge	163:e59c8e839560	1373	/**
AnnaBridge	163:e59c8e839560	1374	* @brief Disable timer counter.
AnnaBridge	163:e59c8e839560	1375	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	163:e59c8e839560	1376	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1377	* @retval None
AnnaBridge	163:e59c8e839560	1378	*/
AnnaBridge	163:e59c8e839560	1379	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1380	{
AnnaBridge	163:e59c8e839560	1381	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	163:e59c8e839560	1382	}
AnnaBridge	163:e59c8e839560	1383
AnnaBridge	163:e59c8e839560	1384	/**
AnnaBridge	163:e59c8e839560	1385	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	163:e59c8e839560	1386	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	163:e59c8e839560	1387	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1388	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1389	*/
AnnaBridge	163:e59c8e839560	1390	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1391	{
AnnaBridge	163:e59c8e839560	1392	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	163:e59c8e839560	1393	}
AnnaBridge	163:e59c8e839560	1394
AnnaBridge	163:e59c8e839560	1395	/**
AnnaBridge	163:e59c8e839560	1396	* @brief Enable update event generation.
AnnaBridge	163:e59c8e839560	1397	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	163:e59c8e839560	1398	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1399	* @retval None
AnnaBridge	163:e59c8e839560	1400	*/
AnnaBridge	163:e59c8e839560	1401	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1402	{
AnnaBridge	168:b9e159c1930a	1403	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	163:e59c8e839560	1404	}
AnnaBridge	163:e59c8e839560	1405
AnnaBridge	163:e59c8e839560	1406	/**
AnnaBridge	163:e59c8e839560	1407	* @brief Disable update event generation.
AnnaBridge	163:e59c8e839560	1408	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	163:e59c8e839560	1409	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1410	* @retval None
AnnaBridge	163:e59c8e839560	1411	*/
AnnaBridge	163:e59c8e839560	1412	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1413	{
AnnaBridge	168:b9e159c1930a	1414	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	163:e59c8e839560	1415	}
AnnaBridge	163:e59c8e839560	1416
AnnaBridge	163:e59c8e839560	1417	/**
AnnaBridge	163:e59c8e839560	1418	* @brief Indicates whether update event generation is enabled.
AnnaBridge	163:e59c8e839560	1419	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	163:e59c8e839560	1420	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1421	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1422	*/
AnnaBridge	163:e59c8e839560	1423	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1424	{
AnnaBridge	163:e59c8e839560	1425	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
AnnaBridge	163:e59c8e839560	1426	}
AnnaBridge	163:e59c8e839560	1427
AnnaBridge	163:e59c8e839560	1428	/**
AnnaBridge	163:e59c8e839560	1429	* @brief Set update event source
AnnaBridge	163:e59c8e839560	1430	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	163:e59c8e839560	1431	* generate an update interrupt or DMA request if enabled:
AnnaBridge	163:e59c8e839560	1432	* - Counter overflow/underflow
AnnaBridge	163:e59c8e839560	1433	* - Setting the UG bit
AnnaBridge	163:e59c8e839560	1434	* - Update generation through the slave mode controller
AnnaBridge	163:e59c8e839560	1435	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	163:e59c8e839560	1436	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	163:e59c8e839560	1437	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	163:e59c8e839560	1438	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1439	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1440	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	163:e59c8e839560	1441	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	163:e59c8e839560	1442	* @retval None
AnnaBridge	163:e59c8e839560	1443	*/
AnnaBridge	163:e59c8e839560	1444	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	163:e59c8e839560	1445	{
AnnaBridge	163:e59c8e839560	1446	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	163:e59c8e839560	1447	}
AnnaBridge	163:e59c8e839560	1448
AnnaBridge	163:e59c8e839560	1449	/**
AnnaBridge	163:e59c8e839560	1450	* @brief Get actual event update source
AnnaBridge	163:e59c8e839560	1451	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	163:e59c8e839560	1452	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1453	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1454	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	163:e59c8e839560	1455	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	163:e59c8e839560	1456	*/
AnnaBridge	163:e59c8e839560	1457	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1458	{
AnnaBridge	163:e59c8e839560	1459	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	163:e59c8e839560	1460	}
AnnaBridge	163:e59c8e839560	1461
AnnaBridge	163:e59c8e839560	1462	/**
AnnaBridge	163:e59c8e839560	1463	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	163:e59c8e839560	1464	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	163:e59c8e839560	1465	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1466	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1467	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	163:e59c8e839560	1468	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	163:e59c8e839560	1469	* @retval None
AnnaBridge	163:e59c8e839560	1470	*/
AnnaBridge	163:e59c8e839560	1471	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	163:e59c8e839560	1472	{
AnnaBridge	163:e59c8e839560	1473	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	163:e59c8e839560	1474	}
AnnaBridge	163:e59c8e839560	1475
AnnaBridge	163:e59c8e839560	1476	/**
AnnaBridge	163:e59c8e839560	1477	* @brief Get actual one pulse mode.
AnnaBridge	163:e59c8e839560	1478	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	163:e59c8e839560	1479	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1480	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1481	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	163:e59c8e839560	1482	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	163:e59c8e839560	1483	*/
AnnaBridge	163:e59c8e839560	1484	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1485	{
AnnaBridge	163:e59c8e839560	1486	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	163:e59c8e839560	1487	}
AnnaBridge	163:e59c8e839560	1488
AnnaBridge	163:e59c8e839560	1489	/**
AnnaBridge	163:e59c8e839560	1490	* @brief Set the timer counter counting mode.
AnnaBridge	163:e59c8e839560	1491	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	163:e59c8e839560	1492	* check whether or not the counter mode selection feature is supported
AnnaBridge	163:e59c8e839560	1493	* by a timer instance.
AnnaBridge	163:e59c8e839560	1494	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	163:e59c8e839560	1495	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	163:e59c8e839560	1496	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1497	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1498	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	163:e59c8e839560	1499	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	163:e59c8e839560	1500	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	163:e59c8e839560	1501	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	163:e59c8e839560	1502	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	163:e59c8e839560	1503	* @retval None
AnnaBridge	163:e59c8e839560	1504	*/
AnnaBridge	163:e59c8e839560	1505	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	163:e59c8e839560	1506	{
AnnaBridge	163:e59c8e839560	1507	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	163:e59c8e839560	1508	}
AnnaBridge	163:e59c8e839560	1509
AnnaBridge	163:e59c8e839560	1510	/**
AnnaBridge	163:e59c8e839560	1511	* @brief Get actual counter mode.
AnnaBridge	163:e59c8e839560	1512	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	163:e59c8e839560	1513	* check whether or not the counter mode selection feature is supported
AnnaBridge	163:e59c8e839560	1514	* by a timer instance.
AnnaBridge	163:e59c8e839560	1515	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	163:e59c8e839560	1516	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	163:e59c8e839560	1517	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1518	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1519	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	163:e59c8e839560	1520	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	163:e59c8e839560	1521	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	163:e59c8e839560	1522	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	163:e59c8e839560	1523	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	163:e59c8e839560	1524	*/
AnnaBridge	163:e59c8e839560	1525	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1526	{
AnnaBridge	163:e59c8e839560	1527	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	163:e59c8e839560	1528	}
AnnaBridge	163:e59c8e839560	1529
AnnaBridge	163:e59c8e839560	1530	/**
AnnaBridge	163:e59c8e839560	1531	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	163:e59c8e839560	1532	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	163:e59c8e839560	1533	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1534	* @retval None
AnnaBridge	163:e59c8e839560	1535	*/
AnnaBridge	163:e59c8e839560	1536	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1537	{
AnnaBridge	163:e59c8e839560	1538	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	163:e59c8e839560	1539	}
AnnaBridge	163:e59c8e839560	1540
AnnaBridge	163:e59c8e839560	1541	/**
AnnaBridge	163:e59c8e839560	1542	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	163:e59c8e839560	1543	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	163:e59c8e839560	1544	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1545	* @retval None
AnnaBridge	163:e59c8e839560	1546	*/
AnnaBridge	163:e59c8e839560	1547	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1548	{
AnnaBridge	163:e59c8e839560	1549	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	163:e59c8e839560	1550	}
AnnaBridge	163:e59c8e839560	1551
AnnaBridge	163:e59c8e839560	1552	/**
AnnaBridge	163:e59c8e839560	1553	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	163:e59c8e839560	1554	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	163:e59c8e839560	1555	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1556	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1557	*/
AnnaBridge	163:e59c8e839560	1558	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1559	{
AnnaBridge	163:e59c8e839560	1560	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	163:e59c8e839560	1561	}
AnnaBridge	163:e59c8e839560	1562
AnnaBridge	163:e59c8e839560	1563	/**
AnnaBridge	163:e59c8e839560	1564	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	163:e59c8e839560	1565	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1566	* whether or not the clock division feature is supported by the timer
AnnaBridge	163:e59c8e839560	1567	* instance.
AnnaBridge	163:e59c8e839560	1568	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	163:e59c8e839560	1569	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1570	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1571	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	163:e59c8e839560	1572	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	163:e59c8e839560	1573	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	163:e59c8e839560	1574	* @retval None
AnnaBridge	163:e59c8e839560	1575	*/
AnnaBridge	163:e59c8e839560	1576	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	163:e59c8e839560	1577	{
AnnaBridge	163:e59c8e839560	1578	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	163:e59c8e839560	1579	}
AnnaBridge	163:e59c8e839560	1580
AnnaBridge	163:e59c8e839560	1581	/**
AnnaBridge	163:e59c8e839560	1582	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	163:e59c8e839560	1583	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1584	* whether or not the clock division feature is supported by the timer
AnnaBridge	163:e59c8e839560	1585	* instance.
AnnaBridge	163:e59c8e839560	1586	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	163:e59c8e839560	1587	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1588	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1589	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	163:e59c8e839560	1590	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	163:e59c8e839560	1591	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	163:e59c8e839560	1592	*/
AnnaBridge	163:e59c8e839560	1593	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1594	{
AnnaBridge	163:e59c8e839560	1595	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	163:e59c8e839560	1596	}
AnnaBridge	163:e59c8e839560	1597
AnnaBridge	163:e59c8e839560	1598	/**
AnnaBridge	163:e59c8e839560	1599	* @brief Set the counter value.
AnnaBridge	163:e59c8e839560	1600	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1601	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	1602	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	163:e59c8e839560	1603	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1604	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	163:e59c8e839560	1605	* @retval None
AnnaBridge	163:e59c8e839560	1606	*/
AnnaBridge	163:e59c8e839560	1607	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	163:e59c8e839560	1608	{
AnnaBridge	163:e59c8e839560	1609	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	163:e59c8e839560	1610	}
AnnaBridge	163:e59c8e839560	1611
AnnaBridge	163:e59c8e839560	1612	/**
AnnaBridge	163:e59c8e839560	1613	* @brief Get the counter value.
AnnaBridge	163:e59c8e839560	1614	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1615	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	1616	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	163:e59c8e839560	1617	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1618	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	163:e59c8e839560	1619	*/
AnnaBridge	163:e59c8e839560	1620	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1621	{
AnnaBridge	163:e59c8e839560	1622	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	163:e59c8e839560	1623	}
AnnaBridge	163:e59c8e839560	1624
AnnaBridge	163:e59c8e839560	1625	/**
AnnaBridge	163:e59c8e839560	1626	* @brief Get the current direction of the counter
AnnaBridge	163:e59c8e839560	1627	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	163:e59c8e839560	1628	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1629	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1630	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	163:e59c8e839560	1631	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	163:e59c8e839560	1632	*/
AnnaBridge	163:e59c8e839560	1633	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1634	{
AnnaBridge	163:e59c8e839560	1635	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	163:e59c8e839560	1636	}
AnnaBridge	163:e59c8e839560	1637
AnnaBridge	163:e59c8e839560	1638	/**
AnnaBridge	163:e59c8e839560	1639	* @brief Set the prescaler value.
AnnaBridge	163:e59c8e839560	1640	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	163:e59c8e839560	1641	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	163:e59c8e839560	1642	* prescaler ratio is taken into account at the next update event.
AnnaBridge	163:e59c8e839560	1643	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	163:e59c8e839560	1644	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	163:e59c8e839560	1645	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1646	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	1647	* @retval None
AnnaBridge	163:e59c8e839560	1648	*/
AnnaBridge	163:e59c8e839560	1649	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	163:e59c8e839560	1650	{
AnnaBridge	163:e59c8e839560	1651	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	163:e59c8e839560	1652	}
AnnaBridge	163:e59c8e839560	1653
AnnaBridge	163:e59c8e839560	1654	/**
AnnaBridge	163:e59c8e839560	1655	* @brief Get the prescaler value.
AnnaBridge	163:e59c8e839560	1656	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	163:e59c8e839560	1657	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1658	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	1659	*/
AnnaBridge	163:e59c8e839560	1660	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1661	{
AnnaBridge	163:e59c8e839560	1662	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	163:e59c8e839560	1663	}
AnnaBridge	163:e59c8e839560	1664
AnnaBridge	163:e59c8e839560	1665	/**
AnnaBridge	163:e59c8e839560	1666	* @brief Set the auto-reload value.
AnnaBridge	163:e59c8e839560	1667	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	163:e59c8e839560	1668	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1669	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	1670	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	163:e59c8e839560	1671	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	163:e59c8e839560	1672	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1673	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	1674	* @retval None
AnnaBridge	163:e59c8e839560	1675	*/
AnnaBridge	163:e59c8e839560	1676	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	163:e59c8e839560	1677	{
AnnaBridge	163:e59c8e839560	1678	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	163:e59c8e839560	1679	}
AnnaBridge	163:e59c8e839560	1680
AnnaBridge	163:e59c8e839560	1681	/**
AnnaBridge	163:e59c8e839560	1682	* @brief Get the auto-reload value.
AnnaBridge	163:e59c8e839560	1683	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	163:e59c8e839560	1684	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1685	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	1686	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1687	* @retval Auto-reload value
AnnaBridge	163:e59c8e839560	1688	*/
AnnaBridge	163:e59c8e839560	1689	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1690	{
AnnaBridge	163:e59c8e839560	1691	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	163:e59c8e839560	1692	}
AnnaBridge	163:e59c8e839560	1693
AnnaBridge	163:e59c8e839560	1694	/**
AnnaBridge	163:e59c8e839560	1695	* @brief Set the repetition counter value.
AnnaBridge	163:e59c8e839560	1696	* @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
AnnaBridge	163:e59c8e839560	1697	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1698	* whether or not a timer instance supports a repetition counter.
AnnaBridge	163:e59c8e839560	1699	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	163:e59c8e839560	1700	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1701	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	163:e59c8e839560	1702	* @retval None
AnnaBridge	163:e59c8e839560	1703	*/
AnnaBridge	163:e59c8e839560	1704	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	163:e59c8e839560	1705	{
AnnaBridge	163:e59c8e839560	1706	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	163:e59c8e839560	1707	}
AnnaBridge	163:e59c8e839560	1708
AnnaBridge	163:e59c8e839560	1709	/**
AnnaBridge	163:e59c8e839560	1710	* @brief Get the repetition counter value.
AnnaBridge	163:e59c8e839560	1711	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1712	* whether or not a timer instance supports a repetition counter.
AnnaBridge	163:e59c8e839560	1713	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	163:e59c8e839560	1714	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1715	* @retval Repetition counter value
AnnaBridge	163:e59c8e839560	1716	*/
AnnaBridge	163:e59c8e839560	1717	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1718	{
AnnaBridge	163:e59c8e839560	1719	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	163:e59c8e839560	1720	}
AnnaBridge	163:e59c8e839560	1721
AnnaBridge	163:e59c8e839560	1722	#if defined(TIM_CR1_UIFREMAP)
AnnaBridge	163:e59c8e839560	1723	/**
AnnaBridge	163:e59c8e839560	1724	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
AnnaBridge	163:e59c8e839560	1725	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
AnnaBridge	163:e59c8e839560	1726	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
AnnaBridge	163:e59c8e839560	1727	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1728	* @retval None
AnnaBridge	163:e59c8e839560	1729	*/
AnnaBridge	163:e59c8e839560	1730	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1731	{
AnnaBridge	163:e59c8e839560	1732	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	163:e59c8e839560	1733	}
AnnaBridge	163:e59c8e839560	1734
AnnaBridge	163:e59c8e839560	1735	/**
AnnaBridge	163:e59c8e839560	1736	* @brief Disable update interrupt flag (UIF) remapping.
AnnaBridge	163:e59c8e839560	1737	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
AnnaBridge	163:e59c8e839560	1738	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1739	* @retval None
AnnaBridge	163:e59c8e839560	1740	*/
AnnaBridge	163:e59c8e839560	1741	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1742	{
AnnaBridge	163:e59c8e839560	1743	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	163:e59c8e839560	1744	}
AnnaBridge	163:e59c8e839560	1745
AnnaBridge	163:e59c8e839560	1746	#endif /* TIM_CR1_UIFREMAP */
AnnaBridge	163:e59c8e839560	1747	/**
AnnaBridge	163:e59c8e839560	1748	* @}
AnnaBridge	163:e59c8e839560	1749	*/
AnnaBridge	163:e59c8e839560	1750
AnnaBridge	163:e59c8e839560	1751	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	163:e59c8e839560	1752	* @{
AnnaBridge	163:e59c8e839560	1753	*/
AnnaBridge	163:e59c8e839560	1754	/**
AnnaBridge	163:e59c8e839560	1755	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	163:e59c8e839560	1756	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	163:e59c8e839560	1757	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	163:e59c8e839560	1758	* @note Only on channels that have a complementary output.
AnnaBridge	163:e59c8e839560	1759	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1760	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	163:e59c8e839560	1761	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	163:e59c8e839560	1762	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1763	* @retval None
AnnaBridge	163:e59c8e839560	1764	*/
AnnaBridge	163:e59c8e839560	1765	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1766	{
AnnaBridge	163:e59c8e839560	1767	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	163:e59c8e839560	1768	}
AnnaBridge	163:e59c8e839560	1769
AnnaBridge	163:e59c8e839560	1770	/**
AnnaBridge	163:e59c8e839560	1771	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	163:e59c8e839560	1772	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1773	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	163:e59c8e839560	1774	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	163:e59c8e839560	1775	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1776	* @retval None
AnnaBridge	163:e59c8e839560	1777	*/
AnnaBridge	163:e59c8e839560	1778	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1779	{
AnnaBridge	163:e59c8e839560	1780	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	163:e59c8e839560	1781	}
AnnaBridge	163:e59c8e839560	1782
AnnaBridge	163:e59c8e839560	1783	/**
AnnaBridge	163:e59c8e839560	1784	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	163:e59c8e839560	1785	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	1786	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	163:e59c8e839560	1787	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	163:e59c8e839560	1788	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1789	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1790	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	163:e59c8e839560	1791	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	163:e59c8e839560	1792	* @retval None
AnnaBridge	163:e59c8e839560	1793	*/
AnnaBridge	163:e59c8e839560	1794	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	163:e59c8e839560	1795	{
AnnaBridge	163:e59c8e839560	1796	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	163:e59c8e839560	1797	}
AnnaBridge	163:e59c8e839560	1798
AnnaBridge	163:e59c8e839560	1799	/**
AnnaBridge	163:e59c8e839560	1800	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	163:e59c8e839560	1801	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	163:e59c8e839560	1802	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1803	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1804	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	163:e59c8e839560	1805	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	163:e59c8e839560	1806	* @retval None
AnnaBridge	163:e59c8e839560	1807	*/
AnnaBridge	163:e59c8e839560	1808	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	163:e59c8e839560	1809	{
AnnaBridge	163:e59c8e839560	1810	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	163:e59c8e839560	1811	}
AnnaBridge	163:e59c8e839560	1812
AnnaBridge	163:e59c8e839560	1813	/**
AnnaBridge	163:e59c8e839560	1814	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	163:e59c8e839560	1815	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	163:e59c8e839560	1816	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1817	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1818	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	163:e59c8e839560	1819	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	163:e59c8e839560	1820	*/
AnnaBridge	163:e59c8e839560	1821	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	1822	{
AnnaBridge	163:e59c8e839560	1823	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	163:e59c8e839560	1824	}
AnnaBridge	163:e59c8e839560	1825
AnnaBridge	163:e59c8e839560	1826	/**
AnnaBridge	163:e59c8e839560	1827	* @brief Set the lock level to freeze the
AnnaBridge	163:e59c8e839560	1828	* configuration of several capture/compare parameters.
AnnaBridge	163:e59c8e839560	1829	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	1830	* the lock mechanism is supported by a timer instance.
AnnaBridge	163:e59c8e839560	1831	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	163:e59c8e839560	1832	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1833	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1834	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	163:e59c8e839560	1835	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	163:e59c8e839560	1836	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	163:e59c8e839560	1837	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	163:e59c8e839560	1838	* @retval None
AnnaBridge	163:e59c8e839560	1839	*/
AnnaBridge	163:e59c8e839560	1840	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	163:e59c8e839560	1841	{
AnnaBridge	163:e59c8e839560	1842	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	163:e59c8e839560	1843	}
AnnaBridge	163:e59c8e839560	1844
AnnaBridge	163:e59c8e839560	1845	/**
AnnaBridge	163:e59c8e839560	1846	* @brief Enable capture/compare channels.
AnnaBridge	163:e59c8e839560	1847	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1848	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1849	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1850	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1851	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1852	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1853	* CCER CC4E LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1854	* CCER CC5E LL_TIM_CC_EnableChannel\n
AnnaBridge	163:e59c8e839560	1855	* CCER CC6E LL_TIM_CC_EnableChannel
AnnaBridge	163:e59c8e839560	1856	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1857	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	163:e59c8e839560	1858	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	1859	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	1860	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	1861	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	1862	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	1863	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	1864	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	1865	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	1866	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	1867	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	1868	* @retval None
AnnaBridge	163:e59c8e839560	1869	*/
AnnaBridge	163:e59c8e839560	1870	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	163:e59c8e839560	1871	{
AnnaBridge	163:e59c8e839560	1872	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	163:e59c8e839560	1873	}
AnnaBridge	163:e59c8e839560	1874
AnnaBridge	163:e59c8e839560	1875	/**
AnnaBridge	163:e59c8e839560	1876	* @brief Disable capture/compare channels.
AnnaBridge	163:e59c8e839560	1877	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1878	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1879	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1880	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1881	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1882	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1883	* CCER CC4E LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1884	* CCER CC5E LL_TIM_CC_DisableChannel\n
AnnaBridge	163:e59c8e839560	1885	* CCER CC6E LL_TIM_CC_DisableChannel
AnnaBridge	163:e59c8e839560	1886	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1887	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	163:e59c8e839560	1888	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	1889	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	1890	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	1891	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	1892	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	1893	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	1894	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	1895	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	1896	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	1897	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	1898	* @retval None
AnnaBridge	163:e59c8e839560	1899	*/
AnnaBridge	163:e59c8e839560	1900	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	163:e59c8e839560	1901	{
AnnaBridge	163:e59c8e839560	1902	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	163:e59c8e839560	1903	}
AnnaBridge	163:e59c8e839560	1904
AnnaBridge	163:e59c8e839560	1905	/**
AnnaBridge	163:e59c8e839560	1906	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	163:e59c8e839560	1907	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1908	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1909	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1910	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1911	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1912	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1913	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1914	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	163:e59c8e839560	1915	* CCER CC6E LL_TIM_CC_IsEnabledChannel
AnnaBridge	163:e59c8e839560	1916	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1917	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	163:e59c8e839560	1918	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	1919	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	1920	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	1921	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	1922	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	1923	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	1924	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	1925	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	1926	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	1927	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	1928	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1929	*/
AnnaBridge	163:e59c8e839560	1930	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	163:e59c8e839560	1931	{
AnnaBridge	163:e59c8e839560	1932	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	163:e59c8e839560	1933	}
AnnaBridge	163:e59c8e839560	1934
AnnaBridge	163:e59c8e839560	1935	/**
AnnaBridge	163:e59c8e839560	1936	* @}
AnnaBridge	163:e59c8e839560	1937	*/
AnnaBridge	163:e59c8e839560	1938
AnnaBridge	163:e59c8e839560	1939	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	163:e59c8e839560	1940	* @{
AnnaBridge	163:e59c8e839560	1941	*/
AnnaBridge	163:e59c8e839560	1942	/**
AnnaBridge	163:e59c8e839560	1943	* @brief Configure an output channel.
AnnaBridge	163:e59c8e839560	1944	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1945	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1946	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1947	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1948	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	1949	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1950	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1951	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	1952	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1953	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1954	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	1955	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1956	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1957	* @endif
AnnaBridge	163:e59c8e839560	1958	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1959	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1960	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1961	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1962	* CCER CC5P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1963	* CCER CC6P LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1964	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1965	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1966	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1967	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1968	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
AnnaBridge	163:e59c8e839560	1969	* CR2 OIS6 LL_TIM_OC_ConfigOutput
AnnaBridge	163:e59c8e839560	1970	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	1971	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1972	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	1973	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	1974	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	1975	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	1976	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	1977	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	1978	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	163:e59c8e839560	1979	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	163:e59c8e839560	1980	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	163:e59c8e839560	1981	* @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	1982	* @retval None
AnnaBridge	163:e59c8e839560	1983	*/
AnnaBridge	163:e59c8e839560	1984	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	163:e59c8e839560	1985	{
AnnaBridge	163:e59c8e839560	1986	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	1987	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	1988	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	1989	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	163:e59c8e839560	1990	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	1991	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	163:e59c8e839560	1992	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	163:e59c8e839560	1993	}
AnnaBridge	163:e59c8e839560	1994
AnnaBridge	163:e59c8e839560	1995	/**
AnnaBridge	163:e59c8e839560	1996	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	163:e59c8e839560	1997	* OCx and OCxN (when relevant) are derived.
AnnaBridge	163:e59c8e839560	1998	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	1999	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2000	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2001	* CCMR2 OC4M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2002	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2003	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2004	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	163:e59c8e839560	2005	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2006	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2007	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	163:e59c8e839560	2008	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2009	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	163:e59c8e839560	2010	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	163:e59c8e839560	2011	* @endif
AnnaBridge	163:e59c8e839560	2012	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2013	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2014	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2015	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2016	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2017	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2018	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2019	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2020	* @param Mode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2021	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	163:e59c8e839560	2022	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	163:e59c8e839560	2023	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	163:e59c8e839560	2024	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	163:e59c8e839560	2025	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	163:e59c8e839560	2026	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	163:e59c8e839560	2027	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	163:e59c8e839560	2028	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	163:e59c8e839560	2029	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	163:e59c8e839560	2030	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	163:e59c8e839560	2031	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	163:e59c8e839560	2032	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	163:e59c8e839560	2033	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	163:e59c8e839560	2034	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	163:e59c8e839560	2035	* @note The following OC modes are not available on all F3 devices :
AnnaBridge	163:e59c8e839560	2036	* - LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	163:e59c8e839560	2037	* - LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	163:e59c8e839560	2038	* - LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	163:e59c8e839560	2039	* - LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	163:e59c8e839560	2040	* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	163:e59c8e839560	2041	* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	163:e59c8e839560	2042	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2043	* @retval None
AnnaBridge	163:e59c8e839560	2044	*/
AnnaBridge	163:e59c8e839560	2045	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	163:e59c8e839560	2046	{
AnnaBridge	163:e59c8e839560	2047	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2048	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2049	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	163:e59c8e839560	2050	}
AnnaBridge	163:e59c8e839560	2051
AnnaBridge	163:e59c8e839560	2052	/**
AnnaBridge	163:e59c8e839560	2053	* @brief Get the output compare mode of an output channel.
AnnaBridge	163:e59c8e839560	2054	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2055	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2056	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2057	* CCMR2 OC4M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2058	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2059	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2060	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	163:e59c8e839560	2061	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2062	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2063	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	163:e59c8e839560	2064	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2065	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	163:e59c8e839560	2066	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	163:e59c8e839560	2067	* @endif
AnnaBridge	163:e59c8e839560	2068	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2069	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2070	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2071	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2072	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2073	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2074	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2075	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2076	* @note The following OC modes are not available on all F3 devices :
AnnaBridge	163:e59c8e839560	2077	* - LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	163:e59c8e839560	2078	* - LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	163:e59c8e839560	2079	* - LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	163:e59c8e839560	2080	* - LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	163:e59c8e839560	2081	* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	163:e59c8e839560	2082	* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	163:e59c8e839560	2083	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2084	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	2085	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	163:e59c8e839560	2086	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	163:e59c8e839560	2087	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	163:e59c8e839560	2088	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	163:e59c8e839560	2089	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	163:e59c8e839560	2090	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	163:e59c8e839560	2091	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	163:e59c8e839560	2092	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	163:e59c8e839560	2093	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	163:e59c8e839560	2094	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	163:e59c8e839560	2095	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	163:e59c8e839560	2096	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	163:e59c8e839560	2097	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	163:e59c8e839560	2098	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	163:e59c8e839560	2099	*/
AnnaBridge	163:e59c8e839560	2100	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2101	{
AnnaBridge	163:e59c8e839560	2102	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2103	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2104	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	163:e59c8e839560	2105	}
AnnaBridge	163:e59c8e839560	2106
AnnaBridge	163:e59c8e839560	2107	/**
AnnaBridge	163:e59c8e839560	2108	* @brief Set the polarity of an output channel.
AnnaBridge	163:e59c8e839560	2109	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2110	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2111	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2112	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2113	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2114	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2115	* CCER CC4P LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2116	* CCER CC5P LL_TIM_OC_SetPolarity\n
AnnaBridge	163:e59c8e839560	2117	* CCER CC6P LL_TIM_OC_SetPolarity
AnnaBridge	163:e59c8e839560	2118	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2119	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2120	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2121	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	2122	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2123	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	2124	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2125	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	2126	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2127	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2128	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2129	* @param Polarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2130	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	163:e59c8e839560	2131	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	163:e59c8e839560	2132	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2133	* @retval None
AnnaBridge	163:e59c8e839560	2134	*/
AnnaBridge	163:e59c8e839560	2135	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	163:e59c8e839560	2136	{
AnnaBridge	163:e59c8e839560	2137	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2138	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	2139	}
AnnaBridge	163:e59c8e839560	2140
AnnaBridge	163:e59c8e839560	2141	/**
AnnaBridge	163:e59c8e839560	2142	* @brief Get the polarity of an output channel.
AnnaBridge	163:e59c8e839560	2143	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2144	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2145	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2146	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2147	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2148	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2149	* CCER CC4P LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2150	* CCER CC5P LL_TIM_OC_GetPolarity\n
AnnaBridge	163:e59c8e839560	2151	* CCER CC6P LL_TIM_OC_GetPolarity
AnnaBridge	163:e59c8e839560	2152	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2153	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2154	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2155	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	2156	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2157	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	2158	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2159	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	2160	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2161	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2162	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2163	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2164	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	2165	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	163:e59c8e839560	2166	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	163:e59c8e839560	2167	*/
AnnaBridge	163:e59c8e839560	2168	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2169	{
AnnaBridge	163:e59c8e839560	2170	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2171	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	2172	}
AnnaBridge	163:e59c8e839560	2173
AnnaBridge	163:e59c8e839560	2174	/**
AnnaBridge	163:e59c8e839560	2175	* @brief Set the IDLE state of an output channel
AnnaBridge	163:e59c8e839560	2176	* @note This function is significant only for the timer instances
AnnaBridge	163:e59c8e839560	2177	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	163:e59c8e839560	2178	* can be used to check whether or not a timer instance provides
AnnaBridge	163:e59c8e839560	2179	* a break input.
AnnaBridge	163:e59c8e839560	2180	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2181	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2182	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2183	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2184	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2185	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2186	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2187	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
AnnaBridge	163:e59c8e839560	2188	* CR2 OIS6 LL_TIM_OC_SetIdleState
AnnaBridge	163:e59c8e839560	2189	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2190	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2191	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2192	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	2193	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2194	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	2195	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2196	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	2197	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2198	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2199	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2200	* @param IdleState This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2201	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	163:e59c8e839560	2202	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	163:e59c8e839560	2203	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2204	* @retval None
AnnaBridge	163:e59c8e839560	2205	*/
AnnaBridge	163:e59c8e839560	2206	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	163:e59c8e839560	2207	{
AnnaBridge	163:e59c8e839560	2208	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2209	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	163:e59c8e839560	2210	}
AnnaBridge	163:e59c8e839560	2211
AnnaBridge	163:e59c8e839560	2212	/**
AnnaBridge	163:e59c8e839560	2213	* @brief Get the IDLE state of an output channel
AnnaBridge	163:e59c8e839560	2214	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2215	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2216	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2217	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2218	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2219	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2220	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2221	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
AnnaBridge	163:e59c8e839560	2222	* CR2 OIS6 LL_TIM_OC_GetIdleState
AnnaBridge	163:e59c8e839560	2223	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2224	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2225	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2226	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	163:e59c8e839560	2227	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2228	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	163:e59c8e839560	2229	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2230	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	163:e59c8e839560	2231	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2232	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2233	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2234	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2235	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	2236	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	163:e59c8e839560	2237	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	163:e59c8e839560	2238	*/
AnnaBridge	163:e59c8e839560	2239	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2240	{
AnnaBridge	163:e59c8e839560	2241	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2242	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	163:e59c8e839560	2243	}
AnnaBridge	163:e59c8e839560	2244
AnnaBridge	163:e59c8e839560	2245	/**
AnnaBridge	163:e59c8e839560	2246	* @brief Enable fast mode for the output channel.
AnnaBridge	163:e59c8e839560	2247	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	163:e59c8e839560	2248	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2249	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2250	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2251	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2252	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2253	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2254	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	163:e59c8e839560	2255	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2256	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2257	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	163:e59c8e839560	2258	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2259	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	163:e59c8e839560	2260	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	163:e59c8e839560	2261	* @endif
AnnaBridge	163:e59c8e839560	2262	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2263	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2264	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2265	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2266	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2267	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2268	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2269	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2270	* @note OC5FE and OC6FE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2271	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2272	* @retval None
AnnaBridge	163:e59c8e839560	2273	*/
AnnaBridge	163:e59c8e839560	2274	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2275	{
AnnaBridge	163:e59c8e839560	2276	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2277	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2278	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2279
AnnaBridge	163:e59c8e839560	2280	}
AnnaBridge	163:e59c8e839560	2281
AnnaBridge	163:e59c8e839560	2282	/**
AnnaBridge	163:e59c8e839560	2283	* @brief Disable fast mode for the output channel.
AnnaBridge	163:e59c8e839560	2284	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2285	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2286	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2287	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2288	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2289	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2290	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	163:e59c8e839560	2291	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2292	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2293	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	163:e59c8e839560	2294	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2295	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2296	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	163:e59c8e839560	2297	* @endif
AnnaBridge	163:e59c8e839560	2298	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2299	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2300	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2301	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2302	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2303	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2304	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2305	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2306	* @note OC5FE and OC6FE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2307	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2308	* @retval None
AnnaBridge	163:e59c8e839560	2309	*/
AnnaBridge	163:e59c8e839560	2310	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2311	{
AnnaBridge	163:e59c8e839560	2312	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2313	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2314	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2315
AnnaBridge	163:e59c8e839560	2316	}
AnnaBridge	163:e59c8e839560	2317
AnnaBridge	163:e59c8e839560	2318	/**
AnnaBridge	163:e59c8e839560	2319	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	163:e59c8e839560	2320	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2321	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2322	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2323	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2324	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2325	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2326	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
AnnaBridge	163:e59c8e839560	2327	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2328	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	163:e59c8e839560	2329	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
AnnaBridge	163:e59c8e839560	2330	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2331	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	163:e59c8e839560	2332	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	163:e59c8e839560	2333	* @endif
AnnaBridge	163:e59c8e839560	2334	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2335	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2336	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2337	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2338	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2339	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2340	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2341	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2342	* @note OC5FE and OC6FE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2343	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2344	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2345	*/
AnnaBridge	163:e59c8e839560	2346	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2347	{
AnnaBridge	163:e59c8e839560	2348	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2349	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2350	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	163:e59c8e839560	2351	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	163:e59c8e839560	2352	}
AnnaBridge	163:e59c8e839560	2353
AnnaBridge	163:e59c8e839560	2354	/**
AnnaBridge	163:e59c8e839560	2355	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	163:e59c8e839560	2356	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2357	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2358	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2359	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2360	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2361	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2362	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	163:e59c8e839560	2363	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2364	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2365	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	163:e59c8e839560	2366	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2367	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	163:e59c8e839560	2368	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	163:e59c8e839560	2369	* @endif
AnnaBridge	163:e59c8e839560	2370	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2371	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2372	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2373	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2374	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2375	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2376	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2377	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2378	* @note OC5PE and OC6PE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2379	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2380	* @retval None
AnnaBridge	163:e59c8e839560	2381	*/
AnnaBridge	163:e59c8e839560	2382	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2383	{
AnnaBridge	163:e59c8e839560	2384	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2385	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2386	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2387	}
AnnaBridge	163:e59c8e839560	2388
AnnaBridge	163:e59c8e839560	2389	/**
AnnaBridge	163:e59c8e839560	2390	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	163:e59c8e839560	2391	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2392	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2393	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2394	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2395	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2396	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2397	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	163:e59c8e839560	2398	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2399	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2400	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	163:e59c8e839560	2401	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2402	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	163:e59c8e839560	2403	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	163:e59c8e839560	2404	* @endif
AnnaBridge	163:e59c8e839560	2405	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2406	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2407	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2408	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2409	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2410	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2411	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2412	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2413	* @note OC5PE and OC6PE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2414	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2415	* @retval None
AnnaBridge	163:e59c8e839560	2416	*/
AnnaBridge	163:e59c8e839560	2417	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2418	{
AnnaBridge	163:e59c8e839560	2419	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2420	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2421	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2422	}
AnnaBridge	163:e59c8e839560	2423
AnnaBridge	163:e59c8e839560	2424	/**
AnnaBridge	163:e59c8e839560	2425	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	163:e59c8e839560	2426	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2427	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2428	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2429	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2430	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2431	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2432	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	163:e59c8e839560	2433	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2434	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2435	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	163:e59c8e839560	2436	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2437	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	163:e59c8e839560	2438	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	163:e59c8e839560	2439	* @endif
AnnaBridge	163:e59c8e839560	2440	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2441	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2442	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2443	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2444	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2445	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2446	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2447	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2448	* @note OC5PE and OC6PE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2449	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2450	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2451	*/
AnnaBridge	163:e59c8e839560	2452	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2453	{
AnnaBridge	163:e59c8e839560	2454	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2455	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2456	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	163:e59c8e839560	2457	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	163:e59c8e839560	2458	}
AnnaBridge	163:e59c8e839560	2459
AnnaBridge	163:e59c8e839560	2460	/**
AnnaBridge	163:e59c8e839560	2461	* @brief Enable clearing the output channel on an external event.
AnnaBridge	163:e59c8e839560	2462	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	163:e59c8e839560	2463	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	163:e59c8e839560	2464	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	163:e59c8e839560	2465	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2466	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2467	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2468	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2469	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2470	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2471	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	163:e59c8e839560	2472	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2473	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2474	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	163:e59c8e839560	2475	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2476	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	163:e59c8e839560	2477	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	163:e59c8e839560	2478	* @endif
AnnaBridge	163:e59c8e839560	2479	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2480	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2481	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2482	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2483	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2484	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2485	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2486	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2487	* @note OC5CE and OC6CE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2488	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2489	* @retval None
AnnaBridge	163:e59c8e839560	2490	*/
AnnaBridge	163:e59c8e839560	2491	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2492	{
AnnaBridge	163:e59c8e839560	2493	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2494	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2495	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2496	}
AnnaBridge	163:e59c8e839560	2497
AnnaBridge	163:e59c8e839560	2498	/**
AnnaBridge	163:e59c8e839560	2499	* @brief Disable clearing the output channel on an external event.
AnnaBridge	163:e59c8e839560	2500	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	163:e59c8e839560	2501	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	163:e59c8e839560	2502	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2503	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2504	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2505	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2506	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2507	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2508	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	163:e59c8e839560	2509	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2510	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2511	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	163:e59c8e839560	2512	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2513	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	163:e59c8e839560	2514	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	163:e59c8e839560	2515	* @endif
AnnaBridge	163:e59c8e839560	2516	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2517	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2518	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2519	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2520	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2521	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2522	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2523	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2524	* @note OC5CE and OC6CE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2525	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2526	* @retval None
AnnaBridge	163:e59c8e839560	2527	*/
AnnaBridge	163:e59c8e839560	2528	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2529	{
AnnaBridge	163:e59c8e839560	2530	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2531	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2532	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	163:e59c8e839560	2533	}
AnnaBridge	163:e59c8e839560	2534
AnnaBridge	163:e59c8e839560	2535	/**
AnnaBridge	163:e59c8e839560	2536	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	163:e59c8e839560	2537	* @note This function enables clearing the output channel on an external event.
AnnaBridge	163:e59c8e839560	2538	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	163:e59c8e839560	2539	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	163:e59c8e839560	2540	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	163:e59c8e839560	2541	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2542	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2543	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2544	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2545	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2546	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2547	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	163:e59c8e839560	2548	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2549	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2550	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	163:e59c8e839560	2551	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2552	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	163:e59c8e839560	2553	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	163:e59c8e839560	2554	* @endif
AnnaBridge	163:e59c8e839560	2555	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2556	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2557	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2558	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2559	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2560	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2561	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	163:e59c8e839560	2562	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	163:e59c8e839560	2563	* @note OC5CE and OC6CE are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2564	* @note CH5 and CH6 channels are not available for all F3 devices
AnnaBridge	163:e59c8e839560	2565	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2566	*/
AnnaBridge	163:e59c8e839560	2567	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2568	{
AnnaBridge	163:e59c8e839560	2569	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2570	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2571	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	163:e59c8e839560	2572	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	163:e59c8e839560	2573	}
AnnaBridge	163:e59c8e839560	2574
AnnaBridge	163:e59c8e839560	2575	/**
AnnaBridge	163:e59c8e839560	2576	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
AnnaBridge	163:e59c8e839560	2577	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2578	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2579	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	163:e59c8e839560	2580	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	163:e59c8e839560	2581	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2582	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	163:e59c8e839560	2583	* @retval None
AnnaBridge	163:e59c8e839560	2584	*/
AnnaBridge	163:e59c8e839560	2585	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	163:e59c8e839560	2586	{
AnnaBridge	163:e59c8e839560	2587	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	163:e59c8e839560	2588	}
AnnaBridge	163:e59c8e839560	2589
AnnaBridge	163:e59c8e839560	2590	/**
AnnaBridge	163:e59c8e839560	2591	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	163:e59c8e839560	2592	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2593	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2594	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2595	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2596	* output channel 1 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2597	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	163:e59c8e839560	2598	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2599	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2600	* @retval None
AnnaBridge	163:e59c8e839560	2601	*/
AnnaBridge	163:e59c8e839560	2602	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2603	{
AnnaBridge	163:e59c8e839560	2604	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	163:e59c8e839560	2605	}
AnnaBridge	163:e59c8e839560	2606
AnnaBridge	163:e59c8e839560	2607	/**
AnnaBridge	163:e59c8e839560	2608	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	163:e59c8e839560	2609	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2610	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2611	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2612	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2613	* output channel 2 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2614	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	163:e59c8e839560	2615	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2616	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2617	* @retval None
AnnaBridge	163:e59c8e839560	2618	*/
AnnaBridge	163:e59c8e839560	2619	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2620	{
AnnaBridge	163:e59c8e839560	2621	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	163:e59c8e839560	2622	}
AnnaBridge	163:e59c8e839560	2623
AnnaBridge	163:e59c8e839560	2624	/**
AnnaBridge	163:e59c8e839560	2625	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	163:e59c8e839560	2626	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2627	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2628	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2629	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2630	* output channel is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2631	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	163:e59c8e839560	2632	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2633	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2634	* @retval None
AnnaBridge	163:e59c8e839560	2635	*/
AnnaBridge	163:e59c8e839560	2636	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2637	{
AnnaBridge	163:e59c8e839560	2638	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	163:e59c8e839560	2639	}
AnnaBridge	163:e59c8e839560	2640
AnnaBridge	163:e59c8e839560	2641	/**
AnnaBridge	163:e59c8e839560	2642	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	163:e59c8e839560	2643	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2644	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2645	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2646	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2647	* output channel 4 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2648	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	163:e59c8e839560	2649	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2650	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2651	* @retval None
AnnaBridge	163:e59c8e839560	2652	*/
AnnaBridge	163:e59c8e839560	2653	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2654	{
AnnaBridge	163:e59c8e839560	2655	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	163:e59c8e839560	2656	}
AnnaBridge	163:e59c8e839560	2657
AnnaBridge	163:e59c8e839560	2658	#if defined(TIM_CCR5_CCR5)
AnnaBridge	163:e59c8e839560	2659	/**
AnnaBridge	163:e59c8e839560	2660	* @brief Set compare value for output channel 5 (TIMx_CCR5).
AnnaBridge	163:e59c8e839560	2661	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2662	* output channel 5 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2663	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2664	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	163:e59c8e839560	2665	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2666	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	163:e59c8e839560	2667	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2668	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	163:e59c8e839560	2669	* @endif
AnnaBridge	163:e59c8e839560	2670	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2671	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2672	* @note CH5 channel is not available for all F3 devices
AnnaBridge	163:e59c8e839560	2673	* @retval None
AnnaBridge	163:e59c8e839560	2674	*/
AnnaBridge	163:e59c8e839560	2675	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2676	{
AnnaBridge	163:e59c8e839560	2677	WRITE_REG(TIMx->CCR5, CompareValue);
AnnaBridge	163:e59c8e839560	2678	}
AnnaBridge	163:e59c8e839560	2679
AnnaBridge	163:e59c8e839560	2680	#endif /* TIM_CCR5_CCR5 */
AnnaBridge	163:e59c8e839560	2681	#if defined(TIM_CCR6_CCR6)
AnnaBridge	163:e59c8e839560	2682	/**
AnnaBridge	163:e59c8e839560	2683	* @brief Set compare value for output channel 6 (TIMx_CCR6).
AnnaBridge	163:e59c8e839560	2684	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2685	* output channel 6 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2686	* @if STM32F344x8
AnnaBridge	163:e59c8e839560	2687	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	163:e59c8e839560	2688	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2689	* CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	163:e59c8e839560	2690	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2691	* CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	163:e59c8e839560	2692	* @endif
AnnaBridge	163:e59c8e839560	2693	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2694	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	163:e59c8e839560	2695	* @note CH6 channel is not available for all F3 devices
AnnaBridge	163:e59c8e839560	2696	* @retval None
AnnaBridge	163:e59c8e839560	2697	*/
AnnaBridge	163:e59c8e839560	2698	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	163:e59c8e839560	2699	{
AnnaBridge	163:e59c8e839560	2700	WRITE_REG(TIMx->CCR6, CompareValue);
AnnaBridge	163:e59c8e839560	2701	}
AnnaBridge	163:e59c8e839560	2702
AnnaBridge	163:e59c8e839560	2703	#endif /* TIM_CCR6_CCR6 */
AnnaBridge	163:e59c8e839560	2704	/**
AnnaBridge	163:e59c8e839560	2705	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	163:e59c8e839560	2706	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2707	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2708	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2709	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2710	* output channel 1 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2711	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	163:e59c8e839560	2712	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2713	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2714	*/
AnnaBridge	163:e59c8e839560	2715	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2716	{
AnnaBridge	163:e59c8e839560	2717	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	163:e59c8e839560	2718	}
AnnaBridge	163:e59c8e839560	2719
AnnaBridge	163:e59c8e839560	2720	/**
AnnaBridge	163:e59c8e839560	2721	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	163:e59c8e839560	2722	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2723	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2724	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2725	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2726	* output channel 2 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2727	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	163:e59c8e839560	2728	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2729	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2730	*/
AnnaBridge	163:e59c8e839560	2731	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2732	{
AnnaBridge	163:e59c8e839560	2733	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	163:e59c8e839560	2734	}
AnnaBridge	163:e59c8e839560	2735
AnnaBridge	163:e59c8e839560	2736	/**
AnnaBridge	163:e59c8e839560	2737	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	163:e59c8e839560	2738	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2739	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2740	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2741	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2742	* output channel 3 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2743	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	163:e59c8e839560	2744	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2745	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2746	*/
AnnaBridge	163:e59c8e839560	2747	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2748	{
AnnaBridge	163:e59c8e839560	2749	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	163:e59c8e839560	2750	}
AnnaBridge	163:e59c8e839560	2751
AnnaBridge	163:e59c8e839560	2752	/**
AnnaBridge	163:e59c8e839560	2753	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	163:e59c8e839560	2754	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	2755	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2756	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	2757	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2758	* output channel 4 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2759	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	163:e59c8e839560	2760	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2761	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2762	*/
AnnaBridge	163:e59c8e839560	2763	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2764	{
AnnaBridge	163:e59c8e839560	2765	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	163:e59c8e839560	2766	}
AnnaBridge	163:e59c8e839560	2767
AnnaBridge	163:e59c8e839560	2768	#if defined(TIM_CCR5_CCR5)
AnnaBridge	163:e59c8e839560	2769	/**
AnnaBridge	163:e59c8e839560	2770	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
AnnaBridge	163:e59c8e839560	2771	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2772	* output channel 5 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2773	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2774	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	163:e59c8e839560	2775	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2776	* CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	163:e59c8e839560	2777	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2778	* CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	163:e59c8e839560	2779	* @endif
AnnaBridge	163:e59c8e839560	2780	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2781	* @note CH5 channel is not available for all F3 devices
AnnaBridge	163:e59c8e839560	2782	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2783	*/
AnnaBridge	163:e59c8e839560	2784	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2785	{
AnnaBridge	163:e59c8e839560	2786	return (uint32_t)(READ_REG(TIMx->CCR5));
AnnaBridge	163:e59c8e839560	2787	}
AnnaBridge	163:e59c8e839560	2788
AnnaBridge	163:e59c8e839560	2789	#endif /* TIM_CCR5_CCR5 */
AnnaBridge	163:e59c8e839560	2790	#if defined(TIM_CCR6_CCR6)
AnnaBridge	163:e59c8e839560	2791	/**
AnnaBridge	163:e59c8e839560	2792	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
AnnaBridge	163:e59c8e839560	2793	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	2794	* output channel 6 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	2795	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2796	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	163:e59c8e839560	2797	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2798	* CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	163:e59c8e839560	2799	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2800	* CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	163:e59c8e839560	2801	* @endif
AnnaBridge	163:e59c8e839560	2802	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2803	* @note CH6 channel is not available for all F3 devices
AnnaBridge	163:e59c8e839560	2804	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	2805	*/
AnnaBridge	163:e59c8e839560	2806	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	2807	{
AnnaBridge	163:e59c8e839560	2808	return (uint32_t)(READ_REG(TIMx->CCR6));
AnnaBridge	163:e59c8e839560	2809	}
AnnaBridge	163:e59c8e839560	2810
AnnaBridge	163:e59c8e839560	2811	#endif /* TIM_CCR6_CCR6 */
AnnaBridge	163:e59c8e839560	2812	#if defined(TIM_CCR5_CCR5)
AnnaBridge	163:e59c8e839560	2813	/**
AnnaBridge	163:e59c8e839560	2814	* @brief Select on which reference signal the OC5REF is combined to.
AnnaBridge	163:e59c8e839560	2815	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	2816	* whether or not a timer instance supports the combined 3-phase PWM mode.
AnnaBridge	163:e59c8e839560	2817	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	2818	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2819	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2820	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	163:e59c8e839560	2821	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	2822	* CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2823	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2824	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	163:e59c8e839560	2825	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	2826	* CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2827	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	163:e59c8e839560	2828	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	163:e59c8e839560	2829	* @endif
AnnaBridge	163:e59c8e839560	2830	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2831	* @param GroupCH5 This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2832	* @arg @ref LL_TIM_GROUPCH5_NONE
AnnaBridge	163:e59c8e839560	2833	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
AnnaBridge	163:e59c8e839560	2834	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
AnnaBridge	163:e59c8e839560	2835	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
AnnaBridge	163:e59c8e839560	2836	* @note CH5 channel is not available for all F3 devices
AnnaBridge	163:e59c8e839560	2837	* @retval None
AnnaBridge	163:e59c8e839560	2838	*/
AnnaBridge	163:e59c8e839560	2839	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
AnnaBridge	163:e59c8e839560	2840	{
AnnaBridge	163:e59c8e839560	2841	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
AnnaBridge	163:e59c8e839560	2842	}
AnnaBridge	163:e59c8e839560	2843
AnnaBridge	163:e59c8e839560	2844	#endif /* TIM_CCR5_CCR5 */
AnnaBridge	163:e59c8e839560	2845	/**
AnnaBridge	163:e59c8e839560	2846	* @}
AnnaBridge	163:e59c8e839560	2847	*/
AnnaBridge	163:e59c8e839560	2848
AnnaBridge	163:e59c8e839560	2849	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	163:e59c8e839560	2850	* @{
AnnaBridge	163:e59c8e839560	2851	*/
AnnaBridge	163:e59c8e839560	2852	/**
AnnaBridge	163:e59c8e839560	2853	* @brief Configure input channel.
AnnaBridge	163:e59c8e839560	2854	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2855	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2856	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2857	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2858	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2859	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2860	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2861	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2862	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2863	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2864	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2865	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2866	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2867	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2868	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2869	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2870	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2871	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2872	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	163:e59c8e839560	2873	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	163:e59c8e839560	2874	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2875	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2876	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2877	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2878	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2879	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2880	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	163:e59c8e839560	2881	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	163:e59c8e839560	2882	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	163:e59c8e839560	2883	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	2884	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	163:e59c8e839560	2885	* @retval None
AnnaBridge	163:e59c8e839560	2886	*/
AnnaBridge	163:e59c8e839560	2887	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	163:e59c8e839560	2888	{
AnnaBridge	163:e59c8e839560	2889	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2890	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2891	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	163:e59c8e839560	2892	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	163:e59c8e839560	2893	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	163:e59c8e839560	2894	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	2895	}
AnnaBridge	163:e59c8e839560	2896
AnnaBridge	163:e59c8e839560	2897	/**
AnnaBridge	163:e59c8e839560	2898	* @brief Set the active input.
AnnaBridge	163:e59c8e839560	2899	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	163:e59c8e839560	2900	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	163:e59c8e839560	2901	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	163:e59c8e839560	2902	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	163:e59c8e839560	2903	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2904	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2905	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2906	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2907	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2908	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2909	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2910	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	163:e59c8e839560	2911	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	163:e59c8e839560	2912	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	163:e59c8e839560	2913	* @retval None
AnnaBridge	163:e59c8e839560	2914	*/
AnnaBridge	163:e59c8e839560	2915	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	163:e59c8e839560	2916	{
AnnaBridge	163:e59c8e839560	2917	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2918	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2919	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	163:e59c8e839560	2920	}
AnnaBridge	163:e59c8e839560	2921
AnnaBridge	163:e59c8e839560	2922	/**
AnnaBridge	163:e59c8e839560	2923	* @brief Get the current active input.
AnnaBridge	163:e59c8e839560	2924	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	163:e59c8e839560	2925	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	163:e59c8e839560	2926	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	163:e59c8e839560	2927	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	163:e59c8e839560	2928	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2929	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2930	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2931	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2932	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2933	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2934	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	2935	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	163:e59c8e839560	2936	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	163:e59c8e839560	2937	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	163:e59c8e839560	2938	*/
AnnaBridge	163:e59c8e839560	2939	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2940	{
AnnaBridge	163:e59c8e839560	2941	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2942	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2943	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	163:e59c8e839560	2944	}
AnnaBridge	163:e59c8e839560	2945
AnnaBridge	163:e59c8e839560	2946	/**
AnnaBridge	163:e59c8e839560	2947	* @brief Set the prescaler of input channel.
AnnaBridge	163:e59c8e839560	2948	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	163:e59c8e839560	2949	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	163:e59c8e839560	2950	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	163:e59c8e839560	2951	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	163:e59c8e839560	2952	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2953	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2954	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2955	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2956	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2957	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2958	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2959	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	163:e59c8e839560	2960	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	163:e59c8e839560	2961	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	163:e59c8e839560	2962	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	163:e59c8e839560	2963	* @retval None
AnnaBridge	163:e59c8e839560	2964	*/
AnnaBridge	163:e59c8e839560	2965	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	163:e59c8e839560	2966	{
AnnaBridge	163:e59c8e839560	2967	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2968	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2969	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	163:e59c8e839560	2970	}
AnnaBridge	163:e59c8e839560	2971
AnnaBridge	163:e59c8e839560	2972	/**
AnnaBridge	163:e59c8e839560	2973	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	163:e59c8e839560	2974	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	163:e59c8e839560	2975	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	163:e59c8e839560	2976	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	163:e59c8e839560	2977	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	163:e59c8e839560	2978	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	2979	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2980	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	2981	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	2982	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	2983	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	2984	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	2985	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	163:e59c8e839560	2986	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	163:e59c8e839560	2987	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	163:e59c8e839560	2988	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	163:e59c8e839560	2989	*/
AnnaBridge	163:e59c8e839560	2990	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	2991	{
AnnaBridge	163:e59c8e839560	2992	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	2993	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	2994	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	163:e59c8e839560	2995	}
AnnaBridge	163:e59c8e839560	2996
AnnaBridge	163:e59c8e839560	2997	/**
AnnaBridge	163:e59c8e839560	2998	* @brief Set the input filter duration.
AnnaBridge	163:e59c8e839560	2999	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	163:e59c8e839560	3000	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	163:e59c8e839560	3001	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	163:e59c8e839560	3002	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	163:e59c8e839560	3003	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3004	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3005	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	3006	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	3007	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	3008	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	3009	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3010	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	163:e59c8e839560	3011	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	163:e59c8e839560	3012	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	163:e59c8e839560	3013	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	163:e59c8e839560	3014	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	163:e59c8e839560	3015	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	163:e59c8e839560	3016	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	163:e59c8e839560	3017	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	163:e59c8e839560	3018	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	163:e59c8e839560	3019	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	163:e59c8e839560	3020	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	163:e59c8e839560	3021	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	163:e59c8e839560	3022	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	163:e59c8e839560	3023	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	163:e59c8e839560	3024	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	163:e59c8e839560	3025	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	3026	* @retval None
AnnaBridge	163:e59c8e839560	3027	*/
AnnaBridge	163:e59c8e839560	3028	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	163:e59c8e839560	3029	{
AnnaBridge	163:e59c8e839560	3030	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	3031	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	3032	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	163:e59c8e839560	3033	}
AnnaBridge	163:e59c8e839560	3034
AnnaBridge	163:e59c8e839560	3035	/**
AnnaBridge	163:e59c8e839560	3036	* @brief Get the input filter duration.
AnnaBridge	163:e59c8e839560	3037	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	163:e59c8e839560	3038	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	163:e59c8e839560	3039	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	163:e59c8e839560	3040	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	163:e59c8e839560	3041	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3042	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3043	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	3044	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	3045	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	3046	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	3047	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	3048	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	163:e59c8e839560	3049	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	163:e59c8e839560	3050	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	163:e59c8e839560	3051	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	163:e59c8e839560	3052	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	163:e59c8e839560	3053	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	163:e59c8e839560	3054	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	163:e59c8e839560	3055	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	163:e59c8e839560	3056	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	163:e59c8e839560	3057	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	163:e59c8e839560	3058	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	163:e59c8e839560	3059	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	163:e59c8e839560	3060	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	163:e59c8e839560	3061	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	163:e59c8e839560	3062	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	163:e59c8e839560	3063	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	3064	*/
AnnaBridge	163:e59c8e839560	3065	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	3066	{
AnnaBridge	163:e59c8e839560	3067	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	3068	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	163:e59c8e839560	3069	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	163:e59c8e839560	3070	}
AnnaBridge	163:e59c8e839560	3071
AnnaBridge	163:e59c8e839560	3072	/**
AnnaBridge	163:e59c8e839560	3073	* @brief Set the input channel polarity.
AnnaBridge	163:e59c8e839560	3074	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3075	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3076	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3077	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3078	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3079	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3080	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	163:e59c8e839560	3081	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	163:e59c8e839560	3082	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3083	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3084	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	3085	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	3086	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	3087	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	3088	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3089	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	163:e59c8e839560	3090	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	163:e59c8e839560	3091	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	163:e59c8e839560	3092	* @retval None
AnnaBridge	163:e59c8e839560	3093	*/
AnnaBridge	163:e59c8e839560	3094	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	163:e59c8e839560	3095	{
AnnaBridge	163:e59c8e839560	3096	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	3097	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	163:e59c8e839560	3098	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	3099	}
AnnaBridge	163:e59c8e839560	3100
AnnaBridge	163:e59c8e839560	3101	/**
AnnaBridge	163:e59c8e839560	3102	* @brief Get the current input channel polarity.
AnnaBridge	163:e59c8e839560	3103	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3104	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3105	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3106	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3107	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3108	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3109	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	163:e59c8e839560	3110	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	163:e59c8e839560	3111	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3112	* @param Channel This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3113	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	163:e59c8e839560	3114	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	163:e59c8e839560	3115	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	163:e59c8e839560	3116	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	163:e59c8e839560	3117	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	3118	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	163:e59c8e839560	3119	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	163:e59c8e839560	3120	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	163:e59c8e839560	3121	*/
AnnaBridge	163:e59c8e839560	3122	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	163:e59c8e839560	3123	{
AnnaBridge	163:e59c8e839560	3124	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	163:e59c8e839560	3125	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	163:e59c8e839560	3126	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	163:e59c8e839560	3127	}
AnnaBridge	163:e59c8e839560	3128
AnnaBridge	163:e59c8e839560	3129	/**
AnnaBridge	163:e59c8e839560	3130	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	163:e59c8e839560	3131	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3132	* a timer instance provides an XOR input.
AnnaBridge	163:e59c8e839560	3133	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	163:e59c8e839560	3134	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3135	* @retval None
AnnaBridge	163:e59c8e839560	3136	*/
AnnaBridge	163:e59c8e839560	3137	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3138	{
AnnaBridge	163:e59c8e839560	3139	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	163:e59c8e839560	3140	}
AnnaBridge	163:e59c8e839560	3141
AnnaBridge	163:e59c8e839560	3142	/**
AnnaBridge	163:e59c8e839560	3143	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	163:e59c8e839560	3144	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3145	* a timer instance provides an XOR input.
AnnaBridge	163:e59c8e839560	3146	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	163:e59c8e839560	3147	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3148	* @retval None
AnnaBridge	163:e59c8e839560	3149	*/
AnnaBridge	163:e59c8e839560	3150	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3151	{
AnnaBridge	163:e59c8e839560	3152	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	163:e59c8e839560	3153	}
AnnaBridge	163:e59c8e839560	3154
AnnaBridge	163:e59c8e839560	3155	/**
AnnaBridge	163:e59c8e839560	3156	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	163:e59c8e839560	3157	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3158	* a timer instance provides an XOR input.
AnnaBridge	163:e59c8e839560	3159	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	163:e59c8e839560	3160	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3161	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3162	*/
AnnaBridge	163:e59c8e839560	3163	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3164	{
AnnaBridge	163:e59c8e839560	3165	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	163:e59c8e839560	3166	}
AnnaBridge	163:e59c8e839560	3167
AnnaBridge	163:e59c8e839560	3168	/**
AnnaBridge	163:e59c8e839560	3169	* @brief Get captured value for input channel 1.
AnnaBridge	163:e59c8e839560	3170	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	3171	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3172	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	3173	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3174	* input channel 1 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	3175	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	163:e59c8e839560	3176	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3177	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	3178	*/
AnnaBridge	163:e59c8e839560	3179	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3180	{
AnnaBridge	163:e59c8e839560	3181	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	163:e59c8e839560	3182	}
AnnaBridge	163:e59c8e839560	3183
AnnaBridge	163:e59c8e839560	3184	/**
AnnaBridge	163:e59c8e839560	3185	* @brief Get captured value for input channel 2.
AnnaBridge	163:e59c8e839560	3186	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	3187	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3188	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	3189	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3190	* input channel 2 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	3191	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	163:e59c8e839560	3192	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3193	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	3194	*/
AnnaBridge	163:e59c8e839560	3195	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3196	{
AnnaBridge	163:e59c8e839560	3197	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	163:e59c8e839560	3198	}
AnnaBridge	163:e59c8e839560	3199
AnnaBridge	163:e59c8e839560	3200	/**
AnnaBridge	163:e59c8e839560	3201	* @brief Get captured value for input channel 3.
AnnaBridge	163:e59c8e839560	3202	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	3203	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3204	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	3205	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3206	* input channel 3 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	3207	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	163:e59c8e839560	3208	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3209	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	3210	*/
AnnaBridge	163:e59c8e839560	3211	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3212	{
AnnaBridge	163:e59c8e839560	3213	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	163:e59c8e839560	3214	}
AnnaBridge	163:e59c8e839560	3215
AnnaBridge	163:e59c8e839560	3216	/**
AnnaBridge	163:e59c8e839560	3217	* @brief Get captured value for input channel 4.
AnnaBridge	163:e59c8e839560	3218	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	163:e59c8e839560	3219	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3220	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	163:e59c8e839560	3221	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3222	* input channel 4 is supported by a timer instance.
AnnaBridge	163:e59c8e839560	3223	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	163:e59c8e839560	3224	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3225	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	163:e59c8e839560	3226	*/
AnnaBridge	163:e59c8e839560	3227	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3228	{
AnnaBridge	163:e59c8e839560	3229	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	163:e59c8e839560	3230	}
AnnaBridge	163:e59c8e839560	3231
AnnaBridge	163:e59c8e839560	3232	/**
AnnaBridge	163:e59c8e839560	3233	* @}
AnnaBridge	163:e59c8e839560	3234	*/
AnnaBridge	163:e59c8e839560	3235
AnnaBridge	163:e59c8e839560	3236	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	163:e59c8e839560	3237	* @{
AnnaBridge	163:e59c8e839560	3238	*/
AnnaBridge	163:e59c8e839560	3239	/**
AnnaBridge	163:e59c8e839560	3240	* @brief Enable external clock mode 2.
AnnaBridge	163:e59c8e839560	3241	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	163:e59c8e839560	3242	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3243	* whether or not a timer instance supports external clock mode2.
AnnaBridge	163:e59c8e839560	3244	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	163:e59c8e839560	3245	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3246	* @retval None
AnnaBridge	163:e59c8e839560	3247	*/
AnnaBridge	163:e59c8e839560	3248	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3249	{
AnnaBridge	163:e59c8e839560	3250	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	163:e59c8e839560	3251	}
AnnaBridge	163:e59c8e839560	3252
AnnaBridge	163:e59c8e839560	3253	/**
AnnaBridge	163:e59c8e839560	3254	* @brief Disable external clock mode 2.
AnnaBridge	163:e59c8e839560	3255	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3256	* whether or not a timer instance supports external clock mode2.
AnnaBridge	163:e59c8e839560	3257	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	163:e59c8e839560	3258	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3259	* @retval None
AnnaBridge	163:e59c8e839560	3260	*/
AnnaBridge	163:e59c8e839560	3261	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3262	{
AnnaBridge	163:e59c8e839560	3263	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	163:e59c8e839560	3264	}
AnnaBridge	163:e59c8e839560	3265
AnnaBridge	163:e59c8e839560	3266	/**
AnnaBridge	163:e59c8e839560	3267	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	163:e59c8e839560	3268	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3269	* whether or not a timer instance supports external clock mode2.
AnnaBridge	163:e59c8e839560	3270	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	163:e59c8e839560	3271	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3272	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3273	*/
AnnaBridge	163:e59c8e839560	3274	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3275	{
AnnaBridge	163:e59c8e839560	3276	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	163:e59c8e839560	3277	}
AnnaBridge	163:e59c8e839560	3278
AnnaBridge	163:e59c8e839560	3279	/**
AnnaBridge	163:e59c8e839560	3280	* @brief Set the clock source of the counter clock.
AnnaBridge	163:e59c8e839560	3281	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	163:e59c8e839560	3282	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	163:e59c8e839560	3283	* function. This timer input must be configured by calling
AnnaBridge	163:e59c8e839560	3284	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	163:e59c8e839560	3285	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3286	* whether or not a timer instance supports external clock mode1.
AnnaBridge	163:e59c8e839560	3287	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3288	* whether or not a timer instance supports external clock mode2.
AnnaBridge	163:e59c8e839560	3289	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	163:e59c8e839560	3290	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	163:e59c8e839560	3291	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3292	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3293	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	163:e59c8e839560	3294	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	163:e59c8e839560	3295	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	163:e59c8e839560	3296	* @retval None
AnnaBridge	163:e59c8e839560	3297	*/
AnnaBridge	163:e59c8e839560	3298	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	163:e59c8e839560	3299	{
AnnaBridge	163:e59c8e839560	3300	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	163:e59c8e839560	3301	}
AnnaBridge	163:e59c8e839560	3302
AnnaBridge	163:e59c8e839560	3303	/**
AnnaBridge	163:e59c8e839560	3304	* @brief Set the encoder interface mode.
AnnaBridge	163:e59c8e839560	3305	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3306	* whether or not a timer instance supports the encoder mode.
AnnaBridge	163:e59c8e839560	3307	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	163:e59c8e839560	3308	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3309	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3310	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	163:e59c8e839560	3311	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	163:e59c8e839560	3312	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	163:e59c8e839560	3313	* @retval None
AnnaBridge	163:e59c8e839560	3314	*/
AnnaBridge	163:e59c8e839560	3315	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	163:e59c8e839560	3316	{
AnnaBridge	163:e59c8e839560	3317	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	163:e59c8e839560	3318	}
AnnaBridge	163:e59c8e839560	3319
AnnaBridge	163:e59c8e839560	3320	/**
AnnaBridge	163:e59c8e839560	3321	* @}
AnnaBridge	163:e59c8e839560	3322	*/
AnnaBridge	163:e59c8e839560	3323
AnnaBridge	163:e59c8e839560	3324	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	163:e59c8e839560	3325	* @{
AnnaBridge	163:e59c8e839560	3326	*/
AnnaBridge	163:e59c8e839560	3327	/**
AnnaBridge	163:e59c8e839560	3328	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	163:e59c8e839560	3329	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3330	* whether or not a timer instance can operate as a master timer.
AnnaBridge	163:e59c8e839560	3331	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	163:e59c8e839560	3332	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3333	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3334	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	163:e59c8e839560	3335	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	163:e59c8e839560	3336	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	163:e59c8e839560	3337	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	163:e59c8e839560	3338	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	163:e59c8e839560	3339	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	163:e59c8e839560	3340	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	163:e59c8e839560	3341	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	163:e59c8e839560	3342	* @retval None
AnnaBridge	163:e59c8e839560	3343	*/
AnnaBridge	163:e59c8e839560	3344	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	163:e59c8e839560	3345	{
AnnaBridge	163:e59c8e839560	3346	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	163:e59c8e839560	3347	}
AnnaBridge	163:e59c8e839560	3348
AnnaBridge	163:e59c8e839560	3349	#if defined(TIM_CR2_MMS2)
AnnaBridge	163:e59c8e839560	3350	/**
AnnaBridge	163:e59c8e839560	3351	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
AnnaBridge	163:e59c8e839560	3352	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
AnnaBridge	163:e59c8e839560	3353	* whether or not a timer instance can be used for ADC synchronization.
AnnaBridge	163:e59c8e839560	3354	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
AnnaBridge	163:e59c8e839560	3355	* @param TIMx Timer Instance
AnnaBridge	163:e59c8e839560	3356	* @param ADCSynchronization This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3357	* @arg @ref LL_TIM_TRGO2_RESET
AnnaBridge	163:e59c8e839560	3358	* @arg @ref LL_TIM_TRGO2_ENABLE
AnnaBridge	163:e59c8e839560	3359	* @arg @ref LL_TIM_TRGO2_UPDATE
AnnaBridge	163:e59c8e839560	3360	* @arg @ref LL_TIM_TRGO2_CC1F
AnnaBridge	163:e59c8e839560	3361	* @arg @ref LL_TIM_TRGO2_OC1
AnnaBridge	163:e59c8e839560	3362	* @arg @ref LL_TIM_TRGO2_OC2
AnnaBridge	163:e59c8e839560	3363	* @arg @ref LL_TIM_TRGO2_OC3
AnnaBridge	163:e59c8e839560	3364	* @arg @ref LL_TIM_TRGO2_OC4
AnnaBridge	163:e59c8e839560	3365	* @arg @ref LL_TIM_TRGO2_OC5
AnnaBridge	163:e59c8e839560	3366	* @arg @ref LL_TIM_TRGO2_OC6
AnnaBridge	163:e59c8e839560	3367	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
AnnaBridge	163:e59c8e839560	3368	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
AnnaBridge	163:e59c8e839560	3369	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
AnnaBridge	163:e59c8e839560	3370	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
AnnaBridge	163:e59c8e839560	3371	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
AnnaBridge	163:e59c8e839560	3372	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
AnnaBridge	163:e59c8e839560	3373	* @note OC5 and OC6 are not available for all F3 devices
AnnaBridge	163:e59c8e839560	3374	* @retval None
AnnaBridge	163:e59c8e839560	3375	*/
AnnaBridge	163:e59c8e839560	3376	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
AnnaBridge	163:e59c8e839560	3377	{
AnnaBridge	163:e59c8e839560	3378	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
AnnaBridge	163:e59c8e839560	3379	}
AnnaBridge	163:e59c8e839560	3380
AnnaBridge	163:e59c8e839560	3381	#endif /* TIM_CR2_MMS2 */
AnnaBridge	163:e59c8e839560	3382	/**
AnnaBridge	163:e59c8e839560	3383	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	163:e59c8e839560	3384	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3385	* a timer instance can operate as a slave timer.
AnnaBridge	163:e59c8e839560	3386	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	163:e59c8e839560	3387	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3388	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3389	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	163:e59c8e839560	3390	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	163:e59c8e839560	3391	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	163:e59c8e839560	3392	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	163:e59c8e839560	3393	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
AnnaBridge	163:e59c8e839560	3394	* @retval None
AnnaBridge	163:e59c8e839560	3395	*/
AnnaBridge	163:e59c8e839560	3396	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	163:e59c8e839560	3397	{
AnnaBridge	163:e59c8e839560	3398	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	163:e59c8e839560	3399	}
AnnaBridge	163:e59c8e839560	3400
AnnaBridge	163:e59c8e839560	3401	/**
AnnaBridge	163:e59c8e839560	3402	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	163:e59c8e839560	3403	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3404	* a timer instance can operate as a slave timer.
AnnaBridge	163:e59c8e839560	3405	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	163:e59c8e839560	3406	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3407	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3408	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	163:e59c8e839560	3409	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	163:e59c8e839560	3410	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	163:e59c8e839560	3411	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	163:e59c8e839560	3412	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	163:e59c8e839560	3413	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	163:e59c8e839560	3414	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	163:e59c8e839560	3415	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	163:e59c8e839560	3416	* @retval None
AnnaBridge	163:e59c8e839560	3417	*/
AnnaBridge	163:e59c8e839560	3418	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	163:e59c8e839560	3419	{
AnnaBridge	163:e59c8e839560	3420	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	163:e59c8e839560	3421	}
AnnaBridge	163:e59c8e839560	3422
AnnaBridge	163:e59c8e839560	3423	/**
AnnaBridge	163:e59c8e839560	3424	* @brief Enable the Master/Slave mode.
AnnaBridge	163:e59c8e839560	3425	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3426	* a timer instance can operate as a slave timer.
AnnaBridge	163:e59c8e839560	3427	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	163:e59c8e839560	3428	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3429	* @retval None
AnnaBridge	163:e59c8e839560	3430	*/
AnnaBridge	163:e59c8e839560	3431	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3432	{
AnnaBridge	163:e59c8e839560	3433	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	163:e59c8e839560	3434	}
AnnaBridge	163:e59c8e839560	3435
AnnaBridge	163:e59c8e839560	3436	/**
AnnaBridge	163:e59c8e839560	3437	* @brief Disable the Master/Slave mode.
AnnaBridge	163:e59c8e839560	3438	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3439	* a timer instance can operate as a slave timer.
AnnaBridge	163:e59c8e839560	3440	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	163:e59c8e839560	3441	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3442	* @retval None
AnnaBridge	163:e59c8e839560	3443	*/
AnnaBridge	163:e59c8e839560	3444	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3445	{
AnnaBridge	163:e59c8e839560	3446	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	163:e59c8e839560	3447	}
AnnaBridge	163:e59c8e839560	3448
AnnaBridge	163:e59c8e839560	3449	/**
AnnaBridge	163:e59c8e839560	3450	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	163:e59c8e839560	3451	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3452	* a timer instance can operate as a slave timer.
AnnaBridge	163:e59c8e839560	3453	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	163:e59c8e839560	3454	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3455	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3456	*/
AnnaBridge	163:e59c8e839560	3457	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3458	{
AnnaBridge	163:e59c8e839560	3459	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	163:e59c8e839560	3460	}
AnnaBridge	163:e59c8e839560	3461
AnnaBridge	163:e59c8e839560	3462	/**
AnnaBridge	163:e59c8e839560	3463	* @brief Configure the external trigger (ETR) input.
AnnaBridge	163:e59c8e839560	3464	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3465	* a timer instance provides an external trigger input.
AnnaBridge	163:e59c8e839560	3466	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	163:e59c8e839560	3467	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	163:e59c8e839560	3468	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	163:e59c8e839560	3469	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3470	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3471	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	163:e59c8e839560	3472	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	163:e59c8e839560	3473	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3474	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	163:e59c8e839560	3475	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	163:e59c8e839560	3476	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	163:e59c8e839560	3477	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	163:e59c8e839560	3478	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3479	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	163:e59c8e839560	3480	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	163:e59c8e839560	3481	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	163:e59c8e839560	3482	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	163:e59c8e839560	3483	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	163:e59c8e839560	3484	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	163:e59c8e839560	3485	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	163:e59c8e839560	3486	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	163:e59c8e839560	3487	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	163:e59c8e839560	3488	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	163:e59c8e839560	3489	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	163:e59c8e839560	3490	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	163:e59c8e839560	3491	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	163:e59c8e839560	3492	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	163:e59c8e839560	3493	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	163:e59c8e839560	3494	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	3495	* @retval None
AnnaBridge	163:e59c8e839560	3496	*/
AnnaBridge	163:e59c8e839560	3497	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	163:e59c8e839560	3498	uint32_t ETRFilter)
AnnaBridge	163:e59c8e839560	3499	{
AnnaBridge	163:e59c8e839560	3500	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	163:e59c8e839560	3501	}
AnnaBridge	163:e59c8e839560	3502
AnnaBridge	163:e59c8e839560	3503	/**
AnnaBridge	163:e59c8e839560	3504	* @}
AnnaBridge	163:e59c8e839560	3505	*/
AnnaBridge	163:e59c8e839560	3506
AnnaBridge	163:e59c8e839560	3507	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	163:e59c8e839560	3508	* @{
AnnaBridge	163:e59c8e839560	3509	*/
AnnaBridge	163:e59c8e839560	3510	/**
AnnaBridge	163:e59c8e839560	3511	* @brief Enable the break function.
AnnaBridge	163:e59c8e839560	3512	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3513	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3514	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	163:e59c8e839560	3515	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3516	* @retval None
AnnaBridge	163:e59c8e839560	3517	*/
AnnaBridge	163:e59c8e839560	3518	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3519	{
AnnaBridge	168:b9e159c1930a	3520	__IO uint32_t tmpreg;
AnnaBridge	168:b9e159c1930a	3521
AnnaBridge	163:e59c8e839560	3522	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	168:b9e159c1930a	3523
AnnaBridge	168:b9e159c1930a	3524	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	168:b9e159c1930a	3525	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	168:b9e159c1930a	3526	(void)(tmpreg);
AnnaBridge	163:e59c8e839560	3527	}
AnnaBridge	163:e59c8e839560	3528
AnnaBridge	163:e59c8e839560	3529	/**
AnnaBridge	163:e59c8e839560	3530	* @brief Disable the break function.
AnnaBridge	163:e59c8e839560	3531	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	163:e59c8e839560	3532	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3533	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3534	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3535	* @retval None
AnnaBridge	163:e59c8e839560	3536	*/
AnnaBridge	163:e59c8e839560	3537	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3538	{
AnnaBridge	168:b9e159c1930a	3539	__IO uint32_t tmpreg;
AnnaBridge	168:b9e159c1930a	3540
AnnaBridge	163:e59c8e839560	3541	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	168:b9e159c1930a	3542
AnnaBridge	168:b9e159c1930a	3543	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	168:b9e159c1930a	3544	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	168:b9e159c1930a	3545	(void)(tmpreg);
AnnaBridge	163:e59c8e839560	3546	}
AnnaBridge	163:e59c8e839560	3547
AnnaBridge	163:e59c8e839560	3548	#if defined(TIM_BDTR_BKF)
AnnaBridge	163:e59c8e839560	3549	/**
AnnaBridge	163:e59c8e839560	3550	* @brief Configure the break input.
AnnaBridge	163:e59c8e839560	3551	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3552	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3553	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
AnnaBridge	163:e59c8e839560	3554	* BDTR BKF LL_TIM_ConfigBRK
AnnaBridge	163:e59c8e839560	3555	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3556	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3557	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	163:e59c8e839560	3558	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	3559	* @param BreakFilter This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3560	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
AnnaBridge	163:e59c8e839560	3561	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
AnnaBridge	163:e59c8e839560	3562	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
AnnaBridge	163:e59c8e839560	3563	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
AnnaBridge	163:e59c8e839560	3564	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
AnnaBridge	163:e59c8e839560	3565	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
AnnaBridge	163:e59c8e839560	3566	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
AnnaBridge	163:e59c8e839560	3567	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
AnnaBridge	163:e59c8e839560	3568	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
AnnaBridge	163:e59c8e839560	3569	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
AnnaBridge	163:e59c8e839560	3570	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
AnnaBridge	163:e59c8e839560	3571	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
AnnaBridge	163:e59c8e839560	3572	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
AnnaBridge	163:e59c8e839560	3573	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
AnnaBridge	163:e59c8e839560	3574	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
AnnaBridge	163:e59c8e839560	3575	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	3576	* @retval None
AnnaBridge	163:e59c8e839560	3577	*/
AnnaBridge	163:e59c8e839560	3578	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
AnnaBridge	163:e59c8e839560	3579	{
AnnaBridge	163:e59c8e839560	3580	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
AnnaBridge	163:e59c8e839560	3581	}
AnnaBridge	163:e59c8e839560	3582
AnnaBridge	163:e59c8e839560	3583	#else
AnnaBridge	163:e59c8e839560	3584	/**
AnnaBridge	163:e59c8e839560	3585	* @brief Configure the break input.
AnnaBridge	163:e59c8e839560	3586	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3587	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3588	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
AnnaBridge	163:e59c8e839560	3589	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3590	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3591	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	163:e59c8e839560	3592	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	3593	* @retval None
AnnaBridge	163:e59c8e839560	3594	*/
AnnaBridge	163:e59c8e839560	3595	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
AnnaBridge	163:e59c8e839560	3596	{
AnnaBridge	168:b9e159c1930a	3597	__IO uint32_t tmpreg;
AnnaBridge	168:b9e159c1930a	3598
AnnaBridge	163:e59c8e839560	3599	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
AnnaBridge	168:b9e159c1930a	3600
AnnaBridge	168:b9e159c1930a	3601	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	168:b9e159c1930a	3602	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	168:b9e159c1930a	3603	(void)(tmpreg);
AnnaBridge	163:e59c8e839560	3604	}
AnnaBridge	163:e59c8e839560	3605
AnnaBridge	163:e59c8e839560	3606	#endif /* TIM_BDTR_BKF */
AnnaBridge	163:e59c8e839560	3607	#if defined(TIM_BDTR_BK2E)
AnnaBridge	163:e59c8e839560	3608	/**
AnnaBridge	163:e59c8e839560	3609	* @brief Enable the break 2 function.
AnnaBridge	163:e59c8e839560	3610	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3611	* a timer instance provides a second break input.
AnnaBridge	163:e59c8e839560	3612	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
AnnaBridge	163:e59c8e839560	3613	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3614	* @retval None
AnnaBridge	163:e59c8e839560	3615	*/
AnnaBridge	163:e59c8e839560	3616	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3617	{
AnnaBridge	163:e59c8e839560	3618	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	163:e59c8e839560	3619	}
AnnaBridge	163:e59c8e839560	3620
AnnaBridge	163:e59c8e839560	3621	/**
AnnaBridge	163:e59c8e839560	3622	* @brief Disable the break 2 function.
AnnaBridge	163:e59c8e839560	3623	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3624	* a timer instance provides a second break input.
AnnaBridge	163:e59c8e839560	3625	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
AnnaBridge	163:e59c8e839560	3626	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3627	* @retval None
AnnaBridge	163:e59c8e839560	3628	*/
AnnaBridge	163:e59c8e839560	3629	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3630	{
AnnaBridge	163:e59c8e839560	3631	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	163:e59c8e839560	3632	}
AnnaBridge	163:e59c8e839560	3633
AnnaBridge	163:e59c8e839560	3634	/**
AnnaBridge	163:e59c8e839560	3635	* @brief Configure the break 2 input.
AnnaBridge	163:e59c8e839560	3636	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3637	* a timer instance provides a second break input.
AnnaBridge	163:e59c8e839560	3638	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
AnnaBridge	163:e59c8e839560	3639	* BDTR BK2F LL_TIM_ConfigBRK2
AnnaBridge	163:e59c8e839560	3640	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3641	* @param Break2Polarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3642	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
AnnaBridge	163:e59c8e839560	3643	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	3644	* @param Break2Filter This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3645	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
AnnaBridge	163:e59c8e839560	3646	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
AnnaBridge	163:e59c8e839560	3647	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
AnnaBridge	163:e59c8e839560	3648	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
AnnaBridge	163:e59c8e839560	3649	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
AnnaBridge	163:e59c8e839560	3650	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
AnnaBridge	163:e59c8e839560	3651	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
AnnaBridge	163:e59c8e839560	3652	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
AnnaBridge	163:e59c8e839560	3653	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
AnnaBridge	163:e59c8e839560	3654	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
AnnaBridge	163:e59c8e839560	3655	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
AnnaBridge	163:e59c8e839560	3656	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
AnnaBridge	163:e59c8e839560	3657	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
AnnaBridge	163:e59c8e839560	3658	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
AnnaBridge	163:e59c8e839560	3659	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
AnnaBridge	163:e59c8e839560	3660	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
AnnaBridge	163:e59c8e839560	3661	* @retval None
AnnaBridge	163:e59c8e839560	3662	*/
AnnaBridge	163:e59c8e839560	3663	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
AnnaBridge	163:e59c8e839560	3664	{
AnnaBridge	163:e59c8e839560	3665	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
AnnaBridge	163:e59c8e839560	3666	}
AnnaBridge	163:e59c8e839560	3667
AnnaBridge	163:e59c8e839560	3668	#endif /* TIM_BDTR_BK2E */
AnnaBridge	163:e59c8e839560	3669	/**
AnnaBridge	163:e59c8e839560	3670	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	163:e59c8e839560	3671	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3672	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3673	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	163:e59c8e839560	3674	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	163:e59c8e839560	3675	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3676	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3677	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	163:e59c8e839560	3678	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	163:e59c8e839560	3679	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3680	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	163:e59c8e839560	3681	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	163:e59c8e839560	3682	* @retval None
AnnaBridge	163:e59c8e839560	3683	*/
AnnaBridge	163:e59c8e839560	3684	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	163:e59c8e839560	3685	{
AnnaBridge	163:e59c8e839560	3686	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	163:e59c8e839560	3687	}
AnnaBridge	163:e59c8e839560	3688
AnnaBridge	163:e59c8e839560	3689	/**
AnnaBridge	163:e59c8e839560	3690	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	163:e59c8e839560	3691	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3692	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3693	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	163:e59c8e839560	3694	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3695	* @retval None
AnnaBridge	163:e59c8e839560	3696	*/
AnnaBridge	163:e59c8e839560	3697	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3698	{
AnnaBridge	163:e59c8e839560	3699	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	163:e59c8e839560	3700	}
AnnaBridge	163:e59c8e839560	3701
AnnaBridge	163:e59c8e839560	3702	/**
AnnaBridge	163:e59c8e839560	3703	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	163:e59c8e839560	3704	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3705	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3706	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	163:e59c8e839560	3707	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3708	* @retval None
AnnaBridge	163:e59c8e839560	3709	*/
AnnaBridge	163:e59c8e839560	3710	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3711	{
AnnaBridge	163:e59c8e839560	3712	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	163:e59c8e839560	3713	}
AnnaBridge	163:e59c8e839560	3714
AnnaBridge	163:e59c8e839560	3715	/**
AnnaBridge	163:e59c8e839560	3716	* @brief Indicate whether automatic output is enabled.
AnnaBridge	163:e59c8e839560	3717	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3718	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3719	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	163:e59c8e839560	3720	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3721	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3722	*/
AnnaBridge	163:e59c8e839560	3723	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3724	{
AnnaBridge	163:e59c8e839560	3725	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	163:e59c8e839560	3726	}
AnnaBridge	163:e59c8e839560	3727
AnnaBridge	163:e59c8e839560	3728	/**
AnnaBridge	163:e59c8e839560	3729	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	163:e59c8e839560	3730	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	163:e59c8e839560	3731	* software and is reset in case of break or break2 event
AnnaBridge	163:e59c8e839560	3732	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3733	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3734	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	163:e59c8e839560	3735	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3736	* @retval None
AnnaBridge	163:e59c8e839560	3737	*/
AnnaBridge	163:e59c8e839560	3738	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3739	{
AnnaBridge	163:e59c8e839560	3740	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	163:e59c8e839560	3741	}
AnnaBridge	163:e59c8e839560	3742
AnnaBridge	163:e59c8e839560	3743	/**
AnnaBridge	163:e59c8e839560	3744	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	163:e59c8e839560	3745	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	163:e59c8e839560	3746	* software and is reset in case of break or break2 event.
AnnaBridge	163:e59c8e839560	3747	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3748	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3749	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	163:e59c8e839560	3750	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3751	* @retval None
AnnaBridge	163:e59c8e839560	3752	*/
AnnaBridge	163:e59c8e839560	3753	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3754	{
AnnaBridge	163:e59c8e839560	3755	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	163:e59c8e839560	3756	}
AnnaBridge	163:e59c8e839560	3757
AnnaBridge	163:e59c8e839560	3758	/**
AnnaBridge	163:e59c8e839560	3759	* @brief Indicates whether outputs are enabled.
AnnaBridge	163:e59c8e839560	3760	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3761	* a timer instance provides a break input.
AnnaBridge	163:e59c8e839560	3762	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	163:e59c8e839560	3763	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3764	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3765	*/
AnnaBridge	163:e59c8e839560	3766	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3767	{
AnnaBridge	163:e59c8e839560	3768	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	163:e59c8e839560	3769	}
AnnaBridge	163:e59c8e839560	3770
AnnaBridge	163:e59c8e839560	3771	/**
AnnaBridge	163:e59c8e839560	3772	* @}
AnnaBridge	163:e59c8e839560	3773	*/
AnnaBridge	163:e59c8e839560	3774
AnnaBridge	163:e59c8e839560	3775	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	163:e59c8e839560	3776	* @{
AnnaBridge	163:e59c8e839560	3777	*/
AnnaBridge	163:e59c8e839560	3778	/**
AnnaBridge	163:e59c8e839560	3779	* @brief Configures the timer DMA burst feature.
AnnaBridge	163:e59c8e839560	3780	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	163:e59c8e839560	3781	* not a timer instance supports the DMA burst mode.
AnnaBridge	163:e59c8e839560	3782	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	163:e59c8e839560	3783	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	163:e59c8e839560	3784	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3785	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3786	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	163:e59c8e839560	3787	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	163:e59c8e839560	3788	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	163:e59c8e839560	3789	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	163:e59c8e839560	3790	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	163:e59c8e839560	3791	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	163:e59c8e839560	3792	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	163:e59c8e839560	3793	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	163:e59c8e839560	3794	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	163:e59c8e839560	3795	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	163:e59c8e839560	3796	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	163:e59c8e839560	3797	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	163:e59c8e839560	3798	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	163:e59c8e839560	3799	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	163:e59c8e839560	3800	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	163:e59c8e839560	3801	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	163:e59c8e839560	3802	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	163:e59c8e839560	3803	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	163:e59c8e839560	3804	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
AnnaBridge	163:e59c8e839560	3805	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
AnnaBridge	163:e59c8e839560	3806	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
AnnaBridge	163:e59c8e839560	3807	* (*) value not defined in all devices
AnnaBridge	163:e59c8e839560	3808	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
AnnaBridge	163:e59c8e839560	3809	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3810	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	163:e59c8e839560	3811	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	163:e59c8e839560	3812	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	163:e59c8e839560	3813	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	163:e59c8e839560	3814	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	163:e59c8e839560	3815	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	163:e59c8e839560	3816	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	163:e59c8e839560	3817	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	163:e59c8e839560	3818	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	163:e59c8e839560	3819	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	163:e59c8e839560	3820	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	163:e59c8e839560	3821	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	163:e59c8e839560	3822	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	163:e59c8e839560	3823	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	163:e59c8e839560	3824	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	163:e59c8e839560	3825	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	163:e59c8e839560	3826	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	163:e59c8e839560	3827	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	163:e59c8e839560	3828	* @retval None
AnnaBridge	163:e59c8e839560	3829	*/
AnnaBridge	163:e59c8e839560	3830	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	163:e59c8e839560	3831	{
AnnaBridge	163:e59c8e839560	3832	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	163:e59c8e839560	3833	}
AnnaBridge	163:e59c8e839560	3834
AnnaBridge	163:e59c8e839560	3835	/**
AnnaBridge	163:e59c8e839560	3836	* @}
AnnaBridge	163:e59c8e839560	3837	*/
AnnaBridge	163:e59c8e839560	3838
AnnaBridge	163:e59c8e839560	3839	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	163:e59c8e839560	3840	* @{
AnnaBridge	163:e59c8e839560	3841	*/
AnnaBridge	163:e59c8e839560	3842	/**
AnnaBridge	163:e59c8e839560	3843	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	163:e59c8e839560	3844	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	163:e59c8e839560	3845	* a some timer inputs can be remapped.
AnnaBridge	163:e59c8e839560	3846	* @if STM32F334x8
AnnaBridge	163:e59c8e839560	3847	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3848	* TIM16_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3849	* @elseif STM32F302x8
AnnaBridge	163:e59c8e839560	3850	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3851	* TIM16_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3852	* @elseif STM32F303xC
AnnaBridge	163:e59c8e839560	3853	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3854	* TIM8_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3855	* TIM20_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	163:e59c8e839560	3856	* @elseif STM32F373xC
AnnaBridge	163:e59c8e839560	3857	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
AnnaBridge	163:e59c8e839560	3858	* @endif
AnnaBridge	163:e59c8e839560	3859	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3860	* @param Remap Remap params depends on the TIMx. Description available only
AnnaBridge	163:e59c8e839560	3861	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	163:e59c8e839560	3862	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	163:e59c8e839560	3863	*
AnnaBridge	163:e59c8e839560	3864	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	163:e59c8e839560	3865	*
AnnaBridge	163:e59c8e839560	3866	* TIM1: any combination of ETR_RMP where (**)
AnnaBridge	163:e59c8e839560	3867	*
AnnaBridge	163:e59c8e839560	3868	* . . ETR_RMP can be one of the following values
AnnaBridge	163:e59c8e839560	3869	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
AnnaBridge	163:e59c8e839560	3870	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3871	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3872	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3873	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3874	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3875	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3876	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3877	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3878	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3879	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3880	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3881	*
AnnaBridge	163:e59c8e839560	3882	* TIM8: any combination of ETR_RMP where (**)
AnnaBridge	163:e59c8e839560	3883	*
AnnaBridge	163:e59c8e839560	3884	* . . ETR_RMP can be one of the following values
AnnaBridge	163:e59c8e839560	3885	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3886	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3887	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3888	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3889	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3890	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3891	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3892	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3893	*
AnnaBridge	163:e59c8e839560	3894	* TIM14: any combination of TI1_RMP where (**)
AnnaBridge	163:e59c8e839560	3895	*
AnnaBridge	163:e59c8e839560	3896	* . . TI1_RMP can be one of the following values
AnnaBridge	163:e59c8e839560	3897	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
AnnaBridge	163:e59c8e839560	3898	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
AnnaBridge	163:e59c8e839560	3899	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
AnnaBridge	163:e59c8e839560	3900	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
AnnaBridge	163:e59c8e839560	3901	*
AnnaBridge	163:e59c8e839560	3902	* TIM16: any combination of TI1_RMP where (**)
AnnaBridge	163:e59c8e839560	3903	*
AnnaBridge	163:e59c8e839560	3904	* . . TI1_RMP can be one of the following values
AnnaBridge	163:e59c8e839560	3905	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
AnnaBridge	163:e59c8e839560	3906	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
AnnaBridge	163:e59c8e839560	3907	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
AnnaBridge	163:e59c8e839560	3908	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
AnnaBridge	163:e59c8e839560	3909	*
AnnaBridge	163:e59c8e839560	3910	* TIM20: any combination of ETR_RMP where (**)
AnnaBridge	163:e59c8e839560	3911	*
AnnaBridge	163:e59c8e839560	3912	* . . ETR_RMP can be one of the following values
AnnaBridge	163:e59c8e839560	3913	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3914	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3915	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3916	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3917	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
AnnaBridge	163:e59c8e839560	3918	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
AnnaBridge	163:e59c8e839560	3919	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
AnnaBridge	163:e59c8e839560	3920	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
AnnaBridge	163:e59c8e839560	3921	*
AnnaBridge	163:e59c8e839560	3922	* (*) Value not defined in all devices. \n
AnnaBridge	163:e59c8e839560	3923	* (**) Register not available in all devices.
AnnaBridge	163:e59c8e839560	3924	* @retval None
AnnaBridge	163:e59c8e839560	3925	*/
AnnaBridge	163:e59c8e839560	3926	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	163:e59c8e839560	3927	{
AnnaBridge	163:e59c8e839560	3928	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
AnnaBridge	163:e59c8e839560	3929	}
AnnaBridge	163:e59c8e839560	3930
AnnaBridge	163:e59c8e839560	3931	/**
AnnaBridge	163:e59c8e839560	3932	* @}
AnnaBridge	163:e59c8e839560	3933	*/
AnnaBridge	163:e59c8e839560	3934
AnnaBridge	163:e59c8e839560	3935	#if defined(TIM_SMCR_OCCS)
AnnaBridge	163:e59c8e839560	3936	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	163:e59c8e839560	3937	* @{
AnnaBridge	163:e59c8e839560	3938	*/
AnnaBridge	163:e59c8e839560	3939	/**
AnnaBridge	163:e59c8e839560	3940	* @brief Set the OCREF clear input source
AnnaBridge	163:e59c8e839560	3941	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	163:e59c8e839560	3942	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	163:e59c8e839560	3943	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	163:e59c8e839560	3944	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3945	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3946	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
AnnaBridge	163:e59c8e839560	3947	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	163:e59c8e839560	3948	* @retval None
AnnaBridge	163:e59c8e839560	3949	*/
AnnaBridge	163:e59c8e839560	3950	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	163:e59c8e839560	3951	{
AnnaBridge	163:e59c8e839560	3952	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	163:e59c8e839560	3953	}
AnnaBridge	163:e59c8e839560	3954	/**
AnnaBridge	163:e59c8e839560	3955	* @}
AnnaBridge	163:e59c8e839560	3956	*/
AnnaBridge	163:e59c8e839560	3957	#endif /* TIM_SMCR_OCCS */
AnnaBridge	163:e59c8e839560	3958
AnnaBridge	163:e59c8e839560	3959	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	163:e59c8e839560	3960	* @{
AnnaBridge	163:e59c8e839560	3961	*/
AnnaBridge	163:e59c8e839560	3962	/**
AnnaBridge	163:e59c8e839560	3963	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	163:e59c8e839560	3964	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	163:e59c8e839560	3965	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3966	* @retval None
AnnaBridge	163:e59c8e839560	3967	*/
AnnaBridge	163:e59c8e839560	3968	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3969	{
AnnaBridge	163:e59c8e839560	3970	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	163:e59c8e839560	3971	}
AnnaBridge	163:e59c8e839560	3972
AnnaBridge	163:e59c8e839560	3973	/**
AnnaBridge	163:e59c8e839560	3974	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	163:e59c8e839560	3975	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	163:e59c8e839560	3976	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3977	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	3978	*/
AnnaBridge	163:e59c8e839560	3979	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3980	{
AnnaBridge	163:e59c8e839560	3981	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	163:e59c8e839560	3982	}
AnnaBridge	163:e59c8e839560	3983
AnnaBridge	163:e59c8e839560	3984	/**
AnnaBridge	163:e59c8e839560	3985	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	163:e59c8e839560	3986	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	163:e59c8e839560	3987	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3988	* @retval None
AnnaBridge	163:e59c8e839560	3989	*/
AnnaBridge	163:e59c8e839560	3990	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	3991	{
AnnaBridge	163:e59c8e839560	3992	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	163:e59c8e839560	3993	}
AnnaBridge	163:e59c8e839560	3994
AnnaBridge	163:e59c8e839560	3995	/**
AnnaBridge	163:e59c8e839560	3996	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	163:e59c8e839560	3997	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	163:e59c8e839560	3998	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	3999	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4000	*/
AnnaBridge	163:e59c8e839560	4001	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4002	{
AnnaBridge	163:e59c8e839560	4003	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	163:e59c8e839560	4004	}
AnnaBridge	163:e59c8e839560	4005
AnnaBridge	163:e59c8e839560	4006	/**
AnnaBridge	163:e59c8e839560	4007	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	163:e59c8e839560	4008	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	163:e59c8e839560	4009	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4010	* @retval None
AnnaBridge	163:e59c8e839560	4011	*/
AnnaBridge	163:e59c8e839560	4012	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4013	{
AnnaBridge	163:e59c8e839560	4014	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	163:e59c8e839560	4015	}
AnnaBridge	163:e59c8e839560	4016
AnnaBridge	163:e59c8e839560	4017	/**
AnnaBridge	163:e59c8e839560	4018	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	163:e59c8e839560	4019	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	163:e59c8e839560	4020	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4021	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4022	*/
AnnaBridge	163:e59c8e839560	4023	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4024	{
AnnaBridge	163:e59c8e839560	4025	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	163:e59c8e839560	4026	}
AnnaBridge	163:e59c8e839560	4027
AnnaBridge	163:e59c8e839560	4028	/**
AnnaBridge	163:e59c8e839560	4029	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	163:e59c8e839560	4030	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	163:e59c8e839560	4031	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4032	* @retval None
AnnaBridge	163:e59c8e839560	4033	*/
AnnaBridge	163:e59c8e839560	4034	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4035	{
AnnaBridge	163:e59c8e839560	4036	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	163:e59c8e839560	4037	}
AnnaBridge	163:e59c8e839560	4038
AnnaBridge	163:e59c8e839560	4039	/**
AnnaBridge	163:e59c8e839560	4040	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	163:e59c8e839560	4041	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	163:e59c8e839560	4042	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4043	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4044	*/
AnnaBridge	163:e59c8e839560	4045	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4046	{
AnnaBridge	163:e59c8e839560	4047	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	163:e59c8e839560	4048	}
AnnaBridge	163:e59c8e839560	4049
AnnaBridge	163:e59c8e839560	4050	/**
AnnaBridge	163:e59c8e839560	4051	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	163:e59c8e839560	4052	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	163:e59c8e839560	4053	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4054	* @retval None
AnnaBridge	163:e59c8e839560	4055	*/
AnnaBridge	163:e59c8e839560	4056	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4057	{
AnnaBridge	163:e59c8e839560	4058	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	163:e59c8e839560	4059	}
AnnaBridge	163:e59c8e839560	4060
AnnaBridge	163:e59c8e839560	4061	/**
AnnaBridge	163:e59c8e839560	4062	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	163:e59c8e839560	4063	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	163:e59c8e839560	4064	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4065	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4066	*/
AnnaBridge	163:e59c8e839560	4067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4068	{
AnnaBridge	163:e59c8e839560	4069	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	163:e59c8e839560	4070	}
AnnaBridge	163:e59c8e839560	4071
AnnaBridge	163:e59c8e839560	4072	#if defined (TIM_SR_CC5IF)
AnnaBridge	163:e59c8e839560	4073	/**
AnnaBridge	163:e59c8e839560	4074	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
AnnaBridge	163:e59c8e839560	4075	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
AnnaBridge	163:e59c8e839560	4076	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4077	* @retval None
AnnaBridge	163:e59c8e839560	4078	*/
AnnaBridge	163:e59c8e839560	4079	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4080	{
AnnaBridge	163:e59c8e839560	4081	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
AnnaBridge	163:e59c8e839560	4082	}
AnnaBridge	163:e59c8e839560	4083
AnnaBridge	163:e59c8e839560	4084	/**
AnnaBridge	163:e59c8e839560	4085	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
AnnaBridge	163:e59c8e839560	4086	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
AnnaBridge	163:e59c8e839560	4087	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4088	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4089	*/
AnnaBridge	163:e59c8e839560	4090	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4091	{
AnnaBridge	163:e59c8e839560	4092	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
AnnaBridge	163:e59c8e839560	4093	}
AnnaBridge	163:e59c8e839560	4094
AnnaBridge	163:e59c8e839560	4095	#endif /* TIM_SR_CC5IF */
AnnaBridge	163:e59c8e839560	4096	#if defined (TIM_SR_CC6IF)
AnnaBridge	163:e59c8e839560	4097	/**
AnnaBridge	163:e59c8e839560	4098	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
AnnaBridge	163:e59c8e839560	4099	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
AnnaBridge	163:e59c8e839560	4100	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4101	* @retval None
AnnaBridge	163:e59c8e839560	4102	*/
AnnaBridge	163:e59c8e839560	4103	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4104	{
AnnaBridge	163:e59c8e839560	4105	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
AnnaBridge	163:e59c8e839560	4106	}
AnnaBridge	163:e59c8e839560	4107
AnnaBridge	163:e59c8e839560	4108	/**
AnnaBridge	163:e59c8e839560	4109	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
AnnaBridge	163:e59c8e839560	4110	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
AnnaBridge	163:e59c8e839560	4111	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4112	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4113	*/
AnnaBridge	163:e59c8e839560	4114	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4115	{
AnnaBridge	163:e59c8e839560	4116	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
AnnaBridge	163:e59c8e839560	4117	}
AnnaBridge	163:e59c8e839560	4118
AnnaBridge	163:e59c8e839560	4119	#endif /* TIM_SR_CC6IF */
AnnaBridge	163:e59c8e839560	4120	/**
AnnaBridge	163:e59c8e839560	4121	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	163:e59c8e839560	4122	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	163:e59c8e839560	4123	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4124	* @retval None
AnnaBridge	163:e59c8e839560	4125	*/
AnnaBridge	163:e59c8e839560	4126	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4127	{
AnnaBridge	163:e59c8e839560	4128	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	163:e59c8e839560	4129	}
AnnaBridge	163:e59c8e839560	4130
AnnaBridge	163:e59c8e839560	4131	/**
AnnaBridge	163:e59c8e839560	4132	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	163:e59c8e839560	4133	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	163:e59c8e839560	4134	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4135	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4136	*/
AnnaBridge	163:e59c8e839560	4137	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4138	{
AnnaBridge	163:e59c8e839560	4139	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	163:e59c8e839560	4140	}
AnnaBridge	163:e59c8e839560	4141
AnnaBridge	163:e59c8e839560	4142	/**
AnnaBridge	163:e59c8e839560	4143	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	163:e59c8e839560	4144	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	163:e59c8e839560	4145	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4146	* @retval None
AnnaBridge	163:e59c8e839560	4147	*/
AnnaBridge	163:e59c8e839560	4148	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4149	{
AnnaBridge	163:e59c8e839560	4150	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	163:e59c8e839560	4151	}
AnnaBridge	163:e59c8e839560	4152
AnnaBridge	163:e59c8e839560	4153	/**
AnnaBridge	163:e59c8e839560	4154	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	163:e59c8e839560	4155	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	163:e59c8e839560	4156	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4157	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4158	*/
AnnaBridge	163:e59c8e839560	4159	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4160	{
AnnaBridge	163:e59c8e839560	4161	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	163:e59c8e839560	4162	}
AnnaBridge	163:e59c8e839560	4163
AnnaBridge	163:e59c8e839560	4164	/**
AnnaBridge	163:e59c8e839560	4165	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	163:e59c8e839560	4166	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	163:e59c8e839560	4167	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4168	* @retval None
AnnaBridge	163:e59c8e839560	4169	*/
AnnaBridge	163:e59c8e839560	4170	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4171	{
AnnaBridge	163:e59c8e839560	4172	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	163:e59c8e839560	4173	}
AnnaBridge	163:e59c8e839560	4174
AnnaBridge	163:e59c8e839560	4175	/**
AnnaBridge	163:e59c8e839560	4176	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	163:e59c8e839560	4177	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	163:e59c8e839560	4178	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4179	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4180	*/
AnnaBridge	163:e59c8e839560	4181	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4182	{
AnnaBridge	163:e59c8e839560	4183	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	163:e59c8e839560	4184	}
AnnaBridge	163:e59c8e839560	4185
AnnaBridge	163:e59c8e839560	4186	#if defined(TIM_SR_B2IF)
AnnaBridge	163:e59c8e839560	4187	/**
AnnaBridge	163:e59c8e839560	4188	* @brief Clear the break 2 interrupt flag (B2IF).
AnnaBridge	163:e59c8e839560	4189	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
AnnaBridge	163:e59c8e839560	4190	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4191	* @retval None
AnnaBridge	163:e59c8e839560	4192	*/
AnnaBridge	163:e59c8e839560	4193	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4194	{
AnnaBridge	163:e59c8e839560	4195	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
AnnaBridge	163:e59c8e839560	4196	}
AnnaBridge	163:e59c8e839560	4197
AnnaBridge	163:e59c8e839560	4198	/**
AnnaBridge	163:e59c8e839560	4199	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
AnnaBridge	163:e59c8e839560	4200	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
AnnaBridge	163:e59c8e839560	4201	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4202	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4203	*/
AnnaBridge	163:e59c8e839560	4204	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4205	{
AnnaBridge	163:e59c8e839560	4206	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
AnnaBridge	163:e59c8e839560	4207	}
AnnaBridge	163:e59c8e839560	4208
AnnaBridge	163:e59c8e839560	4209	#endif /* TIM_SR_B2IF */
AnnaBridge	163:e59c8e839560	4210	/**
AnnaBridge	163:e59c8e839560	4211	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	163:e59c8e839560	4212	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	163:e59c8e839560	4213	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4214	* @retval None
AnnaBridge	163:e59c8e839560	4215	*/
AnnaBridge	163:e59c8e839560	4216	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4217	{
AnnaBridge	163:e59c8e839560	4218	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	163:e59c8e839560	4219	}
AnnaBridge	163:e59c8e839560	4220
AnnaBridge	163:e59c8e839560	4221	/**
AnnaBridge	163:e59c8e839560	4222	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	163:e59c8e839560	4223	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	163:e59c8e839560	4224	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4225	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4226	*/
AnnaBridge	163:e59c8e839560	4227	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4228	{
AnnaBridge	163:e59c8e839560	4229	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	163:e59c8e839560	4230	}
AnnaBridge	163:e59c8e839560	4231
AnnaBridge	163:e59c8e839560	4232	/**
AnnaBridge	163:e59c8e839560	4233	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	163:e59c8e839560	4234	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	163:e59c8e839560	4235	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4236	* @retval None
AnnaBridge	163:e59c8e839560	4237	*/
AnnaBridge	163:e59c8e839560	4238	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4239	{
AnnaBridge	163:e59c8e839560	4240	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	163:e59c8e839560	4241	}
AnnaBridge	163:e59c8e839560	4242
AnnaBridge	163:e59c8e839560	4243	/**
AnnaBridge	163:e59c8e839560	4244	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	163:e59c8e839560	4245	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	163:e59c8e839560	4246	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4247	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4248	*/
AnnaBridge	163:e59c8e839560	4249	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4250	{
AnnaBridge	163:e59c8e839560	4251	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	163:e59c8e839560	4252	}
AnnaBridge	163:e59c8e839560	4253
AnnaBridge	163:e59c8e839560	4254	/**
AnnaBridge	163:e59c8e839560	4255	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	163:e59c8e839560	4256	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	163:e59c8e839560	4257	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4258	* @retval None
AnnaBridge	163:e59c8e839560	4259	*/
AnnaBridge	163:e59c8e839560	4260	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4261	{
AnnaBridge	163:e59c8e839560	4262	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	163:e59c8e839560	4263	}
AnnaBridge	163:e59c8e839560	4264
AnnaBridge	163:e59c8e839560	4265	/**
AnnaBridge	163:e59c8e839560	4266	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	163:e59c8e839560	4267	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	163:e59c8e839560	4268	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4269	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4270	*/
AnnaBridge	163:e59c8e839560	4271	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4272	{
AnnaBridge	163:e59c8e839560	4273	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	163:e59c8e839560	4274	}
AnnaBridge	163:e59c8e839560	4275
AnnaBridge	163:e59c8e839560	4276	/**
AnnaBridge	163:e59c8e839560	4277	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	163:e59c8e839560	4278	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	163:e59c8e839560	4279	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4280	* @retval None
AnnaBridge	163:e59c8e839560	4281	*/
AnnaBridge	163:e59c8e839560	4282	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4283	{
AnnaBridge	163:e59c8e839560	4284	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	163:e59c8e839560	4285	}
AnnaBridge	163:e59c8e839560	4286
AnnaBridge	163:e59c8e839560	4287	/**
AnnaBridge	163:e59c8e839560	4288	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	163:e59c8e839560	4289	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	163:e59c8e839560	4290	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4291	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4292	*/
AnnaBridge	163:e59c8e839560	4293	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4294	{
AnnaBridge	163:e59c8e839560	4295	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	163:e59c8e839560	4296	}
AnnaBridge	163:e59c8e839560	4297
AnnaBridge	163:e59c8e839560	4298	/**
AnnaBridge	163:e59c8e839560	4299	* @}
AnnaBridge	163:e59c8e839560	4300	*/
AnnaBridge	163:e59c8e839560	4301
AnnaBridge	163:e59c8e839560	4302	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	163:e59c8e839560	4303	* @{
AnnaBridge	163:e59c8e839560	4304	*/
AnnaBridge	163:e59c8e839560	4305	/**
AnnaBridge	163:e59c8e839560	4306	* @brief Enable update interrupt (UIE).
AnnaBridge	163:e59c8e839560	4307	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	163:e59c8e839560	4308	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4309	* @retval None
AnnaBridge	163:e59c8e839560	4310	*/
AnnaBridge	163:e59c8e839560	4311	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4312	{
AnnaBridge	163:e59c8e839560	4313	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	163:e59c8e839560	4314	}
AnnaBridge	163:e59c8e839560	4315
AnnaBridge	163:e59c8e839560	4316	/**
AnnaBridge	163:e59c8e839560	4317	* @brief Disable update interrupt (UIE).
AnnaBridge	163:e59c8e839560	4318	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	163:e59c8e839560	4319	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4320	* @retval None
AnnaBridge	163:e59c8e839560	4321	*/
AnnaBridge	163:e59c8e839560	4322	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4323	{
AnnaBridge	163:e59c8e839560	4324	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	163:e59c8e839560	4325	}
AnnaBridge	163:e59c8e839560	4326
AnnaBridge	163:e59c8e839560	4327	/**
AnnaBridge	163:e59c8e839560	4328	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	163:e59c8e839560	4329	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	163:e59c8e839560	4330	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4331	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4332	*/
AnnaBridge	163:e59c8e839560	4333	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4334	{
AnnaBridge	163:e59c8e839560	4335	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	163:e59c8e839560	4336	}
AnnaBridge	163:e59c8e839560	4337
AnnaBridge	163:e59c8e839560	4338	/**
AnnaBridge	163:e59c8e839560	4339	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	163:e59c8e839560	4340	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	163:e59c8e839560	4341	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4342	* @retval None
AnnaBridge	163:e59c8e839560	4343	*/
AnnaBridge	163:e59c8e839560	4344	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4345	{
AnnaBridge	163:e59c8e839560	4346	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	163:e59c8e839560	4347	}
AnnaBridge	163:e59c8e839560	4348
AnnaBridge	163:e59c8e839560	4349	/**
AnnaBridge	163:e59c8e839560	4350	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	163:e59c8e839560	4351	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	163:e59c8e839560	4352	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4353	* @retval None
AnnaBridge	163:e59c8e839560	4354	*/
AnnaBridge	163:e59c8e839560	4355	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4356	{
AnnaBridge	163:e59c8e839560	4357	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	163:e59c8e839560	4358	}
AnnaBridge	163:e59c8e839560	4359
AnnaBridge	163:e59c8e839560	4360	/**
AnnaBridge	163:e59c8e839560	4361	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	163:e59c8e839560	4362	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	163:e59c8e839560	4363	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4364	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4365	*/
AnnaBridge	163:e59c8e839560	4366	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4367	{
AnnaBridge	163:e59c8e839560	4368	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	163:e59c8e839560	4369	}
AnnaBridge	163:e59c8e839560	4370
AnnaBridge	163:e59c8e839560	4371	/**
AnnaBridge	163:e59c8e839560	4372	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	163:e59c8e839560	4373	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	163:e59c8e839560	4374	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4375	* @retval None
AnnaBridge	163:e59c8e839560	4376	*/
AnnaBridge	163:e59c8e839560	4377	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4378	{
AnnaBridge	163:e59c8e839560	4379	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	163:e59c8e839560	4380	}
AnnaBridge	163:e59c8e839560	4381
AnnaBridge	163:e59c8e839560	4382	/**
AnnaBridge	163:e59c8e839560	4383	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	163:e59c8e839560	4384	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	163:e59c8e839560	4385	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4386	* @retval None
AnnaBridge	163:e59c8e839560	4387	*/
AnnaBridge	163:e59c8e839560	4388	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4389	{
AnnaBridge	163:e59c8e839560	4390	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	163:e59c8e839560	4391	}
AnnaBridge	163:e59c8e839560	4392
AnnaBridge	163:e59c8e839560	4393	/**
AnnaBridge	163:e59c8e839560	4394	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	163:e59c8e839560	4395	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	163:e59c8e839560	4396	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4397	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4398	*/
AnnaBridge	163:e59c8e839560	4399	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4400	{
AnnaBridge	163:e59c8e839560	4401	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	163:e59c8e839560	4402	}
AnnaBridge	163:e59c8e839560	4403
AnnaBridge	163:e59c8e839560	4404	/**
AnnaBridge	163:e59c8e839560	4405	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	163:e59c8e839560	4406	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	163:e59c8e839560	4407	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4408	* @retval None
AnnaBridge	163:e59c8e839560	4409	*/
AnnaBridge	163:e59c8e839560	4410	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4411	{
AnnaBridge	163:e59c8e839560	4412	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	163:e59c8e839560	4413	}
AnnaBridge	163:e59c8e839560	4414
AnnaBridge	163:e59c8e839560	4415	/**
AnnaBridge	163:e59c8e839560	4416	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	163:e59c8e839560	4417	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	163:e59c8e839560	4418	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4419	* @retval None
AnnaBridge	163:e59c8e839560	4420	*/
AnnaBridge	163:e59c8e839560	4421	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4422	{
AnnaBridge	163:e59c8e839560	4423	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	163:e59c8e839560	4424	}
AnnaBridge	163:e59c8e839560	4425
AnnaBridge	163:e59c8e839560	4426	/**
AnnaBridge	163:e59c8e839560	4427	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	163:e59c8e839560	4428	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	163:e59c8e839560	4429	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4430	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4431	*/
AnnaBridge	163:e59c8e839560	4432	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4433	{
AnnaBridge	163:e59c8e839560	4434	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	163:e59c8e839560	4435	}
AnnaBridge	163:e59c8e839560	4436
AnnaBridge	163:e59c8e839560	4437	/**
AnnaBridge	163:e59c8e839560	4438	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	163:e59c8e839560	4439	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	163:e59c8e839560	4440	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4441	* @retval None
AnnaBridge	163:e59c8e839560	4442	*/
AnnaBridge	163:e59c8e839560	4443	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4444	{
AnnaBridge	163:e59c8e839560	4445	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	163:e59c8e839560	4446	}
AnnaBridge	163:e59c8e839560	4447
AnnaBridge	163:e59c8e839560	4448	/**
AnnaBridge	163:e59c8e839560	4449	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	163:e59c8e839560	4450	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	163:e59c8e839560	4451	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4452	* @retval None
AnnaBridge	163:e59c8e839560	4453	*/
AnnaBridge	163:e59c8e839560	4454	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4455	{
AnnaBridge	163:e59c8e839560	4456	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	163:e59c8e839560	4457	}
AnnaBridge	163:e59c8e839560	4458
AnnaBridge	163:e59c8e839560	4459	/**
AnnaBridge	163:e59c8e839560	4460	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	163:e59c8e839560	4461	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	163:e59c8e839560	4462	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4463	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4464	*/
AnnaBridge	163:e59c8e839560	4465	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4466	{
AnnaBridge	163:e59c8e839560	4467	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	163:e59c8e839560	4468	}
AnnaBridge	163:e59c8e839560	4469
AnnaBridge	163:e59c8e839560	4470	/**
AnnaBridge	163:e59c8e839560	4471	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	163:e59c8e839560	4472	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	163:e59c8e839560	4473	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4474	* @retval None
AnnaBridge	163:e59c8e839560	4475	*/
AnnaBridge	163:e59c8e839560	4476	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4477	{
AnnaBridge	163:e59c8e839560	4478	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	163:e59c8e839560	4479	}
AnnaBridge	163:e59c8e839560	4480
AnnaBridge	163:e59c8e839560	4481	/**
AnnaBridge	163:e59c8e839560	4482	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	163:e59c8e839560	4483	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	163:e59c8e839560	4484	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4485	* @retval None
AnnaBridge	163:e59c8e839560	4486	*/
AnnaBridge	163:e59c8e839560	4487	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4488	{
AnnaBridge	163:e59c8e839560	4489	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	163:e59c8e839560	4490	}
AnnaBridge	163:e59c8e839560	4491
AnnaBridge	163:e59c8e839560	4492	/**
AnnaBridge	163:e59c8e839560	4493	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	163:e59c8e839560	4494	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	163:e59c8e839560	4495	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4496	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4497	*/
AnnaBridge	163:e59c8e839560	4498	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4499	{
AnnaBridge	163:e59c8e839560	4500	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	163:e59c8e839560	4501	}
AnnaBridge	163:e59c8e839560	4502
AnnaBridge	163:e59c8e839560	4503	/**
AnnaBridge	163:e59c8e839560	4504	* @brief Enable trigger interrupt (TIE).
AnnaBridge	163:e59c8e839560	4505	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	163:e59c8e839560	4506	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4507	* @retval None
AnnaBridge	163:e59c8e839560	4508	*/
AnnaBridge	163:e59c8e839560	4509	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4510	{
AnnaBridge	163:e59c8e839560	4511	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	163:e59c8e839560	4512	}
AnnaBridge	163:e59c8e839560	4513
AnnaBridge	163:e59c8e839560	4514	/**
AnnaBridge	163:e59c8e839560	4515	* @brief Disable trigger interrupt (TIE).
AnnaBridge	163:e59c8e839560	4516	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	163:e59c8e839560	4517	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4518	* @retval None
AnnaBridge	163:e59c8e839560	4519	*/
AnnaBridge	163:e59c8e839560	4520	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4521	{
AnnaBridge	163:e59c8e839560	4522	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	163:e59c8e839560	4523	}
AnnaBridge	163:e59c8e839560	4524
AnnaBridge	163:e59c8e839560	4525	/**
AnnaBridge	163:e59c8e839560	4526	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	163:e59c8e839560	4527	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	163:e59c8e839560	4528	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4529	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4530	*/
AnnaBridge	163:e59c8e839560	4531	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4532	{
AnnaBridge	163:e59c8e839560	4533	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	163:e59c8e839560	4534	}
AnnaBridge	163:e59c8e839560	4535
AnnaBridge	163:e59c8e839560	4536	/**
AnnaBridge	163:e59c8e839560	4537	* @brief Enable break interrupt (BIE).
AnnaBridge	163:e59c8e839560	4538	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	163:e59c8e839560	4539	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4540	* @retval None
AnnaBridge	163:e59c8e839560	4541	*/
AnnaBridge	163:e59c8e839560	4542	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4543	{
AnnaBridge	163:e59c8e839560	4544	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	163:e59c8e839560	4545	}
AnnaBridge	163:e59c8e839560	4546
AnnaBridge	163:e59c8e839560	4547	/**
AnnaBridge	163:e59c8e839560	4548	* @brief Disable break interrupt (BIE).
AnnaBridge	163:e59c8e839560	4549	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	163:e59c8e839560	4550	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4551	* @retval None
AnnaBridge	163:e59c8e839560	4552	*/
AnnaBridge	163:e59c8e839560	4553	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4554	{
AnnaBridge	163:e59c8e839560	4555	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	163:e59c8e839560	4556	}
AnnaBridge	163:e59c8e839560	4557
AnnaBridge	163:e59c8e839560	4558	/**
AnnaBridge	163:e59c8e839560	4559	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	163:e59c8e839560	4560	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	163:e59c8e839560	4561	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4562	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4563	*/
AnnaBridge	163:e59c8e839560	4564	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4565	{
AnnaBridge	163:e59c8e839560	4566	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	163:e59c8e839560	4567	}
AnnaBridge	163:e59c8e839560	4568
AnnaBridge	163:e59c8e839560	4569	/**
AnnaBridge	163:e59c8e839560	4570	* @}
AnnaBridge	163:e59c8e839560	4571	*/
AnnaBridge	163:e59c8e839560	4572
AnnaBridge	163:e59c8e839560	4573	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	163:e59c8e839560	4574	* @{
AnnaBridge	163:e59c8e839560	4575	*/
AnnaBridge	163:e59c8e839560	4576	/**
AnnaBridge	163:e59c8e839560	4577	* @brief Enable update DMA request (UDE).
AnnaBridge	163:e59c8e839560	4578	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	163:e59c8e839560	4579	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4580	* @retval None
AnnaBridge	163:e59c8e839560	4581	*/
AnnaBridge	163:e59c8e839560	4582	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4583	{
AnnaBridge	163:e59c8e839560	4584	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	163:e59c8e839560	4585	}
AnnaBridge	163:e59c8e839560	4586
AnnaBridge	163:e59c8e839560	4587	/**
AnnaBridge	163:e59c8e839560	4588	* @brief Disable update DMA request (UDE).
AnnaBridge	163:e59c8e839560	4589	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	163:e59c8e839560	4590	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4591	* @retval None
AnnaBridge	163:e59c8e839560	4592	*/
AnnaBridge	163:e59c8e839560	4593	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4594	{
AnnaBridge	163:e59c8e839560	4595	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	163:e59c8e839560	4596	}
AnnaBridge	163:e59c8e839560	4597
AnnaBridge	163:e59c8e839560	4598	/**
AnnaBridge	163:e59c8e839560	4599	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	163:e59c8e839560	4600	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	163:e59c8e839560	4601	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4602	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4603	*/
AnnaBridge	163:e59c8e839560	4604	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4605	{
AnnaBridge	163:e59c8e839560	4606	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	163:e59c8e839560	4607	}
AnnaBridge	163:e59c8e839560	4608
AnnaBridge	163:e59c8e839560	4609	/**
AnnaBridge	163:e59c8e839560	4610	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	163:e59c8e839560	4611	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	163:e59c8e839560	4612	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4613	* @retval None
AnnaBridge	163:e59c8e839560	4614	*/
AnnaBridge	163:e59c8e839560	4615	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4616	{
AnnaBridge	163:e59c8e839560	4617	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	163:e59c8e839560	4618	}
AnnaBridge	163:e59c8e839560	4619
AnnaBridge	163:e59c8e839560	4620	/**
AnnaBridge	163:e59c8e839560	4621	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	163:e59c8e839560	4622	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	163:e59c8e839560	4623	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4624	* @retval None
AnnaBridge	163:e59c8e839560	4625	*/
AnnaBridge	163:e59c8e839560	4626	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4627	{
AnnaBridge	163:e59c8e839560	4628	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	163:e59c8e839560	4629	}
AnnaBridge	163:e59c8e839560	4630
AnnaBridge	163:e59c8e839560	4631	/**
AnnaBridge	163:e59c8e839560	4632	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	163:e59c8e839560	4633	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	163:e59c8e839560	4634	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4635	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4636	*/
AnnaBridge	163:e59c8e839560	4637	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4638	{
AnnaBridge	163:e59c8e839560	4639	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	163:e59c8e839560	4640	}
AnnaBridge	163:e59c8e839560	4641
AnnaBridge	163:e59c8e839560	4642	/**
AnnaBridge	163:e59c8e839560	4643	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	163:e59c8e839560	4644	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	163:e59c8e839560	4645	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4646	* @retval None
AnnaBridge	163:e59c8e839560	4647	*/
AnnaBridge	163:e59c8e839560	4648	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4649	{
AnnaBridge	163:e59c8e839560	4650	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	163:e59c8e839560	4651	}
AnnaBridge	163:e59c8e839560	4652
AnnaBridge	163:e59c8e839560	4653	/**
AnnaBridge	163:e59c8e839560	4654	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	163:e59c8e839560	4655	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	163:e59c8e839560	4656	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4657	* @retval None
AnnaBridge	163:e59c8e839560	4658	*/
AnnaBridge	163:e59c8e839560	4659	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4660	{
AnnaBridge	163:e59c8e839560	4661	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	163:e59c8e839560	4662	}
AnnaBridge	163:e59c8e839560	4663
AnnaBridge	163:e59c8e839560	4664	/**
AnnaBridge	163:e59c8e839560	4665	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	163:e59c8e839560	4666	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	163:e59c8e839560	4667	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4668	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4669	*/
AnnaBridge	163:e59c8e839560	4670	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4671	{
AnnaBridge	163:e59c8e839560	4672	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	163:e59c8e839560	4673	}
AnnaBridge	163:e59c8e839560	4674
AnnaBridge	163:e59c8e839560	4675	/**
AnnaBridge	163:e59c8e839560	4676	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	163:e59c8e839560	4677	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	163:e59c8e839560	4678	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4679	* @retval None
AnnaBridge	163:e59c8e839560	4680	*/
AnnaBridge	163:e59c8e839560	4681	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4682	{
AnnaBridge	163:e59c8e839560	4683	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	163:e59c8e839560	4684	}
AnnaBridge	163:e59c8e839560	4685
AnnaBridge	163:e59c8e839560	4686	/**
AnnaBridge	163:e59c8e839560	4687	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	163:e59c8e839560	4688	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	163:e59c8e839560	4689	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4690	* @retval None
AnnaBridge	163:e59c8e839560	4691	*/
AnnaBridge	163:e59c8e839560	4692	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4693	{
AnnaBridge	163:e59c8e839560	4694	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	163:e59c8e839560	4695	}
AnnaBridge	163:e59c8e839560	4696
AnnaBridge	163:e59c8e839560	4697	/**
AnnaBridge	163:e59c8e839560	4698	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	163:e59c8e839560	4699	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	163:e59c8e839560	4700	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4701	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4702	*/
AnnaBridge	163:e59c8e839560	4703	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4704	{
AnnaBridge	163:e59c8e839560	4705	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	163:e59c8e839560	4706	}
AnnaBridge	163:e59c8e839560	4707
AnnaBridge	163:e59c8e839560	4708	/**
AnnaBridge	163:e59c8e839560	4709	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	163:e59c8e839560	4710	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	163:e59c8e839560	4711	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4712	* @retval None
AnnaBridge	163:e59c8e839560	4713	*/
AnnaBridge	163:e59c8e839560	4714	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4715	{
AnnaBridge	163:e59c8e839560	4716	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	163:e59c8e839560	4717	}
AnnaBridge	163:e59c8e839560	4718
AnnaBridge	163:e59c8e839560	4719	/**
AnnaBridge	163:e59c8e839560	4720	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	163:e59c8e839560	4721	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	163:e59c8e839560	4722	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4723	* @retval None
AnnaBridge	163:e59c8e839560	4724	*/
AnnaBridge	163:e59c8e839560	4725	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4726	{
AnnaBridge	163:e59c8e839560	4727	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	163:e59c8e839560	4728	}
AnnaBridge	163:e59c8e839560	4729
AnnaBridge	163:e59c8e839560	4730	/**
AnnaBridge	163:e59c8e839560	4731	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	163:e59c8e839560	4732	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	163:e59c8e839560	4733	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4734	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4735	*/
AnnaBridge	163:e59c8e839560	4736	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4737	{
AnnaBridge	163:e59c8e839560	4738	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	163:e59c8e839560	4739	}
AnnaBridge	163:e59c8e839560	4740
AnnaBridge	163:e59c8e839560	4741	/**
AnnaBridge	163:e59c8e839560	4742	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	163:e59c8e839560	4743	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	163:e59c8e839560	4744	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4745	* @retval None
AnnaBridge	163:e59c8e839560	4746	*/
AnnaBridge	163:e59c8e839560	4747	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4748	{
AnnaBridge	163:e59c8e839560	4749	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	163:e59c8e839560	4750	}
AnnaBridge	163:e59c8e839560	4751
AnnaBridge	163:e59c8e839560	4752	/**
AnnaBridge	163:e59c8e839560	4753	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	163:e59c8e839560	4754	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	163:e59c8e839560	4755	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4756	* @retval None
AnnaBridge	163:e59c8e839560	4757	*/
AnnaBridge	163:e59c8e839560	4758	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4759	{
AnnaBridge	163:e59c8e839560	4760	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	163:e59c8e839560	4761	}
AnnaBridge	163:e59c8e839560	4762
AnnaBridge	163:e59c8e839560	4763	/**
AnnaBridge	163:e59c8e839560	4764	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	163:e59c8e839560	4765	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	163:e59c8e839560	4766	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4767	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4768	*/
AnnaBridge	163:e59c8e839560	4769	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4770	{
AnnaBridge	163:e59c8e839560	4771	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	163:e59c8e839560	4772	}
AnnaBridge	163:e59c8e839560	4773
AnnaBridge	163:e59c8e839560	4774	/**
AnnaBridge	163:e59c8e839560	4775	* @brief Enable trigger interrupt (TDE).
AnnaBridge	163:e59c8e839560	4776	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	163:e59c8e839560	4777	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4778	* @retval None
AnnaBridge	163:e59c8e839560	4779	*/
AnnaBridge	163:e59c8e839560	4780	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4781	{
AnnaBridge	163:e59c8e839560	4782	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	163:e59c8e839560	4783	}
AnnaBridge	163:e59c8e839560	4784
AnnaBridge	163:e59c8e839560	4785	/**
AnnaBridge	163:e59c8e839560	4786	* @brief Disable trigger interrupt (TDE).
AnnaBridge	163:e59c8e839560	4787	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	163:e59c8e839560	4788	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4789	* @retval None
AnnaBridge	163:e59c8e839560	4790	*/
AnnaBridge	163:e59c8e839560	4791	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4792	{
AnnaBridge	163:e59c8e839560	4793	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	163:e59c8e839560	4794	}
AnnaBridge	163:e59c8e839560	4795
AnnaBridge	163:e59c8e839560	4796	/**
AnnaBridge	163:e59c8e839560	4797	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	163:e59c8e839560	4798	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	163:e59c8e839560	4799	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4800	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	4801	*/
AnnaBridge	163:e59c8e839560	4802	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4803	{
AnnaBridge	163:e59c8e839560	4804	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	163:e59c8e839560	4805	}
AnnaBridge	163:e59c8e839560	4806
AnnaBridge	163:e59c8e839560	4807	/**
AnnaBridge	163:e59c8e839560	4808	* @}
AnnaBridge	163:e59c8e839560	4809	*/
AnnaBridge	163:e59c8e839560	4810
AnnaBridge	163:e59c8e839560	4811	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	163:e59c8e839560	4812	* @{
AnnaBridge	163:e59c8e839560	4813	*/
AnnaBridge	163:e59c8e839560	4814	/**
AnnaBridge	163:e59c8e839560	4815	* @brief Generate an update event.
AnnaBridge	163:e59c8e839560	4816	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	163:e59c8e839560	4817	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4818	* @retval None
AnnaBridge	163:e59c8e839560	4819	*/
AnnaBridge	163:e59c8e839560	4820	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4821	{
AnnaBridge	163:e59c8e839560	4822	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	163:e59c8e839560	4823	}
AnnaBridge	163:e59c8e839560	4824
AnnaBridge	163:e59c8e839560	4825	/**
AnnaBridge	163:e59c8e839560	4826	* @brief Generate Capture/Compare 1 event.
AnnaBridge	163:e59c8e839560	4827	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	163:e59c8e839560	4828	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4829	* @retval None
AnnaBridge	163:e59c8e839560	4830	*/
AnnaBridge	163:e59c8e839560	4831	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4832	{
AnnaBridge	163:e59c8e839560	4833	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	163:e59c8e839560	4834	}
AnnaBridge	163:e59c8e839560	4835
AnnaBridge	163:e59c8e839560	4836	/**
AnnaBridge	163:e59c8e839560	4837	* @brief Generate Capture/Compare 2 event.
AnnaBridge	163:e59c8e839560	4838	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	163:e59c8e839560	4839	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4840	* @retval None
AnnaBridge	163:e59c8e839560	4841	*/
AnnaBridge	163:e59c8e839560	4842	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4843	{
AnnaBridge	163:e59c8e839560	4844	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	163:e59c8e839560	4845	}
AnnaBridge	163:e59c8e839560	4846
AnnaBridge	163:e59c8e839560	4847	/**
AnnaBridge	163:e59c8e839560	4848	* @brief Generate Capture/Compare 3 event.
AnnaBridge	163:e59c8e839560	4849	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	163:e59c8e839560	4850	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4851	* @retval None
AnnaBridge	163:e59c8e839560	4852	*/
AnnaBridge	163:e59c8e839560	4853	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4854	{
AnnaBridge	163:e59c8e839560	4855	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	163:e59c8e839560	4856	}
AnnaBridge	163:e59c8e839560	4857
AnnaBridge	163:e59c8e839560	4858	/**
AnnaBridge	163:e59c8e839560	4859	* @brief Generate Capture/Compare 4 event.
AnnaBridge	163:e59c8e839560	4860	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	163:e59c8e839560	4861	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4862	* @retval None
AnnaBridge	163:e59c8e839560	4863	*/
AnnaBridge	163:e59c8e839560	4864	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4865	{
AnnaBridge	163:e59c8e839560	4866	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	163:e59c8e839560	4867	}
AnnaBridge	163:e59c8e839560	4868
AnnaBridge	163:e59c8e839560	4869	/**
AnnaBridge	163:e59c8e839560	4870	* @brief Generate commutation event.
AnnaBridge	163:e59c8e839560	4871	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	163:e59c8e839560	4872	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4873	* @retval None
AnnaBridge	163:e59c8e839560	4874	*/
AnnaBridge	163:e59c8e839560	4875	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4876	{
AnnaBridge	163:e59c8e839560	4877	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	163:e59c8e839560	4878	}
AnnaBridge	163:e59c8e839560	4879
AnnaBridge	163:e59c8e839560	4880	/**
AnnaBridge	163:e59c8e839560	4881	* @brief Generate trigger event.
AnnaBridge	163:e59c8e839560	4882	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	163:e59c8e839560	4883	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4884	* @retval None
AnnaBridge	163:e59c8e839560	4885	*/
AnnaBridge	163:e59c8e839560	4886	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4887	{
AnnaBridge	163:e59c8e839560	4888	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	163:e59c8e839560	4889	}
AnnaBridge	163:e59c8e839560	4890
AnnaBridge	163:e59c8e839560	4891	/**
AnnaBridge	163:e59c8e839560	4892	* @brief Generate break event.
AnnaBridge	163:e59c8e839560	4893	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	163:e59c8e839560	4894	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4895	* @retval None
AnnaBridge	163:e59c8e839560	4896	*/
AnnaBridge	163:e59c8e839560	4897	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4898	{
AnnaBridge	163:e59c8e839560	4899	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	163:e59c8e839560	4900	}
AnnaBridge	163:e59c8e839560	4901
AnnaBridge	163:e59c8e839560	4902	#if defined(TIM_EGR_B2G)
AnnaBridge	163:e59c8e839560	4903	/**
AnnaBridge	163:e59c8e839560	4904	* @brief Generate break 2 event.
AnnaBridge	163:e59c8e839560	4905	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
AnnaBridge	163:e59c8e839560	4906	* @param TIMx Timer instance
AnnaBridge	163:e59c8e839560	4907	* @retval None
AnnaBridge	163:e59c8e839560	4908	*/
AnnaBridge	163:e59c8e839560	4909	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	163:e59c8e839560	4910	{
AnnaBridge	163:e59c8e839560	4911	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
AnnaBridge	163:e59c8e839560	4912	}
AnnaBridge	163:e59c8e839560	4913
AnnaBridge	163:e59c8e839560	4914	#endif /* TIM_EGR_B2G */
AnnaBridge	163:e59c8e839560	4915	/**
AnnaBridge	163:e59c8e839560	4916	* @}
AnnaBridge	163:e59c8e839560	4917	*/
AnnaBridge	163:e59c8e839560	4918
AnnaBridge	163:e59c8e839560	4919	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	4920	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	163:e59c8e839560	4921	* @{
AnnaBridge	163:e59c8e839560	4922	*/
AnnaBridge	163:e59c8e839560	4923
AnnaBridge	163:e59c8e839560	4924	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	163:e59c8e839560	4925	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	163:e59c8e839560	4926	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	163:e59c8e839560	4927	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	163:e59c8e839560	4928	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	163:e59c8e839560	4929	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	163:e59c8e839560	4930	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	163:e59c8e839560	4931	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	163:e59c8e839560	4932	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	163:e59c8e839560	4933	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	163:e59c8e839560	4934	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	163:e59c8e839560	4935	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	163:e59c8e839560	4936	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	163:e59c8e839560	4937	/**
AnnaBridge	163:e59c8e839560	4938	* @}
AnnaBridge	163:e59c8e839560	4939	*/
AnnaBridge	163:e59c8e839560	4940	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	4941
AnnaBridge	163:e59c8e839560	4942	/**
AnnaBridge	163:e59c8e839560	4943	* @}
AnnaBridge	163:e59c8e839560	4944	*/
AnnaBridge	163:e59c8e839560	4945
AnnaBridge	163:e59c8e839560	4946	/**
AnnaBridge	163:e59c8e839560	4947	* @}
AnnaBridge	163:e59c8e839560	4948	*/
AnnaBridge	163:e59c8e839560	4949
AnnaBridge	163:e59c8e839560	4950	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM18 \|\| TIM19 \|\| TIM20 */
AnnaBridge	163:e59c8e839560	4951
AnnaBridge	163:e59c8e839560	4952	/**
AnnaBridge	163:e59c8e839560	4953	* @}
AnnaBridge	163:e59c8e839560	4954	*/
AnnaBridge	163:e59c8e839560	4955
AnnaBridge	163:e59c8e839560	4956	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	4957	}
AnnaBridge	163:e59c8e839560	4958	#endif
AnnaBridge	163:e59c8e839560	4959
AnnaBridge	163:e59c8e839560	4960	#endif /* __STM32F3xx_LL_TIM_H */
AnnaBridge	163:e59c8e839560	4961	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/