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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_ll_spi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_spi.h@168:b9e159c1930a

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32f3xx_ll_spi.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief Header file of SPI LL module.
AnnaBridge	163:e59c8e839560	6	******************************************************************************
AnnaBridge	163:e59c8e839560	7	* @attention
AnnaBridge	163:e59c8e839560	8	*
AnnaBridge	163:e59c8e839560	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	10	*
AnnaBridge	163:e59c8e839560	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	12	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	14	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	17	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	19	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	20	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	21	*
AnnaBridge	163:e59c8e839560	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	32	*
AnnaBridge	163:e59c8e839560	33	******************************************************************************
AnnaBridge	163:e59c8e839560	34	*/
AnnaBridge	163:e59c8e839560	35
AnnaBridge	163:e59c8e839560	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	37	#ifndef __STM32F3xx_LL_SPI_H
AnnaBridge	163:e59c8e839560	38	#define __STM32F3xx_LL_SPI_H
AnnaBridge	163:e59c8e839560	39
AnnaBridge	163:e59c8e839560	40	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	41	extern "C" {
AnnaBridge	163:e59c8e839560	42	#endif
AnnaBridge	163:e59c8e839560	43
AnnaBridge	163:e59c8e839560	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	45	#include "stm32f3xx.h"
AnnaBridge	163:e59c8e839560	46
AnnaBridge	163:e59c8e839560	47	/** @addtogroup STM32F3xx_LL_Driver
AnnaBridge	163:e59c8e839560	48	* @{
AnnaBridge	163:e59c8e839560	49	*/
AnnaBridge	163:e59c8e839560	50
AnnaBridge	163:e59c8e839560	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4)
AnnaBridge	163:e59c8e839560	52
AnnaBridge	163:e59c8e839560	53	/** @defgroup SPI_LL SPI
AnnaBridge	163:e59c8e839560	54	* @{
AnnaBridge	163:e59c8e839560	55	*/
AnnaBridge	163:e59c8e839560	56
AnnaBridge	163:e59c8e839560	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	60
AnnaBridge	163:e59c8e839560	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	163:e59c8e839560	64	* @{
AnnaBridge	163:e59c8e839560	65	*/
AnnaBridge	163:e59c8e839560	66
AnnaBridge	163:e59c8e839560	67	/**
AnnaBridge	163:e59c8e839560	68	* @brief SPI Init structures definition
AnnaBridge	163:e59c8e839560	69	*/
AnnaBridge	163:e59c8e839560	70	typedef struct
AnnaBridge	163:e59c8e839560	71	{
AnnaBridge	163:e59c8e839560	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	163:e59c8e839560	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	163:e59c8e839560	74
AnnaBridge	163:e59c8e839560	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	163:e59c8e839560	76
AnnaBridge	163:e59c8e839560	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	163:e59c8e839560	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	163:e59c8e839560	79
AnnaBridge	163:e59c8e839560	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	163:e59c8e839560	81
AnnaBridge	163:e59c8e839560	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	163:e59c8e839560	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	163:e59c8e839560	84
AnnaBridge	163:e59c8e839560	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	163:e59c8e839560	86
AnnaBridge	163:e59c8e839560	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	163:e59c8e839560	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	163:e59c8e839560	89
AnnaBridge	163:e59c8e839560	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	163:e59c8e839560	91
AnnaBridge	163:e59c8e839560	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	163:e59c8e839560	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	163:e59c8e839560	94
AnnaBridge	163:e59c8e839560	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	163:e59c8e839560	96
AnnaBridge	163:e59c8e839560	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	163:e59c8e839560	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	163:e59c8e839560	99
AnnaBridge	163:e59c8e839560	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	163:e59c8e839560	101
AnnaBridge	163:e59c8e839560	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	163:e59c8e839560	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	163:e59c8e839560	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	163:e59c8e839560	105
AnnaBridge	163:e59c8e839560	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	163:e59c8e839560	107
AnnaBridge	163:e59c8e839560	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	163:e59c8e839560	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	163:e59c8e839560	110
AnnaBridge	163:e59c8e839560	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	163:e59c8e839560	112
AnnaBridge	163:e59c8e839560	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	163:e59c8e839560	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	163:e59c8e839560	115
AnnaBridge	163:e59c8e839560	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	163:e59c8e839560	117
AnnaBridge	163:e59c8e839560	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	163:e59c8e839560	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	163:e59c8e839560	120
AnnaBridge	163:e59c8e839560	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	163:e59c8e839560	122
AnnaBridge	163:e59c8e839560	123	} LL_SPI_InitTypeDef;
AnnaBridge	163:e59c8e839560	124
AnnaBridge	163:e59c8e839560	125	/**
AnnaBridge	163:e59c8e839560	126	* @}
AnnaBridge	163:e59c8e839560	127	*/
AnnaBridge	163:e59c8e839560	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	129
AnnaBridge	163:e59c8e839560	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	163:e59c8e839560	132	* @{
AnnaBridge	163:e59c8e839560	133	*/
AnnaBridge	163:e59c8e839560	134
AnnaBridge	163:e59c8e839560	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	163:e59c8e839560	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	163:e59c8e839560	137	* @{
AnnaBridge	163:e59c8e839560	138	*/
AnnaBridge	163:e59c8e839560	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	163:e59c8e839560	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	163:e59c8e839560	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	163:e59c8e839560	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	163:e59c8e839560	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	163:e59c8e839560	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	163:e59c8e839560	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	163:e59c8e839560	146	/**
AnnaBridge	163:e59c8e839560	147	* @}
AnnaBridge	163:e59c8e839560	148	*/
AnnaBridge	163:e59c8e839560	149
AnnaBridge	163:e59c8e839560	150	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	163:e59c8e839560	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	163:e59c8e839560	152	* @{
AnnaBridge	163:e59c8e839560	153	*/
AnnaBridge	163:e59c8e839560	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	163:e59c8e839560	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	163:e59c8e839560	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	163:e59c8e839560	157	/**
AnnaBridge	163:e59c8e839560	158	* @}
AnnaBridge	163:e59c8e839560	159	*/
AnnaBridge	163:e59c8e839560	160
AnnaBridge	163:e59c8e839560	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	163:e59c8e839560	162	* @{
AnnaBridge	163:e59c8e839560	163	*/
AnnaBridge	163:e59c8e839560	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	163:e59c8e839560	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	163:e59c8e839560	166	/**
AnnaBridge	163:e59c8e839560	167	* @}
AnnaBridge	163:e59c8e839560	168	*/
AnnaBridge	163:e59c8e839560	169
AnnaBridge	163:e59c8e839560	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	163:e59c8e839560	171	* @{
AnnaBridge	163:e59c8e839560	172	*/
AnnaBridge	163:e59c8e839560	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	163:e59c8e839560	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	163:e59c8e839560	175	/**
AnnaBridge	163:e59c8e839560	176	* @}
AnnaBridge	163:e59c8e839560	177	*/
AnnaBridge	163:e59c8e839560	178
AnnaBridge	163:e59c8e839560	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	163:e59c8e839560	180	* @{
AnnaBridge	163:e59c8e839560	181	*/
AnnaBridge	163:e59c8e839560	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	163:e59c8e839560	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	163:e59c8e839560	184	/**
AnnaBridge	163:e59c8e839560	185	* @}
AnnaBridge	163:e59c8e839560	186	*/
AnnaBridge	163:e59c8e839560	187
AnnaBridge	163:e59c8e839560	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	163:e59c8e839560	189	* @{
AnnaBridge	163:e59c8e839560	190	*/
AnnaBridge	163:e59c8e839560	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	163:e59c8e839560	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	163:e59c8e839560	193	/**
AnnaBridge	163:e59c8e839560	194	* @}
AnnaBridge	163:e59c8e839560	195	*/
AnnaBridge	163:e59c8e839560	196
AnnaBridge	163:e59c8e839560	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	163:e59c8e839560	198	* @{
AnnaBridge	163:e59c8e839560	199	*/
AnnaBridge	163:e59c8e839560	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	163:e59c8e839560	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	163:e59c8e839560	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	163:e59c8e839560	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	163:e59c8e839560	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	163:e59c8e839560	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	163:e59c8e839560	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	163:e59c8e839560	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	163:e59c8e839560	208	/**
AnnaBridge	163:e59c8e839560	209	* @}
AnnaBridge	163:e59c8e839560	210	*/
AnnaBridge	163:e59c8e839560	211
AnnaBridge	163:e59c8e839560	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	163:e59c8e839560	213	* @{
AnnaBridge	163:e59c8e839560	214	*/
AnnaBridge	163:e59c8e839560	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	163:e59c8e839560	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	163:e59c8e839560	217	/**
AnnaBridge	163:e59c8e839560	218	* @}
AnnaBridge	163:e59c8e839560	219	*/
AnnaBridge	163:e59c8e839560	220
AnnaBridge	163:e59c8e839560	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	163:e59c8e839560	222	* @{
AnnaBridge	163:e59c8e839560	223	*/
AnnaBridge	163:e59c8e839560	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	163:e59c8e839560	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	163:e59c8e839560	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	163:e59c8e839560	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	163:e59c8e839560	228	/**
AnnaBridge	163:e59c8e839560	229	* @}
AnnaBridge	163:e59c8e839560	230	*/
AnnaBridge	163:e59c8e839560	231
AnnaBridge	163:e59c8e839560	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	163:e59c8e839560	233	* @{
AnnaBridge	163:e59c8e839560	234	*/
AnnaBridge	163:e59c8e839560	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	163:e59c8e839560	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	163:e59c8e839560	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	163:e59c8e839560	238	/**
AnnaBridge	163:e59c8e839560	239	* @}
AnnaBridge	163:e59c8e839560	240	*/
AnnaBridge	163:e59c8e839560	241
AnnaBridge	163:e59c8e839560	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	163:e59c8e839560	243	* @{
AnnaBridge	163:e59c8e839560	244	*/
AnnaBridge	163:e59c8e839560	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
AnnaBridge	163:e59c8e839560	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
AnnaBridge	163:e59c8e839560	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
AnnaBridge	163:e59c8e839560	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
AnnaBridge	163:e59c8e839560	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	163:e59c8e839560	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
AnnaBridge	163:e59c8e839560	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
AnnaBridge	163:e59c8e839560	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
AnnaBridge	163:e59c8e839560	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
AnnaBridge	163:e59c8e839560	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
AnnaBridge	163:e59c8e839560	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
AnnaBridge	163:e59c8e839560	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
AnnaBridge	163:e59c8e839560	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	163:e59c8e839560	258	/**
AnnaBridge	163:e59c8e839560	259	* @}
AnnaBridge	163:e59c8e839560	260	*/
AnnaBridge	163:e59c8e839560	261	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	262
AnnaBridge	163:e59c8e839560	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	163:e59c8e839560	264	* @{
AnnaBridge	163:e59c8e839560	265	*/
AnnaBridge	163:e59c8e839560	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	163:e59c8e839560	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	163:e59c8e839560	268	/**
AnnaBridge	163:e59c8e839560	269	* @}
AnnaBridge	163:e59c8e839560	270	*/
AnnaBridge	163:e59c8e839560	271	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	272
AnnaBridge	163:e59c8e839560	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
AnnaBridge	163:e59c8e839560	274	* @{
AnnaBridge	163:e59c8e839560	275	*/
AnnaBridge	163:e59c8e839560	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
AnnaBridge	163:e59c8e839560	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
AnnaBridge	163:e59c8e839560	278	/**
AnnaBridge	163:e59c8e839560	279	* @}
AnnaBridge	163:e59c8e839560	280	*/
AnnaBridge	163:e59c8e839560	281
AnnaBridge	163:e59c8e839560	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
AnnaBridge	163:e59c8e839560	283	* @{
AnnaBridge	163:e59c8e839560	284	*/
AnnaBridge	163:e59c8e839560	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
AnnaBridge	163:e59c8e839560	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
AnnaBridge	163:e59c8e839560	287	/**
AnnaBridge	163:e59c8e839560	288	* @}
AnnaBridge	163:e59c8e839560	289	*/
AnnaBridge	163:e59c8e839560	290
AnnaBridge	163:e59c8e839560	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
AnnaBridge	163:e59c8e839560	292	* @{
AnnaBridge	163:e59c8e839560	293	*/
AnnaBridge	163:e59c8e839560	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
AnnaBridge	163:e59c8e839560	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
AnnaBridge	163:e59c8e839560	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
AnnaBridge	163:e59c8e839560	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
AnnaBridge	163:e59c8e839560	298	/**
AnnaBridge	163:e59c8e839560	299	* @}
AnnaBridge	163:e59c8e839560	300	*/
AnnaBridge	163:e59c8e839560	301
AnnaBridge	163:e59c8e839560	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
AnnaBridge	163:e59c8e839560	303	* @{
AnnaBridge	163:e59c8e839560	304	*/
AnnaBridge	163:e59c8e839560	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
AnnaBridge	163:e59c8e839560	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
AnnaBridge	163:e59c8e839560	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
AnnaBridge	163:e59c8e839560	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
AnnaBridge	163:e59c8e839560	309	/**
AnnaBridge	163:e59c8e839560	310	* @}
AnnaBridge	163:e59c8e839560	311	*/
AnnaBridge	163:e59c8e839560	312
AnnaBridge	163:e59c8e839560	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
AnnaBridge	163:e59c8e839560	314	* @{
AnnaBridge	163:e59c8e839560	315	*/
AnnaBridge	163:e59c8e839560	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
AnnaBridge	163:e59c8e839560	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
AnnaBridge	163:e59c8e839560	318
AnnaBridge	163:e59c8e839560	319	/**
AnnaBridge	163:e59c8e839560	320	* @}
AnnaBridge	163:e59c8e839560	321	*/
AnnaBridge	163:e59c8e839560	322
AnnaBridge	163:e59c8e839560	323	/**
AnnaBridge	163:e59c8e839560	324	* @}
AnnaBridge	163:e59c8e839560	325	*/
AnnaBridge	163:e59c8e839560	326
AnnaBridge	163:e59c8e839560	327	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	163:e59c8e839560	329	* @{
AnnaBridge	163:e59c8e839560	330	*/
AnnaBridge	163:e59c8e839560	331
AnnaBridge	163:e59c8e839560	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	163:e59c8e839560	333	* @{
AnnaBridge	163:e59c8e839560	334	*/
AnnaBridge	163:e59c8e839560	335
AnnaBridge	163:e59c8e839560	336	/**
AnnaBridge	163:e59c8e839560	337	* @brief Write a value in SPI register
AnnaBridge	163:e59c8e839560	338	* @param __INSTANCE__ SPI Instance
AnnaBridge	163:e59c8e839560	339	* @param __REG__ Register to be written
AnnaBridge	163:e59c8e839560	340	* @param __VALUE__ Value to be written in the register
AnnaBridge	163:e59c8e839560	341	* @retval None
AnnaBridge	163:e59c8e839560	342	*/
AnnaBridge	163:e59c8e839560	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	163:e59c8e839560	344
AnnaBridge	163:e59c8e839560	345	/**
AnnaBridge	163:e59c8e839560	346	* @brief Read a value in SPI register
AnnaBridge	163:e59c8e839560	347	* @param __INSTANCE__ SPI Instance
AnnaBridge	163:e59c8e839560	348	* @param __REG__ Register to be read
AnnaBridge	163:e59c8e839560	349	* @retval Register value
AnnaBridge	163:e59c8e839560	350	*/
AnnaBridge	163:e59c8e839560	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	163:e59c8e839560	352	/**
AnnaBridge	163:e59c8e839560	353	* @}
AnnaBridge	163:e59c8e839560	354	*/
AnnaBridge	163:e59c8e839560	355
AnnaBridge	163:e59c8e839560	356	/**
AnnaBridge	163:e59c8e839560	357	* @}
AnnaBridge	163:e59c8e839560	358	*/
AnnaBridge	163:e59c8e839560	359
AnnaBridge	163:e59c8e839560	360	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	163:e59c8e839560	362	* @{
AnnaBridge	163:e59c8e839560	363	*/
AnnaBridge	163:e59c8e839560	364
AnnaBridge	163:e59c8e839560	365	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	163:e59c8e839560	366	* @{
AnnaBridge	163:e59c8e839560	367	*/
AnnaBridge	163:e59c8e839560	368
AnnaBridge	163:e59c8e839560	369	/**
AnnaBridge	163:e59c8e839560	370	* @brief Enable SPI peripheral
AnnaBridge	163:e59c8e839560	371	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	163:e59c8e839560	372	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	373	* @retval None
AnnaBridge	163:e59c8e839560	374	*/
AnnaBridge	163:e59c8e839560	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	376	{
AnnaBridge	163:e59c8e839560	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	163:e59c8e839560	378	}
AnnaBridge	163:e59c8e839560	379
AnnaBridge	163:e59c8e839560	380	/**
AnnaBridge	163:e59c8e839560	381	* @brief Disable SPI peripheral
AnnaBridge	163:e59c8e839560	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	163:e59c8e839560	383	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	163:e59c8e839560	384	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	385	* @retval None
AnnaBridge	163:e59c8e839560	386	*/
AnnaBridge	163:e59c8e839560	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	388	{
AnnaBridge	163:e59c8e839560	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	163:e59c8e839560	390	}
AnnaBridge	163:e59c8e839560	391
AnnaBridge	163:e59c8e839560	392	/**
AnnaBridge	163:e59c8e839560	393	* @brief Check if SPI peripheral is enabled
AnnaBridge	163:e59c8e839560	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	163:e59c8e839560	395	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	396	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	397	*/
AnnaBridge	163:e59c8e839560	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	399	{
AnnaBridge	163:e59c8e839560	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	163:e59c8e839560	401	}
AnnaBridge	163:e59c8e839560	402
AnnaBridge	163:e59c8e839560	403	/**
AnnaBridge	163:e59c8e839560	404	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	163:e59c8e839560	405	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	163:e59c8e839560	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	163:e59c8e839560	407	* CR1 SSI LL_SPI_SetMode
AnnaBridge	163:e59c8e839560	408	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	409	* @param Mode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	410	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	163:e59c8e839560	411	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	163:e59c8e839560	412	* @retval None
AnnaBridge	163:e59c8e839560	413	*/
AnnaBridge	163:e59c8e839560	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	163:e59c8e839560	415	{
AnnaBridge	163:e59c8e839560	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	163:e59c8e839560	417	}
AnnaBridge	163:e59c8e839560	418
AnnaBridge	163:e59c8e839560	419	/**
AnnaBridge	163:e59c8e839560	420	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	163:e59c8e839560	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	163:e59c8e839560	422	* CR1 SSI LL_SPI_GetMode
AnnaBridge	163:e59c8e839560	423	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	424	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	425	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	163:e59c8e839560	426	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	163:e59c8e839560	427	*/
AnnaBridge	163:e59c8e839560	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	429	{
AnnaBridge	163:e59c8e839560	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	163:e59c8e839560	431	}
AnnaBridge	163:e59c8e839560	432
AnnaBridge	163:e59c8e839560	433	/**
AnnaBridge	163:e59c8e839560	434	* @brief Set serial protocol used
AnnaBridge	163:e59c8e839560	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	163:e59c8e839560	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	163:e59c8e839560	437	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	438	* @param Standard This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	163:e59c8e839560	440	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	163:e59c8e839560	441	* @retval None
AnnaBridge	163:e59c8e839560	442	*/
AnnaBridge	163:e59c8e839560	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	163:e59c8e839560	444	{
AnnaBridge	163:e59c8e839560	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	163:e59c8e839560	446	}
AnnaBridge	163:e59c8e839560	447
AnnaBridge	163:e59c8e839560	448	/**
AnnaBridge	163:e59c8e839560	449	* @brief Get serial protocol used
AnnaBridge	163:e59c8e839560	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	163:e59c8e839560	451	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	452	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	163:e59c8e839560	454	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	163:e59c8e839560	455	*/
AnnaBridge	163:e59c8e839560	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	457	{
AnnaBridge	163:e59c8e839560	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	163:e59c8e839560	459	}
AnnaBridge	163:e59c8e839560	460
AnnaBridge	163:e59c8e839560	461	/**
AnnaBridge	163:e59c8e839560	462	* @brief Set clock phase
AnnaBridge	163:e59c8e839560	463	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	163:e59c8e839560	464	* This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	163:e59c8e839560	466	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	467	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	468	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	163:e59c8e839560	469	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	163:e59c8e839560	470	* @retval None
AnnaBridge	163:e59c8e839560	471	*/
AnnaBridge	163:e59c8e839560	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	163:e59c8e839560	473	{
AnnaBridge	163:e59c8e839560	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	163:e59c8e839560	475	}
AnnaBridge	163:e59c8e839560	476
AnnaBridge	163:e59c8e839560	477	/**
AnnaBridge	163:e59c8e839560	478	* @brief Get clock phase
AnnaBridge	163:e59c8e839560	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	163:e59c8e839560	480	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	481	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	482	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	163:e59c8e839560	483	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	163:e59c8e839560	484	*/
AnnaBridge	163:e59c8e839560	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	486	{
AnnaBridge	163:e59c8e839560	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	163:e59c8e839560	488	}
AnnaBridge	163:e59c8e839560	489
AnnaBridge	163:e59c8e839560	490	/**
AnnaBridge	163:e59c8e839560	491	* @brief Set clock polarity
AnnaBridge	163:e59c8e839560	492	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	163:e59c8e839560	493	* This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	163:e59c8e839560	495	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	496	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	497	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	163:e59c8e839560	498	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	499	* @retval None
AnnaBridge	163:e59c8e839560	500	*/
AnnaBridge	163:e59c8e839560	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	163:e59c8e839560	502	{
AnnaBridge	163:e59c8e839560	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	163:e59c8e839560	504	}
AnnaBridge	163:e59c8e839560	505
AnnaBridge	163:e59c8e839560	506	/**
AnnaBridge	163:e59c8e839560	507	* @brief Get clock polarity
AnnaBridge	163:e59c8e839560	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	163:e59c8e839560	509	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	510	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	511	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	163:e59c8e839560	512	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	513	*/
AnnaBridge	163:e59c8e839560	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	515	{
AnnaBridge	163:e59c8e839560	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	163:e59c8e839560	517	}
AnnaBridge	163:e59c8e839560	518
AnnaBridge	163:e59c8e839560	519	/**
AnnaBridge	163:e59c8e839560	520	* @brief Set baud rate prescaler
AnnaBridge	163:e59c8e839560	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	163:e59c8e839560	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	163:e59c8e839560	523	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	524	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	163:e59c8e839560	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	163:e59c8e839560	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	163:e59c8e839560	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	163:e59c8e839560	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	163:e59c8e839560	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	163:e59c8e839560	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	163:e59c8e839560	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	163:e59c8e839560	533	* @retval None
AnnaBridge	163:e59c8e839560	534	*/
AnnaBridge	163:e59c8e839560	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	163:e59c8e839560	536	{
AnnaBridge	163:e59c8e839560	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	163:e59c8e839560	538	}
AnnaBridge	163:e59c8e839560	539
AnnaBridge	163:e59c8e839560	540	/**
AnnaBridge	163:e59c8e839560	541	* @brief Get baud rate prescaler
AnnaBridge	163:e59c8e839560	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	163:e59c8e839560	543	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	544	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	163:e59c8e839560	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	163:e59c8e839560	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	163:e59c8e839560	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	163:e59c8e839560	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	163:e59c8e839560	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	163:e59c8e839560	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	163:e59c8e839560	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	163:e59c8e839560	553	*/
AnnaBridge	163:e59c8e839560	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	555	{
AnnaBridge	163:e59c8e839560	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	163:e59c8e839560	557	}
AnnaBridge	163:e59c8e839560	558
AnnaBridge	163:e59c8e839560	559	/**
AnnaBridge	163:e59c8e839560	560	* @brief Set transfer bit order
AnnaBridge	163:e59c8e839560	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	163:e59c8e839560	563	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	564	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	565	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	163:e59c8e839560	566	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	163:e59c8e839560	567	* @retval None
AnnaBridge	163:e59c8e839560	568	*/
AnnaBridge	163:e59c8e839560	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	163:e59c8e839560	570	{
AnnaBridge	163:e59c8e839560	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	163:e59c8e839560	572	}
AnnaBridge	163:e59c8e839560	573
AnnaBridge	163:e59c8e839560	574	/**
AnnaBridge	163:e59c8e839560	575	* @brief Get transfer bit order
AnnaBridge	163:e59c8e839560	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	163:e59c8e839560	577	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	578	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	579	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	163:e59c8e839560	580	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	163:e59c8e839560	581	*/
AnnaBridge	163:e59c8e839560	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	583	{
AnnaBridge	163:e59c8e839560	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	163:e59c8e839560	585	}
AnnaBridge	163:e59c8e839560	586
AnnaBridge	163:e59c8e839560	587	/**
AnnaBridge	163:e59c8e839560	588	* @brief Set transfer direction mode
AnnaBridge	163:e59c8e839560	589	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	163:e59c8e839560	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	163:e59c8e839560	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	163:e59c8e839560	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	163:e59c8e839560	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	163:e59c8e839560	594	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	595	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	596	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	163:e59c8e839560	597	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	163:e59c8e839560	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	163:e59c8e839560	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	163:e59c8e839560	600	* @retval None
AnnaBridge	163:e59c8e839560	601	*/
AnnaBridge	163:e59c8e839560	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	163:e59c8e839560	603	{
AnnaBridge	163:e59c8e839560	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	163:e59c8e839560	605	}
AnnaBridge	163:e59c8e839560	606
AnnaBridge	163:e59c8e839560	607	/**
AnnaBridge	163:e59c8e839560	608	* @brief Get transfer direction mode
AnnaBridge	163:e59c8e839560	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	163:e59c8e839560	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	163:e59c8e839560	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	163:e59c8e839560	612	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	613	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	614	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	163:e59c8e839560	615	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	163:e59c8e839560	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	163:e59c8e839560	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	163:e59c8e839560	618	*/
AnnaBridge	163:e59c8e839560	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	620	{
AnnaBridge	163:e59c8e839560	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	163:e59c8e839560	622	}
AnnaBridge	163:e59c8e839560	623
AnnaBridge	163:e59c8e839560	624	/**
AnnaBridge	163:e59c8e839560	625	* @brief Set frame data width
AnnaBridge	163:e59c8e839560	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
AnnaBridge	163:e59c8e839560	627	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	628	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	163:e59c8e839560	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	163:e59c8e839560	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	163:e59c8e839560	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	163:e59c8e839560	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	163:e59c8e839560	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	163:e59c8e839560	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	163:e59c8e839560	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	163:e59c8e839560	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	163:e59c8e839560	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	163:e59c8e839560	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	163:e59c8e839560	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	163:e59c8e839560	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	163:e59c8e839560	642	* @retval None
AnnaBridge	163:e59c8e839560	643	*/
AnnaBridge	163:e59c8e839560	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	163:e59c8e839560	645	{
AnnaBridge	163:e59c8e839560	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
AnnaBridge	163:e59c8e839560	647	}
AnnaBridge	163:e59c8e839560	648
AnnaBridge	163:e59c8e839560	649	/**
AnnaBridge	163:e59c8e839560	650	* @brief Get frame data width
AnnaBridge	163:e59c8e839560	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
AnnaBridge	163:e59c8e839560	652	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	653	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	163:e59c8e839560	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	163:e59c8e839560	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	163:e59c8e839560	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	163:e59c8e839560	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	163:e59c8e839560	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	163:e59c8e839560	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	163:e59c8e839560	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	163:e59c8e839560	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	163:e59c8e839560	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	163:e59c8e839560	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	163:e59c8e839560	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	163:e59c8e839560	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	163:e59c8e839560	667	*/
AnnaBridge	163:e59c8e839560	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	669	{
AnnaBridge	163:e59c8e839560	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
AnnaBridge	163:e59c8e839560	671	}
AnnaBridge	163:e59c8e839560	672
AnnaBridge	163:e59c8e839560	673	/**
AnnaBridge	163:e59c8e839560	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
AnnaBridge	163:e59c8e839560	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
AnnaBridge	163:e59c8e839560	676	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	677	* @param Threshold This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	163:e59c8e839560	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	163:e59c8e839560	680	* @retval None
AnnaBridge	163:e59c8e839560	681	*/
AnnaBridge	163:e59c8e839560	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	163:e59c8e839560	683	{
AnnaBridge	163:e59c8e839560	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
AnnaBridge	163:e59c8e839560	685	}
AnnaBridge	163:e59c8e839560	686
AnnaBridge	163:e59c8e839560	687	/**
AnnaBridge	163:e59c8e839560	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
AnnaBridge	163:e59c8e839560	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
AnnaBridge	163:e59c8e839560	690	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	691	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	163:e59c8e839560	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	163:e59c8e839560	694	*/
AnnaBridge	163:e59c8e839560	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	696	{
AnnaBridge	163:e59c8e839560	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
AnnaBridge	163:e59c8e839560	698	}
AnnaBridge	163:e59c8e839560	699
AnnaBridge	163:e59c8e839560	700	/**
AnnaBridge	163:e59c8e839560	701	* @}
AnnaBridge	163:e59c8e839560	702	*/
AnnaBridge	163:e59c8e839560	703
AnnaBridge	163:e59c8e839560	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	163:e59c8e839560	705	* @{
AnnaBridge	163:e59c8e839560	706	*/
AnnaBridge	163:e59c8e839560	707
AnnaBridge	163:e59c8e839560	708	/**
AnnaBridge	163:e59c8e839560	709	* @brief Enable CRC
AnnaBridge	163:e59c8e839560	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	163:e59c8e839560	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	163:e59c8e839560	712	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	713	* @retval None
AnnaBridge	163:e59c8e839560	714	*/
AnnaBridge	163:e59c8e839560	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	716	{
AnnaBridge	163:e59c8e839560	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	163:e59c8e839560	718	}
AnnaBridge	163:e59c8e839560	719
AnnaBridge	163:e59c8e839560	720	/**
AnnaBridge	163:e59c8e839560	721	* @brief Disable CRC
AnnaBridge	163:e59c8e839560	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	163:e59c8e839560	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	163:e59c8e839560	724	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	725	* @retval None
AnnaBridge	163:e59c8e839560	726	*/
AnnaBridge	163:e59c8e839560	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	728	{
AnnaBridge	163:e59c8e839560	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	163:e59c8e839560	730	}
AnnaBridge	163:e59c8e839560	731
AnnaBridge	163:e59c8e839560	732	/**
AnnaBridge	163:e59c8e839560	733	* @brief Check if CRC is enabled
AnnaBridge	163:e59c8e839560	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	163:e59c8e839560	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	163:e59c8e839560	736	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	737	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	738	*/
AnnaBridge	163:e59c8e839560	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	740	{
AnnaBridge	163:e59c8e839560	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	163:e59c8e839560	742	}
AnnaBridge	163:e59c8e839560	743
AnnaBridge	163:e59c8e839560	744	/**
AnnaBridge	163:e59c8e839560	745	* @brief Set CRC Length
AnnaBridge	163:e59c8e839560	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	163:e59c8e839560	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
AnnaBridge	163:e59c8e839560	748	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	749	* @param CRCLength This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	750	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	163:e59c8e839560	751	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	163:e59c8e839560	752	* @retval None
AnnaBridge	163:e59c8e839560	753	*/
AnnaBridge	163:e59c8e839560	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge	163:e59c8e839560	755	{
AnnaBridge	163:e59c8e839560	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
AnnaBridge	163:e59c8e839560	757	}
AnnaBridge	163:e59c8e839560	758
AnnaBridge	163:e59c8e839560	759	/**
AnnaBridge	163:e59c8e839560	760	* @brief Get CRC Length
AnnaBridge	163:e59c8e839560	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
AnnaBridge	163:e59c8e839560	762	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	763	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	764	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	163:e59c8e839560	765	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	163:e59c8e839560	766	*/
AnnaBridge	163:e59c8e839560	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	768	{
AnnaBridge	163:e59c8e839560	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
AnnaBridge	163:e59c8e839560	770	}
AnnaBridge	163:e59c8e839560	771
AnnaBridge	163:e59c8e839560	772	/**
AnnaBridge	163:e59c8e839560	773	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	163:e59c8e839560	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	163:e59c8e839560	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	163:e59c8e839560	776	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	777	* @retval None
AnnaBridge	163:e59c8e839560	778	*/
AnnaBridge	163:e59c8e839560	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	780	{
AnnaBridge	163:e59c8e839560	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	163:e59c8e839560	782	}
AnnaBridge	163:e59c8e839560	783
AnnaBridge	163:e59c8e839560	784	/**
AnnaBridge	163:e59c8e839560	785	* @brief Set polynomial for CRC calculation
AnnaBridge	163:e59c8e839560	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	163:e59c8e839560	787	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	163:e59c8e839560	789	* @retval None
AnnaBridge	163:e59c8e839560	790	*/
AnnaBridge	163:e59c8e839560	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	163:e59c8e839560	792	{
AnnaBridge	163:e59c8e839560	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	163:e59c8e839560	794	}
AnnaBridge	163:e59c8e839560	795
AnnaBridge	163:e59c8e839560	796	/**
AnnaBridge	163:e59c8e839560	797	* @brief Get polynomial for CRC calculation
AnnaBridge	163:e59c8e839560	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	163:e59c8e839560	799	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	163:e59c8e839560	801	*/
AnnaBridge	163:e59c8e839560	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	803	{
AnnaBridge	163:e59c8e839560	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	163:e59c8e839560	805	}
AnnaBridge	163:e59c8e839560	806
AnnaBridge	163:e59c8e839560	807	/**
AnnaBridge	163:e59c8e839560	808	* @brief Get Rx CRC
AnnaBridge	163:e59c8e839560	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	163:e59c8e839560	810	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	163:e59c8e839560	812	*/
AnnaBridge	163:e59c8e839560	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	814	{
AnnaBridge	163:e59c8e839560	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	163:e59c8e839560	816	}
AnnaBridge	163:e59c8e839560	817
AnnaBridge	163:e59c8e839560	818	/**
AnnaBridge	163:e59c8e839560	819	* @brief Get Tx CRC
AnnaBridge	163:e59c8e839560	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	163:e59c8e839560	821	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	163:e59c8e839560	823	*/
AnnaBridge	163:e59c8e839560	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	825	{
AnnaBridge	163:e59c8e839560	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	163:e59c8e839560	827	}
AnnaBridge	163:e59c8e839560	828
AnnaBridge	163:e59c8e839560	829	/**
AnnaBridge	163:e59c8e839560	830	* @}
AnnaBridge	163:e59c8e839560	831	*/
AnnaBridge	163:e59c8e839560	832
AnnaBridge	163:e59c8e839560	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	163:e59c8e839560	834	* @{
AnnaBridge	163:e59c8e839560	835	*/
AnnaBridge	163:e59c8e839560	836
AnnaBridge	163:e59c8e839560	837	/**
AnnaBridge	163:e59c8e839560	838	* @brief Set NSS mode
AnnaBridge	163:e59c8e839560	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	163:e59c8e839560	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	163:e59c8e839560	842	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	843	* @param NSS This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	844	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	163:e59c8e839560	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	163:e59c8e839560	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	163:e59c8e839560	847	* @retval None
AnnaBridge	163:e59c8e839560	848	*/
AnnaBridge	163:e59c8e839560	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	163:e59c8e839560	850	{
AnnaBridge	163:e59c8e839560	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	163:e59c8e839560	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	163:e59c8e839560	853	}
AnnaBridge	163:e59c8e839560	854
AnnaBridge	163:e59c8e839560	855	/**
AnnaBridge	163:e59c8e839560	856	* @brief Get NSS mode
AnnaBridge	163:e59c8e839560	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	163:e59c8e839560	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	163:e59c8e839560	859	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	860	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	861	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	163:e59c8e839560	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	163:e59c8e839560	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	163:e59c8e839560	864	*/
AnnaBridge	163:e59c8e839560	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	866	{
AnnaBridge	163:e59c8e839560	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	163:e59c8e839560	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	163:e59c8e839560	869	return (Ssm \| Ssoe);
AnnaBridge	163:e59c8e839560	870	}
AnnaBridge	163:e59c8e839560	871
AnnaBridge	163:e59c8e839560	872	/**
AnnaBridge	163:e59c8e839560	873	* @brief Enable NSS pulse management
AnnaBridge	163:e59c8e839560	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
AnnaBridge	163:e59c8e839560	876	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	877	* @retval None
AnnaBridge	163:e59c8e839560	878	*/
AnnaBridge	163:e59c8e839560	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	880	{
AnnaBridge	163:e59c8e839560	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	163:e59c8e839560	882	}
AnnaBridge	163:e59c8e839560	883
AnnaBridge	163:e59c8e839560	884	/**
AnnaBridge	163:e59c8e839560	885	* @brief Disable NSS pulse management
AnnaBridge	163:e59c8e839560	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
AnnaBridge	163:e59c8e839560	888	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	889	* @retval None
AnnaBridge	163:e59c8e839560	890	*/
AnnaBridge	163:e59c8e839560	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	892	{
AnnaBridge	163:e59c8e839560	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	163:e59c8e839560	894	}
AnnaBridge	163:e59c8e839560	895
AnnaBridge	163:e59c8e839560	896	/**
AnnaBridge	163:e59c8e839560	897	* @brief Check if NSS pulse is enabled
AnnaBridge	163:e59c8e839560	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	163:e59c8e839560	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
AnnaBridge	163:e59c8e839560	900	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	901	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	902	*/
AnnaBridge	163:e59c8e839560	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	904	{
AnnaBridge	163:e59c8e839560	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
AnnaBridge	163:e59c8e839560	906	}
AnnaBridge	163:e59c8e839560	907
AnnaBridge	163:e59c8e839560	908	/**
AnnaBridge	163:e59c8e839560	909	* @}
AnnaBridge	163:e59c8e839560	910	*/
AnnaBridge	163:e59c8e839560	911
AnnaBridge	163:e59c8e839560	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	163:e59c8e839560	913	* @{
AnnaBridge	163:e59c8e839560	914	*/
AnnaBridge	163:e59c8e839560	915
AnnaBridge	163:e59c8e839560	916	/**
AnnaBridge	163:e59c8e839560	917	* @brief Check if Rx buffer is not empty
AnnaBridge	163:e59c8e839560	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	163:e59c8e839560	919	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	920	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	921	*/
AnnaBridge	163:e59c8e839560	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	923	{
AnnaBridge	163:e59c8e839560	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	163:e59c8e839560	925	}
AnnaBridge	163:e59c8e839560	926
AnnaBridge	163:e59c8e839560	927	/**
AnnaBridge	163:e59c8e839560	928	* @brief Check if Tx buffer is empty
AnnaBridge	163:e59c8e839560	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	163:e59c8e839560	930	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	931	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	932	*/
AnnaBridge	163:e59c8e839560	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	934	{
AnnaBridge	163:e59c8e839560	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	163:e59c8e839560	936	}
AnnaBridge	163:e59c8e839560	937
AnnaBridge	163:e59c8e839560	938	/**
AnnaBridge	163:e59c8e839560	939	* @brief Get CRC error flag
AnnaBridge	163:e59c8e839560	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	163:e59c8e839560	941	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	942	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	943	*/
AnnaBridge	163:e59c8e839560	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	945	{
AnnaBridge	163:e59c8e839560	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	163:e59c8e839560	947	}
AnnaBridge	163:e59c8e839560	948
AnnaBridge	163:e59c8e839560	949	/**
AnnaBridge	163:e59c8e839560	950	* @brief Get mode fault error flag
AnnaBridge	163:e59c8e839560	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	163:e59c8e839560	952	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	953	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	954	*/
AnnaBridge	163:e59c8e839560	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	956	{
AnnaBridge	163:e59c8e839560	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	163:e59c8e839560	958	}
AnnaBridge	163:e59c8e839560	959
AnnaBridge	163:e59c8e839560	960	/**
AnnaBridge	163:e59c8e839560	961	* @brief Get overrun error flag
AnnaBridge	163:e59c8e839560	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	163:e59c8e839560	963	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	964	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	965	*/
AnnaBridge	163:e59c8e839560	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	967	{
AnnaBridge	163:e59c8e839560	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	163:e59c8e839560	969	}
AnnaBridge	163:e59c8e839560	970
AnnaBridge	163:e59c8e839560	971	/**
AnnaBridge	163:e59c8e839560	972	* @brief Get busy flag
AnnaBridge	163:e59c8e839560	973	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	163:e59c8e839560	974	* -When the SPI is correctly disabled
AnnaBridge	163:e59c8e839560	975	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	163:e59c8e839560	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	163:e59c8e839560	977	* sent
AnnaBridge	163:e59c8e839560	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	163:e59c8e839560	979	* each data transfer.
AnnaBridge	163:e59c8e839560	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	163:e59c8e839560	981	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	982	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	983	*/
AnnaBridge	163:e59c8e839560	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	985	{
AnnaBridge	163:e59c8e839560	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	163:e59c8e839560	987	}
AnnaBridge	163:e59c8e839560	988
AnnaBridge	163:e59c8e839560	989	/**
AnnaBridge	163:e59c8e839560	990	* @brief Get frame format error flag
AnnaBridge	163:e59c8e839560	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	163:e59c8e839560	992	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	993	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	994	*/
AnnaBridge	163:e59c8e839560	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	996	{
AnnaBridge	163:e59c8e839560	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	163:e59c8e839560	998	}
AnnaBridge	163:e59c8e839560	999
AnnaBridge	163:e59c8e839560	1000	/**
AnnaBridge	163:e59c8e839560	1001	* @brief Get FIFO reception Level
AnnaBridge	163:e59c8e839560	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
AnnaBridge	163:e59c8e839560	1003	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1004	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
AnnaBridge	163:e59c8e839560	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
AnnaBridge	163:e59c8e839560	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
AnnaBridge	163:e59c8e839560	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
AnnaBridge	163:e59c8e839560	1009	*/
AnnaBridge	163:e59c8e839560	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1011	{
AnnaBridge	163:e59c8e839560	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
AnnaBridge	163:e59c8e839560	1013	}
AnnaBridge	163:e59c8e839560	1014
AnnaBridge	163:e59c8e839560	1015	/**
AnnaBridge	163:e59c8e839560	1016	* @brief Get FIFO Transmission Level
AnnaBridge	163:e59c8e839560	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
AnnaBridge	163:e59c8e839560	1018	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1019	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
AnnaBridge	163:e59c8e839560	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
AnnaBridge	163:e59c8e839560	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
AnnaBridge	163:e59c8e839560	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
AnnaBridge	163:e59c8e839560	1024	*/
AnnaBridge	163:e59c8e839560	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1026	{
AnnaBridge	163:e59c8e839560	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
AnnaBridge	163:e59c8e839560	1028	}
AnnaBridge	163:e59c8e839560	1029
AnnaBridge	163:e59c8e839560	1030	/**
AnnaBridge	163:e59c8e839560	1031	* @brief Clear CRC error flag
AnnaBridge	163:e59c8e839560	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	163:e59c8e839560	1033	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1034	* @retval None
AnnaBridge	163:e59c8e839560	1035	*/
AnnaBridge	163:e59c8e839560	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1037	{
AnnaBridge	163:e59c8e839560	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	163:e59c8e839560	1039	}
AnnaBridge	163:e59c8e839560	1040
AnnaBridge	163:e59c8e839560	1041	/**
AnnaBridge	163:e59c8e839560	1042	* @brief Clear mode fault error flag
AnnaBridge	163:e59c8e839560	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	163:e59c8e839560	1044	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	163:e59c8e839560	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	163:e59c8e839560	1046	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1047	* @retval None
AnnaBridge	163:e59c8e839560	1048	*/
AnnaBridge	163:e59c8e839560	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1050	{
AnnaBridge	163:e59c8e839560	1051	__IO uint32_t tmpreg;
AnnaBridge	163:e59c8e839560	1052	tmpreg = SPIx->SR;
AnnaBridge	163:e59c8e839560	1053	(void) tmpreg;
AnnaBridge	163:e59c8e839560	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	163:e59c8e839560	1055	(void) tmpreg;
AnnaBridge	163:e59c8e839560	1056	}
AnnaBridge	163:e59c8e839560	1057
AnnaBridge	163:e59c8e839560	1058	/**
AnnaBridge	163:e59c8e839560	1059	* @brief Clear overrun error flag
AnnaBridge	163:e59c8e839560	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	163:e59c8e839560	1061	* register followed by a read access to the SPIx_SR register
AnnaBridge	163:e59c8e839560	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	163:e59c8e839560	1063	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1064	* @retval None
AnnaBridge	163:e59c8e839560	1065	*/
AnnaBridge	163:e59c8e839560	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1067	{
AnnaBridge	163:e59c8e839560	1068	__IO uint32_t tmpreg;
AnnaBridge	163:e59c8e839560	1069	tmpreg = SPIx->DR;
AnnaBridge	163:e59c8e839560	1070	(void) tmpreg;
AnnaBridge	163:e59c8e839560	1071	tmpreg = SPIx->SR;
AnnaBridge	163:e59c8e839560	1072	(void) tmpreg;
AnnaBridge	163:e59c8e839560	1073	}
AnnaBridge	163:e59c8e839560	1074
AnnaBridge	163:e59c8e839560	1075	/**
AnnaBridge	163:e59c8e839560	1076	* @brief Clear frame format error flag
AnnaBridge	163:e59c8e839560	1077	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	163:e59c8e839560	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	163:e59c8e839560	1079	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1080	* @retval None
AnnaBridge	163:e59c8e839560	1081	*/
AnnaBridge	163:e59c8e839560	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1083	{
AnnaBridge	163:e59c8e839560	1084	__IO uint32_t tmpreg;
AnnaBridge	163:e59c8e839560	1085	tmpreg = SPIx->SR;
AnnaBridge	163:e59c8e839560	1086	(void) tmpreg;
AnnaBridge	163:e59c8e839560	1087	}
AnnaBridge	163:e59c8e839560	1088
AnnaBridge	163:e59c8e839560	1089	/**
AnnaBridge	163:e59c8e839560	1090	* @}
AnnaBridge	163:e59c8e839560	1091	*/
AnnaBridge	163:e59c8e839560	1092
AnnaBridge	163:e59c8e839560	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	163:e59c8e839560	1094	* @{
AnnaBridge	163:e59c8e839560	1095	*/
AnnaBridge	163:e59c8e839560	1096
AnnaBridge	163:e59c8e839560	1097	/**
AnnaBridge	163:e59c8e839560	1098	* @brief Enable error interrupt
AnnaBridge	163:e59c8e839560	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	163:e59c8e839560	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	163:e59c8e839560	1101	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1102	* @retval None
AnnaBridge	163:e59c8e839560	1103	*/
AnnaBridge	163:e59c8e839560	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1105	{
AnnaBridge	163:e59c8e839560	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	163:e59c8e839560	1107	}
AnnaBridge	163:e59c8e839560	1108
AnnaBridge	163:e59c8e839560	1109	/**
AnnaBridge	163:e59c8e839560	1110	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	163:e59c8e839560	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	163:e59c8e839560	1112	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1113	* @retval None
AnnaBridge	163:e59c8e839560	1114	*/
AnnaBridge	163:e59c8e839560	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1116	{
AnnaBridge	163:e59c8e839560	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	163:e59c8e839560	1118	}
AnnaBridge	163:e59c8e839560	1119
AnnaBridge	163:e59c8e839560	1120	/**
AnnaBridge	163:e59c8e839560	1121	* @brief Enable Tx buffer empty interrupt
AnnaBridge	163:e59c8e839560	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	163:e59c8e839560	1123	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1124	* @retval None
AnnaBridge	163:e59c8e839560	1125	*/
AnnaBridge	163:e59c8e839560	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1127	{
AnnaBridge	163:e59c8e839560	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	163:e59c8e839560	1129	}
AnnaBridge	163:e59c8e839560	1130
AnnaBridge	163:e59c8e839560	1131	/**
AnnaBridge	163:e59c8e839560	1132	* @brief Disable error interrupt
AnnaBridge	163:e59c8e839560	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	163:e59c8e839560	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	163:e59c8e839560	1135	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1136	* @retval None
AnnaBridge	163:e59c8e839560	1137	*/
AnnaBridge	163:e59c8e839560	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1139	{
AnnaBridge	163:e59c8e839560	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	163:e59c8e839560	1141	}
AnnaBridge	163:e59c8e839560	1142
AnnaBridge	163:e59c8e839560	1143	/**
AnnaBridge	163:e59c8e839560	1144	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	163:e59c8e839560	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	163:e59c8e839560	1146	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1147	* @retval None
AnnaBridge	163:e59c8e839560	1148	*/
AnnaBridge	163:e59c8e839560	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1150	{
AnnaBridge	163:e59c8e839560	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	163:e59c8e839560	1152	}
AnnaBridge	163:e59c8e839560	1153
AnnaBridge	163:e59c8e839560	1154	/**
AnnaBridge	163:e59c8e839560	1155	* @brief Disable Tx buffer empty interrupt
AnnaBridge	163:e59c8e839560	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	163:e59c8e839560	1157	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1158	* @retval None
AnnaBridge	163:e59c8e839560	1159	*/
AnnaBridge	163:e59c8e839560	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1161	{
AnnaBridge	163:e59c8e839560	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	163:e59c8e839560	1163	}
AnnaBridge	163:e59c8e839560	1164
AnnaBridge	163:e59c8e839560	1165	/**
AnnaBridge	163:e59c8e839560	1166	* @brief Check if error interrupt is enabled
AnnaBridge	163:e59c8e839560	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	163:e59c8e839560	1168	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1169	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1170	*/
AnnaBridge	163:e59c8e839560	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1172	{
AnnaBridge	163:e59c8e839560	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	163:e59c8e839560	1174	}
AnnaBridge	163:e59c8e839560	1175
AnnaBridge	163:e59c8e839560	1176	/**
AnnaBridge	163:e59c8e839560	1177	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	163:e59c8e839560	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	163:e59c8e839560	1179	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1180	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1181	*/
AnnaBridge	163:e59c8e839560	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1183	{
AnnaBridge	163:e59c8e839560	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	163:e59c8e839560	1185	}
AnnaBridge	163:e59c8e839560	1186
AnnaBridge	163:e59c8e839560	1187	/**
AnnaBridge	163:e59c8e839560	1188	* @brief Check if Tx buffer empty interrupt
AnnaBridge	163:e59c8e839560	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	163:e59c8e839560	1190	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1191	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1192	*/
AnnaBridge	163:e59c8e839560	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1194	{
AnnaBridge	163:e59c8e839560	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	163:e59c8e839560	1196	}
AnnaBridge	163:e59c8e839560	1197
AnnaBridge	163:e59c8e839560	1198	/**
AnnaBridge	163:e59c8e839560	1199	* @}
AnnaBridge	163:e59c8e839560	1200	*/
AnnaBridge	163:e59c8e839560	1201
AnnaBridge	163:e59c8e839560	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	163:e59c8e839560	1203	* @{
AnnaBridge	163:e59c8e839560	1204	*/
AnnaBridge	163:e59c8e839560	1205
AnnaBridge	163:e59c8e839560	1206	/**
AnnaBridge	163:e59c8e839560	1207	* @brief Enable DMA Rx
AnnaBridge	163:e59c8e839560	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	163:e59c8e839560	1209	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1210	* @retval None
AnnaBridge	163:e59c8e839560	1211	*/
AnnaBridge	163:e59c8e839560	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1213	{
AnnaBridge	163:e59c8e839560	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	163:e59c8e839560	1215	}
AnnaBridge	163:e59c8e839560	1216
AnnaBridge	163:e59c8e839560	1217	/**
AnnaBridge	163:e59c8e839560	1218	* @brief Disable DMA Rx
AnnaBridge	163:e59c8e839560	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	163:e59c8e839560	1220	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1221	* @retval None
AnnaBridge	163:e59c8e839560	1222	*/
AnnaBridge	163:e59c8e839560	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1224	{
AnnaBridge	163:e59c8e839560	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	163:e59c8e839560	1226	}
AnnaBridge	163:e59c8e839560	1227
AnnaBridge	163:e59c8e839560	1228	/**
AnnaBridge	163:e59c8e839560	1229	* @brief Check if DMA Rx is enabled
AnnaBridge	163:e59c8e839560	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	163:e59c8e839560	1231	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1232	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1233	*/
AnnaBridge	163:e59c8e839560	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1235	{
AnnaBridge	163:e59c8e839560	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	163:e59c8e839560	1237	}
AnnaBridge	163:e59c8e839560	1238
AnnaBridge	163:e59c8e839560	1239	/**
AnnaBridge	163:e59c8e839560	1240	* @brief Enable DMA Tx
AnnaBridge	163:e59c8e839560	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	163:e59c8e839560	1242	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1243	* @retval None
AnnaBridge	163:e59c8e839560	1244	*/
AnnaBridge	163:e59c8e839560	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1246	{
AnnaBridge	163:e59c8e839560	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	163:e59c8e839560	1248	}
AnnaBridge	163:e59c8e839560	1249
AnnaBridge	163:e59c8e839560	1250	/**
AnnaBridge	163:e59c8e839560	1251	* @brief Disable DMA Tx
AnnaBridge	163:e59c8e839560	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	163:e59c8e839560	1253	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1254	* @retval None
AnnaBridge	163:e59c8e839560	1255	*/
AnnaBridge	163:e59c8e839560	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1257	{
AnnaBridge	163:e59c8e839560	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	163:e59c8e839560	1259	}
AnnaBridge	163:e59c8e839560	1260
AnnaBridge	163:e59c8e839560	1261	/**
AnnaBridge	163:e59c8e839560	1262	* @brief Check if DMA Tx is enabled
AnnaBridge	163:e59c8e839560	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	163:e59c8e839560	1264	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1265	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1266	*/
AnnaBridge	163:e59c8e839560	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1268	{
AnnaBridge	163:e59c8e839560	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	163:e59c8e839560	1270	}
AnnaBridge	163:e59c8e839560	1271
AnnaBridge	163:e59c8e839560	1272	/**
AnnaBridge	163:e59c8e839560	1273	* @brief Set parity of Last DMA reception
AnnaBridge	163:e59c8e839560	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
AnnaBridge	163:e59c8e839560	1275	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1276	* @param Parity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	163:e59c8e839560	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1279	* @retval None
AnnaBridge	163:e59c8e839560	1280	*/
AnnaBridge	163:e59c8e839560	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	163:e59c8e839560	1282	{
AnnaBridge	168:b9e159c1930a	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
AnnaBridge	163:e59c8e839560	1284	}
AnnaBridge	163:e59c8e839560	1285
AnnaBridge	163:e59c8e839560	1286	/**
AnnaBridge	163:e59c8e839560	1287	* @brief Get parity configuration for Last DMA reception
AnnaBridge	163:e59c8e839560	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
AnnaBridge	163:e59c8e839560	1289	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1290	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	163:e59c8e839560	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1293	*/
AnnaBridge	163:e59c8e839560	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1295	{
AnnaBridge	168:b9e159c1930a	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
AnnaBridge	163:e59c8e839560	1297	}
AnnaBridge	163:e59c8e839560	1298
AnnaBridge	163:e59c8e839560	1299	/**
AnnaBridge	163:e59c8e839560	1300	* @brief Set parity of Last DMA transmission
AnnaBridge	163:e59c8e839560	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
AnnaBridge	163:e59c8e839560	1302	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1303	* @param Parity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	163:e59c8e839560	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1306	* @retval None
AnnaBridge	163:e59c8e839560	1307	*/
AnnaBridge	163:e59c8e839560	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	163:e59c8e839560	1309	{
AnnaBridge	168:b9e159c1930a	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
AnnaBridge	163:e59c8e839560	1311	}
AnnaBridge	163:e59c8e839560	1312
AnnaBridge	163:e59c8e839560	1313	/**
AnnaBridge	163:e59c8e839560	1314	* @brief Get parity configuration for Last DMA transmission
AnnaBridge	163:e59c8e839560	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
AnnaBridge	163:e59c8e839560	1316	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1317	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	163:e59c8e839560	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1320	*/
AnnaBridge	163:e59c8e839560	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1322	{
AnnaBridge	168:b9e159c1930a	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
AnnaBridge	163:e59c8e839560	1324	}
AnnaBridge	163:e59c8e839560	1325
AnnaBridge	163:e59c8e839560	1326	/**
AnnaBridge	163:e59c8e839560	1327	* @brief Get the data register address used for DMA transfer
AnnaBridge	163:e59c8e839560	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	163:e59c8e839560	1329	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1330	* @retval Address of data register
AnnaBridge	163:e59c8e839560	1331	*/
AnnaBridge	163:e59c8e839560	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1333	{
AnnaBridge	163:e59c8e839560	1334	return (uint32_t) & (SPIx->DR);
AnnaBridge	163:e59c8e839560	1335	}
AnnaBridge	163:e59c8e839560	1336
AnnaBridge	163:e59c8e839560	1337	/**
AnnaBridge	163:e59c8e839560	1338	* @}
AnnaBridge	163:e59c8e839560	1339	*/
AnnaBridge	163:e59c8e839560	1340
AnnaBridge	163:e59c8e839560	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	163:e59c8e839560	1342	* @{
AnnaBridge	163:e59c8e839560	1343	*/
AnnaBridge	163:e59c8e839560	1344
AnnaBridge	163:e59c8e839560	1345	/**
AnnaBridge	163:e59c8e839560	1346	* @brief Read 8-Bits in the data register
AnnaBridge	163:e59c8e839560	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	163:e59c8e839560	1348	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	163:e59c8e839560	1350	*/
AnnaBridge	163:e59c8e839560	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1352	{
AnnaBridge	163:e59c8e839560	1353	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	163:e59c8e839560	1354	}
AnnaBridge	163:e59c8e839560	1355
AnnaBridge	163:e59c8e839560	1356	/**
AnnaBridge	163:e59c8e839560	1357	* @brief Read 16-Bits in the data register
AnnaBridge	163:e59c8e839560	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	163:e59c8e839560	1359	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	163:e59c8e839560	1361	*/
AnnaBridge	163:e59c8e839560	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1363	{
AnnaBridge	163:e59c8e839560	1364	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	163:e59c8e839560	1365	}
AnnaBridge	163:e59c8e839560	1366
AnnaBridge	163:e59c8e839560	1367	/**
AnnaBridge	163:e59c8e839560	1368	* @brief Write 8-Bits in the data register
AnnaBridge	163:e59c8e839560	1369	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	163:e59c8e839560	1370	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	163:e59c8e839560	1372	* @retval None
AnnaBridge	163:e59c8e839560	1373	*/
AnnaBridge	163:e59c8e839560	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	163:e59c8e839560	1375	{
AnnaBridge	163:e59c8e839560	1376	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	163:e59c8e839560	1377	}
AnnaBridge	163:e59c8e839560	1378
AnnaBridge	168:b9e159c1930a	1379	// MBED patch
AnnaBridge	167:84c0a372a020	1380	#if __GNUC__
AnnaBridge	167:84c0a372a020	1381	# define MAY_ALIAS __attribute__ ((__may_alias__))
AnnaBridge	167:84c0a372a020	1382	#else
AnnaBridge	167:84c0a372a020	1383	# define MAY_ALIAS
AnnaBridge	167:84c0a372a020	1384	#endif
AnnaBridge	167:84c0a372a020	1385
AnnaBridge	167:84c0a372a020	1386	typedef __IO uint16_t MAY_ALIAS uint16_io_t;
AnnaBridge	168:b9e159c1930a	1387	// MBED patch
AnnaBridge	167:84c0a372a020	1388
AnnaBridge	163:e59c8e839560	1389	/**
AnnaBridge	163:e59c8e839560	1390	* @brief Write 16-Bits in the data register
AnnaBridge	163:e59c8e839560	1391	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	163:e59c8e839560	1392	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1393	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	163:e59c8e839560	1394	* @retval None
AnnaBridge	163:e59c8e839560	1395	*/
AnnaBridge	163:e59c8e839560	1396	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	163:e59c8e839560	1397	{
AnnaBridge	168:b9e159c1930a	1398	((uint16_io_t)&SPIx->DR) = TxData; // MBED patch
AnnaBridge	163:e59c8e839560	1399	}
AnnaBridge	163:e59c8e839560	1400
AnnaBridge	163:e59c8e839560	1401	/**
AnnaBridge	163:e59c8e839560	1402	* @}
AnnaBridge	163:e59c8e839560	1403	*/
AnnaBridge	163:e59c8e839560	1404	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	1405	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	163:e59c8e839560	1406	* @{
AnnaBridge	163:e59c8e839560	1407	*/
AnnaBridge	163:e59c8e839560	1408
AnnaBridge	163:e59c8e839560	1409	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	163:e59c8e839560	1410	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	163:e59c8e839560	1411	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	163:e59c8e839560	1412
AnnaBridge	163:e59c8e839560	1413	/**
AnnaBridge	163:e59c8e839560	1414	* @}
AnnaBridge	163:e59c8e839560	1415	*/
AnnaBridge	163:e59c8e839560	1416	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	1417	/**
AnnaBridge	163:e59c8e839560	1418	* @}
AnnaBridge	163:e59c8e839560	1419	*/
AnnaBridge	163:e59c8e839560	1420
AnnaBridge	163:e59c8e839560	1421	/**
AnnaBridge	163:e59c8e839560	1422	* @}
AnnaBridge	163:e59c8e839560	1423	*/
AnnaBridge	163:e59c8e839560	1424
AnnaBridge	163:e59c8e839560	1425	#if defined(SPI_I2S_SUPPORT)
AnnaBridge	163:e59c8e839560	1426	/** @defgroup I2S_LL I2S
AnnaBridge	163:e59c8e839560	1427	* @{
AnnaBridge	163:e59c8e839560	1428	*/
AnnaBridge	163:e59c8e839560	1429
AnnaBridge	163:e59c8e839560	1430	/* Private variables ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1431	/* Private constants ---------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1432	/* Private macros ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1433
AnnaBridge	163:e59c8e839560	1434	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1435	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	1436	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	163:e59c8e839560	1437	* @{
AnnaBridge	163:e59c8e839560	1438	*/
AnnaBridge	163:e59c8e839560	1439
AnnaBridge	163:e59c8e839560	1440	/**
AnnaBridge	163:e59c8e839560	1441	* @brief I2S Init structure definition
AnnaBridge	163:e59c8e839560	1442	*/
AnnaBridge	163:e59c8e839560	1443
AnnaBridge	163:e59c8e839560	1444	typedef struct
AnnaBridge	163:e59c8e839560	1445	{
AnnaBridge	163:e59c8e839560	1446	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	163:e59c8e839560	1447	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	163:e59c8e839560	1448
AnnaBridge	163:e59c8e839560	1449	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	163:e59c8e839560	1450
AnnaBridge	163:e59c8e839560	1451	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	163:e59c8e839560	1452	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	163:e59c8e839560	1453
AnnaBridge	163:e59c8e839560	1454	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	163:e59c8e839560	1455
AnnaBridge	163:e59c8e839560	1456
AnnaBridge	163:e59c8e839560	1457	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	163:e59c8e839560	1458	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	163:e59c8e839560	1459
AnnaBridge	163:e59c8e839560	1460	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	163:e59c8e839560	1461
AnnaBridge	163:e59c8e839560	1462
AnnaBridge	163:e59c8e839560	1463	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	163:e59c8e839560	1464	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	163:e59c8e839560	1465
AnnaBridge	163:e59c8e839560	1466	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	163:e59c8e839560	1467
AnnaBridge	163:e59c8e839560	1468
AnnaBridge	163:e59c8e839560	1469	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	163:e59c8e839560	1470	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	163:e59c8e839560	1471
AnnaBridge	163:e59c8e839560	1472	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	163:e59c8e839560	1473	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	163:e59c8e839560	1474
AnnaBridge	163:e59c8e839560	1475
AnnaBridge	163:e59c8e839560	1476	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	163:e59c8e839560	1477	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	163:e59c8e839560	1478
AnnaBridge	163:e59c8e839560	1479	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	163:e59c8e839560	1480
AnnaBridge	163:e59c8e839560	1481	} LL_I2S_InitTypeDef;
AnnaBridge	163:e59c8e839560	1482
AnnaBridge	163:e59c8e839560	1483	/**
AnnaBridge	163:e59c8e839560	1484	* @}
AnnaBridge	163:e59c8e839560	1485	*/
AnnaBridge	163:e59c8e839560	1486	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	163:e59c8e839560	1487
AnnaBridge	163:e59c8e839560	1488	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1489	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	163:e59c8e839560	1490	* @{
AnnaBridge	163:e59c8e839560	1491	*/
AnnaBridge	163:e59c8e839560	1492
AnnaBridge	163:e59c8e839560	1493	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	163:e59c8e839560	1494	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	163:e59c8e839560	1495	* @{
AnnaBridge	163:e59c8e839560	1496	*/
AnnaBridge	163:e59c8e839560	1497	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	163:e59c8e839560	1498	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	163:e59c8e839560	1499	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	168:b9e159c1930a	1500	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	163:e59c8e839560	1501	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	163:e59c8e839560	1502	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	163:e59c8e839560	1503	/**
AnnaBridge	163:e59c8e839560	1504	* @}
AnnaBridge	163:e59c8e839560	1505	*/
AnnaBridge	163:e59c8e839560	1506
AnnaBridge	163:e59c8e839560	1507	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	163:e59c8e839560	1508	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	163:e59c8e839560	1509	* @{
AnnaBridge	163:e59c8e839560	1510	*/
AnnaBridge	163:e59c8e839560	1511	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	163:e59c8e839560	1512	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	163:e59c8e839560	1513	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	163:e59c8e839560	1514	/**
AnnaBridge	163:e59c8e839560	1515	* @}
AnnaBridge	163:e59c8e839560	1516	*/
AnnaBridge	163:e59c8e839560	1517
AnnaBridge	163:e59c8e839560	1518	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	163:e59c8e839560	1519	* @{
AnnaBridge	163:e59c8e839560	1520	*/
AnnaBridge	163:e59c8e839560	1521	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	163:e59c8e839560	1522	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	163:e59c8e839560	1523	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	163:e59c8e839560	1524	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	163:e59c8e839560	1525	/**
AnnaBridge	163:e59c8e839560	1526	* @}
AnnaBridge	163:e59c8e839560	1527	*/
AnnaBridge	163:e59c8e839560	1528
AnnaBridge	163:e59c8e839560	1529	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	163:e59c8e839560	1530	* @{
AnnaBridge	163:e59c8e839560	1531	*/
AnnaBridge	163:e59c8e839560	1532	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
AnnaBridge	163:e59c8e839560	1533	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	163:e59c8e839560	1534	/**
AnnaBridge	163:e59c8e839560	1535	* @}
AnnaBridge	163:e59c8e839560	1536	*/
AnnaBridge	163:e59c8e839560	1537
AnnaBridge	163:e59c8e839560	1538	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	163:e59c8e839560	1539	* @{
AnnaBridge	163:e59c8e839560	1540	*/
AnnaBridge	163:e59c8e839560	1541	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
AnnaBridge	163:e59c8e839560	1542	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	163:e59c8e839560	1543	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	163:e59c8e839560	1544	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	163:e59c8e839560	1545	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	163:e59c8e839560	1546	/**
AnnaBridge	163:e59c8e839560	1547	* @}
AnnaBridge	163:e59c8e839560	1548	*/
AnnaBridge	163:e59c8e839560	1549
AnnaBridge	163:e59c8e839560	1550	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	163:e59c8e839560	1551	* @{
AnnaBridge	163:e59c8e839560	1552	*/
AnnaBridge	163:e59c8e839560	1553	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
AnnaBridge	163:e59c8e839560	1554	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	163:e59c8e839560	1555	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	163:e59c8e839560	1556	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	163:e59c8e839560	1557	/**
AnnaBridge	163:e59c8e839560	1558	* @}
AnnaBridge	163:e59c8e839560	1559	*/
AnnaBridge	163:e59c8e839560	1560
AnnaBridge	163:e59c8e839560	1561	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	163:e59c8e839560	1562	* @{
AnnaBridge	163:e59c8e839560	1563	*/
AnnaBridge	163:e59c8e839560	1564	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	163:e59c8e839560	1565	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	163:e59c8e839560	1566	/**
AnnaBridge	163:e59c8e839560	1567	* @}
AnnaBridge	163:e59c8e839560	1568	*/
AnnaBridge	163:e59c8e839560	1569
AnnaBridge	163:e59c8e839560	1570	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	1571
AnnaBridge	163:e59c8e839560	1572	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	163:e59c8e839560	1573	* @{
AnnaBridge	163:e59c8e839560	1574	*/
AnnaBridge	163:e59c8e839560	1575	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
AnnaBridge	163:e59c8e839560	1576	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	163:e59c8e839560	1577	/**
AnnaBridge	163:e59c8e839560	1578	* @}
AnnaBridge	163:e59c8e839560	1579	*/
AnnaBridge	163:e59c8e839560	1580
AnnaBridge	163:e59c8e839560	1581	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	163:e59c8e839560	1582	* @{
AnnaBridge	163:e59c8e839560	1583	*/
AnnaBridge	163:e59c8e839560	1584
AnnaBridge	163:e59c8e839560	1585	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	163:e59c8e839560	1586	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	163:e59c8e839560	1587	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	163:e59c8e839560	1588	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	163:e59c8e839560	1589	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	163:e59c8e839560	1590	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	163:e59c8e839560	1591	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	163:e59c8e839560	1592	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	163:e59c8e839560	1593	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	163:e59c8e839560	1594	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	163:e59c8e839560	1595	/**
AnnaBridge	163:e59c8e839560	1596	* @}
AnnaBridge	163:e59c8e839560	1597	*/
AnnaBridge	163:e59c8e839560	1598	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	1599
AnnaBridge	163:e59c8e839560	1600	/**
AnnaBridge	163:e59c8e839560	1601	* @}
AnnaBridge	163:e59c8e839560	1602	*/
AnnaBridge	163:e59c8e839560	1603
AnnaBridge	163:e59c8e839560	1604	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1605	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	163:e59c8e839560	1606	* @{
AnnaBridge	163:e59c8e839560	1607	*/
AnnaBridge	163:e59c8e839560	1608
AnnaBridge	163:e59c8e839560	1609	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	163:e59c8e839560	1610	* @{
AnnaBridge	163:e59c8e839560	1611	*/
AnnaBridge	163:e59c8e839560	1612
AnnaBridge	163:e59c8e839560	1613	/**
AnnaBridge	163:e59c8e839560	1614	* @brief Write a value in I2S register
AnnaBridge	163:e59c8e839560	1615	* @param __INSTANCE__ I2S Instance
AnnaBridge	163:e59c8e839560	1616	* @param __REG__ Register to be written
AnnaBridge	163:e59c8e839560	1617	* @param __VALUE__ Value to be written in the register
AnnaBridge	163:e59c8e839560	1618	* @retval None
AnnaBridge	163:e59c8e839560	1619	*/
AnnaBridge	163:e59c8e839560	1620	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	163:e59c8e839560	1621
AnnaBridge	163:e59c8e839560	1622	/**
AnnaBridge	163:e59c8e839560	1623	* @brief Read a value in I2S register
AnnaBridge	163:e59c8e839560	1624	* @param __INSTANCE__ I2S Instance
AnnaBridge	163:e59c8e839560	1625	* @param __REG__ Register to be read
AnnaBridge	163:e59c8e839560	1626	* @retval Register value
AnnaBridge	163:e59c8e839560	1627	*/
AnnaBridge	163:e59c8e839560	1628	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	163:e59c8e839560	1629	/**
AnnaBridge	163:e59c8e839560	1630	* @}
AnnaBridge	163:e59c8e839560	1631	*/
AnnaBridge	163:e59c8e839560	1632
AnnaBridge	163:e59c8e839560	1633	/**
AnnaBridge	163:e59c8e839560	1634	* @}
AnnaBridge	163:e59c8e839560	1635	*/
AnnaBridge	163:e59c8e839560	1636
AnnaBridge	163:e59c8e839560	1637
AnnaBridge	163:e59c8e839560	1638	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1639
AnnaBridge	163:e59c8e839560	1640	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	163:e59c8e839560	1641	* @{
AnnaBridge	163:e59c8e839560	1642	*/
AnnaBridge	163:e59c8e839560	1643
AnnaBridge	163:e59c8e839560	1644	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	163:e59c8e839560	1645	* @{
AnnaBridge	163:e59c8e839560	1646	*/
AnnaBridge	163:e59c8e839560	1647
AnnaBridge	163:e59c8e839560	1648	/**
AnnaBridge	163:e59c8e839560	1649	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	163:e59c8e839560	1650	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	163:e59c8e839560	1651	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	163:e59c8e839560	1652	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1653	* @retval None
AnnaBridge	163:e59c8e839560	1654	*/
AnnaBridge	163:e59c8e839560	1655	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1656	{
AnnaBridge	163:e59c8e839560	1657	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	163:e59c8e839560	1658	}
AnnaBridge	163:e59c8e839560	1659
AnnaBridge	163:e59c8e839560	1660	/**
AnnaBridge	163:e59c8e839560	1661	* @brief Disable I2S peripheral
AnnaBridge	163:e59c8e839560	1662	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	163:e59c8e839560	1663	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1664	* @retval None
AnnaBridge	163:e59c8e839560	1665	*/
AnnaBridge	163:e59c8e839560	1666	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1667	{
AnnaBridge	163:e59c8e839560	1668	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	163:e59c8e839560	1669	}
AnnaBridge	163:e59c8e839560	1670
AnnaBridge	163:e59c8e839560	1671	/**
AnnaBridge	163:e59c8e839560	1672	* @brief Check if I2S peripheral is enabled
AnnaBridge	163:e59c8e839560	1673	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	163:e59c8e839560	1674	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1675	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1676	*/
AnnaBridge	163:e59c8e839560	1677	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1678	{
AnnaBridge	163:e59c8e839560	1679	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	163:e59c8e839560	1680	}
AnnaBridge	163:e59c8e839560	1681
AnnaBridge	163:e59c8e839560	1682	/**
AnnaBridge	163:e59c8e839560	1683	* @brief Set I2S data frame length
AnnaBridge	163:e59c8e839560	1684	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	163:e59c8e839560	1685	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	163:e59c8e839560	1686	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1687	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1688	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	163:e59c8e839560	1689	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	163:e59c8e839560	1690	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	163:e59c8e839560	1691	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	163:e59c8e839560	1692	* @retval None
AnnaBridge	163:e59c8e839560	1693	*/
AnnaBridge	163:e59c8e839560	1694	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	163:e59c8e839560	1695	{
AnnaBridge	163:e59c8e839560	1696	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	163:e59c8e839560	1697	}
AnnaBridge	163:e59c8e839560	1698
AnnaBridge	163:e59c8e839560	1699	/**
AnnaBridge	163:e59c8e839560	1700	* @brief Get I2S data frame length
AnnaBridge	163:e59c8e839560	1701	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	163:e59c8e839560	1702	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	163:e59c8e839560	1703	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1704	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1705	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	163:e59c8e839560	1706	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	163:e59c8e839560	1707	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	163:e59c8e839560	1708	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	163:e59c8e839560	1709	*/
AnnaBridge	163:e59c8e839560	1710	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1711	{
AnnaBridge	163:e59c8e839560	1712	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	163:e59c8e839560	1713	}
AnnaBridge	163:e59c8e839560	1714
AnnaBridge	163:e59c8e839560	1715	/**
AnnaBridge	163:e59c8e839560	1716	* @brief Set I2S clock polarity
AnnaBridge	163:e59c8e839560	1717	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	163:e59c8e839560	1718	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1719	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1720	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	163:e59c8e839560	1721	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	1722	* @retval None
AnnaBridge	163:e59c8e839560	1723	*/
AnnaBridge	163:e59c8e839560	1724	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	163:e59c8e839560	1725	{
AnnaBridge	163:e59c8e839560	1726	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	163:e59c8e839560	1727	}
AnnaBridge	163:e59c8e839560	1728
AnnaBridge	163:e59c8e839560	1729	/**
AnnaBridge	163:e59c8e839560	1730	* @brief Get I2S clock polarity
AnnaBridge	163:e59c8e839560	1731	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	163:e59c8e839560	1732	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1733	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1734	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	163:e59c8e839560	1735	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	163:e59c8e839560	1736	*/
AnnaBridge	163:e59c8e839560	1737	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1738	{
AnnaBridge	163:e59c8e839560	1739	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	163:e59c8e839560	1740	}
AnnaBridge	163:e59c8e839560	1741
AnnaBridge	163:e59c8e839560	1742	/**
AnnaBridge	163:e59c8e839560	1743	* @brief Set I2S standard protocol
AnnaBridge	163:e59c8e839560	1744	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	163:e59c8e839560	1745	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	163:e59c8e839560	1746	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1747	* @param Standard This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1748	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	163:e59c8e839560	1749	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	163:e59c8e839560	1750	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	163:e59c8e839560	1751	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	163:e59c8e839560	1752	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	163:e59c8e839560	1753	* @retval None
AnnaBridge	163:e59c8e839560	1754	*/
AnnaBridge	163:e59c8e839560	1755	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	163:e59c8e839560	1756	{
AnnaBridge	163:e59c8e839560	1757	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	163:e59c8e839560	1758	}
AnnaBridge	163:e59c8e839560	1759
AnnaBridge	163:e59c8e839560	1760	/**
AnnaBridge	163:e59c8e839560	1761	* @brief Get I2S standard protocol
AnnaBridge	163:e59c8e839560	1762	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	163:e59c8e839560	1763	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	163:e59c8e839560	1764	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1765	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1766	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	163:e59c8e839560	1767	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	163:e59c8e839560	1768	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	163:e59c8e839560	1769	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	163:e59c8e839560	1770	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	163:e59c8e839560	1771	*/
AnnaBridge	163:e59c8e839560	1772	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1773	{
AnnaBridge	163:e59c8e839560	1774	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	163:e59c8e839560	1775	}
AnnaBridge	163:e59c8e839560	1776
AnnaBridge	163:e59c8e839560	1777	/**
AnnaBridge	163:e59c8e839560	1778	* @brief Set I2S transfer mode
AnnaBridge	163:e59c8e839560	1779	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	163:e59c8e839560	1780	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1781	* @param Mode This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1782	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	163:e59c8e839560	1783	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	163:e59c8e839560	1784	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	163:e59c8e839560	1785	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	163:e59c8e839560	1786	* @retval None
AnnaBridge	163:e59c8e839560	1787	*/
AnnaBridge	163:e59c8e839560	1788	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	163:e59c8e839560	1789	{
AnnaBridge	163:e59c8e839560	1790	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	163:e59c8e839560	1791	}
AnnaBridge	163:e59c8e839560	1792
AnnaBridge	163:e59c8e839560	1793	/**
AnnaBridge	163:e59c8e839560	1794	* @brief Get I2S transfer mode
AnnaBridge	163:e59c8e839560	1795	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	163:e59c8e839560	1796	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1797	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1798	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	163:e59c8e839560	1799	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	163:e59c8e839560	1800	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	163:e59c8e839560	1801	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	163:e59c8e839560	1802	*/
AnnaBridge	163:e59c8e839560	1803	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1804	{
AnnaBridge	163:e59c8e839560	1805	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	163:e59c8e839560	1806	}
AnnaBridge	163:e59c8e839560	1807
AnnaBridge	163:e59c8e839560	1808	/**
AnnaBridge	163:e59c8e839560	1809	* @brief Set I2S linear prescaler
AnnaBridge	163:e59c8e839560	1810	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	163:e59c8e839560	1811	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1812	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	163:e59c8e839560	1813	* @retval None
AnnaBridge	163:e59c8e839560	1814	*/
AnnaBridge	163:e59c8e839560	1815	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	163:e59c8e839560	1816	{
AnnaBridge	163:e59c8e839560	1817	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	163:e59c8e839560	1818	}
AnnaBridge	163:e59c8e839560	1819
AnnaBridge	163:e59c8e839560	1820	/**
AnnaBridge	163:e59c8e839560	1821	* @brief Get I2S linear prescaler
AnnaBridge	163:e59c8e839560	1822	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	163:e59c8e839560	1823	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1824	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	163:e59c8e839560	1825	*/
AnnaBridge	163:e59c8e839560	1826	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1827	{
AnnaBridge	163:e59c8e839560	1828	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	163:e59c8e839560	1829	}
AnnaBridge	163:e59c8e839560	1830
AnnaBridge	163:e59c8e839560	1831	/**
AnnaBridge	163:e59c8e839560	1832	* @brief Set I2S parity prescaler
AnnaBridge	163:e59c8e839560	1833	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	163:e59c8e839560	1834	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1835	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1836	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1837	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	163:e59c8e839560	1838	* @retval None
AnnaBridge	163:e59c8e839560	1839	*/
AnnaBridge	163:e59c8e839560	1840	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	163:e59c8e839560	1841	{
AnnaBridge	163:e59c8e839560	1842	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	163:e59c8e839560	1843	}
AnnaBridge	163:e59c8e839560	1844
AnnaBridge	163:e59c8e839560	1845	/**
AnnaBridge	163:e59c8e839560	1846	* @brief Get I2S parity prescaler
AnnaBridge	163:e59c8e839560	1847	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	163:e59c8e839560	1848	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1849	* @retval Returned value can be one of the following values:
AnnaBridge	163:e59c8e839560	1850	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	163:e59c8e839560	1851	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	163:e59c8e839560	1852	*/
AnnaBridge	163:e59c8e839560	1853	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1854	{
AnnaBridge	163:e59c8e839560	1855	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	163:e59c8e839560	1856	}
AnnaBridge	163:e59c8e839560	1857
AnnaBridge	163:e59c8e839560	1858	/**
AnnaBridge	163:e59c8e839560	1859	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	163:e59c8e839560	1860	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	163:e59c8e839560	1861	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1862	* @retval None
AnnaBridge	163:e59c8e839560	1863	*/
AnnaBridge	163:e59c8e839560	1864	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1865	{
AnnaBridge	163:e59c8e839560	1866	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	163:e59c8e839560	1867	}
AnnaBridge	163:e59c8e839560	1868
AnnaBridge	163:e59c8e839560	1869	/**
AnnaBridge	163:e59c8e839560	1870	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	163:e59c8e839560	1871	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	163:e59c8e839560	1872	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1873	* @retval None
AnnaBridge	163:e59c8e839560	1874	*/
AnnaBridge	163:e59c8e839560	1875	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1876	{
AnnaBridge	163:e59c8e839560	1877	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	163:e59c8e839560	1878	}
AnnaBridge	163:e59c8e839560	1879
AnnaBridge	163:e59c8e839560	1880	/**
AnnaBridge	163:e59c8e839560	1881	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	163:e59c8e839560	1882	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	163:e59c8e839560	1883	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1884	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1885	*/
AnnaBridge	163:e59c8e839560	1886	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1887	{
AnnaBridge	163:e59c8e839560	1888	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	163:e59c8e839560	1889	}
AnnaBridge	163:e59c8e839560	1890
AnnaBridge	163:e59c8e839560	1891	/**
AnnaBridge	163:e59c8e839560	1892	* @}
AnnaBridge	163:e59c8e839560	1893	*/
AnnaBridge	163:e59c8e839560	1894
AnnaBridge	163:e59c8e839560	1895	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	163:e59c8e839560	1896	* @{
AnnaBridge	163:e59c8e839560	1897	*/
AnnaBridge	163:e59c8e839560	1898
AnnaBridge	163:e59c8e839560	1899	/**
AnnaBridge	163:e59c8e839560	1900	* @brief Check if Rx buffer is not empty
AnnaBridge	163:e59c8e839560	1901	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	163:e59c8e839560	1902	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1903	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1904	*/
AnnaBridge	163:e59c8e839560	1905	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1906	{
AnnaBridge	163:e59c8e839560	1907	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	163:e59c8e839560	1908	}
AnnaBridge	163:e59c8e839560	1909
AnnaBridge	163:e59c8e839560	1910	/**
AnnaBridge	163:e59c8e839560	1911	* @brief Check if Tx buffer is empty
AnnaBridge	163:e59c8e839560	1912	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	163:e59c8e839560	1913	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1914	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1915	*/
AnnaBridge	163:e59c8e839560	1916	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1917	{
AnnaBridge	163:e59c8e839560	1918	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	163:e59c8e839560	1919	}
AnnaBridge	163:e59c8e839560	1920
AnnaBridge	163:e59c8e839560	1921	/**
AnnaBridge	163:e59c8e839560	1922	* @brief Get busy flag
AnnaBridge	163:e59c8e839560	1923	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	163:e59c8e839560	1924	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1925	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1926	*/
AnnaBridge	163:e59c8e839560	1927	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1928	{
AnnaBridge	163:e59c8e839560	1929	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	163:e59c8e839560	1930	}
AnnaBridge	163:e59c8e839560	1931
AnnaBridge	163:e59c8e839560	1932	/**
AnnaBridge	163:e59c8e839560	1933	* @brief Get overrun error flag
AnnaBridge	163:e59c8e839560	1934	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	163:e59c8e839560	1935	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1936	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1937	*/
AnnaBridge	163:e59c8e839560	1938	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1939	{
AnnaBridge	163:e59c8e839560	1940	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	163:e59c8e839560	1941	}
AnnaBridge	163:e59c8e839560	1942
AnnaBridge	163:e59c8e839560	1943	/**
AnnaBridge	163:e59c8e839560	1944	* @brief Get underrun error flag
AnnaBridge	163:e59c8e839560	1945	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	163:e59c8e839560	1946	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1947	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1948	*/
AnnaBridge	163:e59c8e839560	1949	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1950	{
AnnaBridge	163:e59c8e839560	1951	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	163:e59c8e839560	1952	}
AnnaBridge	163:e59c8e839560	1953
AnnaBridge	163:e59c8e839560	1954	/**
AnnaBridge	163:e59c8e839560	1955	* @brief Get frame format error flag
AnnaBridge	163:e59c8e839560	1956	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	163:e59c8e839560	1957	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1958	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1959	*/
AnnaBridge	163:e59c8e839560	1960	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1961	{
AnnaBridge	163:e59c8e839560	1962	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	163:e59c8e839560	1963	}
AnnaBridge	163:e59c8e839560	1964
AnnaBridge	163:e59c8e839560	1965	/**
AnnaBridge	163:e59c8e839560	1966	* @brief Get channel side flag.
AnnaBridge	163:e59c8e839560	1967	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	163:e59c8e839560	1968	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	163:e59c8e839560	1969	* It has no significance in PCM mode.
AnnaBridge	163:e59c8e839560	1970	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	163:e59c8e839560	1971	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1972	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	1973	*/
AnnaBridge	163:e59c8e839560	1974	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1975	{
AnnaBridge	163:e59c8e839560	1976	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	163:e59c8e839560	1977	}
AnnaBridge	163:e59c8e839560	1978
AnnaBridge	163:e59c8e839560	1979	/**
AnnaBridge	163:e59c8e839560	1980	* @brief Clear overrun error flag
AnnaBridge	163:e59c8e839560	1981	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	163:e59c8e839560	1982	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1983	* @retval None
AnnaBridge	163:e59c8e839560	1984	*/
AnnaBridge	163:e59c8e839560	1985	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1986	{
AnnaBridge	163:e59c8e839560	1987	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	163:e59c8e839560	1988	}
AnnaBridge	163:e59c8e839560	1989
AnnaBridge	163:e59c8e839560	1990	/**
AnnaBridge	163:e59c8e839560	1991	* @brief Clear underrun error flag
AnnaBridge	163:e59c8e839560	1992	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	163:e59c8e839560	1993	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	1994	* @retval None
AnnaBridge	163:e59c8e839560	1995	*/
AnnaBridge	163:e59c8e839560	1996	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	1997	{
AnnaBridge	163:e59c8e839560	1998	__IO uint32_t tmpreg;
AnnaBridge	163:e59c8e839560	1999	tmpreg = SPIx->SR;
AnnaBridge	163:e59c8e839560	2000	(void)tmpreg;
AnnaBridge	163:e59c8e839560	2001	}
AnnaBridge	163:e59c8e839560	2002
AnnaBridge	163:e59c8e839560	2003	/**
AnnaBridge	163:e59c8e839560	2004	* @brief Clear frame format error flag
AnnaBridge	163:e59c8e839560	2005	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	163:e59c8e839560	2006	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2007	* @retval None
AnnaBridge	163:e59c8e839560	2008	*/
AnnaBridge	163:e59c8e839560	2009	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2010	{
AnnaBridge	163:e59c8e839560	2011	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	163:e59c8e839560	2012	}
AnnaBridge	163:e59c8e839560	2013
AnnaBridge	163:e59c8e839560	2014	/**
AnnaBridge	163:e59c8e839560	2015	* @}
AnnaBridge	163:e59c8e839560	2016	*/
AnnaBridge	163:e59c8e839560	2017
AnnaBridge	163:e59c8e839560	2018	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	163:e59c8e839560	2019	* @{
AnnaBridge	163:e59c8e839560	2020	*/
AnnaBridge	163:e59c8e839560	2021
AnnaBridge	163:e59c8e839560	2022	/**
AnnaBridge	163:e59c8e839560	2023	* @brief Enable error IT
AnnaBridge	163:e59c8e839560	2024	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	163:e59c8e839560	2025	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	163:e59c8e839560	2026	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2027	* @retval None
AnnaBridge	163:e59c8e839560	2028	*/
AnnaBridge	163:e59c8e839560	2029	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2030	{
AnnaBridge	163:e59c8e839560	2031	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	163:e59c8e839560	2032	}
AnnaBridge	163:e59c8e839560	2033
AnnaBridge	163:e59c8e839560	2034	/**
AnnaBridge	163:e59c8e839560	2035	* @brief Enable Rx buffer not empty IT
AnnaBridge	163:e59c8e839560	2036	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	163:e59c8e839560	2037	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2038	* @retval None
AnnaBridge	163:e59c8e839560	2039	*/
AnnaBridge	163:e59c8e839560	2040	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2041	{
AnnaBridge	163:e59c8e839560	2042	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	163:e59c8e839560	2043	}
AnnaBridge	163:e59c8e839560	2044
AnnaBridge	163:e59c8e839560	2045	/**
AnnaBridge	163:e59c8e839560	2046	* @brief Enable Tx buffer empty IT
AnnaBridge	163:e59c8e839560	2047	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	163:e59c8e839560	2048	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2049	* @retval None
AnnaBridge	163:e59c8e839560	2050	*/
AnnaBridge	163:e59c8e839560	2051	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2052	{
AnnaBridge	163:e59c8e839560	2053	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	163:e59c8e839560	2054	}
AnnaBridge	163:e59c8e839560	2055
AnnaBridge	163:e59c8e839560	2056	/**
AnnaBridge	163:e59c8e839560	2057	* @brief Disable error IT
AnnaBridge	163:e59c8e839560	2058	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	163:e59c8e839560	2059	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	163:e59c8e839560	2060	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2061	* @retval None
AnnaBridge	163:e59c8e839560	2062	*/
AnnaBridge	163:e59c8e839560	2063	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2064	{
AnnaBridge	163:e59c8e839560	2065	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	163:e59c8e839560	2066	}
AnnaBridge	163:e59c8e839560	2067
AnnaBridge	163:e59c8e839560	2068	/**
AnnaBridge	163:e59c8e839560	2069	* @brief Disable Rx buffer not empty IT
AnnaBridge	163:e59c8e839560	2070	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	163:e59c8e839560	2071	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2072	* @retval None
AnnaBridge	163:e59c8e839560	2073	*/
AnnaBridge	163:e59c8e839560	2074	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2075	{
AnnaBridge	163:e59c8e839560	2076	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	163:e59c8e839560	2077	}
AnnaBridge	163:e59c8e839560	2078
AnnaBridge	163:e59c8e839560	2079	/**
AnnaBridge	163:e59c8e839560	2080	* @brief Disable Tx buffer empty IT
AnnaBridge	163:e59c8e839560	2081	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	163:e59c8e839560	2082	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2083	* @retval None
AnnaBridge	163:e59c8e839560	2084	*/
AnnaBridge	163:e59c8e839560	2085	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2086	{
AnnaBridge	163:e59c8e839560	2087	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	163:e59c8e839560	2088	}
AnnaBridge	163:e59c8e839560	2089
AnnaBridge	163:e59c8e839560	2090	/**
AnnaBridge	163:e59c8e839560	2091	* @brief Check if ERR IT is enabled
AnnaBridge	163:e59c8e839560	2092	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	163:e59c8e839560	2093	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2094	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2095	*/
AnnaBridge	163:e59c8e839560	2096	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2097	{
AnnaBridge	163:e59c8e839560	2098	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	163:e59c8e839560	2099	}
AnnaBridge	163:e59c8e839560	2100
AnnaBridge	163:e59c8e839560	2101	/**
AnnaBridge	163:e59c8e839560	2102	* @brief Check if RXNE IT is enabled
AnnaBridge	163:e59c8e839560	2103	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	163:e59c8e839560	2104	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2105	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2106	*/
AnnaBridge	163:e59c8e839560	2107	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2108	{
AnnaBridge	163:e59c8e839560	2109	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	163:e59c8e839560	2110	}
AnnaBridge	163:e59c8e839560	2111
AnnaBridge	163:e59c8e839560	2112	/**
AnnaBridge	163:e59c8e839560	2113	* @brief Check if TXE IT is enabled
AnnaBridge	163:e59c8e839560	2114	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	163:e59c8e839560	2115	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2116	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2117	*/
AnnaBridge	163:e59c8e839560	2118	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2119	{
AnnaBridge	163:e59c8e839560	2120	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	163:e59c8e839560	2121	}
AnnaBridge	163:e59c8e839560	2122
AnnaBridge	163:e59c8e839560	2123	/**
AnnaBridge	163:e59c8e839560	2124	* @}
AnnaBridge	163:e59c8e839560	2125	*/
AnnaBridge	163:e59c8e839560	2126
AnnaBridge	163:e59c8e839560	2127	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	163:e59c8e839560	2128	* @{
AnnaBridge	163:e59c8e839560	2129	*/
AnnaBridge	163:e59c8e839560	2130
AnnaBridge	163:e59c8e839560	2131	/**
AnnaBridge	163:e59c8e839560	2132	* @brief Enable DMA Rx
AnnaBridge	163:e59c8e839560	2133	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	163:e59c8e839560	2134	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2135	* @retval None
AnnaBridge	163:e59c8e839560	2136	*/
AnnaBridge	163:e59c8e839560	2137	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2138	{
AnnaBridge	163:e59c8e839560	2139	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	163:e59c8e839560	2140	}
AnnaBridge	163:e59c8e839560	2141
AnnaBridge	163:e59c8e839560	2142	/**
AnnaBridge	163:e59c8e839560	2143	* @brief Disable DMA Rx
AnnaBridge	163:e59c8e839560	2144	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	163:e59c8e839560	2145	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2146	* @retval None
AnnaBridge	163:e59c8e839560	2147	*/
AnnaBridge	163:e59c8e839560	2148	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2149	{
AnnaBridge	163:e59c8e839560	2150	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	163:e59c8e839560	2151	}
AnnaBridge	163:e59c8e839560	2152
AnnaBridge	163:e59c8e839560	2153	/**
AnnaBridge	163:e59c8e839560	2154	* @brief Check if DMA Rx is enabled
AnnaBridge	163:e59c8e839560	2155	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	163:e59c8e839560	2156	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2157	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2158	*/
AnnaBridge	163:e59c8e839560	2159	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2160	{
AnnaBridge	163:e59c8e839560	2161	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	163:e59c8e839560	2162	}
AnnaBridge	163:e59c8e839560	2163
AnnaBridge	163:e59c8e839560	2164	/**
AnnaBridge	163:e59c8e839560	2165	* @brief Enable DMA Tx
AnnaBridge	163:e59c8e839560	2166	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	163:e59c8e839560	2167	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2168	* @retval None
AnnaBridge	163:e59c8e839560	2169	*/
AnnaBridge	163:e59c8e839560	2170	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2171	{
AnnaBridge	163:e59c8e839560	2172	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	163:e59c8e839560	2173	}
AnnaBridge	163:e59c8e839560	2174
AnnaBridge	163:e59c8e839560	2175	/**
AnnaBridge	163:e59c8e839560	2176	* @brief Disable DMA Tx
AnnaBridge	163:e59c8e839560	2177	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	163:e59c8e839560	2178	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2179	* @retval None
AnnaBridge	163:e59c8e839560	2180	*/
AnnaBridge	163:e59c8e839560	2181	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2182	{
AnnaBridge	163:e59c8e839560	2183	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	163:e59c8e839560	2184	}
AnnaBridge	163:e59c8e839560	2185
AnnaBridge	163:e59c8e839560	2186	/**
AnnaBridge	163:e59c8e839560	2187	* @brief Check if DMA Tx is enabled
AnnaBridge	163:e59c8e839560	2188	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	163:e59c8e839560	2189	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2190	* @retval State of bit (1 or 0).
AnnaBridge	163:e59c8e839560	2191	*/
AnnaBridge	163:e59c8e839560	2192	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2193	{
AnnaBridge	163:e59c8e839560	2194	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	163:e59c8e839560	2195	}
AnnaBridge	163:e59c8e839560	2196
AnnaBridge	163:e59c8e839560	2197	/**
AnnaBridge	163:e59c8e839560	2198	* @}
AnnaBridge	163:e59c8e839560	2199	*/
AnnaBridge	163:e59c8e839560	2200
AnnaBridge	163:e59c8e839560	2201	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	163:e59c8e839560	2202	* @{
AnnaBridge	163:e59c8e839560	2203	*/
AnnaBridge	163:e59c8e839560	2204
AnnaBridge	163:e59c8e839560	2205	/**
AnnaBridge	163:e59c8e839560	2206	* @brief Read 16-Bits in data register
AnnaBridge	163:e59c8e839560	2207	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	163:e59c8e839560	2208	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2209	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	163:e59c8e839560	2210	*/
AnnaBridge	163:e59c8e839560	2211	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	163:e59c8e839560	2212	{
AnnaBridge	163:e59c8e839560	2213	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	163:e59c8e839560	2214	}
AnnaBridge	163:e59c8e839560	2215
AnnaBridge	163:e59c8e839560	2216	/**
AnnaBridge	163:e59c8e839560	2217	* @brief Write 16-Bits in data register
AnnaBridge	163:e59c8e839560	2218	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	163:e59c8e839560	2219	* @param SPIx SPI Instance
AnnaBridge	163:e59c8e839560	2220	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	163:e59c8e839560	2221	* @retval None
AnnaBridge	163:e59c8e839560	2222	*/
AnnaBridge	163:e59c8e839560	2223	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	163:e59c8e839560	2224	{
AnnaBridge	163:e59c8e839560	2225	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	163:e59c8e839560	2226	}
AnnaBridge	163:e59c8e839560	2227
AnnaBridge	163:e59c8e839560	2228	/**
AnnaBridge	163:e59c8e839560	2229	* @}
AnnaBridge	163:e59c8e839560	2230	*/
AnnaBridge	163:e59c8e839560	2231
AnnaBridge	163:e59c8e839560	2232	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	163:e59c8e839560	2233	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	163:e59c8e839560	2234	* @{
AnnaBridge	163:e59c8e839560	2235	*/
AnnaBridge	163:e59c8e839560	2236
AnnaBridge	163:e59c8e839560	2237	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	163:e59c8e839560	2238	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	163:e59c8e839560	2239	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	163:e59c8e839560	2240	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	163:e59c8e839560	2241	#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
AnnaBridge	163:e59c8e839560	2242	ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef I2Sxext, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	163:e59c8e839560	2243	#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
AnnaBridge	163:e59c8e839560	2244
AnnaBridge	163:e59c8e839560	2245	/**
AnnaBridge	163:e59c8e839560	2246	* @}
AnnaBridge	163:e59c8e839560	2247	*/
AnnaBridge	163:e59c8e839560	2248	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	163:e59c8e839560	2249
AnnaBridge	163:e59c8e839560	2250	/**
AnnaBridge	163:e59c8e839560	2251	* @}
AnnaBridge	163:e59c8e839560	2252	*/
AnnaBridge	163:e59c8e839560	2253
AnnaBridge	163:e59c8e839560	2254	/**
AnnaBridge	163:e59c8e839560	2255	* @}
AnnaBridge	163:e59c8e839560	2256	*/
AnnaBridge	163:e59c8e839560	2257	#endif /* SPI_I2S_SUPPORT */
AnnaBridge	163:e59c8e839560	2258
AnnaBridge	163:e59c8e839560	2259	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) */
AnnaBridge	163:e59c8e839560	2260
AnnaBridge	163:e59c8e839560	2261	/**
AnnaBridge	163:e59c8e839560	2262	* @}
AnnaBridge	163:e59c8e839560	2263	*/
AnnaBridge	163:e59c8e839560	2264
AnnaBridge	163:e59c8e839560	2265	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	2266	}
AnnaBridge	163:e59c8e839560	2267	#endif
AnnaBridge	163:e59c8e839560	2268
AnnaBridge	163:e59c8e839560	2269	#endif /* __STM32F3xx_LL_SPI_H */
AnnaBridge	163:e59c8e839560	2270
AnnaBridge	163:e59c8e839560	2271	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/