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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_ll_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h@168:b9e159c1930a 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 163:e59c8e839560 1 /**
AnnaBridge 163:e59c8e839560 2 ******************************************************************************
AnnaBridge 163:e59c8e839560 3 * @file stm32f3xx_ll_dma.h
AnnaBridge 163:e59c8e839560 4 * @author MCD Application Team
AnnaBridge 163:e59c8e839560 5 * @brief Header file of DMA LL module.
AnnaBridge 163:e59c8e839560 6 ******************************************************************************
AnnaBridge 163:e59c8e839560 7 * @attention
AnnaBridge 163:e59c8e839560 8 *
AnnaBridge 163:e59c8e839560 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 163:e59c8e839560 10 *
AnnaBridge 163:e59c8e839560 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 163:e59c8e839560 12 * are permitted provided that the following conditions are met:
AnnaBridge 163:e59c8e839560 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 163:e59c8e839560 14 * this list of conditions and the following disclaimer.
AnnaBridge 163:e59c8e839560 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 163:e59c8e839560 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 163:e59c8e839560 17 * and/or other materials provided with the distribution.
AnnaBridge 163:e59c8e839560 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 163:e59c8e839560 19 * may be used to endorse or promote products derived from this software
AnnaBridge 163:e59c8e839560 20 * without specific prior written permission.
AnnaBridge 163:e59c8e839560 21 *
AnnaBridge 163:e59c8e839560 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 163:e59c8e839560 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 163:e59c8e839560 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 163:e59c8e839560 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 163:e59c8e839560 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 163:e59c8e839560 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 163:e59c8e839560 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 163:e59c8e839560 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 163:e59c8e839560 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 163:e59c8e839560 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 163:e59c8e839560 32 *
AnnaBridge 163:e59c8e839560 33 ******************************************************************************
AnnaBridge 163:e59c8e839560 34 */
AnnaBridge 163:e59c8e839560 35
AnnaBridge 163:e59c8e839560 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 163:e59c8e839560 37 #ifndef __STM32F3xx_LL_DMA_H
AnnaBridge 163:e59c8e839560 38 #define __STM32F3xx_LL_DMA_H
AnnaBridge 163:e59c8e839560 39
AnnaBridge 163:e59c8e839560 40 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 41 extern "C" {
AnnaBridge 163:e59c8e839560 42 #endif
AnnaBridge 163:e59c8e839560 43
AnnaBridge 163:e59c8e839560 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 45 #include "stm32f3xx.h"
AnnaBridge 163:e59c8e839560 46
AnnaBridge 163:e59c8e839560 47 /** @addtogroup STM32F3xx_LL_Driver
AnnaBridge 163:e59c8e839560 48 * @{
AnnaBridge 163:e59c8e839560 49 */
AnnaBridge 163:e59c8e839560 50
AnnaBridge 163:e59c8e839560 51 #if defined (DMA1) || defined (DMA2)
AnnaBridge 163:e59c8e839560 52
AnnaBridge 163:e59c8e839560 53 /** @defgroup DMA_LL DMA
AnnaBridge 163:e59c8e839560 54 * @{
AnnaBridge 163:e59c8e839560 55 */
AnnaBridge 163:e59c8e839560 56
AnnaBridge 163:e59c8e839560 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge 163:e59c8e839560 60 * @{
AnnaBridge 163:e59c8e839560 61 */
AnnaBridge 163:e59c8e839560 62 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge 163:e59c8e839560 63 static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge 163:e59c8e839560 64 {
AnnaBridge 163:e59c8e839560 65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 70 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge 163:e59c8e839560 71 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge 163:e59c8e839560 72 };
AnnaBridge 163:e59c8e839560 73 /**
AnnaBridge 163:e59c8e839560 74 * @}
AnnaBridge 163:e59c8e839560 75 */
AnnaBridge 163:e59c8e839560 76
AnnaBridge 163:e59c8e839560 77 /* Private constants ---------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 78 /* Private macros ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 79 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 163:e59c8e839560 80 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge 163:e59c8e839560 81 * @{
AnnaBridge 163:e59c8e839560 82 */
AnnaBridge 163:e59c8e839560 83 /**
AnnaBridge 163:e59c8e839560 84 * @}
AnnaBridge 163:e59c8e839560 85 */
AnnaBridge 163:e59c8e839560 86 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 163:e59c8e839560 87
AnnaBridge 163:e59c8e839560 88 /* Exported types ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 89 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 163:e59c8e839560 90 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge 163:e59c8e839560 91 * @{
AnnaBridge 163:e59c8e839560 92 */
AnnaBridge 163:e59c8e839560 93 typedef struct
AnnaBridge 163:e59c8e839560 94 {
AnnaBridge 163:e59c8e839560 95 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge 163:e59c8e839560 96 or as Source base address in case of memory to memory transfer direction.
AnnaBridge 163:e59c8e839560 97
AnnaBridge 163:e59c8e839560 98 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 163:e59c8e839560 99
AnnaBridge 163:e59c8e839560 100 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge 163:e59c8e839560 101 or as Destination base address in case of memory to memory transfer direction.
AnnaBridge 163:e59c8e839560 102
AnnaBridge 163:e59c8e839560 103 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 163:e59c8e839560 104
AnnaBridge 163:e59c8e839560 105 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 163:e59c8e839560 106 from memory to memory or from peripheral to memory.
AnnaBridge 163:e59c8e839560 107 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge 163:e59c8e839560 108
AnnaBridge 163:e59c8e839560 109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge 163:e59c8e839560 110
AnnaBridge 163:e59c8e839560 111 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge 163:e59c8e839560 112 This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge 163:e59c8e839560 113 @note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge 163:e59c8e839560 114 data transfer direction is configured on the selected Channel
AnnaBridge 163:e59c8e839560 115
AnnaBridge 163:e59c8e839560 116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge 163:e59c8e839560 117
AnnaBridge 163:e59c8e839560 118 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge 163:e59c8e839560 119 is incremented or not.
AnnaBridge 163:e59c8e839560 120 This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge 163:e59c8e839560 121
AnnaBridge 163:e59c8e839560 122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge 163:e59c8e839560 123
AnnaBridge 163:e59c8e839560 124 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge 163:e59c8e839560 125 is incremented or not.
AnnaBridge 163:e59c8e839560 126 This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge 163:e59c8e839560 127
AnnaBridge 163:e59c8e839560 128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge 163:e59c8e839560 129
AnnaBridge 163:e59c8e839560 130 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge 163:e59c8e839560 131 in case of memory to memory transfer direction.
AnnaBridge 163:e59c8e839560 132 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge 163:e59c8e839560 133
AnnaBridge 163:e59c8e839560 134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge 163:e59c8e839560 135
AnnaBridge 163:e59c8e839560 136 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge 163:e59c8e839560 137 in case of memory to memory transfer direction.
AnnaBridge 163:e59c8e839560 138 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge 163:e59c8e839560 139
AnnaBridge 163:e59c8e839560 140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge 163:e59c8e839560 141
AnnaBridge 163:e59c8e839560 142 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge 163:e59c8e839560 143 The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge 163:e59c8e839560 144 or MemorySize parameters depending in the transfer direction.
AnnaBridge 163:e59c8e839560 145 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 163:e59c8e839560 146
AnnaBridge 163:e59c8e839560 147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge 163:e59c8e839560 148
AnnaBridge 163:e59c8e839560 149 uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge 163:e59c8e839560 150 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge 163:e59c8e839560 151
AnnaBridge 163:e59c8e839560 152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge 163:e59c8e839560 153
AnnaBridge 163:e59c8e839560 154 } LL_DMA_InitTypeDef;
AnnaBridge 163:e59c8e839560 155 /**
AnnaBridge 163:e59c8e839560 156 * @}
AnnaBridge 163:e59c8e839560 157 */
AnnaBridge 163:e59c8e839560 158 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 163:e59c8e839560 159
AnnaBridge 163:e59c8e839560 160 /* Exported constants --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge 163:e59c8e839560 162 * @{
AnnaBridge 163:e59c8e839560 163 */
AnnaBridge 163:e59c8e839560 164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 163:e59c8e839560 165 * @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge 163:e59c8e839560 166 * @{
AnnaBridge 163:e59c8e839560 167 */
AnnaBridge 163:e59c8e839560 168 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
AnnaBridge 163:e59c8e839560 169 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 163:e59c8e839560 170 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 163:e59c8e839560 171 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 163:e59c8e839560 172 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
AnnaBridge 163:e59c8e839560 173 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 163:e59c8e839560 174 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 163:e59c8e839560 175 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 163:e59c8e839560 176 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
AnnaBridge 163:e59c8e839560 177 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 163:e59c8e839560 178 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 163:e59c8e839560 179 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 163:e59c8e839560 180 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
AnnaBridge 163:e59c8e839560 181 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 163:e59c8e839560 182 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 163:e59c8e839560 183 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 163:e59c8e839560 184 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
AnnaBridge 163:e59c8e839560 185 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 163:e59c8e839560 186 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 163:e59c8e839560 187 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 163:e59c8e839560 188 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
AnnaBridge 163:e59c8e839560 189 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 163:e59c8e839560 190 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 163:e59c8e839560 191 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 163:e59c8e839560 192 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
AnnaBridge 163:e59c8e839560 193 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 163:e59c8e839560 194 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 163:e59c8e839560 195 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 163:e59c8e839560 196 /**
AnnaBridge 163:e59c8e839560 197 * @}
AnnaBridge 163:e59c8e839560 198 */
AnnaBridge 163:e59c8e839560 199
AnnaBridge 163:e59c8e839560 200 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 163:e59c8e839560 201 * @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge 163:e59c8e839560 202 * @{
AnnaBridge 163:e59c8e839560 203 */
AnnaBridge 163:e59c8e839560 204 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
AnnaBridge 163:e59c8e839560 205 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 163:e59c8e839560 206 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 163:e59c8e839560 207 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 163:e59c8e839560 208 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
AnnaBridge 163:e59c8e839560 209 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 163:e59c8e839560 210 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 163:e59c8e839560 211 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 163:e59c8e839560 212 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
AnnaBridge 163:e59c8e839560 213 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 163:e59c8e839560 214 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 163:e59c8e839560 215 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 163:e59c8e839560 216 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
AnnaBridge 163:e59c8e839560 217 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 163:e59c8e839560 218 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 163:e59c8e839560 219 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 163:e59c8e839560 220 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
AnnaBridge 163:e59c8e839560 221 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 163:e59c8e839560 222 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 163:e59c8e839560 223 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 163:e59c8e839560 224 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
AnnaBridge 163:e59c8e839560 225 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 163:e59c8e839560 226 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 163:e59c8e839560 227 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 163:e59c8e839560 228 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
AnnaBridge 163:e59c8e839560 229 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 163:e59c8e839560 230 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 163:e59c8e839560 231 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 163:e59c8e839560 232 /**
AnnaBridge 163:e59c8e839560 233 * @}
AnnaBridge 163:e59c8e839560 234 */
AnnaBridge 163:e59c8e839560 235
AnnaBridge 163:e59c8e839560 236 /** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge 163:e59c8e839560 237 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge 163:e59c8e839560 238 * @{
AnnaBridge 163:e59c8e839560 239 */
AnnaBridge 163:e59c8e839560 240 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
AnnaBridge 163:e59c8e839560 241 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
AnnaBridge 163:e59c8e839560 242 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
AnnaBridge 163:e59c8e839560 243 /**
AnnaBridge 163:e59c8e839560 244 * @}
AnnaBridge 163:e59c8e839560 245 */
AnnaBridge 163:e59c8e839560 246
AnnaBridge 163:e59c8e839560 247 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge 163:e59c8e839560 248 * @{
AnnaBridge 163:e59c8e839560 249 */
AnnaBridge 168:b9e159c1930a 250 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
AnnaBridge 168:b9e159c1930a 251 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
AnnaBridge 168:b9e159c1930a 252 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
AnnaBridge 168:b9e159c1930a 253 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
AnnaBridge 168:b9e159c1930a 254 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
AnnaBridge 168:b9e159c1930a 255 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
AnnaBridge 168:b9e159c1930a 256 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
AnnaBridge 163:e59c8e839560 257 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 168:b9e159c1930a 258 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
AnnaBridge 163:e59c8e839560 259 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 163:e59c8e839560 260 /**
AnnaBridge 163:e59c8e839560 261 * @}
AnnaBridge 163:e59c8e839560 262 */
AnnaBridge 163:e59c8e839560 263
AnnaBridge 163:e59c8e839560 264 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge 163:e59c8e839560 265 * @{
AnnaBridge 163:e59c8e839560 266 */
AnnaBridge 168:b9e159c1930a 267 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 163:e59c8e839560 268 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
AnnaBridge 163:e59c8e839560 269 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
AnnaBridge 163:e59c8e839560 270 /**
AnnaBridge 163:e59c8e839560 271 * @}
AnnaBridge 163:e59c8e839560 272 */
AnnaBridge 163:e59c8e839560 273
AnnaBridge 163:e59c8e839560 274 /** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge 163:e59c8e839560 275 * @{
AnnaBridge 163:e59c8e839560 276 */
AnnaBridge 168:b9e159c1930a 277 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
AnnaBridge 163:e59c8e839560 278 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
AnnaBridge 163:e59c8e839560 279 /**
AnnaBridge 163:e59c8e839560 280 * @}
AnnaBridge 163:e59c8e839560 281 */
AnnaBridge 163:e59c8e839560 282
AnnaBridge 163:e59c8e839560 283 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge 163:e59c8e839560 284 * @{
AnnaBridge 163:e59c8e839560 285 */
AnnaBridge 163:e59c8e839560 286 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
AnnaBridge 168:b9e159c1930a 287 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
AnnaBridge 163:e59c8e839560 288 /**
AnnaBridge 163:e59c8e839560 289 * @}
AnnaBridge 163:e59c8e839560 290 */
AnnaBridge 163:e59c8e839560 291
AnnaBridge 163:e59c8e839560 292 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge 163:e59c8e839560 293 * @{
AnnaBridge 163:e59c8e839560 294 */
AnnaBridge 163:e59c8e839560 295 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
AnnaBridge 168:b9e159c1930a 296 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
AnnaBridge 163:e59c8e839560 297 /**
AnnaBridge 163:e59c8e839560 298 * @}
AnnaBridge 163:e59c8e839560 299 */
AnnaBridge 163:e59c8e839560 300
AnnaBridge 163:e59c8e839560 301 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge 163:e59c8e839560 302 * @{
AnnaBridge 163:e59c8e839560 303 */
AnnaBridge 168:b9e159c1930a 304 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
AnnaBridge 163:e59c8e839560 305 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
AnnaBridge 163:e59c8e839560 306 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
AnnaBridge 163:e59c8e839560 307 /**
AnnaBridge 163:e59c8e839560 308 * @}
AnnaBridge 163:e59c8e839560 309 */
AnnaBridge 163:e59c8e839560 310
AnnaBridge 163:e59c8e839560 311 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge 163:e59c8e839560 312 * @{
AnnaBridge 163:e59c8e839560 313 */
AnnaBridge 168:b9e159c1930a 314 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
AnnaBridge 163:e59c8e839560 315 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
AnnaBridge 163:e59c8e839560 316 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
AnnaBridge 163:e59c8e839560 317 /**
AnnaBridge 163:e59c8e839560 318 * @}
AnnaBridge 163:e59c8e839560 319 */
AnnaBridge 163:e59c8e839560 320
AnnaBridge 163:e59c8e839560 321 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge 163:e59c8e839560 322 * @{
AnnaBridge 163:e59c8e839560 323 */
AnnaBridge 168:b9e159c1930a 324 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
AnnaBridge 163:e59c8e839560 325 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
AnnaBridge 163:e59c8e839560 326 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
AnnaBridge 163:e59c8e839560 327 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
AnnaBridge 163:e59c8e839560 328 /**
AnnaBridge 163:e59c8e839560 329 * @}
AnnaBridge 163:e59c8e839560 330 */
AnnaBridge 163:e59c8e839560 331
AnnaBridge 163:e59c8e839560 332
AnnaBridge 163:e59c8e839560 333 /**
AnnaBridge 163:e59c8e839560 334 * @}
AnnaBridge 163:e59c8e839560 335 */
AnnaBridge 163:e59c8e839560 336
AnnaBridge 163:e59c8e839560 337 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge 163:e59c8e839560 339 * @{
AnnaBridge 163:e59c8e839560 340 */
AnnaBridge 163:e59c8e839560 341
AnnaBridge 163:e59c8e839560 342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge 163:e59c8e839560 343 * @{
AnnaBridge 163:e59c8e839560 344 */
AnnaBridge 163:e59c8e839560 345 /**
AnnaBridge 163:e59c8e839560 346 * @brief Write a value in DMA register
AnnaBridge 163:e59c8e839560 347 * @param __INSTANCE__ DMA Instance
AnnaBridge 163:e59c8e839560 348 * @param __REG__ Register to be written
AnnaBridge 163:e59c8e839560 349 * @param __VALUE__ Value to be written in the register
AnnaBridge 163:e59c8e839560 350 * @retval None
AnnaBridge 163:e59c8e839560 351 */
AnnaBridge 163:e59c8e839560 352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 163:e59c8e839560 353
AnnaBridge 163:e59c8e839560 354 /**
AnnaBridge 163:e59c8e839560 355 * @brief Read a value in DMA register
AnnaBridge 163:e59c8e839560 356 * @param __INSTANCE__ DMA Instance
AnnaBridge 163:e59c8e839560 357 * @param __REG__ Register to be read
AnnaBridge 163:e59c8e839560 358 * @retval Register value
AnnaBridge 163:e59c8e839560 359 */
AnnaBridge 163:e59c8e839560 360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 163:e59c8e839560 361 /**
AnnaBridge 163:e59c8e839560 362 * @}
AnnaBridge 163:e59c8e839560 363 */
AnnaBridge 163:e59c8e839560 364
AnnaBridge 163:e59c8e839560 365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge 163:e59c8e839560 366 * @{
AnnaBridge 163:e59c8e839560 367 */
AnnaBridge 163:e59c8e839560 368 /**
AnnaBridge 163:e59c8e839560 369 * @brief Convert DMAx_Channely into DMAx
AnnaBridge 163:e59c8e839560 370 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 163:e59c8e839560 371 * @retval DMAx
AnnaBridge 163:e59c8e839560 372 */
AnnaBridge 163:e59c8e839560 373 #if defined(DMA2)
AnnaBridge 163:e59c8e839560 374 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge 163:e59c8e839560 375 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge 163:e59c8e839560 376 #else
AnnaBridge 163:e59c8e839560 377 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge 163:e59c8e839560 378 #endif
AnnaBridge 163:e59c8e839560 379
AnnaBridge 163:e59c8e839560 380 /**
AnnaBridge 163:e59c8e839560 381 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge 163:e59c8e839560 382 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 163:e59c8e839560 383 * @retval LL_DMA_CHANNEL_y
AnnaBridge 163:e59c8e839560 384 */
AnnaBridge 163:e59c8e839560 385 #if defined (DMA2)
AnnaBridge 163:e59c8e839560 386 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge 163:e59c8e839560 387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 163:e59c8e839560 388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 163:e59c8e839560 389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 163:e59c8e839560 390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 163:e59c8e839560 391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 163:e59c8e839560 392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 163:e59c8e839560 393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 163:e59c8e839560 394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 163:e59c8e839560 395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 163:e59c8e839560 396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 163:e59c8e839560 397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 163:e59c8e839560 398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 163:e59c8e839560 399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 163:e59c8e839560 400 LL_DMA_CHANNEL_7)
AnnaBridge 163:e59c8e839560 401 #else
AnnaBridge 163:e59c8e839560 402 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 163:e59c8e839560 403 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 163:e59c8e839560 404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 163:e59c8e839560 405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 163:e59c8e839560 406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 163:e59c8e839560 407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 163:e59c8e839560 408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 163:e59c8e839560 409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 163:e59c8e839560 410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 163:e59c8e839560 411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 163:e59c8e839560 412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 163:e59c8e839560 413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 163:e59c8e839560 414 LL_DMA_CHANNEL_7)
AnnaBridge 163:e59c8e839560 415 #endif
AnnaBridge 163:e59c8e839560 416 #else
AnnaBridge 163:e59c8e839560 417 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 163:e59c8e839560 418 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 163:e59c8e839560 419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 163:e59c8e839560 420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 163:e59c8e839560 421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 163:e59c8e839560 422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 163:e59c8e839560 423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 163:e59c8e839560 424 LL_DMA_CHANNEL_7)
AnnaBridge 163:e59c8e839560 425 #endif
AnnaBridge 163:e59c8e839560 426
AnnaBridge 163:e59c8e839560 427 /**
AnnaBridge 163:e59c8e839560 428 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge 163:e59c8e839560 429 * @param __DMA_INSTANCE__ DMAx
AnnaBridge 163:e59c8e839560 430 * @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge 163:e59c8e839560 431 * @retval DMAx_Channely
AnnaBridge 163:e59c8e839560 432 */
AnnaBridge 163:e59c8e839560 433 #if defined (DMA2)
AnnaBridge 163:e59c8e839560 434 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge 163:e59c8e839560 435 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 163:e59c8e839560 437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 163:e59c8e839560 438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 163:e59c8e839560 439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 163:e59c8e839560 440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 163:e59c8e839560 441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 163:e59c8e839560 442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 163:e59c8e839560 443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 163:e59c8e839560 444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 163:e59c8e839560 445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 163:e59c8e839560 446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 163:e59c8e839560 447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge 163:e59c8e839560 448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge 163:e59c8e839560 449 DMA2_Channel7)
AnnaBridge 163:e59c8e839560 450 #else
AnnaBridge 163:e59c8e839560 451 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 163:e59c8e839560 453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 163:e59c8e839560 454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 163:e59c8e839560 455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 163:e59c8e839560 456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 163:e59c8e839560 457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 163:e59c8e839560 458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 163:e59c8e839560 459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 163:e59c8e839560 460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 163:e59c8e839560 461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 163:e59c8e839560 462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 163:e59c8e839560 463 DMA1_Channel7)
AnnaBridge 163:e59c8e839560 464 #endif
AnnaBridge 163:e59c8e839560 465 #else
AnnaBridge 163:e59c8e839560 466 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 467 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 163:e59c8e839560 468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 163:e59c8e839560 469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 163:e59c8e839560 470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 163:e59c8e839560 471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 163:e59c8e839560 472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 163:e59c8e839560 473 DMA1_Channel7)
AnnaBridge 163:e59c8e839560 474 #endif
AnnaBridge 163:e59c8e839560 475
AnnaBridge 163:e59c8e839560 476 /**
AnnaBridge 163:e59c8e839560 477 * @}
AnnaBridge 163:e59c8e839560 478 */
AnnaBridge 163:e59c8e839560 479
AnnaBridge 163:e59c8e839560 480 /**
AnnaBridge 163:e59c8e839560 481 * @}
AnnaBridge 163:e59c8e839560 482 */
AnnaBridge 163:e59c8e839560 483
AnnaBridge 163:e59c8e839560 484 /* Exported functions --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 485 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge 163:e59c8e839560 486 * @{
AnnaBridge 163:e59c8e839560 487 */
AnnaBridge 163:e59c8e839560 488
AnnaBridge 163:e59c8e839560 489 /** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge 163:e59c8e839560 490 * @{
AnnaBridge 163:e59c8e839560 491 */
AnnaBridge 163:e59c8e839560 492 /**
AnnaBridge 163:e59c8e839560 493 * @brief Enable DMA channel.
AnnaBridge 163:e59c8e839560 494 * @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge 163:e59c8e839560 495 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 496 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 497 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 498 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 499 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 500 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 501 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 502 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 503 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 504 * @retval None
AnnaBridge 163:e59c8e839560 505 */
AnnaBridge 163:e59c8e839560 506 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 507 {
AnnaBridge 163:e59c8e839560 508 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 163:e59c8e839560 509 }
AnnaBridge 163:e59c8e839560 510
AnnaBridge 163:e59c8e839560 511 /**
AnnaBridge 163:e59c8e839560 512 * @brief Disable DMA channel.
AnnaBridge 163:e59c8e839560 513 * @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge 163:e59c8e839560 514 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 515 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 516 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 517 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 518 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 519 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 520 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 521 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 522 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 523 * @retval None
AnnaBridge 163:e59c8e839560 524 */
AnnaBridge 163:e59c8e839560 525 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 526 {
AnnaBridge 163:e59c8e839560 527 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 163:e59c8e839560 528 }
AnnaBridge 163:e59c8e839560 529
AnnaBridge 163:e59c8e839560 530 /**
AnnaBridge 163:e59c8e839560 531 * @brief Check if DMA channel is enabled or disabled.
AnnaBridge 163:e59c8e839560 532 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge 163:e59c8e839560 533 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 534 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 535 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 536 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 537 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 538 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 539 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 540 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 541 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 542 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 543 */
AnnaBridge 163:e59c8e839560 544 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 545 {
AnnaBridge 163:e59c8e839560 546 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 547 DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge 163:e59c8e839560 548 }
AnnaBridge 163:e59c8e839560 549
AnnaBridge 163:e59c8e839560 550 /**
AnnaBridge 163:e59c8e839560 551 * @brief Configure all parameters link to DMA transfer.
AnnaBridge 163:e59c8e839560 552 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 553 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 554 * CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 555 * CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 556 * CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 557 * CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 558 * CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 163:e59c8e839560 559 * CCR PL LL_DMA_ConfigTransfer
AnnaBridge 163:e59c8e839560 560 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 561 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 562 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 563 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 564 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 565 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 566 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 567 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 568 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 569 * @param Configuration This parameter must be a combination of all the following values:
AnnaBridge 163:e59c8e839560 570 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 163:e59c8e839560 571 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 163:e59c8e839560 572 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 163:e59c8e839560 573 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 163:e59c8e839560 574 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 575 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 576 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 163:e59c8e839560 577 * @retval None
AnnaBridge 163:e59c8e839560 578 */
AnnaBridge 163:e59c8e839560 579 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge 163:e59c8e839560 580 {
AnnaBridge 163:e59c8e839560 581 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 582 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
AnnaBridge 163:e59c8e839560 583 Configuration);
AnnaBridge 163:e59c8e839560 584 }
AnnaBridge 163:e59c8e839560 585
AnnaBridge 163:e59c8e839560 586 /**
AnnaBridge 163:e59c8e839560 587 * @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge 163:e59c8e839560 588 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge 163:e59c8e839560 589 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge 163:e59c8e839560 590 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 591 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 592 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 593 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 594 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 595 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 596 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 597 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 598 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 599 * @param Direction This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 600 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 163:e59c8e839560 601 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 163:e59c8e839560 602 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 163:e59c8e839560 603 * @retval None
AnnaBridge 163:e59c8e839560 604 */
AnnaBridge 163:e59c8e839560 605 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge 163:e59c8e839560 606 {
AnnaBridge 163:e59c8e839560 607 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 608 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
AnnaBridge 163:e59c8e839560 609 }
AnnaBridge 163:e59c8e839560 610
AnnaBridge 163:e59c8e839560 611 /**
AnnaBridge 163:e59c8e839560 612 * @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge 163:e59c8e839560 613 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge 163:e59c8e839560 614 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge 163:e59c8e839560 615 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 616 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 617 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 618 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 619 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 620 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 621 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 622 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 623 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 624 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 625 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 163:e59c8e839560 626 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 163:e59c8e839560 627 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 163:e59c8e839560 628 */
AnnaBridge 163:e59c8e839560 629 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 630 {
AnnaBridge 163:e59c8e839560 631 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 632 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
AnnaBridge 163:e59c8e839560 633 }
AnnaBridge 163:e59c8e839560 634
AnnaBridge 163:e59c8e839560 635 /**
AnnaBridge 163:e59c8e839560 636 * @brief Set DMA mode circular or normal.
AnnaBridge 163:e59c8e839560 637 * @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 163:e59c8e839560 638 * data transfer is configured on the selected Channel.
AnnaBridge 163:e59c8e839560 639 * @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge 163:e59c8e839560 640 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 641 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 642 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 643 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 644 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 645 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 646 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 647 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 648 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 649 * @param Mode This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 650 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 163:e59c8e839560 651 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 163:e59c8e839560 652 * @retval None
AnnaBridge 163:e59c8e839560 653 */
AnnaBridge 163:e59c8e839560 654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge 163:e59c8e839560 655 {
AnnaBridge 163:e59c8e839560 656 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge 163:e59c8e839560 657 Mode);
AnnaBridge 163:e59c8e839560 658 }
AnnaBridge 163:e59c8e839560 659
AnnaBridge 163:e59c8e839560 660 /**
AnnaBridge 163:e59c8e839560 661 * @brief Get DMA mode circular or normal.
AnnaBridge 163:e59c8e839560 662 * @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge 163:e59c8e839560 663 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 664 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 665 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 666 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 667 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 668 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 669 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 670 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 671 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 672 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 673 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 163:e59c8e839560 674 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 163:e59c8e839560 675 */
AnnaBridge 163:e59c8e839560 676 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 677 {
AnnaBridge 163:e59c8e839560 678 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 679 DMA_CCR_CIRC));
AnnaBridge 163:e59c8e839560 680 }
AnnaBridge 163:e59c8e839560 681
AnnaBridge 163:e59c8e839560 682 /**
AnnaBridge 163:e59c8e839560 683 * @brief Set Peripheral increment mode.
AnnaBridge 163:e59c8e839560 684 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge 163:e59c8e839560 685 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 686 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 687 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 688 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 689 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 690 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 691 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 692 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 693 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 694 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 695 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 163:e59c8e839560 696 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 163:e59c8e839560 697 * @retval None
AnnaBridge 163:e59c8e839560 698 */
AnnaBridge 163:e59c8e839560 699 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge 163:e59c8e839560 700 {
AnnaBridge 163:e59c8e839560 701 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge 163:e59c8e839560 702 PeriphOrM2MSrcIncMode);
AnnaBridge 163:e59c8e839560 703 }
AnnaBridge 163:e59c8e839560 704
AnnaBridge 163:e59c8e839560 705 /**
AnnaBridge 163:e59c8e839560 706 * @brief Get Peripheral increment mode.
AnnaBridge 163:e59c8e839560 707 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge 163:e59c8e839560 708 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 709 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 710 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 711 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 712 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 713 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 714 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 715 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 716 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 717 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 718 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 163:e59c8e839560 719 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 163:e59c8e839560 720 */
AnnaBridge 163:e59c8e839560 721 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 722 {
AnnaBridge 163:e59c8e839560 723 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 724 DMA_CCR_PINC));
AnnaBridge 163:e59c8e839560 725 }
AnnaBridge 163:e59c8e839560 726
AnnaBridge 163:e59c8e839560 727 /**
AnnaBridge 163:e59c8e839560 728 * @brief Set Memory increment mode.
AnnaBridge 163:e59c8e839560 729 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge 163:e59c8e839560 730 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 731 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 732 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 733 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 734 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 735 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 736 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 737 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 738 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 739 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 740 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 163:e59c8e839560 741 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 163:e59c8e839560 742 * @retval None
AnnaBridge 163:e59c8e839560 743 */
AnnaBridge 163:e59c8e839560 744 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge 163:e59c8e839560 745 {
AnnaBridge 163:e59c8e839560 746 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge 163:e59c8e839560 747 MemoryOrM2MDstIncMode);
AnnaBridge 163:e59c8e839560 748 }
AnnaBridge 163:e59c8e839560 749
AnnaBridge 163:e59c8e839560 750 /**
AnnaBridge 163:e59c8e839560 751 * @brief Get Memory increment mode.
AnnaBridge 163:e59c8e839560 752 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge 163:e59c8e839560 753 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 754 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 755 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 756 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 757 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 758 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 759 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 760 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 761 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 762 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 763 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 163:e59c8e839560 764 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 163:e59c8e839560 765 */
AnnaBridge 163:e59c8e839560 766 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 767 {
AnnaBridge 163:e59c8e839560 768 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 769 DMA_CCR_MINC));
AnnaBridge 163:e59c8e839560 770 }
AnnaBridge 163:e59c8e839560 771
AnnaBridge 163:e59c8e839560 772 /**
AnnaBridge 163:e59c8e839560 773 * @brief Set Peripheral size.
AnnaBridge 163:e59c8e839560 774 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge 163:e59c8e839560 775 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 776 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 777 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 778 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 779 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 780 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 781 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 782 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 783 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 784 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 785 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 163:e59c8e839560 786 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 163:e59c8e839560 787 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 788 * @retval None
AnnaBridge 163:e59c8e839560 789 */
AnnaBridge 163:e59c8e839560 790 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge 163:e59c8e839560 791 {
AnnaBridge 163:e59c8e839560 792 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge 163:e59c8e839560 793 PeriphOrM2MSrcDataSize);
AnnaBridge 163:e59c8e839560 794 }
AnnaBridge 163:e59c8e839560 795
AnnaBridge 163:e59c8e839560 796 /**
AnnaBridge 163:e59c8e839560 797 * @brief Get Peripheral size.
AnnaBridge 163:e59c8e839560 798 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge 163:e59c8e839560 799 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 800 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 801 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 802 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 803 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 804 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 805 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 806 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 807 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 808 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 809 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 163:e59c8e839560 810 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 163:e59c8e839560 811 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 812 */
AnnaBridge 163:e59c8e839560 813 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 814 {
AnnaBridge 163:e59c8e839560 815 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 816 DMA_CCR_PSIZE));
AnnaBridge 163:e59c8e839560 817 }
AnnaBridge 163:e59c8e839560 818
AnnaBridge 163:e59c8e839560 819 /**
AnnaBridge 163:e59c8e839560 820 * @brief Set Memory size.
AnnaBridge 163:e59c8e839560 821 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge 163:e59c8e839560 822 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 823 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 824 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 825 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 826 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 827 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 828 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 829 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 830 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 831 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 832 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 163:e59c8e839560 833 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 163:e59c8e839560 834 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 835 * @retval None
AnnaBridge 163:e59c8e839560 836 */
AnnaBridge 163:e59c8e839560 837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge 163:e59c8e839560 838 {
AnnaBridge 163:e59c8e839560 839 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge 163:e59c8e839560 840 MemoryOrM2MDstDataSize);
AnnaBridge 163:e59c8e839560 841 }
AnnaBridge 163:e59c8e839560 842
AnnaBridge 163:e59c8e839560 843 /**
AnnaBridge 163:e59c8e839560 844 * @brief Get Memory size.
AnnaBridge 163:e59c8e839560 845 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge 163:e59c8e839560 846 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 847 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 848 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 849 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 850 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 851 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 852 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 853 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 854 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 855 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 856 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 163:e59c8e839560 857 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 163:e59c8e839560 858 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 163:e59c8e839560 859 */
AnnaBridge 163:e59c8e839560 860 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 861 {
AnnaBridge 163:e59c8e839560 862 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 863 DMA_CCR_MSIZE));
AnnaBridge 163:e59c8e839560 864 }
AnnaBridge 163:e59c8e839560 865
AnnaBridge 163:e59c8e839560 866 /**
AnnaBridge 163:e59c8e839560 867 * @brief Set Channel priority level.
AnnaBridge 163:e59c8e839560 868 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge 163:e59c8e839560 869 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 870 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 871 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 872 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 873 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 874 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 875 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 876 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 877 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 878 * @param Priority This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 879 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 163:e59c8e839560 880 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 163:e59c8e839560 881 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 163:e59c8e839560 882 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 163:e59c8e839560 883 * @retval None
AnnaBridge 163:e59c8e839560 884 */
AnnaBridge 163:e59c8e839560 885 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge 163:e59c8e839560 886 {
AnnaBridge 163:e59c8e839560 887 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge 163:e59c8e839560 888 Priority);
AnnaBridge 163:e59c8e839560 889 }
AnnaBridge 163:e59c8e839560 890
AnnaBridge 163:e59c8e839560 891 /**
AnnaBridge 163:e59c8e839560 892 * @brief Get Channel priority level.
AnnaBridge 163:e59c8e839560 893 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge 163:e59c8e839560 894 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 895 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 896 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 897 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 898 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 899 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 900 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 901 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 902 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 903 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 904 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 163:e59c8e839560 905 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 163:e59c8e839560 906 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 163:e59c8e839560 907 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 163:e59c8e839560 908 */
AnnaBridge 163:e59c8e839560 909 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 910 {
AnnaBridge 163:e59c8e839560 911 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 912 DMA_CCR_PL));
AnnaBridge 163:e59c8e839560 913 }
AnnaBridge 163:e59c8e839560 914
AnnaBridge 163:e59c8e839560 915 /**
AnnaBridge 163:e59c8e839560 916 * @brief Set Number of data to transfer.
AnnaBridge 163:e59c8e839560 917 * @note This action has no effect if
AnnaBridge 163:e59c8e839560 918 * channel is enabled.
AnnaBridge 163:e59c8e839560 919 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge 163:e59c8e839560 920 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 921 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 922 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 923 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 924 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 925 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 926 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 927 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 928 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 929 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 163:e59c8e839560 930 * @retval None
AnnaBridge 163:e59c8e839560 931 */
AnnaBridge 163:e59c8e839560 932 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge 163:e59c8e839560 933 {
AnnaBridge 163:e59c8e839560 934 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 163:e59c8e839560 935 DMA_CNDTR_NDT, NbData);
AnnaBridge 163:e59c8e839560 936 }
AnnaBridge 163:e59c8e839560 937
AnnaBridge 163:e59c8e839560 938 /**
AnnaBridge 163:e59c8e839560 939 * @brief Get Number of data to transfer.
AnnaBridge 163:e59c8e839560 940 * @note Once the channel is enabled, the return value indicate the
AnnaBridge 163:e59c8e839560 941 * remaining bytes to be transmitted.
AnnaBridge 163:e59c8e839560 942 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge 163:e59c8e839560 943 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 944 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 945 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 946 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 947 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 948 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 949 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 950 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 951 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 952 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 953 */
AnnaBridge 163:e59c8e839560 954 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 955 {
AnnaBridge 163:e59c8e839560 956 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 163:e59c8e839560 957 DMA_CNDTR_NDT));
AnnaBridge 163:e59c8e839560 958 }
AnnaBridge 163:e59c8e839560 959
AnnaBridge 163:e59c8e839560 960 /**
AnnaBridge 163:e59c8e839560 961 * @brief Configure the Source and Destination addresses.
AnnaBridge 168:b9e159c1930a 962 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 168:b9e159c1930a 963 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge 163:e59c8e839560 964 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge 163:e59c8e839560 965 * CMAR MA LL_DMA_ConfigAddresses
AnnaBridge 163:e59c8e839560 966 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 967 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 968 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 969 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 970 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 971 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 972 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 973 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 974 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 975 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 976 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 977 * @param Direction This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 978 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 163:e59c8e839560 979 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 163:e59c8e839560 980 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 163:e59c8e839560 981 * @retval None
AnnaBridge 163:e59c8e839560 982 */
AnnaBridge 163:e59c8e839560 983 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge 163:e59c8e839560 984 uint32_t DstAddress, uint32_t Direction)
AnnaBridge 163:e59c8e839560 985 {
AnnaBridge 163:e59c8e839560 986 /* Direction Memory to Periph */
AnnaBridge 163:e59c8e839560 987 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge 163:e59c8e839560 988 {
AnnaBridge 168:b9e159c1930a 989 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge 168:b9e159c1930a 990 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge 163:e59c8e839560 991 }
AnnaBridge 163:e59c8e839560 992 /* Direction Periph to Memory and Memory to Memory */
AnnaBridge 163:e59c8e839560 993 else
AnnaBridge 163:e59c8e839560 994 {
AnnaBridge 168:b9e159c1930a 995 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge 168:b9e159c1930a 996 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge 163:e59c8e839560 997 }
AnnaBridge 163:e59c8e839560 998 }
AnnaBridge 163:e59c8e839560 999
AnnaBridge 163:e59c8e839560 1000 /**
AnnaBridge 163:e59c8e839560 1001 * @brief Set the Memory address.
AnnaBridge 163:e59c8e839560 1002 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 168:b9e159c1930a 1003 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 163:e59c8e839560 1004 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge 163:e59c8e839560 1005 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1006 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1007 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1008 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1009 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1010 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1011 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1012 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1013 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1014 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1015 * @retval None
AnnaBridge 163:e59c8e839560 1016 */
AnnaBridge 163:e59c8e839560 1017 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 163:e59c8e839560 1018 {
AnnaBridge 168:b9e159c1930a 1019 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 163:e59c8e839560 1020 }
AnnaBridge 163:e59c8e839560 1021
AnnaBridge 163:e59c8e839560 1022 /**
AnnaBridge 163:e59c8e839560 1023 * @brief Set the Peripheral address.
AnnaBridge 163:e59c8e839560 1024 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 168:b9e159c1930a 1025 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 163:e59c8e839560 1026 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge 163:e59c8e839560 1027 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1028 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1029 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1030 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1031 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1032 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1033 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1034 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1035 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1036 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1037 * @retval None
AnnaBridge 163:e59c8e839560 1038 */
AnnaBridge 163:e59c8e839560 1039 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge 163:e59c8e839560 1040 {
AnnaBridge 168:b9e159c1930a 1041 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge 163:e59c8e839560 1042 }
AnnaBridge 163:e59c8e839560 1043
AnnaBridge 163:e59c8e839560 1044 /**
AnnaBridge 163:e59c8e839560 1045 * @brief Get Memory address.
AnnaBridge 163:e59c8e839560 1046 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 163:e59c8e839560 1047 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge 163:e59c8e839560 1048 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1049 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1050 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1051 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1052 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1053 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1054 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1055 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1056 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1057 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1058 */
AnnaBridge 163:e59c8e839560 1059 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1060 {
AnnaBridge 168:b9e159c1930a 1061 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 163:e59c8e839560 1062 }
AnnaBridge 163:e59c8e839560 1063
AnnaBridge 163:e59c8e839560 1064 /**
AnnaBridge 163:e59c8e839560 1065 * @brief Get Peripheral address.
AnnaBridge 163:e59c8e839560 1066 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 163:e59c8e839560 1067 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge 163:e59c8e839560 1068 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1069 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1070 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1071 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1072 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1073 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1074 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1075 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1076 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1077 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1078 */
AnnaBridge 163:e59c8e839560 1079 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1080 {
AnnaBridge 168:b9e159c1930a 1081 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 163:e59c8e839560 1082 }
AnnaBridge 163:e59c8e839560 1083
AnnaBridge 163:e59c8e839560 1084 /**
AnnaBridge 163:e59c8e839560 1085 * @brief Set the Memory to Memory Source address.
AnnaBridge 163:e59c8e839560 1086 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 168:b9e159c1930a 1087 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 163:e59c8e839560 1088 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge 163:e59c8e839560 1089 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1090 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1091 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1092 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1093 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1094 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1095 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1096 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1097 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1098 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1099 * @retval None
AnnaBridge 163:e59c8e839560 1100 */
AnnaBridge 163:e59c8e839560 1101 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 163:e59c8e839560 1102 {
AnnaBridge 168:b9e159c1930a 1103 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge 163:e59c8e839560 1104 }
AnnaBridge 163:e59c8e839560 1105
AnnaBridge 163:e59c8e839560 1106 /**
AnnaBridge 163:e59c8e839560 1107 * @brief Set the Memory to Memory Destination address.
AnnaBridge 163:e59c8e839560 1108 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 168:b9e159c1930a 1109 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 163:e59c8e839560 1110 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge 163:e59c8e839560 1111 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1112 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1113 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1114 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1115 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1116 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1117 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1118 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1119 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1120 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1121 * @retval None
AnnaBridge 163:e59c8e839560 1122 */
AnnaBridge 163:e59c8e839560 1123 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 163:e59c8e839560 1124 {
AnnaBridge 168:b9e159c1930a 1125 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 163:e59c8e839560 1126 }
AnnaBridge 163:e59c8e839560 1127
AnnaBridge 163:e59c8e839560 1128 /**
AnnaBridge 163:e59c8e839560 1129 * @brief Get the Memory to Memory Source address.
AnnaBridge 163:e59c8e839560 1130 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 163:e59c8e839560 1131 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge 163:e59c8e839560 1132 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1133 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1134 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1135 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1136 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1137 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1138 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1139 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1140 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1141 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1142 */
AnnaBridge 163:e59c8e839560 1143 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1144 {
AnnaBridge 168:b9e159c1930a 1145 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 163:e59c8e839560 1146 }
AnnaBridge 163:e59c8e839560 1147
AnnaBridge 163:e59c8e839560 1148 /**
AnnaBridge 163:e59c8e839560 1149 * @brief Get the Memory to Memory Destination address.
AnnaBridge 163:e59c8e839560 1150 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 163:e59c8e839560 1151 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge 163:e59c8e839560 1152 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1153 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1154 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1155 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1156 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1157 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1158 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1159 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1160 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 163:e59c8e839560 1162 */
AnnaBridge 163:e59c8e839560 1163 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1164 {
AnnaBridge 168:b9e159c1930a 1165 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 163:e59c8e839560 1166 }
AnnaBridge 163:e59c8e839560 1167
AnnaBridge 163:e59c8e839560 1168
AnnaBridge 163:e59c8e839560 1169 /**
AnnaBridge 163:e59c8e839560 1170 * @}
AnnaBridge 163:e59c8e839560 1171 */
AnnaBridge 163:e59c8e839560 1172
AnnaBridge 163:e59c8e839560 1173 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 163:e59c8e839560 1174 * @{
AnnaBridge 163:e59c8e839560 1175 */
AnnaBridge 163:e59c8e839560 1176
AnnaBridge 163:e59c8e839560 1177 /**
AnnaBridge 163:e59c8e839560 1178 * @brief Get Channel 1 global interrupt flag.
AnnaBridge 163:e59c8e839560 1179 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge 163:e59c8e839560 1180 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1181 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1182 */
AnnaBridge 163:e59c8e839560 1183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1184 {
AnnaBridge 163:e59c8e839560 1185 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge 163:e59c8e839560 1186 }
AnnaBridge 163:e59c8e839560 1187
AnnaBridge 163:e59c8e839560 1188 /**
AnnaBridge 163:e59c8e839560 1189 * @brief Get Channel 2 global interrupt flag.
AnnaBridge 163:e59c8e839560 1190 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge 163:e59c8e839560 1191 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1192 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1193 */
AnnaBridge 163:e59c8e839560 1194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1195 {
AnnaBridge 163:e59c8e839560 1196 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge 163:e59c8e839560 1197 }
AnnaBridge 163:e59c8e839560 1198
AnnaBridge 163:e59c8e839560 1199 /**
AnnaBridge 163:e59c8e839560 1200 * @brief Get Channel 3 global interrupt flag.
AnnaBridge 163:e59c8e839560 1201 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge 163:e59c8e839560 1202 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1203 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1204 */
AnnaBridge 163:e59c8e839560 1205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1206 {
AnnaBridge 163:e59c8e839560 1207 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge 163:e59c8e839560 1208 }
AnnaBridge 163:e59c8e839560 1209
AnnaBridge 163:e59c8e839560 1210 /**
AnnaBridge 163:e59c8e839560 1211 * @brief Get Channel 4 global interrupt flag.
AnnaBridge 163:e59c8e839560 1212 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge 163:e59c8e839560 1213 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1214 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1215 */
AnnaBridge 163:e59c8e839560 1216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1217 {
AnnaBridge 163:e59c8e839560 1218 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge 163:e59c8e839560 1219 }
AnnaBridge 163:e59c8e839560 1220
AnnaBridge 163:e59c8e839560 1221 /**
AnnaBridge 163:e59c8e839560 1222 * @brief Get Channel 5 global interrupt flag.
AnnaBridge 163:e59c8e839560 1223 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge 163:e59c8e839560 1224 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1225 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1226 */
AnnaBridge 163:e59c8e839560 1227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1228 {
AnnaBridge 163:e59c8e839560 1229 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge 163:e59c8e839560 1230 }
AnnaBridge 163:e59c8e839560 1231
AnnaBridge 163:e59c8e839560 1232 /**
AnnaBridge 163:e59c8e839560 1233 * @brief Get Channel 6 global interrupt flag.
AnnaBridge 163:e59c8e839560 1234 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge 163:e59c8e839560 1235 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1236 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1237 */
AnnaBridge 163:e59c8e839560 1238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1239 {
AnnaBridge 163:e59c8e839560 1240 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge 163:e59c8e839560 1241 }
AnnaBridge 163:e59c8e839560 1242
AnnaBridge 163:e59c8e839560 1243 /**
AnnaBridge 163:e59c8e839560 1244 * @brief Get Channel 7 global interrupt flag.
AnnaBridge 163:e59c8e839560 1245 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge 163:e59c8e839560 1246 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1247 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1248 */
AnnaBridge 163:e59c8e839560 1249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1250 {
AnnaBridge 163:e59c8e839560 1251 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge 163:e59c8e839560 1252 }
AnnaBridge 163:e59c8e839560 1253
AnnaBridge 163:e59c8e839560 1254 /**
AnnaBridge 163:e59c8e839560 1255 * @brief Get Channel 1 transfer complete flag.
AnnaBridge 163:e59c8e839560 1256 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge 163:e59c8e839560 1257 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1258 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1259 */
AnnaBridge 163:e59c8e839560 1260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1261 {
AnnaBridge 163:e59c8e839560 1262 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge 163:e59c8e839560 1263 }
AnnaBridge 163:e59c8e839560 1264
AnnaBridge 163:e59c8e839560 1265 /**
AnnaBridge 163:e59c8e839560 1266 * @brief Get Channel 2 transfer complete flag.
AnnaBridge 163:e59c8e839560 1267 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge 163:e59c8e839560 1268 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1269 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1270 */
AnnaBridge 163:e59c8e839560 1271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1272 {
AnnaBridge 163:e59c8e839560 1273 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge 163:e59c8e839560 1274 }
AnnaBridge 163:e59c8e839560 1275
AnnaBridge 163:e59c8e839560 1276 /**
AnnaBridge 163:e59c8e839560 1277 * @brief Get Channel 3 transfer complete flag.
AnnaBridge 163:e59c8e839560 1278 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge 163:e59c8e839560 1279 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1280 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1281 */
AnnaBridge 163:e59c8e839560 1282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1283 {
AnnaBridge 163:e59c8e839560 1284 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge 163:e59c8e839560 1285 }
AnnaBridge 163:e59c8e839560 1286
AnnaBridge 163:e59c8e839560 1287 /**
AnnaBridge 163:e59c8e839560 1288 * @brief Get Channel 4 transfer complete flag.
AnnaBridge 163:e59c8e839560 1289 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge 163:e59c8e839560 1290 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1291 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1292 */
AnnaBridge 163:e59c8e839560 1293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1294 {
AnnaBridge 163:e59c8e839560 1295 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge 163:e59c8e839560 1296 }
AnnaBridge 163:e59c8e839560 1297
AnnaBridge 163:e59c8e839560 1298 /**
AnnaBridge 163:e59c8e839560 1299 * @brief Get Channel 5 transfer complete flag.
AnnaBridge 163:e59c8e839560 1300 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge 163:e59c8e839560 1301 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1302 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1303 */
AnnaBridge 163:e59c8e839560 1304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1305 {
AnnaBridge 163:e59c8e839560 1306 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge 163:e59c8e839560 1307 }
AnnaBridge 163:e59c8e839560 1308
AnnaBridge 163:e59c8e839560 1309 /**
AnnaBridge 163:e59c8e839560 1310 * @brief Get Channel 6 transfer complete flag.
AnnaBridge 163:e59c8e839560 1311 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge 163:e59c8e839560 1312 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1313 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1314 */
AnnaBridge 163:e59c8e839560 1315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1316 {
AnnaBridge 163:e59c8e839560 1317 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge 163:e59c8e839560 1318 }
AnnaBridge 163:e59c8e839560 1319
AnnaBridge 163:e59c8e839560 1320 /**
AnnaBridge 163:e59c8e839560 1321 * @brief Get Channel 7 transfer complete flag.
AnnaBridge 163:e59c8e839560 1322 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge 163:e59c8e839560 1323 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1324 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1325 */
AnnaBridge 163:e59c8e839560 1326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1327 {
AnnaBridge 163:e59c8e839560 1328 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge 163:e59c8e839560 1329 }
AnnaBridge 163:e59c8e839560 1330
AnnaBridge 163:e59c8e839560 1331 /**
AnnaBridge 163:e59c8e839560 1332 * @brief Get Channel 1 half transfer flag.
AnnaBridge 163:e59c8e839560 1333 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge 163:e59c8e839560 1334 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1335 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1336 */
AnnaBridge 163:e59c8e839560 1337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1338 {
AnnaBridge 163:e59c8e839560 1339 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge 163:e59c8e839560 1340 }
AnnaBridge 163:e59c8e839560 1341
AnnaBridge 163:e59c8e839560 1342 /**
AnnaBridge 163:e59c8e839560 1343 * @brief Get Channel 2 half transfer flag.
AnnaBridge 163:e59c8e839560 1344 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge 163:e59c8e839560 1345 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1346 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1347 */
AnnaBridge 163:e59c8e839560 1348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1349 {
AnnaBridge 163:e59c8e839560 1350 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge 163:e59c8e839560 1351 }
AnnaBridge 163:e59c8e839560 1352
AnnaBridge 163:e59c8e839560 1353 /**
AnnaBridge 163:e59c8e839560 1354 * @brief Get Channel 3 half transfer flag.
AnnaBridge 163:e59c8e839560 1355 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge 163:e59c8e839560 1356 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1357 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1358 */
AnnaBridge 163:e59c8e839560 1359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1360 {
AnnaBridge 163:e59c8e839560 1361 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge 163:e59c8e839560 1362 }
AnnaBridge 163:e59c8e839560 1363
AnnaBridge 163:e59c8e839560 1364 /**
AnnaBridge 163:e59c8e839560 1365 * @brief Get Channel 4 half transfer flag.
AnnaBridge 163:e59c8e839560 1366 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge 163:e59c8e839560 1367 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1368 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1369 */
AnnaBridge 163:e59c8e839560 1370 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1371 {
AnnaBridge 163:e59c8e839560 1372 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge 163:e59c8e839560 1373 }
AnnaBridge 163:e59c8e839560 1374
AnnaBridge 163:e59c8e839560 1375 /**
AnnaBridge 163:e59c8e839560 1376 * @brief Get Channel 5 half transfer flag.
AnnaBridge 163:e59c8e839560 1377 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge 163:e59c8e839560 1378 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1379 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1380 */
AnnaBridge 163:e59c8e839560 1381 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1382 {
AnnaBridge 163:e59c8e839560 1383 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge 163:e59c8e839560 1384 }
AnnaBridge 163:e59c8e839560 1385
AnnaBridge 163:e59c8e839560 1386 /**
AnnaBridge 163:e59c8e839560 1387 * @brief Get Channel 6 half transfer flag.
AnnaBridge 163:e59c8e839560 1388 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge 163:e59c8e839560 1389 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1390 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1391 */
AnnaBridge 163:e59c8e839560 1392 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1393 {
AnnaBridge 163:e59c8e839560 1394 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge 163:e59c8e839560 1395 }
AnnaBridge 163:e59c8e839560 1396
AnnaBridge 163:e59c8e839560 1397 /**
AnnaBridge 163:e59c8e839560 1398 * @brief Get Channel 7 half transfer flag.
AnnaBridge 163:e59c8e839560 1399 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge 163:e59c8e839560 1400 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1401 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1402 */
AnnaBridge 163:e59c8e839560 1403 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1404 {
AnnaBridge 163:e59c8e839560 1405 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge 163:e59c8e839560 1406 }
AnnaBridge 163:e59c8e839560 1407
AnnaBridge 163:e59c8e839560 1408 /**
AnnaBridge 163:e59c8e839560 1409 * @brief Get Channel 1 transfer error flag.
AnnaBridge 163:e59c8e839560 1410 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge 163:e59c8e839560 1411 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1412 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1413 */
AnnaBridge 163:e59c8e839560 1414 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1415 {
AnnaBridge 163:e59c8e839560 1416 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge 163:e59c8e839560 1417 }
AnnaBridge 163:e59c8e839560 1418
AnnaBridge 163:e59c8e839560 1419 /**
AnnaBridge 163:e59c8e839560 1420 * @brief Get Channel 2 transfer error flag.
AnnaBridge 163:e59c8e839560 1421 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge 163:e59c8e839560 1422 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1423 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1424 */
AnnaBridge 163:e59c8e839560 1425 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1426 {
AnnaBridge 163:e59c8e839560 1427 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge 163:e59c8e839560 1428 }
AnnaBridge 163:e59c8e839560 1429
AnnaBridge 163:e59c8e839560 1430 /**
AnnaBridge 163:e59c8e839560 1431 * @brief Get Channel 3 transfer error flag.
AnnaBridge 163:e59c8e839560 1432 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge 163:e59c8e839560 1433 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1434 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1435 */
AnnaBridge 163:e59c8e839560 1436 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1437 {
AnnaBridge 163:e59c8e839560 1438 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge 163:e59c8e839560 1439 }
AnnaBridge 163:e59c8e839560 1440
AnnaBridge 163:e59c8e839560 1441 /**
AnnaBridge 163:e59c8e839560 1442 * @brief Get Channel 4 transfer error flag.
AnnaBridge 163:e59c8e839560 1443 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge 163:e59c8e839560 1444 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1445 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1446 */
AnnaBridge 163:e59c8e839560 1447 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1448 {
AnnaBridge 163:e59c8e839560 1449 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge 163:e59c8e839560 1450 }
AnnaBridge 163:e59c8e839560 1451
AnnaBridge 163:e59c8e839560 1452 /**
AnnaBridge 163:e59c8e839560 1453 * @brief Get Channel 5 transfer error flag.
AnnaBridge 163:e59c8e839560 1454 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge 163:e59c8e839560 1455 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1456 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1457 */
AnnaBridge 163:e59c8e839560 1458 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1459 {
AnnaBridge 163:e59c8e839560 1460 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge 163:e59c8e839560 1461 }
AnnaBridge 163:e59c8e839560 1462
AnnaBridge 163:e59c8e839560 1463 /**
AnnaBridge 163:e59c8e839560 1464 * @brief Get Channel 6 transfer error flag.
AnnaBridge 163:e59c8e839560 1465 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge 163:e59c8e839560 1466 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1467 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1468 */
AnnaBridge 163:e59c8e839560 1469 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1470 {
AnnaBridge 163:e59c8e839560 1471 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge 163:e59c8e839560 1472 }
AnnaBridge 163:e59c8e839560 1473
AnnaBridge 163:e59c8e839560 1474 /**
AnnaBridge 163:e59c8e839560 1475 * @brief Get Channel 7 transfer error flag.
AnnaBridge 163:e59c8e839560 1476 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge 163:e59c8e839560 1477 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1478 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1479 */
AnnaBridge 163:e59c8e839560 1480 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1481 {
AnnaBridge 163:e59c8e839560 1482 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge 163:e59c8e839560 1483 }
AnnaBridge 163:e59c8e839560 1484
AnnaBridge 163:e59c8e839560 1485 /**
AnnaBridge 163:e59c8e839560 1486 * @brief Clear Channel 1 global interrupt flag.
AnnaBridge 163:e59c8e839560 1487 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge 163:e59c8e839560 1488 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1489 * @retval None
AnnaBridge 163:e59c8e839560 1490 */
AnnaBridge 163:e59c8e839560 1491 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1492 {
AnnaBridge 168:b9e159c1930a 1493 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge 163:e59c8e839560 1494 }
AnnaBridge 163:e59c8e839560 1495
AnnaBridge 163:e59c8e839560 1496 /**
AnnaBridge 163:e59c8e839560 1497 * @brief Clear Channel 2 global interrupt flag.
AnnaBridge 163:e59c8e839560 1498 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge 163:e59c8e839560 1499 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1500 * @retval None
AnnaBridge 163:e59c8e839560 1501 */
AnnaBridge 163:e59c8e839560 1502 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1503 {
AnnaBridge 168:b9e159c1930a 1504 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge 163:e59c8e839560 1505 }
AnnaBridge 163:e59c8e839560 1506
AnnaBridge 163:e59c8e839560 1507 /**
AnnaBridge 163:e59c8e839560 1508 * @brief Clear Channel 3 global interrupt flag.
AnnaBridge 163:e59c8e839560 1509 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge 163:e59c8e839560 1510 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1511 * @retval None
AnnaBridge 163:e59c8e839560 1512 */
AnnaBridge 163:e59c8e839560 1513 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1514 {
AnnaBridge 168:b9e159c1930a 1515 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge 163:e59c8e839560 1516 }
AnnaBridge 163:e59c8e839560 1517
AnnaBridge 163:e59c8e839560 1518 /**
AnnaBridge 163:e59c8e839560 1519 * @brief Clear Channel 4 global interrupt flag.
AnnaBridge 163:e59c8e839560 1520 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge 163:e59c8e839560 1521 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1522 * @retval None
AnnaBridge 163:e59c8e839560 1523 */
AnnaBridge 163:e59c8e839560 1524 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1525 {
AnnaBridge 168:b9e159c1930a 1526 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge 163:e59c8e839560 1527 }
AnnaBridge 163:e59c8e839560 1528
AnnaBridge 163:e59c8e839560 1529 /**
AnnaBridge 163:e59c8e839560 1530 * @brief Clear Channel 5 global interrupt flag.
AnnaBridge 163:e59c8e839560 1531 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge 163:e59c8e839560 1532 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1533 * @retval None
AnnaBridge 163:e59c8e839560 1534 */
AnnaBridge 163:e59c8e839560 1535 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1536 {
AnnaBridge 168:b9e159c1930a 1537 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge 163:e59c8e839560 1538 }
AnnaBridge 163:e59c8e839560 1539
AnnaBridge 163:e59c8e839560 1540 /**
AnnaBridge 163:e59c8e839560 1541 * @brief Clear Channel 6 global interrupt flag.
AnnaBridge 163:e59c8e839560 1542 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge 163:e59c8e839560 1543 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1544 * @retval None
AnnaBridge 163:e59c8e839560 1545 */
AnnaBridge 163:e59c8e839560 1546 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1547 {
AnnaBridge 168:b9e159c1930a 1548 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge 163:e59c8e839560 1549 }
AnnaBridge 163:e59c8e839560 1550
AnnaBridge 163:e59c8e839560 1551 /**
AnnaBridge 163:e59c8e839560 1552 * @brief Clear Channel 7 global interrupt flag.
AnnaBridge 163:e59c8e839560 1553 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge 163:e59c8e839560 1554 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1555 * @retval None
AnnaBridge 163:e59c8e839560 1556 */
AnnaBridge 163:e59c8e839560 1557 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1558 {
AnnaBridge 168:b9e159c1930a 1559 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge 163:e59c8e839560 1560 }
AnnaBridge 163:e59c8e839560 1561
AnnaBridge 163:e59c8e839560 1562 /**
AnnaBridge 163:e59c8e839560 1563 * @brief Clear Channel 1 transfer complete flag.
AnnaBridge 163:e59c8e839560 1564 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge 163:e59c8e839560 1565 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1566 * @retval None
AnnaBridge 163:e59c8e839560 1567 */
AnnaBridge 163:e59c8e839560 1568 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1569 {
AnnaBridge 168:b9e159c1930a 1570 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge 163:e59c8e839560 1571 }
AnnaBridge 163:e59c8e839560 1572
AnnaBridge 163:e59c8e839560 1573 /**
AnnaBridge 163:e59c8e839560 1574 * @brief Clear Channel 2 transfer complete flag.
AnnaBridge 163:e59c8e839560 1575 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge 163:e59c8e839560 1576 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1577 * @retval None
AnnaBridge 163:e59c8e839560 1578 */
AnnaBridge 163:e59c8e839560 1579 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1580 {
AnnaBridge 168:b9e159c1930a 1581 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge 163:e59c8e839560 1582 }
AnnaBridge 163:e59c8e839560 1583
AnnaBridge 163:e59c8e839560 1584 /**
AnnaBridge 163:e59c8e839560 1585 * @brief Clear Channel 3 transfer complete flag.
AnnaBridge 163:e59c8e839560 1586 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge 163:e59c8e839560 1587 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1588 * @retval None
AnnaBridge 163:e59c8e839560 1589 */
AnnaBridge 163:e59c8e839560 1590 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1591 {
AnnaBridge 168:b9e159c1930a 1592 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge 163:e59c8e839560 1593 }
AnnaBridge 163:e59c8e839560 1594
AnnaBridge 163:e59c8e839560 1595 /**
AnnaBridge 163:e59c8e839560 1596 * @brief Clear Channel 4 transfer complete flag.
AnnaBridge 163:e59c8e839560 1597 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge 163:e59c8e839560 1598 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1599 * @retval None
AnnaBridge 163:e59c8e839560 1600 */
AnnaBridge 163:e59c8e839560 1601 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1602 {
AnnaBridge 168:b9e159c1930a 1603 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge 163:e59c8e839560 1604 }
AnnaBridge 163:e59c8e839560 1605
AnnaBridge 163:e59c8e839560 1606 /**
AnnaBridge 163:e59c8e839560 1607 * @brief Clear Channel 5 transfer complete flag.
AnnaBridge 163:e59c8e839560 1608 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge 163:e59c8e839560 1609 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1610 * @retval None
AnnaBridge 163:e59c8e839560 1611 */
AnnaBridge 163:e59c8e839560 1612 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1613 {
AnnaBridge 168:b9e159c1930a 1614 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge 163:e59c8e839560 1615 }
AnnaBridge 163:e59c8e839560 1616
AnnaBridge 163:e59c8e839560 1617 /**
AnnaBridge 163:e59c8e839560 1618 * @brief Clear Channel 6 transfer complete flag.
AnnaBridge 163:e59c8e839560 1619 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge 163:e59c8e839560 1620 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1621 * @retval None
AnnaBridge 163:e59c8e839560 1622 */
AnnaBridge 163:e59c8e839560 1623 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1624 {
AnnaBridge 168:b9e159c1930a 1625 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge 163:e59c8e839560 1626 }
AnnaBridge 163:e59c8e839560 1627
AnnaBridge 163:e59c8e839560 1628 /**
AnnaBridge 163:e59c8e839560 1629 * @brief Clear Channel 7 transfer complete flag.
AnnaBridge 163:e59c8e839560 1630 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge 163:e59c8e839560 1631 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1632 * @retval None
AnnaBridge 163:e59c8e839560 1633 */
AnnaBridge 163:e59c8e839560 1634 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1635 {
AnnaBridge 168:b9e159c1930a 1636 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge 163:e59c8e839560 1637 }
AnnaBridge 163:e59c8e839560 1638
AnnaBridge 163:e59c8e839560 1639 /**
AnnaBridge 163:e59c8e839560 1640 * @brief Clear Channel 1 half transfer flag.
AnnaBridge 163:e59c8e839560 1641 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge 163:e59c8e839560 1642 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1643 * @retval None
AnnaBridge 163:e59c8e839560 1644 */
AnnaBridge 163:e59c8e839560 1645 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1646 {
AnnaBridge 168:b9e159c1930a 1647 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge 163:e59c8e839560 1648 }
AnnaBridge 163:e59c8e839560 1649
AnnaBridge 163:e59c8e839560 1650 /**
AnnaBridge 163:e59c8e839560 1651 * @brief Clear Channel 2 half transfer flag.
AnnaBridge 163:e59c8e839560 1652 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge 163:e59c8e839560 1653 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1654 * @retval None
AnnaBridge 163:e59c8e839560 1655 */
AnnaBridge 163:e59c8e839560 1656 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1657 {
AnnaBridge 168:b9e159c1930a 1658 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge 163:e59c8e839560 1659 }
AnnaBridge 163:e59c8e839560 1660
AnnaBridge 163:e59c8e839560 1661 /**
AnnaBridge 163:e59c8e839560 1662 * @brief Clear Channel 3 half transfer flag.
AnnaBridge 163:e59c8e839560 1663 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge 163:e59c8e839560 1664 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1665 * @retval None
AnnaBridge 163:e59c8e839560 1666 */
AnnaBridge 163:e59c8e839560 1667 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1668 {
AnnaBridge 168:b9e159c1930a 1669 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge 163:e59c8e839560 1670 }
AnnaBridge 163:e59c8e839560 1671
AnnaBridge 163:e59c8e839560 1672 /**
AnnaBridge 163:e59c8e839560 1673 * @brief Clear Channel 4 half transfer flag.
AnnaBridge 163:e59c8e839560 1674 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge 163:e59c8e839560 1675 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1676 * @retval None
AnnaBridge 163:e59c8e839560 1677 */
AnnaBridge 163:e59c8e839560 1678 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1679 {
AnnaBridge 168:b9e159c1930a 1680 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge 163:e59c8e839560 1681 }
AnnaBridge 163:e59c8e839560 1682
AnnaBridge 163:e59c8e839560 1683 /**
AnnaBridge 163:e59c8e839560 1684 * @brief Clear Channel 5 half transfer flag.
AnnaBridge 163:e59c8e839560 1685 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge 163:e59c8e839560 1686 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1687 * @retval None
AnnaBridge 163:e59c8e839560 1688 */
AnnaBridge 163:e59c8e839560 1689 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1690 {
AnnaBridge 168:b9e159c1930a 1691 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge 163:e59c8e839560 1692 }
AnnaBridge 163:e59c8e839560 1693
AnnaBridge 163:e59c8e839560 1694 /**
AnnaBridge 163:e59c8e839560 1695 * @brief Clear Channel 6 half transfer flag.
AnnaBridge 163:e59c8e839560 1696 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge 163:e59c8e839560 1697 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1698 * @retval None
AnnaBridge 163:e59c8e839560 1699 */
AnnaBridge 163:e59c8e839560 1700 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1701 {
AnnaBridge 168:b9e159c1930a 1702 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge 163:e59c8e839560 1703 }
AnnaBridge 163:e59c8e839560 1704
AnnaBridge 163:e59c8e839560 1705 /**
AnnaBridge 163:e59c8e839560 1706 * @brief Clear Channel 7 half transfer flag.
AnnaBridge 163:e59c8e839560 1707 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge 163:e59c8e839560 1708 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1709 * @retval None
AnnaBridge 163:e59c8e839560 1710 */
AnnaBridge 163:e59c8e839560 1711 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1712 {
AnnaBridge 168:b9e159c1930a 1713 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge 163:e59c8e839560 1714 }
AnnaBridge 163:e59c8e839560 1715
AnnaBridge 163:e59c8e839560 1716 /**
AnnaBridge 163:e59c8e839560 1717 * @brief Clear Channel 1 transfer error flag.
AnnaBridge 163:e59c8e839560 1718 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge 163:e59c8e839560 1719 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1720 * @retval None
AnnaBridge 163:e59c8e839560 1721 */
AnnaBridge 163:e59c8e839560 1722 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1723 {
AnnaBridge 168:b9e159c1930a 1724 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge 163:e59c8e839560 1725 }
AnnaBridge 163:e59c8e839560 1726
AnnaBridge 163:e59c8e839560 1727 /**
AnnaBridge 163:e59c8e839560 1728 * @brief Clear Channel 2 transfer error flag.
AnnaBridge 163:e59c8e839560 1729 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge 163:e59c8e839560 1730 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1731 * @retval None
AnnaBridge 163:e59c8e839560 1732 */
AnnaBridge 163:e59c8e839560 1733 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1734 {
AnnaBridge 168:b9e159c1930a 1735 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge 163:e59c8e839560 1736 }
AnnaBridge 163:e59c8e839560 1737
AnnaBridge 163:e59c8e839560 1738 /**
AnnaBridge 163:e59c8e839560 1739 * @brief Clear Channel 3 transfer error flag.
AnnaBridge 163:e59c8e839560 1740 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge 163:e59c8e839560 1741 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1742 * @retval None
AnnaBridge 163:e59c8e839560 1743 */
AnnaBridge 163:e59c8e839560 1744 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1745 {
AnnaBridge 168:b9e159c1930a 1746 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge 163:e59c8e839560 1747 }
AnnaBridge 163:e59c8e839560 1748
AnnaBridge 163:e59c8e839560 1749 /**
AnnaBridge 163:e59c8e839560 1750 * @brief Clear Channel 4 transfer error flag.
AnnaBridge 163:e59c8e839560 1751 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge 163:e59c8e839560 1752 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1753 * @retval None
AnnaBridge 163:e59c8e839560 1754 */
AnnaBridge 163:e59c8e839560 1755 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1756 {
AnnaBridge 168:b9e159c1930a 1757 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge 163:e59c8e839560 1758 }
AnnaBridge 163:e59c8e839560 1759
AnnaBridge 163:e59c8e839560 1760 /**
AnnaBridge 163:e59c8e839560 1761 * @brief Clear Channel 5 transfer error flag.
AnnaBridge 163:e59c8e839560 1762 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge 163:e59c8e839560 1763 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1764 * @retval None
AnnaBridge 163:e59c8e839560 1765 */
AnnaBridge 163:e59c8e839560 1766 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1767 {
AnnaBridge 168:b9e159c1930a 1768 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge 163:e59c8e839560 1769 }
AnnaBridge 163:e59c8e839560 1770
AnnaBridge 163:e59c8e839560 1771 /**
AnnaBridge 163:e59c8e839560 1772 * @brief Clear Channel 6 transfer error flag.
AnnaBridge 163:e59c8e839560 1773 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge 163:e59c8e839560 1774 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1775 * @retval None
AnnaBridge 163:e59c8e839560 1776 */
AnnaBridge 163:e59c8e839560 1777 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1778 {
AnnaBridge 168:b9e159c1930a 1779 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge 163:e59c8e839560 1780 }
AnnaBridge 163:e59c8e839560 1781
AnnaBridge 163:e59c8e839560 1782 /**
AnnaBridge 163:e59c8e839560 1783 * @brief Clear Channel 7 transfer error flag.
AnnaBridge 163:e59c8e839560 1784 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge 163:e59c8e839560 1785 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1786 * @retval None
AnnaBridge 163:e59c8e839560 1787 */
AnnaBridge 163:e59c8e839560 1788 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 163:e59c8e839560 1789 {
AnnaBridge 168:b9e159c1930a 1790 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge 163:e59c8e839560 1791 }
AnnaBridge 163:e59c8e839560 1792
AnnaBridge 163:e59c8e839560 1793 /**
AnnaBridge 163:e59c8e839560 1794 * @}
AnnaBridge 163:e59c8e839560 1795 */
AnnaBridge 163:e59c8e839560 1796
AnnaBridge 163:e59c8e839560 1797 /** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge 163:e59c8e839560 1798 * @{
AnnaBridge 163:e59c8e839560 1799 */
AnnaBridge 163:e59c8e839560 1800 /**
AnnaBridge 163:e59c8e839560 1801 * @brief Enable Transfer complete interrupt.
AnnaBridge 163:e59c8e839560 1802 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge 163:e59c8e839560 1803 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1804 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1805 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1806 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1807 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1808 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1809 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1810 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1811 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1812 * @retval None
AnnaBridge 163:e59c8e839560 1813 */
AnnaBridge 163:e59c8e839560 1814 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1815 {
AnnaBridge 163:e59c8e839560 1816 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 163:e59c8e839560 1817 }
AnnaBridge 163:e59c8e839560 1818
AnnaBridge 163:e59c8e839560 1819 /**
AnnaBridge 163:e59c8e839560 1820 * @brief Enable Half transfer interrupt.
AnnaBridge 163:e59c8e839560 1821 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge 163:e59c8e839560 1822 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1823 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1824 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1825 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1826 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1827 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1828 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1829 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1830 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1831 * @retval None
AnnaBridge 163:e59c8e839560 1832 */
AnnaBridge 163:e59c8e839560 1833 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1834 {
AnnaBridge 163:e59c8e839560 1835 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 163:e59c8e839560 1836 }
AnnaBridge 163:e59c8e839560 1837
AnnaBridge 163:e59c8e839560 1838 /**
AnnaBridge 163:e59c8e839560 1839 * @brief Enable Transfer error interrupt.
AnnaBridge 163:e59c8e839560 1840 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge 163:e59c8e839560 1841 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1842 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1843 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1844 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1845 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1846 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1847 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1848 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1849 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1850 * @retval None
AnnaBridge 163:e59c8e839560 1851 */
AnnaBridge 163:e59c8e839560 1852 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1853 {
AnnaBridge 163:e59c8e839560 1854 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 163:e59c8e839560 1855 }
AnnaBridge 163:e59c8e839560 1856
AnnaBridge 163:e59c8e839560 1857 /**
AnnaBridge 163:e59c8e839560 1858 * @brief Disable Transfer complete interrupt.
AnnaBridge 163:e59c8e839560 1859 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge 163:e59c8e839560 1860 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1861 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1862 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1863 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1864 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1865 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1866 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1867 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1868 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1869 * @retval None
AnnaBridge 163:e59c8e839560 1870 */
AnnaBridge 163:e59c8e839560 1871 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1872 {
AnnaBridge 163:e59c8e839560 1873 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 163:e59c8e839560 1874 }
AnnaBridge 163:e59c8e839560 1875
AnnaBridge 163:e59c8e839560 1876 /**
AnnaBridge 163:e59c8e839560 1877 * @brief Disable Half transfer interrupt.
AnnaBridge 163:e59c8e839560 1878 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge 163:e59c8e839560 1879 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1880 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1881 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1882 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1883 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1884 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1885 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1886 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1887 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1888 * @retval None
AnnaBridge 163:e59c8e839560 1889 */
AnnaBridge 163:e59c8e839560 1890 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1891 {
AnnaBridge 163:e59c8e839560 1892 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 163:e59c8e839560 1893 }
AnnaBridge 163:e59c8e839560 1894
AnnaBridge 163:e59c8e839560 1895 /**
AnnaBridge 163:e59c8e839560 1896 * @brief Disable Transfer error interrupt.
AnnaBridge 163:e59c8e839560 1897 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge 163:e59c8e839560 1898 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1899 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1900 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1901 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1902 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1903 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1904 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1905 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1906 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1907 * @retval None
AnnaBridge 163:e59c8e839560 1908 */
AnnaBridge 163:e59c8e839560 1909 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1910 {
AnnaBridge 163:e59c8e839560 1911 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 163:e59c8e839560 1912 }
AnnaBridge 163:e59c8e839560 1913
AnnaBridge 163:e59c8e839560 1914 /**
AnnaBridge 163:e59c8e839560 1915 * @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge 163:e59c8e839560 1916 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge 163:e59c8e839560 1917 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1918 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1919 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1920 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1921 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1922 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1923 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1924 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1925 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1926 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1927 */
AnnaBridge 163:e59c8e839560 1928 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1929 {
AnnaBridge 163:e59c8e839560 1930 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 1931 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge 163:e59c8e839560 1932 }
AnnaBridge 163:e59c8e839560 1933
AnnaBridge 163:e59c8e839560 1934 /**
AnnaBridge 163:e59c8e839560 1935 * @brief Check if Half transfer Interrupt is enabled.
AnnaBridge 163:e59c8e839560 1936 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge 163:e59c8e839560 1937 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1938 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1939 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1940 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1941 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1942 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1943 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1944 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1945 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1946 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1947 */
AnnaBridge 163:e59c8e839560 1948 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1949 {
AnnaBridge 163:e59c8e839560 1950 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 1951 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge 163:e59c8e839560 1952 }
AnnaBridge 163:e59c8e839560 1953
AnnaBridge 163:e59c8e839560 1954 /**
AnnaBridge 163:e59c8e839560 1955 * @brief Check if Transfer error Interrupt is enabled.
AnnaBridge 163:e59c8e839560 1956 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge 163:e59c8e839560 1957 * @param DMAx DMAx Instance
AnnaBridge 163:e59c8e839560 1958 * @param Channel This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1959 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 163:e59c8e839560 1960 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 163:e59c8e839560 1961 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 163:e59c8e839560 1962 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 163:e59c8e839560 1963 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 163:e59c8e839560 1964 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 163:e59c8e839560 1965 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 163:e59c8e839560 1966 * @retval State of bit (1 or 0).
AnnaBridge 163:e59c8e839560 1967 */
AnnaBridge 163:e59c8e839560 1968 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 163:e59c8e839560 1969 {
AnnaBridge 163:e59c8e839560 1970 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 163:e59c8e839560 1971 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge 163:e59c8e839560 1972 }
AnnaBridge 163:e59c8e839560 1973
AnnaBridge 163:e59c8e839560 1974 /**
AnnaBridge 163:e59c8e839560 1975 * @}
AnnaBridge 163:e59c8e839560 1976 */
AnnaBridge 163:e59c8e839560 1977
AnnaBridge 163:e59c8e839560 1978 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 163:e59c8e839560 1979 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 163:e59c8e839560 1980 * @{
AnnaBridge 163:e59c8e839560 1981 */
AnnaBridge 163:e59c8e839560 1982
AnnaBridge 163:e59c8e839560 1983 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 163:e59c8e839560 1984 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1985 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 163:e59c8e839560 1986
AnnaBridge 163:e59c8e839560 1987 /**
AnnaBridge 163:e59c8e839560 1988 * @}
AnnaBridge 163:e59c8e839560 1989 */
AnnaBridge 163:e59c8e839560 1990 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 163:e59c8e839560 1991
AnnaBridge 163:e59c8e839560 1992 /**
AnnaBridge 163:e59c8e839560 1993 * @}
AnnaBridge 163:e59c8e839560 1994 */
AnnaBridge 163:e59c8e839560 1995
AnnaBridge 163:e59c8e839560 1996 /**
AnnaBridge 163:e59c8e839560 1997 * @}
AnnaBridge 163:e59c8e839560 1998 */
AnnaBridge 163:e59c8e839560 1999
AnnaBridge 163:e59c8e839560 2000 #endif /* DMA1 || DMA2 */
AnnaBridge 163:e59c8e839560 2001
AnnaBridge 163:e59c8e839560 2002 /**
AnnaBridge 163:e59c8e839560 2003 * @}
AnnaBridge 163:e59c8e839560 2004 */
AnnaBridge 163:e59c8e839560 2005
AnnaBridge 163:e59c8e839560 2006 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 2007 }
AnnaBridge 163:e59c8e839560 2008 #endif
AnnaBridge 163:e59c8e839560 2009
AnnaBridge 163:e59c8e839560 2010 #endif /* __STM32F3xx_LL_DMA_H */
AnnaBridge 163:e59c8e839560 2011
AnnaBridge 163:e59c8e839560 2012 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/